7030 mmSQ_DEBUG_STS_GLOBAL 0 0x10a9 4 0 0 BUSY 0 0 INTERRUPT_MSG_BUSY 1 1 WAVE_LEVEL_SA0 4 15 WAVE_LEVEL_SA1 16 27 mmSQ_DEBUG_STS_GLOBAL2 0 0x10b0 3 0 0 FIFO_LEVEL_GFX0 0 7 FIFO_LEVEL_GFX1 8 15 FIFO_LEVEL_COMPUTE 16 23 mmSDMA0_DEC_START 0 0x0 1 0 0 START 0 31 mmSDMA0_GLOBAL_TIMESTAMP_LO 0 0xf 1 0 0 DATA 0 31 mmSDMA0_GLOBAL_TIMESTAMP_HI 0 0x10 1 0 0 DATA 0 31 mmSDMA0_PG_CNTL 0 0x16 2 0 0 CMD 0 3 STATUS 16 19 mmSDMA0_PG_CTX_LO 0 0x17 1 0 0 ADDR 0 31 mmSDMA0_PG_CTX_HI 0 0x18 1 0 0 ADDR 0 31 mmSDMA0_PG_CTX_CNTL 0 0x19 1 0 0 VMID 0 3 mmSDMA0_POWER_CNTL 0 0x1a 6 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 ON_OFF_STATUS_DURATION_TIME 26 31 mmSDMA0_CLK_CTRL 0 0x1b 10 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED_24_12 12 24 CGCG_EN_OVERRIDE 25 25 SOFT_OVERRIDE4 26 26 SOFT_OVERRIDE3 27 27 SOFT_OVERRIDE2 28 28 SOFT_OVERRIDE1 29 29 SOFT_OVERRIDE0 30 30 SOFT_OVERRIDER_REG 31 31 mmSDMA0_CNTL 0 0x1c 13 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 PAGE_INT_ENABLE 7 7 CH_PERFCNT_ENABLE 16 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA0_CHICKEN_BITS 0 0x1d 20 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 SOFT_OVERRIDE_DCGE 4 4 SOFT_OVERRIDE_SDMA_GRBM_FGCG 5 5 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 T2L_256B_ENABLE 18 18 GCR_FGCG_ENABLE 19 19 SRBM_POLL_RETRYING 20 20 CH_FGCG_ENABLE 21 21 UTCL2_INVREQ_FGCG_ENABLE 22 22 CG_STATUS_OUTPUT 23 23 UTCL1_FGCG_ENABLE 24 24 TIME_BASED_QOS 25 25 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA0_GB_ADDR_CONFIG 0 0x1e 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA0_GB_ADDR_CONFIG_READ 0 0x1f 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA0_RB_RPTR_FETCH_HI 0 0x20 1 0 0 OFFSET 0 31 mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0 0x21 1 0 0 TIMER 0 31 mmSDMA0_RB_RPTR_FETCH 0 0x22 1 0 0 OFFSET 2 31 mmSDMA0_IB_OFFSET_FETCH 0 0x23 1 0 0 OFFSET 2 21 mmSDMA0_PROGRAM 0 0x24 1 0 0 STREAM 0 31 mmSDMA0_STATUS_REG 0 0x25 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA0_STATUS1_REG 0 0x26 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA0_RD_BURST_CNTL 0 0x27 1 0 0 RD_BURST 0 1 mmSDMA0_HBM_PAGE_CONFIG 0 0x28 1 0 0 PAGE_SIZE_EXPONENT 0 1 mmSDMA0_UCODE_CHECKSUM 0 0x29 1 0 0 DATA 0 31 mmSDMA0_F32_CNTL 0 0x2a 4 0 0 HALT 0 0 STEP 1 1 CHECKSUM_CLR 8 8 RESET 9 9 mmSDMA0_FREEZE 0 0x2b 5 0 0 PREEMPT 0 0 FORCE_PREEMPT 1 1 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA0_PHASE0_QUANTUM 0 0x2c 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA0_PHASE1_QUANTUM 0 0x2d 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA0_EDC_CONFIG 0 0x32 2 0 0 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA0_BA_THRESHOLD 0 0x33 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA0_ID 0 0x34 1 0 0 DEVICE_ID 0 7 mmSDMA0_VERSION 0 0x35 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 mmSDMA0_EDC_COUNTER 0 0x36 17 0 0 SDMA_UCODE_BUF_DED 0 0 SDMA_UCODE_BUF_SEC 1 1 SDMA_RB_CMD_BUF_SED 2 2 SDMA_IB_CMD_BUF_SED 3 3 SDMA_UTCL1_RD_FIFO_SED 4 4 SDMA_UTCL1_RDBST_FIFO_SED 5 5 SDMA_DATA_LUT_FIFO_SED 6 6 SDMA_MBANK_DATA_BUF0_SED 7 7 SDMA_MBANK_DATA_BUF1_SED 8 8 SDMA_MBANK_DATA_BUF2_SED 9 9 SDMA_MBANK_DATA_BUF3_SED 10 10 SDMA_MBANK_DATA_BUF4_SED 11 11 SDMA_MBANK_DATA_BUF5_SED 12 12 SDMA_MBANK_DATA_BUF6_SED 13 13 SDMA_MBANK_DATA_BUF7_SED 14 14 SDMA_SPLIT_DAT_BUF_SED 15 15 SDMA_MC_WR_ADDR_FIFO_SED 16 16 mmSDMA0_EDC_COUNTER_CLEAR 0 0x37 1 0 0 DUMMY 0 0 mmSDMA0_STATUS2_REG 0 0x38 3 0 0 ID 0 1 F32_INSTR_PTR 2 15 CMD_OP 16 31 mmSDMA0_ATOMIC_CNTL 0 0x39 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA0_ATOMIC_PREOP_LO 0 0x3a 1 0 0 DATA 0 31 mmSDMA0_ATOMIC_PREOP_HI 0 0x3b 1 0 0 DATA 0 31 mmSDMA0_UTCL1_CNTL 0 0x3c 9 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 5 REDO_WATERMK 6 8 RESP_MODE 9 11 FORCE_INVALIDATION 14 14 FORCE_INVREQ_HEAVY 15 15 INVACK_DELAY 16 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 mmSDMA0_UTCL1_WATERMK 0 0x3d 4 0 0 REQMC_WATERMK 0 9 REQPG_WATERMK 10 17 INVREQ_WATERMK 18 25 XNACK_WATERMK 26 31 mmSDMA0_UTCL1_RD_STATUS 0 0x3e 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_RD_VECTOR 17 20 MERGE_STATE 21 23 ADDR_RD_RTR 24 24 RD_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 HIT_CACHE 27 27 RD_DCC_ENABLE 28 28 NACK_TIMEOUT_SW 29 29 DCC_PAGE_FAULT 30 30 DCC_PAGE_NULL 31 31 mmSDMA0_UTCL1_WR_STATUS 0 0x3f 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_WR_VECTOR 17 20 MERGE_STATE 21 23 F32_WR_RTR 24 24 WR_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 ATOMIC_OP 27 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 mmSDMA0_UTCL1_INV0 0 0x40 14 0 0 CPF_INVREQ_EN 0 0 GPUVM_INVREQ_EN 1 1 CPF_GPA_INVREQ 2 2 GPUVM_INVREQ_LOW 3 3 GPUVM_INVREQ_HIGH 4 4 INVREQ_SIZE 5 10 INVREQ_IDLE 11 11 VMINV_PEND_CNT 12 15 GPUVM_LO_INV_VMID 16 19 GPUVM_HI_INV_VMID 20 23 GPUVM_INV_MODE 24 25 INVREQ_IS_HEAVY 26 26 INVREQ_FROM_CPF 27 27 GPUVM_INVREQ_TAG 28 31 mmSDMA0_UTCL1_INV1 0 0x41 1 0 0 INV_ADDR_LO 0 31 mmSDMA0_UTCL1_INV2 0 0x42 2 0 0 INV_VMID_VEC 0 15 RESERVED 16 31 mmSDMA0_UTCL1_RD_XNACK0 0 0x43 1 0 0 XNACK_ADDR_LO 0 31 mmSDMA0_UTCL1_RD_XNACK1 0 0x44 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA0_UTCL1_WR_XNACK0 0 0x45 1 0 0 XNACK_ADDR_LO 0 31 mmSDMA0_UTCL1_WR_XNACK1 0 0x46 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA0_UTCL1_TIMEOUT 0 0x47 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 mmSDMA0_UTCL1_PAGE 0 0x48 11 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 9 USE_PT_SNOOP 10 10 USE_IO 11 11 RD_L2_POLICY 12 13 WR_L2_POLICY 14 15 DMA_PAGE_SIZE 16 21 USE_BC 22 22 ADDR_IS_PA 23 23 LLC_NOALLOC 24 24 mmSDMA0_RELAX_ORDERING_LUT 0 0x4a 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 mmSDMA0_CHICKEN_BITS_2 0 0x4b 12 0 0 F32_CMD_PROC_DELAY 0 3 CE_BACKWARDS_SIZE_SEL 4 4 CE_DCC_READ_128B_ENABLE 5 5 UTCL1_FORCE_INV_RET_FIFO_FULL_EN 6 6 RESERVED0 7 10 LUT_FIFO_AFULL_MARGIN 11 14 LEGACY_WPTR_POLL_BEHAVIOR 15 15 RB_FIFO_WATERMARK 16 17 IB_FIFO_WATERMARK 18 19 REPEATER_FGCG_EN 20 20 F32_SEND_POSTCODE_EN 21 21 RESERVED 22 31 mmSDMA0_STATUS3_REG 0 0x4c 9 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 AQL_PREV_CMD_IDLE 21 21 TLBI_IDLE 22 22 GCR_IDLE 23 23 INVREQ_IDLE 24 24 QUEUE_ID_MATCH 25 25 INT_QUEUE_ID 26 29 mmSDMA0_PHYSICAL_ADDR_LO 0 0x4d 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 mmSDMA0_PHYSICAL_ADDR_HI 0 0x4e 1 0 0 ADDR 0 15 mmSDMA0_PHASE2_QUANTUM 0 0x4f 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA0_ERROR_LOG 0 0x50 2 0 0 OVERRIDE 0 15 STATUS 16 31 mmSDMA0_PUB_DUMMY_REG0 0 0x51 1 0 0 VALUE 0 31 mmSDMA0_PUB_DUMMY_REG1 0 0x52 1 0 0 VALUE 0 31 mmSDMA0_PUB_DUMMY_REG2 0 0x53 1 0 0 VALUE 0 31 mmSDMA0_PUB_DUMMY_REG3 0 0x54 1 0 0 VALUE 0 31 mmSDMA0_F32_COUNTER 0 0x55 1 0 0 VALUE 0 31 mmSDMA0_CRD_CNTL 0 0x5b 4 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 CH_WRREQ_CREDIT 19 24 CH_RDREQ_CREDIT 25 30 mmSDMA0_AQL_STATUS 0 0x5f 2 0 0 COMPLETE_SIGNAL_EMPTY 0 0 INVALID_CMD_EMPTY 1 1 mmSDMA0_EA_DBIT_ADDR_DATA 0 0x60 1 0 0 VALUE 0 31 mmSDMA0_EA_DBIT_ADDR_INDEX 0 0x61 1 0 0 VALUE 0 2 mmSDMA0_TLBI_GCR_CNTL 0 0x62 5 0 0 TLBI_CMD_DW 0 3 GCR_CMD_DW 4 7 GCR_CLKEN_CYCLE 8 11 TLBI_CREDIT 16 23 GCR_CREDIT 24 31 mmSDMA0_TILING_CONFIG 0 0x63 1 0 0 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA0_INT_STATUS 0 0x70 1 0 0 DATA 0 31 mmSDMA0_HOLE_ADDR_LO 0 0x72 1 0 0 VALUE 0 31 mmSDMA0_HOLE_ADDR_HI 0 0x73 1 0 0 VALUE 0 31 mmSDMA0_CLOCK_GATING_REG 0 0x75 6 0 0 DYN_CLK_GATE_STATUS 0 0 PTR_CLK_GATE_STATUS 1 1 CE_CLK_GATE_STATUS 2 2 CE_BC_CLK_GATE_STATUS 3 3 CE_NBC_CLK_GATE_STATUS 4 4 REG_CLK_GATE_STATUS 5 5 mmSDMA0_STATUS4_REG 0 0x76 16 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 CH_RD_OUTSTANDING 4 4 CH_WR_OUTSTANDING 5 5 GCR_OUTSTANDING 6 6 TLBI_OUTSTANDING 7 7 UTCL2_RD_OUTSTANDING 8 8 UTCL2_WR_OUTSTANDING 9 9 REG_POLLING 10 10 MEM_POLLING 11 11 UTCL2_RD_XNACK 12 13 UTCL2_WR_XNACK 14 15 ACTIVE_QUEUE_ID 16 19 SRIOV_WATING_RLCV_CMD 20 20 SRIOV_SDMA_EXECUTING_CMD 21 21 mmSDMA0_SCRATCH_RAM_DATA 0 0x77 1 0 0 DATA 0 31 mmSDMA0_SCRATCH_RAM_ADDR 0 0x78 1 0 0 ADDR 0 9 mmSDMA0_TIMESTAMP_CNTL 0 0x79 1 0 0 CAPTURE 0 0 mmSDMA0_STATUS5_REG 0 0x7a 11 0 0 GFX_RB_ENABLE_STATUS 0 0 PAGE_RB_ENABLE_STATUS 1 1 RLC0_RB_ENABLE_STATUS 2 2 RLC1_RB_ENABLE_STATUS 3 3 RLC2_RB_ENABLE_STATUS 4 4 RLC3_RB_ENABLE_STATUS 5 5 RLC4_RB_ENABLE_STATUS 6 6 RLC5_RB_ENABLE_STATUS 7 7 RLC6_RB_ENABLE_STATUS 8 8 RLC7_RB_ENABLE_STATUS 9 9 ACTIVE_QUEUE_ID 16 19 mmSDMA0_QUEUE_RESET_REQ 0 0x7b 11 0 0 GFX_QUEUE_RESET 0 0 PAGE_QUEUE_RESET 1 1 RLC0_QUEUE_RESET 2 2 RLC1_QUEUE_RESET 3 3 RLC2_QUEUE_RESET 4 4 RLC3_QUEUE_RESET 5 5 RLC4_QUEUE_RESET 6 6 RLC5_QUEUE_RESET 7 7 RLC6_QUEUE_RESET 8 8 RLC7_QUEUE_RESET 9 9 RESERVED 10 31 mmSDMA0_GFX_RB_CNTL 0 0x80 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_GFX_RB_BASE 0 0x81 1 0 0 ADDR 0 31 mmSDMA0_GFX_RB_BASE_HI 0 0x82 1 0 0 ADDR 0 23 mmSDMA0_GFX_RB_RPTR 0 0x83 1 0 0 OFFSET 0 31 mmSDMA0_GFX_RB_RPTR_HI 0 0x84 1 0 0 OFFSET 0 31 mmSDMA0_GFX_RB_WPTR 0 0x85 1 0 0 OFFSET 0 31 mmSDMA0_GFX_RB_WPTR_HI 0 0x86 1 0 0 OFFSET 0 31 mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0 0x87 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_GFX_RB_RPTR_ADDR_HI 0 0x88 1 0 0 ADDR 0 31 mmSDMA0_GFX_RB_RPTR_ADDR_LO 0 0x89 1 0 0 ADDR 2 31 mmSDMA0_GFX_IB_CNTL 0 0x8a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_GFX_IB_RPTR 0 0x8b 1 0 0 OFFSET 2 21 mmSDMA0_GFX_IB_OFFSET 0 0x8c 1 0 0 OFFSET 2 21 mmSDMA0_GFX_IB_BASE_LO 0 0x8d 1 0 0 ADDR 5 31 mmSDMA0_GFX_IB_BASE_HI 0 0x8e 1 0 0 ADDR 0 31 mmSDMA0_GFX_IB_SIZE 0 0x8f 1 0 0 SIZE 0 19 mmSDMA0_GFX_SKIP_CNTL 0 0x90 1 0 0 SKIP_COUNT 0 19 mmSDMA0_GFX_CONTEXT_STATUS 0 0x91 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_GFX_DOORBELL 0 0x92 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_GFX_CONTEXT_CNTL 0 0x93 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA0_GFX_STATUS 0 0xa8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_GFX_DOORBELL_LOG 0 0xa9 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_GFX_WATERMARK 0 0xaa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_GFX_DOORBELL_OFFSET 0 0xab 1 0 0 OFFSET 2 27 mmSDMA0_GFX_CSA_ADDR_LO 0 0xac 1 0 0 ADDR 2 31 mmSDMA0_GFX_CSA_ADDR_HI 0 0xad 1 0 0 ADDR 0 31 mmSDMA0_GFX_IB_SUB_REMAIN 0 0xaf 1 0 0 SIZE 0 13 mmSDMA0_GFX_PREEMPT 0 0xb0 1 0 0 IB_PREEMPT 0 0 mmSDMA0_GFX_DUMMY_REG 0 0xb1 1 0 0 DUMMY 0 31 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0 0xb2 1 0 0 ADDR 0 31 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0 0xb3 1 0 0 ADDR 2 31 mmSDMA0_GFX_RB_AQL_CNTL 0 0xb4 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_GFX_MINOR_PTR_UPDATE 0 0xb5 1 0 0 ENABLE 0 0 mmSDMA0_GFX_MIDCMD_DATA0 0 0xc0 1 0 0 DATA0 0 31 mmSDMA0_GFX_MIDCMD_DATA1 0 0xc1 1 0 0 DATA1 0 31 mmSDMA0_GFX_MIDCMD_DATA2 0 0xc2 1 0 0 DATA2 0 31 mmSDMA0_GFX_MIDCMD_DATA3 0 0xc3 1 0 0 DATA3 0 31 mmSDMA0_GFX_MIDCMD_DATA4 0 0xc4 1 0 0 DATA4 0 31 mmSDMA0_GFX_MIDCMD_DATA5 0 0xc5 1 0 0 DATA5 0 31 mmSDMA0_GFX_MIDCMD_DATA6 0 0xc6 1 0 0 DATA6 0 31 mmSDMA0_GFX_MIDCMD_DATA7 0 0xc7 1 0 0 DATA7 0 31 mmSDMA0_GFX_MIDCMD_DATA8 0 0xc8 1 0 0 DATA8 0 31 mmSDMA0_GFX_MIDCMD_DATA9 0 0xc9 1 0 0 DATA9 0 31 mmSDMA0_GFX_MIDCMD_DATA10 0 0xca 1 0 0 DATA10 0 31 mmSDMA0_GFX_MIDCMD_CNTL 0 0xcb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_PAGE_RB_CNTL 0 0xd8 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_PAGE_RB_BASE 0 0xd9 1 0 0 ADDR 0 31 mmSDMA0_PAGE_RB_BASE_HI 0 0xda 1 0 0 ADDR 0 23 mmSDMA0_PAGE_RB_RPTR 0 0xdb 1 0 0 OFFSET 0 31 mmSDMA0_PAGE_RB_RPTR_HI 0 0xdc 1 0 0 OFFSET 0 31 mmSDMA0_PAGE_RB_WPTR 0 0xdd 1 0 0 OFFSET 0 31 mmSDMA0_PAGE_RB_WPTR_HI 0 0xde 1 0 0 OFFSET 0 31 mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0 0xdf 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0 0xe0 1 0 0 ADDR 0 31 mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0 0xe1 1 0 0 ADDR 2 31 mmSDMA0_PAGE_IB_CNTL 0 0xe2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_PAGE_IB_RPTR 0 0xe3 1 0 0 OFFSET 2 21 mmSDMA0_PAGE_IB_OFFSET 0 0xe4 1 0 0 OFFSET 2 21 mmSDMA0_PAGE_IB_BASE_LO 0 0xe5 1 0 0 ADDR 5 31 mmSDMA0_PAGE_IB_BASE_HI 0 0xe6 1 0 0 ADDR 0 31 mmSDMA0_PAGE_IB_SIZE 0 0xe7 1 0 0 SIZE 0 19 mmSDMA0_PAGE_SKIP_CNTL 0 0xe8 1 0 0 SKIP_COUNT 0 19 mmSDMA0_PAGE_CONTEXT_STATUS 0 0xe9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_PAGE_DOORBELL 0 0xea 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_PAGE_STATUS 0 0x100 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_PAGE_DOORBELL_LOG 0 0x101 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_PAGE_WATERMARK 0 0x102 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_PAGE_DOORBELL_OFFSET 0 0x103 1 0 0 OFFSET 2 27 mmSDMA0_PAGE_CSA_ADDR_LO 0 0x104 1 0 0 ADDR 2 31 mmSDMA0_PAGE_CSA_ADDR_HI 0 0x105 1 0 0 ADDR 0 31 mmSDMA0_PAGE_IB_SUB_REMAIN 0 0x107 1 0 0 SIZE 0 13 mmSDMA0_PAGE_PREEMPT 0 0x108 1 0 0 IB_PREEMPT 0 0 mmSDMA0_PAGE_DUMMY_REG 0 0x109 1 0 0 DUMMY 0 31 mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x10a 1 0 0 ADDR 0 31 mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x10b 1 0 0 ADDR 2 31 mmSDMA0_PAGE_RB_AQL_CNTL 0 0x10c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_PAGE_MINOR_PTR_UPDATE 0 0x10d 1 0 0 ENABLE 0 0 mmSDMA0_PAGE_MIDCMD_DATA0 0 0x118 1 0 0 DATA0 0 31 mmSDMA0_PAGE_MIDCMD_DATA1 0 0x119 1 0 0 DATA1 0 31 mmSDMA0_PAGE_MIDCMD_DATA2 0 0x11a 1 0 0 DATA2 0 31 mmSDMA0_PAGE_MIDCMD_DATA3 0 0x11b 1 0 0 DATA3 0 31 mmSDMA0_PAGE_MIDCMD_DATA4 0 0x11c 1 0 0 DATA4 0 31 mmSDMA0_PAGE_MIDCMD_DATA5 0 0x11d 1 0 0 DATA5 0 31 mmSDMA0_PAGE_MIDCMD_DATA6 0 0x11e 1 0 0 DATA6 0 31 mmSDMA0_PAGE_MIDCMD_DATA7 0 0x11f 1 0 0 DATA7 0 31 mmSDMA0_PAGE_MIDCMD_DATA8 0 0x120 1 0 0 DATA8 0 31 mmSDMA0_PAGE_MIDCMD_DATA9 0 0x121 1 0 0 DATA9 0 31 mmSDMA0_PAGE_MIDCMD_DATA10 0 0x122 1 0 0 DATA10 0 31 mmSDMA0_PAGE_MIDCMD_CNTL 0 0x123 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC0_RB_CNTL 0 0x130 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC0_RB_BASE 0 0x131 1 0 0 ADDR 0 31 mmSDMA0_RLC0_RB_BASE_HI 0 0x132 1 0 0 ADDR 0 23 mmSDMA0_RLC0_RB_RPTR 0 0x133 1 0 0 OFFSET 0 31 mmSDMA0_RLC0_RB_RPTR_HI 0 0x134 1 0 0 OFFSET 0 31 mmSDMA0_RLC0_RB_WPTR 0 0x135 1 0 0 OFFSET 0 31 mmSDMA0_RLC0_RB_WPTR_HI 0 0x136 1 0 0 OFFSET 0 31 mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0 0x137 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0 0x138 1 0 0 ADDR 0 31 mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0 0x139 1 0 0 ADDR 2 31 mmSDMA0_RLC0_IB_CNTL 0 0x13a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC0_IB_RPTR 0 0x13b 1 0 0 OFFSET 2 21 mmSDMA0_RLC0_IB_OFFSET 0 0x13c 1 0 0 OFFSET 2 21 mmSDMA0_RLC0_IB_BASE_LO 0 0x13d 1 0 0 ADDR 5 31 mmSDMA0_RLC0_IB_BASE_HI 0 0x13e 1 0 0 ADDR 0 31 mmSDMA0_RLC0_IB_SIZE 0 0x13f 1 0 0 SIZE 0 19 mmSDMA0_RLC0_SKIP_CNTL 0 0x140 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC0_CONTEXT_STATUS 0 0x141 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC0_DOORBELL 0 0x142 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC0_STATUS 0 0x158 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC0_DOORBELL_LOG 0 0x159 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC0_WATERMARK 0 0x15a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC0_DOORBELL_OFFSET 0 0x15b 1 0 0 OFFSET 2 27 mmSDMA0_RLC0_CSA_ADDR_LO 0 0x15c 1 0 0 ADDR 2 31 mmSDMA0_RLC0_CSA_ADDR_HI 0 0x15d 1 0 0 ADDR 0 31 mmSDMA0_RLC0_IB_SUB_REMAIN 0 0x15f 1 0 0 SIZE 0 13 mmSDMA0_RLC0_PREEMPT 0 0x160 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC0_DUMMY_REG 0 0x161 1 0 0 DUMMY 0 31 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x162 1 0 0 ADDR 0 31 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x163 1 0 0 ADDR 2 31 mmSDMA0_RLC0_RB_AQL_CNTL 0 0x164 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC0_MINOR_PTR_UPDATE 0 0x165 1 0 0 ENABLE 0 0 mmSDMA0_RLC0_MIDCMD_DATA0 0 0x170 1 0 0 DATA0 0 31 mmSDMA0_RLC0_MIDCMD_DATA1 0 0x171 1 0 0 DATA1 0 31 mmSDMA0_RLC0_MIDCMD_DATA2 0 0x172 1 0 0 DATA2 0 31 mmSDMA0_RLC0_MIDCMD_DATA3 0 0x173 1 0 0 DATA3 0 31 mmSDMA0_RLC0_MIDCMD_DATA4 0 0x174 1 0 0 DATA4 0 31 mmSDMA0_RLC0_MIDCMD_DATA5 0 0x175 1 0 0 DATA5 0 31 mmSDMA0_RLC0_MIDCMD_DATA6 0 0x176 1 0 0 DATA6 0 31 mmSDMA0_RLC0_MIDCMD_DATA7 0 0x177 1 0 0 DATA7 0 31 mmSDMA0_RLC0_MIDCMD_DATA8 0 0x178 1 0 0 DATA8 0 31 mmSDMA0_RLC0_MIDCMD_DATA9 0 0x179 1 0 0 DATA9 0 31 mmSDMA0_RLC0_MIDCMD_DATA10 0 0x17a 1 0 0 DATA10 0 31 mmSDMA0_RLC0_MIDCMD_CNTL 0 0x17b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC1_RB_CNTL 0 0x188 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC1_RB_BASE 0 0x189 1 0 0 ADDR 0 31 mmSDMA0_RLC1_RB_BASE_HI 0 0x18a 1 0 0 ADDR 0 23 mmSDMA0_RLC1_RB_RPTR 0 0x18b 1 0 0 OFFSET 0 31 mmSDMA0_RLC1_RB_RPTR_HI 0 0x18c 1 0 0 OFFSET 0 31 mmSDMA0_RLC1_RB_WPTR 0 0x18d 1 0 0 OFFSET 0 31 mmSDMA0_RLC1_RB_WPTR_HI 0 0x18e 1 0 0 OFFSET 0 31 mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0 0x18f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0 0x190 1 0 0 ADDR 0 31 mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0 0x191 1 0 0 ADDR 2 31 mmSDMA0_RLC1_IB_CNTL 0 0x192 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC1_IB_RPTR 0 0x193 1 0 0 OFFSET 2 21 mmSDMA0_RLC1_IB_OFFSET 0 0x194 1 0 0 OFFSET 2 21 mmSDMA0_RLC1_IB_BASE_LO 0 0x195 1 0 0 ADDR 5 31 mmSDMA0_RLC1_IB_BASE_HI 0 0x196 1 0 0 ADDR 0 31 mmSDMA0_RLC1_IB_SIZE 0 0x197 1 0 0 SIZE 0 19 mmSDMA0_RLC1_SKIP_CNTL 0 0x198 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC1_CONTEXT_STATUS 0 0x199 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC1_DOORBELL 0 0x19a 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC1_STATUS 0 0x1b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC1_DOORBELL_LOG 0 0x1b1 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC1_WATERMARK 0 0x1b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC1_DOORBELL_OFFSET 0 0x1b3 1 0 0 OFFSET 2 27 mmSDMA0_RLC1_CSA_ADDR_LO 0 0x1b4 1 0 0 ADDR 2 31 mmSDMA0_RLC1_CSA_ADDR_HI 0 0x1b5 1 0 0 ADDR 0 31 mmSDMA0_RLC1_IB_SUB_REMAIN 0 0x1b7 1 0 0 SIZE 0 13 mmSDMA0_RLC1_PREEMPT 0 0x1b8 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC1_DUMMY_REG 0 0x1b9 1 0 0 DUMMY 0 31 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1ba 1 0 0 ADDR 0 31 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1bb 1 0 0 ADDR 2 31 mmSDMA0_RLC1_RB_AQL_CNTL 0 0x1bc 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC1_MINOR_PTR_UPDATE 0 0x1bd 1 0 0 ENABLE 0 0 mmSDMA0_RLC1_MIDCMD_DATA0 0 0x1c8 1 0 0 DATA0 0 31 mmSDMA0_RLC1_MIDCMD_DATA1 0 0x1c9 1 0 0 DATA1 0 31 mmSDMA0_RLC1_MIDCMD_DATA2 0 0x1ca 1 0 0 DATA2 0 31 mmSDMA0_RLC1_MIDCMD_DATA3 0 0x1cb 1 0 0 DATA3 0 31 mmSDMA0_RLC1_MIDCMD_DATA4 0 0x1cc 1 0 0 DATA4 0 31 mmSDMA0_RLC1_MIDCMD_DATA5 0 0x1cd 1 0 0 DATA5 0 31 mmSDMA0_RLC1_MIDCMD_DATA6 0 0x1ce 1 0 0 DATA6 0 31 mmSDMA0_RLC1_MIDCMD_DATA7 0 0x1cf 1 0 0 DATA7 0 31 mmSDMA0_RLC1_MIDCMD_DATA8 0 0x1d0 1 0 0 DATA8 0 31 mmSDMA0_RLC1_MIDCMD_DATA9 0 0x1d1 1 0 0 DATA9 0 31 mmSDMA0_RLC1_MIDCMD_DATA10 0 0x1d2 1 0 0 DATA10 0 31 mmSDMA0_RLC1_MIDCMD_CNTL 0 0x1d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC2_RB_CNTL 0 0x1e0 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC2_RB_BASE 0 0x1e1 1 0 0 ADDR 0 31 mmSDMA0_RLC2_RB_BASE_HI 0 0x1e2 1 0 0 ADDR 0 23 mmSDMA0_RLC2_RB_RPTR 0 0x1e3 1 0 0 OFFSET 0 31 mmSDMA0_RLC2_RB_RPTR_HI 0 0x1e4 1 0 0 OFFSET 0 31 mmSDMA0_RLC2_RB_WPTR 0 0x1e5 1 0 0 OFFSET 0 31 mmSDMA0_RLC2_RB_WPTR_HI 0 0x1e6 1 0 0 OFFSET 0 31 mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0 0x1e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0 0x1e8 1 0 0 ADDR 0 31 mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0 0x1e9 1 0 0 ADDR 2 31 mmSDMA0_RLC2_IB_CNTL 0 0x1ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC2_IB_RPTR 0 0x1eb 1 0 0 OFFSET 2 21 mmSDMA0_RLC2_IB_OFFSET 0 0x1ec 1 0 0 OFFSET 2 21 mmSDMA0_RLC2_IB_BASE_LO 0 0x1ed 1 0 0 ADDR 5 31 mmSDMA0_RLC2_IB_BASE_HI 0 0x1ee 1 0 0 ADDR 0 31 mmSDMA0_RLC2_IB_SIZE 0 0x1ef 1 0 0 SIZE 0 19 mmSDMA0_RLC2_SKIP_CNTL 0 0x1f0 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC2_CONTEXT_STATUS 0 0x1f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC2_DOORBELL 0 0x1f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC2_STATUS 0 0x208 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC2_DOORBELL_LOG 0 0x209 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC2_WATERMARK 0 0x20a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC2_DOORBELL_OFFSET 0 0x20b 1 0 0 OFFSET 2 27 mmSDMA0_RLC2_CSA_ADDR_LO 0 0x20c 1 0 0 ADDR 2 31 mmSDMA0_RLC2_CSA_ADDR_HI 0 0x20d 1 0 0 ADDR 0 31 mmSDMA0_RLC2_IB_SUB_REMAIN 0 0x20f 1 0 0 SIZE 0 13 mmSDMA0_RLC2_PREEMPT 0 0x210 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC2_DUMMY_REG 0 0x211 1 0 0 DUMMY 0 31 mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x212 1 0 0 ADDR 0 31 mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x213 1 0 0 ADDR 2 31 mmSDMA0_RLC2_RB_AQL_CNTL 0 0x214 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC2_MINOR_PTR_UPDATE 0 0x215 1 0 0 ENABLE 0 0 mmSDMA0_RLC2_MIDCMD_DATA0 0 0x220 1 0 0 DATA0 0 31 mmSDMA0_RLC2_MIDCMD_DATA1 0 0x221 1 0 0 DATA1 0 31 mmSDMA0_RLC2_MIDCMD_DATA2 0 0x222 1 0 0 DATA2 0 31 mmSDMA0_RLC2_MIDCMD_DATA3 0 0x223 1 0 0 DATA3 0 31 mmSDMA0_RLC2_MIDCMD_DATA4 0 0x224 1 0 0 DATA4 0 31 mmSDMA0_RLC2_MIDCMD_DATA5 0 0x225 1 0 0 DATA5 0 31 mmSDMA0_RLC2_MIDCMD_DATA6 0 0x226 1 0 0 DATA6 0 31 mmSDMA0_RLC2_MIDCMD_DATA7 0 0x227 1 0 0 DATA7 0 31 mmSDMA0_RLC2_MIDCMD_DATA8 0 0x228 1 0 0 DATA8 0 31 mmSDMA0_RLC2_MIDCMD_DATA9 0 0x229 1 0 0 DATA9 0 31 mmSDMA0_RLC2_MIDCMD_DATA10 0 0x22a 1 0 0 DATA10 0 31 mmSDMA0_RLC2_MIDCMD_CNTL 0 0x22b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC3_RB_CNTL 0 0x238 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC3_RB_BASE 0 0x239 1 0 0 ADDR 0 31 mmSDMA0_RLC3_RB_BASE_HI 0 0x23a 1 0 0 ADDR 0 23 mmSDMA0_RLC3_RB_RPTR 0 0x23b 1 0 0 OFFSET 0 31 mmSDMA0_RLC3_RB_RPTR_HI 0 0x23c 1 0 0 OFFSET 0 31 mmSDMA0_RLC3_RB_WPTR 0 0x23d 1 0 0 OFFSET 0 31 mmSDMA0_RLC3_RB_WPTR_HI 0 0x23e 1 0 0 OFFSET 0 31 mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0 0x23f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0 0x240 1 0 0 ADDR 0 31 mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0 0x241 1 0 0 ADDR 2 31 mmSDMA0_RLC3_IB_CNTL 0 0x242 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC3_IB_RPTR 0 0x243 1 0 0 OFFSET 2 21 mmSDMA0_RLC3_IB_OFFSET 0 0x244 1 0 0 OFFSET 2 21 mmSDMA0_RLC3_IB_BASE_LO 0 0x245 1 0 0 ADDR 5 31 mmSDMA0_RLC3_IB_BASE_HI 0 0x246 1 0 0 ADDR 0 31 mmSDMA0_RLC3_IB_SIZE 0 0x247 1 0 0 SIZE 0 19 mmSDMA0_RLC3_SKIP_CNTL 0 0x248 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC3_CONTEXT_STATUS 0 0x249 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC3_DOORBELL 0 0x24a 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC3_STATUS 0 0x260 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC3_DOORBELL_LOG 0 0x261 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC3_WATERMARK 0 0x262 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC3_DOORBELL_OFFSET 0 0x263 1 0 0 OFFSET 2 27 mmSDMA0_RLC3_CSA_ADDR_LO 0 0x264 1 0 0 ADDR 2 31 mmSDMA0_RLC3_CSA_ADDR_HI 0 0x265 1 0 0 ADDR 0 31 mmSDMA0_RLC3_IB_SUB_REMAIN 0 0x267 1 0 0 SIZE 0 13 mmSDMA0_RLC3_PREEMPT 0 0x268 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC3_DUMMY_REG 0 0x269 1 0 0 DUMMY 0 31 mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x26a 1 0 0 ADDR 0 31 mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x26b 1 0 0 ADDR 2 31 mmSDMA0_RLC3_RB_AQL_CNTL 0 0x26c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC3_MINOR_PTR_UPDATE 0 0x26d 1 0 0 ENABLE 0 0 mmSDMA0_RLC3_MIDCMD_DATA0 0 0x278 1 0 0 DATA0 0 31 mmSDMA0_RLC3_MIDCMD_DATA1 0 0x279 1 0 0 DATA1 0 31 mmSDMA0_RLC3_MIDCMD_DATA2 0 0x27a 1 0 0 DATA2 0 31 mmSDMA0_RLC3_MIDCMD_DATA3 0 0x27b 1 0 0 DATA3 0 31 mmSDMA0_RLC3_MIDCMD_DATA4 0 0x27c 1 0 0 DATA4 0 31 mmSDMA0_RLC3_MIDCMD_DATA5 0 0x27d 1 0 0 DATA5 0 31 mmSDMA0_RLC3_MIDCMD_DATA6 0 0x27e 1 0 0 DATA6 0 31 mmSDMA0_RLC3_MIDCMD_DATA7 0 0x27f 1 0 0 DATA7 0 31 mmSDMA0_RLC3_MIDCMD_DATA8 0 0x280 1 0 0 DATA8 0 31 mmSDMA0_RLC3_MIDCMD_DATA9 0 0x281 1 0 0 DATA9 0 31 mmSDMA0_RLC3_MIDCMD_DATA10 0 0x282 1 0 0 DATA10 0 31 mmSDMA0_RLC3_MIDCMD_CNTL 0 0x283 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC4_RB_CNTL 0 0x290 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC4_RB_BASE 0 0x291 1 0 0 ADDR 0 31 mmSDMA0_RLC4_RB_BASE_HI 0 0x292 1 0 0 ADDR 0 23 mmSDMA0_RLC4_RB_RPTR 0 0x293 1 0 0 OFFSET 0 31 mmSDMA0_RLC4_RB_RPTR_HI 0 0x294 1 0 0 OFFSET 0 31 mmSDMA0_RLC4_RB_WPTR 0 0x295 1 0 0 OFFSET 0 31 mmSDMA0_RLC4_RB_WPTR_HI 0 0x296 1 0 0 OFFSET 0 31 mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0 0x297 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0 0x298 1 0 0 ADDR 0 31 mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0 0x299 1 0 0 ADDR 2 31 mmSDMA0_RLC4_IB_CNTL 0 0x29a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC4_IB_RPTR 0 0x29b 1 0 0 OFFSET 2 21 mmSDMA0_RLC4_IB_OFFSET 0 0x29c 1 0 0 OFFSET 2 21 mmSDMA0_RLC4_IB_BASE_LO 0 0x29d 1 0 0 ADDR 5 31 mmSDMA0_RLC4_IB_BASE_HI 0 0x29e 1 0 0 ADDR 0 31 mmSDMA0_RLC4_IB_SIZE 0 0x29f 1 0 0 SIZE 0 19 mmSDMA0_RLC4_SKIP_CNTL 0 0x2a0 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC4_CONTEXT_STATUS 0 0x2a1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC4_DOORBELL 0 0x2a2 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC4_STATUS 0 0x2b8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC4_DOORBELL_LOG 0 0x2b9 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC4_WATERMARK 0 0x2ba 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC4_DOORBELL_OFFSET 0 0x2bb 1 0 0 OFFSET 2 27 mmSDMA0_RLC4_CSA_ADDR_LO 0 0x2bc 1 0 0 ADDR 2 31 mmSDMA0_RLC4_CSA_ADDR_HI 0 0x2bd 1 0 0 ADDR 0 31 mmSDMA0_RLC4_IB_SUB_REMAIN 0 0x2bf 1 0 0 SIZE 0 13 mmSDMA0_RLC4_PREEMPT 0 0x2c0 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC4_DUMMY_REG 0 0x2c1 1 0 0 DUMMY 0 31 mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x2c2 1 0 0 ADDR 0 31 mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x2c3 1 0 0 ADDR 2 31 mmSDMA0_RLC4_RB_AQL_CNTL 0 0x2c4 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC4_MINOR_PTR_UPDATE 0 0x2c5 1 0 0 ENABLE 0 0 mmSDMA0_RLC4_MIDCMD_DATA0 0 0x2d0 1 0 0 DATA0 0 31 mmSDMA0_RLC4_MIDCMD_DATA1 0 0x2d1 1 0 0 DATA1 0 31 mmSDMA0_RLC4_MIDCMD_DATA2 0 0x2d2 1 0 0 DATA2 0 31 mmSDMA0_RLC4_MIDCMD_DATA3 0 0x2d3 1 0 0 DATA3 0 31 mmSDMA0_RLC4_MIDCMD_DATA4 0 0x2d4 1 0 0 DATA4 0 31 mmSDMA0_RLC4_MIDCMD_DATA5 0 0x2d5 1 0 0 DATA5 0 31 mmSDMA0_RLC4_MIDCMD_DATA6 0 0x2d6 1 0 0 DATA6 0 31 mmSDMA0_RLC4_MIDCMD_DATA7 0 0x2d7 1 0 0 DATA7 0 31 mmSDMA0_RLC4_MIDCMD_DATA8 0 0x2d8 1 0 0 DATA8 0 31 mmSDMA0_RLC4_MIDCMD_DATA9 0 0x2d9 1 0 0 DATA9 0 31 mmSDMA0_RLC4_MIDCMD_DATA10 0 0x2da 1 0 0 DATA10 0 31 mmSDMA0_RLC4_MIDCMD_CNTL 0 0x2db 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC5_RB_CNTL 0 0x2e8 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC5_RB_BASE 0 0x2e9 1 0 0 ADDR 0 31 mmSDMA0_RLC5_RB_BASE_HI 0 0x2ea 1 0 0 ADDR 0 23 mmSDMA0_RLC5_RB_RPTR 0 0x2eb 1 0 0 OFFSET 0 31 mmSDMA0_RLC5_RB_RPTR_HI 0 0x2ec 1 0 0 OFFSET 0 31 mmSDMA0_RLC5_RB_WPTR 0 0x2ed 1 0 0 OFFSET 0 31 mmSDMA0_RLC5_RB_WPTR_HI 0 0x2ee 1 0 0 OFFSET 0 31 mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0 0x2ef 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0 0x2f0 1 0 0 ADDR 0 31 mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0 0x2f1 1 0 0 ADDR 2 31 mmSDMA0_RLC5_IB_CNTL 0 0x2f2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC5_IB_RPTR 0 0x2f3 1 0 0 OFFSET 2 21 mmSDMA0_RLC5_IB_OFFSET 0 0x2f4 1 0 0 OFFSET 2 21 mmSDMA0_RLC5_IB_BASE_LO 0 0x2f5 1 0 0 ADDR 5 31 mmSDMA0_RLC5_IB_BASE_HI 0 0x2f6 1 0 0 ADDR 0 31 mmSDMA0_RLC5_IB_SIZE 0 0x2f7 1 0 0 SIZE 0 19 mmSDMA0_RLC5_SKIP_CNTL 0 0x2f8 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC5_CONTEXT_STATUS 0 0x2f9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC5_DOORBELL 0 0x2fa 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC5_STATUS 0 0x310 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC5_DOORBELL_LOG 0 0x311 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC5_WATERMARK 0 0x312 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC5_DOORBELL_OFFSET 0 0x313 1 0 0 OFFSET 2 27 mmSDMA0_RLC5_CSA_ADDR_LO 0 0x314 1 0 0 ADDR 2 31 mmSDMA0_RLC5_CSA_ADDR_HI 0 0x315 1 0 0 ADDR 0 31 mmSDMA0_RLC5_IB_SUB_REMAIN 0 0x317 1 0 0 SIZE 0 13 mmSDMA0_RLC5_PREEMPT 0 0x318 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC5_DUMMY_REG 0 0x319 1 0 0 DUMMY 0 31 mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x31a 1 0 0 ADDR 0 31 mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x31b 1 0 0 ADDR 2 31 mmSDMA0_RLC5_RB_AQL_CNTL 0 0x31c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC5_MINOR_PTR_UPDATE 0 0x31d 1 0 0 ENABLE 0 0 mmSDMA0_RLC5_MIDCMD_DATA0 0 0x328 1 0 0 DATA0 0 31 mmSDMA0_RLC5_MIDCMD_DATA1 0 0x329 1 0 0 DATA1 0 31 mmSDMA0_RLC5_MIDCMD_DATA2 0 0x32a 1 0 0 DATA2 0 31 mmSDMA0_RLC5_MIDCMD_DATA3 0 0x32b 1 0 0 DATA3 0 31 mmSDMA0_RLC5_MIDCMD_DATA4 0 0x32c 1 0 0 DATA4 0 31 mmSDMA0_RLC5_MIDCMD_DATA5 0 0x32d 1 0 0 DATA5 0 31 mmSDMA0_RLC5_MIDCMD_DATA6 0 0x32e 1 0 0 DATA6 0 31 mmSDMA0_RLC5_MIDCMD_DATA7 0 0x32f 1 0 0 DATA7 0 31 mmSDMA0_RLC5_MIDCMD_DATA8 0 0x330 1 0 0 DATA8 0 31 mmSDMA0_RLC5_MIDCMD_DATA9 0 0x331 1 0 0 DATA9 0 31 mmSDMA0_RLC5_MIDCMD_DATA10 0 0x332 1 0 0 DATA10 0 31 mmSDMA0_RLC5_MIDCMD_CNTL 0 0x333 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC6_RB_CNTL 0 0x340 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC6_RB_BASE 0 0x341 1 0 0 ADDR 0 31 mmSDMA0_RLC6_RB_BASE_HI 0 0x342 1 0 0 ADDR 0 23 mmSDMA0_RLC6_RB_RPTR 0 0x343 1 0 0 OFFSET 0 31 mmSDMA0_RLC6_RB_RPTR_HI 0 0x344 1 0 0 OFFSET 0 31 mmSDMA0_RLC6_RB_WPTR 0 0x345 1 0 0 OFFSET 0 31 mmSDMA0_RLC6_RB_WPTR_HI 0 0x346 1 0 0 OFFSET 0 31 mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0 0x347 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0 0x348 1 0 0 ADDR 0 31 mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0 0x349 1 0 0 ADDR 2 31 mmSDMA0_RLC6_IB_CNTL 0 0x34a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC6_IB_RPTR 0 0x34b 1 0 0 OFFSET 2 21 mmSDMA0_RLC6_IB_OFFSET 0 0x34c 1 0 0 OFFSET 2 21 mmSDMA0_RLC6_IB_BASE_LO 0 0x34d 1 0 0 ADDR 5 31 mmSDMA0_RLC6_IB_BASE_HI 0 0x34e 1 0 0 ADDR 0 31 mmSDMA0_RLC6_IB_SIZE 0 0x34f 1 0 0 SIZE 0 19 mmSDMA0_RLC6_SKIP_CNTL 0 0x350 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC6_CONTEXT_STATUS 0 0x351 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC6_DOORBELL 0 0x352 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC6_STATUS 0 0x368 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC6_DOORBELL_LOG 0 0x369 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC6_WATERMARK 0 0x36a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC6_DOORBELL_OFFSET 0 0x36b 1 0 0 OFFSET 2 27 mmSDMA0_RLC6_CSA_ADDR_LO 0 0x36c 1 0 0 ADDR 2 31 mmSDMA0_RLC6_CSA_ADDR_HI 0 0x36d 1 0 0 ADDR 0 31 mmSDMA0_RLC6_IB_SUB_REMAIN 0 0x36f 1 0 0 SIZE 0 13 mmSDMA0_RLC6_PREEMPT 0 0x370 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC6_DUMMY_REG 0 0x371 1 0 0 DUMMY 0 31 mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x372 1 0 0 ADDR 0 31 mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x373 1 0 0 ADDR 2 31 mmSDMA0_RLC6_RB_AQL_CNTL 0 0x374 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC6_MINOR_PTR_UPDATE 0 0x375 1 0 0 ENABLE 0 0 mmSDMA0_RLC6_MIDCMD_DATA0 0 0x380 1 0 0 DATA0 0 31 mmSDMA0_RLC6_MIDCMD_DATA1 0 0x381 1 0 0 DATA1 0 31 mmSDMA0_RLC6_MIDCMD_DATA2 0 0x382 1 0 0 DATA2 0 31 mmSDMA0_RLC6_MIDCMD_DATA3 0 0x383 1 0 0 DATA3 0 31 mmSDMA0_RLC6_MIDCMD_DATA4 0 0x384 1 0 0 DATA4 0 31 mmSDMA0_RLC6_MIDCMD_DATA5 0 0x385 1 0 0 DATA5 0 31 mmSDMA0_RLC6_MIDCMD_DATA6 0 0x386 1 0 0 DATA6 0 31 mmSDMA0_RLC6_MIDCMD_DATA7 0 0x387 1 0 0 DATA7 0 31 mmSDMA0_RLC6_MIDCMD_DATA8 0 0x388 1 0 0 DATA8 0 31 mmSDMA0_RLC6_MIDCMD_DATA9 0 0x389 1 0 0 DATA9 0 31 mmSDMA0_RLC6_MIDCMD_DATA10 0 0x38a 1 0 0 DATA10 0 31 mmSDMA0_RLC6_MIDCMD_CNTL 0 0x38b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC7_RB_CNTL 0 0x398 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA0_RLC7_RB_BASE 0 0x399 1 0 0 ADDR 0 31 mmSDMA0_RLC7_RB_BASE_HI 0 0x39a 1 0 0 ADDR 0 23 mmSDMA0_RLC7_RB_RPTR 0 0x39b 1 0 0 OFFSET 0 31 mmSDMA0_RLC7_RB_RPTR_HI 0 0x39c 1 0 0 OFFSET 0 31 mmSDMA0_RLC7_RB_WPTR 0 0x39d 1 0 0 OFFSET 0 31 mmSDMA0_RLC7_RB_WPTR_HI 0 0x39e 1 0 0 OFFSET 0 31 mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0 0x39f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0 0x3a0 1 0 0 ADDR 0 31 mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0 0x3a1 1 0 0 ADDR 2 31 mmSDMA0_RLC7_IB_CNTL 0 0x3a2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC7_IB_RPTR 0 0x3a3 1 0 0 OFFSET 2 21 mmSDMA0_RLC7_IB_OFFSET 0 0x3a4 1 0 0 OFFSET 2 21 mmSDMA0_RLC7_IB_BASE_LO 0 0x3a5 1 0 0 ADDR 5 31 mmSDMA0_RLC7_IB_BASE_HI 0 0x3a6 1 0 0 ADDR 0 31 mmSDMA0_RLC7_IB_SIZE 0 0x3a7 1 0 0 SIZE 0 19 mmSDMA0_RLC7_SKIP_CNTL 0 0x3a8 1 0 0 SKIP_COUNT 0 19 mmSDMA0_RLC7_CONTEXT_STATUS 0 0x3a9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC7_DOORBELL 0 0x3aa 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC7_STATUS 0 0x3c0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA0_RLC7_DOORBELL_LOG 0 0x3c1 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC7_WATERMARK 0 0x3c2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA0_RLC7_DOORBELL_OFFSET 0 0x3c3 1 0 0 OFFSET 2 27 mmSDMA0_RLC7_CSA_ADDR_LO 0 0x3c4 1 0 0 ADDR 2 31 mmSDMA0_RLC7_CSA_ADDR_HI 0 0x3c5 1 0 0 ADDR 0 31 mmSDMA0_RLC7_IB_SUB_REMAIN 0 0x3c7 1 0 0 SIZE 0 13 mmSDMA0_RLC7_PREEMPT 0 0x3c8 1 0 0 IB_PREEMPT 0 0 mmSDMA0_RLC7_DUMMY_REG 0 0x3c9 1 0 0 DUMMY 0 31 mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x3ca 1 0 0 ADDR 0 31 mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x3cb 1 0 0 ADDR 2 31 mmSDMA0_RLC7_RB_AQL_CNTL 0 0x3cc 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA0_RLC7_MINOR_PTR_UPDATE 0 0x3cd 1 0 0 ENABLE 0 0 mmSDMA0_RLC7_MIDCMD_DATA0 0 0x3d8 1 0 0 DATA0 0 31 mmSDMA0_RLC7_MIDCMD_DATA1 0 0x3d9 1 0 0 DATA1 0 31 mmSDMA0_RLC7_MIDCMD_DATA2 0 0x3da 1 0 0 DATA2 0 31 mmSDMA0_RLC7_MIDCMD_DATA3 0 0x3db 1 0 0 DATA3 0 31 mmSDMA0_RLC7_MIDCMD_DATA4 0 0x3dc 1 0 0 DATA4 0 31 mmSDMA0_RLC7_MIDCMD_DATA5 0 0x3dd 1 0 0 DATA5 0 31 mmSDMA0_RLC7_MIDCMD_DATA6 0 0x3de 1 0 0 DATA6 0 31 mmSDMA0_RLC7_MIDCMD_DATA7 0 0x3df 1 0 0 DATA7 0 31 mmSDMA0_RLC7_MIDCMD_DATA8 0 0x3e0 1 0 0 DATA8 0 31 mmSDMA0_RLC7_MIDCMD_DATA9 0 0x3e1 1 0 0 DATA9 0 31 mmSDMA0_RLC7_MIDCMD_DATA10 0 0x3e2 1 0 0 DATA10 0 31 mmSDMA0_RLC7_MIDCMD_CNTL 0 0x3e3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_DEC_START 0 0x600 1 0 0 START 0 31 mmSDMA1_GLOBAL_TIMESTAMP_LO 0 0x60f 1 0 0 DATA 0 31 mmSDMA1_GLOBAL_TIMESTAMP_HI 0 0x610 1 0 0 DATA 0 31 mmSDMA1_PG_CNTL 0 0x616 2 0 0 CMD 0 3 STATUS 16 19 mmSDMA1_PG_CTX_LO 0 0x617 1 0 0 ADDR 0 31 mmSDMA1_PG_CTX_HI 0 0x618 1 0 0 ADDR 0 31 mmSDMA1_PG_CTX_CNTL 0 0x619 1 0 0 VMID 4 7 mmSDMA1_POWER_CNTL 0 0x61a 6 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 ON_OFF_STATUS_DURATION_TIME 26 31 mmSDMA1_CLK_CTRL 0 0x61b 10 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED_24_12 12 24 CGCG_EN_OVERRIDE 25 25 SOFT_OVERRIDE4 26 26 SOFT_OVERRIDE3 27 27 SOFT_OVERRIDE2 28 28 SOFT_OVERRIDE1 29 29 SOFT_OVERRIDE0 30 30 SOFT_OVERRIDER_REG 31 31 mmSDMA1_CNTL 0 0x61c 13 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 PAGE_INT_ENABLE 7 7 CH_PERFCNT_ENABLE 16 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA1_CHICKEN_BITS 0 0x61d 20 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 SOFT_OVERRIDE_DCGE 4 4 SOFT_OVERRIDE_SDMA_GRBM_FGCG 5 5 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 T2L_256B_ENABLE 18 18 GCR_FGCG_ENABLE 19 19 SRBM_POLL_RETRYING 20 20 CH_FGCG_ENABLE 21 21 UTCL2_INVREQ_FGCG_ENABLE 22 22 CG_STATUS_OUTPUT 23 23 UTCL1_FGCG_ENABLE 24 24 TIME_BASED_QOS 25 25 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA1_GB_ADDR_CONFIG 0 0x61e 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA1_GB_ADDR_CONFIG_READ 0 0x61f 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA1_RB_RPTR_FETCH_HI 0 0x620 1 0 0 OFFSET 0 31 mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0 0x621 1 0 0 TIMER 0 31 mmSDMA1_RB_RPTR_FETCH 0 0x622 1 0 0 OFFSET 2 31 mmSDMA1_IB_OFFSET_FETCH 0 0x623 1 0 0 OFFSET 2 21 mmSDMA1_PROGRAM 0 0x624 1 0 0 STREAM 0 31 mmSDMA1_STATUS_REG 0 0x625 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA1_STATUS1_REG 0 0x626 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA1_RD_BURST_CNTL 0 0x627 1 0 0 RD_BURST 0 1 mmSDMA1_HBM_PAGE_CONFIG 0 0x628 1 0 0 PAGE_SIZE_EXPONENT 0 0 mmSDMA1_UCODE_CHECKSUM 0 0x629 1 0 0 DATA 0 31 mmSDMA1_F32_CNTL 0 0x62a 4 0 0 HALT 0 0 STEP 1 1 CHECKSUM_CLR 8 8 RESET 9 9 mmSDMA1_FREEZE 0 0x62b 5 0 0 PREEMPT 0 0 FORCE_PREEMPT 1 1 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA1_PHASE0_QUANTUM 0 0x62c 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA1_PHASE1_QUANTUM 0 0x62d 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA1_EDC_CONFIG 0 0x632 2 0 0 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA1_BA_THRESHOLD 0 0x633 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA1_ID 0 0x634 1 0 0 DEVICE_ID 0 7 mmSDMA1_VERSION 0 0x635 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 mmSDMA1_EDC_COUNTER 0 0x636 17 0 0 SDMA_UCODE_BUF_DED 0 0 SDMA_UCODE_BUF_SEC 1 1 SDMA_RB_CMD_BUF_SED 2 2 SDMA_IB_CMD_BUF_SED 3 3 SDMA_UTCL1_RD_FIFO_SED 4 4 SDMA_UTCL1_RDBST_FIFO_SED 5 5 SDMA_DATA_LUT_FIFO_SED 6 6 SDMA_MBANK_DATA_BUF0_SED 7 7 SDMA_MBANK_DATA_BUF1_SED 8 8 SDMA_MBANK_DATA_BUF2_SED 9 9 SDMA_MBANK_DATA_BUF3_SED 10 10 SDMA_MBANK_DATA_BUF4_SED 11 11 SDMA_MBANK_DATA_BUF5_SED 12 12 SDMA_MBANK_DATA_BUF6_SED 13 13 SDMA_MBANK_DATA_BUF7_SED 14 14 SDMA_SPLIT_DAT_BUF_SED 15 15 SDMA_MC_WR_ADDR_FIFO_SED 16 16 mmSDMA1_EDC_COUNTER_CLEAR 0 0x637 1 0 0 DUMMY 0 0 mmSDMA1_STATUS2_REG 0 0x638 3 0 0 ID 0 1 F32_INSTR_PTR 2 15 CMD_OP 16 31 mmSDMA1_ATOMIC_CNTL 0 0x639 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA1_ATOMIC_PREOP_LO 0 0x63a 1 0 0 DATA 0 31 mmSDMA1_ATOMIC_PREOP_HI 0 0x63b 1 0 0 DATA 0 31 mmSDMA1_UTCL1_CNTL 0 0x63c 9 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 5 REDO_WATERMK 6 8 RESP_MODE 9 11 FORCE_INVALIDATION 14 14 FORCE_INVREQ_HEAVY 15 15 INVACK_DELAY 16 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 mmSDMA1_UTCL1_WATERMK 0 0x63d 4 0 0 REQMC_WATERMK 0 9 REQPG_WATERMK 10 17 INVREQ_WATERMK 18 25 XNACK_WATERMK 26 31 mmSDMA1_UTCL1_RD_STATUS 0 0x63e 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_RD_VECTOR 17 20 MERGE_STATE 21 23 ADDR_RD_RTR 24 24 RD_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 HIT_CACHE 27 27 RD_DCC_ENABLE 28 28 NACK_TIMEOUT_SW 29 29 DCC_PAGE_FAULT 30 30 DCC_PAGE_NULL 31 31 mmSDMA1_UTCL1_WR_STATUS 0 0x63f 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_WR_VECTOR 17 20 MERGE_STATE 21 23 F32_WR_RTR 24 24 WR_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 ATOMIC_OP 27 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 mmSDMA1_UTCL1_INV0 0 0x640 14 0 0 CPF_INVREQ_EN 0 0 GPUVM_INVREQ_EN 1 1 CPF_GPA_INVREQ 2 2 GPUVM_INVREQ_LOW 3 3 GPUVM_INVREQ_HIGH 4 4 INVREQ_SIZE 5 10 INVREQ_IDLE 11 11 VMINV_PEND_CNT 12 15 GPUVM_LO_INV_VMID 16 19 GPUVM_HI_INV_VMID 20 23 GPUVM_INV_MODE 24 25 INVREQ_IS_HEAVY 26 26 INVREQ_FROM_CPF 27 27 GPUVM_INVREQ_TAG 28 31 mmSDMA1_UTCL1_INV1 0 0x641 1 0 0 INV_ADDR_LO 0 31 mmSDMA1_UTCL1_INV2 0 0x642 2 0 0 INV_VMID_VEC 0 15 RESERVED 16 31 mmSDMA1_UTCL1_RD_XNACK0 0 0x643 1 0 0 XNACK_ADDR_LO 0 31 mmSDMA1_UTCL1_RD_XNACK1 0 0x644 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA1_UTCL1_WR_XNACK0 0 0x645 1 0 0 XNACK_ADDR_LO 0 31 mmSDMA1_UTCL1_WR_XNACK1 0 0x646 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA1_UTCL1_TIMEOUT 0 0x647 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 mmSDMA1_UTCL1_PAGE 0 0x648 11 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 9 USE_PT_SNOOP 10 10 USE_IO 11 11 RD_L2_POLICY 12 13 WR_L2_POLICY 14 15 DMA_PAGE_SIZE 16 21 USE_BC 22 22 ADDR_IS_PA 23 23 LLC_NOALLOC 24 24 mmSDMA1_RELAX_ORDERING_LUT 0 0x64a 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 mmSDMA1_CHICKEN_BITS_2 0 0x64b 12 0 0 F32_CMD_PROC_DELAY 0 3 CE_BACKWARDS_SIZE_SEL 4 4 CE_DCC_READ_128B_ENABLE 5 5 UTCL1_FORCE_INV_RET_FIFO_FULL_EN 6 6 RESERVED0 7 10 LUT_FIFO_AFULL_MARGIN 11 14 LEGACY_WPTR_POLL_BEHAVIOR 15 15 RB_FIFO_WATERMARK 16 17 IB_FIFO_WATERMARK 18 19 REPEATER_FGCG_EN 20 20 F32_SEND_POSTCODE_EN 21 21 RESERVED 22 31 mmSDMA1_STATUS3_REG 0 0x64c 9 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 AQL_PREV_CMD_IDLE 21 21 TLBI_IDLE 22 22 GCR_IDLE 23 23 INVREQ_IDLE 24 24 QUEUE_ID_MATCH 25 25 INT_QUEUE_ID 26 29 mmSDMA1_PHYSICAL_ADDR_LO 0 0x64d 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 mmSDMA1_PHYSICAL_ADDR_HI 0 0x64e 1 0 0 ADDR 0 15 mmSDMA1_PHASE2_QUANTUM 0 0x64f 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA1_ERROR_LOG 0 0x650 2 0 0 OVERRIDE 0 15 STATUS 16 31 mmSDMA1_PUB_DUMMY_REG0 0 0x651 1 0 0 VALUE 0 31 mmSDMA1_PUB_DUMMY_REG1 0 0x652 1 0 0 VALUE 0 31 mmSDMA1_PUB_DUMMY_REG2 0 0x653 1 0 0 VALUE 0 31 mmSDMA1_PUB_DUMMY_REG3 0 0x654 1 0 0 VALUE 0 31 mmSDMA1_F32_COUNTER 0 0x655 1 0 0 VALUE 0 31 mmSDMA1_CRD_CNTL 0 0x65b 4 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 CH_WRREQ_CREDIT 19 24 CH_RDREQ_CREDIT 25 30 mmSDMA1_AQL_STATUS 0 0x65f 2 0 0 COMPLETE_SIGNAL_EMPTY 0 0 INVALID_CMD_EMPTY 1 1 mmSDMA1_EA_DBIT_ADDR_DATA 0 0x660 1 0 0 VALUE 0 31 mmSDMA1_EA_DBIT_ADDR_INDEX 0 0x661 1 0 0 VALUE 0 2 mmSDMA1_TLBI_GCR_CNTL 0 0x662 5 0 0 TLBI_CMD_DW 0 3 GCR_CMD_DW 4 7 GCR_CLKEN_CYCLE 8 11 TLBI_CREDIT 16 23 GCR_CREDIT 24 31 mmSDMA1_TILING_CONFIG 0 0x663 1 0 0 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA1_INT_STATUS 0 0x670 1 0 0 DATA 0 31 mmSDMA1_HOLE_ADDR_LO 0 0x672 1 0 0 VALUE 0 31 mmSDMA1_HOLE_ADDR_HI 0 0x673 1 0 0 VALUE 0 31 mmSDMA1_CLOCK_GATING_REG 0 0x675 6 0 0 DYN_CLK_GATE_STATUS 0 0 PTR_CLK_GATE_STATUS 1 1 CE_CLK_GATE_STATUS 2 2 CE_BC_CLK_GATE_STATUS 3 3 CE_NBC_CLK_GATE_STATUS 4 4 REG_CLK_GATE_STATUS 5 5 mmSDMA1_STATUS4_REG 0 0x676 16 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 CH_RD_OUTSTANDING 4 4 CH_WR_OUTSTANDING 5 5 GCR_OUTSTANDING 6 6 TLBI_OUTSTANDING 7 7 UTCL2_RD_OUTSTANDING 8 8 UTCL2_WR_OUTSTANDING 9 9 REG_POLLING 10 10 MEM_POLLING 11 11 UTCL2_RD_XNACK 12 13 UTCL2_WR_XNACK 14 15 ACTIVE_QUEUE_ID 16 19 SRIOV_WATING_RLCV_CMD 20 20 SRIOV_SDMA_EXECUTING_CMD 21 21 mmSDMA1_SCRATCH_RAM_DATA 0 0x677 1 0 0 DATA 0 31 mmSDMA1_SCRATCH_RAM_ADDR 0 0x678 1 0 0 ADDR 0 9 mmSDMA1_TIMESTAMP_CNTL 0 0x679 1 0 0 CAPTURE 0 0 mmSDMA1_STATUS5_REG 0 0x67a 11 0 0 GFX_RB_ENABLE_STATUS 0 0 PAGE_RB_ENABLE_STATUS 1 1 RLC0_RB_ENABLE_STATUS 2 2 RLC1_RB_ENABLE_STATUS 3 3 RLC2_RB_ENABLE_STATUS 4 4 RLC3_RB_ENABLE_STATUS 5 5 RLC4_RB_ENABLE_STATUS 6 6 RLC5_RB_ENABLE_STATUS 7 7 RLC6_RB_ENABLE_STATUS 8 8 RLC7_RB_ENABLE_STATUS 9 9 ACTIVE_QUEUE_ID 16 19 mmSDMA1_QUEUE_RESET_REQ 0 0x67b 11 0 0 GFX_QUEUE_RESET 0 0 PAGE_QUEUE_RESET 1 1 RLC0_QUEUE_RESET 2 2 RLC1_QUEUE_RESET 3 3 RLC2_QUEUE_RESET 4 4 RLC3_QUEUE_RESET 5 5 RLC4_QUEUE_RESET 6 6 RLC5_QUEUE_RESET 7 7 RLC6_QUEUE_RESET 8 8 RLC7_QUEUE_RESET 9 9 RESERVED 10 31 mmSDMA1_GFX_RB_CNTL 0 0x680 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_GFX_RB_BASE 0 0x681 1 0 0 ADDR 0 31 mmSDMA1_GFX_RB_BASE_HI 0 0x682 1 0 0 ADDR 0 23 mmSDMA1_GFX_RB_RPTR 0 0x683 1 0 0 OFFSET 0 31 mmSDMA1_GFX_RB_RPTR_HI 0 0x684 1 0 0 OFFSET 0 31 mmSDMA1_GFX_RB_WPTR 0 0x685 1 0 0 OFFSET 0 31 mmSDMA1_GFX_RB_WPTR_HI 0 0x686 1 0 0 OFFSET 0 31 mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0 0x687 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_GFX_RB_RPTR_ADDR_HI 0 0x688 1 0 0 ADDR 0 31 mmSDMA1_GFX_RB_RPTR_ADDR_LO 0 0x689 1 0 0 ADDR 2 31 mmSDMA1_GFX_IB_CNTL 0 0x68a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_GFX_IB_RPTR 0 0x68b 1 0 0 OFFSET 2 21 mmSDMA1_GFX_IB_OFFSET 0 0x68c 1 0 0 OFFSET 2 21 mmSDMA1_GFX_IB_BASE_LO 0 0x68d 1 0 0 ADDR 5 31 mmSDMA1_GFX_IB_BASE_HI 0 0x68e 1 0 0 ADDR 0 31 mmSDMA1_GFX_IB_SIZE 0 0x68f 1 0 0 SIZE 0 19 mmSDMA1_GFX_SKIP_CNTL 0 0x690 1 0 0 SKIP_COUNT 0 19 mmSDMA1_GFX_CONTEXT_STATUS 0 0x691 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_GFX_DOORBELL 0 0x692 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_GFX_CONTEXT_CNTL 0 0x693 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA1_GFX_STATUS 0 0x6a8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_GFX_DOORBELL_LOG 0 0x6a9 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_GFX_WATERMARK 0 0x6aa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_GFX_DOORBELL_OFFSET 0 0x6ab 1 0 0 OFFSET 2 27 mmSDMA1_GFX_CSA_ADDR_LO 0 0x6ac 1 0 0 ADDR 2 31 mmSDMA1_GFX_CSA_ADDR_HI 0 0x6ad 1 0 0 ADDR 0 31 mmSDMA1_GFX_IB_SUB_REMAIN 0 0x6af 1 0 0 SIZE 0 13 mmSDMA1_GFX_PREEMPT 0 0x6b0 1 0 0 IB_PREEMPT 0 0 mmSDMA1_GFX_DUMMY_REG 0 0x6b1 1 0 0 DUMMY 0 31 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0 0x6b2 1 0 0 ADDR 0 31 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0 0x6b3 1 0 0 ADDR 2 31 mmSDMA1_GFX_RB_AQL_CNTL 0 0x6b4 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_GFX_MINOR_PTR_UPDATE 0 0x6b5 1 0 0 ENABLE 0 0 mmSDMA1_GFX_MIDCMD_DATA0 0 0x6c0 1 0 0 DATA0 0 31 mmSDMA1_GFX_MIDCMD_DATA1 0 0x6c1 1 0 0 DATA1 0 31 mmSDMA1_GFX_MIDCMD_DATA2 0 0x6c2 1 0 0 DATA2 0 31 mmSDMA1_GFX_MIDCMD_DATA3 0 0x6c3 1 0 0 DATA3 0 31 mmSDMA1_GFX_MIDCMD_DATA4 0 0x6c4 1 0 0 DATA4 0 31 mmSDMA1_GFX_MIDCMD_DATA5 0 0x6c5 1 0 0 DATA5 0 31 mmSDMA1_GFX_MIDCMD_DATA6 0 0x6c6 1 0 0 DATA6 0 31 mmSDMA1_GFX_MIDCMD_DATA7 0 0x6c7 1 0 0 DATA7 0 31 mmSDMA1_GFX_MIDCMD_DATA8 0 0x6c8 1 0 0 DATA8 0 31 mmSDMA1_GFX_MIDCMD_DATA9 0 0x6c9 1 0 0 DATA9 0 31 mmSDMA1_GFX_MIDCMD_DATA10 0 0x6ca 1 0 0 DATA10 0 31 mmSDMA1_GFX_MIDCMD_CNTL 0 0x6cb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_PAGE_RB_CNTL 0 0x6d8 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_PAGE_RB_BASE 0 0x6d9 1 0 0 ADDR 0 31 mmSDMA1_PAGE_RB_BASE_HI 0 0x6da 1 0 0 ADDR 0 23 mmSDMA1_PAGE_RB_RPTR 0 0x6db 1 0 0 OFFSET 0 31 mmSDMA1_PAGE_RB_RPTR_HI 0 0x6dc 1 0 0 OFFSET 0 31 mmSDMA1_PAGE_RB_WPTR 0 0x6dd 1 0 0 OFFSET 0 31 mmSDMA1_PAGE_RB_WPTR_HI 0 0x6de 1 0 0 OFFSET 0 31 mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0 0x6df 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0 0x6e0 1 0 0 ADDR 0 31 mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0 0x6e1 1 0 0 ADDR 2 31 mmSDMA1_PAGE_IB_CNTL 0 0x6e2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_PAGE_IB_RPTR 0 0x6e3 1 0 0 OFFSET 2 21 mmSDMA1_PAGE_IB_OFFSET 0 0x6e4 1 0 0 OFFSET 2 21 mmSDMA1_PAGE_IB_BASE_LO 0 0x6e5 1 0 0 ADDR 5 31 mmSDMA1_PAGE_IB_BASE_HI 0 0x6e6 1 0 0 ADDR 0 31 mmSDMA1_PAGE_IB_SIZE 0 0x6e7 1 0 0 SIZE 0 19 mmSDMA1_PAGE_SKIP_CNTL 0 0x6e8 1 0 0 SKIP_COUNT 0 19 mmSDMA1_PAGE_CONTEXT_STATUS 0 0x6e9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_PAGE_DOORBELL 0 0x6ea 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_PAGE_STATUS 0 0x700 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_PAGE_DOORBELL_LOG 0 0x701 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_PAGE_WATERMARK 0 0x702 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_PAGE_DOORBELL_OFFSET 0 0x703 1 0 0 OFFSET 2 27 mmSDMA1_PAGE_CSA_ADDR_LO 0 0x704 1 0 0 ADDR 2 31 mmSDMA1_PAGE_CSA_ADDR_HI 0 0x705 1 0 0 ADDR 0 31 mmSDMA1_PAGE_IB_SUB_REMAIN 0 0x707 1 0 0 SIZE 0 13 mmSDMA1_PAGE_PREEMPT 0 0x708 1 0 0 IB_PREEMPT 0 0 mmSDMA1_PAGE_DUMMY_REG 0 0x709 1 0 0 DUMMY 0 31 mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x70a 1 0 0 ADDR 0 31 mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x70b 1 0 0 ADDR 2 31 mmSDMA1_PAGE_RB_AQL_CNTL 0 0x70c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_PAGE_MINOR_PTR_UPDATE 0 0x70d 1 0 0 ENABLE 0 0 mmSDMA1_PAGE_MIDCMD_DATA0 0 0x718 1 0 0 DATA0 0 31 mmSDMA1_PAGE_MIDCMD_DATA1 0 0x719 1 0 0 DATA1 0 31 mmSDMA1_PAGE_MIDCMD_DATA2 0 0x71a 1 0 0 DATA2 0 31 mmSDMA1_PAGE_MIDCMD_DATA3 0 0x71b 1 0 0 DATA3 0 31 mmSDMA1_PAGE_MIDCMD_DATA4 0 0x71c 1 0 0 DATA4 0 31 mmSDMA1_PAGE_MIDCMD_DATA5 0 0x71d 1 0 0 DATA5 0 31 mmSDMA1_PAGE_MIDCMD_DATA6 0 0x71e 1 0 0 DATA6 0 31 mmSDMA1_PAGE_MIDCMD_DATA7 0 0x71f 1 0 0 DATA7 0 31 mmSDMA1_PAGE_MIDCMD_DATA8 0 0x720 1 0 0 DATA8 0 31 mmSDMA1_PAGE_MIDCMD_DATA9 0 0x721 1 0 0 DATA9 0 31 mmSDMA1_PAGE_MIDCMD_DATA10 0 0x722 1 0 0 DATA10 0 31 mmSDMA1_PAGE_MIDCMD_CNTL 0 0x723 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC0_RB_CNTL 0 0x730 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC0_RB_BASE 0 0x731 1 0 0 ADDR 0 31 mmSDMA1_RLC0_RB_BASE_HI 0 0x732 1 0 0 ADDR 0 23 mmSDMA1_RLC0_RB_RPTR 0 0x733 1 0 0 OFFSET 0 31 mmSDMA1_RLC0_RB_RPTR_HI 0 0x734 1 0 0 OFFSET 0 31 mmSDMA1_RLC0_RB_WPTR 0 0x735 1 0 0 OFFSET 0 31 mmSDMA1_RLC0_RB_WPTR_HI 0 0x736 1 0 0 OFFSET 0 31 mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0 0x737 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0 0x738 1 0 0 ADDR 0 31 mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0 0x739 1 0 0 ADDR 2 31 mmSDMA1_RLC0_IB_CNTL 0 0x73a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC0_IB_RPTR 0 0x73b 1 0 0 OFFSET 2 21 mmSDMA1_RLC0_IB_OFFSET 0 0x73c 1 0 0 OFFSET 2 21 mmSDMA1_RLC0_IB_BASE_LO 0 0x73d 1 0 0 ADDR 5 31 mmSDMA1_RLC0_IB_BASE_HI 0 0x73e 1 0 0 ADDR 0 31 mmSDMA1_RLC0_IB_SIZE 0 0x73f 1 0 0 SIZE 0 19 mmSDMA1_RLC0_SKIP_CNTL 0 0x740 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC0_CONTEXT_STATUS 0 0x741 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC0_DOORBELL 0 0x742 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC0_STATUS 0 0x758 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC0_DOORBELL_LOG 0 0x759 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC0_WATERMARK 0 0x75a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC0_DOORBELL_OFFSET 0 0x75b 1 0 0 OFFSET 2 27 mmSDMA1_RLC0_CSA_ADDR_LO 0 0x75c 1 0 0 ADDR 2 31 mmSDMA1_RLC0_CSA_ADDR_HI 0 0x75d 1 0 0 ADDR 0 31 mmSDMA1_RLC0_IB_SUB_REMAIN 0 0x75f 1 0 0 SIZE 0 13 mmSDMA1_RLC0_PREEMPT 0 0x760 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC0_DUMMY_REG 0 0x761 1 0 0 DUMMY 0 31 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x762 1 0 0 ADDR 0 31 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x763 1 0 0 ADDR 2 31 mmSDMA1_RLC0_RB_AQL_CNTL 0 0x764 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC0_MINOR_PTR_UPDATE 0 0x765 1 0 0 ENABLE 0 0 mmSDMA1_RLC0_MIDCMD_DATA0 0 0x770 1 0 0 DATA0 0 31 mmSDMA1_RLC0_MIDCMD_DATA1 0 0x771 1 0 0 DATA1 0 31 mmSDMA1_RLC0_MIDCMD_DATA2 0 0x772 1 0 0 DATA2 0 31 mmSDMA1_RLC0_MIDCMD_DATA3 0 0x773 1 0 0 DATA3 0 31 mmSDMA1_RLC0_MIDCMD_DATA4 0 0x774 1 0 0 DATA4 0 31 mmSDMA1_RLC0_MIDCMD_DATA5 0 0x775 1 0 0 DATA5 0 31 mmSDMA1_RLC0_MIDCMD_DATA6 0 0x776 1 0 0 DATA6 0 31 mmSDMA1_RLC0_MIDCMD_DATA7 0 0x777 1 0 0 DATA7 0 31 mmSDMA1_RLC0_MIDCMD_DATA8 0 0x778 1 0 0 DATA8 0 31 mmSDMA1_RLC0_MIDCMD_DATA9 0 0x779 1 0 0 DATA9 0 31 mmSDMA1_RLC0_MIDCMD_DATA10 0 0x77a 1 0 0 DATA10 0 31 mmSDMA1_RLC0_MIDCMD_CNTL 0 0x77b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC1_RB_CNTL 0 0x788 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC1_RB_BASE 0 0x789 1 0 0 ADDR 0 31 mmSDMA1_RLC1_RB_BASE_HI 0 0x78a 1 0 0 ADDR 0 23 mmSDMA1_RLC1_RB_RPTR 0 0x78b 1 0 0 OFFSET 0 31 mmSDMA1_RLC1_RB_RPTR_HI 0 0x78c 1 0 0 OFFSET 0 31 mmSDMA1_RLC1_RB_WPTR 0 0x78d 1 0 0 OFFSET 0 31 mmSDMA1_RLC1_RB_WPTR_HI 0 0x78e 1 0 0 OFFSET 0 31 mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0 0x78f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0 0x790 1 0 0 ADDR 0 31 mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0 0x791 1 0 0 ADDR 2 31 mmSDMA1_RLC1_IB_CNTL 0 0x792 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC1_IB_RPTR 0 0x793 1 0 0 OFFSET 2 21 mmSDMA1_RLC1_IB_OFFSET 0 0x794 1 0 0 OFFSET 2 21 mmSDMA1_RLC1_IB_BASE_LO 0 0x795 1 0 0 ADDR 5 31 mmSDMA1_RLC1_IB_BASE_HI 0 0x796 1 0 0 ADDR 0 31 mmSDMA1_RLC1_IB_SIZE 0 0x797 1 0 0 SIZE 0 19 mmSDMA1_RLC1_SKIP_CNTL 0 0x798 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC1_CONTEXT_STATUS 0 0x799 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC1_DOORBELL 0 0x79a 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC1_STATUS 0 0x7b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC1_DOORBELL_LOG 0 0x7b1 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC1_WATERMARK 0 0x7b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC1_DOORBELL_OFFSET 0 0x7b3 1 0 0 OFFSET 2 27 mmSDMA1_RLC1_CSA_ADDR_LO 0 0x7b4 1 0 0 ADDR 2 31 mmSDMA1_RLC1_CSA_ADDR_HI 0 0x7b5 1 0 0 ADDR 0 31 mmSDMA1_RLC1_IB_SUB_REMAIN 0 0x7b7 1 0 0 SIZE 0 13 mmSDMA1_RLC1_PREEMPT 0 0x7b8 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC1_DUMMY_REG 0 0x7b9 1 0 0 DUMMY 0 31 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x7ba 1 0 0 ADDR 0 31 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x7bb 1 0 0 ADDR 2 31 mmSDMA1_RLC1_RB_AQL_CNTL 0 0x7bc 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC1_MINOR_PTR_UPDATE 0 0x7bd 1 0 0 ENABLE 0 0 mmSDMA1_RLC1_MIDCMD_DATA0 0 0x7c8 1 0 0 DATA0 0 31 mmSDMA1_RLC1_MIDCMD_DATA1 0 0x7c9 1 0 0 DATA1 0 31 mmSDMA1_RLC1_MIDCMD_DATA2 0 0x7ca 1 0 0 DATA2 0 31 mmSDMA1_RLC1_MIDCMD_DATA3 0 0x7cb 1 0 0 DATA3 0 31 mmSDMA1_RLC1_MIDCMD_DATA4 0 0x7cc 1 0 0 DATA4 0 31 mmSDMA1_RLC1_MIDCMD_DATA5 0 0x7cd 1 0 0 DATA5 0 31 mmSDMA1_RLC1_MIDCMD_DATA6 0 0x7ce 1 0 0 DATA6 0 31 mmSDMA1_RLC1_MIDCMD_DATA7 0 0x7cf 1 0 0 DATA7 0 31 mmSDMA1_RLC1_MIDCMD_DATA8 0 0x7d0 1 0 0 DATA8 0 31 mmSDMA1_RLC1_MIDCMD_DATA9 0 0x7d1 1 0 0 DATA9 0 31 mmSDMA1_RLC1_MIDCMD_DATA10 0 0x7d2 1 0 0 DATA10 0 31 mmSDMA1_RLC1_MIDCMD_CNTL 0 0x7d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC2_RB_CNTL 0 0x7e0 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC2_RB_BASE 0 0x7e1 1 0 0 ADDR 0 31 mmSDMA1_RLC2_RB_BASE_HI 0 0x7e2 1 0 0 ADDR 0 23 mmSDMA1_RLC2_RB_RPTR 0 0x7e3 1 0 0 OFFSET 0 31 mmSDMA1_RLC2_RB_RPTR_HI 0 0x7e4 1 0 0 OFFSET 0 31 mmSDMA1_RLC2_RB_WPTR 0 0x7e5 1 0 0 OFFSET 0 31 mmSDMA1_RLC2_RB_WPTR_HI 0 0x7e6 1 0 0 OFFSET 0 31 mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0 0x7e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0 0x7e8 1 0 0 ADDR 0 31 mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0 0x7e9 1 0 0 ADDR 2 31 mmSDMA1_RLC2_IB_CNTL 0 0x7ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC2_IB_RPTR 0 0x7eb 1 0 0 OFFSET 2 21 mmSDMA1_RLC2_IB_OFFSET 0 0x7ec 1 0 0 OFFSET 2 21 mmSDMA1_RLC2_IB_BASE_LO 0 0x7ed 1 0 0 ADDR 5 31 mmSDMA1_RLC2_IB_BASE_HI 0 0x7ee 1 0 0 ADDR 0 31 mmSDMA1_RLC2_IB_SIZE 0 0x7ef 1 0 0 SIZE 0 19 mmSDMA1_RLC2_SKIP_CNTL 0 0x7f0 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC2_CONTEXT_STATUS 0 0x7f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC2_DOORBELL 0 0x7f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC2_STATUS 0 0x808 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC2_DOORBELL_LOG 0 0x809 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC2_WATERMARK 0 0x80a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC2_DOORBELL_OFFSET 0 0x80b 1 0 0 OFFSET 2 27 mmSDMA1_RLC2_CSA_ADDR_LO 0 0x80c 1 0 0 ADDR 2 31 mmSDMA1_RLC2_CSA_ADDR_HI 0 0x80d 1 0 0 ADDR 0 31 mmSDMA1_RLC2_IB_SUB_REMAIN 0 0x80f 1 0 0 SIZE 0 13 mmSDMA1_RLC2_PREEMPT 0 0x810 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC2_DUMMY_REG 0 0x811 1 0 0 DUMMY 0 31 mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x812 1 0 0 ADDR 0 31 mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x813 1 0 0 ADDR 2 31 mmSDMA1_RLC2_RB_AQL_CNTL 0 0x814 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC2_MINOR_PTR_UPDATE 0 0x815 1 0 0 ENABLE 0 0 mmSDMA1_RLC2_MIDCMD_DATA0 0 0x820 1 0 0 DATA0 0 31 mmSDMA1_RLC2_MIDCMD_DATA1 0 0x821 1 0 0 DATA1 0 31 mmSDMA1_RLC2_MIDCMD_DATA2 0 0x822 1 0 0 DATA2 0 31 mmSDMA1_RLC2_MIDCMD_DATA3 0 0x823 1 0 0 DATA3 0 31 mmSDMA1_RLC2_MIDCMD_DATA4 0 0x824 1 0 0 DATA4 0 31 mmSDMA1_RLC2_MIDCMD_DATA5 0 0x825 1 0 0 DATA5 0 31 mmSDMA1_RLC2_MIDCMD_DATA6 0 0x826 1 0 0 DATA6 0 31 mmSDMA1_RLC2_MIDCMD_DATA7 0 0x827 1 0 0 DATA7 0 31 mmSDMA1_RLC2_MIDCMD_DATA8 0 0x828 1 0 0 DATA8 0 31 mmSDMA1_RLC2_MIDCMD_DATA9 0 0x829 1 0 0 DATA9 0 31 mmSDMA1_RLC2_MIDCMD_DATA10 0 0x82a 1 0 0 DATA10 0 31 mmSDMA1_RLC2_MIDCMD_CNTL 0 0x82b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC3_RB_CNTL 0 0x838 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC3_RB_BASE 0 0x839 1 0 0 ADDR 0 31 mmSDMA1_RLC3_RB_BASE_HI 0 0x83a 1 0 0 ADDR 0 23 mmSDMA1_RLC3_RB_RPTR 0 0x83b 1 0 0 OFFSET 0 31 mmSDMA1_RLC3_RB_RPTR_HI 0 0x83c 1 0 0 OFFSET 0 31 mmSDMA1_RLC3_RB_WPTR 0 0x83d 1 0 0 OFFSET 0 31 mmSDMA1_RLC3_RB_WPTR_HI 0 0x83e 1 0 0 OFFSET 0 31 mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0 0x83f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0 0x840 1 0 0 ADDR 0 31 mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0 0x841 1 0 0 ADDR 2 31 mmSDMA1_RLC3_IB_CNTL 0 0x842 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC3_IB_RPTR 0 0x843 1 0 0 OFFSET 2 21 mmSDMA1_RLC3_IB_OFFSET 0 0x844 1 0 0 OFFSET 2 21 mmSDMA1_RLC3_IB_BASE_LO 0 0x845 1 0 0 ADDR 5 31 mmSDMA1_RLC3_IB_BASE_HI 0 0x846 1 0 0 ADDR 0 31 mmSDMA1_RLC3_IB_SIZE 0 0x847 1 0 0 SIZE 0 19 mmSDMA1_RLC3_SKIP_CNTL 0 0x848 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC3_CONTEXT_STATUS 0 0x849 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC3_DOORBELL 0 0x84a 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC3_STATUS 0 0x860 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC3_DOORBELL_LOG 0 0x861 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC3_WATERMARK 0 0x862 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC3_DOORBELL_OFFSET 0 0x863 1 0 0 OFFSET 2 27 mmSDMA1_RLC3_CSA_ADDR_LO 0 0x864 1 0 0 ADDR 2 31 mmSDMA1_RLC3_CSA_ADDR_HI 0 0x865 1 0 0 ADDR 0 31 mmSDMA1_RLC3_IB_SUB_REMAIN 0 0x867 1 0 0 SIZE 0 13 mmSDMA1_RLC3_PREEMPT 0 0x868 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC3_DUMMY_REG 0 0x869 1 0 0 DUMMY 0 31 mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x86a 1 0 0 ADDR 0 31 mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x86b 1 0 0 ADDR 2 31 mmSDMA1_RLC3_RB_AQL_CNTL 0 0x86c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC3_MINOR_PTR_UPDATE 0 0x86d 1 0 0 ENABLE 0 0 mmSDMA1_RLC3_MIDCMD_DATA0 0 0x878 1 0 0 DATA0 0 31 mmSDMA1_RLC3_MIDCMD_DATA1 0 0x879 1 0 0 DATA1 0 31 mmSDMA1_RLC3_MIDCMD_DATA2 0 0x87a 1 0 0 DATA2 0 31 mmSDMA1_RLC3_MIDCMD_DATA3 0 0x87b 1 0 0 DATA3 0 31 mmSDMA1_RLC3_MIDCMD_DATA4 0 0x87c 1 0 0 DATA4 0 31 mmSDMA1_RLC3_MIDCMD_DATA5 0 0x87d 1 0 0 DATA5 0 31 mmSDMA1_RLC3_MIDCMD_DATA6 0 0x87e 1 0 0 DATA6 0 31 mmSDMA1_RLC3_MIDCMD_DATA7 0 0x87f 1 0 0 DATA7 0 31 mmSDMA1_RLC3_MIDCMD_DATA8 0 0x880 1 0 0 DATA8 0 31 mmSDMA1_RLC3_MIDCMD_DATA9 0 0x881 1 0 0 DATA9 0 31 mmSDMA1_RLC3_MIDCMD_DATA10 0 0x882 1 0 0 DATA10 0 31 mmSDMA1_RLC3_MIDCMD_CNTL 0 0x883 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC4_RB_CNTL 0 0x890 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC4_RB_BASE 0 0x891 1 0 0 ADDR 0 31 mmSDMA1_RLC4_RB_BASE_HI 0 0x892 1 0 0 ADDR 0 23 mmSDMA1_RLC4_RB_RPTR 0 0x893 1 0 0 OFFSET 0 31 mmSDMA1_RLC4_RB_RPTR_HI 0 0x894 1 0 0 OFFSET 0 31 mmSDMA1_RLC4_RB_WPTR 0 0x895 1 0 0 OFFSET 0 31 mmSDMA1_RLC4_RB_WPTR_HI 0 0x896 1 0 0 OFFSET 0 31 mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0 0x897 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0 0x898 1 0 0 ADDR 0 31 mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0 0x899 1 0 0 ADDR 2 31 mmSDMA1_RLC4_IB_CNTL 0 0x89a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC4_IB_RPTR 0 0x89b 1 0 0 OFFSET 2 21 mmSDMA1_RLC4_IB_OFFSET 0 0x89c 1 0 0 OFFSET 2 21 mmSDMA1_RLC4_IB_BASE_LO 0 0x89d 1 0 0 ADDR 5 31 mmSDMA1_RLC4_IB_BASE_HI 0 0x89e 1 0 0 ADDR 0 31 mmSDMA1_RLC4_IB_SIZE 0 0x89f 1 0 0 SIZE 0 19 mmSDMA1_RLC4_SKIP_CNTL 0 0x8a0 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC4_CONTEXT_STATUS 0 0x8a1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC4_DOORBELL 0 0x8a2 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC4_STATUS 0 0x8b8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC4_DOORBELL_LOG 0 0x8b9 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC4_WATERMARK 0 0x8ba 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC4_DOORBELL_OFFSET 0 0x8bb 1 0 0 OFFSET 2 27 mmSDMA1_RLC4_CSA_ADDR_LO 0 0x8bc 1 0 0 ADDR 2 31 mmSDMA1_RLC4_CSA_ADDR_HI 0 0x8bd 1 0 0 ADDR 0 31 mmSDMA1_RLC4_IB_SUB_REMAIN 0 0x8bf 1 0 0 SIZE 0 13 mmSDMA1_RLC4_PREEMPT 0 0x8c0 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC4_DUMMY_REG 0 0x8c1 1 0 0 DUMMY 0 31 mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x8c2 1 0 0 ADDR 0 31 mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x8c3 1 0 0 ADDR 2 31 mmSDMA1_RLC4_RB_AQL_CNTL 0 0x8c4 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC4_MINOR_PTR_UPDATE 0 0x8c5 1 0 0 ENABLE 0 0 mmSDMA1_RLC4_MIDCMD_DATA0 0 0x8d0 1 0 0 DATA0 0 31 mmSDMA1_RLC4_MIDCMD_DATA1 0 0x8d1 1 0 0 DATA1 0 31 mmSDMA1_RLC4_MIDCMD_DATA2 0 0x8d2 1 0 0 DATA2 0 31 mmSDMA1_RLC4_MIDCMD_DATA3 0 0x8d3 1 0 0 DATA3 0 31 mmSDMA1_RLC4_MIDCMD_DATA4 0 0x8d4 1 0 0 DATA4 0 31 mmSDMA1_RLC4_MIDCMD_DATA5 0 0x8d5 1 0 0 DATA5 0 31 mmSDMA1_RLC4_MIDCMD_DATA6 0 0x8d6 1 0 0 DATA6 0 31 mmSDMA1_RLC4_MIDCMD_DATA7 0 0x8d7 1 0 0 DATA7 0 31 mmSDMA1_RLC4_MIDCMD_DATA8 0 0x8d8 1 0 0 DATA8 0 31 mmSDMA1_RLC4_MIDCMD_DATA9 0 0x8d9 1 0 0 DATA9 0 31 mmSDMA1_RLC4_MIDCMD_DATA10 0 0x8da 1 0 0 DATA10 0 31 mmSDMA1_RLC4_MIDCMD_CNTL 0 0x8db 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC5_RB_CNTL 0 0x8e8 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC5_RB_BASE 0 0x8e9 1 0 0 ADDR 0 31 mmSDMA1_RLC5_RB_BASE_HI 0 0x8ea 1 0 0 ADDR 0 23 mmSDMA1_RLC5_RB_RPTR 0 0x8eb 1 0 0 OFFSET 0 31 mmSDMA1_RLC5_RB_RPTR_HI 0 0x8ec 1 0 0 OFFSET 0 31 mmSDMA1_RLC5_RB_WPTR 0 0x8ed 1 0 0 OFFSET 0 31 mmSDMA1_RLC5_RB_WPTR_HI 0 0x8ee 1 0 0 OFFSET 0 31 mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0 0x8ef 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0 0x8f0 1 0 0 ADDR 0 31 mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0 0x8f1 1 0 0 ADDR 2 31 mmSDMA1_RLC5_IB_CNTL 0 0x8f2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC5_IB_RPTR 0 0x8f3 1 0 0 OFFSET 2 21 mmSDMA1_RLC5_IB_OFFSET 0 0x8f4 1 0 0 OFFSET 2 21 mmSDMA1_RLC5_IB_BASE_LO 0 0x8f5 1 0 0 ADDR 5 31 mmSDMA1_RLC5_IB_BASE_HI 0 0x8f6 1 0 0 ADDR 0 31 mmSDMA1_RLC5_IB_SIZE 0 0x8f7 1 0 0 SIZE 0 19 mmSDMA1_RLC5_SKIP_CNTL 0 0x8f8 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC5_CONTEXT_STATUS 0 0x8f9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC5_DOORBELL 0 0x8fa 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC5_STATUS 0 0x910 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC5_DOORBELL_LOG 0 0x911 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC5_WATERMARK 0 0x912 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC5_DOORBELL_OFFSET 0 0x913 1 0 0 OFFSET 2 27 mmSDMA1_RLC5_CSA_ADDR_LO 0 0x914 1 0 0 ADDR 2 31 mmSDMA1_RLC5_CSA_ADDR_HI 0 0x915 1 0 0 ADDR 0 31 mmSDMA1_RLC5_IB_SUB_REMAIN 0 0x917 1 0 0 SIZE 0 13 mmSDMA1_RLC5_PREEMPT 0 0x918 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC5_DUMMY_REG 0 0x919 1 0 0 DUMMY 0 31 mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x91a 1 0 0 ADDR 0 31 mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x91b 1 0 0 ADDR 2 31 mmSDMA1_RLC5_RB_AQL_CNTL 0 0x91c 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC5_MINOR_PTR_UPDATE 0 0x91d 1 0 0 ENABLE 0 0 mmSDMA1_RLC5_MIDCMD_DATA0 0 0x928 1 0 0 DATA0 0 31 mmSDMA1_RLC5_MIDCMD_DATA1 0 0x929 1 0 0 DATA1 0 31 mmSDMA1_RLC5_MIDCMD_DATA2 0 0x92a 1 0 0 DATA2 0 31 mmSDMA1_RLC5_MIDCMD_DATA3 0 0x92b 1 0 0 DATA3 0 31 mmSDMA1_RLC5_MIDCMD_DATA4 0 0x92c 1 0 0 DATA4 0 31 mmSDMA1_RLC5_MIDCMD_DATA5 0 0x92d 1 0 0 DATA5 0 31 mmSDMA1_RLC5_MIDCMD_DATA6 0 0x92e 1 0 0 DATA6 0 31 mmSDMA1_RLC5_MIDCMD_DATA7 0 0x92f 1 0 0 DATA7 0 31 mmSDMA1_RLC5_MIDCMD_DATA8 0 0x930 1 0 0 DATA8 0 31 mmSDMA1_RLC5_MIDCMD_DATA9 0 0x931 1 0 0 DATA9 0 31 mmSDMA1_RLC5_MIDCMD_DATA10 0 0x932 1 0 0 DATA10 0 31 mmSDMA1_RLC5_MIDCMD_CNTL 0 0x933 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC6_RB_CNTL 0 0x940 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC6_RB_BASE 0 0x941 1 0 0 ADDR 0 31 mmSDMA1_RLC6_RB_BASE_HI 0 0x942 1 0 0 ADDR 0 23 mmSDMA1_RLC6_RB_RPTR 0 0x943 1 0 0 OFFSET 0 31 mmSDMA1_RLC6_RB_RPTR_HI 0 0x944 1 0 0 OFFSET 0 31 mmSDMA1_RLC6_RB_WPTR 0 0x945 1 0 0 OFFSET 0 31 mmSDMA1_RLC6_RB_WPTR_HI 0 0x946 1 0 0 OFFSET 0 31 mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0 0x947 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0 0x948 1 0 0 ADDR 0 31 mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0 0x949 1 0 0 ADDR 2 31 mmSDMA1_RLC6_IB_CNTL 0 0x94a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC6_IB_RPTR 0 0x94b 1 0 0 OFFSET 2 21 mmSDMA1_RLC6_IB_OFFSET 0 0x94c 1 0 0 OFFSET 2 21 mmSDMA1_RLC6_IB_BASE_LO 0 0x94d 1 0 0 ADDR 5 31 mmSDMA1_RLC6_IB_BASE_HI 0 0x94e 1 0 0 ADDR 0 31 mmSDMA1_RLC6_IB_SIZE 0 0x94f 1 0 0 SIZE 0 19 mmSDMA1_RLC6_SKIP_CNTL 0 0x950 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC6_CONTEXT_STATUS 0 0x951 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC6_DOORBELL 0 0x952 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC6_STATUS 0 0x968 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC6_DOORBELL_LOG 0 0x969 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC6_WATERMARK 0 0x96a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC6_DOORBELL_OFFSET 0 0x96b 1 0 0 OFFSET 2 27 mmSDMA1_RLC6_CSA_ADDR_LO 0 0x96c 1 0 0 ADDR 2 31 mmSDMA1_RLC6_CSA_ADDR_HI 0 0x96d 1 0 0 ADDR 0 31 mmSDMA1_RLC6_IB_SUB_REMAIN 0 0x96f 1 0 0 SIZE 0 13 mmSDMA1_RLC6_PREEMPT 0 0x970 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC6_DUMMY_REG 0 0x971 1 0 0 DUMMY 0 31 mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x972 1 0 0 ADDR 0 31 mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x973 1 0 0 ADDR 2 31 mmSDMA1_RLC6_RB_AQL_CNTL 0 0x974 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC6_MINOR_PTR_UPDATE 0 0x975 1 0 0 ENABLE 0 0 mmSDMA1_RLC6_MIDCMD_DATA0 0 0x980 1 0 0 DATA0 0 31 mmSDMA1_RLC6_MIDCMD_DATA1 0 0x981 1 0 0 DATA1 0 31 mmSDMA1_RLC6_MIDCMD_DATA2 0 0x982 1 0 0 DATA2 0 31 mmSDMA1_RLC6_MIDCMD_DATA3 0 0x983 1 0 0 DATA3 0 31 mmSDMA1_RLC6_MIDCMD_DATA4 0 0x984 1 0 0 DATA4 0 31 mmSDMA1_RLC6_MIDCMD_DATA5 0 0x985 1 0 0 DATA5 0 31 mmSDMA1_RLC6_MIDCMD_DATA6 0 0x986 1 0 0 DATA6 0 31 mmSDMA1_RLC6_MIDCMD_DATA7 0 0x987 1 0 0 DATA7 0 31 mmSDMA1_RLC6_MIDCMD_DATA8 0 0x988 1 0 0 DATA8 0 31 mmSDMA1_RLC6_MIDCMD_DATA9 0 0x989 1 0 0 DATA9 0 31 mmSDMA1_RLC6_MIDCMD_DATA10 0 0x98a 1 0 0 DATA10 0 31 mmSDMA1_RLC6_MIDCMD_CNTL 0 0x98b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC7_RB_CNTL 0 0x998 9 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA1_RLC7_RB_BASE 0 0x999 1 0 0 ADDR 0 31 mmSDMA1_RLC7_RB_BASE_HI 0 0x99a 1 0 0 ADDR 0 23 mmSDMA1_RLC7_RB_RPTR 0 0x99b 1 0 0 OFFSET 0 31 mmSDMA1_RLC7_RB_RPTR_HI 0 0x99c 1 0 0 OFFSET 0 31 mmSDMA1_RLC7_RB_WPTR 0 0x99d 1 0 0 OFFSET 0 31 mmSDMA1_RLC7_RB_WPTR_HI 0 0x99e 1 0 0 OFFSET 0 31 mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0 0x99f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0 0x9a0 1 0 0 ADDR 0 31 mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0 0x9a1 1 0 0 ADDR 2 31 mmSDMA1_RLC7_IB_CNTL 0 0x9a2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC7_IB_RPTR 0 0x9a3 1 0 0 OFFSET 2 21 mmSDMA1_RLC7_IB_OFFSET 0 0x9a4 1 0 0 OFFSET 2 21 mmSDMA1_RLC7_IB_BASE_LO 0 0x9a5 1 0 0 ADDR 5 31 mmSDMA1_RLC7_IB_BASE_HI 0 0x9a6 1 0 0 ADDR 0 31 mmSDMA1_RLC7_IB_SIZE 0 0x9a7 1 0 0 SIZE 0 19 mmSDMA1_RLC7_SKIP_CNTL 0 0x9a8 1 0 0 SKIP_COUNT 0 19 mmSDMA1_RLC7_CONTEXT_STATUS 0 0x9a9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC7_DOORBELL 0 0x9aa 2 0 0 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC7_STATUS 0 0x9c0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA1_RLC7_DOORBELL_LOG 0 0x9c1 2 0 0 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC7_WATERMARK 0 0x9c2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA1_RLC7_DOORBELL_OFFSET 0 0x9c3 1 0 0 OFFSET 2 27 mmSDMA1_RLC7_CSA_ADDR_LO 0 0x9c4 1 0 0 ADDR 2 31 mmSDMA1_RLC7_CSA_ADDR_HI 0 0x9c5 1 0 0 ADDR 0 31 mmSDMA1_RLC7_IB_SUB_REMAIN 0 0x9c7 1 0 0 SIZE 0 13 mmSDMA1_RLC7_PREEMPT 0 0x9c8 1 0 0 IB_PREEMPT 0 0 mmSDMA1_RLC7_DUMMY_REG 0 0x9c9 1 0 0 DUMMY 0 31 mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x9ca 1 0 0 ADDR 0 31 mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x9cb 1 0 0 ADDR 2 31 mmSDMA1_RLC7_RB_AQL_CNTL 0 0x9cc 6 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA1_RLC7_MINOR_PTR_UPDATE 0 0x9cd 1 0 0 ENABLE 0 0 mmSDMA1_RLC7_MIDCMD_DATA0 0 0x9d8 1 0 0 DATA0 0 31 mmSDMA1_RLC7_MIDCMD_DATA1 0 0x9d9 1 0 0 DATA1 0 31 mmSDMA1_RLC7_MIDCMD_DATA2 0 0x9da 1 0 0 DATA2 0 31 mmSDMA1_RLC7_MIDCMD_DATA3 0 0x9db 1 0 0 DATA3 0 31 mmSDMA1_RLC7_MIDCMD_DATA4 0 0x9dc 1 0 0 DATA4 0 31 mmSDMA1_RLC7_MIDCMD_DATA5 0 0x9dd 1 0 0 DATA5 0 31 mmSDMA1_RLC7_MIDCMD_DATA6 0 0x9de 1 0 0 DATA6 0 31 mmSDMA1_RLC7_MIDCMD_DATA7 0 0x9df 1 0 0 DATA7 0 31 mmSDMA1_RLC7_MIDCMD_DATA8 0 0x9e0 1 0 0 DATA8 0 31 mmSDMA1_RLC7_MIDCMD_DATA9 0 0x9e1 1 0 0 DATA9 0 31 mmSDMA1_RLC7_MIDCMD_DATA10 0 0x9e2 1 0 0 DATA10 0 31 mmSDMA1_RLC7_MIDCMD_CNTL 0 0x9e3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmGRBM_CNTL 0 0xda0 2 0 0 READ_TIMEOUT 0 7 REPORT_LAST_RDERR 31 31 mmGRBM_SKEW_CNTL 0 0xda1 2 0 0 SKEW_TOP_THRESHOLD 0 5 SKEW_COUNT 6 11 mmGRBM_STATUS2 0 0xda2 29 0 0 ME0PIPE1_CMDFIFO_AVAIL 0 3 ME0PIPE1_CF_RQ_PENDING 4 4 ME0PIPE1_PF_RQ_PENDING 5 5 ME1PIPE0_RQ_PENDING 6 6 ME1PIPE1_RQ_PENDING 7 7 ME1PIPE2_RQ_PENDING 8 8 ME1PIPE3_RQ_PENDING 9 9 ME2PIPE0_RQ_PENDING 10 10 ME2PIPE1_RQ_PENDING 11 11 ME2PIPE2_RQ_PENDING 12 12 ME2PIPE3_RQ_PENDING 13 13 RLC_RQ_PENDING 14 14 UTCL2_BUSY 15 15 EA_BUSY 16 16 RMI_BUSY 17 17 UTCL2_RQ_PENDING 18 18 SDMA_SCH_RQ_PENDING 19 19 EA_LINK_BUSY 20 20 SDMA_BUSY 21 21 SDMA0_RQ_PENDING 22 22 SDMA1_RQ_PENDING 23 23 SDMA2_RQ_PENDING 24 24 SDMA3_RQ_PENDING 25 25 RLC_BUSY 26 26 TCP_BUSY 27 27 CPF_BUSY 28 28 CPC_BUSY 29 29 CPG_BUSY 30 30 CPAXI_BUSY 31 31 mmGRBM_PWR_CNTL 0 0xda3 6 0 0 ALL_REQ_TYPE 0 1 GFX_REQ_TYPE 2 3 ALL_RSP_TYPE 4 5 GFX_RSP_TYPE 6 7 GFX_REQ_EN 14 14 ALL_REQ_EN 15 15 mmGRBM_STATUS 0 0xda4 20 0 0 ME0PIPE0_CMDFIFO_AVAIL 0 3 ME0PIPE0_CF_RQ_PENDING 7 7 ME0PIPE0_PF_RQ_PENDING 8 8 GDS_DMA_RQ_PENDING 9 9 DB_CLEAN 12 12 CB_CLEAN 13 13 TA_BUSY 14 14 GDS_BUSY 15 15 GE_BUSY_NO_DMA 16 16 SX_BUSY 20 20 GE_BUSY 21 21 SPI_BUSY 22 22 BCI_BUSY 23 23 SC_BUSY 24 24 PA_BUSY 25 25 DB_BUSY 26 26 CP_COHERENCY_BUSY 28 28 CP_BUSY 29 29 CB_BUSY 30 30 GUI_ACTIVE 31 31 mmGRBM_STATUS_SE0 0 0xda5 14 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 UTCL1_BUSY 3 3 TCP_BUSY 4 4 GL1CC_BUSY 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS_SE1 0 0xda6 14 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 UTCL1_BUSY 3 3 TCP_BUSY 4 4 GL1CC_BUSY 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS3 0 0xda7 15 0 0 GRBM_RLC_INTR_CREDIT_PENDING 5 5 GRBM_UTCL2_INTR_CREDIT_PENDING 6 6 GRBM_CPF_INTR_CREDIT_PENDING 7 7 MESPIPE0_RQ_PENDING 8 8 MESPIPE1_RQ_PENDING 9 9 MESPIPE2_RQ_PENDING 10 10 MESPIPE3_RQ_PENDING 11 11 PH_BUSY 13 13 CH_BUSY 14 14 GL2CC_BUSY 15 15 GL1CC_BUSY 16 16 GUS_LINK_BUSY 28 28 GUS_BUSY 29 29 UTCL1_BUSY 30 30 PMM_BUSY 31 31 mmGRBM_SOFT_RESET 0 0xda8 13 0 0 SOFT_RESET_CP 0 0 SOFT_RESET_RLC 2 2 SOFT_RESET_GFX 16 16 SOFT_RESET_CPF 17 17 SOFT_RESET_CPC 18 18 SOFT_RESET_CPG 19 19 SOFT_RESET_CAC 20 20 SOFT_RESET_CPAXI 21 21 SOFT_RESET_EA 22 22 SOFT_RESET_SDMA0 23 23 SOFT_RESET_SDMA1 24 24 SOFT_RESET_SDMA2 25 25 SOFT_RESET_SDMA3 26 26 mmGRBM_GFX_CLKEN_CNTL 0 0xdac 2 0 0 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmGRBM_WAIT_IDLE_CLOCKS 0 0xdad 1 0 0 WAIT_IDLE_CLOCKS 0 7 mmGRBM_STATUS_SE2 0 0xdae 14 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 UTCL1_BUSY 3 3 TCP_BUSY 4 4 GL1CC_BUSY 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS_SE3 0 0xdaf 14 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 UTCL1_BUSY 3 3 TCP_BUSY 4 4 GL1CC_BUSY 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_READ_ERROR 0 0xdb6 4 0 0 READ_ADDRESS 2 17 READ_PIPEID 20 21 READ_MEID 22 23 READ_ERROR 31 31 mmGRBM_READ_ERROR2 0 0xdb7 22 0 0 READ_REQUESTER_MESPIPE0 9 9 READ_REQUESTER_MESPIPE1 10 10 READ_REQUESTER_MESPIPE2 11 11 READ_REQUESTER_MESPIPE3 12 12 READ_REQUESTER_SDMA0 13 13 READ_REQUESTER_SDMA1 14 14 READ_REQUESTER_SDMA2 15 15 READ_REQUESTER_SDMA3 16 16 READ_REQUESTER_RLC 18 18 READ_REQUESTER_GDS_DMA 19 19 READ_REQUESTER_ME0PIPE0_CF 20 20 READ_REQUESTER_ME0PIPE0_PF 21 21 READ_REQUESTER_ME0PIPE1_CF 22 22 READ_REQUESTER_ME0PIPE1_PF 23 23 READ_REQUESTER_ME1PIPE0 24 24 READ_REQUESTER_ME1PIPE1 25 25 READ_REQUESTER_ME1PIPE2 26 26 READ_REQUESTER_ME1PIPE3 27 27 READ_REQUESTER_ME2PIPE0 28 28 READ_REQUESTER_ME2PIPE1 29 29 READ_REQUESTER_ME2PIPE2 30 30 READ_REQUESTER_ME2PIPE3 31 31 mmGRBM_INT_CNTL 0 0xdb8 2 0 0 RDERR_INT_ENABLE 0 0 GUI_IDLE_INT_ENABLE 19 19 mmGRBM_TRAP_OP 0 0xdb9 1 0 0 RW 0 0 mmGRBM_TRAP_ADDR 0 0xdba 1 0 0 DATA 0 17 mmGRBM_TRAP_ADDR_MSK 0 0xdbb 1 0 0 DATA 0 17 mmGRBM_TRAP_WD 0 0xdbc 1 0 0 DATA 0 31 mmGRBM_TRAP_WD_MSK 0 0xdbd 1 0 0 DATA 0 31 mmGRBM_DSM_BYPASS 0 0xdbe 2 0 0 BYPASS_BITS 0 1 BYPASS_EN 2 2 mmGRBM_WRITE_ERROR 0 0xdbf 9 0 0 WRITE_REQUESTER_RLC 0 0 WRITE_SSRCID 2 4 WRITE_VFID 5 10 WRITE_VF 12 12 WRITE_VMID 13 16 CP_SECURE_WR_ILLEGAL 18 18 WRITE_PIPEID 20 21 WRITE_MEID 22 23 WRITE_ERROR 31 31 mmGRBM_CHIP_REVISION 0 0xdc1 1 0 0 CHIP_REVISION 0 7 mmGRBM_GFX_CNTL 0 0xdc2 4 0 0 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 mmGRBM_IH_CREDIT 0 0xdc4 2 0 0 CREDIT_VALUE 0 1 IH_CLIENT_ID 16 23 mmGRBM_PWR_CNTL2 0 0xdc5 2 0 0 PWR_REQUEST_HALT 16 16 PWR_GFX3D_REQUEST_HALT 20 20 mmGRBM_UTCL2_INVAL_RANGE_START 0 0xdc6 1 0 0 DATA 0 17 mmGRBM_UTCL2_INVAL_RANGE_END 0 0xdc7 1 0 0 DATA 0 17 mmGRBM_FENCE_RANGE0 0 0xdca 2 0 0 START 0 15 END 16 31 mmGRBM_FENCE_RANGE1 0 0xdcb 2 0 0 START 0 15 END 16 31 mmGRBM_NOWHERE 0 0xddf 1 0 0 DATA 0 31 mmGRBM_SCRATCH_REG0 0 0xde0 1 0 0 SCRATCH_REG0 0 31 mmGRBM_SCRATCH_REG1 0 0xde1 1 0 0 SCRATCH_REG1 0 31 mmGRBM_SCRATCH_REG2 0 0xde2 1 0 0 SCRATCH_REG2 0 31 mmGRBM_SCRATCH_REG3 0 0xde3 1 0 0 SCRATCH_REG3 0 31 mmGRBM_SCRATCH_REG4 0 0xde4 1 0 0 SCRATCH_REG4 0 31 mmGRBM_SCRATCH_REG5 0 0xde5 1 0 0 SCRATCH_REG5 0 31 mmGRBM_SCRATCH_REG6 0 0xde6 1 0 0 SCRATCH_REG6 0 31 mmGRBM_SCRATCH_REG7 0 0xde7 1 0 0 SCRATCH_REG7 0 31 mmVIOLATION_DATA_ASYNC_VF_PROG 0 0xdf1 3 0 0 SSRCID 0 3 VFID 4 9 VIOLATION_ERROR 31 31 mmCP_CPC_STATUS 0 0xe24 21 0 0 MEC1_BUSY 0 0 MEC2_BUSY 1 1 DC0_BUSY 2 2 DC1_BUSY 3 3 RCIU1_BUSY 4 4 RCIU2_BUSY 5 5 ROQ1_BUSY 6 6 ROQ2_BUSY 7 7 TCIU_BUSY 10 10 SCRATCH_RAM_BUSY 11 11 QU_BUSY 12 12 UTCL2IU_BUSY 13 13 SAVE_RESTORE_BUSY 14 14 GCRIU_BUSY 15 15 MES_BUSY 16 16 MES_SCRATCH_RAM_BUSY 17 17 RCIU3_BUSY 18 18 MES_INSTRUCTION_CACHE_BUSY 19 19 CPG_CPC_BUSY 29 29 CPF_CPC_BUSY 30 30 CPC_BUSY 31 31 mmCP_CPC_BUSY_STAT 0 0xe25 28 0 0 MEC1_LOAD_BUSY 0 0 MEC1_SEMAPOHRE_BUSY 1 1 MEC1_MUTEX_BUSY 2 2 MEC1_MESSAGE_BUSY 3 3 MEC1_EOP_QUEUE_BUSY 4 4 MEC1_IQ_QUEUE_BUSY 5 5 MEC1_IB_QUEUE_BUSY 6 6 MEC1_TC_BUSY 7 7 MEC1_DMA_BUSY 8 8 MEC1_PARTIAL_FLUSH_BUSY 9 9 MEC1_PIPE0_BUSY 10 10 MEC1_PIPE1_BUSY 11 11 MEC1_PIPE2_BUSY 12 12 MEC1_PIPE3_BUSY 13 13 MEC2_LOAD_BUSY 16 16 MEC2_SEMAPOHRE_BUSY 17 17 MEC2_MUTEX_BUSY 18 18 MEC2_MESSAGE_BUSY 19 19 MEC2_EOP_QUEUE_BUSY 20 20 MEC2_IQ_QUEUE_BUSY 21 21 MEC2_IB_QUEUE_BUSY 22 22 MEC2_TC_BUSY 23 23 MEC2_DMA_BUSY 24 24 MEC2_PARTIAL_FLUSH_BUSY 25 25 MEC2_PIPE0_BUSY 26 26 MEC2_PIPE1_BUSY 27 27 MEC2_PIPE2_BUSY 28 28 MEC2_PIPE3_BUSY 29 29 mmCP_CPC_STALLED_STAT1 0 0xe26 15 0 0 RCIU_TX_FREE_STALL 3 3 RCIU_PRIV_VIOLATION 4 4 TCIU_TX_FREE_STALL 6 6 MEC1_DECODING_PACKET 8 8 MEC1_WAIT_ON_RCIU 9 9 MEC1_WAIT_ON_RCIU_READ 10 10 MEC1_WAIT_ON_ROQ_DATA 13 13 MEC2_DECODING_PACKET 16 16 MEC2_WAIT_ON_RCIU 17 17 MEC2_WAIT_ON_RCIU_READ 18 18 MEC2_WAIT_ON_ROQ_DATA 21 21 UTCL2IU_WAITING_ON_FREE 22 22 UTCL2IU_WAITING_ON_TAGS 23 23 UTCL1_WAITING_ON_TRANS 24 24 GCRIU_WAITING_ON_FREE 25 25 mmCP_CPF_STATUS 0 0xe27 28 0 0 POST_WPTR_GFX_BUSY 0 0 CSF_BUSY 1 1 ROQ_ALIGN_BUSY 4 4 ROQ_RING_BUSY 5 5 ROQ_INDIRECT1_BUSY 6 6 ROQ_INDIRECT2_BUSY 7 7 ROQ_STATE_BUSY 8 8 ROQ_CE_RING_BUSY 9 9 ROQ_CE_INDIRECT1_BUSY 10 10 ROQ_CE_INDIRECT2_BUSY 11 11 SEMAPHORE_BUSY 12 12 INTERRUPT_BUSY 13 13 TCIU_BUSY 14 14 HQD_BUSY 15 15 PRT_BUSY 16 16 UTCL2IU_BUSY 17 17 RCIU_BUSY 18 18 RCIU_GFX_BUSY 19 19 RCIU_CMP_BUSY 20 20 ROQ_DATA_BUSY 21 21 ROQ_CE_DATA_BUSY 22 22 GCRIU_BUSY 23 23 MES_HQD_BUSY 24 24 CPF_GFX_BUSY 26 26 CPF_CMP_BUSY 27 27 GRBM_CPF_STAT_BUSY 28 29 CPC_CPF_BUSY 30 30 CPF_BUSY 31 31 mmCP_CPF_BUSY_STAT 0 0xe28 32 0 0 REG_BUS_FIFO_BUSY 0 0 CSF_RING_BUSY 1 1 CSF_INDIRECT1_BUSY 2 2 CSF_INDIRECT2_BUSY 3 3 CSF_STATE_BUSY 4 4 CSF_CE_INDR1_BUSY 5 5 CSF_CE_INDR2_BUSY 6 6 CSF_ARBITER_BUSY 7 7 CSF_INPUT_BUSY 8 8 CSF_DATA_BUSY 9 9 CSF_CE_DATA_BUSY 10 10 HPD_PROCESSING_EOP_BUSY 11 11 HQD_DISPATCH_BUSY 12 12 HQD_IQ_TIMER_BUSY 13 13 HQD_DMA_OFFLOAD_BUSY 14 14 HQD_WAIT_SEMAPHORE_BUSY 15 15 HQD_SIGNAL_SEMAPHORE_BUSY 16 16 HQD_MESSAGE_BUSY 17 17 HQD_PQ_FETCHER_BUSY 18 18 HQD_IB_FETCHER_BUSY 19 19 HQD_IQ_FETCHER_BUSY 20 20 HQD_EOP_FETCHER_BUSY 21 21 HQD_CONSUMED_RPTR_BUSY 22 22 HQD_FETCHER_ARB_BUSY 23 23 HQD_ROQ_ALIGN_BUSY 24 24 HQD_ROQ_EOP_BUSY 25 25 HQD_ROQ_IQ_BUSY 26 26 HQD_ROQ_PQ_BUSY 27 27 HQD_ROQ_IB_BUSY 28 28 HQD_WPTR_POLL_BUSY 29 29 HQD_PQ_BUSY 30 30 HQD_IB_BUSY 31 31 mmCP_CPF_STALLED_STAT1 0 0xe29 13 0 0 RING_FETCHING_DATA 0 0 INDR1_FETCHING_DATA 1 1 INDR2_FETCHING_DATA 2 2 STATE_FETCHING_DATA 3 3 TCIU_WAITING_ON_FREE 5 5 TCIU_WAITING_ON_TAGS 6 6 UTCL2IU_WAITING_ON_FREE 7 7 UTCL2IU_WAITING_ON_TAGS 8 8 GFX_UTCL1_WAITING_ON_TRANS 9 9 CMP_UTCL1_WAITING_ON_TRANS 10 10 RCIU_WAITING_ON_FREE 11 11 DATA_FETCHING_DATA 12 12 GCRIU_WAIT_ON_FREE 13 13 mmCP_CPC_BUSY_STAT2 0 0xe2a 9 0 0 MES_LOAD_BUSY 0 0 MES_MUTEX_BUSY 2 2 MES_MESSAGE_BUSY 3 3 MES_TC_BUSY 7 7 MES_DMA_BUSY 8 8 MES_PIPE0_BUSY 10 10 MES_PIPE1_BUSY 11 11 MES_PIPE2_BUSY 12 12 MES_PIPE3_BUSY 13 13 mmCP_CPC_GRBM_FREE_COUNT 0 0xe2b 1 0 0 FREE_COUNT 0 5 mmCP_CPC_PRIV_VIOLATION_ADDR 0 0xe2c 1 0 0 PRIV_VIOLATION_ADDR 0 15 mmCP_MEC_ME1_HEADER_DUMP 0 0xe2e 1 0 0 HEADER_DUMP 0 31 mmCP_MEC_ME2_HEADER_DUMP 0 0xe2f 1 0 0 HEADER_DUMP 0 31 mmCP_CPC_SCRATCH_INDEX 0 0xe30 2 0 0 SCRATCH_INDEX 0 8 SCRATCH_INDEX_64BIT_MODE 31 31 mmCP_CPC_SCRATCH_DATA 0 0xe31 1 0 0 SCRATCH_DATA 0 31 mmCP_CPF_GRBM_FREE_COUNT 0 0xe32 1 0 0 FREE_COUNT 0 2 mmCP_CPF_BUSY_STAT2 0 0xe33 9 0 0 MES_HQD_DISPATCH_BUSY 12 12 MES_HQD_DMA_OFFLOAD_BUSY 14 14 MES_HQD_MESSAGE_BUSY 17 17 MES_HQD_PQ_FETCHER_BUSY 18 18 MES_HQD_CONSUMED_RPTR_BUSY 22 22 MES_HQD_FETCHER_ARB_BUSY 23 23 MES_HQD_ROQ_ALIGN_BUSY 24 24 MES_HQD_ROQ_PQ_BUSY 27 27 MES_HQD_PQ_BUSY 30 30 mmCONFIG_RESERVED_REG0 0 0xe34 1 0 0 DATA 0 31 mmCONFIG_RESERVED_REG1 0 0xe35 1 0 0 DATA 0 31 mmCP_CPC_HALT_HYST_COUNT 0 0xe47 1 0 0 COUNT 0 3 mmCP_CE_COMPARE_COUNT 0 0xe60 1 0 0 COMPARE_COUNT 0 31 mmCP_CE_DE_COUNT 0 0xe61 1 0 0 DRAW_ENGINE_COUNT 0 31 mmCP_DE_CE_COUNT 0 0xe62 1 0 0 CONST_ENGINE_COUNT 0 31 mmCP_DE_LAST_INVAL_COUNT 0 0xe63 1 0 0 LAST_INVAL_COUNT 0 31 mmCP_DE_DE_COUNT 0 0xe64 1 0 0 DRAW_ENGINE_COUNT 0 31 mmCP_STALLED_STAT3 0 0xf3c 20 0 0 CE_TO_CSF_NOT_RDY_TO_RCV 0 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV 1 1 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER 2 2 CE_TO_RAM_INIT_NOT_RDY 3 3 CE_TO_RAM_DUMP_NOT_RDY 4 4 CE_TO_RAM_WRITE_NOT_RDY 5 5 CE_TO_INC_FIFO_NOT_RDY_TO_RCV 6 6 CE_TO_WR_FIFO_NOT_RDY_TO_RCV 7 7 CE_WAITING_ON_BUFFER_DATA 10 10 CE_WAITING_ON_CE_BUFFER_FLAG 11 11 CE_WAITING_ON_DE_COUNTER 12 12 CE_WAITING_ON_DE_COUNTER_UNDERFLOW 13 13 TCIU_WAITING_ON_FREE 14 14 TCIU_WAITING_ON_TAGS 15 15 CE_STALLED_ON_TC_WR_CONFIRM 16 16 CE_STALLED_ON_ATOMIC_RTN_DATA 17 17 UTCL2IU_WAITING_ON_FREE 18 18 UTCL2IU_WAITING_ON_TAGS 19 19 UTCL1_WAITING_ON_TRANS 20 20 GCRIU_WAITING_ON_FREE 21 21 mmCP_STALLED_STAT1 0 0xf3d 18 0 0 RBIU_TO_DMA_NOT_RDY_TO_RCV 0 0 RBIU_TO_SEM_NOT_RDY_TO_RCV_R0 2 2 RBIU_TO_SEM_NOT_RDY_TO_RCV_R1 3 3 RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0 4 4 RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1 5 5 ME_HAS_ACTIVE_CE_BUFFER_FLAG 10 10 ME_HAS_ACTIVE_DE_BUFFER_FLAG 11 11 ME_STALLED_ON_TC_WR_CONFIRM 12 12 ME_STALLED_ON_ATOMIC_RTN_DATA 13 13 ME_WAITING_ON_TC_READ_DATA 14 14 ME_WAITING_ON_REG_READ_DATA 15 15 RCIU_WAITING_ON_GDS_FREE 23 23 RCIU_WAITING_ON_GRBM_FREE 24 24 RCIU_WAITING_ON_VGT_FREE 25 25 RCIU_STALLED_ON_ME_READ 26 26 RCIU_STALLED_ON_DMA_READ 27 27 RCIU_STALLED_ON_APPEND_READ 28 28 RCIU_HALTED_BY_REG_VIOLATION 29 29 mmCP_STALLED_STAT2 0 0xf3e 30 0 0 PFP_TO_CSF_NOT_RDY_TO_RCV 0 0 PFP_TO_MEQ_NOT_RDY_TO_RCV 1 1 PFP_TO_RCIU_NOT_RDY_TO_RCV 2 2 PFP_TO_VGT_WRITES_PENDING 4 4 PFP_RCIU_READ_PENDING 5 5 PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV 6 6 PFP_WAITING_ON_BUFFER_DATA 8 8 ME_WAIT_ON_CE_COUNTER 9 9 ME_WAIT_ON_AVAIL_BUFFER 10 10 GFX_CNTX_NOT_AVAIL_TO_ME 11 11 ME_RCIU_NOT_RDY_TO_RCV 12 12 ME_TO_CONST_NOT_RDY_TO_RCV 13 13 ME_WAITING_DATA_FROM_PFP 14 14 ME_WAITING_ON_PARTIAL_FLUSH 15 15 MEQ_TO_ME_NOT_RDY_TO_RCV 16 16 STQ_TO_ME_NOT_RDY_TO_RCV 17 17 ME_WAITING_DATA_FROM_STQ 18 18 PFP_STALLED_ON_TC_WR_CONFIRM 19 19 PFP_STALLED_ON_ATOMIC_RTN_DATA 20 20 QU_STALLED_ON_EOP_DONE_PULSE 21 21 QU_STALLED_ON_EOP_DONE_WR_CONFIRM 22 22 STRMO_WR_OF_PRIM_DATA_PENDING 23 23 PIPE_STATS_WR_DATA_PENDING 24 24 APPEND_RDY_WAIT_ON_CS_DONE 25 25 APPEND_RDY_WAIT_ON_PS_DONE 26 26 APPEND_WAIT_ON_WR_CONFIRM 27 27 APPEND_ACTIVE_PARTITION 28 28 APPEND_WAITING_TO_SEND_MEMWRITE 29 29 SURF_SYNC_NEEDS_IDLE_CNTXS 30 30 SURF_SYNC_NEEDS_ALL_CLEAN 31 31 mmCP_BUSY_STAT 0 0xf3f 16 0 0 REG_BUS_FIFO_BUSY 0 0 COHER_CNT_NEQ_ZERO 6 6 PFP_PARSING_PACKETS 7 7 ME_PARSING_PACKETS 8 8 RCIU_PFP_BUSY 9 9 RCIU_ME_BUSY 10 10 SEM_CMDFIFO_NOT_EMPTY 12 12 SEM_FAILED_AND_HOLDING 13 13 SEM_POLLING_FOR_PASS 14 14 GFX_CONTEXT_BUSY 15 15 ME_PARSER_BUSY 17 17 EOP_DONE_BUSY 18 18 STRM_OUT_BUSY 19 19 PIPE_STATS_BUSY 20 20 RCIU_CE_BUSY 21 21 CE_PARSING_PACKETS 22 22 mmCP_STAT 0 0xf40 25 0 0 ROQ_DB_BUSY 5 5 ROQ_CE_DB_BUSY 6 6 ROQ_RING_BUSY 9 9 ROQ_INDIRECT1_BUSY 10 10 ROQ_INDIRECT2_BUSY 11 11 ROQ_STATE_BUSY 12 12 DC_BUSY 13 13 UTCL2IU_BUSY 14 14 PFP_BUSY 15 15 MEQ_BUSY 16 16 ME_BUSY 17 17 QUERY_BUSY 18 18 SEMAPHORE_BUSY 19 19 INTERRUPT_BUSY 20 20 SURFACE_SYNC_BUSY 21 21 DMA_BUSY 22 22 RCIU_BUSY 23 23 SCRATCH_RAM_BUSY 24 24 GCRIU_BUSY 25 25 CE_BUSY 26 26 TCIU_BUSY 27 27 ROQ_CE_RING_BUSY 28 28 ROQ_CE_INDIRECT1_BUSY 29 29 ROQ_CE_INDIRECT2_BUSY 30 30 CP_BUSY 31 31 mmCP_ME_HEADER_DUMP 0 0xf41 1 0 0 ME_HEADER_DUMP 0 31 mmCP_PFP_HEADER_DUMP 0 0xf42 1 0 0 PFP_HEADER_DUMP 0 31 mmCP_GRBM_FREE_COUNT 0 0xf43 3 0 0 FREE_COUNT 0 5 FREE_COUNT_GDS 8 13 FREE_COUNT_PFP 16 21 mmCP_CE_HEADER_DUMP 0 0xf44 1 0 0 CE_HEADER_DUMP 0 31 mmCP_PFP_INSTR_PNTR 0 0xf45 1 0 0 INSTR_PNTR 0 15 mmCP_ME_INSTR_PNTR 0 0xf46 1 0 0 INSTR_PNTR 0 15 mmCP_CE_INSTR_PNTR 0 0xf47 1 0 0 INSTR_PNTR 0 15 mmCP_MEC1_INSTR_PNTR 0 0xf48 1 0 0 INSTR_PNTR 0 15 mmCP_MEC2_INSTR_PNTR 0 0xf49 1 0 0 INSTR_PNTR 0 15 mmCP_CSF_STAT 0 0xf54 1 0 0 BUFFER_REQUEST_COUNT 8 16 mmCP_MEC_CNTL 0 0xf55 13 0 0 MEC_ME1_PIPE0_RESET 16 16 MEC_ME1_PIPE1_RESET 17 17 MEC_ME1_PIPE2_RESET 18 18 MEC_ME1_PIPE3_RESET 19 19 MEC_ME2_PIPE0_RESET 20 20 MEC_ME2_PIPE1_RESET 21 21 MEC_ME2_PIPE2_RESET 22 22 MEC_ME2_PIPE3_RESET 23 23 MEC_INVALIDATE_ICACHE 27 27 MEC_ME2_HALT 28 28 MEC_ME2_STEP 29 29 MEC_ME1_HALT 30 30 MEC_ME1_STEP 31 31 mmCP_ME_CNTL 0 0xf56 15 0 0 CE_INVALIDATE_ICACHE 4 4 PFP_INVALIDATE_ICACHE 6 6 ME_INVALIDATE_ICACHE 8 8 CE_PIPE0_RESET 16 16 CE_PIPE1_RESET 17 17 PFP_PIPE0_RESET 18 18 PFP_PIPE1_RESET 19 19 ME_PIPE0_RESET 20 20 ME_PIPE1_RESET 21 21 CE_HALT 24 24 CE_STEP 25 25 PFP_HALT 26 26 PFP_STEP 27 27 ME_HALT 28 28 ME_STEP 29 29 mmCP_CNTX_STAT 0 0xf58 4 0 0 ACTIVE_HP3D_CONTEXTS 0 7 CURRENT_HP3D_CONTEXT 8 10 ACTIVE_GFX_CONTEXTS 20 27 CURRENT_GFX_CONTEXT 28 30 mmCP_ME_PREEMPTION 0 0xf59 1 0 0 OBSOLETE 0 0 mmCP_ROQ_THRESHOLDS 0 0xf5c 2 0 0 IB1_START 0 7 IB2_START 8 15 mmCP_MEQ_STQ_THRESHOLD 0 0xf5d 1 0 0 STQ_START 0 7 mmCP_RB2_RPTR 0 0xf5e 1 0 0 RB_RPTR 0 19 mmCP_RB1_RPTR 0 0xf5f 1 0 0 RB_RPTR 0 19 mmCP_RB0_RPTR 0 0xf60 1 0 0 RB_RPTR 0 19 mmCP_RB_RPTR 0 0xf60 1 0 0 RB_RPTR 0 19 mmCP_RB_WPTR_DELAY 0 0xf61 2 0 0 PRE_WRITE_TIMER 0 27 PRE_WRITE_LIMIT 28 31 mmCP_RB_WPTR_POLL_CNTL 0 0xf62 2 0 0 POLL_FREQUENCY 0 15 IDLE_POLL_COUNT 16 31 mmCP_ROQ1_THRESHOLDS 0 0xf75 3 0 0 RB1_START 0 9 R0_IB1_START 10 19 R1_IB1_START 20 29 mmCP_ROQ2_THRESHOLDS 0 0xf76 2 0 0 R0_IB2_START 0 9 R1_IB2_START 10 19 mmCP_STQ_THRESHOLDS 0 0xf77 3 0 0 STQ0_START 0 7 STQ1_START 8 15 STQ2_START 16 23 mmCP_QUEUE_THRESHOLDS 0 0xf78 2 0 0 ROQ_IB1_START 0 5 ROQ_IB2_START 8 13 mmCP_MEQ_THRESHOLDS 0 0xf79 2 0 0 MEQ1_START 0 7 MEQ2_START 8 15 mmCP_ROQ_AVAIL 0 0xf7a 2 0 0 ROQ_CNT_RING 0 11 ROQ_CNT_IB1 16 27 mmCP_STQ_AVAIL 0 0xf7b 1 0 0 STQ_CNT 0 8 mmCP_ROQ2_AVAIL 0 0xf7c 2 0 0 ROQ_CNT_IB2 0 11 ROQ_CNT_DB 16 27 mmCP_MEQ_AVAIL 0 0xf7d 1 0 0 MEQ_CNT 0 9 mmCP_CMD_INDEX 0 0xf7e 3 0 0 CMD_INDEX 0 10 CMD_ME_SEL 12 13 CMD_QUEUE_SEL 16 18 mmCP_CMD_DATA 0 0xf7f 1 0 0 CMD_DATA 0 31 mmCP_ROQ_RB_STAT 0 0xf80 2 0 0 ROQ_RPTR_PRIMARY 0 11 ROQ_WPTR_PRIMARY 16 27 mmCP_ROQ_IB1_STAT 0 0xf81 2 0 0 ROQ_RPTR_INDIRECT1 0 11 ROQ_WPTR_INDIRECT1 16 27 mmCP_ROQ_IB2_STAT 0 0xf82 2 0 0 ROQ_RPTR_INDIRECT2 0 11 ROQ_WPTR_INDIRECT2 16 27 mmCP_STQ_STAT 0 0xf83 1 0 0 STQ_RPTR 0 9 mmCP_STQ_WR_STAT 0 0xf84 1 0 0 STQ_WPTR 0 9 mmCP_MEQ_STAT 0 0xf85 2 0 0 MEQ_RPTR 0 9 MEQ_WPTR 16 25 mmCP_CEQ1_AVAIL 0 0xf86 2 0 0 CEQ_CNT_RING 0 11 CEQ_CNT_IB1 16 27 mmCP_CEQ2_AVAIL 0 0xf87 2 0 0 CEQ_CNT_IB2 0 11 CEQ_CNT_DB 16 27 mmCP_CE_ROQ_RB_STAT 0 0xf88 2 0 0 CEQ_RPTR_PRIMARY 0 11 CEQ_WPTR_PRIMARY 16 27 mmCP_CE_ROQ_IB1_STAT 0 0xf89 2 0 0 CEQ_RPTR_INDIRECT1 0 11 CEQ_WPTR_INDIRECT1 16 27 mmCP_CE_ROQ_IB2_STAT 0 0xf8a 2 0 0 CEQ_RPTR_INDIRECT2 0 11 CEQ_WPTR_INDIRECT2 16 27 mmCP_CE_ROQ_DB_STAT 0 0xf8b 2 0 0 CEQ_RPTR_DB 0 11 CEQ_WPTR_DB 16 27 mmCP_ROQ3_THRESHOLDS 0 0xf8c 2 0 0 R0_DB_START 0 9 R1_DB_START 10 19 mmCP_ROQ_DB_STAT 0 0xf8d 2 0 0 ROQ_RPTR_DB 0 11 ROQ_WPTR_DB 16 27 mmCP_PRIV_VIOLATION_ADDR 0 0xf9a 1 0 0 PRIV_VIOLATION_ADDR 0 15 mmVGT_CACHE_INVALIDATION 0 0xfc0 14 0 0 CACHE_INVALIDATION 0 1 DIS_INSTANCING_OPT 4 4 VS_NO_EXTRA_BUFFER 5 5 AUTO_INVLD_EN 6 7 USE_GS_DONE 9 9 DIS_RANGE_FULL_INVLD 11 11 GS_LATE_ALLOC_EN 12 12 STREAMOUT_FULL_FLUSH 13 13 ES_LIMIT 16 20 ENABLE_PING_PONG 21 21 OPT_FLOW_CNTL_1 22 24 OPT_FLOW_CNTL_2 25 27 EN_WAVE_MERGE 28 28 ENABLE_PING_PONG_EOI 29 29 mmVGT_ESGS_RING_SIZE 0 0xfc1 1 0 0 MEM_SIZE 0 31 mmVGT_GSVS_RING_SIZE 0 0xfc2 1 0 0 MEM_SIZE 0 31 mmVGT_TF_RING_SIZE 0 0xfc3 1 0 0 SIZE 0 15 mmVGT_HS_OFFCHIP_PARAM 0 0xfc4 2 0 0 OFFCHIP_BUFFERING 0 9 OFFCHIP_GRANULARITY 10 11 mmVGT_TF_MEMORY_BASE 0 0xfc5 1 0 0 BASE 0 31 mmVGT_TF_MEMORY_BASE_HI 0 0xfc6 1 0 0 BASE_HI 0 7 mmVGT_VTX_VECT_EJECT_REG 0 0xfcc 1 0 0 PRIM_COUNT 0 9 mmVGT_DMA_DATA_FIFO_DEPTH 0 0xfcd 1 0 0 DMA_DATA_FIFO_DEPTH 0 9 mmVGT_DMA_REQ_FIFO_DEPTH 0 0xfce 1 0 0 DMA_REQ_FIFO_DEPTH 0 5 mmVGT_DRAW_INIT_FIFO_DEPTH 0 0xfcf 1 0 0 DRAW_INIT_FIFO_DEPTH 0 5 mmVGT_LAST_COPY_STATE 0 0xfd0 2 0 0 SRC_STATE_ID 0 2 DST_STATE_ID 16 18 mmVGT_FIFO_DEPTHS 0 0xfd4 5 0 0 VS_DEALLOC_TBL_DEPTH 0 6 RESERVED_0 7 7 CLIPP_FIFO_DEPTH 8 21 RESERVED_1 22 22 HSINPUT_FIFO_DEPTH 23 28 mmVGT_GS_VERTEX_REUSE 0 0xfd5 1 0 0 VERT_REUSE 0 4 mmVGT_MC_LAT_CNTL 0 0xfd6 1 0 0 MC_TIME_STAMP_RES 0 3 mmIA_UTCL1_STATUS_2 0 0xfd7 11 0 0 IA_BUSY 0 0 IA_DMA_BUSY 1 1 IA_DMA_REQ_BUSY 2 2 IA_GRP_BUSY 3 3 IA_ADC_BUSY 4 4 FAULT_DETECTED 5 5 RETRY_DETECTED 6 6 PRT_DETECTED 7 7 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmWD_CNTL_STATUS 0 0xfdf 30 0 0 VR3_BUSY 0 0 VR2_BUSY 1 1 VR1_BUSY 2 2 VR0_BUSY 3 3 HS3_BUSY 4 4 HS2_BUSY 5 5 HS1_BUSY 6 6 HS0_BUSY 7 7 GS3_BUSY 8 8 GS2_BUSY 9 9 GS1_BUSY 10 10 GS0_BUSY 11 11 NGG3_BUSY 12 12 NGG2_BUSY 13 13 NGG1_BUSY 14 14 NGG0_BUSY 15 15 DIST_BUSY 16 16 DIST_BE_BUSY 17 17 WD_TE11_BUSY 18 18 SA3_OUTPUT_BLOCK_BUSY 19 19 SA2_OUTPUT_BLOCK_BUSY 20 20 SA1_OUTPUT_BLOCK_BUSY 21 21 SA0_OUTPUT_BLOCK_BUSY 22 22 GE_UTCL1_BUSY 23 23 TE3_BUSY 24 24 TE2_BUSY 25 25 TE1_BUSY 26 26 TE0_BUSY 27 27 WLC_BUSY 28 28 PC_MANAGER_BUSY 29 29 mmCC_GC_PRIM_CONFIG 0 0xfe0 1 0 0 INACTIVE_PA 4 19 mmGC_USER_PRIM_CONFIG 0 0xfe1 1 0 0 INACTIVE_PA 4 19 mmWD_QOS 0 0xfe2 1 0 0 DRAW_STALL 0 0 mmWD_UTCL1_CNTL 0 0xfe3 9 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 MTYPE_OVERRIDE 29 29 LLC_NOALLOC_OVERRIDE 30 30 mmWD_UTCL1_STATUS 0 0xfe4 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmGE_PC_CNTL 0 0xfe5 3 0 0 PC_SIZE 0 15 NO_RESERVATION_EN 17 17 WAVES_WITH_NO_GRANT 18 21 mmIA_UTCL1_CNTL 0 0xfe6 9 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 MTYPE_OVERRIDE 29 29 LLC_NOALLOC_OVERRIDE 30 30 mmIA_UTCL1_STATUS 0 0xfe7 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmCC_GC_SA_UNIT_DISABLE 0 0xfe9 1 0 0 SA_DISABLE 8 15 mmGC_USER_SA_UNIT_DISABLE 0 0xfea 1 0 0 SA_DISABLE 8 15 mmVGT_SYS_CONFIG 0 0x1003 4 0 0 DUAL_CORE_EN 0 0 MAX_LS_HS_THDGRP 1 6 ADC_EVENT_FILTER_DISABLE 7 7 NUM_SUBGROUPS_IN_FLIGHT 8 18 mmGE_PRIV_CONTROL 0 0x1004 5 0 0 DISCARD_LEGACY 0 0 CLAMP_PRIMGRP_SIZE 1 9 RESET_ON_PIPELINE_CHANGE 10 10 FGCG_OVERRIDE 15 15 CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE 16 16 mmGE_STATUS 0 0x1005 2 0 0 PERFCOUNTER_STATUS 0 0 THREAD_TRACE_STATUS 1 1 mmVGT_VS_MAX_WAVE_ID 0 0x1008 1 0 0 MAX_WAVE_ID 0 11 mmVGT_GS_MAX_WAVE_ID 0 0x1009 1 0 0 MAX_WAVE_ID 0 11 mmCC_GC_SHADER_ARRAY_CONFIG_GEN1 0 0x100a 1 0 0 GEN1_INACTIVE_CU 0 13 mmCC_GC_SHADER_ARRAY_CONFIG_GEN0 0 0x100b 1 0 0 GEN0_INACTIVE_CU 0 13 mmGFX_PIPE_CONTROL 0 0x100d 4 0 0 HYSTERESIS_CNT 0 12 RESERVED 13 15 CONTEXT_SUSPEND_EN 16 16 CONTEXT_SUSPEND_STALL_EN 17 17 mmCC_GC_SHADER_ARRAY_CONFIG 0 0x100f 1 0 0 INACTIVE_WGPS 16 31 mmGC_USER_SHADER_ARRAY_CONFIG 0 0x1010 1 0 0 INACTIVE_WGPS 16 31 mmVGT_DMA_PRIMITIVE_TYPE 0 0x1011 1 0 0 PRIM_TYPE 0 5 mmVGT_DMA_CONTROL 0 0x1012 4 0 0 PRIMGROUP_SIZE 0 15 IA_SWITCH_ON_EOP 17 17 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 mmVGT_DMA_LS_HS_CONFIG 0 0x1013 1 0 0 HS_NUM_INPUT_CP 8 13 mmVGT_STRMOUT_DELAY 0 0x1015 5 0 0 SKIP_DELAY 0 7 SE0_WD_DELAY 8 10 SE1_WD_DELAY 11 13 SE2_WD_DELAY 14 16 SE3_WD_DELAY 17 19 mmWD_BUF_RESOURCE_1 0 0x1016 2 0 0 POS_BUF_SIZE 0 15 INDEX_BUF_SIZE 16 31 mmWD_BUF_RESOURCE_2 0 0x1017 3 0 0 PARAM_BUF_SIZE 0 12 ADDR_MODE 15 15 CNTL_SB_BUF_SIZE 16 31 mmPA_CL_CNTL_STATUS 0 0x1024 4 0 0 UTC_FAULT_DETECTED 0 0 UTC_RETRY_DETECTED 1 1 UTC_PRT_DETECTED 2 2 CL_BUSY 31 31 mmPA_CL_ENHANCE 0 0x1025 22 0 0 CLIP_VTX_REORDER_ENA 0 0 NUM_CLIP_SEQ 1 2 CLIPPED_PRIM_SEQ_STALL 3 3 VE_NAN_PROC_DISABLE 4 4 IGNORE_PIPELINE_RESET 6 6 KILL_INNER_EDGE_FLAGS 7 7 NGG_PA_TO_ALL_SC 8 8 TC_LATENCY_TIME_STAMP_RESOLUTION 9 10 NGG_BYPASS_PRIM_FILTER 11 11 NGG_SIDEBAND_MEMORY_DEPTH 12 13 NGG_PRIM_INDICES_FIFO_DEPTH 14 16 PROG_NEAR_CLIP_PLANE_ENABLE 17 17 OUTPUT_SWITCH_TO_LEGACY_EVENT 18 18 NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET 19 19 POLY_INNER_EDGE_FLAG_DISABLE 20 20 TC_REQUEST_PERF_CNTR_ENABLE 21 21 DISABLE_PA_PH_INTF_FINE_CLOCK_GATE 22 22 CLAMP_NEGATIVE_BB_TO_ZERO 24 24 ECO_SPARE3 28 28 ECO_SPARE2 29 29 ECO_SPARE1 30 30 ECO_SPARE0 31 31 mmPA_SU_CNTL_STATUS 0 0x1034 1 0 0 SU_BUSY 31 31 mmPA_SC_FIFO_DEPTH_CNTL 0 0x1035 1 0 0 DEPTH 0 9 mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0 0x1060 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0 0x1061 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 mmPA_SC_TRAP_SCREEN_HV_LOCK 0 0x1062 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 mmPA_SC_FORCE_EOV_MAX_CNTS 0 0x1069 2 0 0 FORCE_EOV_MAX_CLK_CNT 0 15 FORCE_EOV_MAX_REZ_CNT 16 31 mmPA_SC_BINNER_EVENT_CNTL_0 0 0x106c 16 0 0 RESERVED_0 0 1 SAMPLE_STREAMOUTSTATS1 2 3 SAMPLE_STREAMOUTSTATS2 4 5 SAMPLE_STREAMOUTSTATS3 6 7 CACHE_FLUSH_TS 8 9 CONTEXT_DONE 10 11 CACHE_FLUSH 12 13 CS_PARTIAL_FLUSH 14 15 VGT_STREAMOUT_SYNC 16 17 RESERVED_9 18 19 VGT_STREAMOUT_RESET 20 21 END_OF_PIPE_INCR_DE 22 23 END_OF_PIPE_IB_END 24 25 RST_PIX_CNT 26 27 BREAK_BATCH 28 29 VS_PARTIAL_FLUSH 30 31 mmPA_SC_BINNER_EVENT_CNTL_1 0 0x106d 16 0 0 PS_PARTIAL_FLUSH 0 1 FLUSH_HS_OUTPUT 2 3 FLUSH_DFSM 4 5 RESET_TO_LOWEST_VGT 6 7 CACHE_FLUSH_AND_INV_TS_EVENT 8 9 ZPASS_DONE 10 11 CACHE_FLUSH_AND_INV_EVENT 12 13 PERFCOUNTER_START 14 15 PERFCOUNTER_STOP 16 17 PIPELINESTAT_START 18 19 PIPELINESTAT_STOP 20 21 PERFCOUNTER_SAMPLE 22 23 FLUSH_ES_OUTPUT 24 25 BIN_CONF_OVERRIDE_CHECK 26 27 SAMPLE_PIPELINESTAT 28 29 SO_VGTSTREAMOUT_FLUSH 30 31 mmPA_SC_BINNER_EVENT_CNTL_2 0 0x106e 16 0 0 SAMPLE_STREAMOUTSTATS 0 1 RESET_VTX_CNT 2 3 BLOCK_CONTEXT_DONE 4 5 RESERVED_35 6 7 VGT_FLUSH 8 9 TGID_ROLLOVER 10 11 SQ_NON_EVENT 12 13 SC_SEND_DB_VPZ 14 15 BOTTOM_OF_PIPE_TS 16 17 RESERVED_41 18 19 DB_CACHE_FLUSH_AND_INV 20 21 FLUSH_AND_INV_DB_DATA_TS 22 23 FLUSH_AND_INV_DB_META 24 25 FLUSH_AND_INV_CB_DATA_TS 26 27 FLUSH_AND_INV_CB_META 28 29 CS_DONE 30 31 mmPA_SC_BINNER_EVENT_CNTL_3 0 0x106f 16 0 0 PS_DONE 0 1 FLUSH_AND_INV_CB_PIXEL_DATA 2 3 RESERVED_50 4 5 THREAD_TRACE_START 6 7 THREAD_TRACE_STOP 8 9 THREAD_TRACE_MARKER 10 11 THREAD_TRACE_DRAW 12 13 THREAD_TRACE_FINISH 14 15 PIXEL_PIPE_STAT_CONTROL 16 17 PIXEL_PIPE_STAT_DUMP 18 19 PIXEL_PIPE_STAT_RESET 20 21 CONTEXT_SUSPEND 22 23 OFFCHIP_HS_DEALLOC 24 25 ENABLE_NGG_PIPELINE 26 27 ENABLE_LEGACY_PIPELINE 28 29 DRAW_DONE 30 31 mmPA_SC_BINNER_TIMEOUT_COUNTER 0 0x1070 1 0 0 THRESHOLD 0 31 mmPA_SC_BINNER_PERF_CNTL_0 0 0x1071 4 0 0 BIN_HIST_NUM_PRIMS_THRESHOLD 0 9 BATCH_HIST_NUM_PRIMS_THRESHOLD 10 19 BIN_HIST_NUM_CONTEXT_THRESHOLD 20 22 BATCH_HIST_NUM_CONTEXT_THRESHOLD 23 25 mmPA_SC_BINNER_PERF_CNTL_1 0 0x1072 3 0 0 BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD 0 4 BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD 5 9 BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD 10 25 mmPA_SC_BINNER_PERF_CNTL_2 0 0x1073 2 0 0 BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD 0 10 BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD 11 21 mmPA_SC_BINNER_PERF_CNTL_3 0 0x1074 1 0 0 BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD 0 31 mmPA_SC_ENHANCE_2 0 0x107c 28 0 0 DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE 0 0 DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE 1 1 DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE 2 2 DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE 3 3 ENABLE_LPOV_WAVE_BREAK 4 4 ENABLE_FPOV_WAVE_BREAK 5 5 ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD 7 7 DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH 8 8 DISABLE_FULL_TILE_WAVE_BREAK 9 9 ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS 10 10 PBB_TIMEOUT_THRESHOLD_MODE 11 11 DISABLE_PACKER_GRAD_FDCE_ENHANCE 12 12 DISABLE_SC_SPI_INTF_EARLY_WAKEUP 13 13 DISABLE_SC_BCI_INTF_EARLY_WAKEUP 14 14 DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ 15 15 PBB_WARP_CLK_MAIN_CLK_WAKEUP 16 16 PBB_MAIN_CLK_REG_BUSY_WAKEUP 17 17 DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET 18 18 ENABLE_BLOCKING_WRITES_OF_GEN1_REG 19 19 ENABLE_BLOCKING_WRITES_OF_GEN2_REG 20 20 DISABLE_SC_DBR_DATAPATH_FGCG 21 21 PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO 23 23 DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE 24 24 DISABLE_DFSM_FLUSH 25 25 BREAK_WHEN_ONE_NULL_PRIM_BATCH 26 26 NULL_PRIM_BREAK_BATCH_LIMIT 27 29 DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT 30 30 RSVD 31 31 mmPA_SC_ENHANCE_INTERNAL 0 0x107d 0 0 0 mmPA_SC_BINNER_CNTL_OVERRIDE 0 0x107e 6 0 0 BINNING_MODE 0 1 CONTEXT_STATES_PER_BIN 10 12 PERSISTENT_STATES_PER_BIN 13 17 FPOVS_PER_BATCH 19 26 DIRECT_OVERRIDE_MODE 27 27 OVERRIDE 28 31 mmPA_SC_PBB_OVERRIDE_FLAG 0 0x107f 2 0 0 OVERRIDE 0 0 PIPE_ID 1 1 mmPA_PH_INTERFACE_FIFO_SIZE 0 0x1080 2 0 0 PA_PH_IF_FIFO_SIZE 0 9 PH_SC_IF_FIFO_SIZE 16 21 mmPA_PH_ENHANCE 0 0x1081 11 0 0 ECO_SPARE0 0 0 ECO_SPARE1 1 1 ECO_SPARE2 2 2 ECO_SPARE3 3 3 DISABLE_PH_SC_INTF_FINE_CLOCK_GATE 4 4 DISABLE_FOPKT 5 5 DISABLE_FOPKT_SCAN_POST_RESET 6 6 DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE 7 7 DISABLE_PH_PERF_REG_FGCG 9 9 ENABLE_PH_INTF_CLKEN_STRETCH 10 12 DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT 13 13 mmPA_SC_BC_WAVE_BREAK 0 0x1084 2 0 0 MAX_DEALLOCS_IN_WAVE 0 10 MAX_FPOVS_IN_WAVE 16 23 mmPA_SC_ENHANCE_3 0 0x1085 6 0 0 FORCE_USE_OF_SC_CENTROID_DATA 0 0 DISABLE_RB_MASK_COPY_FOR_NONP2_SA_HARVEST 2 2 FORCE_PBB_WORKLOAD_MODE_TO_ZERO 3 3 DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION 4 4 DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN 5 5 RSVD 6 31 mmPA_SC_FIFO_SIZE 0 0x1093 4 0 0 SC_FRONTEND_PRIM_FIFO_SIZE 0 5 SC_BACKEND_PRIM_FIFO_SIZE 6 14 SC_HIZ_TILE_FIFO_SIZE 15 20 SC_EARLYZ_TILE_FIFO_SIZE 21 31 mmPA_SC_IF_FIFO_SIZE 0 0x1095 4 0 0 SC_DB_TILE_IF_FIFO_SIZE 0 5 SC_DB_QUAD_IF_FIFO_SIZE 6 11 SC_SPI_IF_FIFO_SIZE 12 17 SC_BCI_IF_FIFO_SIZE 18 23 mmPA_SC_PKR_WAVE_TABLE_CNTL 0 0x1098 1 0 0 SIZE 0 5 mmPA_SIDEBAND_REQUEST_DELAYS 0 0x109b 2 0 0 RETRY_DELAY 0 15 INITIAL_DELAY 16 31 mmPA_SC_ENHANCE 0 0x109c 30 0 0 ENABLE_PA_SC_OUT_OF_ORDER 0 0 DISABLE_SC_DB_TILE_FIX 1 1 DISABLE_AA_MASK_FULL_FIX 2 2 ENABLE_1XMSAA_SAMPLE_LOCATIONS 3 3 ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 4 4 DISABLE_SCISSOR_FIX 5 5 SEND_UNLIT_STILES_TO_PACKER 6 6 DISABLE_DUALGRAD_PERF_OPTIMIZATION 7 7 DISABLE_SC_PROCESS_RESET_PRIM 8 8 DISABLE_SC_PROCESS_RESET_SUPERTILE 9 9 DISABLE_SC_PROCESS_RESET_TILE 10 10 DISABLE_PA_SC_GUIDANCE 11 11 DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS 12 12 ENABLE_MULTICYCLE_BUBBLE_FREEZE 13 13 DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE 14 14 ENABLE_OUT_OF_ORDER_POLY_MODE 15 15 DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST 16 16 DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING 17 17 ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY 18 18 DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING 19 19 DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING 20 20 DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS 21 21 ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID 22 22 DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO 23 23 OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT 24 24 OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING 25 25 DISABLE_EOP_LINE_STIPPLE_RESET 26 26 DISABLE_VPZ_EOP_LINE_STIPPLE_RESET 27 27 IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE 28 28 OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING 29 29 mmPA_SC_ENHANCE_1 0 0x109d 27 0 0 REALIGN_DQUADS_OVERRIDE_ENABLE 0 0 REALIGN_DQUADS_OVERRIDE 1 2 DISABLE_SC_BINNING 3 3 BYPASS_PBB 4 4 ECO_SPARE0 5 5 ECO_SPARE1 6 6 ECO_SPARE2 7 7 ECO_SPARE3 8 8 DISABLE_SC_PROCESS_RESET_PBB 9 9 DISABLE_PBB_SCISSOR_OPT 10 10 ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM 11 11 DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE 14 14 DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION 15 15 DISABLE_PACKER_ODC_ENHANCE 16 16 OPTIMAL_BIN_SELECTION 18 18 DISABLE_FORCE_SOP_ALL_EVENTS 19 19 DISABLE_PBB_CLK_OPTIMIZATION 20 20 DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION 21 21 DISABLE_PBB_BINNING_CLK_OPTIMIZATION 22 22 DISABLE_INTF_CG 23 23 IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT 24 24 DISABLE_SHADER_PROFILING_FOR_POWER 25 25 FLUSH_ON_BINNING_TRANSITION 26 26 DISABLE_QUAD_PROC_FDCE_ENHANCE 27 27 DISABLE_SC_PS_PA_ARBITER_FIX 28 28 DISABLE_SC_PS_PA_ARBITER_FIX_1 29 29 PASS_VPZ_EVENT_TO_SPI 30 30 mmPA_SC_DSM_CNTL 0 0x109e 2 0 0 FORCE_EOV_REZ_0 0 0 FORCE_EOV_REZ_1 1 1 mmPA_SC_TILE_STEERING_CREST_OVERRIDE 0 0x109f 5 0 0 ONE_RB_MODE_ENABLE 0 0 SE_SELECT 1 2 RB_SELECT 5 6 SA_SELECT 8 10 FORCE_TILE_STEERING_OVERRIDE_USE 31 31 mmSQ_CONFIG 0 0x10a0 12 0 0 UNUSED 0 4 CHICKEN_BIT_DEGGIGXX0_8637 0 0 UNUSED_6 0 0 DISABLE_SGPR_RD_KILL 0 0 VGPR_SWIZZLE_EN 12 12 LDS_BUSY_HYSTERESIS_CNT 13 14 SP_BUSY_HYSTERESIS_CNT 15 16 ENABLE_HIPRIO_ON_EXP_RDY_VS 18 18 PRIO_VAL_ON_EXP_RDY_VS 19 20 WCLK_HYSTERESIS_CNT 0 0 DISABLE_SP_REDUNDANT_THREAD_GATING 29 29 TA_BUSY_HYSTERESIS_CNT 30 31 mmSQC_CONFIG 0 0x10a1 11 0 0 INST_CACHE_SIZE 0 1 DATA_CACHE_SIZE 2 3 MISS_FIFO_DEPTH 4 5 HIT_FIFO_DEPTH 6 6 FORCE_ALWAYS_MISS 7 7 FORCE_IN_ORDER 8 8 PER_VMID_INV_DISABLE 11 11 EVICT_LRU 12 13 FORCE_2_BANK 14 14 FORCE_1_BANK 15 15 LS_DISABLE_CLOCKS 16 23 mmLDS_CONFIG 0 0x10a2 9 0 0 ADDR_OUT_OF_RANGE_REPORTING 0 0 VGPR_SWIZZLE_EN 1 1 WAVE32_INTERP_DUAL_ISSUE_DISABLE 2 2 SP_TDDATA_FGCG_OVERRIDE 3 3 SQC_PERF_FGCG_OVERRIDE 4 4 CONF_BIT_5 5 5 CONF_BIT_6 6 6 CONF_BIT_7 7 7 CONF_BIT_8 8 8 mmSQ_RANDOM_WAVE_PRI 0 0x10a3 4 0 0 RET 0 6 RUI 7 9 RNG 10 23 FORCE_IB_ARB_PRIO_MSK_VALID 31 31 mmSQG_STATUS 0 0x10a4 1 0 0 REG_BUSY 0 0 mmSQ_FIFO_SIZES 0 0x10a5 6 0 0 INTERRUPT_FIFO_SIZE 0 3 TTRACE_FIFO_SIZE 8 9 EXPORT_BUF_VS_RESERVED 12 13 EXPORT_BUF_PS_RESERVED 14 15 EXPORT_BUF_REDUCE 16 17 VMEM_DATA_FIFO_SIZE 18 19 mmSQ_DSM_CNTL 0 0x10a6 16 0 0 WAVEFRONT_STALL_0 0 0 WAVEFRONT_STALL_1 1 1 SPI_BACKPRESSURE_0 2 2 SPI_BACKPRESSURE_1 3 3 SEL_DSM_SGPR_IRRITATOR_DATA0 8 8 SEL_DSM_SGPR_IRRITATOR_DATA1 9 9 SGPR_ENABLE_SINGLE_WRITE 10 10 SEL_DSM_LDS_IRRITATOR_DATA0 16 16 SEL_DSM_LDS_IRRITATOR_DATA1 17 17 LDS_ENABLE_SINGLE_WRITE01 18 18 SEL_DSM_LDS_IRRITATOR_DATA2 19 19 SEL_DSM_LDS_IRRITATOR_DATA3 20 20 LDS_ENABLE_SINGLE_WRITE23 21 21 SEL_DSM_SP_IRRITATOR_DATA0 24 24 SEL_DSM_SP_IRRITATOR_DATA1 25 25 SP_ENABLE_SINGLE_WRITE 26 26 mmSQ_DSM_CNTL2 0 0x10a7 11 0 0 SGPR_ENABLE_ERROR_INJECT 0 1 SGPR_SELECT_INJECT_DELAY 2 2 LDS_D_ENABLE_ERROR_INJECT 3 4 LDS_D_SELECT_INJECT_DELAY 5 5 LDS_I_ENABLE_ERROR_INJECT 6 7 LDS_I_SELECT_INJECT_DELAY 8 8 SP_ENABLE_ERROR_INJECT 9 10 SP_SELECT_INJECT_DELAY 11 11 LDS_INJECT_DELAY 14 19 SP_INJECT_DELAY 20 25 SQ_INJECT_DELAY 26 31 mmSQ_RUNTIME_CONFIG 0 0x10a8 1 0 0 UNUSED_REGISTER 0 0 mmSH_MEM_BASES 0 0x10aa 2 0 0 PRIVATE_BASE 0 15 SHARED_BASE 16 31 mmSP_CONFIG 0 0x10ab 5 0 0 DEST_CACHE_EVICT_COUNTER 0 1 ALU_BUSY_MGCG_OVERRIDE 2 2 DISABLE_TRANS_COEXEC 3 3 CAC_COUNTER_OVERRIDE 4 4 SP_SX_EXPVDATA_FGCG_OVERRIDE 5 5 mmSQ_ARB_CONFIG 0 0x10ac 2 0 0 WG_RR_INTERVAL 0 1 FWD_PROG_INTERVAL 4 5 mmSH_MEM_CONFIG 0 0x10ad 5 0 0 ADDRESS_MODE 0 0 ALIGNMENT_MODE 2 3 DEFAULT_MTYPE 4 6 INITIAL_INST_PREFETCH 14 15 ICACHE_USE_GL1 18 18 mmSQ_SHADER_TBA_LO 0 0x10b2 1 0 0 ADDR_LO 0 31 mmSQ_SHADER_TBA_HI 0 0x10b3 2 0 0 ADDR_HI 0 7 TRAP_EN 31 31 mmSQ_SHADER_TMA_LO 0 0x10b4 1 0 0 ADDR_LO 0 31 mmSQ_SHADER_TMA_HI 0 0x10b5 1 0 0 ADDR_HI 0 7 mmSQG_UTCL0_CNTL1 0 0x10b7 17 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 RESERVED 16 16 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 mmSQG_UTCL0_CNTL2 0 0x10b8 20 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 ARB_BURST_MODE 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 DIS_DUAL_L2_REQ 25 25 FORCE_FRAG_2M_TO_64K 26 26 PERM_MODE_OVRD 27 27 LINE_INVALIDATE_OPT 28 28 GPUVM_16K_DEF 29 29 RESERVED 30 31 mmSQG_UTCL0_STATUS 0 0x10b9 5 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 RESERVED 3 7 UNUSED 8 31 mmSQG_CONFIG 0 0x10ba 2 0 0 UTCL0_PREFETCH_PAGE 0 3 UTCL0_RETRY_TIMER 4 10 mmCC_GC_SHADER_RATE_CONFIG 0 0x10bc 2 0 0 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 mmGC_USER_SHADER_RATE_CONFIG 0 0x10bd 2 0 0 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 mmSQ_INTERRUPT_AUTO_MASK 0 0x10be 1 0 0 MASK 0 23 mmSQ_INTERRUPT_MSG_CTRL 0 0x10bf 1 0 0 STALL 0 0 mmSQ_WATCH0_ADDR_H 0 0x10d0 1 0 0 ADDR 0 15 mmSQ_WATCH0_ADDR_L 0 0x10d1 1 0 0 ADDR 6 31 mmSQ_WATCH0_CNTL 0 0x10d2 3 0 0 MASK 0 23 VMID 24 27 VALID 31 31 mmSQ_WATCH1_ADDR_H 0 0x10d3 1 0 0 ADDR 0 15 mmSQ_WATCH1_ADDR_L 0 0x10d4 1 0 0 ADDR 6 31 mmSQ_WATCH1_CNTL 0 0x10d5 3 0 0 MASK 0 23 VMID 24 27 VALID 31 31 mmSQ_WATCH2_ADDR_H 0 0x10d6 1 0 0 ADDR 0 15 mmSQ_WATCH2_ADDR_L 0 0x10d7 1 0 0 ADDR 6 31 mmSQ_WATCH2_CNTL 0 0x10d8 3 0 0 MASK 0 23 VMID 24 27 VALID 31 31 mmSQ_WATCH3_ADDR_H 0 0x10d9 1 0 0 ADDR 0 15 mmSQ_WATCH3_ADDR_L 0 0x10da 1 0 0 ADDR 6 31 mmSQ_WATCH3_CNTL 0 0x10db 3 0 0 MASK 0 23 VMID 24 27 VALID 31 31 mmSQ_THREAD_TRACE_BUF0_BASE 0 0x10e0 1 0 0 BASE_LO 0 31 mmSQ_THREAD_TRACE_BUF0_SIZE 0 0x10e1 2 0 0 BASE_HI 0 3 SIZE 8 29 mmSQ_THREAD_TRACE_BUF1_BASE 0 0x10e2 1 0 0 BASE_LO 0 31 mmSQ_THREAD_TRACE_BUF1_SIZE 0 0x10e3 2 0 0 BASE_HI 0 3 SIZE 8 29 mmSQ_THREAD_TRACE_WPTR 0 0x10e4 2 0 0 OFFSET 0 28 BUFFER_ID 31 31 mmSQ_THREAD_TRACE_MASK 0 0x10e5 4 0 0 SIMD_SEL 0 1 WGP_SEL 4 7 SA_SEL 9 9 WTYPE_INCLUDE 10 16 mmSQ_THREAD_TRACE_TOKEN_MASK 0 0x10e6 6 0 0 TOKEN_EXCLUDE 0 10 BOP_EVENTS_TOKEN_INCLUDE 12 12 REG_INCLUDE 16 23 INST_EXCLUDE 24 25 REG_EXCLUDE 26 28 REG_DETAIL_ALL 31 31 mmSQ_THREAD_TRACE_CTRL 0 0x10e7 20 0 0 MODE 0 1 ALL_VMID 2 2 CH_PERF_EN 3 3 INTERRUPT_EN 4 4 DOUBLE_BUFFER 5 5 HIWATER 6 8 REG_STALL_EN 9 9 SPI_STALL_EN 10 10 SQ_STALL_EN 11 11 REG_DROP_ON_STALL 12 12 UTIL_TIMER 13 13 WAVESTART_MODE 14 15 RT_FREQ 16 17 SYNC_COUNT_MARKERS 18 18 SYNC_COUNT_DRAWS 19 19 LOWATER_OFFSET 20 22 AUTO_FLUSH_PADDING_DIS 28 28 AUTO_FLUSH_MODE 29 29 CAPTURE_ALL 30 30 DRAW_EVENT_EN 31 31 mmSQ_THREAD_TRACE_STATUS 0 0x10e8 7 0 0 FINISH_PENDING 0 11 FINISH_DONE 12 23 UTC_ERR 24 24 BUSY 25 25 EVENT_CNTR_OVERFLOW 26 26 EVENT_CNTR_STALL 27 27 OWNER_VMID 28 31 mmSQ_THREAD_TRACE_DROPPED_CNTR 0 0x10e9 1 0 0 CNTR 0 31 mmSQ_THREAD_TRACE_GFX_DRAW_CNTR 0 0x10eb 1 0 0 CNTR 0 31 mmSQ_THREAD_TRACE_GFX_MARKER_CNTR 0 0x10ec 1 0 0 CNTR 0 31 mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0 0x10ed 1 0 0 CNTR 0 31 mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0 0x10ee 1 0 0 CNTR 0 31 mmSQ_THREAD_TRACE_STATUS2 0 0x10ef 3 0 0 BUF0_FULL 0 0 BUF1_FULL 1 1 PACKET_LOST_BUF_NO_LOCKDOWN 4 4 mmSQ_IND_INDEX 0 0x1118 4 0 0 WAVE_ID 0 4 WORKITEM_ID 5 10 AUTO_INCR 11 11 INDEX 16 31 mmSQ_IND_DATA 0 0x1119 1 0 0 DATA 0 31 mmSQ_CMD 0 0x111b 7 0 0 CMD 0 3 MODE 4 6 CHECK_VMID 7 7 DATA 8 11 WAVE_ID 16 20 QUEUE_ID 24 26 VM_ID 28 31 mmSQ_TIME_HI 0 0x111c 1 0 0 TIME 0 31 mmSQ_TIME_LO 0 0x111d 1 0 0 TIME 0 31 mmSQ_LB_CTR_CTRL 0 0x1138 3 0 0 START 0 0 LOAD 1 1 CLEAR 2 2 mmSQ_LB_DATA0 0 0x1139 1 0 0 DATA 0 31 mmSQ_LB_DATA1 0 0x113a 1 0 0 DATA 0 31 mmSQ_LB_DATA2 0 0x113b 1 0 0 DATA 0 31 mmSQ_LB_DATA3 0 0x113c 1 0 0 DATA 0 31 mmSQ_LB_CTR_SEL0 0 0x113d 4 0 0 SEL0 0 7 DIV0 15 15 SEL1 16 23 DIV1 31 31 mmSQ_LB_CTR_SEL1 0 0x113e 4 0 0 SEL2 0 7 DIV2 15 15 SEL3 16 23 DIV3 31 31 mmSQ_EDC_CNT 0 0x1146 14 0 0 LDS_D_SEC_COUNT 0 1 LDS_D_DED_COUNT 2 3 LDS_I_SEC_COUNT 4 5 LDS_I_DED_COUNT 6 7 SGPR_SEC_COUNT 8 9 SGPR_DED_COUNT 10 11 VGPR0_SEC_COUNT 12 13 VGPR0_DED_COUNT 14 15 VGPR1_SEC_COUNT 16 17 VGPR1_DED_COUNT 18 19 VGPR2_SEC_COUNT 20 21 VGPR2_DED_COUNT 22 23 VGPR3_SEC_COUNT 24 25 VGPR3_DED_COUNT 26 27 mmSQ_EDC_FUE_CNTL 0 0x1147 2 0 0 BLOCK_FUE_FLAGS 0 15 FUE_INTERRUPT_ENABLES 16 31 mmSQ_WREXEC_EXEC_HI 0 0x1151 4 0 0 ADDR_HI 0 15 FIRST_WAVE 26 26 MTYPE 28 30 MSB 31 31 mmSQ_WREXEC_EXEC_LO 0 0x1151 1 0 0 ADDR_LO 0 31 mmSQC_ICACHE_UTCL0_CNTL1 0 0x1173 16 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 mmSQC_ICACHE_UTCL0_CNTL2 0 0x1174 19 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 ARB_BURST_MODE 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 FORCE_FRAG_2M_TO_64K 26 26 PERM_MODE_OVRD 27 27 LINE_INVALIDATE_OPT 28 28 GPUVM_16K_DEF 29 29 FGCG_DISABLE 30 30 mmSQC_DCACHE_UTCL0_CNTL1 0 0x1175 16 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 mmSQC_DCACHE_UTCL0_CNTL2 0 0x1176 19 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 ARB_BURST_MODE 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 FORCE_FRAG_2M_TO_64K 26 26 PERM_MODE_OVRD 27 27 LINE_INVALIDATE_OPT 28 28 GPUVM_16K_DEF 29 29 FGCG_DISABLE 30 30 mmSQC_ICACHE_UTCL0_STATUS 0 0x1177 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 mmSQC_DCACHE_UTCL0_STATUS 0 0x1178 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 mmSX_DEBUG_1 0 0x11b8 17 0 0 SX_DB_QUAD_CREDIT 0 6 DISABLE_BLEND_OPT_DONT_RD_DST 8 8 DISABLE_BLEND_OPT_BYPASS 9 9 DISABLE_BLEND_OPT_DISCARD_PIXEL 10 10 DISABLE_QUAD_PAIR_OPT 11 11 DISABLE_PIX_EN_ZERO_OPT 12 12 DISABLE_REP_FGCG 13 13 ENABLE_SAME_PC_GDS_CGTS 14 14 DISABLE_RAM_FGCG 15 15 PC_DISABLE_SAME_ADDR_OPT 16 16 DISABLE_COL_VAL_READ_OPT 17 17 DISABLE_BC_RB_PLUS 18 18 DISABLE_NATIVE_DOWNCVT_FMT_MAPPING 19 19 DISABLE_SCBD_READ_PWR_OPT 20 20 DISABLE_GDS_CGTS_OPT 21 21 DISABLE_DOWNCVT_PWR_OPT 22 22 DEBUG_DATA 23 31 mmSPI_PS_MAX_WAVE_ID 0 0x11da 2 0 0 MAX_WAVE_ID 0 11 MAX_COLLISION_WAVE_ID 16 25 mmSPI_START_PHASE 0 0x11db 4 0 0 PC_X_PHASE_SE0 0 1 PC_X_PHASE_SE1 2 3 PC_X_PHASE_SE2 4 5 PC_X_PHASE_SE3 6 7 mmSPI_GFX_CNTL 0 0x11dc 1 0 0 RESET_COUNTS 0 0 mmSPI_DSM_CNTL 0 0x11e3 2 0 0 SPI_SR_MEM_DSM_IRRITATOR_DATA 0 1 SPI_SR_MEM_ENABLE_SINGLE_WRITE 2 2 mmSPI_DSM_CNTL2 0 0x11e4 3 0 0 SPI_SR_MEM_ENABLE_ERROR_INJECT 0 1 SPI_SR_MEM_SELECT_INJECT_DELAY 2 2 SPI_SR_MEM_INJECT_DELAY 3 8 mmSPI_EDC_CNT 0 0x11e5 1 0 0 SPI_SR_MEM_SED_COUNT 0 1 mmSPI_USER_ACCUM_VMID_CNTL 0 0x11eb 1 0 0 EN_USER_ACCUM 0 3 mmSPI_CONFIG_CNTL 0 0x11ec 9 0 0 GPR_WRITE_PRIORITY 0 20 EXP_PRIORITY_ORDER 21 23 ENABLE_SQG_TOP_EVENTS 24 24 ENABLE_SQG_BOP_EVENTS 25 25 FORCE_HALF_RATE_PC_EXP 26 26 TTRACE_STALL_ALL 27 27 ALLOC_ARB_LRU_ENA 28 28 EXP_ARB_LRU_ENA 29 29 PS_PKR_PRIORITY_CNTL 30 31 mmSPI_WAVE_LIMIT_CNTL 0 0x11ed 4 0 0 PS_WAVE_GRAN 0 1 VS_WAVE_GRAN 2 3 GS_WAVE_GRAN 4 5 HS_WAVE_GRAN 6 7 mmSPI_CONFIG_CNTL_2 0 0x11ee 2 0 0 CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD 0 3 CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD 4 7 mmSPI_CONFIG_CNTL_1 0 0x11ef 13 0 0 VTX_DONE_DELAY 0 3 INTERP_ONE_PRIM_PER_ROW 4 4 PC_LIMIT_ENABLE 5 6 PC_LIMIT_STRICT 7 7 CRC_SIMD_ID_WADDR_DISABLE 8 8 LBPW_CU_CHK_MODE 9 9 LBPW_CU_CHK_CNT 10 13 CSC_PWR_SAVE_DISABLE 14 14 CSG_PWR_SAVE_DISABLE 15 15 MAX_VTX_SYNC_CNT 16 20 EN_USER_ACCUM 21 21 SA_SCREEN_MAP 22 22 RESERVED 23 31 mmSPI_CONFIG_PS_CU_EN 0 0x11f2 1 0 0 PKR_OFFSET 0 3 mmSPI_WF_LIFETIME_CNTL 0 0x124a 2 0 0 SAMPLE_PERIOD 0 3 EN 4 4 mmSPI_WF_LIFETIME_LIMIT_0 0 0x124b 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_1 0 0x124c 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_2 0 0x124d 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_3 0 0x124e 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_4 0 0x124f 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_5 0 0x1250 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_STATUS_0 0 0x1255 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_1 0 0x1256 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_2 0 0x1257 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_4 0 0x1259 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_6 0 0x125b 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_7 0 0x125c 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_8 0 0x125d 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_9 0 0x125e 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_11 0 0x1260 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_13 0 0x1262 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_14 0 0x1263 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_15 0 0x1264 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_16 0 0x1265 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_17 0 0x1266 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_18 0 0x1267 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_19 0 0x1268 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_20 0 0x1269 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_21 0 0x126b 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_LB_CTR_CTRL 0 0x1274 4 0 0 LOAD 0 0 WAVES_SELECT 1 2 CLEAR_ON_READ 3 3 RESET_COUNTS 4 4 mmSPI_LB_WGP_MASK 0 0x1275 1 0 0 WGP_MASK 0 15 mmSPI_LB_DATA_REG 0 0x1276 1 0 0 CNT_DATA 0 31 mmSPI_PG_ENABLE_STATIC_WGP_MASK 0 0x1277 1 0 0 WGP_MASK 0 15 mmSPI_GDS_CREDITS 0 0x1278 2 0 0 DS_DATA_CREDITS 0 7 DS_CMD_CREDITS 8 15 mmSPI_SX_EXPORT_BUFFER_SIZES 0 0x1279 2 0 0 COLOR_BUFFER_SIZE 0 15 POSITION_BUFFER_SIZE 16 31 mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0 0x127a 2 0 0 COLOR_SCOREBOARD_SIZE 0 15 POSITION_SCOREBOARD_SIZE 16 31 mmSPI_CSQ_WF_ACTIVE_STATUS 0 0x127b 1 0 0 ACTIVE 0 31 mmSPI_CSQ_WF_ACTIVE_COUNT_0 0 0x127c 2 0 0 COUNT 0 10 EVENTS 16 26 mmSPI_CSQ_WF_ACTIVE_COUNT_1 0 0x127d 2 0 0 COUNT 0 10 EVENTS 16 26 mmSPI_CSQ_WF_ACTIVE_COUNT_2 0 0x127e 2 0 0 COUNT 0 10 EVENTS 16 26 mmSPI_CSQ_WF_ACTIVE_COUNT_3 0 0x127f 2 0 0 COUNT 0 10 EVENTS 16 26 mmSPI_LB_DATA_WAVES 0 0x1284 2 0 0 COUNT0 0 15 COUNT1 16 31 mmSPI_LB_DATA_PERWGP_WAVE_HSGS 0 0x1285 2 0 0 WGP_USED_HS 0 15 WGP_USED_GS 16 31 mmSPI_LB_DATA_PERWGP_WAVE_VSPS 0 0x1286 2 0 0 WGP_USED_VS 0 15 WGP_USED_PS 16 31 mmSPI_LB_DATA_PERWGP_WAVE_CS 0 0x1287 1 0 0 ACTIVE 0 15 mmSPI_P0_TRAP_SCREEN_PSBA_LO 0 0x128c 1 0 0 MEM_BASE 0 31 mmSPI_P0_TRAP_SCREEN_PSBA_HI 0 0x128d 1 0 0 MEM_BASE 0 7 mmSPI_P0_TRAP_SCREEN_PSMA_LO 0 0x128e 1 0 0 MEM_BASE 0 31 mmSPI_P0_TRAP_SCREEN_PSMA_HI 0 0x128f 1 0 0 MEM_BASE 0 7 mmSPI_P0_TRAP_SCREEN_GPR_MIN 0 0x1290 2 0 0 VGPR_MIN 0 5 SGPR_MIN 6 9 mmSPI_P1_TRAP_SCREEN_PSBA_LO 0 0x1291 1 0 0 MEM_BASE 0 31 mmSPI_P1_TRAP_SCREEN_PSBA_HI 0 0x1292 1 0 0 MEM_BASE 0 7 mmSPI_P1_TRAP_SCREEN_PSMA_LO 0 0x1293 1 0 0 MEM_BASE 0 31 mmSPI_P1_TRAP_SCREEN_PSMA_HI 0 0x1294 1 0 0 MEM_BASE 0 7 mmSPI_P1_TRAP_SCREEN_GPR_MIN 0 0x1295 2 0 0 VGPR_MIN 0 5 SGPR_MIN 6 9 mmTD_STATUS 0 0x12c6 1 0 0 BUSY 31 31 mmTD_DSM_CNTL 0 0x12cf 6 0 0 TD_SS_FIFO_LO_DSM_IRRITATOR_DATA 0 1 TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE 2 2 TD_SS_FIFO_HI_DSM_IRRITATOR_DATA 3 4 TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE 5 5 TD_CS_FIFO_DSM_IRRITATOR_DATA 6 7 TD_CS_FIFO_ENABLE_SINGLE_WRITE 8 8 mmTD_DSM_CNTL2 0 0x12d0 7 0 0 TD_SS_FIFO_LO_ENABLE_ERROR_INJECT 0 1 TD_SS_FIFO_LO_SELECT_INJECT_DELAY 2 2 TD_SS_FIFO_HI_ENABLE_ERROR_INJECT 3 4 TD_SS_FIFO_HI_SELECT_INJECT_DELAY 5 5 TD_CS_FIFO_ENABLE_ERROR_INJECT 6 7 TD_CS_FIFO_SELECT_INJECT_DELAY 8 8 TD_INJECT_DELAY 26 31 mmTD_SCRATCH 0 0x12d3 1 0 0 SCRATCH 0 31 mmTA_CNTL 0 0x12e1 2 0 0 ALIGNER_CREDIT 16 20 TD_FIFO_CREDIT 22 31 mmTA_RESERVED_010C 0 0x12e3 1 0 0 Unused 0 31 mmTA_STATUS 0 0x12e8 17 0 0 FG_PFIFO_EMPTYB 12 12 FG_LFIFO_EMPTYB 13 13 FG_SFIFO_EMPTYB 14 14 FL_PFIFO_EMPTYB 16 16 FL_LFIFO_EMPTYB 17 17 FL_SFIFO_EMPTYB 18 18 FA_PFIFO_EMPTYB 20 20 FA_LFIFO_EMPTYB 21 21 FA_SFIFO_EMPTYB 22 22 IN_BUSY 24 24 FG_BUSY 25 25 LA_BUSY 26 26 FL_BUSY 27 27 TA_BUSY 28 28 FA_BUSY 29 29 AL_BUSY 30 30 BUSY 31 31 mmTA_SCRATCH 0 0x1304 1 0 0 SCRATCH 0 31 mmGDS_CONFIG 0 0x1360 5 0 0 SH0_GPR_PHASE_SEL 1 2 SH1_GPR_PHASE_SEL 3 4 SH2_GPR_PHASE_SEL 5 6 SH3_GPR_PHASE_SEL 7 8 UNUSED 9 31 mmGDS_CNTL_STATUS 0 0x1361 16 0 0 GDS_BUSY 0 0 GRBM_WBUF_BUSY 1 1 ORD_APP_BUSY 2 2 DS_BANK_CONFLICT 3 3 DS_ADDR_CONFLICT 4 4 DS_WR_CLAMP 5 5 DS_RD_CLAMP 6 6 GRBM_RBUF_BUSY 7 7 DS_BUSY 8 8 GWS_BUSY 9 9 ORD_FIFO_BUSY 10 10 CREDIT_BUSY0 11 11 CREDIT_BUSY1 12 12 CREDIT_BUSY2 13 13 CREDIT_BUSY3 14 14 UNUSED 15 31 mmGDS_ENHANCE 0 0x1362 4 0 0 MISC 0 15 AUTO_INC_INDEX 16 16 CGPG_RESTORE 17 17 UNUSED 18 31 mmGDS_PROTECTION_FAULT 0 0x1363 8 0 0 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GRBM 2 2 SH_ID 3 5 CU_ID 6 9 SIMD_ID 10 11 WAVE_ID 12 15 ADDRESS 16 31 mmGDS_VM_PROTECTION_FAULT 0 0x1364 10 0 0 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GWS 2 2 OA 3 3 GRBM 4 4 TMZ 5 5 UNUSED1 6 7 VMID 8 11 UNUSED2 12 15 ADDRESS 16 31 mmGDS_EDC_CNT 0 0x1365 4 0 0 GDS_MEM_DED 0 1 GDS_INPUT_QUEUE_SED 2 3 GDS_MEM_SEC 4 5 UNUSED 6 31 mmGDS_EDC_GRBM_CNT 0 0x1366 3 0 0 DED 0 1 SEC 2 3 UNUSED 4 31 mmGDS_EDC_OA_DED 0 0x1367 14 0 0 ME0_GFXHP3D_PIX_DED 0 0 ME0_GFXHP3D_VTX_DED 1 1 ME0_CS_DED 2 2 ME0_GFXHP3D_GS_DED 3 3 ME1_PIPE0_DED 4 4 ME1_PIPE1_DED 5 5 ME1_PIPE2_DED 6 6 ME1_PIPE3_DED 7 7 ME2_PIPE0_DED 8 8 ME2_PIPE1_DED 9 9 ME2_PIPE2_DED 10 10 ME2_PIPE3_DED 11 11 ME0_PIPE1_CS_DED 12 12 UNUSED1 13 31 mmGDS_DSM_CNTL 0 0x136a 16 0 0 SEL_DSM_GDS_MEM_IRRITATOR_DATA_0 0 0 SEL_DSM_GDS_MEM_IRRITATOR_DATA_1 1 1 GDS_MEM_ENABLE_SINGLE_WRITE 2 2 SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0 3 3 SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1 4 4 GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE 5 5 SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0 6 6 SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1 7 7 GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE 8 8 SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0 9 9 SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1 10 10 GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE 11 11 SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0 12 12 SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1 13 13 GDS_PIPE_MEM_ENABLE_SINGLE_WRITE 14 14 UNUSED 15 31 mmGDS_EDC_OA_PHY_CNT 0 0x136b 6 0 0 ME0_CS_PIPE_MEM_SEC 0 1 ME0_CS_PIPE_MEM_DED 2 3 PHY_CMD_RAM_MEM_SEC 4 5 PHY_CMD_RAM_MEM_DED 6 7 PHY_DATA_RAM_MEM_SED 8 9 UNUSED1 10 31 mmGDS_EDC_OA_PIPE_CNT 0 0x136c 9 0 0 ME1_PIPE0_PIPE_MEM_SEC 0 1 ME1_PIPE0_PIPE_MEM_DED 2 3 ME1_PIPE1_PIPE_MEM_SEC 4 5 ME1_PIPE1_PIPE_MEM_DED 6 7 ME1_PIPE2_PIPE_MEM_SEC 8 9 ME1_PIPE2_PIPE_MEM_DED 10 11 ME1_PIPE3_PIPE_MEM_SEC 12 13 ME1_PIPE3_PIPE_MEM_DED 14 15 UNUSED 16 31 mmGDS_DSM_CNTL2 0 0x136d 12 0 0 GDS_MEM_ENABLE_ERROR_INJECT 0 1 GDS_MEM_SELECT_INJECT_DELAY 2 2 GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT 3 4 GDS_INPUT_QUEUE_SELECT_INJECT_DELAY 5 5 GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT 6 7 GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY 8 8 GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT 9 10 GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY 11 11 GDS_PIPE_MEM_ENABLE_ERROR_INJECT 12 13 GDS_PIPE_MEM_SELECT_INJECT_DELAY 14 14 UNUSED 15 25 GDS_INJECT_DELAY 26 31 mmGDS_WD_GDS_CSB 0 0x136e 2 0 0 COUNTER 0 12 UNUSED 13 31 mmDB_DEBUG 0 0x13ac 24 0 0 DEBUG_STENCIL_COMPRESS_DISABLE 0 0 DEBUG_DEPTH_COMPRESS_DISABLE 1 1 FETCH_FULL_Z_TILE 2 2 FETCH_FULL_STENCIL_TILE 3 3 FORCE_Z_MODE 4 5 DEBUG_FORCE_DEPTH_READ 6 6 DEBUG_FORCE_STENCIL_READ 7 7 DEBUG_FORCE_HIZ_ENABLE 8 9 DEBUG_FORCE_HIS_ENABLE0 10 11 DEBUG_FORCE_HIS_ENABLE1 12 13 DEBUG_FAST_Z_DISABLE 14 14 DEBUG_FAST_STENCIL_DISABLE 15 15 DEBUG_NOOP_CULL_DISABLE 16 16 DISABLE_SUMM_SQUADS 17 17 DEPTH_CACHE_FORCE_MISS 18 18 DEBUG_FORCE_FULL_Z_RANGE 19 20 NEVER_FREE_Z_ONLY 21 21 ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS 22 22 DISABLE_VPORT_ZPLANE_OPTIMIZATION 23 23 DECOMPRESS_AFTER_N_ZPLANES 24 27 ONE_FREE_IN_FLIGHT 28 28 FORCE_MISS_IF_NOT_INFLIGHT 29 29 DISABLE_DEPTH_SURFACE_SYNC 30 30 DISABLE_HTILE_SURFACE_SYNC 31 31 mmDB_DEBUG2 0 0x13ad 25 0 0 ALLOW_COMPZ_BYTE_MASKING 0 0 DISABLE_TC_ZRANGE_L0_CACHE 1 1 DISABLE_TC_MASK_L0_CACHE 2 2 DTR_ROUND_ROBIN_ARB 3 3 DTR_PREZ_STALLS_FOR_ETF_ROOM 4 4 DISABLE_PREZL_FIFO_STALL 5 5 DISABLE_PREZL_FIFO_STALL_REZ 6 6 ENABLE_VIEWPORT_STALL_ON_ALL 7 7 OPTIMIZE_HIZ_MATCHES_FB_DISABLE 8 8 CLK_OFF_DELAY 9 13 FORCE_PERF_COUNTERS_ON 14 14 FULL_TILE_CACHE_EVICT_ON_HALF_FULL 15 15 DISABLE_HTILE_PAIRED_PIPES 16 16 DISABLE_NULL_EOT_FORWARDING 17 17 DISABLE_DTT_DATA_FORWARDING 18 18 DISABLE_QUAD_COHERENCY_STALL 19 19 FULL_TILE_WAVE_BREAK_MODE 20 21 DUAL_PIPE_REZ_STALL_MANUAL_CONTROL 22 22 DUAL_PIPE_REZ_STALL_SELECT_NEW 23 23 FORCE_ITERATE_256 24 25 RESERVED1 26 26 ENABLE_PREZ_OF_REZ_SUMM 28 28 DISABLE_PREZL_VIEWPORT_STALL 29 29 DISABLE_SINGLE_STENCIL_QUAD_SUMM 30 30 DISABLE_WRITE_STALL_ON_RDWR_CONFLICT 31 31 mmDB_DEBUG3 0 0x13ae 32 0 0 DISABLE_CLEAR_ZRANGE_CORRECTION 0 0 DISABLE_RELOAD_CONTEXT_DRAW_DATA 1 1 FORCE_DB_IS_GOOD 2 2 DISABLE_TL_SSO_NULL_SUPPRESSION 3 3 DISABLE_HIZ_ON_VPORT_CLAMP 4 4 EQAA_INTERPOLATE_COMP_Z 5 5 EQAA_INTERPOLATE_SRC_Z 6 6 DISABLE_TCP_CAM_BYPASS 7 7 DISABLE_ZCMP_DIRTY_SUPPRESSION 8 8 DISABLE_REDUNDANT_PLANE_FLUSHES_OPT 9 9 DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP 10 10 ENABLE_INCOHERENT_EQAA_READS 11 11 DISABLE_OP_Z_DATA_FORWARDING 12 12 DISABLE_OP_DF_BYPASS 13 13 DISABLE_OP_DF_WRITE_COMBINE 14 14 DISABLE_OP_DF_DIRECT_FEEDBACK 15 15 DISABLE_SLOCS_PER_CTXT_MATCH 16 16 SLOW_PREZ_TO_A2M_OMASK_RATE 17 17 DISABLE_OP_S_DATA_FORWARDING 18 18 DISABLE_TC_UPDATE_WRITE_COMBINE 19 19 DISABLE_HZ_TC_WRITE_COMBINE 20 20 ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT 21 21 ENABLE_TC_MA_ROUND_ROBIN_ARB 22 22 DISABLE_RAM_READ_SUPPRESION_ON_FWD 23 23 DISABLE_EQAA_A2M_PERF_OPT 24 24 DISABLE_DI_DT_STALL 25 25 ENABLE_DB_PROCESS_RESET 26 26 DISABLE_OVERRASTERIZATION_FIX 27 27 DONT_INSERT_CONTEXT_SUSPEND 28 28 DELETE_CONTEXT_SUSPEND 29 29 DISABLE_TS_WRITE_L0 30 30 DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT 31 31 mmDB_DEBUG4 0 0x13af 30 0 0 DISABLE_QC_Z_MASK_SUMMATION 0 0 DISABLE_QC_STENCIL_MASK_SUMMATION 1 1 DISABLE_RESUMM_TO_SINGLE_STENCIL 2 2 DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL 3 3 DISABLE_SEPARATE_OP_PIPE_CLK 4 4 DISABLE_SEPARATE_DFSM_CLK 5 5 ALWAYS_ON_RMI_CLK_EN 6 6 ENABLE_DBCB_SLOW_FORMAT_COLLAPSE 7 7 DFSM_CONVERT_PASSTHROUGH_TO_BYPASS 8 8 DISABLE_UNMAPPED_Z_INDICATOR 9 9 DISABLE_UNMAPPED_S_INDICATOR 10 10 DISABLE_UNMAPPED_H_INDICATOR 11 11 ENABLE_A2M_DQUAD_OPTIMIZATION 12 12 DISABLE_DTT_FAST_HTILENACK_LOOKUP 13 13 DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION 14 14 DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE 15 15 DISABLE_HIZ_TS_COLLISION_DETECT 16 16 DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT 17 17 DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE 18 18 ENABLE_CZ_OVERFLOW_TESTMODE 19 19 DISABLE_LATEZ_NO_EXPORT_POWER_SAVING 20 20 DISABLE_MCC_BURST_FIFO 21 21 DISABLE_MCC_BURST_FIFO_CONFLICT 22 22 DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK 23 23 WR_MEM_BURST_CTL 24 26 DISABLE_WR_MEM_BURST_POOLING 27 27 DISABLE_RD_MEM_BURST 28 28 LATE_ACK_SCOREBOARD_NEW 29 29 LATE_ACK_SCOREBOARD_MULTIPLE_SLOT 30 30 LATE_ACK_PSD_EOP_GFX9_METHOD 31 31 mmDB_ETILE_STUTTER_CONTROL 0 0x13b0 2 0 0 THRESHOLD 0 7 TIMEOUT 16 23 mmDB_LTILE_STUTTER_CONTROL 0 0x13b1 2 0 0 THRESHOLD 0 7 TIMEOUT 16 23 mmDB_EQUAD_STUTTER_CONTROL 0 0x13b2 2 0 0 THRESHOLD 0 7 TIMEOUT 16 23 mmDB_LQUAD_STUTTER_CONTROL 0 0x13b3 2 0 0 THRESHOLD 0 7 TIMEOUT 16 23 mmDB_CREDIT_LIMIT 0 0x13b4 4 0 0 DB_SC_TILE_CREDITS 0 4 DB_SC_QUAD_CREDITS 5 9 DB_CB_LQUAD_CREDITS 10 12 DB_CB_TILE_CREDITS 24 30 mmDB_WATERMARKS 0 0x13b5 4 0 0 DEPTH_FREE 0 7 DEPTH_FLUSH 8 15 DEPTH_PENDING_FREE 16 23 DEPTH_CACHELINE_FREE 24 31 mmDB_SUBTILE_CONTROL 0 0x13b6 10 0 0 MSAA1_X 0 1 MSAA1_Y 2 3 MSAA2_X 4 5 MSAA2_Y 6 7 MSAA4_X 8 9 MSAA4_Y 10 11 MSAA8_X 12 13 MSAA8_Y 14 15 MSAA16_X 16 17 MSAA16_Y 18 19 mmDB_FREE_CACHELINES 0 0x13b7 4 0 0 FREE_DTILE_DEPTH 0 7 FREE_PLANE_DEPTH 8 15 FREE_Z_DEPTH 16 23 FREE_HTILE_DEPTH 24 31 mmDB_FIFO_DEPTH1 0 0x13b8 4 0 0 MI_RDREQ_FIFO_DEPTH 0 7 MI_WRREQ_FIFO_DEPTH 8 15 MCC_DEPTH 16 23 QC_DEPTH 24 31 mmDB_FIFO_DEPTH2 0 0x13b9 4 0 0 EQUAD_FIFO_DEPTH 0 7 ETILE_OP_FIFO_DEPTH 8 15 LQUAD_FIFO_DEPTH 16 24 LTILE_OP_FIFO_DEPTH 25 31 mmDB_LAST_OF_BURST_CONFIG 0 0x13ba 16 0 0 MAXBURST 0 7 TIMEOUT 8 10 DBCB_LOB_SWITCH_TIMEOUT 11 15 DBCB_LOB_USES_MAXBURST 16 16 ENABLE_FG_DEFAULT_TIMEOUT 17 17 DISABLE_MCC_BURST_COUNT_RESET_ON_LOB 18 18 DISABLE_FLQ_LOB_EVERY_256B 19 19 DISABLE_ZCACHE_FL_OP_EVEN_ARB 20 20 DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO 21 21 ENABLE_TIMEOUT_FL_BURST 25 25 ENABLE_TIMEOUT_FG_LOB_FWDR 26 26 ENABLE_TIMEOUT_RD_BA_ACCUM 27 27 BYPASS_SORT_RD_BA 28 28 DISABLE_256B_COALESCE 29 29 DISABLE_RD_BURST 30 30 LEGACY_LOB_INSERT_EN 31 31 mmDB_RING_CONTROL 0 0x13bb 1 0 0 COUNTER_CONTROL 0 1 mmDB_MEM_ARB_WATERMARKS 0 0x13bc 4 0 0 CLIENT0_WATERMARK 0 2 CLIENT1_WATERMARK 8 10 CLIENT2_WATERMARK 16 18 CLIENT3_WATERMARK 24 26 mmDB_FIFO_DEPTH3 0 0x13bd 2 0 0 LTILE_PROBE_FIFO_DEPTH 0 7 QUAD_READ_REQS 24 31 mmDB_RMI_BC_GL2_CACHE_CONTROL 0 0x13be 8 0 0 Z_WR_POLICY 0 1 S_WR_POLICY 2 3 HTILE_WR_POLICY 4 5 ZPCPSD_WR_POLICY 6 7 Z_RD_POLICY 16 17 S_RD_POLICY 18 19 HTILE_RD_POLICY 20 21 VOL 31 31 mmDB_EXCEPTION_CONTROL 0 0x13bf 8 0 0 EARLY_Z_PANIC_DISABLE 0 0 LATE_Z_PANIC_DISABLE 1 1 RE_Z_PANIC_DISABLE 2 2 AUTO_FLUSH_HTILE 3 3 AUTO_FLUSH_QUAD 4 4 FORCE_SUMMARIZE 8 11 FORCE_VRS_RATE_FINE 16 23 DTAG_WATERMARK 24 30 mmDB_DFSM_CONFIG 0 0x13d0 9 0 0 BYPASS_DFSM 0 0 DISABLE_PUNCHOUT 1 1 DISABLE_POPS 2 2 FORCE_FLUSH 3 3 SQUAD_WATERMARK 4 13 POPS_INCREMENT_CONTROL 14 15 CAM_WATERMARK 16 22 FORCE_PUNCHOUT_5BIT_MODE 23 23 OUTPUT_WATCHDOG 24 31 mmDB_DEBUG5 0 0x13d1 26 0 0 DISABLE_TILE_CACHE_PRELOAD 0 0 ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION 1 1 DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT 2 2 DISABLE_DB_CB_TILE_SEND_ON_CB_TILE_ONLY_MODES 3 3 DISABLE_FLQ_MCC_DTILEID_CHECK 4 4 DISABLE_NOZ_POWER_SAVINGS 5 5 ENABLE_DUAL_QUAD_MODE_IN_BC 6 6 DISABLE_MGCG_GATING_ON_SHADER_WAIT 7 7 DISABLE_DF_TILE_PANIC 8 8 ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE 9 9 DISABLE_RTINDEX_MASKING_IN_BC 10 10 DISABLE_ZPASS_ADDR_CLAMP_IN_BC 11 11 DISABLE_TILE_CACHE_PREFETCH 12 12 DISABLE_PSL_AUTO_MODE_FIX 13 13 DISABLE_FORCE_ZMASK_EXPANDED 14 14 SPARE_BIT_15 15 15 DISABLE_Z_WITHOUT_PLANES_FLQ 16 16 PRESERVE_QMASK_FOR_POSTZ_OP_PIPE 17 17 Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT 18 18 S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT 19 19 DISABLE_RESIDENCY_CHECK_Z 20 20 DISABLE_RESIDENCY_CHECK_STENCIL 21 21 DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK 22 22 DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE 23 23 DISABLE_HTILE_HARVESTING 24 24 SPARE_BITS 25 31 mmDB_DFSM_TILES_IN_FLIGHT 0 0x13d2 1 0 0 HIGH_WATERMARK 0 15 mmDB_DFSM_PRIMS_IN_FLIGHT 0 0x13d3 1 0 0 HIGH_WATERMARK 0 15 mmDB_DFSM_WATCHDOG 0 0x13d4 1 0 0 TIMER_TARGET 0 31 mmDB_DFSM_FLUSH_ENABLE 0 0x13d5 3 0 0 PRIMARY_EVENTS 0 10 AUX_FORCE_PASSTHRU 24 27 AUX_EVENTS 28 31 mmDB_DFSM_FLUSH_AUX_EVENT 0 0x13d6 4 0 0 EVENT_A 0 7 EVENT_B 8 15 EVENT_C 16 23 EVENT_D 24 31 mmDB_FGCG_SRAMS_CLK_CTRL 0 0x13d7 27 0 0 OVERRIDE0 0 0 OVERRIDE1 1 1 OVERRIDE2 2 2 OVERRIDE3 3 3 OVERRIDE4 4 4 OVERRIDE5 5 5 OVERRIDE6 6 6 OVERRIDE7 7 7 OVERRIDE8 8 8 OVERRIDE9 9 9 OVERRIDE10 10 10 OVERRIDE11 11 11 OVERRIDE12 12 12 OVERRIDE13 13 13 OVERRIDE14 14 14 OVERRIDE15 15 15 OVERRIDE16 16 16 OVERRIDE17 17 17 OVERRIDE18 18 18 OVERRIDE19 19 19 OVERRIDE20 20 20 OVERRIDE21 21 21 OVERRIDE22 22 22 OVERRIDE23 23 23 OVERRIDE24 24 24 OVERRIDE25 25 25 OVERRIDE26 26 26 mmDB_FGCG_INTERFACES_CLK_CTRL 0 0x13d8 7 0 0 DB_SC_QUAD_OVERRIDE 0 0 DB_CB_TILE_OVERRIDE 1 1 DB_CB_LQUAD_OVERRIDE 2 2 DB_RMI_RDREQ_OVERRIDE 3 3 DB_RMI_WRREQ_OVERRIDE 4 4 DB_SC_TILE_OVERRIDE 5 5 DB_CB_RMIRET_OVERRIDE 6 6 mmCC_RB_REDUNDANCY 0 0x13dc 4 0 0 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 mmCC_RB_BACKEND_DISABLE 0 0x13dd 1 0 0 BACKEND_DISABLE 16 23 mmGB_ADDR_CONFIG 0 0x13de 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmGB_BACKEND_MAP 0 0x13df 1 0 0 BACKEND_MAP 0 31 mmGB_GPU_ID 0 0x13e0 1 0 0 GPU_ID 0 3 mmCC_RB_DAISY_CHAIN 0 0x13e1 8 0 0 RB_0 0 3 RB_1 4 7 RB_2 8 11 RB_3 12 15 RB_4 16 19 RB_5 20 23 RB_6 24 27 RB_7 28 31 mmGB_ADDR_CONFIG_READ 0 0x13e2 6 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmCB_HW_CONTROL_4 0 0x1422 18 0 0 COLOR_CACHE_FETCH_NUM_CLS_LOG2 0 2 FMASK_CACHE_FETCH_NUM_CLS_LOG2 3 4 DISABLE_USE_OF_QUAD_SCOREBOARD 5 5 DISABLE_CMASK_CLOCK_GATING 6 6 DISABLE_FMASK_CLOCK_GATING 7 7 DISABLE_COLOR_CLOCK_GATING 8 8 DISABLE_QSB_AA_MODE 9 9 DISABLE_QSB_WAIT_FOR_SCORE 10 10 DISABLE_QSB_FRAG_GT0 11 11 REVERSE_KEYXFR_RD_PRIORITY 12 12 DISABLE_KEYXFR_HIT_RETURNS 13 13 DISABLE_BC_COLOR_CACHE_PREFETCH 14 14 DISABLE_MA_WAIT_FOR_LAST 15 15 DISABLE_QSB_SPECULATIVE 16 16 QSB_WAIT_FOR_SCORE 17 21 DISABLE_TILE_FGCG 22 22 DISABLE_LQUAD_FGCG 23 23 FC_QSB_FIFO_DEPTH 24 31 mmCB_HW_CONTROL_3 0 0x1423 28 0 0 DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL 0 0 RAM_ADDRESS_CONFLICTS_DISALLOWED 1 1 DISABLE_FAST_CLEAR_FETCH_OPT 2 2 DISABLE_QUAD_MARKER_DROP_STOP 3 3 DISABLE_OVERWRITE_COMBINER_CAM_CLR 4 4 DISABLE_CC_CACHE_OVWR_STATUS_ACCUM 5 5 DISABLE_CC_CACHE_PANIC_GATING 7 7 SPLIT_ALL_FAST_MODE_TRANSFERS 9 9 DISABLE_SHADER_BLEND_OPTS 10 10 DISABLE_CMASK_LAST_QUAD_INSERTION 11 11 DISABLE_ROP3_FIXES_OF_BUG_511967 12 12 DISABLE_ROP3_FIXES_OF_BUG_520657 13 13 DISABLE_OC_FIXES_OF_BUG_522542 14 14 FORCE_RMI_LAST_HIGH 15 15 FORCE_RMI_CLKEN_HIGH 16 16 DISABLE_EARLY_WRACKS_CC 17 17 DISABLE_EARLY_WRACKS_FC 18 18 DISABLE_EARLY_WRACKS_DC 19 19 DISABLE_EARLY_WRACKS_CM 20 20 DISABLE_NACK_PROCESSING_CC 21 21 DISABLE_NACK_PROCESSING_FC 22 22 DISABLE_NACK_PROCESSING_DC 23 23 DISABLE_NACK_PROCESSING_CM 24 24 DISABLE_NACK_COLOR_RD_WR_OPT 25 25 DISABLE_BLENDER_CLOCK_GATING 26 26 DISABLE_DCC_VRS_OPT 28 28 DISABLE_FMASK_NOFETCH_OPT 30 30 DISABLE_FMASK_NOFETCH_OPT_BC 31 31 mmCB_HW_CONTROL 0 0x1424 24 0 0 ALLOW_MRT_WITH_DUAL_SOURCE 0 0 DISABLE_VRS_FILLRATE_OPTIMIZATION 1 1 DISABLE_FILLRATE_OPT_FIX_WITH_CFC 3 3 DISABLE_POST_DCC_WITH_CFC_FIX 4 4 DISABLE_COMPRESS_1FRAG_WHEN_VRS_RATE_HINT_EN 5 5 RMI_CREDITS 6 11 CHICKEN_BITS 12 14 DISABLE_FMASK_MULTI_MGCG_DOMAINS 15 15 DISABLE_CMASK_CACHE_BYTEMASKING 16 16 DISABLE_DCC_CACHE_BYTEMASKING 17 17 DISABLE_INTNORM_LE11BPC_CLAMPING 18 18 FORCE_NEEDS_DST 19 19 FORCE_ALWAYS_TOGGLE 20 20 DISABLE_BLEND_OPT_RESULT_EQ_DEST 21 21 DISABLE_FULL_WRITE_MASK 22 22 DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG 23 23 DISABLE_BLEND_OPT_DONT_RD_DST 24 24 DISABLE_BLEND_OPT_BYPASS 25 25 DISABLE_BLEND_OPT_DISCARD_PIXEL 26 26 DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED 27 27 PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT 28 28 PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT 29 29 DISABLE_CC_IB_SERIALIZER_STATE_OPT 30 30 DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE 31 31 mmCB_HW_CONTROL_1 0 0x1425 4 0 0 CM_CACHE_NUM_TAGS 0 4 FC_CACHE_NUM_TAGS 5 11 CC_CACHE_NUM_TAGS 12 17 CM_TILE_FIFO_DEPTH 18 26 mmCB_HW_CONTROL_2 0 0x1426 5 0 0 CC_EVEN_ODD_FIFO_DEPTH 0 7 FC_RDLAT_TILE_FIFO_DEPTH 8 14 FC_RDLAT_QUAD_FIFO_DEPTH 15 22 DRR_ASSUMED_FIFO_DEPTH_DIV8 24 29 CHICKEN_BITS 30 31 mmCB_DCC_CONFIG 0 0x1427 7 0 0 OVERWRITE_COMBINER_DEPTH 0 4 OVERWRITE_COMBINER_DISABLE 5 5 OVERWRITE_COMBINER_CC_POP_DISABLE 6 6 DISABLE_CONSTANT_ENCODE 7 7 FC_RDLAT_KEYID_FIFO_DEPTH 8 15 READ_RETURN_SKID_FIFO_DEPTH 16 24 DCC_CACHE_NUM_TAGS 25 31 mmCB_HW_MEM_ARBITER_RD 0 0x1428 13 0 0 MODE 0 1 IGNORE_URGENT_AGE 2 5 BREAK_GROUP_AGE 6 9 WEIGHT_CC 10 11 WEIGHT_FC 12 13 WEIGHT_CM 14 15 WEIGHT_DC 16 17 WEIGHT_DECAY_REQS 18 19 WEIGHT_DECAY_NOREQS 20 21 WEIGHT_IGNORE_NUM_TIDS 22 22 SCALE_AGE 23 25 SCALE_WEIGHT 26 28 SEND_LASTS_WITHIN_GROUPS 29 29 mmCB_HW_MEM_ARBITER_WR 0 0x1429 13 0 0 MODE 0 1 IGNORE_URGENT_AGE 2 5 BREAK_GROUP_AGE 6 9 WEIGHT_CC 10 11 WEIGHT_FC 12 13 WEIGHT_CM 14 15 WEIGHT_DC 16 17 WEIGHT_DECAY_REQS 18 19 WEIGHT_DECAY_NOREQS 20 21 WEIGHT_IGNORE_BYTE_MASK 22 22 SCALE_AGE 23 25 SCALE_WEIGHT 26 28 SEND_LASTS_WITHIN_GROUPS 29 29 mmCB_RMI_BC_GL2_CACHE_CONTROL 0 0x142a 9 0 0 CMASK_WR_POLICY 0 1 FMASK_WR_POLICY 2 3 DCC_WR_POLICY 4 5 COLOR_WR_POLICY 6 7 CMASK_RD_POLICY 16 17 FMASK_RD_POLICY 18 19 DCC_RD_POLICY 20 21 COLOR_RD_POLICY 22 23 VOLAT 31 31 mmCB_STUTTER_CONTROL_CMASK_RDLAT 0 0x142b 2 0 0 THRESHOLD 0 7 TIMEOUT 8 15 mmCB_STUTTER_CONTROL_FMASK_RDLAT 0 0x142c 2 0 0 THRESHOLD 0 7 TIMEOUT 8 15 mmCB_STUTTER_CONTROL_COLOR_RDLAT 0 0x142d 2 0 0 THRESHOLD 0 7 TIMEOUT 8 15 mmCB_CACHE_EVICT_POINTS 0 0x142e 4 0 0 CM_CACHE_EVICT_POINT 0 7 FC_CACHE_EVICT_POINT 8 15 DCC_CACHE_EVICT_POINT 16 23 CC_CACHE_EVICT_POINT 24 31 mmGC_USER_RB_REDUNDANCY 0 0x147e 4 0 0 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 mmGC_USER_RB_BACKEND_DISABLE 0 0x147f 1 0 0 BACKEND_DISABLE 16 23 mmGCEA_MISC 0 0x14a2 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmGCEA_LATENCY_SAMPLING 0 0x14a3 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmGCEA_DSM_CNTL 0 0x14b4 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmGCEA_DSM_CNTLA 0 0x14b5 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmGCEA_DSM_CNTLB 0 0x14b6 0 0 0 mmGCEA_DSM_CNTL2 0 0x14b7 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmGCEA_DSM_CNTL2A 0 0x14b8 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmGCEA_DSM_CNTL2B 0 0x14b9 0 0 0 mmGCEA_GL2C_XBR_CREDITS 0 0x14ba 8 0 0 DRAM_RD_LIMIT 0 5 DRAM_RD_RESERVE 6 7 IO_RD_LIMIT 8 13 IO_RD_RESERVE 14 15 DRAM_WR_LIMIT 16 21 DRAM_WR_RESERVE 22 23 IO_WR_LIMIT 24 29 IO_WR_RESERVE 30 31 mmGCEA_GL2C_XBR_MAXBURST 0 0x14bb 8 0 0 DRAM_RD 0 3 IO_RD 4 7 DRAM_WR 8 11 IO_WR 12 15 DRAM_RD_COMB_FLUSH_TIMER 16 18 DRAM_RD_COMB_SAME64B_ONLY 19 19 DRAM_WR_COMB_FLUSH_TIMER 20 22 DRAM_WR_COMB_SAME64B_ONLY 23 23 mmGCEA_PROBE_CNTL 0 0x14bc 2 0 0 REQ2RSP_DELAY 0 4 PRB_FILTER_DISABLE 5 5 mmGCEA_PROBE_MAP 0 0x14bd 17 0 0 CHADDR0_TO_RIGHTGL2C 0 0 CHADDR1_TO_RIGHTGL2C 1 1 CHADDR2_TO_RIGHTGL2C 2 2 CHADDR3_TO_RIGHTGL2C 3 3 CHADDR4_TO_RIGHTGL2C 4 4 CHADDR5_TO_RIGHTGL2C 5 5 CHADDR6_TO_RIGHTGL2C 6 6 CHADDR7_TO_RIGHTGL2C 7 7 CHADDR8_TO_RIGHTGL2C 8 8 CHADDR9_TO_RIGHTGL2C 9 9 CHADDR10_TO_RIGHTGL2C 10 10 CHADDR11_TO_RIGHTGL2C 11 11 CHADDR12_TO_RIGHTGL2C 12 12 CHADDR13_TO_RIGHTGL2C 13 13 CHADDR14_TO_RIGHTGL2C 14 14 CHADDR15_TO_RIGHTGL2C 15 15 INTLV_SIZE 16 17 mmGCEA_ERR_STATUS 0 0x14be 7 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmGCEA_MISC2 0 0x14bf 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 BLOCK_REQUESTS 13 13 REQUESTS_BLOCKED 14 14 FGCLKEN_OVERRIDE 15 15 mmSPI_PQEV_CTRL 0 0x14c0 3 0 0 SCAN_PERIOD 0 9 QUEUE_DURATION 10 15 COMPUTE_PIPE_EN 16 23 mmSPI_EXP_THROTTLE_CTRL 0 0x14c3 9 0 0 ENABLE 0 0 PERIOD 1 4 UPSTEP 5 8 DOWNSTEP 9 12 LOW_STALL_MON_HIST_COUNT 13 15 HIGH_STALL_MON_HIST_COUNT 16 18 EXP_STALL_THRESHOLD 19 25 SKEW_COUNT 26 28 THROTTLE_RESET 29 29 mmGCEA_RRET_MEM_RESERVE 0 0x1518 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmRMI_GENERAL_CNTL 0 0x1520 11 0 0 BURST_DISABLE 0 0 VMID_BYPASS_ENABLE 1 16 XBAR_MUX_CONFIG 17 18 RB0_HARVEST_EN 19 19 LOOPBACK_DIS_BY_REQ_TYPE 21 24 XBAR_MUX_CONFIG_UPDATE 25 25 SKID_FIFO_0_OVERFLOW_ERROR_MASK 26 26 SKID_FIFO_0_UNDERFLOW_ERROR_MASK 27 27 SKID_FIFO_1_OVERFLOW_ERROR_MASK 28 28 SKID_FIFO_1_UNDERFLOW_ERROR_MASK 29 29 SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 30 30 mmRMI_GENERAL_CNTL1 0 0x1521 10 0 0 EARLY_WRACK_ENABLE_PER_MTYPE 0 3 TCIW0_64B_RD_STALL_MODE 4 5 TCIW1_64B_RD_STALL_MODE 6 7 EARLY_WRACK_DISABLE_FOR_LOOPBACK 8 8 POLICY_OVERRIDE_VALUE 9 10 POLICY_OVERRIDE 11 11 UTCL1_PROBE0_RR_ARB_BURST_HINT_EN 12 12 UTCL1_PROBE1_RR_ARB_BURST_HINT_EN 13 13 ARBITER_ADDRESS_CHANGE_ENABLE 14 14 LAST_OF_BURST_INSERTION_DISABLE 15 15 mmRMI_GENERAL_STATUS 0 0x1522 23 0 0 GENERAL_RMI_ERRORS_COMBINED 0 0 SKID_FIFO_0_OVERFLOW_ERROR 1 1 SKID_FIFO_0_UNDERFLOW_ERROR 2 2 SKID_FIFO_1_OVERFLOW_ERROR 3 3 SKID_FIFO_1_UNDERFLOW_ERROR 4 4 RMI_XBAR_BUSY 5 5 RMI_UTCL1_BUSY 6 6 RMI_SCOREBOARD_BUSY 7 7 TCIW0_PRT_FIFO_BUSY 8 8 TCIW_FRMTR0_BUSY 9 9 TCIW_RTN_FRMTR0_BUSY 10 10 WRREQ_CONSUMER_FIFO_0_BUSY 11 11 RDREQ_CONSUMER_FIFO_0_BUSY 12 12 TCIW1_PRT_FIFO_BUSY 13 13 TCIW_FRMTR1_BUSY 14 14 TCIW_RTN_FRMTR1_BUSY 15 15 UTC_PROBE1_BUSY 18 18 UTC_PROBE0_BUSY 19 19 RMI_XNACK_BUSY 20 20 XNACK_FIFO_NUM_USED 21 28 XNACK_FIFO_EMPTY 29 29 XNACK_FIFO_FULL 30 30 SKID_FIFO_FREESPACE_IS_ZERO_ERROR 31 31 mmRMI_SUBBLOCK_STATUS0 0 0x1523 7 0 0 UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0 0 6 UTC_EXT_LAT_HID_FIFO_FULL_PROBE0 7 7 UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0 8 8 UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1 9 15 UTC_EXT_LAT_HID_FIFO_FULL_PROBE1 16 16 UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1 17 17 TCIW0_INFLIGHT_CNT 18 27 mmRMI_SUBBLOCK_STATUS1 0 0x1524 3 0 0 SKID_FIFO_0_FREE_SPACE 0 9 SKID_FIFO_1_FREE_SPACE 10 19 TCIW1_INFLIGHT_CNT 20 29 mmRMI_SUBBLOCK_STATUS2 0 0x1525 2 0 0 PRT_FIFO_0_NUM_USED 0 8 PRT_FIFO_1_NUM_USED 9 17 mmRMI_SUBBLOCK_STATUS3 0 0x1526 2 0 0 SKID_FIFO_0_FREE_SPACE_TOTAL 0 9 SKID_FIFO_1_FREE_SPACE_TOTAL 10 19 mmRMI_XBAR_CONFIG 0 0x1527 7 0 0 XBAR_MUX_CONFIG_OVERRIDE 0 1 XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE 2 5 XBAR_MUX_CONFIG_CB_DB_OVERRIDE 6 6 ARBITER_DIS 7 7 XBAR_EN_IN_REQ 8 11 XBAR_EN_IN_REQ_OVERRIDE 12 12 XBAR_EN_IN_RB0 13 13 mmRMI_PROBE_POP_LOGIC_CNTL 0 0x1528 5 0 0 EXT_LAT_FIFO_0_MAX_DEPTH 0 6 XLAT_COMBINE0_DIS 7 7 REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2 8 9 EXT_LAT_FIFO_1_MAX_DEPTH 10 16 XLAT_COMBINE1_DIS 17 17 mmRMI_UTC_XNACK_N_MISC_CNTL 0 0x1529 4 0 0 MASTER_XNACK_TIMER_INC 0 7 IND_XNACK_TIMER_START_VALUE 8 11 UTCL1_PERM_MODE 12 12 CP_VMID_RESET_REQUEST_DISABLE 13 13 mmRMI_DEMUX_CNTL 0 0x152a 12 0 0 DEMUX_ARB0_STALL 0 0 DEMUX_ARB0_BREAK_LOB_ON_IDLEIN 1 1 DEMUX_ARB0_MODE_OVERRIDE_EN 2 2 DEMUX_ARB0_STALL_TIMER_OVERRIDE 4 5 DEMUX_ARB0_STALL_TIMER_START_VALUE 6 13 DEMUX_ARB0_MODE 14 15 DEMUX_ARB1_STALL 16 16 DEMUX_ARB1_BREAK_LOB_ON_IDLEIN 17 17 DEMUX_ARB1_MODE_OVERRIDE_EN 18 18 DEMUX_ARB1_STALL_TIMER_OVERRIDE 20 21 DEMUX_ARB1_STALL_TIMER_START_VALUE 22 29 DEMUX_ARB1_MODE 30 31 mmRMI_UTCL1_CNTL1 0 0x152b 17 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 USERVM_DIS 16 16 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 mmRMI_UTCL1_CNTL2 0 0x152c 20 0 0 UTC_SPARE 0 7 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 UTCL1_ARB_BURST_MODE 16 17 UTCL1_ENABLE_PERF_EVENT_RD_WR 18 18 UTCL1_PERF_EVENT_RD_WR 19 19 UTCL1_ENABLE_PERF_EVENT_VMID 20 20 UTCL1_PERF_EVENT_VMID 21 24 UTCL1_DIS_DUAL_L2_REQ 25 25 UTCL1_FORCE_FRAG_2M_TO_64K 26 26 PERM_MODE_OVRD 27 27 LINE_INVALIDATE_OPT 28 28 GPUVM_16K_DEFAULT 29 29 FGCG_DISABLE 30 30 RESERVED 31 31 mmRMI_UTC_UNIT_CONFIG 0 0x152d 0 0 0 mmRMI_TCIW_FORMATTER0_CNTL 0 0x152e 9 0 0 WR_COMBINE0_DIS_OVERRIDE 0 0 WR_COMBINE0_TIME_OUT_WINDOW 1 8 TCIW0_MAX_ALLOWED_INFLIGHT_REQ 9 18 SKID_FIFO_0_FREE_SPACE_DELTA 19 26 SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE 27 27 TCIW0_REQ_SAFE_MODE 28 28 RMI_IN0_REORDER_DIS 29 29 WR_COMBINE0_DIS_AT_LAST_OF_BURST 30 30 ALL_FAULT_RET0_DATA 31 31 mmRMI_TCIW_FORMATTER1_CNTL 0 0x152f 9 0 0 WR_COMBINE1_DIS_OVERRIDE 0 0 WR_COMBINE1_TIME_OUT_WINDOW 1 8 TCIW1_MAX_ALLOWED_INFLIGHT_REQ 9 18 SKID_FIFO_1_FREE_SPACE_DELTA 19 26 SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE 27 27 TCIW1_REQ_SAFE_MODE 28 28 RMI_IN1_REORDER_DIS 29 29 WR_COMBINE1_DIS_AT_LAST_OF_BURST 30 30 ALL_FAULT_RET1_DATA 31 31 mmRMI_SCOREBOARD_CNTL 0 0x1530 10 0 0 COMPLETE_RB0_FLUSH 0 0 REQ_IN_RE_EN_AFTER_FLUSH_RB0 1 1 COMPLETE_RB1_FLUSH 2 2 REQ_IN_RE_EN_AFTER_FLUSH_RB1 3 3 TIME_STAMP_FLUSH_RB1 4 4 VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN 5 5 VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE 6 6 TIME_STAMP_FLUSH_RB0 7 7 FORCE_VMID_INVAL_DONE_EN 8 8 FORCE_VMID_INVAL_DONE_TIMER_START_VALUE 9 20 mmRMI_SCOREBOARD_STATUS0 0 0x1531 8 0 0 CURRENT_SESSION_ID 0 0 CP_VMID_INV_IN_PROG 1 1 CP_VMID_INV_REQ_VMID 2 17 CP_VMID_INV_UTC_DONE 18 18 CP_VMID_INV_DONE 19 19 CP_VMID_INV_FLUSH_TYPE 20 20 FORCE_VMID_INV_DONE 21 21 COUNTER_SELECT 22 26 mmRMI_SCOREBOARD_STATUS1 0 0x1532 9 0 0 RUNNING_CNT_RB0 0 11 RUNNING_CNT_UNDERFLOW_RB0 12 12 RUNNING_CNT_OVERFLOW_RB0 13 13 MULTI_VMID_INVAL_FROM_CP_DETECTED 14 14 RUNNING_CNT_RB1 15 26 RUNNING_CNT_UNDERFLOW_RB1 27 27 RUNNING_CNT_OVERFLOW_RB1 28 28 COM_FLUSH_IN_PROG_RB1 29 29 COM_FLUSH_IN_PROG_RB0 30 30 mmRMI_SCOREBOARD_STATUS2 0 0x1533 10 0 0 SNAPSHOT_CNT_RB0 0 11 SNAPSHOT_CNT_UNDERFLOW_RB0 12 12 SNAPSHOT_CNT_RB1 13 24 SNAPSHOT_CNT_UNDERFLOW_RB1 25 25 COM_FLUSH_DONE_RB1 26 26 COM_FLUSH_DONE_RB0 27 27 TIME_STAMP_FLUSH_IN_PROG_RB0 28 28 TIME_STAMP_FLUSH_IN_PROG_RB1 29 29 TIME_STAMP_FLUSH_DONE_RB0 30 30 TIME_STAMP_FLUSH_DONE_RB1 31 31 mmRMI_XBAR_ARBITER_CONFIG 0 0x1534 14 0 0 XBAR_ARB0_MODE 0 1 XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR 2 2 XBAR_ARB0_STALL 3 3 XBAR_ARB0_BREAK_LOB_ON_IDLEIN 4 4 XBAR_ARB0_MODE_OVERRIDE_EN 5 5 XBAR_ARB0_STALL_TIMER_OVERRIDE 6 7 XBAR_ARB0_STALL_TIMER_START_VALUE 8 15 XBAR_ARB1_MODE 16 17 XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR 18 18 XBAR_ARB1_STALL 19 19 XBAR_ARB1_BREAK_LOB_ON_IDLEIN 20 20 XBAR_ARB1_MODE_OVERRIDE_EN 21 21 XBAR_ARB1_STALL_TIMER_OVERRIDE 22 23 XBAR_ARB1_STALL_TIMER_START_VALUE 24 31 mmRMI_XBAR_ARBITER_CONFIG_1 0 0x1535 2 0 0 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD 0 7 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR 8 15 mmRMI_CLOCK_CNTRL 0 0x1536 4 0 0 DYN_CLK_RB0_BUSY_MASK 0 4 DYN_CLK_CMN_BUSY_MASK 5 9 DYN_CLK_RB0_WAKEUP_MASK 10 14 DYN_CLK_CMN_WAKEUP_MASK 15 19 mmRMI_UTCL1_STATUS 0 0x1537 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 mmRMI_RB_GLX_CID_MAP 0 0x1538 8 0 0 CB_COLOR_MAP 0 3 CB_FMASK_MAP 4 7 CB_CMASK_MAP 8 11 CB_DCC_MAP 12 15 DB_Z_MAP 16 19 DB_S_MAP 20 23 DB_TILE_MAP 24 27 DB_ZPCPSD_MAP 28 31 mmRMI_SPARE 0 0x153f 17 0 0 RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING 0 0 RMI_2_GL1_128B_READ_DISABLE 1 1 RMI_2_GL1_REPEATER_FGCG_DISABLE 2 2 RMI_2_RB_REPEATER_FGCG_DISABLE 3 3 EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS 4 4 RMI_REORDER_BYPASS_CHANNEL_DIS 5 5 XNACK_RETURN_DATA_OVERRIDE 6 6 SPARE_BIT_7 7 7 NOFILL_RMI_CID_CC 8 8 NOFILL_RMI_CID_FC 9 9 NOFILL_RMI_CID_CM 10 10 NOFILL_RMI_CID_DC 11 11 NOFILL_RMI_CID_Z 12 12 NOFILL_RMI_CID_S 13 13 NOFILL_RMI_CID_TILE 14 14 SPARE_BIT_15_0 15 15 ARBITER_ADDRESS_MASK 16 31 mmRMI_SPARE_1 0 0x1540 10 0 0 EARLY_WRACK_FIFO_DISABLE 0 0 SPARE_BIT_9 1 1 SPARE_BIT_10 2 2 SPARE_BIT_11 3 3 SPARE_BIT_12 4 4 SPARE_BIT_13 5 5 SPARE_BIT_14 6 6 SPARE_BIT_15 7 7 RMI_REORDER_DIS_BY_CID 8 15 SPARE_BIT_16_1 16 31 mmRMI_SPARE_2 0 0x1541 3 0 0 ERROR_ZERO_BYTE_MASK_CID 0 15 SPARE_BIT_8_2 16 23 SPARE_BIT_8_3 24 31 mmCC_RMI_REDUNDANCY 0 0x1542 4 0 0 REPAIR_EN_IN_0 1 1 REPAIR_EN_IN_1 2 2 REPAIR_RMI_OVERRIDE 3 3 REPAIR_ID_SWAP 4 4 mmGC_USER_RMI_REDUNDANCY 0 0x1543 4 0 0 REPAIR_EN_IN_0 1 1 REPAIR_EN_IN_1 2 2 REPAIR_RMI_OVERRIDE 3 3 REPAIR_ID_SWAP 4 4 mmGCR_GENERAL_CNTL 0 0x1580 15 0 0 FORCE_4K_L2_RESP 0 0 REDUCE_HALF_MAIN_WQ 1 1 REDUCE_HALF_PHY_WQ 2 2 FORCE_INV_ALL 3 3 HI_PRIORITY_CNTL 4 5 HI_PRIORITY_DISABLE 6 6 BIG_PAGE_FILTER_DISABLE 7 7 PERF_CNTR_ENABLE 8 8 FORCE_SINGLE_WQ 9 9 UTCL2_REQ_PERM 10 12 TARGET_MGCG_CLKEN_DIS 13 13 MIXED_RANGE_MODE_DIS 14 14 ENABLE_16K_UTCL2_REQ 15 15 DISABLE_FGCG 16 16 CLIENT_ID 20 28 mmGCR_CMD_STATUS 0 0x1582 7 0 0 GCR_CONTROL 0 18 GCR_SRC 20 22 GCR_TLB_SHOOTDOWN 23 23 GCR_TLB_SHOOTDOWN_VMID 24 27 UTCL2_NACK_STATUS 28 29 GCR_SEQ_OP_ERROR 30 30 UTCL2_NACK_ERROR 31 31 mmGCR_SPARE 0 0x1583 9 0 0 SPARE_BIT_1 1 1 SPARE_BIT_2 2 2 SPARE_BIT_3 3 3 SPARE_BIT_4 4 4 SPARE_BIT_5 5 5 SPARE_BIT_6 6 6 SPARE_BIT_7 7 7 SPARE_BIT_8_0 8 15 SPARE_BIT_31_16 16 31 mmPMM_GENERAL_CNTL 0 0x1585 3 0 0 PMM_MODE 0 0 PMM_DISABLE 1 1 PMM_ALOG_IH_IDLE 2 2 mmGCR_PIO_CNTL 0 0x1586 6 0 0 GCR_DATA_INDEX 0 1 GCR_REG_DONE 2 2 GCR_REG_RESET 3 3 GCR_PIO_RSP_TAG 16 23 GCR_PIO_RSP_DONE 30 30 GCR_READY 31 31 mmGCR_PIO_DATA 0 0x1587 1 0 0 GCR_DATA 0 31 mmUTCL1_CTRL 0 0x1588 26 0 0 UTCL1_SMALL_PAGE_SIZE 0 0 UTCL1_LARGE_PAGE_SIZE 1 1 UTCL1_CACHE_CORE_BYPASS 2 2 UTCL1_TCP_BYPASS 3 3 UTCL1_SQCI_BYPASS 4 4 UTCL1_SQCD_BYPASS 5 5 UTCL1_RMI_BYPASS 6 6 UTCL1_SQG_BYPASS 7 7 UTCL1_RMI_DEDICATED_CACHE_CORE 8 8 UTCL1_FORCE_RANGE_INV_TO_VMID 9 9 UTCL1_FORCE_INV_ALL 10 10 UTCL1_FORCE_INV_ALL_DONE 11 11 UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE 12 12 UTCL1_INV_FILTER_2M 13 13 UTCL1_RANGE_INV_FORCE_CHK_ALL 14 14 UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE 15 15 UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE 16 16 GCRD_FGCG_DISABLE 17 17 UTCL1_MH_INV_FRAG_SIZE_OVERRIDE 18 18 UTCL1_CACHE_WRITE_PERM 19 19 UTCL1_MH_CAM_DUPLICATE_4K_FILTER 20 20 UTCL1_MH_DISABLE_DUPLICATES 21 21 UTCL1_MH_DISABLE_RECENT_BUFFER 23 23 UTCL1_MISS_CC_PRIORITY 24 25 UTCL1_REDUCE_CC_SIZE 26 27 RESERVED 28 31 mmUTCL1_ALOG 0 0x1589 13 0 0 UTCL1_ALOG_MODE1_FILTER1_THRESHOLD 0 2 UTCL1_ALOG_MODE1_FILTER2_BYPASS 3 3 UTCL1_ALOG_ACTIVE 4 4 UTCL1_ALOG_MODE 5 5 UTCL1_ALOG_MODE2_LOCK_WINDOW 6 8 UTCL1_ALOG_ONLY_MISS 9 9 UTCL1_ALOG_MODE2_INTR_THRESHOLD 10 11 UTCL1_ALOG_SPACE_EN 12 14 UTCL1_ALOG_CLEAN 15 15 UTCL1_ALOG_IDLE 16 16 UTCL1_ALOG_TRACK_SEGMENT_SIZE 17 22 UTCL1_ALOG_MODE1_FILTER1_BYPASS 23 23 UTCL1_ALOG_MODE1_INTR_ON_ALLOC 24 24 mmUTCL1_UTCL0_INVREQ_DISABLE 0 0x158a 1 0 0 UTCL1_UTCL0_INVREQ_DISABLE 0 31 mmGCRD_SA_TARGETS_DISABLE 0 0x158b 1 0 0 GCRD_TARGETS_DISABLE 0 18 mmUTCL1_STATUS 0 0x158c 8 0 0 UTCL1_HIT_PATH_BUSY 0 0 UTCL1_MH_BUSY 1 1 UTCL1_INV_BUSY 2 2 UTCL1_PENDING_UTCL2_REQ 3 3 UTCL1_PENDING_UTCL2_RET 4 4 UTCL1_LAST_UTCL2_RET_XNACK 5 6 UTCL1_RANGE_INV_IN_PROGRESS 7 7 RESERVED 8 8 mmGCVM_L2_CNTL 0 0x15bc 14 0 0 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 mmGCVM_L2_CNTL2 0 0x15bd 7 0 0 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmGCVM_L2_CNTL3 0 0x15be 11 0 0 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmGCVM_L2_STATUS 0 0x15bf 7 0 0 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 mmGCVM_DUMMY_PAGE_FAULT_CNTL 0 0x15c0 3 0 0 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x15c1 1 0 0 DUMMY_PAGE_ADDR_LO32 0 31 mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x15c2 1 0 0 DUMMY_PAGE_ADDR_HI4 0 3 mmGCVM_INVALIDATE_CNTL 0 0x15c3 2 0 0 PRI_REG_ALTERNATING 0 7 MAX_REG_OUTSTANDING 8 15 mmGCVM_L2_PROTECTION_FAULT_CNTL 0 0x15c4 17 0 0 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 mmGCVM_L2_PROTECTION_FAULT_CNTL2 0 0x15c5 5 0 0 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x15c6 1 0 0 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x15c7 1 0 0 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmGCVM_L2_PROTECTION_FAULT_STATUS 0 0x15c8 10 0 0 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 29 mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x15c9 1 0 0 LOGICAL_PAGE_ADDR_LO32 0 31 mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x15ca 1 0 0 LOGICAL_PAGE_ADDR_HI4 0 3 mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x15cb 1 0 0 PHYSICAL_PAGE_ADDR_LO32 0 31 mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x15cc 1 0 0 PHYSICAL_PAGE_ADDR_HI4 0 3 mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x15ce 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x15cf 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x15d0 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x15d1 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x15d2 1 0 0 PHYSICAL_PAGE_OFFSET_LO32 0 31 mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x15d3 1 0 0 PHYSICAL_PAGE_OFFSET_HI4 0 3 mmGCVM_L2_CNTL4 0 0x15d4 7 0 0 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 GC_CH_FGCG_OFF 29 29 mmGCVM_L2_MM_GROUP_RT_CLASSES 0 0x15d5 32 0 0 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 mmGCVM_L2_BANK_SELECT_RESERVED_CID 0 0x15d6 6 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 RESERVED_CACHE_FRAGMENT_SIZE 26 30 mmGCVM_L2_BANK_SELECT_RESERVED_CID2 0 0x15d7 6 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 RESERVED_CACHE_FRAGMENT_SIZE 26 30 mmGCVM_L2_CACHE_PARITY_CNTL 0 0x15d8 9 0 0 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 mmGCVM_L2_CNTL5 0 0x15dc 2 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 WALKER_PRIORITY_CLIENT_ID 5 13 mmGCVM_L2_GCR_CNTL 0 0x15dd 2 0 0 GCR_ENABLE 0 0 GCR_CLIENT_ID 1 9 mmGCVML2_WALKER_MACRO_THROTTLE_TIME 0 0x15de 1 0 0 TIME 0 23 mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0 0x15df 1 0 0 LIMIT 1 15 mmGCVML2_WALKER_MICRO_THROTTLE_TIME 0 0x15e0 1 0 0 TIME 0 23 mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0 0x15e1 1 0 0 LIMIT 1 15 mmGCVM_L2_PTE_CACHE_DUMP_CNTL 0 0x15e3 6 0 0 ENABLE 0 0 READY 1 1 BANK 4 7 CACHE 8 11 ASSOC 12 15 INDEX 16 31 mmGCVM_L2_PTE_CACHE_DUMP_READ 0 0x15e4 1 0 0 DATA 0 31 mmGCVM_CONTEXT0_CNTL 0 0x15fc 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT1_CNTL 0 0x15fd 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT2_CNTL 0 0x15fe 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT3_CNTL 0 0x15ff 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT4_CNTL 0 0x1600 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT5_CNTL 0 0x1601 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT6_CNTL 0 0x1602 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT7_CNTL 0 0x1603 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT8_CNTL 0 0x1604 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT9_CNTL 0 0x1605 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT10_CNTL 0 0x1606 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT11_CNTL 0 0x1607 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT12_CNTL 0 0x1608 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT13_CNTL 0 0x1609 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT14_CNTL 0 0x160a 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXT15_CNTL 0 0x160b 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmGCVM_CONTEXTS_DISABLE 0 0x160c 16 0 0 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmGCVM_INVALIDATE_ENG0_SEM 0 0x160d 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG1_SEM 0 0x160e 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG2_SEM 0 0x160f 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG3_SEM 0 0x1610 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG4_SEM 0 0x1611 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG5_SEM 0 0x1612 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG6_SEM 0 0x1613 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG7_SEM 0 0x1614 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG8_SEM 0 0x1615 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG9_SEM 0 0x1616 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG10_SEM 0 0x1617 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG11_SEM 0 0x1618 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG12_SEM 0 0x1619 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG13_SEM 0 0x161a 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG14_SEM 0 0x161b 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG15_SEM 0 0x161c 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG16_SEM 0 0x161d 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG17_SEM 0 0x161e 1 0 0 SEMAPHORE 0 0 mmGCVM_INVALIDATE_ENG0_REQ 0 0x161f 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG1_REQ 0 0x1620 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG2_REQ 0 0x1621 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG3_REQ 0 0x1622 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG4_REQ 0 0x1623 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG5_REQ 0 0x1624 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG6_REQ 0 0x1625 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG7_REQ 0 0x1626 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG8_REQ 0 0x1627 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG9_REQ 0 0x1628 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG10_REQ 0 0x1629 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG11_REQ 0 0x162a 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG12_REQ 0 0x162b 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG13_REQ 0 0x162c 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG14_REQ 0 0x162d 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG15_REQ 0 0x162e 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG16_REQ 0 0x162f 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG17_REQ 0 0x1630 10 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmGCVM_INVALIDATE_ENG0_ACK 0 0x1631 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG1_ACK 0 0x1632 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG2_ACK 0 0x1633 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG3_ACK 0 0x1634 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG4_ACK 0 0x1635 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG5_ACK 0 0x1636 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG6_ACK 0 0x1637 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG7_ACK 0 0x1638 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG8_ACK 0 0x1639 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG9_ACK 0 0x163a 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG10_ACK 0 0x163b 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG11_ACK 0 0x163c 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG12_ACK 0 0x163d 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG13_ACK 0 0x163e 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG14_ACK 0 0x163f 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG15_ACK 0 0x1640 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG16_ACK 0 0x1641 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG17_ACK 0 0x1642 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0x1643 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0x1644 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0x1645 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0x1646 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0x1647 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0x1648 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0x1649 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0x164a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0x164b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0x164c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0x164d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0x164e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0x164f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0x1650 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0x1651 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0x1652 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0x1653 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0x1654 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0x1655 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0x1656 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0x1657 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0x1658 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0x1659 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0x165a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0x165b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0x165c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0x165d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0x165e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0x165f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0x1660 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0x1661 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0x1662 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0x1663 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0x1664 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0x1665 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0x1666 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x1667 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x1668 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x1669 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x166a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x166b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x166c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x166d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x166e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x166f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x1670 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x1671 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x1672 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x1673 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x1674 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x1675 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x1676 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x1677 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x1678 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x1679 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x167a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x167b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x167c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x167d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x167e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x167f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x1680 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x1681 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x1682 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x1683 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x1684 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x1685 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x1686 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x1687 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x1688 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x1689 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x168a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x168b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x168c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x168d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x168e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x168f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x1690 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x1691 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x1692 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x1693 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x1694 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x1695 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x1696 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x1697 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x1698 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x1699 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x169a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x169b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x169c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x169d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x169e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x169f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x16a0 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x16a1 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x16a2 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x16a3 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x16a4 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x16a5 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x16a6 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x16a7 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x16a8 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x16a9 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x16aa 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x16ab 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x16ac 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x16ad 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x16ae 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x16af 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x16b0 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x16b1 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x16b2 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x16b3 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x16b4 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x16b5 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x16b6 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x16b7 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x16b8 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x16b9 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x16ba 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x16bb 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x16bc 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x16bd 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x16be 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x16bf 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x16c0 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x16c1 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x16c2 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x16c3 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x16c4 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x16c5 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x16c6 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16c7 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16c8 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16c9 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16ca 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16cb 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16cc 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16cd 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16ce 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16cf 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d0 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d1 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d2 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d3 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d4 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d5 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d6 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x16d7 3 0 0 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmGCMC_VM_NB_MMIOBASE 0 0x16e0 1 0 0 MMIOBASE 0 31 mmGCMC_VM_NB_MMIOLIMIT 0 0x16e1 1 0 0 MMIOLIMIT 0 31 mmGCMC_VM_NB_PCI_CTRL 0 0x16e2 1 0 0 MMIOENABLE 23 23 mmGCMC_VM_NB_PCI_ARB 0 0x16e3 1 0 0 VGA_HOLE 3 3 mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0 0x16e4 1 0 0 TOP_OF_DRAM 23 31 mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0 0x16e5 2 0 0 ENABLE 0 0 LOWER_TOM2 23 31 mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0 0x16e6 1 0 0 UPPER_TOM2 0 11 mmGCMC_VM_FB_OFFSET 0 0x16e7 1 0 0 FB_OFFSET 0 23 mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x16e8 1 0 0 PHYSICAL_PAGE_NUMBER_LSB 0 31 mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x16e9 1 0 0 PHYSICAL_PAGE_NUMBER_MSB 0 3 mmGCMC_VM_STEERING 0 0x16ea 1 0 0 DEFAULT_STEERING 0 1 mmGCMC_SHARED_VIRT_RESET_REQ 0 0x16eb 2 0 0 VF 0 30 PF 31 31 mmGCMC_MEM_POWER_LS 0 0x16ec 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0x16ed 1 0 0 ADDRESS 0 19 mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0x16ee 1 0 0 ADDRESS 0 19 mmGCMC_VM_APT_CNTL 0 0x16ef 3 0 0 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 FRAG_APT_INTXN_MODE 2 3 mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x16f0 1 0 0 LOCK 0 0 mmGCMC_VM_LOCAL_HBM_ADDRESS_START 0 0x16f1 1 0 0 ADDRESS 0 19 mmGCMC_VM_LOCAL_HBM_ADDRESS_END 0 0x16f2 1 0 0 ADDRESS 0 19 mmGCMC_SHARED_ACTIVE_FCN_ID 0 0x16f4 2 0 0 VFID 0 4 VF 31 31 mmGCMC_SHARED_VIRT_RESET_REQ2 0 0x16f5 1 0 0 VF 0 0 mmGCMC_VM_XGMI_LFB_CNTL 0 0x16f7 2 0 0 PF_LFB_REGION 0 3 PF_MAX_REGION 4 7 mmGCMC_VM_XGMI_LFB_SIZE 0 0x16f8 1 0 0 PF_LFB_SIZE 0 16 mmGCMC_VM_FB_NOALLOC_CNTL 0 0x16f9 3 0 0 LOCAL_FB_NOALLOC_NOPTE 0 0 REMOTE_FB_NOALLOC_NOPTE 1 1 FB_NOALLOC_WALKER_FETCH 2 2 mmGCUTCL2_HARVEST_BYPASS_GROUPS 0 0x16fa 1 0 0 BYPASS_GROUPS 0 31 mmGCMC_VM_FB_LOCATION_BASE 0 0x16fc 1 0 0 FB_BASE 0 23 mmGCMC_VM_FB_LOCATION_TOP 0 0x16fd 1 0 0 FB_TOP 0 23 mmGCMC_VM_AGP_TOP 0 0x16fe 1 0 0 AGP_TOP 0 23 mmGCMC_VM_AGP_BOT 0 0x16ff 1 0 0 AGP_BOT 0 23 mmGCMC_VM_AGP_BASE 0 0x1700 1 0 0 AGP_BASE 0 23 mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x1701 1 0 0 LOGICAL_ADDR 0 29 mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x1702 1 0 0 LOGICAL_ADDR 0 29 mmGCMC_VM_MX_L1_TLB_CNTL 0 0x1703 6 0 0 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 13 mmGCEA_DRAM_RD_CLI2GRP_MAP0 0 0x17a0 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmGCEA_DRAM_RD_CLI2GRP_MAP1 0 0x17a1 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmGCEA_DRAM_WR_CLI2GRP_MAP0 0 0x17a2 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmGCEA_DRAM_WR_CLI2GRP_MAP1 0 0x17a3 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmGCEA_DRAM_RD_GRP2VC_MAP 0 0x17a4 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmGCEA_DRAM_WR_GRP2VC_MAP 0 0x17a5 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmGCEA_DRAM_RD_LAZY 0 0x17a6 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmGCEA_DRAM_WR_LAZY 0 0x17a7 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmGCEA_DRAM_RD_CAM_CNTL 0 0x17a8 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmGCEA_DRAM_WR_CAM_CNTL 0 0x17a9 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmGCEA_DRAM_PAGE_BURST 0 0x17aa 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmGCEA_DRAM_RD_PRI_AGE 0 0x17ab 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmGCEA_DRAM_WR_PRI_AGE 0 0x17ac 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmGCEA_DRAM_RD_PRI_QUEUING 0 0x17ad 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmGCEA_DRAM_WR_PRI_QUEUING 0 0x17ae 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmGCEA_DRAM_RD_PRI_FIXED 0 0x17af 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmGCEA_DRAM_WR_PRI_FIXED 0 0x17b0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmGCEA_DRAM_RD_PRI_URGENCY 0 0x17b1 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmGCEA_DRAM_WR_PRI_URGENCY 0 0x17b2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmGCEA_DRAM_RD_PRI_QUANT_PRI1 0 0x17b3 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_DRAM_RD_PRI_QUANT_PRI2 0 0x17b4 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_DRAM_RD_PRI_QUANT_PRI3 0 0x17b5 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_DRAM_WR_PRI_QUANT_PRI1 0 0x17b6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_DRAM_WR_PRI_QUANT_PRI2 0 0x17b7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_DRAM_WR_PRI_QUANT_PRI3 0 0x17b8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_RD_CLI2GRP_MAP0 0 0x187d 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmGCEA_IO_RD_CLI2GRP_MAP1 0 0x187e 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmGCEA_IO_WR_CLI2GRP_MAP0 0 0x187f 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmGCEA_IO_WR_CLI2GRP_MAP1 0 0x1880 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmGCEA_IO_RD_COMBINE_FLUSH 0 0x1881 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmGCEA_IO_WR_COMBINE_FLUSH 0 0x1882 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmGCEA_IO_GROUP_BURST 0 0x1883 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmGCEA_IO_RD_PRI_AGE 0 0x1884 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmGCEA_IO_WR_PRI_AGE 0 0x1885 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmGCEA_IO_RD_PRI_QUEUING 0 0x1886 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmGCEA_IO_WR_PRI_QUEUING 0 0x1887 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmGCEA_IO_RD_PRI_FIXED 0 0x1888 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmGCEA_IO_WR_PRI_FIXED 0 0x1889 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmGCEA_IO_RD_PRI_URGENCY 0 0x188a 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmGCEA_IO_WR_PRI_URGENCY 0 0x188b 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmGCEA_IO_RD_PRI_URGENCY_MASKING 0 0x188c 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmGCEA_IO_WR_PRI_URGENCY_MASKING 0 0x188d 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmGCEA_IO_RD_PRI_QUANT_PRI1 0 0x188e 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_RD_PRI_QUANT_PRI2 0 0x188f 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_RD_PRI_QUANT_PRI3 0 0x1890 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_WR_PRI_QUANT_PRI1 0 0x1891 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_WR_PRI_QUANT_PRI2 0 0x1892 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGCEA_IO_WR_PRI_QUANT_PRI3 0 0x1893 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmTCP_INVALIDATE 0 0x18a0 1 0 0 START 0 0 mmTCP_STATUS 0 0x18a1 13 0 0 TCP_BUSY 0 0 INPUT_BUSY 1 1 ADRS_BUSY 2 2 TAGRAMS_BUSY 3 3 CNTRL_BUSY 4 4 LFIFO_BUSY 5 5 READ_BUSY 6 6 FORMAT_BUSY 7 7 VM_BUSY 8 8 MEMIF_BUSY 9 9 GCR_BUSY 10 10 OFIFO_BUSY 11 11 OFIFO_QUEUE_BUSY 12 13 mmTCP_EDC_CNT 0 0x18b7 3 0 0 SEC_COUNT 0 7 LFIFO_SED_COUNT 8 15 DED_COUNT 16 23 mmTCI_STATUS 0 0x1901 1 0 0 TCI_BUSY 0 0 mmTCI_CNTL_1 0 0x1902 3 0 0 WBINVL1_NUM_CYCLES 0 15 REQ_FIFO_DEPTH 16 23 WDATA_RAM_DEPTH 24 31 mmTCI_CNTL_2 0 0x1903 2 0 0 L1_INVAL_ON_WBINVL2 0 0 TCA_MAX_CREDIT 1 8 mmSPI_SHADER_PGM_RSRC4_PS 0 0x19a1 1 0 0 CU_EN 0 15 mmSPI_SHADER_PGM_CHKSUM_PS 0 0x19a6 1 0 0 CHECKSUM 0 31 mmSPI_SHADER_PGM_RSRC3_PS 0 0x19a7 3 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_PGM_LO_PS 0 0x19a8 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_PS 0 0x19a9 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_PS 0 0x19aa 12 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 CU_GROUP_DISABLE 24 24 MEM_ORDERED 25 25 FWD_PROGRESS 26 26 LOAD_PROVOKING_VTX 27 27 FP16_OVFL 29 29 mmSPI_SHADER_PGM_RSRC2_PS 0 0x19ab 10 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 WAVE_CNT_EN 7 7 EXTRA_LDS_SIZE 8 15 EXCP_EN 16 24 LOAD_COLLISION_WAVEID 25 25 LOAD_INTRAWAVE_COLLISION 26 26 USER_SGPR_MSB 27 27 SHARED_VGPR_CNT 28 31 mmSPI_SHADER_USER_DATA_PS_0 0 0x19ac 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_1 0 0x19ad 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_2 0 0x19ae 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_3 0 0x19af 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_4 0 0x19b0 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_5 0 0x19b1 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_6 0 0x19b2 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_7 0 0x19b3 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_8 0 0x19b4 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_9 0 0x19b5 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_10 0 0x19b6 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_11 0 0x19b7 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_12 0 0x19b8 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_13 0 0x19b9 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_14 0 0x19ba 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_15 0 0x19bb 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_16 0 0x19bc 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_17 0 0x19bd 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_18 0 0x19be 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_19 0 0x19bf 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_20 0 0x19c0 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_21 0 0x19c1 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_22 0 0x19c2 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_23 0 0x19c3 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_24 0 0x19c4 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_25 0 0x19c5 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_26 0 0x19c6 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_27 0 0x19c7 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_28 0 0x19c8 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_29 0 0x19c9 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_30 0 0x19ca 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_31 0 0x19cb 1 0 0 DATA 0 31 mmSPI_SHADER_REQ_CTRL_PS 0 0x19d0 8 0 0 SOFT_GROUPING_EN 0 0 NUMBER_OF_REQUESTS_PER_CU 1 4 SOFT_GROUPING_ALLOCATION_TIMEOUT 5 8 HARD_LOCK_HYSTERESIS 9 9 HARD_LOCK_LOW_THRESHOLD 10 14 PRODUCER_REQUEST_LOCKOUT 15 15 GLOBAL_SCANNING_EN 16 16 ALLOCATION_RATE_THROTTLING_THRESHOLD 17 19 mmSPI_SHADER_USER_ACCUM_PS_0 0 0x19d2 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_PS_1 0 0x19d3 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_PS_2 0 0x19d4 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_PS_3 0 0x19d5 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_PGM_RSRC4_VS 0 0x19e1 1 0 0 CU_EN 0 15 mmSPI_SHADER_PGM_CHKSUM_VS 0 0x19e5 1 0 0 CHECKSUM 0 31 mmSPI_SHADER_PGM_RSRC3_VS 0 0x19e6 3 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_LATE_ALLOC_VS 0 0x19e7 1 0 0 LIMIT 0 5 mmSPI_SHADER_PGM_LO_VS 0 0x19e8 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_VS 0 0x19e9 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_VS 0 0x19ea 12 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 VGPR_COMP_CNT 24 25 CU_GROUP_ENABLE 26 26 MEM_ORDERED 27 27 FWD_PROGRESS 28 28 FP16_OVFL 31 31 mmSPI_SHADER_PGM_RSRC2_VS 0 0x19eb 14 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 SO_BASE0_EN 8 8 SO_BASE1_EN 9 9 SO_BASE2_EN 10 10 SO_BASE3_EN 11 11 SO_EN 12 12 EXCP_EN 13 21 PC_BASE_EN 22 22 DISPATCH_DRAW_EN 24 24 USER_SGPR_MSB 27 27 SHARED_VGPR_CNT 28 31 mmSPI_SHADER_USER_DATA_VS_0 0 0x19ec 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_1 0 0x19ed 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_2 0 0x19ee 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_3 0 0x19ef 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_4 0 0x19f0 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_5 0 0x19f1 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_6 0 0x19f2 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_7 0 0x19f3 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_8 0 0x19f4 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_9 0 0x19f5 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_10 0 0x19f6 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_11 0 0x19f7 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_12 0 0x19f8 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_13 0 0x19f9 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_14 0 0x19fa 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_15 0 0x19fb 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_16 0 0x19fc 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_17 0 0x19fd 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_18 0 0x19fe 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_19 0 0x19ff 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_20 0 0x1a00 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_21 0 0x1a01 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_22 0 0x1a02 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_23 0 0x1a03 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_24 0 0x1a04 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_25 0 0x1a05 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_26 0 0x1a06 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_27 0 0x1a07 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_28 0 0x1a08 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_29 0 0x1a09 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_30 0 0x1a0a 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_31 0 0x1a0b 1 0 0 DATA 0 31 mmSPI_SHADER_REQ_CTRL_VS 0 0x1a10 8 0 0 SOFT_GROUPING_EN 0 0 NUMBER_OF_REQUESTS_PER_CU 1 4 SOFT_GROUPING_ALLOCATION_TIMEOUT 5 8 HARD_LOCK_HYSTERESIS 9 9 HARD_LOCK_LOW_THRESHOLD 10 14 PRODUCER_REQUEST_LOCKOUT 15 15 GLOBAL_SCANNING_EN 16 16 ALLOCATION_RATE_THROTTLING_THRESHOLD 17 19 mmSPI_SHADER_USER_ACCUM_VS_0 0 0x1a12 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_VS_1 0 0x1a13 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_VS_2 0 0x1a14 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_VS_3 0 0x1a15 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_PGM_RSRC2_GS_VS 0 0x1a1b 9 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 VGPR_COMP_CNT 16 17 OC_LDS_EN 18 18 LDS_SIZE 19 26 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 mmSPI_SHADER_PGM_CHKSUM_GS 0 0x1a20 1 0 0 CHECKSUM 0 31 mmSPI_SHADER_PGM_RSRC4_GS 0 0x1a21 2 0 0 CU_EN 0 15 SPI_SHADER_LATE_ALLOC_GS 16 22 mmSPI_SHADER_USER_DATA_ADDR_LO_GS 0 0x1a22 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_USER_DATA_ADDR_HI_GS 0 0x1a23 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_LO_ES_GS 0 0x1a24 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_ES_GS 0 0x1a25 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC3_GS 0 0x1a27 4 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 GROUP_FIFO_DEPTH 26 31 mmSPI_SHADER_PGM_LO_GS 0 0x1a28 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_GS 0 0x1a29 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_GS 0 0x1a2a 13 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 CU_GROUP_ENABLE 24 24 MEM_ORDERED 25 25 FWD_PROGRESS 26 26 WGP_MODE 27 27 GS_VGPR_COMP_CNT 29 30 FP16_OVFL 31 31 mmSPI_SHADER_PGM_RSRC2_GS 0 0x1a2b 9 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 ES_VGPR_COMP_CNT 16 17 OC_LDS_EN 18 18 LDS_SIZE 19 26 USER_SGPR_MSB 27 27 SHARED_VGPR_CNT 28 31 mmSPI_SHADER_USER_DATA_GS_0 0 0x1a2c 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_1 0 0x1a2d 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_2 0 0x1a2e 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_3 0 0x1a2f 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_4 0 0x1a30 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_5 0 0x1a31 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_6 0 0x1a32 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_7 0 0x1a33 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_8 0 0x1a34 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_9 0 0x1a35 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_10 0 0x1a36 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_11 0 0x1a37 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_12 0 0x1a38 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_13 0 0x1a39 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_14 0 0x1a3a 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_15 0 0x1a3b 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_16 0 0x1a3c 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_17 0 0x1a3d 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_18 0 0x1a3e 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_19 0 0x1a3f 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_20 0 0x1a40 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_21 0 0x1a41 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_22 0 0x1a42 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_23 0 0x1a43 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_24 0 0x1a44 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_25 0 0x1a45 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_26 0 0x1a46 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_27 0 0x1a47 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_28 0 0x1a48 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_29 0 0x1a49 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_30 0 0x1a4a 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_31 0 0x1a4b 1 0 0 DATA 0 31 mmSPI_SHADER_REQ_CTRL_ESGS 0 0x1a50 8 0 0 SOFT_GROUPING_EN 0 0 NUMBER_OF_REQUESTS_PER_CU 1 4 SOFT_GROUPING_ALLOCATION_TIMEOUT 5 8 HARD_LOCK_HYSTERESIS 9 9 HARD_LOCK_LOW_THRESHOLD 10 14 PRODUCER_REQUEST_LOCKOUT 15 15 GLOBAL_SCANNING_EN 16 16 ALLOCATION_RATE_THROTTLING_THRESHOLD 17 19 mmSPI_SHADER_USER_ACCUM_ESGS_0 0 0x1a52 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_ESGS_1 0 0x1a53 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_ESGS_2 0 0x1a54 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_ESGS_3 0 0x1a55 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_PGM_LO_ES 0 0x1a68 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_ES 0 0x1a69 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_CHKSUM_HS 0 0x1aa0 1 0 0 CHECKSUM 0 31 mmSPI_SHADER_PGM_RSRC4_HS 0 0x1aa1 1 0 0 CU_EN 0 15 mmSPI_SHADER_USER_DATA_ADDR_LO_HS 0 0x1aa2 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_USER_DATA_ADDR_HI_HS 0 0x1aa3 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_LO_LS_HS 0 0x1aa4 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_LS_HS 0 0x1aa5 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC3_HS 0 0x1aa7 4 0 0 WAVE_LIMIT 0 5 LOCK_LOW_THRESHOLD 6 9 GROUP_FIFO_DEPTH 10 15 CU_EN 16 31 mmSPI_SHADER_PGM_LO_HS 0 0x1aa8 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_HS 0 0x1aa9 1 0 0 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_HS 0 0x1aaa 12 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 MEM_ORDERED 24 24 FWD_PROGRESS 25 25 WGP_MODE 26 26 LS_VGPR_COMP_CNT 28 29 FP16_OVFL 30 30 mmSPI_SHADER_PGM_RSRC2_HS 0 0x1aab 9 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 TG_SIZE_EN 8 8 EXCP_EN 9 17 LDS_SIZE 18 26 USER_SGPR_MSB 27 27 SHARED_VGPR_CNT 28 31 mmSPI_SHADER_USER_DATA_HS_0 0 0x1aac 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_1 0 0x1aad 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_2 0 0x1aae 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_3 0 0x1aaf 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_4 0 0x1ab0 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_5 0 0x1ab1 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_6 0 0x1ab2 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_7 0 0x1ab3 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_8 0 0x1ab4 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_9 0 0x1ab5 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_10 0 0x1ab6 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_11 0 0x1ab7 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_12 0 0x1ab8 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_13 0 0x1ab9 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_14 0 0x1aba 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_15 0 0x1abb 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_16 0 0x1abc 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_17 0 0x1abd 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_18 0 0x1abe 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_19 0 0x1abf 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_20 0 0x1ac0 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_21 0 0x1ac1 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_22 0 0x1ac2 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_23 0 0x1ac3 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_24 0 0x1ac4 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_25 0 0x1ac5 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_26 0 0x1ac6 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_27 0 0x1ac7 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_28 0 0x1ac8 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_29 0 0x1ac9 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_30 0 0x1aca 1 0 0 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_31 0 0x1acb 1 0 0 DATA 0 31 mmSPI_SHADER_REQ_CTRL_LSHS 0 0x1ad0 8 0 0 SOFT_GROUPING_EN 0 0 NUMBER_OF_REQUESTS_PER_CU 1 4 SOFT_GROUPING_ALLOCATION_TIMEOUT 5 8 HARD_LOCK_HYSTERESIS 9 9 HARD_LOCK_LOW_THRESHOLD 10 14 PRODUCER_REQUEST_LOCKOUT 15 15 GLOBAL_SCANNING_EN 16 16 ALLOCATION_RATE_THROTTLING_THRESHOLD 17 19 mmSPI_SHADER_USER_ACCUM_LSHS_0 0 0x1ad2 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_LSHS_1 0 0x1ad3 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_LSHS_2 0 0x1ad4 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_USER_ACCUM_LSHS_3 0 0x1ad5 1 0 0 CONTRIBUTION 0 6 mmSPI_SHADER_PGM_LO_LS 0 0x1ae8 1 0 0 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_LS 0 0x1ae9 1 0 0 MEM_BASE 0 7 mmCOMPUTE_DISPATCH_INITIATOR 0 0x1ba0 13 0 0 COMPUTE_SHADER_EN 0 0 PARTIAL_TG_EN 1 1 FORCE_START_AT_000 2 2 ORDERED_APPEND_ENBL 3 3 ORDERED_APPEND_MODE 4 4 USE_THREAD_DIMENSIONS 5 5 ORDER_MODE 6 6 SCALAR_L1_INV_VOL 10 10 VECTOR_L1_INV_VOL 11 11 RESERVED 12 12 TUNNEL_ENABLE 13 13 RESTORE 14 14 CS_W32_EN 15 15 mmCOMPUTE_DIM_X 0 0x1ba1 1 0 0 SIZE 0 31 mmCOMPUTE_DIM_Y 0 0x1ba2 1 0 0 SIZE 0 31 mmCOMPUTE_DIM_Z 0 0x1ba3 1 0 0 SIZE 0 31 mmCOMPUTE_START_X 0 0x1ba4 1 0 0 START 0 31 mmCOMPUTE_START_Y 0 0x1ba5 1 0 0 START 0 31 mmCOMPUTE_START_Z 0 0x1ba6 1 0 0 START 0 31 mmCOMPUTE_NUM_THREAD_X 0 0x1ba7 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_NUM_THREAD_Y 0 0x1ba8 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_NUM_THREAD_Z 0 0x1ba9 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_PIPELINESTAT_ENABLE 0 0x1baa 1 0 0 PIPELINESTAT_ENABLE 0 0 mmCOMPUTE_PERFCOUNT_ENABLE 0 0x1bab 1 0 0 PERFCOUNT_ENABLE 0 0 mmCOMPUTE_PGM_LO 0 0x1bac 1 0 0 DATA 0 31 mmCOMPUTE_PGM_HI 0 0x1bad 1 0 0 DATA 0 7 mmCOMPUTE_DISPATCH_PKT_ADDR_LO 0 0x1bae 1 0 0 DATA 0 31 mmCOMPUTE_DISPATCH_PKT_ADDR_HI 0 0x1baf 1 0 0 DATA 0 7 mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0 0x1bb0 1 0 0 DATA 0 31 mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0 0x1bb1 1 0 0 DATA 0 7 mmCOMPUTE_PGM_RSRC1 0 0x1bb2 12 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 BULKY 24 24 FP16_OVFL 26 26 WGP_MODE 29 29 MEM_ORDERED 30 30 FWD_PROGRESS 31 31 mmCOMPUTE_PGM_RSRC2 0 0x1bb3 11 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 TGID_X_EN 7 7 TGID_Y_EN 8 8 TGID_Z_EN 9 9 TG_SIZE_EN 10 10 TIDIG_COMP_CNT 11 12 EXCP_EN_MSB 13 14 LDS_SIZE 15 23 EXCP_EN 24 30 mmCOMPUTE_VMID 0 0x1bb4 1 0 0 DATA 0 3 mmCOMPUTE_RESOURCE_LIMITS 0 0x1bb5 6 0 0 WAVES_PER_SH 0 9 TG_PER_CU 12 15 LOCK_THRESHOLD 16 21 SIMD_DEST_CNTL 22 22 FORCE_SIMD_DIST 23 23 CU_GROUP_COUNT 24 26 mmCOMPUTE_DESTINATION_EN_SE0 0 0x1bb6 1 0 0 CU_EN 0 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0 0x1bb6 2 0 0 SA0_CU_EN 0 15 SA1_CU_EN 16 31 mmCOMPUTE_DESTINATION_EN_SE1 0 0x1bb7 1 0 0 CU_EN 0 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0 0x1bb7 2 0 0 SA0_CU_EN 0 15 SA1_CU_EN 16 31 mmCOMPUTE_TMPRING_SIZE 0 0x1bb8 2 0 0 WAVES 0 11 WAVESIZE 12 24 mmCOMPUTE_DESTINATION_EN_SE2 0 0x1bb9 1 0 0 CU_EN 0 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0 0x1bb9 2 0 0 SA0_CU_EN 0 15 SA1_CU_EN 16 31 mmCOMPUTE_DESTINATION_EN_SE3 0 0x1bba 1 0 0 CU_EN 0 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0 0x1bba 2 0 0 SA0_CU_EN 0 15 SA1_CU_EN 16 31 mmCOMPUTE_RESTART_X 0 0x1bbb 1 0 0 RESTART 0 31 mmCOMPUTE_RESTART_Y 0 0x1bbc 1 0 0 RESTART 0 31 mmCOMPUTE_RESTART_Z 0 0x1bbd 1 0 0 RESTART 0 31 mmCOMPUTE_THREAD_TRACE_ENABLE 0 0x1bbe 1 0 0 THREAD_TRACE_ENABLE 0 0 mmCOMPUTE_MISC_RESERVED 0 0x1bbf 5 0 0 SEND_SEID 0 1 RESERVED2 2 2 RESERVED3 3 3 RESERVED4 4 4 WAVE_ID_BASE 5 16 mmCOMPUTE_DISPATCH_ID 0 0x1bc0 1 0 0 DISPATCH_ID 0 31 mmCOMPUTE_THREADGROUP_ID 0 0x1bc1 1 0 0 THREADGROUP_ID 0 31 mmCOMPUTE_REQ_CTRL 0 0x1bc2 9 0 0 SOFT_GROUPING_EN 0 0 NUMBER_OF_REQUESTS_PER_CU 1 4 SOFT_GROUPING_ALLOCATION_TIMEOUT 5 8 HARD_LOCK_HYSTERESIS 9 9 HARD_LOCK_LOW_THRESHOLD 10 14 PRODUCER_REQUEST_LOCKOUT 15 15 GLOBAL_SCANNING_EN 16 16 ALLOCATION_RATE_THROTTLING_THRESHOLD 17 19 DEDICATED_PREALLOCATION_BUFFER_LIMIT 20 26 mmCOMPUTE_USER_ACCUM_0 0 0x1bc4 1 0 0 CONTRIBUTION 0 6 mmCOMPUTE_USER_ACCUM_1 0 0x1bc5 1 0 0 CONTRIBUTION 0 6 mmCOMPUTE_USER_ACCUM_2 0 0x1bc6 1 0 0 CONTRIBUTION 0 6 mmCOMPUTE_USER_ACCUM_3 0 0x1bc7 1 0 0 CONTRIBUTION 0 6 mmCOMPUTE_PGM_RSRC3 0 0x1bc8 1 0 0 SHARED_VGPR_CNT 0 3 mmCOMPUTE_DDID_INDEX 0 0x1bc9 1 0 0 INDEX 0 10 mmCOMPUTE_SHADER_CHKSUM 0 0x1bca 1 0 0 CHECKSUM 0 31 mmCOMPUTE_RELAUNCH 0 0x1bcb 3 0 0 PAYLOAD 0 29 IS_EVENT 30 30 IS_STATE 31 31 mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0 0x1bcc 1 0 0 ADDR 0 31 mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0 0x1bcd 1 0 0 ADDR 0 15 mmCOMPUTE_RELAUNCH2 0 0x1bce 3 0 0 PAYLOAD 0 29 IS_EVENT 30 30 IS_STATE 31 31 mmCOMPUTE_USER_DATA_0 0 0x1be0 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_1 0 0x1be1 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_2 0 0x1be2 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_3 0 0x1be3 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_4 0 0x1be4 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_5 0 0x1be5 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_6 0 0x1be6 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_7 0 0x1be7 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_8 0 0x1be8 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_9 0 0x1be9 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_10 0 0x1bea 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_11 0 0x1beb 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_12 0 0x1bec 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_13 0 0x1bed 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_14 0 0x1bee 1 0 0 DATA 0 31 mmCOMPUTE_USER_DATA_15 0 0x1bef 1 0 0 DATA 0 31 mmCOMPUTE_DISPATCH_TUNNEL 0 0x1c1d 2 0 0 OFF_DELAY 0 9 IMMEDIATE 10 10 mmCOMPUTE_DISPATCH_END 0 0x1c1e 1 0 0 DATA 0 31 mmCOMPUTE_NOWHERE 0 0x1c1f 1 0 0 DATA 0 31 mmSH_RESERVED_REG0 0 0x1c20 1 0 0 DATA 0 31 mmSH_RESERVED_REG1 0 0x1c21 1 0 0 DATA 0 31 mmCP_EOPQ_WAIT_TIME 0 0x1dd5 2 0 0 WAIT_TIME 0 9 SCALE_COUNT 10 17 mmCP_CPC_MGCG_SYNC_CNTL 0 0x1dd6 2 0 0 COOLDOWN_PERIOD 0 7 WARMUP_PERIOD 8 15 mmCPC_INT_INFO 0 0x1dd7 4 0 0 ADDR_HI 0 15 TYPE 16 16 VMID 20 23 QUEUE_ID 28 30 mmCP_VIRT_STATUS 0 0x1dd8 1 0 0 VIRT_STATUS 0 31 mmCPC_INT_ADDR 0 0x1dd9 1 0 0 ADDR 0 31 mmCPC_INT_PASID 0 0x1dda 2 0 0 PASID 0 15 BYPASS_PASID 16 16 mmCP_GFX_ERROR 0 0x1ddb 29 0 0 EDC_ERROR_ID 0 3 SUA_ERROR 4 4 CE_DATA_FETCHER_UTCL1_ERROR 5 5 DATA_FETCHER_UTCL1_ERROR 6 6 SEM_UTCL1_ERROR 7 7 QU_STRM_UTCL1_ERROR 8 8 QU_EOP_UTCL1_ERROR 9 9 QU_PIPE_UTCL1_ERROR 10 10 QU_READ_UTCL1_ERROR 11 11 SYNC_MEMRD_UTCL1_ERROR 12 12 SYNC_MEMWR_UTCL1_ERROR 13 13 SHADOW_UTCL1_ERROR 14 14 APPEND_UTCL1_ERROR 15 15 CE_DMA_UTCL1_ERROR 16 16 PFP_VGTDMA_UTCL1_ERROR 17 17 DMA_SRC_UTCL1_ERROR 18 18 DMA_DST_UTCL1_ERROR 19 19 PFP_TC_UTCL1_ERROR 20 20 ME_TC_UTCL1_ERROR 21 21 CE_TC_UTCL1_ERROR 22 22 PRT_LOD_UTCL1_ERROR 23 23 RDPTR_RPT_UTCL1_ERROR 24 24 RB_FETCHER_UTCL1_ERROR 25 25 I1_FETCHER_UTCL1_ERROR 26 26 I2_FETCHER_UTCL1_ERROR 27 27 C1_FETCHER_UTCL1_ERROR 28 28 C2_FETCHER_UTCL1_ERROR 29 29 ST_FETCHER_UTCL1_ERROR 30 30 CE_INIT_UTCL1_ERROR 31 31 mmCPG_UTCL1_CNTL 0 0x1ddc 7 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 MTYPE_NO_PTE_MODE 30 30 mmCPC_UTCL1_CNTL 0 0x1ddd 6 0 0 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 MTYPE_NO_PTE_MODE 30 30 mmCPF_UTCL1_CNTL 0 0x1dde 8 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 MTYPE_NO_PTE_MODE 30 30 FORCE_NO_EXE 31 31 mmCP_AQL_SMM_STATUS 0 0x1ddf 1 0 0 AQL_QUEUE_SMM 0 31 mmCP_RB0_BASE 0 0x1de0 1 0 0 RB_BASE 0 31 mmCP_RB_BASE 0 0x1de0 1 0 0 RB_BASE 0 31 mmCP_RB0_CNTL 0 0x1de1 11 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 CE_HQD_NEQ_RB_HQD 30 30 RB_RPTR_WR_ENA 31 31 mmCP_RB_CNTL 0 0x1de1 12 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 KMD_QUEUE 29 29 CE_HQD_NEQ_RB_HQD 30 30 RB_RPTR_WR_ENA 31 31 mmCP_RB_RPTR_WR 0 0x1de2 1 0 0 RB_RPTR_WR 0 19 mmCP_RB0_RPTR_ADDR 0 0x1de3 1 0 0 RB_RPTR_ADDR 2 31 mmCP_RB_RPTR_ADDR 0 0x1de3 1 0 0 RB_RPTR_ADDR 2 31 mmCP_RB0_RPTR_ADDR_HI 0 0x1de4 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_RB_RPTR_ADDR_HI 0 0x1de4 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_RB0_BUFSZ_MASK 0 0x1de5 1 0 0 DATA 0 19 mmCP_RB_BUFSZ_MASK 0 0x1de5 1 0 0 DATA 0 19 mmCP_INT_CNTL 0 0x1de9 19 0 0 RESUME_INT_ENABLE 8 8 SUSPEND_INT_ENABLE 9 9 DMA_WATCH_INT_ENABLE 10 10 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_STATUS 0 0x1dea 19 0 0 RESUME_INT_STAT 8 8 SUSPEND_INT_STAT 9 9 DMA_WATCH_INT_STAT 10 10 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_DEVICE_ID 0 0x1deb 1 0 0 DEVICE_ID 0 7 mmCP_ME0_PIPE_PRIORITY_CNTS 0 0x1dec 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_RING_PRIORITY_CNTS 0 0x1dec 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME0_PIPE0_PRIORITY 0 0x1ded 1 0 0 PRIORITY 0 1 mmCP_RING0_PRIORITY 0 0x1ded 1 0 0 PRIORITY 0 1 mmCP_ME0_PIPE1_PRIORITY 0 0x1dee 1 0 0 PRIORITY 0 1 mmCP_RING1_PRIORITY 0 0x1dee 1 0 0 PRIORITY 0 1 mmCP_ME0_PIPE2_PRIORITY 0 0x1def 1 0 0 PRIORITY 0 1 mmCP_RING2_PRIORITY 0 0x1def 1 0 0 PRIORITY 0 1 mmCP_FATAL_ERROR 0 0x1df0 5 0 0 CPF_FATAL_ERROR 0 0 CPG_FATAL_ERROR 1 1 GFX_HALT_PROC 2 2 DIS_CPG_FATAL_ERROR 3 3 CPG_TAG_FATAL_ERROR_EN 4 4 mmCP_RB_VMID 0 0x1df1 3 0 0 RB0_VMID 0 3 RB1_VMID 8 11 RB2_VMID 16 19 mmCP_ME0_PIPE0_VMID 0 0x1df2 1 0 0 VMID 0 3 mmCP_ME0_PIPE1_VMID 0 0x1df3 1 0 0 VMID 0 3 mmCP_RB0_WPTR 0 0x1df4 1 0 0 RB_WPTR 0 31 mmCP_RB_WPTR 0 0x1df4 1 0 0 RB_WPTR 0 31 mmCP_RB0_WPTR_HI 0 0x1df5 1 0 0 RB_WPTR 0 31 mmCP_RB_WPTR_HI 0 0x1df5 1 0 0 RB_WPTR 0 31 mmCP_RB1_WPTR 0 0x1df6 1 0 0 RB_WPTR 0 31 mmCP_RB1_WPTR_HI 0 0x1df7 1 0 0 RB_WPTR 0 31 mmCP_RB2_WPTR 0 0x1df8 1 0 0 RB_WPTR 0 19 mmCP_PROCESS_QUANTUM 0 0x1df9 4 0 0 QUANTUM_DURATION 0 27 TIMER_EXPIRED 28 28 QUANTUM_SCALE 29 30 QUANTUM_EN 31 31 mmCP_RB_DOORBELL_RANGE_LOWER 0 0x1dfa 1 0 0 DOORBELL_RANGE_LOWER 2 11 mmCP_RB_DOORBELL_RANGE_UPPER 0 0x1dfb 1 0 0 DOORBELL_RANGE_UPPER 2 11 mmCP_MEC_DOORBELL_RANGE_LOWER 0 0x1dfc 1 0 0 DOORBELL_RANGE_LOWER 2 11 mmCP_MEC_DOORBELL_RANGE_UPPER 0 0x1dfd 1 0 0 DOORBELL_RANGE_UPPER 2 11 mmCPG_UTCL1_ERROR 0 0x1dfe 1 0 0 ERROR_DETECTED_HALT 0 0 mmCPC_UTCL1_ERROR 0 0x1dff 1 0 0 ERROR_DETECTED_HALT 0 0 mmCP_RB1_BASE 0 0x1e00 1 0 0 RB_BASE 0 31 mmCP_RB1_CNTL 0 0x1e01 12 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 KMD_QUEUE 29 29 CE_HQD_NEQ_RB_HQD 30 30 RB_RPTR_WR_ENA 31 31 mmCP_RB1_RPTR_ADDR 0 0x1e02 1 0 0 RB_RPTR_ADDR 2 31 mmCP_RB1_RPTR_ADDR_HI 0 0x1e03 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_RB1_BUFSZ_MASK 0 0x1e04 1 0 0 DATA 0 19 mmCP_RB2_BASE 0 0x1e05 1 0 0 RB_BASE 0 31 mmCP_RB2_CNTL 0 0x1e06 12 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 KMD_QUEUE 29 29 CE_HQD_NEQ_RB_HQD 30 30 RB_RPTR_WR_ENA 31 31 mmCP_RB2_RPTR_ADDR 0 0x1e07 1 0 0 RB_RPTR_ADDR 2 31 mmCP_RB2_RPTR_ADDR_HI 0 0x1e08 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_INT_CNTL_RING0 0 0x1e0a 19 0 0 RESUME_INT_ENABLE 8 8 SUSPEND_INT_ENABLE 9 9 DMA_WATCH_INT_ENABLE 10 10 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_CNTL_RING1 0 0x1e0b 17 0 0 DMA_WATCH_INT_ENABLE 10 10 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_CNTL_RING2 0 0x1e0c 17 0 0 DMA_WATCH_INT_ENABLE 10 10 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_STATUS_RING0 0 0x1e0d 19 0 0 RESUME_INT_STAT 8 8 SUSPEND_INT_STAT 9 9 DMA_WATCH_INT_STAT 10 10 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 GCNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_INT_STATUS_RING1 0 0x1e0e 17 0 0 DMA_WATCH_INT_STAT 10 10 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_INT_STATUS_RING2 0 0x1e0f 17 0 0 DMA_WATCH_INT_STAT 10 10 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_ME_F32_INTERRUPT 0 0x1e13 4 0 0 ECC_ERROR_INT 0 0 TIME_STAMP_INT 1 1 ME_F32_INT_2 2 2 ME_F32_INT_3 3 3 mmCP_PFP_F32_INTERRUPT 0 0x1e14 4 0 0 ECC_ERROR_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 PFP_F32_INT_3 3 3 mmCP_CE_F32_INTERRUPT 0 0x1e15 4 0 0 ECC_ERROR_INT 0 0 RESERVED_BIT_ERR_INT 1 1 CE_F32_INT_2 2 2 CE_F32_INT_3 3 3 mmCP_MEC1_F32_INTERRUPT 0 0x1e16 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 mmCP_MEC2_F32_INTERRUPT 0 0x1e17 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 mmCP_PWR_CNTL 0 0x1e18 14 0 0 GFX_CLK_HALT_ME0_PIPE0 0 0 GFX_CLK_HALT_ME0_PIPE1 1 1 CMP_CLK_HALT_ME1_PIPE0 8 8 CMP_CLK_HALT_ME1_PIPE1 9 9 CMP_CLK_HALT_ME1_PIPE2 10 10 CMP_CLK_HALT_ME1_PIPE3 11 11 CMP_CLK_HALT_ME2_PIPE0 16 16 CMP_CLK_HALT_ME2_PIPE1 17 17 CMP_CLK_HALT_ME2_PIPE2 18 18 CMP_CLK_HALT_ME2_PIPE3 19 19 CMP_CLK_HALT_ME3_PIPE0 20 20 CMP_CLK_HALT_ME3_PIPE1 21 21 CMP_CLK_HALT_ME3_PIPE2 22 22 CMP_CLK_HALT_ME3_PIPE3 23 23 mmCP_MEM_SLP_CNTL 0 0x1e19 7 0 0 CP_MEM_LS_EN 0 0 CP_MEM_DS_EN 1 1 RESERVED 2 6 CP_LS_DS_BUSY_OVERRIDE 7 7 CP_MEM_LS_ON_DELAY 8 15 CP_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 mmCP_ECC_FIRSTOCCURRENCE 0 0x1e1a 6 0 0 INTERFACE 0 1 CLIENT 4 7 ME 8 9 PIPE 10 11 QUEUE 12 14 VMID 16 19 mmCP_ECC_FIRSTOCCURRENCE_RING0 0 0x1e1b 1 0 0 OBSOLETE 0 31 mmCP_ECC_FIRSTOCCURRENCE_RING1 0 0x1e1c 1 0 0 OBSOLETE 0 31 mmCP_ECC_FIRSTOCCURRENCE_RING2 0 0x1e1d 1 0 0 OBSOLETE 0 31 mmGB_EDC_MODE 0 0x1e1e 6 0 0 FORCE_SEC_ON_DED 15 15 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmCP_PQ_WPTR_POLL_CNTL 0 0x1e23 4 0 0 PERIOD 0 7 DISABLE_PEND_REQ_ONE_SHOT 29 29 POLL_ACTIVE 30 30 EN 31 31 mmCP_PQ_WPTR_POLL_CNTL1 0 0x1e24 1 0 0 QUEUE_MASK 0 31 mmCP_ME1_PIPE0_INT_CNTL 0 0x1e25 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE1_INT_CNTL 0 0x1e26 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE2_INT_CNTL 0 0x1e27 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE3_INT_CNTL 0 0x1e28 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE0_INT_CNTL 0 0x1e29 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE1_INT_CNTL 0 0x1e2a 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE2_INT_CNTL 0 0x1e2b 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE3_INT_CNTL 0 0x1e2c 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE0_INT_STATUS 0 0x1e2d 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE1_INT_STATUS 0 0x1e2e 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE2_INT_STATUS 0 0x1e2f 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE3_INT_STATUS 0 0x1e30 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE0_INT_STATUS 0 0x1e31 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE1_INT_STATUS 0 0x1e32 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE2_INT_STATUS 0 0x1e33 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE3_INT_STATUS 0 0x1e34 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_GFX_QUEUE_INDEX 0 0x1e37 3 0 0 QUEUE_ACCESS 0 0 PIPE_ID 4 5 QUEUE_ID 8 10 mmCC_GC_EDC_CONFIG 0 0x1e38 1 0 0 DIS_EDC 1 1 mmCP_ME1_PIPE_PRIORITY_CNTS 0 0x1e39 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME1_PIPE0_PRIORITY 0 0x1e3a 1 0 0 PRIORITY 0 1 mmCP_ME1_PIPE1_PRIORITY 0 0x1e3b 1 0 0 PRIORITY 0 1 mmCP_ME1_PIPE2_PRIORITY 0 0x1e3c 1 0 0 PRIORITY 0 1 mmCP_ME1_PIPE3_PRIORITY 0 0x1e3d 1 0 0 PRIORITY 0 1 mmCP_ME2_PIPE_PRIORITY_CNTS 0 0x1e3e 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME2_PIPE0_PRIORITY 0 0x1e3f 1 0 0 PRIORITY 0 1 mmCP_ME2_PIPE1_PRIORITY 0 0x1e40 1 0 0 PRIORITY 0 1 mmCP_ME2_PIPE2_PRIORITY 0 0x1e41 1 0 0 PRIORITY 0 1 mmCP_ME2_PIPE3_PRIORITY 0 0x1e42 1 0 0 PRIORITY 0 1 mmCP_CE_PRGRM_CNTR_START 0 0x1e43 1 0 0 IP_START 0 19 mmCP_PFP_PRGRM_CNTR_START 0 0x1e44 1 0 0 IP_START 0 19 mmCP_ME_PRGRM_CNTR_START 0 0x1e45 1 0 0 IP_START 0 19 mmCP_MEC1_PRGRM_CNTR_START 0 0x1e46 1 0 0 IP_START 0 19 mmCP_MEC2_PRGRM_CNTR_START 0 0x1e47 1 0 0 IP_START 0 19 mmCP_CE_INTR_ROUTINE_START 0 0x1e48 1 0 0 IR_START 0 19 mmCP_PFP_INTR_ROUTINE_START 0 0x1e49 1 0 0 IR_START 0 19 mmCP_ME_INTR_ROUTINE_START 0 0x1e4a 1 0 0 IR_START 0 19 mmCP_MEC1_INTR_ROUTINE_START 0 0x1e4b 1 0 0 IR_START 0 19 mmCP_MEC2_INTR_ROUTINE_START 0 0x1e4c 1 0 0 IR_START 0 19 mmCP_CONTEXT_CNTL 0 0x1e4d 4 0 0 ME0PIPE0_MAX_GE_CNTX 0 2 ME0PIPE0_MAX_PIPE_CNTX 4 6 ME0PIPE1_MAX_GE_CNTX 16 18 ME0PIPE1_MAX_PIPE_CNTX 20 22 mmCP_MAX_CONTEXT 0 0x1e4e 1 0 0 MAX_CONTEXT 0 2 mmCP_IQ_WAIT_TIME1 0 0x1e4f 4 0 0 IB_OFFLOAD 0 7 ATOMIC_OFFLOAD 8 15 WRM_OFFLOAD 16 23 GWS 24 31 mmCP_IQ_WAIT_TIME2 0 0x1e50 4 0 0 QUE_SLEEP 0 7 SCH_WAVE 8 15 SEM_REARM 16 23 DEQ_RETRY 24 31 mmCP_RB0_BASE_HI 0 0x1e51 1 0 0 RB_BASE_HI 0 7 mmCP_RB1_BASE_HI 0 0x1e52 1 0 0 RB_BASE_HI 0 7 mmCP_VMID_RESET 0 0x1e53 3 0 0 RESET_REQUEST 0 15 PIPE0_QUEUES 16 23 PIPE1_QUEUES 24 31 mmCPC_INT_CNTL 0 0x1e54 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCPC_INT_STATUS 0 0x1e55 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_VMID_PREEMPT 0 0x1e56 2 0 0 PREEMPT_REQUEST 0 15 VIRT_COMMAND 16 19 mmCPC_INT_CNTX_ID 0 0x1e57 1 0 0 CNTX_ID 0 31 mmCP_PQ_STATUS 0 0x1e58 4 0 0 DOORBELL_UPDATED 0 0 DOORBELL_ENABLE 1 1 DOORBELL_UPDATED_EN 2 2 DOORBELL_UPDATED_MODE 3 3 mmCP_MEC1_F32_INT_DIS 0 0x1e5d 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 mmCP_MEC2_F32_INT_DIS 0 0x1e5e 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 mmCP_VMID_STATUS 0 0x1e5f 2 0 0 PREEMPT_DE_STATUS 0 15 PREEMPT_CE_STATUS 16 31 mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0 0x1e60 1 0 0 ADDR 12 31 mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0 0x1e61 1 0 0 ADDR_HI 0 15 mmCPC_SUSPEND_CTX_SAVE_CONTROL 0 0x1e62 2 0 0 POLICY 3 4 EXE_DISABLE 23 23 mmCPC_SUSPEND_CNTL_STACK_OFFSET 0 0x1e63 1 0 0 OFFSET 2 14 mmCPC_SUSPEND_CNTL_STACK_SIZE 0 0x1e64 1 0 0 SIZE 12 14 mmCPC_SUSPEND_WG_STATE_OFFSET 0 0x1e65 1 0 0 OFFSET 2 24 mmCPC_SUSPEND_CTX_SAVE_SIZE 0 0x1e66 1 0 0 SIZE 12 24 mmCPC_OS_PIPES 0 0x1e67 1 0 0 OS_PIPES 0 7 mmCP_SUSPEND_RESUME_REQ 0 0x1e68 2 0 0 SUSPEND_REQ 0 0 RESUME_REQ 1 1 mmCP_SUSPEND_CNTL 0 0x1e69 4 0 0 SUSPEND_MODE 0 0 SUSPEND_ENABLE 1 1 RESUME_LOCK 2 2 ACE_SUSPEND_ACTIVE 3 3 mmCP_IQ_WAIT_TIME3 0 0x1e6a 1 0 0 SUSPEND_QUE 0 7 mmCPC_DDID_BASE_ADDR_LO 0 0x1e6b 1 0 0 BASE_ADDR_LO 6 31 mmCP_DDID_BASE_ADDR_LO 0 0x1e6b 1 0 0 BASE_ADDR_LO 6 31 mmCPC_DDID_BASE_ADDR_HI 0 0x1e6c 1 0 0 BASE_ADDR_HI 0 15 mmCP_DDID_BASE_ADDR_HI 0 0x1e6c 1 0 0 BASE_ADDR_HI 0 15 mmCPC_DDID_CNTL 0 0x1e6d 6 0 0 THRESHOLD 0 7 SIZE 16 16 NO_RING_MEMORY 19 19 POLICY 28 29 MODE 30 30 ENABLE 31 31 mmCP_DDID_CNTL 0 0x1e6d 8 0 0 THRESHOLD 0 7 SIZE 16 16 NO_RING_MEMORY 19 19 VMID 20 23 VMID_SEL 24 24 POLICY 28 29 MODE 30 30 ENABLE 31 31 mmCP_GFX_DDID_INFLIGHT_COUNT 0 0x1e6e 1 0 0 COUNT 0 15 mmCP_GFX_DDID_WPTR 0 0x1e6f 1 0 0 COUNT 0 15 mmCP_GFX_DDID_RPTR 0 0x1e70 1 0 0 COUNT 0 15 mmCP_GFX_DDID_DELTA_RPT_COUNT 0 0x1e71 1 0 0 COUNT 0 7 mmCP_GFX_HPD_STATUS0 0 0x1e72 9 0 0 QUEUE_STATE 0 4 MAPPED_QUEUE 5 7 QUEUE_AVAILABLE 8 15 FORCE_MAPPED_QUEUE 16 18 FORCE_QUEUE_STATE 20 24 SUSPEND_REQ 28 28 ENABLE_OVERIDE_QUEUEID 29 29 OVERIDE_QUEUEID 30 30 FORCE_QUEUE 31 31 mmCP_GFX_HPD_CONTROL0 0 0x1e73 3 0 0 SUSPEND_ENABLE 0 0 PIPE_HOLDING 4 4 RB_CE_ROQ_CNTL 8 8 mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0 0x1e74 1 0 0 ADDR_LO 2 31 mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0 0x1e75 2 0 0 ADDR_HI 0 15 RSVD 16 31 mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0 0x1e76 1 0 0 DATA_LO 0 31 mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0 0x1e77 1 0 0 DATA_HI 0 31 mmCP_GFX_INDEX_MUTEX 0 0x1e78 2 0 0 REQUEST 0 0 CLIENTID 1 3 mmCP_GFX_MQD_BASE_ADDR 0 0x1e7e 1 0 0 BASE_ADDR 2 31 mmCP_GFX_MQD_BASE_ADDR_HI 0 0x1e7f 2 0 0 BASE_ADDR_HI 0 15 APP_VMID 28 31 mmCP_GFX_HQD_ACTIVE 0 0x1e80 1 0 0 ACTIVE 0 0 mmCP_GFX_HQD_VMID 0 0x1e81 1 0 0 VMID 0 3 mmCP_GFX_HQD_QUEUE_PRIORITY 0 0x1e84 1 0 0 PRIORITY_LEVEL 0 3 mmCP_GFX_HQD_QUANTUM 0 0x1e85 4 0 0 QUANTUM_EN 0 0 QUANTUM_SCALE 3 4 QUANTUM_DURATION 8 15 QUANTUM_ACTIVE 31 31 mmCP_GFX_HQD_BASE 0 0x1e86 1 0 0 RB_BASE 0 31 mmCP_GFX_HQD_BASE_HI 0 0x1e87 1 0 0 RB_BASE_HI 0 7 mmCP_GFX_HQD_RPTR 0 0x1e88 1 0 0 RB_RPTR 0 19 mmCP_GFX_HQD_RPTR_ADDR 0 0x1e89 1 0 0 RB_RPTR_ADDR 2 31 mmCP_GFX_HQD_RPTR_ADDR_HI 0 0x1e8a 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_RB_WPTR_POLL_ADDR_LO 0 0x1e8b 1 0 0 RB_WPTR_POLL_ADDR_LO 2 31 mmCP_RB_WPTR_POLL_ADDR_HI 0 0x1e8c 1 0 0 RB_WPTR_POLL_ADDR_HI 0 15 mmCP_RB_DOORBELL_CONTROL 0 0x1e8d 4 0 0 DOORBELL_BIF_DROP 1 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_GFX_HQD_OFFSET 0 0x1e8e 2 0 0 RB_OFFSET 0 19 DISABLE_RB_OFFSET 31 31 mmCP_GFX_HQD_CNTL 0 0x1e8f 13 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 BUF_SWAP 16 17 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 KMD_QUEUE 29 29 CE_HQD_NEQ_RB_HQD 30 30 RB_RPTR_WR_ENA 31 31 mmCP_GFX_HQD_CSMD_RPTR 0 0x1e90 1 0 0 RB_RPTR 0 19 mmCP_GFX_HQD_WPTR 0 0x1e91 1 0 0 RB_WPTR 0 31 mmCP_GFX_HQD_WPTR_HI 0 0x1e92 1 0 0 RB_WPTR 0 31 mmCP_GFX_HQD_DEQUEUE_REQUEST 0 0x1e93 4 0 0 DEQUEUE_REQ 0 0 IQ_REQ_PEND 4 4 IQ_REQ_PEND_EN 9 9 DEQUEUE_REQ_EN 10 10 mmCP_GFX_HQD_MAPPED 0 0x1e94 1 0 0 MAPPED 0 0 mmCP_GFX_HQD_QUE_MGR_CONTROL 0 0x1e95 1 0 0 CONTROL 0 23 mmCP_GFX_HQD_HQ_STATUS0 0 0x1e98 4 0 0 DEQUEUE_STATUS 0 0 OS_PREEMPT_STATUS 4 5 PREEMPT_ACK 6 6 QUEUE_IDLE 30 30 mmCP_GFX_HQD_HQ_CONTROL0 0 0x1e99 1 0 0 COMMAND 0 3 mmCP_GFX_MQD_CONTROL 0 0x1e9a 6 0 0 VMID 0 3 PRIV_STATE 8 8 PROCESSING_MQD 12 12 PROCESSING_MQD_EN 13 13 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_HQD_GFX_CONTROL 0 0x1e9f 3 0 0 MESSAGE 0 3 MISC 4 14 DB_UPDATED_MSG_EN 15 15 mmCP_HQD_GFX_STATUS 0 0x1ea0 1 0 0 STATUS 0 15 mmCP_GFX_HQD_CE_RPTR_WR 0 0x1ea1 1 0 0 RB_RPTR_WR 0 19 mmCP_GFX_HQD_CE_BASE 0 0x1ea2 1 0 0 RB_BASE 0 31 mmCP_GFX_HQD_CE_BASE_HI 0 0x1ea3 1 0 0 RB_BASE_HI 0 7 mmCP_GFX_HQD_CE_RPTR 0 0x1ea4 1 0 0 RB_RPTR 0 19 mmCP_GFX_HQD_CE_RPTR_ADDR 0 0x1ea5 1 0 0 RB_RPTR_ADDR 2 31 mmCP_GFX_HQD_CE_RPTR_ADDR_HI 0 0x1ea6 1 0 0 RB_RPTR_ADDR_HI 0 15 mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO 0 0x1ea7 1 0 0 RB_WPTR_POLL_ADDR_LO 2 31 mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI 0 0x1ea8 1 0 0 RB_WPTR_POLL_ADDR_HI 0 15 mmCP_GFX_HQD_CE_OFFSET 0 0x1ea9 2 0 0 RB_OFFSET 0 19 DISABLE_RB_OFFSET 31 31 mmCP_GFX_HQD_CE_CNTL 0 0x1eaa 10 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 RB_NON_PRIV 15 15 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_EXE 28 28 RB_RPTR_WR_ENA 31 31 mmCP_GFX_HQD_CE_CSMD_RPTR 0 0x1eab 1 0 0 RB_RPTR 0 19 mmCP_GFX_HQD_CE_WPTR 0 0x1eac 1 0 0 RB_WPTR 0 31 mmCP_GFX_HQD_CE_WPTR_HI 0 0x1ead 1 0 0 RB_WPTR 0 31 mmCP_CE_DOORBELL_CONTROL 0 0x1eae 4 0 0 DOORBELL_BIF_DROP 1 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_DMA_WATCH0_ADDR_LO 0 0x1ec0 2 0 0 RSVD 0 6 ADDR_LO 7 31 mmCP_DMA_WATCH0_ADDR_HI 0 0x1ec1 2 0 0 ADDR_HI 0 15 RSVD 16 31 mmCP_DMA_WATCH0_MASK 0 0x1ec2 2 0 0 RSVD 0 6 MASK 7 31 mmCP_DMA_WATCH0_CNTL 0 0x1ec3 6 0 0 VMID 0 3 RSVD1 4 7 WATCH_READS 8 8 WATCH_WRITES 9 9 ANY_VMID 10 10 RSVD2 11 31 mmCP_DMA_WATCH1_ADDR_LO 0 0x1ec4 2 0 0 RSVD 0 6 ADDR_LO 7 31 mmCP_DMA_WATCH1_ADDR_HI 0 0x1ec5 2 0 0 ADDR_HI 0 15 RSVD 16 31 mmCP_DMA_WATCH1_MASK 0 0x1ec6 2 0 0 RSVD 0 6 MASK 7 31 mmCP_DMA_WATCH1_CNTL 0 0x1ec7 6 0 0 VMID 0 3 RSVD1 4 7 WATCH_READS 8 8 WATCH_WRITES 9 9 ANY_VMID 10 10 RSVD2 11 31 mmCP_DMA_WATCH2_ADDR_LO 0 0x1ec8 2 0 0 RSVD 0 6 ADDR_LO 7 31 mmCP_DMA_WATCH2_ADDR_HI 0 0x1ec9 2 0 0 ADDR_HI 0 15 RSVD 16 31 mmCP_DMA_WATCH2_MASK 0 0x1eca 2 0 0 RSVD 0 6 MASK 7 31 mmCP_DMA_WATCH2_CNTL 0 0x1ecb 6 0 0 VMID 0 3 RSVD1 4 7 WATCH_READS 8 8 WATCH_WRITES 9 9 ANY_VMID 10 10 RSVD2 11 31 mmCP_DMA_WATCH3_ADDR_LO 0 0x1ecc 2 0 0 RSVD 0 6 ADDR_LO 7 31 mmCP_DMA_WATCH3_ADDR_HI 0 0x1ecd 2 0 0 ADDR_HI 0 15 RSVD 16 31 mmCP_DMA_WATCH3_MASK 0 0x1ece 2 0 0 RSVD 0 6 MASK 7 31 mmCP_DMA_WATCH3_CNTL 0 0x1ecf 6 0 0 VMID 0 3 RSVD1 4 7 WATCH_READS 8 8 WATCH_WRITES 9 9 ANY_VMID 10 10 RSVD2 11 31 mmCP_DMA_WATCH_STAT_ADDR_LO 0 0x1ed0 1 0 0 ADDR_LO 2 31 mmCP_DMA_WATCH_STAT_ADDR_HI 0 0x1ed1 1 0 0 ADDR_HI 0 15 mmCP_DMA_WATCH_STAT 0 0x1ed2 7 0 0 VMID 0 3 QUEUE_ID 4 6 CLIENT_ID 8 10 PIPE 12 13 WATCH_ID 16 17 RD_WR 20 20 TRAP_FLAG 31 31 mmCP_PFP_JT_STAT 0 0x1ed3 2 0 0 JT_LOADED 0 1 WR_MASK 16 17 mmCP_CE_JT_STAT 0 0x1ed4 2 0 0 JT_LOADED 0 1 WR_MASK 16 17 mmCP_MEC_JT_STAT 0 0x1ed5 2 0 0 JT_LOADED 0 7 WR_MASK 16 23 mmCP_FETCHER_SOURCE 0 0x1f1e 1 0 0 ME_SRC 0 0 mmCP_CE_CS_PARTITION_INDEX 0 0x1f1f 1 0 0 CS1_INDEX 0 16 mmCP_RB_DOORBELL_CLEAR 0 0x1f28 7 0 0 MAPPED_QUEUE 0 2 MAPPED_QUE_DOORBELL_EN_CLEAR 8 8 MAPPED_QUE_DOORBELL_HIT_CLEAR 9 9 MASTER_DOORBELL_EN_CLEAR 10 10 MASTER_DOORBELL_HIT_CLEAR 11 11 QUEUES_DOORBELL_EN_CLEAR 12 12 QUEUES_DOORBELL_HIT_CLEAR 13 13 mmCP_RB0_ACTIVE 0 0x1f40 1 0 0 ACTIVE 0 0 mmCP_RB_ACTIVE 0 0x1f40 1 0 0 ACTIVE 0 0 mmCP_RB1_ACTIVE 0 0x1f41 1 0 0 ACTIVE 0 0 mmCP_RB_STATUS 0 0x1f43 2 0 0 DOORBELL_UPDATED 0 0 DOORBELL_ENABLE 1 1 mmCPG_RCIU_CAM_INDEX 0 0x1f44 1 0 0 INDEX 0 4 mmCPG_RCIU_CAM_DATA 0 0x1f45 1 0 0 DATA 0 31 mmCPG_RCIU_CAM_DATA_PHASE0 0 0x1f45 4 0 0 ADDR 0 17 PIPE0_EN 24 24 PIPE1_EN 25 25 SKIP_WR 31 31 mmCPG_RCIU_CAM_DATA_PHASE1 0 0x1f45 1 0 0 MASK 0 31 mmCPG_RCIU_CAM_DATA_PHASE2 0 0x1f45 1 0 0 VALUE 0 31 mmCP_GPU_TIMESTAMP_OFFSET_LO 0 0x1f4c 1 0 0 OFFSET_LO 0 31 mmCP_GPU_TIMESTAMP_OFFSET_HI 0 0x1f4d 1 0 0 OFFSET_HI 0 31 mmCPF_GCR_CNTL 0 0x1f53 1 0 0 GCR_GL_CMD 0 18 mmCPG_UTCL1_STATUS 0 0x1f54 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmCPC_UTCL1_STATUS 0 0x1f55 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmCPF_UTCL1_STATUS 0 0x1f56 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 mmCP_SD_CNTL 0 0x1f57 10 0 0 CPF_EN 0 0 CPG_EN 1 1 CPC_EN 2 2 RLC_EN 3 3 SPI_EN 4 4 GE_EN 5 5 UTCL1_EN 6 6 EA_EN 9 9 SDMA_EN 10 10 SD_VMIDVEC_OVERRIDE 31 31 mmCP_SOFT_RESET_CNTL 0 0x1f59 7 0 0 CMP_ONLY_SOFT_RESET 0 0 GFX_ONLY_SOFT_RESET 1 1 CMP_HQD_REG_RESET 2 2 CMP_INTR_REG_RESET 3 3 CMP_HQD_QUEUE_DOORBELL_RESET 4 4 GFX_RB_DOORBELL_RESET 5 5 GFX_INTR_REG_RESET 6 6 mmCP_CPC_GFX_CNTL 0 0x1f5a 4 0 0 QUEUEID 0 2 PIPEID 3 4 MEID 5 6 VALID 7 7 mmSPI_ARB_PRIORITY 0 0x1f60 8 0 0 PIPE_ORDER_TS0 0 2 PIPE_ORDER_TS1 3 5 PIPE_ORDER_TS2 6 8 PIPE_ORDER_TS3 9 11 TS0_DUR_MULT 12 13 TS1_DUR_MULT 14 15 TS2_DUR_MULT 16 17 TS3_DUR_MULT 18 19 mmSPI_ARB_CYCLES_0 0 0x1f61 2 0 0 TS0_DURATION 0 15 TS1_DURATION 16 31 mmSPI_ARB_CYCLES_1 0 0x1f62 2 0 0 TS2_DURATION 0 15 TS3_DURATION 16 31 mmSPI_WCL_PIPE_PERCENT_GFX 0 0x1f67 3 0 0 VALUE 0 6 HS_GRP_VALUE 12 16 GS_GRP_VALUE 22 26 mmSPI_WCL_PIPE_PERCENT_HP3D 0 0x1f68 3 0 0 VALUE 0 6 HS_GRP_VALUE 12 16 GS_GRP_VALUE 22 26 mmSPI_WCL_PIPE_PERCENT_CS0 0 0x1f69 1 0 0 VALUE 0 6 mmSPI_WCL_PIPE_PERCENT_CS1 0 0x1f6a 1 0 0 VALUE 0 6 mmSPI_WCL_PIPE_PERCENT_CS2 0 0x1f6b 1 0 0 VALUE 0 6 mmSPI_WCL_PIPE_PERCENT_CS3 0 0x1f6c 1 0 0 VALUE 0 6 mmSPI_GDBG_WAVE_CNTL 0 0x1f71 2 0 0 STALL_RA 0 0 STALL_VMID 1 16 mmSPI_GDBG_TRAP_MASK 0 0x1f73 2 0 0 EXCP_EN 0 8 REPLACE 9 9 mmSPI_GDBG_WAVE_CNTL2 0 0x1f74 2 0 0 VMID_MASK 0 15 MODE 16 17 mmSPI_COMPUTE_QUEUE_RESET 0 0x1f7b 1 0 0 RESET 0 0 mmSPI_RESOURCE_RESERVE_CU_0 0 0x1f7c 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_1 0 0x1f7d 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_2 0 0x1f7e 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_3 0 0x1f7f 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_4 0 0x1f80 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_5 0 0x1f81 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_6 0 0x1f82 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_7 0 0x1f83 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_8 0 0x1f84 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_9 0 0x1f85 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_EN_CU_0 0 0x1f86 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_1 0 0x1f87 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_2 0 0x1f88 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_3 0 0x1f89 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_4 0 0x1f8a 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_5 0 0x1f8b 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_6 0 0x1f8c 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_7 0 0x1f8d 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_8 0 0x1f8e 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_RESOURCE_RESERVE_EN_CU_9 0 0x1f8f 3 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 mmSPI_COMPUTE_WF_CTX_SAVE 0 0x1f9c 5 0 0 INITIATE 0 0 GDS_INTERRUPT_EN 1 1 DONE_INTERRUPT_EN 2 2 GDS_REQ_BUSY 30 30 SAVE_BUSY 31 31 mmSPI_ARB_CNTL_0 0 0x1f9d 3 0 0 EXP_ARB_COL_WT 0 3 EXP_ARB_POS_WT 4 7 EXP_ARB_GDS_WT 8 11 mmSPI_FEATURE_CTRL 0 0x1f9e 8 0 0 CU_LOCKING_FAIRNESS_DISABLE 0 0 ALLOCATION_RATE_THROTTLE_THRESHOLD 2 6 ACTIVE_HARD_LOCK_LIMIT 7 11 LR_IMBALANCE_THRESHOLD 12 17 RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN 18 18 BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN 19 19 BUS_ACTIVITY_THRESHOLD 20 27 TUNNELING_WAVE_LIMIT 28 31 mmSPI_SHADER_RSRC_LIMIT_CTRL 0 0x1f9f 8 0 0 WAVES_PER_SIMD32 0 4 VGPR_PER_SIMD32 5 11 VGPR_WRAP_DISABLE 12 12 BARRIER_LIMIT 13 18 BARRIER_LIMIT_HIERARCHY_LEVEL 19 19 LDS_LIMIT 20 27 LDS_LIMIT_HIERARCHY_LEVEL 28 28 PERFORMANCE_LIMIT_ENABLE 31 31 mmCP_HPD_MES_ROQ_OFFSETS 0 0x1fa4 3 0 0 IQ_OFFSET 0 2 PQ_OFFSET 8 13 IB_OFFSET 16 22 mmCP_HPD_ROQ_OFFSETS 0 0x1fa4 3 0 0 IQ_OFFSET 0 2 PQ_OFFSET 8 13 IB_OFFSET 16 22 mmCP_HPD_STATUS0 0 0x1fa5 11 0 0 QUEUE_STATE 0 4 MAPPED_QUEUE 5 7 QUEUE_AVAILABLE 8 15 FETCHING_MQD 16 16 PEND_TXFER_SIZE_PQIB 17 17 PEND_TXFER_SIZE_IQ 18 18 FORCE_QUEUE_STATE 20 24 MASTER_QUEUE_IDLE_DIS 27 27 ENABLE_OFFLOAD_CHECK 28 29 FREEZE_QUEUE_STATE 30 30 FORCE_QUEUE 31 31 mmCP_HPD_UTCL1_CNTL 0 0x1fa6 1 0 0 SELECT 0 3 mmCP_HPD_UTCL1_ERROR 0 0x1fa7 3 0 0 ADDR_HI 0 15 TYPE 16 16 VMID 20 23 mmCP_HPD_UTCL1_ERROR_ADDR 0 0x1fa8 1 0 0 ADDR 12 31 mmCP_MQD_BASE_ADDR 0 0x1fa9 1 0 0 BASE_ADDR 2 31 mmCP_MQD_BASE_ADDR_HI 0 0x1faa 1 0 0 BASE_ADDR_HI 0 15 mmCP_HQD_ACTIVE 0 0x1fab 2 0 0 ACTIVE 0 0 BUSY_GATE 1 1 mmCP_HQD_VMID 0 0x1fac 3 0 0 VMID 0 3 IB_VMID 8 11 VQID 16 25 mmCP_HQD_PERSISTENT_STATE 0 0x1fad 15 0 0 PRELOAD_REQ 0 0 SUSPEND_STATUS 7 7 PRELOAD_SIZE 8 17 WPP_CLAMP_EN 20 20 WPP_SWITCH_QOS_EN 21 21 IQ_SWITCH_QOS_EN 22 22 IB_SWITCH_QOS_EN 23 23 EOP_SWITCH_QOS_EN 24 24 PQ_SWITCH_QOS_EN 25 25 TC_OFFLOAD_QOS_EN 26 26 CACHE_FULL_PACKET_EN 27 27 RESTORE_ACTIVE 28 28 RELAUNCH_WAVES 29 29 QSWITCH_MODE 30 30 DISP_ACTIVE 31 31 mmCP_HQD_PIPE_PRIORITY 0 0x1fae 1 0 0 PIPE_PRIORITY 0 1 mmCP_HQD_QUEUE_PRIORITY 0 0x1faf 1 0 0 PRIORITY_LEVEL 0 3 mmCP_HQD_QUANTUM 0 0x1fb0 4 0 0 QUANTUM_EN 0 0 QUANTUM_SCALE 4 4 QUANTUM_DURATION 8 13 QUANTUM_ACTIVE 31 31 mmCP_HQD_PQ_BASE 0 0x1fb1 1 0 0 ADDR 0 31 mmCP_HQD_PQ_BASE_HI 0 0x1fb2 1 0 0 ADDR_HI 0 7 mmCP_HQD_PQ_RPTR 0 0x1fb3 1 0 0 CONSUMED_OFFSET 0 31 mmCP_HQD_PQ_RPTR_REPORT_ADDR 0 0x1fb4 1 0 0 RPTR_REPORT_ADDR 2 31 mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0 0x1fb5 1 0 0 RPTR_REPORT_ADDR_HI 0 15 mmCP_HQD_PQ_WPTR_POLL_ADDR 0 0x1fb6 1 0 0 WPTR_ADDR 3 31 mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0 0x1fb7 1 0 0 WPTR_ADDR_HI 0 15 mmCP_HQD_PQ_DOORBELL_CONTROL 0 0x1fb8 7 0 0 DOORBELL_MODE 0 0 DOORBELL_BIF_DROP 1 1 DOORBELL_OFFSET 2 27 DOORBELL_SOURCE 28 28 DOORBELL_SCHD_HIT 29 29 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_HQD_PQ_CONTROL 0 0x1fba 16 0 0 QUEUE_SIZE 0 5 WPTR_CARRY 6 6 RPTR_CARRY 7 7 RPTR_BLOCK_SIZE 8 13 QUEUE_FULL_EN 14 14 PQ_EMPTY 15 15 SLOT_BASED_WPTR 18 19 MIN_AVAIL_SIZE 20 21 EXE_DISABLE 23 23 CACHE_POLICY 24 25 PQ_VOLATILE 26 26 NO_UPDATE_RPTR 27 27 UNORD_DISPATCH 28 28 TUNNEL_DISPATCH 29 29 PRIV_STATE 30 30 KMD_QUEUE 31 31 mmCP_HQD_IB_BASE_ADDR 0 0x1fbb 1 0 0 IB_BASE_ADDR 2 31 mmCP_HQD_IB_BASE_ADDR_HI 0 0x1fbc 1 0 0 IB_BASE_ADDR_HI 0 15 mmCP_HQD_IB_RPTR 0 0x1fbd 1 0 0 CONSUMED_OFFSET 0 19 mmCP_HQD_IB_CONTROL 0 0x1fbe 6 0 0 IB_SIZE 0 19 MIN_IB_AVAIL_SIZE 20 21 IB_EXE_DISABLE 23 23 IB_CACHE_POLICY 24 25 IB_VOLATILE 26 26 PROCESSING_IB 31 31 mmCP_HQD_IQ_TIMER 0 0x1fbf 15 0 0 WAIT_TIME 0 7 RETRY_TYPE 8 10 IMMEDIATE_EXPIRE 11 11 INTERRUPT_TYPE 12 13 CLOCK_COUNT 14 15 INTERRUPT_SIZE 16 21 QUANTUM_TIMER 22 22 EXE_DISABLE 23 23 CACHE_POLICY 24 25 IQ_VOLATILE 26 26 QUEUE_TYPE 27 27 REARM_TIMER 28 28 PROCESS_IQ_EN 29 29 PROCESSING_IQ 30 30 ACTIVE 31 31 mmCP_HQD_IQ_RPTR 0 0x1fc0 1 0 0 OFFSET 0 5 mmCP_HQD_DEQUEUE_REQUEST 0 0x1fc1 5 0 0 DEQUEUE_REQ 0 3 IQ_REQ_PEND 4 4 DEQUEUE_INT 8 8 IQ_REQ_PEND_EN 9 9 DEQUEUE_REQ_EN 10 10 mmCP_HQD_DMA_OFFLOAD 0 0x1fc2 1 0 0 DMA_OFFLOAD 0 0 mmCP_HQD_OFFLOAD 0 0x1fc2 6 0 0 DMA_OFFLOAD 0 0 DMA_OFFLOAD_EN 1 1 AQL_OFFLOAD 2 2 AQL_OFFLOAD_EN 3 3 EOP_OFFLOAD 4 4 EOP_OFFLOAD_EN 5 5 mmCP_HQD_SEMA_CMD 0 0x1fc3 4 0 0 RETRY 0 0 RESULT 1 2 POLLING_DIS 8 8 MESSAGE_EN 9 9 mmCP_HQD_MSG_TYPE 0 0x1fc4 2 0 0 ACTION 0 2 SAVE_STATE 4 6 mmCP_HQD_ATOMIC0_PREOP_LO 0 0x1fc5 1 0 0 ATOMIC0_PREOP_LO 0 31 mmCP_HQD_ATOMIC0_PREOP_HI 0 0x1fc6 1 0 0 ATOMIC0_PREOP_HI 0 31 mmCP_HQD_ATOMIC1_PREOP_LO 0 0x1fc7 1 0 0 ATOMIC1_PREOP_LO 0 31 mmCP_HQD_ATOMIC1_PREOP_HI 0 0x1fc8 1 0 0 ATOMIC1_PREOP_HI 0 31 mmCP_HQD_HQ_SCHEDULER0 0 0x1fc9 1 0 0 SCHEDULER 0 31 mmCP_HQD_HQ_STATUS0 0 0x1fc9 9 0 0 DEQUEUE_STATUS 0 1 DEQUEUE_RETRY_CNT 2 3 RSV_6_4 4 6 SCRATCH_RAM_INIT 7 7 TCL2_DIRTY 8 8 PG_ACTIVATED 9 9 RSVR_29_10 10 29 QUEUE_IDLE 30 30 DB_UPDATED_MSG_EN 31 31 mmCP_HQD_HQ_CONTROL0 0 0x1fca 1 0 0 CONTROL 0 31 mmCP_HQD_HQ_SCHEDULER1 0 0x1fca 1 0 0 SCHEDULER 0 31 mmCP_MQD_CONTROL 0 0x1fcb 7 0 0 VMID 0 3 PRIV_STATE 8 8 PROCESSING_MQD 12 12 PROCESSING_MQD_EN 13 13 EXE_DISABLE 23 23 CACHE_POLICY 24 25 MQD_VOLATILE 26 26 mmCP_HQD_HQ_STATUS1 0 0x1fcc 1 0 0 STATUS 0 31 mmCP_HQD_HQ_CONTROL1 0 0x1fcd 1 0 0 CONTROL 0 31 mmCP_HQD_EOP_BASE_ADDR 0 0x1fce 1 0 0 BASE_ADDR 0 31 mmCP_HQD_EOP_BASE_ADDR_HI 0 0x1fcf 1 0 0 BASE_ADDR_HI 0 7 mmCP_HQD_EOP_CONTROL 0 0x1fd0 12 0 0 EOP_SIZE 0 5 PROCESSING_EOP 8 8 PROCESS_EOP_EN 12 12 PROCESSING_EOPIB 13 13 PROCESS_EOPIB_EN 14 14 HALT_FETCHER 21 21 HALT_FETCHER_EN 22 22 EXE_DISABLE 23 23 CACHE_POLICY 24 25 EOP_VOLATILE 26 26 SIG_SEM_RESULT 29 30 PEND_SIG_SEM 31 31 mmCP_HQD_EOP_RPTR 0 0x1fd1 5 0 0 RPTR 0 12 RESET_FETCHER 28 28 DEQUEUE_PEND 29 29 RPTR_EQ_CSMD_WPTR 30 30 INIT_FETCHER 31 31 mmCP_HQD_EOP_WPTR 0 0x1fd2 3 0 0 WPTR 0 12 EOP_EMPTY 15 15 EOP_AVAIL 16 28 mmCP_HQD_EOP_EVENTS 0 0x1fd3 2 0 0 EVENT_COUNT 0 11 CS_PARTIAL_FLUSH_PEND 16 16 mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0 0x1fd4 1 0 0 ADDR 12 31 mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0 0x1fd5 1 0 0 ADDR_HI 0 15 mmCP_HQD_CTX_SAVE_CONTROL 0 0x1fd6 2 0 0 POLICY 3 4 EXE_DISABLE 23 23 mmCP_HQD_CNTL_STACK_OFFSET 0 0x1fd7 1 0 0 OFFSET 2 14 mmCP_HQD_CNTL_STACK_SIZE 0 0x1fd8 1 0 0 SIZE 12 14 mmCP_HQD_WG_STATE_OFFSET 0 0x1fd9 1 0 0 OFFSET 2 24 mmCP_HQD_CTX_SAVE_SIZE 0 0x1fda 1 0 0 SIZE 12 24 mmCP_HQD_GDS_RESOURCE_STATE 0 0x1fdb 4 0 0 OA_REQUIRED 0 0 OA_ACQUIRED 1 1 GWS_SIZE 4 9 GWS_PNTR 12 17 mmCP_HQD_ERROR 0 0x1fdc 15 0 0 EDC_ERROR_ID 0 3 SUA_ERROR 4 4 AQL_ERROR 5 5 PQ_UTCL1_ERROR 8 8 IB_UTCL1_ERROR 9 9 EOP_UTCL1_ERROR 10 10 IQ_UTCL1_ERROR 11 11 RRPT_UTCL1_ERROR 12 12 WPP_UTCL1_ERROR 13 13 SEM_UTCL1_ERROR 14 14 DMA_SRC_UTCL1_ERROR 15 15 DMA_DST_UTCL1_ERROR 16 16 SR_UTCL1_ERROR 17 17 QU_UTCL1_ERROR 18 18 TC_UTCL1_ERROR 19 19 mmCP_HQD_EOP_WPTR_MEM 0 0x1fdd 1 0 0 WPTR 0 12 mmCP_HQD_AQL_CONTROL 0 0x1fde 4 0 0 CONTROL0 0 14 CONTROL0_EN 15 15 CONTROL1 16 30 CONTROL1_EN 31 31 mmCP_HQD_PQ_WPTR_LO 0 0x1fdf 1 0 0 OFFSET 0 31 mmCP_HQD_PQ_WPTR_HI 0 0x1fe0 1 0 0 DATA 0 31 mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0 0x1fe1 1 0 0 OFFSET 2 14 mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0 0x1fe2 1 0 0 CNT 0 12 mmCP_HQD_SUSPEND_WG_STATE_OFFSET 0 0x1fe3 1 0 0 OFFSET 2 24 mmCP_HQD_DDID_RPTR 0 0x1fe4 1 0 0 RPTR 0 10 mmCP_HQD_DDID_WPTR 0 0x1fe5 1 0 0 WPTR 0 10 mmCP_HQD_DDID_INFLIGHT_COUNT 0 0x1fe6 1 0 0 COUNT 0 15 mmCP_HQD_DDID_DELTA_RPT_COUNT 0 0x1fe7 1 0 0 COUNT 0 7 mmCP_HQD_DEQUEUE_STATUS 0 0x1fe8 4 0 0 DEQUEUE_STAT 0 3 SUSPEND_REQ_PEND 4 4 SUSPEND_REQ_PEND_EN 9 9 DEQUEUE_STAT_EN 10 10 mmDIDT_IND_INDEX 0 0x2020 1 0 0 DIDT_IND_INDEX 0 31 mmDIDT_IND_DATA 0 0x2021 1 0 0 DIDT_IND_DATA 0 31 mmDIDT_INDEX_AUTO_INCR_EN 0 0x2022 1 0 0 DIDT_INDEX_AUTO_INCR_EN 0 0 mmGC_CAC_CTRL_1 0 0x2024 2 0 0 CAC_WINDOW 0 23 TDP_WINDOW 24 31 mmGC_CAC_CTRL_2 0 0x2025 6 0 0 CAC_ENABLE 0 0 CAC_SOFT_CTRL_ENABLE 1 1 GC_LCAC_ENABLE 2 2 SE_LCAC_ENABLE 3 3 GC_CAC_INDEX_AUTO_INCR_EN 4 4 TOGGLE_EN 5 5 mmGC_CAC_AGGR_LOWER 0 0x2026 1 0 0 AGGR_31_0 0 31 mmGC_CAC_AGGR_UPPER 0 0x2027 1 0 0 AGGR_63_32 0 31 mmGC_CAC_SOFT_CTRL 0 0x202a 2 0 0 SOFT_SNAP 0 0 UNUSED 1 31 mmGC_EDC_CTRL 0 0x202b 15 0 0 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_ALLOW_WRITE_PWRDELTA 9 9 EDC_THROTTLE_PATTERN_BIT_NUMS 10 13 EDC_LEVEL_SEL 14 14 EDC_ALGORITHM_MODE 15 15 EDC_AVGDIV 16 19 PSM_THROTTLE_SRC_SEL 20 22 THROTTLE_SRC0_MASK 23 23 THROTTLE_SRC1_MASK 24 24 THROTTLE_SRC2_MASK 25 25 THROTTLE_SRC3_MASK 26 26 mmGC_EDC_THRESHOLD 0 0x202c 1 0 0 EDC_THRESHOLD 0 31 mmGC_EDC_STATUS 0 0x202d 3 0 0 EDC_THROTTLE_LEVEL 0 2 GPIO_IN_0 3 3 GPIO_IN_1 4 4 mmGC_EDC_OVERFLOW 0 0x202e 2 0 0 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 mmGC_EDC_ROLLING_POWER_DELTA 0 0x202f 1 0 0 EDC_ROLLING_POWER_DELTA 0 31 mmGC_THROTTLE_CTRL 0 0x2030 19 0 0 THROTTLE_CTRL_SW_RST 0 0 GC_EDC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 PWRBRK_POLARITY_CNTL 3 3 PCC_STALL_EN 4 4 PATTERN_MODE 5 5 GC_EDC_ONLY_MODE 6 6 GC_EDC_OVERRIDE 7 7 PCC_OVERRIDE 8 8 PWRBRK_OVERRIDE 9 9 GC_EDC_PERF_COUNTER_EN 10 10 PCC_PERF_COUNTER_EN 11 11 PWRBRK_PERF_COUNTER_EN 12 12 RELEASE_STEP_INTERVAL 13 22 FIXED_PATTERN_PERF_COUNTER_EN 23 23 FIXED_PATTERN_LOG_INDEX 24 28 LUT_HW_UPDATE 29 29 THROTTLE_CTRL_CLK_EN_OVERRIDE 30 30 PCC_POLARITY_CNTL 31 31 mmGC_THROTTLE_CTRL1 0 0x2031 11 0 0 PCC_FP_PROGRAM_STEP_EN 0 0 PCC_PROGRAM_MIN_STEP 1 4 PCC_PROGRAM_MAX_STEP 5 9 PCC_PROGRAM_UPWARDS_STEP_SIZE 10 12 PWRBRK_FP_PROGRAM_STEP_EN 13 13 PWRBRK_PROGRAM_MIN_STEP 14 17 PWRBRK_PROGRAM_MAX_STEP 18 22 PWRBRK_PROGRAM_UPWARDS_STEP_SIZE 23 25 FIXED_PATTERN_SELECT 26 27 GC_EDC_STRETCH_PERF_COUNTER_EN 30 30 GC_EDC_UNSTRETCH_PERF_COUNTER_EN 31 31 mmGC_THROTTLE_STATUS 0 0x2032 2 0 0 FSM_STATE 0 3 PATTERN_INDEX 4 9 mmEDC_PERF_COUNTER 0 0x2033 1 0 0 EDC_PERF_COUNTER 0 31 mmPCC_PERF_COUNTER 0 0x2034 1 0 0 PCC_PERF_COUNTER 0 31 mmPWRBRK_PERF_COUNTER 0 0x2035 1 0 0 PWRBRK_PERF_COUNTER 0 31 mmGC_EDC_STRETCH_CTRL 0 0x2036 6 0 0 EDC_STRETCH_EN 0 0 EDC_STRETCH_DELAY 1 9 EDC_UNSTRETCH_DELAY 10 18 EDC_CLK_MONITOR_EN 19 19 EDC_CLK_MONITOR_INTERVAL 20 23 EDC_CLK_MONITOR_THRESHOLD 24 31 mmGC_EDC_STRETCH_THRESHOLD 0 0x2037 1 0 0 EDC_STRETCH_THRESHOLD 0 31 mmEDC_HYSTERESIS_CNTL 0 0x2038 1 0 0 MAX_HYSTERESIS 0 7 mmEDC_HYSTERESIS_STAT 0 0x2039 2 0 0 HYSTERESIS_CNT 0 7 EDC_STATUS 8 8 mmGC_CAC_IND_INDEX 0 0x203c 1 0 0 GC_CAC_IND_ADDR 0 31 mmGC_CAC_IND_DATA 0 0x203d 1 0 0 GC_CAC_IND_DATA 0 31 mmSE_CAC_IND_INDEX 0 0x203e 1 0 0 SE_CAC_IND_ADDR 0 31 mmSE_CAC_IND_DATA 0 0x203f 1 0 0 SE_CAC_IND_DATA 0 31 mmTCP_WATCH0_ADDR_H 0 0x2040 1 0 0 ADDR 0 15 mmTCP_WATCH0_ADDR_L 0 0x2041 1 0 0 ADDR 7 31 mmTCP_WATCH0_CNTL 0 0x2042 4 0 0 MASK 0 22 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH1_ADDR_H 0 0x2043 1 0 0 ADDR 0 15 mmTCP_WATCH1_ADDR_L 0 0x2044 1 0 0 ADDR 7 31 mmTCP_WATCH1_CNTL 0 0x2045 4 0 0 MASK 0 22 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH2_ADDR_H 0 0x2046 1 0 0 ADDR 0 15 mmTCP_WATCH2_ADDR_L 0 0x2047 1 0 0 ADDR 7 31 mmTCP_WATCH2_CNTL 0 0x2048 4 0 0 MASK 0 22 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH3_ADDR_H 0 0x2049 1 0 0 ADDR 0 15 mmTCP_WATCH3_ADDR_L 0 0x204a 1 0 0 ADDR 7 31 mmTCP_WATCH3_CNTL 0 0x204b 4 0 0 MASK 0 22 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_PERFCOUNTER_FILTER 0 0x2059 12 0 0 BUFFER 0 0 FLAT 1 1 DIM 2 4 DATA_FORMAT 5 11 NUM_FORMAT 13 16 SW_MODE 17 21 NUM_SAMPLES 22 23 OPCODE_TYPE 24 26 SLC 27 27 DLC 28 28 GLC 29 29 COMPRESSION_ENABLE 30 30 mmTCP_PERFCOUNTER_FILTER_EN 0 0x205a 13 0 0 BUFFER 0 0 FLAT 1 1 DIM 2 2 DATA_FORMAT 3 3 NUM_FORMAT 4 4 SW_MODE 5 5 NUM_SAMPLES 6 6 OPCODE_TYPE 7 7 SLC 8 8 DLC 9 9 GLC 10 10 COMPRESSION_ENABLE 11 11 REQ_MODE 12 12 mmTCP_PERFCOUNTER_FILTER2 0 0x205b 1 0 0 REQ_MODE 0 2 mmGDS_VMID0_BASE 0 0x20a0 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID0_SIZE 0 0x20a1 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID1_BASE 0 0x20a2 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID1_SIZE 0 0x20a3 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID2_BASE 0 0x20a4 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID2_SIZE 0 0x20a5 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID3_BASE 0 0x20a6 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID3_SIZE 0 0x20a7 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID4_BASE 0 0x20a8 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID4_SIZE 0 0x20a9 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID5_BASE 0 0x20aa 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID5_SIZE 0 0x20ab 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID6_BASE 0 0x20ac 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID6_SIZE 0 0x20ad 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID7_BASE 0 0x20ae 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID7_SIZE 0 0x20af 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID8_BASE 0 0x20b0 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID8_SIZE 0 0x20b1 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID9_BASE 0 0x20b2 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID9_SIZE 0 0x20b3 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID10_BASE 0 0x20b4 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID10_SIZE 0 0x20b5 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID11_BASE 0 0x20b6 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID11_SIZE 0 0x20b7 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID12_BASE 0 0x20b8 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID12_SIZE 0 0x20b9 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID13_BASE 0 0x20ba 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID13_SIZE 0 0x20bb 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID14_BASE 0 0x20bc 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID14_SIZE 0 0x20bd 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_VMID15_BASE 0 0x20be 2 0 0 BASE 0 15 UNUSED 16 31 mmGDS_VMID15_SIZE 0 0x20bf 2 0 0 SIZE 0 16 UNUSED 17 31 mmGDS_GWS_VMID0 0 0x20c0 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID1 0 0x20c1 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID2 0 0x20c2 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID3 0 0x20c3 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID4 0 0x20c4 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID5 0 0x20c5 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID6 0 0x20c6 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID7 0 0x20c7 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID8 0 0x20c8 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID9 0 0x20c9 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID10 0 0x20ca 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID11 0 0x20cb 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID12 0 0x20cc 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID13 0 0x20cd 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID14 0 0x20ce 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_GWS_VMID15 0 0x20cf 4 0 0 BASE 0 5 UNUSED1 6 15 SIZE 16 22 UNUSED2 23 31 mmGDS_OA_VMID0 0 0x20d0 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID1 0 0x20d1 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID2 0 0x20d2 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID3 0 0x20d3 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID4 0 0x20d4 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID5 0 0x20d5 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID6 0 0x20d6 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID7 0 0x20d7 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID8 0 0x20d8 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID9 0 0x20d9 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID10 0 0x20da 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID11 0 0x20db 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID12 0 0x20dc 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID13 0 0x20dd 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID14 0 0x20de 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID15 0 0x20df 2 0 0 MASK 0 15 UNUSED 16 31 mmGDS_GWS_RESET0 0 0x20e4 32 0 0 RESOURCE0_RESET 0 0 RESOURCE1_RESET 1 1 RESOURCE2_RESET 2 2 RESOURCE3_RESET 3 3 RESOURCE4_RESET 4 4 RESOURCE5_RESET 5 5 RESOURCE6_RESET 6 6 RESOURCE7_RESET 7 7 RESOURCE8_RESET 8 8 RESOURCE9_RESET 9 9 RESOURCE10_RESET 10 10 RESOURCE11_RESET 11 11 RESOURCE12_RESET 12 12 RESOURCE13_RESET 13 13 RESOURCE14_RESET 14 14 RESOURCE15_RESET 15 15 RESOURCE16_RESET 16 16 RESOURCE17_RESET 17 17 RESOURCE18_RESET 18 18 RESOURCE19_RESET 19 19 RESOURCE20_RESET 20 20 RESOURCE21_RESET 21 21 RESOURCE22_RESET 22 22 RESOURCE23_RESET 23 23 RESOURCE24_RESET 24 24 RESOURCE25_RESET 25 25 RESOURCE26_RESET 26 26 RESOURCE27_RESET 27 27 RESOURCE28_RESET 28 28 RESOURCE29_RESET 29 29 RESOURCE30_RESET 30 30 RESOURCE31_RESET 31 31 mmGDS_GWS_RESET1 0 0x20e5 32 0 0 RESOURCE32_RESET 0 0 RESOURCE33_RESET 1 1 RESOURCE34_RESET 2 2 RESOURCE35_RESET 3 3 RESOURCE36_RESET 4 4 RESOURCE37_RESET 5 5 RESOURCE38_RESET 6 6 RESOURCE39_RESET 7 7 RESOURCE40_RESET 8 8 RESOURCE41_RESET 9 9 RESOURCE42_RESET 10 10 RESOURCE43_RESET 11 11 RESOURCE44_RESET 12 12 RESOURCE45_RESET 13 13 RESOURCE46_RESET 14 14 RESOURCE47_RESET 15 15 RESOURCE48_RESET 16 16 RESOURCE49_RESET 17 17 RESOURCE50_RESET 18 18 RESOURCE51_RESET 19 19 RESOURCE52_RESET 20 20 RESOURCE53_RESET 21 21 RESOURCE54_RESET 22 22 RESOURCE55_RESET 23 23 RESOURCE56_RESET 24 24 RESOURCE57_RESET 25 25 RESOURCE58_RESET 26 26 RESOURCE59_RESET 27 27 RESOURCE60_RESET 28 28 RESOURCE61_RESET 29 29 RESOURCE62_RESET 30 30 RESOURCE63_RESET 31 31 mmGDS_GWS_RESOURCE_RESET 0 0x20e6 3 0 0 RESET 0 0 RESOURCE_ID 8 15 UNUSED 16 31 mmGDS_COMPUTE_MAX_WAVE_ID 0 0x20e8 2 0 0 MAX_WAVE_ID 0 11 UNUSED 12 31 mmGDS_OA_RESET_MASK 0 0x20e9 14 0 0 ME0_GFXHP3D_PIX_RESET 0 0 ME0_GFXHP3D_VTX_RESET 1 1 ME0_CS_RESET 2 2 ME0_GFXHP3D_GS_RESET 3 3 ME1_PIPE0_RESET 4 4 ME1_PIPE1_RESET 5 5 ME1_PIPE2_RESET 6 6 ME1_PIPE3_RESET 7 7 ME2_PIPE0_RESET 8 8 ME2_PIPE1_RESET 9 9 ME2_PIPE2_RESET 10 10 ME2_PIPE3_RESET 11 11 ME0_PIPE1_CS_RESET 12 12 UNUSED1 13 31 mmGDS_OA_RESET 0 0x20ea 3 0 0 RESET 0 0 PIPE_ID 8 15 UNUSED 16 31 mmGDS_ENHANCE2 0 0x20eb 8 0 0 MISC 0 17 RD_BUF_TAG_MISS 18 18 GDS_INTERFACES_FGCG_OVERRIDE 21 21 GDS_CLK_ENHANCE_DIS 22 22 DISABLE_LOGIC_ID_CLAMP 23 23 DISABLE_MEMORY_VIOLATION_REPORT 24 24 GDS_CLK_ENHANCE_DIS_MGCG_DSO 25 28 GDS_CLK_ENHANCE_DIS_MGCG_DSA 29 31 mmGDS_OA_CGPG_RESTORE 0 0x20ec 5 0 0 VMID 0 7 MEID 8 11 PIPEID 12 15 QUEUEID 16 19 UNUSED 20 31 mmGDS_CS_CTXSW_STATUS 0 0x20ed 3 0 0 R 0 0 W 1 1 UNUSED 2 31 mmGDS_CS_CTXSW_CNT0 0 0x20ee 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_CS_CTXSW_CNT1 0 0x20ef 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_CS_CTXSW_CNT2 0 0x20f0 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_CS_CTXSW_CNT3 0 0x20f1 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_GFX_CTXSW_STATUS 0 0x20f2 3 0 0 R 0 0 W 1 1 UNUSED 2 31 mmGDS_VS_CTXSW_CNT0 0 0x20f3 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_VS_CTXSW_CNT1 0 0x20f4 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_VS_CTXSW_CNT2 0 0x20f5 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_VS_CTXSW_CNT3 0 0x20f6 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_PS_CTXSW_CNT0 0 0x20f7 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_PS_CTXSW_CNT1 0 0x20f8 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_PS_CTXSW_CNT2 0 0x20f9 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_PS_CTXSW_CNT3 0 0x20fa 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_PS_CTXSW_IDX 0 0x20fb 2 0 0 PACKER_ID 0 3 UNUSED 4 31 mmGDS_GS_CTXSW_CNT0 0 0x2117 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_GS_CTXSW_CNT1 0 0x2118 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_GS_CTXSW_CNT2 0 0x2119 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_GS_CTXSW_CNT3 0 0x211a 2 0 0 UPDN 0 15 PTR 16 31 mmGDS_MEMORY_CLEAN 0 0x211f 3 0 0 START 0 0 FINISH 1 1 UNUSED 2 31 mmDB_RENDER_CONTROL 0 0x0 11 0 1 DEPTH_CLEAR_ENABLE 0 0 STENCIL_CLEAR_ENABLE 1 1 DEPTH_COPY 2 2 STENCIL_COPY 3 3 RESUMMARIZE_ENABLE 4 4 STENCIL_COMPRESS_DISABLE 5 5 DEPTH_COMPRESS_DISABLE 6 6 COPY_CENTROID 7 7 COPY_SAMPLE 8 11 DECOMPRESS_ENABLE 12 12 PS_INVOKE_DISABLE 13 13 mmDB_COUNT_CONTROL 0 0x1 11 0 1 ZPASS_INCREMENT_DISABLE 0 0 PERFECT_ZPASS_COUNTS 1 1 DISABLE_CONSERVATIVE_ZPASS_COUNTS 2 2 ENHANCED_CONSERVATIVE_ZPASS_COUNTS 3 3 SAMPLE_RATE 4 6 ZPASS_ENABLE 8 11 ZFAIL_ENABLE 12 15 SFAIL_ENABLE 16 19 DBFAIL_ENABLE 20 23 SLICE_EVEN_ENABLE 24 27 SLICE_ODD_ENABLE 28 31 mmDB_DEPTH_VIEW 0 0x2 7 0 1 SLICE_START 0 10 SLICE_START_HI 11 12 SLICE_MAX 13 23 Z_READ_ONLY 24 24 STENCIL_READ_ONLY 25 25 MIPID 26 29 SLICE_MAX_HI 30 31 mmDB_RENDER_OVERRIDE 0 0x3 23 0 1 FORCE_HIZ_ENABLE 0 1 FORCE_HIS_ENABLE0 2 3 FORCE_HIS_ENABLE1 4 5 FORCE_SHADER_Z_ORDER 6 6 FAST_Z_DISABLE 7 7 FAST_STENCIL_DISABLE 8 8 NOOP_CULL_DISABLE 9 9 FORCE_COLOR_KILL 10 10 FORCE_Z_READ 11 11 FORCE_STENCIL_READ 12 12 FORCE_FULL_Z_RANGE 13 14 FORCE_QC_SMASK_CONFLICT 15 15 DISABLE_VIEWPORT_CLAMP 16 16 IGNORE_SC_ZRANGE 17 17 DISABLE_FULLY_COVERED 18 18 FORCE_Z_LIMIT_SUMM 19 20 MAX_TILES_IN_DTT 21 25 DISABLE_TILE_RATE_TILES 26 26 FORCE_Z_DIRTY 27 27 FORCE_STENCIL_DIRTY 28 28 FORCE_Z_VALID 29 29 FORCE_STENCIL_VALID 30 30 PRESERVE_COMPRESSION 31 31 mmDB_RENDER_OVERRIDE2 0 0x4 18 0 1 PARTIAL_SQUAD_LAUNCH_CONTROL 0 1 PARTIAL_SQUAD_LAUNCH_COUNTDOWN 2 4 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 5 5 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 6 6 DISABLE_COLOR_ON_VALIDATION 7 7 DECOMPRESS_Z_ON_FLUSH 8 8 DISABLE_REG_SNOOP 9 9 DEPTH_BOUNDS_HIER_DEPTH_DISABLE 10 10 SEPARATE_HIZS_FUNC_ENABLE 11 11 HIZ_ZFUNC 12 14 HIS_SFUNC_FF 15 17 HIS_SFUNC_BF 18 20 PRESERVE_ZRANGE 21 21 PRESERVE_SRESULTS 22 22 DISABLE_FAST_PASS 23 23 ALLOW_PARTIAL_RES_HIER_KILL 25 25 FORCE_VRS_RATE_FINE 26 26 CENTROID_COMPUTATION_MODE 27 28 mmDB_HTILE_DATA_BASE 0 0x5 1 0 1 BASE_256B 0 31 mmDB_DEPTH_SIZE_XY 0 0x7 2 0 1 X_MAX 0 13 Y_MAX 16 29 mmDB_DEPTH_BOUNDS_MIN 0 0x8 1 0 1 MIN 0 31 mmDB_DEPTH_BOUNDS_MAX 0 0x9 1 0 1 MAX 0 31 mmDB_STENCIL_CLEAR 0 0xa 1 0 1 CLEAR 0 7 mmDB_DEPTH_CLEAR 0 0xb 1 0 1 DEPTH_CLEAR 0 31 mmPA_SC_SCREEN_SCISSOR_TL 0 0xc 2 0 1 TL_X 0 15 TL_Y 16 31 mmPA_SC_SCREEN_SCISSOR_BR 0 0xd 2 0 1 BR_X 0 15 BR_Y 16 31 mmDB_DFSM_CONTROL 0 0xe 3 0 1 PUNCHOUT_MODE 0 1 POPS_DRAIN_PS_ON_OVERLAP 2 2 DISALLOW_OVERFLOW 3 3 mmDB_RESERVED_REG_2 0 0xf 8 0 1 FIELD_1 0 3 FIELD_2 4 7 FIELD_3 8 12 FIELD_4 13 14 FIELD_5 15 16 FIELD_6 17 18 FIELD_7 19 20 FIELD_8 28 31 mmDB_Z_INFO 0 0x10 14 0 1 FORMAT 0 1 NUM_SAMPLES 2 3 SW_MODE 4 8 FAULT_BEHAVIOR 9 10 ITERATE_FLUSH 11 11 PARTIALLY_RESIDENT 12 12 RESERVED_FIELD_1 13 15 MAXMIP 16 19 ITERATE_256 20 20 DECOMPRESS_ON_N_ZPLANES 23 26 ALLOW_EXPCLEAR 27 27 READ_SIZE 28 28 TILE_SURFACE_ENABLE 29 29 ZRANGE_PRECISION 31 31 mmDB_STENCIL_INFO 0 0x11 9 0 1 FORMAT 0 0 SW_MODE 4 8 FAULT_BEHAVIOR 9 10 ITERATE_FLUSH 11 11 PARTIALLY_RESIDENT 12 12 RESERVED_FIELD_1 13 15 ITERATE_256 20 20 ALLOW_EXPCLEAR 27 27 TILE_STENCIL_DISABLE 29 29 mmDB_Z_READ_BASE 0 0x12 1 0 1 BASE_256B 0 31 mmDB_STENCIL_READ_BASE 0 0x13 1 0 1 BASE_256B 0 31 mmDB_Z_WRITE_BASE 0 0x14 1 0 1 BASE_256B 0 31 mmDB_STENCIL_WRITE_BASE 0 0x15 1 0 1 BASE_256B 0 31 mmDB_RESERVED_REG_1 0 0x16 2 0 1 FIELD_1 0 10 FIELD_2 11 21 mmDB_RESERVED_REG_3 0 0x17 1 0 1 FIELD_1 0 21 mmDB_VRS_OVERRIDE_CNTL 0 0x19 3 0 1 VRS_OVERRIDE_RATE_COMBINER_MODE 0 2 VRS_OVERRIDE_RATE_X 4 5 VRS_OVERRIDE_RATE_Y 6 7 mmDB_Z_READ_BASE_HI 0 0x1a 1 0 1 BASE_HI 0 7 mmDB_STENCIL_READ_BASE_HI 0 0x1b 1 0 1 BASE_HI 0 7 mmDB_Z_WRITE_BASE_HI 0 0x1c 1 0 1 BASE_HI 0 7 mmDB_STENCIL_WRITE_BASE_HI 0 0x1d 1 0 1 BASE_HI 0 7 mmDB_HTILE_DATA_BASE_HI 0 0x1e 1 0 1 BASE_HI 0 7 mmDB_RMI_L2_CACHE_CONTROL 0 0x1f 13 0 1 Z_WR_POLICY 0 1 S_WR_POLICY 2 3 HTILE_WR_POLICY 4 5 ZPCPSD_WR_POLICY 6 7 Z_RD_POLICY 16 17 S_RD_POLICY 18 19 HTILE_RD_POLICY 20 21 Z_BIG_PAGE 24 24 S_BIG_PAGE 25 25 Z_NOALLOC 26 26 S_NOALLOC 27 27 HTILE_NOALLOC 28 28 ZPCPSD_NOALLOC 29 29 mmTA_BC_BASE_ADDR 0 0x20 1 0 1 ADDRESS 0 31 mmTA_BC_BASE_ADDR_HI 0 0x21 1 0 1 ADDRESS 0 7 mmCOHER_DEST_BASE_HI_0 0 0x7a 1 0 1 DEST_BASE_HI_256B 0 7 mmCOHER_DEST_BASE_HI_1 0 0x7b 1 0 1 DEST_BASE_HI_256B 0 7 mmCOHER_DEST_BASE_HI_2 0 0x7c 1 0 1 DEST_BASE_HI_256B 0 7 mmCOHER_DEST_BASE_HI_3 0 0x7d 1 0 1 DEST_BASE_HI_256B 0 7 mmCOHER_DEST_BASE_2 0 0x7e 1 0 1 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_3 0 0x7f 1 0 1 DEST_BASE_256B 0 31 mmPA_SC_WINDOW_OFFSET 0 0x80 2 0 1 WINDOW_X_OFFSET 0 15 WINDOW_Y_OFFSET 16 31 mmPA_SC_WINDOW_SCISSOR_TL 0 0x81 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_WINDOW_SCISSOR_BR 0 0x82 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_RULE 0 0x83 1 0 1 CLIP_RULE 0 15 mmPA_SC_CLIPRECT_0_TL 0 0x84 2 0 1 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_0_BR 0 0x85 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_1_TL 0 0x86 2 0 1 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_1_BR 0 0x87 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_2_TL 0 0x88 2 0 1 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_2_BR 0 0x89 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_3_TL 0 0x8a 2 0 1 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_3_BR 0 0x8b 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_EDGERULE 0 0x8c 7 0 1 ER_TRI 0 3 ER_POINT 4 7 ER_RECT 8 11 ER_LINE_LR 12 17 ER_LINE_RL 18 23 ER_LINE_TB 24 27 ER_LINE_BT 28 31 mmPA_SU_HARDWARE_SCREEN_OFFSET 0 0x8d 2 0 1 HW_SCREEN_OFFSET_X 0 8 HW_SCREEN_OFFSET_Y 16 24 mmCB_TARGET_MASK 0 0x8e 8 0 1 TARGET0_ENABLE 0 3 TARGET1_ENABLE 4 7 TARGET2_ENABLE 8 11 TARGET3_ENABLE 12 15 TARGET4_ENABLE 16 19 TARGET5_ENABLE 20 23 TARGET6_ENABLE 24 27 TARGET7_ENABLE 28 31 mmCB_SHADER_MASK 0 0x8f 8 0 1 OUTPUT0_ENABLE 0 3 OUTPUT1_ENABLE 4 7 OUTPUT2_ENABLE 8 11 OUTPUT3_ENABLE 12 15 OUTPUT4_ENABLE 16 19 OUTPUT5_ENABLE 20 23 OUTPUT6_ENABLE 24 27 OUTPUT7_ENABLE 28 31 mmPA_SC_GENERIC_SCISSOR_TL 0 0x90 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_GENERIC_SCISSOR_BR 0 0x91 2 0 1 BR_X 0 14 BR_Y 16 30 mmCOHER_DEST_BASE_0 0 0x92 1 0 1 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_1 0 0x93 1 0 1 DEST_BASE_256B 0 31 mmPA_SC_VPORT_SCISSOR_0_TL 0 0x94 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_0_BR 0 0x95 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_1_TL 0 0x96 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_1_BR 0 0x97 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_2_TL 0 0x98 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_2_BR 0 0x99 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_3_TL 0 0x9a 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_3_BR 0 0x9b 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_4_TL 0 0x9c 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_4_BR 0 0x9d 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_5_TL 0 0x9e 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_5_BR 0 0x9f 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_6_TL 0 0xa0 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_6_BR 0 0xa1 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_7_TL 0 0xa2 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_7_BR 0 0xa3 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_8_TL 0 0xa4 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_8_BR 0 0xa5 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_9_TL 0 0xa6 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_9_BR 0 0xa7 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_10_TL 0 0xa8 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_10_BR 0 0xa9 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_11_TL 0 0xaa 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_11_BR 0 0xab 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_12_TL 0 0xac 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_12_BR 0 0xad 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_13_TL 0 0xae 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_13_BR 0 0xaf 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_14_TL 0 0xb0 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_14_BR 0 0xb1 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_15_TL 0 0xb2 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_15_BR 0 0xb3 2 0 1 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_ZMIN_0 0 0xb4 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_0 0 0xb5 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_1 0 0xb6 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_1 0 0xb7 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_2 0 0xb8 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_2 0 0xb9 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_3 0 0xba 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_3 0 0xbb 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_4 0 0xbc 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_4 0 0xbd 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_5 0 0xbe 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_5 0 0xbf 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_6 0 0xc0 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_6 0 0xc1 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_7 0 0xc2 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_7 0 0xc3 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_8 0 0xc4 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_8 0 0xc5 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_9 0 0xc6 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_9 0 0xc7 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_10 0 0xc8 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_10 0 0xc9 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_11 0 0xca 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_11 0 0xcb 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_12 0 0xcc 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_12 0 0xcd 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_13 0 0xce 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_13 0 0xcf 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_14 0 0xd0 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_14 0 0xd1 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMIN_15 0 0xd2 1 0 1 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_15 0 0xd3 1 0 1 VPORT_ZMAX 0 31 mmPA_SC_RASTER_CONFIG 0 0xd4 15 0 1 RB_MAP_PKR0 0 1 RB_MAP_PKR1 2 3 RB_XSEL2 4 5 RB_XSEL 6 6 RB_YSEL 7 7 PKR_MAP 8 9 PKR_XSEL 10 11 PKR_YSEL 12 13 PKR_XSEL2 14 15 SC_MAP 16 17 SC_XSEL 18 19 SC_YSEL 20 21 SE_MAP 24 25 SE_XSEL 26 27 SE_YSEL 28 29 mmPA_SC_RASTER_CONFIG_1 0 0xd5 3 0 1 SE_PAIR_MAP 0 1 SE_PAIR_XSEL 2 3 SE_PAIR_YSEL 4 5 mmPA_SC_SCREEN_EXTENT_CONTROL 0 0xd6 2 0 1 SLICE_EVEN_ENABLE 0 1 SLICE_ODD_ENABLE 2 3 mmPA_SC_TILE_STEERING_OVERRIDE 0 0xd7 6 0 1 ENABLE 0 0 NUM_SE 1 2 NUM_RB_PER_SE 5 6 NUM_SC 12 13 NUM_RB_PER_SC 16 17 NUM_PACKER_PER_SC 20 21 mmCP_PERFMON_CNTX_CNTL 0 0xd8 1 0 1 PERFMON_ENABLE 31 31 mmCP_PIPEID 0 0xd9 1 0 1 PIPE_ID 0 1 mmCP_RINGID 0 0xd9 1 0 1 RINGID 0 1 mmCP_VMID 0 0xda 1 0 1 VMID 0 3 mmCONTEXT_RESERVED_REG0 0 0xdb 1 0 1 DATA 0 31 mmCONTEXT_RESERVED_REG1 0 0xdc 1 0 1 DATA 0 31 mmVGT_MAX_VTX_INDX 0 0x100 1 0 1 MAX_INDX 0 31 mmVGT_MIN_VTX_INDX 0 0x101 1 0 1 MIN_INDX 0 31 mmVGT_INDX_OFFSET 0 0x102 1 0 1 INDX_OFFSET 0 31 mmVGT_MULTI_PRIM_IB_RESET_INDX 0 0x103 1 0 1 RESET_INDX 0 31 mmCB_RMI_GL2_CACHE_CONTROL 0 0x104 14 0 1 CMASK_WR_POLICY 0 1 FMASK_WR_POLICY 2 3 DCC_WR_POLICY 4 5 COLOR_WR_POLICY 6 7 CMASK_RD_POLICY 16 17 FMASK_RD_POLICY 18 19 DCC_RD_POLICY 20 21 COLOR_RD_POLICY 22 23 CMASK_L3_BYPASS 24 24 FMASK_L3_BYPASS 25 25 DCC_L3_BYPASS 26 26 COLOR_L3_BYPASS 27 27 FMASK_BIG_PAGE 30 30 COLOR_BIG_PAGE 31 31 mmCB_BLEND_RED 0 0x105 1 0 1 BLEND_RED 0 31 mmCB_BLEND_GREEN 0 0x106 1 0 1 BLEND_GREEN 0 31 mmCB_BLEND_BLUE 0 0x107 1 0 1 BLEND_BLUE 0 31 mmCB_BLEND_ALPHA 0 0x108 1 0 1 BLEND_ALPHA 0 31 mmCB_DCC_CONTROL 0 0x109 8 0 1 OVERWRITE_COMBINER_DISABLE 0 0 OVERWRITE_COMBINER_WATERMARK 2 6 DISABLE_CONSTANT_ENCODE_AC01 8 8 DISABLE_CONSTANT_ENCODE_SINGLE 9 9 DISABLE_CONSTANT_ENCODE_REG 10 10 DISABLE_ELIMFC_SKIP_OF_AC01 12 12 DISABLE_ELIMFC_SKIP_OF_SINGLE 13 13 ENABLE_ELIMFC_SKIP_OF_REG 14 14 mmCB_COVERAGE_OUT_CONTROL 0 0x10a 4 0 1 COVERAGE_OUT_ENABLE 0 0 COVERAGE_OUT_MRT 1 3 COVERAGE_OUT_CHANNEL 4 5 COVERAGE_OUT_SAMPLES 8 11 mmDB_STENCIL_CONTROL 0 0x10b 6 0 1 STENCILFAIL 0 3 STENCILZPASS 4 7 STENCILZFAIL 8 11 STENCILFAIL_BF 12 15 STENCILZPASS_BF 16 19 STENCILZFAIL_BF 20 23 mmDB_STENCILREFMASK 0 0x10c 4 0 1 STENCILTESTVAL 0 7 STENCILMASK 8 15 STENCILWRITEMASK 16 23 STENCILOPVAL 24 31 mmDB_STENCILREFMASK_BF 0 0x10d 4 0 1 STENCILTESTVAL_BF 0 7 STENCILMASK_BF 8 15 STENCILWRITEMASK_BF 16 23 STENCILOPVAL_BF 24 31 mmPA_CL_VPORT_XSCALE 0 0x10f 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET 0 0x110 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE 0 0x111 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET 0 0x112 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE 0 0x113 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET 0 0x114 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_1 0 0x115 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_1 0 0x116 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_1 0 0x117 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_1 0 0x118 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_1 0 0x119 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_1 0 0x11a 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_2 0 0x11b 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_2 0 0x11c 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_2 0 0x11d 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_2 0 0x11e 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_2 0 0x11f 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_2 0 0x120 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_3 0 0x121 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_3 0 0x122 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_3 0 0x123 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_3 0 0x124 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_3 0 0x125 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_3 0 0x126 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_4 0 0x127 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_4 0 0x128 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_4 0 0x129 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_4 0 0x12a 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_4 0 0x12b 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_4 0 0x12c 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_5 0 0x12d 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_5 0 0x12e 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_5 0 0x12f 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_5 0 0x130 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_5 0 0x131 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_5 0 0x132 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_6 0 0x133 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_6 0 0x134 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_6 0 0x135 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_6 0 0x136 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_6 0 0x137 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_6 0 0x138 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_7 0 0x139 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_7 0 0x13a 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_7 0 0x13b 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_7 0 0x13c 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_7 0 0x13d 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_7 0 0x13e 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_8 0 0x13f 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_8 0 0x140 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_8 0 0x141 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_8 0 0x142 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_8 0 0x143 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_8 0 0x144 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_9 0 0x145 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_9 0 0x146 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_9 0 0x147 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_9 0 0x148 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_9 0 0x149 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_9 0 0x14a 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_10 0 0x14b 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_10 0 0x14c 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_10 0 0x14d 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_10 0 0x14e 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_10 0 0x14f 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_10 0 0x150 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_11 0 0x151 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_11 0 0x152 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_11 0 0x153 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_11 0 0x154 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_11 0 0x155 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_11 0 0x156 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_12 0 0x157 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_12 0 0x158 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_12 0 0x159 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_12 0 0x15a 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_12 0 0x15b 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_12 0 0x15c 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_13 0 0x15d 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_13 0 0x15e 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_13 0 0x15f 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_13 0 0x160 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_13 0 0x161 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_13 0 0x162 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_14 0 0x163 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_14 0 0x164 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_14 0 0x165 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_14 0 0x166 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_14 0 0x167 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_14 0 0x168 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_15 0 0x169 1 0 1 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_15 0 0x16a 1 0 1 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_15 0 0x16b 1 0 1 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_15 0 0x16c 1 0 1 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_15 0 0x16d 1 0 1 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_15 0 0x16e 1 0 1 VPORT_ZOFFSET 0 31 mmPA_CL_UCP_0_X 0 0x16f 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_0_Y 0 0x170 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_0_Z 0 0x171 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_0_W 0 0x172 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_1_X 0 0x173 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_1_Y 0 0x174 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_1_Z 0 0x175 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_1_W 0 0x176 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_2_X 0 0x177 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_2_Y 0 0x178 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_2_Z 0 0x179 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_2_W 0 0x17a 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_3_X 0 0x17b 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_3_Y 0 0x17c 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_3_Z 0 0x17d 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_3_W 0 0x17e 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_4_X 0 0x17f 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_4_Y 0 0x180 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_4_Z 0 0x181 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_4_W 0 0x182 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_5_X 0 0x183 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_5_Y 0 0x184 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_5_Z 0 0x185 1 0 1 DATA_REGISTER 0 31 mmPA_CL_UCP_5_W 0 0x186 1 0 1 DATA_REGISTER 0 31 mmPA_CL_PROG_NEAR_CLIP_Z 0 0x187 1 0 1 DATA_REGISTER 0 31 mmSPI_PS_INPUT_CNTL_0 0 0x191 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_1 0 0x192 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_2 0 0x193 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_3 0 0x194 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_4 0 0x195 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_5 0 0x196 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_6 0 0x197 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_7 0 0x198 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_8 0 0x199 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_9 0 0x19a 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_10 0 0x19b 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_11 0 0x19c 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_12 0 0x19d 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_13 0 0x19e 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_14 0 0x19f 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_15 0 0x1a0 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_16 0 0x1a1 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_17 0 0x1a2 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_18 0 0x1a3 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_19 0 0x1a4 13 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_20 0 0x1a5 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_21 0 0x1a6 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_22 0 0x1a7 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_23 0 0x1a8 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_24 0 0x1a9 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_25 0 0x1aa 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_26 0 0x1ab 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_27 0 0x1ac 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_28 0 0x1ad 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_29 0 0x1ae 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_30 0 0x1af 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_PS_INPUT_CNTL_31 0 0x1b0 10 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 ROTATE_PC_PTR 11 11 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 mmSPI_VS_OUT_CONFIG 0 0x1b1 4 0 1 VS_EXPORT_COUNT 1 5 VS_HALF_PACK 6 6 NO_PC_EXPORT 7 7 PRIM_EXPORT_COUNT 8 12 mmSPI_PS_INPUT_ENA 0 0x1b3 16 0 1 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 mmSPI_PS_INPUT_ADDR 0 0x1b4 16 0 1 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 mmSPI_INTERP_CONTROL_0 0 0x1b5 7 0 1 FLAT_SHADE_ENA 0 0 PNT_SPRITE_ENA 1 1 PNT_SPRITE_OVRD_X 2 4 PNT_SPRITE_OVRD_Y 5 7 PNT_SPRITE_OVRD_Z 8 10 PNT_SPRITE_OVRD_W 11 13 PNT_SPRITE_TOP_1 14 14 mmSPI_PS_IN_CONTROL 0 0x1b6 6 0 1 NUM_INTERP 0 5 OFFCHIP_PARAM_EN 7 7 LATE_PC_DEALLOC 8 8 NUM_PRIM_INTERP 9 13 BC_OPTIMIZE_DISABLE 14 14 PS_W32_EN 15 15 mmSPI_BARYC_CNTL 0 0x1b8 7 0 1 PERSP_CENTER_CNTL 0 0 PERSP_CENTROID_CNTL 4 4 LINEAR_CENTER_CNTL 8 8 LINEAR_CENTROID_CNTL 12 12 POS_FLOAT_LOCATION 16 17 POS_FLOAT_ULC 20 20 FRONT_FACE_ALL_BITS 24 24 mmSPI_TMPRING_SIZE 0 0x1ba 2 0 1 WAVES 0 11 WAVESIZE 12 24 mmSPI_SHADER_IDX_FORMAT 0 0x1c2 1 0 1 IDX0_EXPORT_FORMAT 0 3 mmSPI_SHADER_POS_FORMAT 0 0x1c3 5 0 1 POS0_EXPORT_FORMAT 0 3 POS1_EXPORT_FORMAT 4 7 POS2_EXPORT_FORMAT 8 11 POS3_EXPORT_FORMAT 12 15 POS4_EXPORT_FORMAT 16 19 mmSPI_SHADER_Z_FORMAT 0 0x1c4 1 0 1 Z_EXPORT_FORMAT 0 3 mmSPI_SHADER_COL_FORMAT 0 0x1c5 8 0 1 COL0_EXPORT_FORMAT 0 3 COL1_EXPORT_FORMAT 4 7 COL2_EXPORT_FORMAT 8 11 COL3_EXPORT_FORMAT 12 15 COL4_EXPORT_FORMAT 16 19 COL5_EXPORT_FORMAT 20 23 COL6_EXPORT_FORMAT 24 27 COL7_EXPORT_FORMAT 28 31 mmSX_PS_DOWNCONVERT_CONTROL 0 0x1d4 8 0 1 MRT0_FMT_MAPPING_DISABLE 0 0 MRT1_FMT_MAPPING_DISABLE 1 1 MRT2_FMT_MAPPING_DISABLE 2 2 MRT3_FMT_MAPPING_DISABLE 3 3 MRT4_FMT_MAPPING_DISABLE 4 4 MRT5_FMT_MAPPING_DISABLE 5 5 MRT6_FMT_MAPPING_DISABLE 6 6 MRT7_FMT_MAPPING_DISABLE 7 7 mmSX_PS_DOWNCONVERT 0 0x1d5 8 0 1 MRT0 0 3 MRT1 4 7 MRT2 8 11 MRT3 12 15 MRT4 16 19 MRT5 20 23 MRT6 24 27 MRT7 28 31 mmSX_BLEND_OPT_EPSILON 0 0x1d6 8 0 1 MRT0_EPSILON 0 3 MRT1_EPSILON 4 7 MRT2_EPSILON 8 11 MRT3_EPSILON 12 15 MRT4_EPSILON 16 19 MRT5_EPSILON 20 23 MRT6_EPSILON 24 27 MRT7_EPSILON 28 31 mmSX_BLEND_OPT_CONTROL 0 0x1d7 17 0 1 MRT0_COLOR_OPT_DISABLE 0 0 MRT0_ALPHA_OPT_DISABLE 1 1 MRT1_COLOR_OPT_DISABLE 4 4 MRT1_ALPHA_OPT_DISABLE 5 5 MRT2_COLOR_OPT_DISABLE 8 8 MRT2_ALPHA_OPT_DISABLE 9 9 MRT3_COLOR_OPT_DISABLE 12 12 MRT3_ALPHA_OPT_DISABLE 13 13 MRT4_COLOR_OPT_DISABLE 16 16 MRT4_ALPHA_OPT_DISABLE 17 17 MRT5_COLOR_OPT_DISABLE 20 20 MRT5_ALPHA_OPT_DISABLE 21 21 MRT6_COLOR_OPT_DISABLE 24 24 MRT6_ALPHA_OPT_DISABLE 25 25 MRT7_COLOR_OPT_DISABLE 28 28 MRT7_ALPHA_OPT_DISABLE 29 29 PIXEN_ZERO_OPT_DISABLE 31 31 mmSX_MRT0_BLEND_OPT 0 0x1d8 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT1_BLEND_OPT 0 0x1d9 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT2_BLEND_OPT 0 0x1da 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT3_BLEND_OPT 0 0x1db 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT4_BLEND_OPT 0 0x1dc 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT5_BLEND_OPT 0 0x1dd 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT6_BLEND_OPT 0 0x1de 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmSX_MRT7_BLEND_OPT 0 0x1df 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 mmCB_BLEND0_CONTROL 0 0x1e0 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND1_CONTROL 0 0x1e1 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND2_CONTROL 0 0x1e2 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND3_CONTROL 0 0x1e3 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND4_CONTROL 0 0x1e4 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND5_CONTROL 0 0x1e5 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND6_CONTROL 0 0x1e6 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND7_CONTROL 0 0x1e7 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCS_COPY_STATE 0 0x1f3 1 0 1 SRC_STATE_ID 0 2 mmGFX_COPY_STATE 0 0x1f4 1 0 1 SRC_STATE_ID 0 2 mmPA_CL_POINT_X_RAD 0 0x1f5 1 0 1 DATA_REGISTER 0 31 mmPA_CL_POINT_Y_RAD 0 0x1f6 1 0 1 DATA_REGISTER 0 31 mmPA_CL_POINT_SIZE 0 0x1f7 1 0 1 DATA_REGISTER 0 31 mmPA_CL_POINT_CULL_RAD 0 0x1f8 1 0 1 DATA_REGISTER 0 31 mmVGT_DMA_BASE_HI 0 0x1f9 1 0 1 BASE_ADDR 0 15 mmVGT_DMA_BASE 0 0x1fa 1 0 1 BASE_ADDR 0 31 mmVGT_DRAW_INITIATOR 0 0x1fc 6 0 1 SOURCE_SELECT 0 1 MAJOR_MODE 2 3 SPRITE_EN_R6XX 4 4 NOT_EOP 5 5 USE_OPAQUE 6 6 REG_RT_INDEX 29 31 mmVGT_IMMED_DATA 0 0x1fd 1 0 1 DATA 0 31 mmVGT_EVENT_ADDRESS_REG 0 0x1fe 1 0 1 ADDRESS_LOW 0 27 mmGE_MAX_OUTPUT_PER_SUBGROUP 0 0x1ff 1 0 1 MAX_VERTS_PER_SUBGROUP 0 9 mmDB_DEPTH_CONTROL 0 0x200 10 0 1 STENCIL_ENABLE 0 0 Z_ENABLE 1 1 Z_WRITE_ENABLE 2 2 DEPTH_BOUNDS_ENABLE 3 3 ZFUNC 4 6 BACKFACE_ENABLE 7 7 STENCILFUNC 8 10 STENCILFUNC_BF 20 22 ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 30 30 DISABLE_COLOR_WRITES_ON_DEPTH_PASS 31 31 mmDB_EQAA 0 0x201 12 0 1 MAX_ANCHOR_SAMPLES 0 2 PS_ITER_SAMPLES 4 6 MASK_EXPORT_NUM_SAMPLES 8 10 ALPHA_TO_MASK_NUM_SAMPLES 12 14 HIGH_QUALITY_INTERSECTIONS 16 16 INCOHERENT_EQAA_READS 17 17 INTERPOLATE_COMP_Z 18 18 INTERPOLATE_SRC_Z 19 19 STATIC_ANCHOR_ASSOCIATIONS 20 20 ALPHA_TO_MASK_EQAA_DISABLE 21 21 OVERRASTERIZATION_AMOUNT 24 26 ENABLE_POSTZ_OVERRASTERIZATION 27 27 mmCB_COLOR_CONTROL 0 0x202 5 0 1 DISABLE_DUAL_QUAD 0 0 ENABLE_1FRAG_PS_INVOKE 1 1 DEGAMMA_ENABLE 3 3 MODE 4 6 ROP3 16 23 mmDB_SHADER_CONTROL 0 0x203 17 0 1 Z_EXPORT_ENABLE 0 0 STENCIL_TEST_VAL_EXPORT_ENABLE 1 1 STENCIL_OP_VAL_EXPORT_ENABLE 2 2 Z_ORDER 4 5 KILL_ENABLE 6 6 COVERAGE_TO_MASK_ENABLE 7 7 MASK_EXPORT_ENABLE 8 8 EXEC_ON_HIER_FAIL 9 9 EXEC_ON_NOOP 10 10 ALPHA_TO_MASK_DISABLE 11 11 DEPTH_BEFORE_SHADER 12 12 CONSERVATIVE_Z_EXPORT 13 14 DUAL_QUAD_DISABLE 15 15 PRIMITIVE_ORDERED_PIXEL_SHADER 16 16 EXEC_IF_OVERLAPPED 17 17 POPS_OVERLAP_NUM_SAMPLES 20 22 PRE_SHADER_DEPTH_COVERAGE_ENABLE 23 23 mmPA_CL_CLIP_CNTL 0 0x204 20 0 1 UCP_ENA_0 0 0 UCP_ENA_1 1 1 UCP_ENA_2 2 2 UCP_ENA_3 3 3 UCP_ENA_4 4 4 UCP_ENA_5 5 5 PS_UCP_Y_SCALE_NEG 13 13 PS_UCP_MODE 14 15 CLIP_DISABLE 16 16 UCP_CULL_ONLY_ENA 17 17 BOUNDARY_EDGE_FLAG_ENA 18 18 DX_CLIP_SPACE_DEF 19 19 DIS_CLIP_ERR_DETECT 20 20 VTX_KILL_OR 21 21 DX_RASTERIZATION_KILL 22 22 DX_LINEAR_ATTR_CLIP_ENA 24 24 VTE_VPORT_PROVOKE_DISABLE 25 25 ZCLIP_NEAR_DISABLE 26 26 ZCLIP_FAR_DISABLE 27 27 ZCLIP_PROG_NEAR_ENA 28 28 mmPA_SU_SC_MODE_CNTL 0 0x205 16 0 1 CULL_FRONT 0 0 CULL_BACK 1 1 FACE 2 2 POLY_MODE 3 4 POLYMODE_FRONT_PTYPE 5 7 POLYMODE_BACK_PTYPE 8 10 POLY_OFFSET_FRONT_ENABLE 11 11 POLY_OFFSET_BACK_ENABLE 12 12 POLY_OFFSET_PARA_ENABLE 13 13 VTX_WINDOW_OFFSET_ENABLE 16 16 PROVOKING_VTX_LAST 19 19 PERSP_CORR_DIS 20 20 MULTI_PRIM_IB_ENA 21 21 RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF 22 22 NEW_QUAD_DECOMPOSITION 23 23 KEEP_TOGETHER_ENABLE 24 24 mmPA_CL_VTE_CNTL 0 0x206 10 0 1 VPORT_X_SCALE_ENA 0 0 VPORT_X_OFFSET_ENA 1 1 VPORT_Y_SCALE_ENA 2 2 VPORT_Y_OFFSET_ENA 3 3 VPORT_Z_SCALE_ENA 4 4 VPORT_Z_OFFSET_ENA 5 5 VTX_XY_FMT 8 8 VTX_Z_FMT 9 9 VTX_W0_FMT 10 10 PERFCOUNTER_REF 11 11 mmPA_CL_VS_OUT_CNTL 0 0x207 30 0 1 CLIP_DIST_ENA_0 0 0 CLIP_DIST_ENA_1 1 1 CLIP_DIST_ENA_2 2 2 CLIP_DIST_ENA_3 3 3 CLIP_DIST_ENA_4 4 4 CLIP_DIST_ENA_5 5 5 CLIP_DIST_ENA_6 6 6 CLIP_DIST_ENA_7 7 7 CULL_DIST_ENA_0 8 8 CULL_DIST_ENA_1 9 9 CULL_DIST_ENA_2 10 10 CULL_DIST_ENA_3 11 11 CULL_DIST_ENA_4 12 12 CULL_DIST_ENA_5 13 13 CULL_DIST_ENA_6 14 14 CULL_DIST_ENA_7 15 15 USE_VTX_POINT_SIZE 16 16 USE_VTX_EDGE_FLAG 17 17 USE_VTX_RENDER_TARGET_INDX 18 18 USE_VTX_VIEWPORT_INDX 19 19 USE_VTX_KILL_FLAG 20 20 VS_OUT_MISC_VEC_ENA 21 21 VS_OUT_CCDIST0_VEC_ENA 22 22 VS_OUT_CCDIST1_VEC_ENA 23 23 VS_OUT_MISC_SIDE_BUS_ENA 24 24 USE_VTX_GS_CUT_FLAG 25 25 USE_VTX_LINE_WIDTH 27 27 USE_VTX_VRS_RATE 28 28 BYPASS_VTX_RATE_COMBINER 29 29 BYPASS_PRIM_RATE_COMBINER 30 30 mmPA_CL_NANINF_CNTL 0 0x208 16 0 1 VTE_XY_INF_DISCARD 0 0 VTE_Z_INF_DISCARD 1 1 VTE_W_INF_DISCARD 2 2 VTE_0XNANINF_IS_0 3 3 VTE_XY_NAN_RETAIN 4 4 VTE_Z_NAN_RETAIN 5 5 VTE_W_NAN_RETAIN 6 6 VTE_W_RECIP_NAN_IS_0 7 7 VS_XY_NAN_TO_INF 8 8 VS_XY_INF_RETAIN 9 9 VS_Z_NAN_TO_INF 10 10 VS_Z_INF_RETAIN 11 11 VS_W_NAN_TO_INF 12 12 VS_W_INF_RETAIN 13 13 VS_CLIP_DIST_INF_DISCARD 14 14 VTE_NO_OUTPUT_NEG_0 20 20 mmPA_SU_LINE_STIPPLE_CNTL 0 0x209 4 0 1 LINE_STIPPLE_RESET 0 1 EXPAND_FULL_LENGTH 2 2 FRACTIONAL_ACCUM 3 3 DIAMOND_ADJUST 4 4 mmPA_SU_LINE_STIPPLE_SCALE 0 0x20a 1 0 1 LINE_STIPPLE_SCALE 0 31 mmPA_SU_PRIM_FILTER_CNTL 0 0x20b 11 0 1 TRIANGLE_FILTER_DISABLE 0 0 LINE_FILTER_DISABLE 1 1 POINT_FILTER_DISABLE 2 2 RECTANGLE_FILTER_DISABLE 3 3 TRIANGLE_EXPAND_ENA 4 4 LINE_EXPAND_ENA 5 5 POINT_EXPAND_ENA 6 6 RECTANGLE_EXPAND_ENA 7 7 PRIM_EXPAND_CONSTANT 8 15 XMAX_RIGHT_EXCLUSION 30 30 YMAX_BOTTOM_EXCLUSION 31 31 mmPA_SU_SMALL_PRIM_FILTER_CNTL 0 0x20c 5 0 1 SMALL_PRIM_FILTER_ENABLE 0 0 TRIANGLE_FILTER_DISABLE 1 1 LINE_FILTER_DISABLE 2 2 POINT_FILTER_DISABLE 3 3 RECTANGLE_FILTER_DISABLE 4 4 mmPA_CL_NGG_CNTL 0 0x20e 3 0 1 VERTEX_REUSE_OFF 0 0 INDEX_BUF_EDGE_FLAG_ENA 1 1 VERTEX_REUSE_DEPTH 2 9 mmPA_SU_OVER_RASTERIZATION_CNTL 0 0x20f 5 0 1 DISCARD_0_AREA_TRIANGLES 0 0 DISCARD_0_AREA_LINES 1 1 DISCARD_0_AREA_POINTS 2 2 DISCARD_0_AREA_RECTANGLES 3 3 USE_PROVOKING_ZW 4 4 mmPA_STEREO_CNTL 0 0x210 5 0 1 STEREO_MODE 1 4 RT_SLICE_MODE 5 7 RT_SLICE_OFFSET 8 11 VP_ID_MODE 16 18 VP_ID_OFFSET 19 22 mmPA_STATE_STEREO_X 0 0x211 1 0 1 STEREO_X_OFFSET 0 31 mmPA_CL_VRS_CNTL 0 0x212 6 0 1 VERTEX_RATE_COMBINER_MODE 0 2 PRIMITIVE_RATE_COMBINER_MODE 3 5 HTILE_RATE_COMBINER_MODE 6 8 SAMPLE_ITER_COMBINER_MODE 9 11 EXPOSE_VRS_PIXELS_MASK 13 13 CMASK_RATE_HINT_FORCE_ZERO 14 14 mmPA_SU_POINT_SIZE 0 0x280 2 0 1 HEIGHT 0 15 WIDTH 16 31 mmPA_SU_POINT_MINMAX 0 0x281 2 0 1 MIN_SIZE 0 15 MAX_SIZE 16 31 mmPA_SU_LINE_CNTL 0 0x282 1 0 1 WIDTH 0 15 mmPA_SC_LINE_STIPPLE 0 0x283 4 0 1 LINE_PATTERN 0 15 REPEAT_COUNT 16 23 PATTERN_BIT_ORDER 28 28 AUTO_RESET_CNTL 29 30 mmVGT_OUTPUT_PATH_CNTL 0 0x284 1 0 1 PATH_SELECT 0 2 mmVGT_HOS_CNTL 0 0x285 1 0 1 TESS_MODE 0 1 mmVGT_HOS_MAX_TESS_LEVEL 0 0x286 1 0 1 MAX_TESS 0 31 mmVGT_HOS_MIN_TESS_LEVEL 0 0x287 1 0 1 MIN_TESS 0 31 mmVGT_HOS_REUSE_DEPTH 0 0x288 1 0 1 REUSE_DEPTH 0 7 mmVGT_GROUP_PRIM_TYPE 0 0x289 4 0 1 PRIM_TYPE 0 4 RETAIN_ORDER 14 14 RETAIN_QUADS 15 15 PRIM_ORDER 16 18 mmVGT_GROUP_FIRST_DECR 0 0x28a 1 0 1 FIRST_DECR 0 3 mmVGT_GROUP_DECR 0 0x28b 1 0 1 DECR 0 3 mmVGT_GROUP_VECT_0_CNTL 0 0x28c 6 0 1 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 mmVGT_GROUP_VECT_1_CNTL 0 0x28d 6 0 1 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 mmVGT_GROUP_VECT_0_FMT_CNTL 0 0x28e 8 0 1 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 mmVGT_GROUP_VECT_1_FMT_CNTL 0 0x28f 8 0 1 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 mmVGT_GS_MODE 0 0x290 15 0 1 MODE 0 2 RESERVED_0 3 3 CUT_MODE 4 5 RESERVED_1 6 10 GS_C_PACK_EN 11 11 RESERVED_2 12 12 ES_PASSTHRU 13 13 COMPUTE_MODE 14 14 FAST_COMPUTE_MODE 15 15 ELEMENT_INFO_EN 16 16 PARTIAL_THD_AT_EOI 17 17 SUPPRESS_CUTS 18 18 ES_WRITE_OPTIMIZE 19 19 GS_WRITE_OPTIMIZE 20 20 ONCHIP 21 22 mmVGT_GS_ONCHIP_CNTL 0 0x291 3 0 1 ES_VERTS_PER_SUBGRP 0 10 GS_PRIMS_PER_SUBGRP 11 21 GS_INST_PRIMS_IN_SUBGRP 22 31 mmPA_SC_MODE_CNTL_0 0 0x292 6 0 1 MSAA_ENABLE 0 0 VPORT_SCISSOR_ENABLE 1 1 LINE_STIPPLE_ENABLE 2 2 SEND_UNLIT_STILES_TO_PKR 3 3 ALTERNATE_RBS_PER_TILE 5 5 COARSE_TILE_STARTS_ON_EVEN_RB 6 6 mmPA_SC_MODE_CNTL_1 0 0x293 24 0 1 WALK_SIZE 0 0 WALK_ALIGNMENT 1 1 WALK_ALIGN8_PRIM_FITS_ST 2 2 WALK_FENCE_ENABLE 3 3 WALK_FENCE_SIZE 4 6 SUPERTILE_WALK_ORDER_ENABLE 7 7 TILE_WALK_ORDER_ENABLE 8 8 TILE_COVER_DISABLE 9 9 TILE_COVER_NO_SCISSOR 10 10 ZMM_LINE_EXTENT 11 11 ZMM_LINE_OFFSET 12 12 ZMM_RECT_EXTENT 13 13 KILL_PIX_POST_HI_Z 14 14 KILL_PIX_POST_DETAIL_MASK 15 15 PS_ITER_SAMPLE 16 16 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE 17 17 MULTI_GPU_SUPERTILE_ENABLE 18 18 GPU_ID_OVERRIDE_ENABLE 19 19 GPU_ID_OVERRIDE 20 23 MULTI_GPU_PRIM_DISCARD_ENABLE 24 24 FORCE_EOV_CNTDWN_ENABLE 25 25 FORCE_EOV_REZ_ENABLE 26 26 OUT_OF_ORDER_PRIMITIVE_ENABLE 27 27 OUT_OF_ORDER_WATER_MARK 28 30 mmVGT_ENHANCE 0 0x294 1 0 1 MISC 0 31 mmVGT_GS_PER_ES 0 0x295 1 0 1 GS_PER_ES 0 10 mmVGT_ES_PER_GS 0 0x296 1 0 1 ES_PER_GS 0 10 mmVGT_GS_PER_VS 0 0x297 1 0 1 GS_PER_VS 0 3 mmVGT_GSVS_RING_OFFSET_1 0 0x298 1 0 1 OFFSET 0 14 mmVGT_GSVS_RING_OFFSET_2 0 0x299 1 0 1 OFFSET 0 14 mmVGT_GSVS_RING_OFFSET_3 0 0x29a 1 0 1 OFFSET 0 14 mmVGT_GS_OUT_PRIM_TYPE 0 0x29b 5 0 1 OUTPRIM_TYPE 0 5 OUTPRIM_TYPE_1 8 13 OUTPRIM_TYPE_2 16 21 OUTPRIM_TYPE_3 22 27 UNIQUE_TYPE_PER_STREAM 31 31 mmIA_ENHANCE 0 0x29c 1 0 1 MISC 0 31 mmVGT_DMA_SIZE 0 0x29d 1 0 1 NUM_INDICES 0 31 mmVGT_DMA_MAX_SIZE 0 0x29e 1 0 1 MAX_SIZE 0 31 mmVGT_DMA_INDEX_TYPE 0 0x29f 9 0 1 INDEX_TYPE 0 1 SWAP_MODE 2 3 BUF_TYPE 4 5 RDREQ_POLICY 6 7 ATC 8 8 NOT_EOP 9 9 REQ_PATH 10 10 MTYPE 11 13 DISABLE_INSTANCE_PACKING 14 14 mmWD_ENHANCE 0 0x2a0 1 0 1 MISC 0 31 mmVGT_PRIMITIVEID_EN 0 0x2a1 3 0 1 PRIMITIVEID_EN 0 0 DISABLE_RESET_ON_EOI 1 1 NGG_DISABLE_PROVOK_REUSE 2 2 mmVGT_DMA_NUM_INSTANCES 0 0x2a2 1 0 1 NUM_INSTANCES 0 31 mmVGT_PRIMITIVEID_RESET 0 0x2a3 1 0 1 VALUE 0 31 mmVGT_EVENT_INITIATOR 0 0x2a4 3 0 1 EVENT_TYPE 0 5 ADDRESS_HI 10 26 EXTENDED_EVENT 27 27 mmVGT_MULTI_PRIM_IB_RESET_EN 0 0x2a5 2 0 1 RESET_EN 0 0 MATCH_ALL_BITS 1 1 mmVGT_DRAW_PAYLOAD_CNTL 0 0x2a6 3 0 1 EN_REG_RT_INDEX 1 1 EN_PRIM_PAYLOAD 3 3 EN_DRAW_VP 4 4 mmVGT_INSTANCE_STEP_RATE_0 0 0x2a8 1 0 1 STEP_RATE 0 31 mmVGT_INSTANCE_STEP_RATE_1 0 0x2a9 1 0 1 STEP_RATE 0 31 mmIA_MULTI_VGT_PARAM 0 0x2aa 6 0 1 PRIMGROUP_SIZE 0 15 PARTIAL_VS_WAVE_ON 16 16 SWITCH_ON_EOP 17 17 PARTIAL_ES_WAVE_ON 18 18 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 mmVGT_ESGS_RING_ITEMSIZE 0 0x2ab 1 0 1 ITEMSIZE 0 14 mmVGT_GSVS_RING_ITEMSIZE 0 0x2ac 1 0 1 ITEMSIZE 0 14 mmVGT_REUSE_OFF 0 0x2ad 1 0 1 REUSE_OFF 0 0 mmVGT_VTX_CNT_EN 0 0x2ae 1 0 1 VTX_CNT_EN 0 0 mmDB_HTILE_SURFACE 0 0x2af 10 0 1 RESERVED_FIELD_1 0 0 FULL_CACHE 1 1 RESERVED_FIELD_2 2 2 RESERVED_FIELD_3 3 3 RESERVED_FIELD_4 4 9 RESERVED_FIELD_5 10 15 DST_OUTSIDE_ZERO_TO_ONE 16 16 RESERVED_FIELD_6 17 17 PIPE_ALIGNED 18 18 VRS_HTILE_ENCODING 19 20 mmDB_SRESULTS_COMPARE_STATE0 0 0x2b0 4 0 1 COMPAREFUNC0 0 2 COMPAREVALUE0 4 11 COMPAREMASK0 12 19 ENABLE0 24 24 mmDB_SRESULTS_COMPARE_STATE1 0 0x2b1 4 0 1 COMPAREFUNC1 0 2 COMPAREVALUE1 4 11 COMPAREMASK1 12 19 ENABLE1 24 24 mmDB_PRELOAD_CONTROL 0 0x2b2 4 0 1 START_X 0 7 START_Y 8 15 MAX_X 16 23 MAX_Y 24 31 mmVGT_STRMOUT_BUFFER_SIZE_0 0 0x2b4 1 0 1 SIZE 0 31 mmVGT_STRMOUT_VTX_STRIDE_0 0 0x2b5 1 0 1 STRIDE 0 9 mmVGT_STRMOUT_BUFFER_OFFSET_0 0 0x2b7 1 0 1 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_SIZE_1 0 0x2b8 1 0 1 SIZE 0 31 mmVGT_STRMOUT_VTX_STRIDE_1 0 0x2b9 1 0 1 STRIDE 0 9 mmVGT_STRMOUT_BUFFER_OFFSET_1 0 0x2bb 1 0 1 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_SIZE_2 0 0x2bc 1 0 1 SIZE 0 31 mmVGT_STRMOUT_VTX_STRIDE_2 0 0x2bd 1 0 1 STRIDE 0 9 mmVGT_STRMOUT_BUFFER_OFFSET_2 0 0x2bf 1 0 1 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_SIZE_3 0 0x2c0 1 0 1 SIZE 0 31 mmVGT_STRMOUT_VTX_STRIDE_3 0 0x2c1 1 0 1 STRIDE 0 9 mmVGT_STRMOUT_BUFFER_OFFSET_3 0 0x2c3 1 0 1 OFFSET 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0 0x2ca 1 0 1 OFFSET 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0 0x2cb 1 0 1 SIZE 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0 0x2cc 1 0 1 VERTEX_STRIDE 0 8 mmVGT_GS_MAX_VERT_OUT 0 0x2ce 1 0 1 MAX_VERT_OUT 0 10 mmGE_NGG_SUBGRP_CNTL 0 0x2d3 2 0 1 PRIM_AMP_FACTOR 0 8 THDS_PER_SUBGRP 9 17 mmVGT_TESS_DISTRIBUTION 0 0x2d4 5 0 1 ACCUM_ISOLINE 0 7 ACCUM_TRI 8 15 ACCUM_QUAD 16 23 DONUT_SPLIT 24 28 TRAP_SPLIT 29 31 mmVGT_SHADER_STAGES_EN 0 0x2d5 19 0 1 LS_EN 0 1 HS_EN 2 2 ES_EN 3 4 GS_EN 5 5 VS_EN 6 7 DYNAMIC_HS 8 8 DISPATCH_DRAW_EN 9 9 DIS_DEALLOC_ACCUM_0 10 10 DIS_DEALLOC_ACCUM_1 11 11 VS_WAVE_ID_EN 12 12 PRIMGEN_EN 13 13 ORDERED_ID_MODE 14 14 MAX_PRIMGRP_IN_WAVE 15 18 GS_FAST_LAUNCH 19 20 HS_W32_EN 21 21 GS_W32_EN 22 22 VS_W32_EN 23 23 NGG_WAVE_ID_EN 24 24 PRIMGEN_PASSTHRU_EN 25 25 mmVGT_LS_HS_CONFIG 0 0x2d6 3 0 1 NUM_PATCHES 0 7 HS_NUM_INPUT_CP 8 13 HS_NUM_OUTPUT_CP 14 19 mmVGT_GS_VERT_ITEMSIZE 0 0x2d7 1 0 1 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_1 0 0x2d8 1 0 1 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_2 0 0x2d9 1 0 1 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_3 0 0x2da 1 0 1 ITEMSIZE 0 14 mmVGT_TF_PARAM 0 0x2db 12 0 1 TYPE 0 1 PARTITIONING 2 4 TOPOLOGY 5 7 RESERVED_REDUC_AXIS 8 8 DEPRECATED 9 9 NUM_DS_WAVES_PER_SIMD 10 13 DISABLE_DONUTS 14 14 RDREQ_POLICY 15 16 DISTRIBUTION_MODE 17 18 DETECT_ONE 19 19 DETECT_ZERO 20 20 MTYPE 23 25 mmDB_ALPHA_TO_MASK 0 0x2dc 6 0 1 ALPHA_TO_MASK_ENABLE 0 0 ALPHA_TO_MASK_OFFSET0 8 9 ALPHA_TO_MASK_OFFSET1 10 11 ALPHA_TO_MASK_OFFSET2 12 13 ALPHA_TO_MASK_OFFSET3 14 15 OFFSET_ROUND 16 16 mmVGT_DISPATCH_DRAW_INDEX 0 0x2dd 1 0 1 MATCH_INDEX 0 31 mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0 0x2de 2 0 1 POLY_OFFSET_NEG_NUM_DB_BITS 0 7 POLY_OFFSET_DB_IS_FLOAT_FMT 8 8 mmPA_SU_POLY_OFFSET_CLAMP 0 0x2df 1 0 1 CLAMP 0 31 mmPA_SU_POLY_OFFSET_FRONT_SCALE 0 0x2e0 1 0 1 SCALE 0 31 mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0 0x2e1 1 0 1 OFFSET 0 31 mmPA_SU_POLY_OFFSET_BACK_SCALE 0 0x2e2 1 0 1 SCALE 0 31 mmPA_SU_POLY_OFFSET_BACK_OFFSET 0 0x2e3 1 0 1 OFFSET 0 31 mmVGT_GS_INSTANCE_CNT 0 0x2e4 3 0 1 ENABLE 0 0 CNT 2 8 EN_MAX_VERT_OUT_PER_GS_INSTANCE 31 31 mmVGT_STRMOUT_CONFIG 0 0x2e5 8 0 1 STREAMOUT_0_EN 0 0 STREAMOUT_1_EN 1 1 STREAMOUT_2_EN 2 2 STREAMOUT_3_EN 3 3 RAST_STREAM 4 6 EN_PRIMS_NEEDED_CNT 7 7 RAST_STREAM_MASK 8 11 USE_RAST_STREAM_MASK 31 31 mmVGT_STRMOUT_BUFFER_CONFIG 0 0x2e6 4 0 1 STREAM_0_BUFFER_EN 0 3 STREAM_1_BUFFER_EN 4 7 STREAM_2_BUFFER_EN 8 11 STREAM_3_BUFFER_EN 12 15 mmVGT_DMA_EVENT_INITIATOR 0 0x2e7 3 0 1 EVENT_TYPE 0 5 ADDRESS_HI 10 26 EXTENDED_EVENT 27 27 mmPA_SC_CENTROID_PRIORITY_0 0 0x2f5 8 0 1 DISTANCE_0 0 3 DISTANCE_1 4 7 DISTANCE_2 8 11 DISTANCE_3 12 15 DISTANCE_4 16 19 DISTANCE_5 20 23 DISTANCE_6 24 27 DISTANCE_7 28 31 mmPA_SC_CENTROID_PRIORITY_1 0 0x2f6 8 0 1 DISTANCE_8 0 3 DISTANCE_9 4 7 DISTANCE_10 8 11 DISTANCE_11 12 15 DISTANCE_12 16 19 DISTANCE_13 20 23 DISTANCE_14 24 27 DISTANCE_15 28 31 mmPA_SC_LINE_CNTL 0 0x2f7 5 0 1 EXPAND_LINE_WIDTH 9 9 LAST_PIXEL 10 10 PERPENDICULAR_ENDCAP_ENA 11 11 DX10_DIAMOND_TEST_ENA 12 12 EXTRA_DX_DY_PRECISION 13 13 mmPA_SC_AA_CONFIG 0 0x2f8 8 0 1 MSAA_NUM_SAMPLES 0 2 AA_MASK_CENTROID_DTMN 4 4 MAX_SAMPLE_DIST 13 16 MSAA_EXPOSED_SAMPLES 20 22 DETAIL_TO_EXPOSED_MODE 24 25 COVERAGE_TO_SHADER_SELECT 26 27 SAMPLE_COVERAGE_ENCODING 28 28 COVERED_CENTROID_IS_CENTER 29 29 mmPA_SU_VTX_CNTL 0 0x2f9 3 0 1 PIX_CENTER 0 0 ROUND_MODE 1 2 QUANT_MODE 3 5 mmPA_CL_GB_VERT_CLIP_ADJ 0 0x2fa 1 0 1 DATA_REGISTER 0 31 mmPA_CL_GB_VERT_DISC_ADJ 0 0x2fb 1 0 1 DATA_REGISTER 0 31 mmPA_CL_GB_HORZ_CLIP_ADJ 0 0x2fc 1 0 1 DATA_REGISTER 0 31 mmPA_CL_GB_HORZ_DISC_ADJ 0 0x2fd 1 0 1 DATA_REGISTER 0 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0 0x2fe 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0 0x2ff 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0 0x300 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0 0x301 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0 0x302 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0 0x303 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0 0x304 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0 0x305 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0 0x306 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0 0x307 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0 0x308 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0 0x309 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0 0x30a 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0 0x30b 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0 0x30c 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0 0x30d 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_MASK_X0Y0_X1Y0 0 0x30e 2 0 1 AA_MASK_X0Y0 0 15 AA_MASK_X1Y0 16 31 mmPA_SC_AA_MASK_X0Y1_X1Y1 0 0x30f 2 0 1 AA_MASK_X0Y1 0 15 AA_MASK_X1Y1 16 31 mmPA_SC_SHADER_CONTROL 0 0x310 4 0 1 REALIGN_DQUADS_AFTER_N_WAVES 0 1 LOAD_COLLISION_WAVEID 2 2 LOAD_INTRAWAVE_COLLISION 3 3 WAVE_BREAK_REGION_SIZE 5 6 mmPA_SC_BINNER_CNTL_0 0 0x311 12 0 1 BINNING_MODE 0 1 BIN_SIZE_X 2 2 BIN_SIZE_Y 3 3 BIN_SIZE_X_EXTEND 4 6 BIN_SIZE_Y_EXTEND 7 9 CONTEXT_STATES_PER_BIN 10 12 PERSISTENT_STATES_PER_BIN 13 17 DISABLE_START_OF_PRIM 18 18 FPOVS_PER_BATCH 19 26 OPTIMAL_BIN_SELECTION 27 27 FLUSH_ON_BINNING_TRANSITION 28 28 BIN_MAPPING_MODE 29 30 mmPA_SC_BINNER_CNTL_1 0 0x312 2 0 1 MAX_ALLOC_COUNT 0 15 MAX_PRIM_PER_BATCH 16 31 mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0 0x313 20 0 1 OVER_RAST_ENABLE 0 0 OVER_RAST_SAMPLE_SELECT 1 4 UNDER_RAST_ENABLE 5 5 UNDER_RAST_SAMPLE_SELECT 6 9 PBB_UNCERTAINTY_REGION_ENABLE 10 10 ZMM_TRI_EXTENT 11 11 ZMM_TRI_OFFSET 12 12 OVERRIDE_OVER_RAST_INNER_TO_NORMAL 13 13 OVERRIDE_UNDER_RAST_INNER_TO_NORMAL 14 14 DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE 15 15 UNCERTAINTY_REGION_MODE 16 17 OUTER_UNCERTAINTY_EDGERULE_OVERRIDE 18 18 INNER_UNCERTAINTY_EDGERULE_OVERRIDE 19 19 NULL_SQUAD_AA_MASK_ENABLE 20 20 COVERAGE_AA_MASK_ENABLE 21 21 PREZ_AA_MASK_ENABLE 22 22 POSTZ_AA_MASK_ENABLE 23 23 CENTROID_SAMPLE_OVERRIDE 24 24 UNCERTAINTY_REGION_MULT 25 26 UNCERTAINTY_REGION_PBB_MULT 27 28 mmPA_SC_NGG_MODE_CNTL 0 0x314 2 0 1 MAX_DEALLOCS_IN_WAVE 0 10 MAX_FPOVS_IN_WAVE 16 23 mmVGT_VERTEX_REUSE_BLOCK_CNTL 0 0x316 1 0 1 VTX_REUSE_DEPTH 0 7 mmVGT_OUT_DEALLOC_CNTL 0 0x317 1 0 1 DEALLOC_DIST 0 6 mmCB_COLOR0_BASE 0 0x318 1 0 1 BASE_256B 0 31 mmCB_COLOR0_PITCH 0 0x319 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR0_SLICE 0 0x31a 1 0 1 TILE_MAX 0 21 mmCB_COLOR0_VIEW 0 0x31b 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR0_INFO 0 0x31c 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR0_ATTRIB 0 0x31d 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR0_DCC_CONTROL 0 0x31e 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR0_CMASK 0 0x31f 1 0 1 BASE_256B 0 31 mmCB_COLOR0_CMASK_SLICE 0 0x320 1 0 1 TILE_MAX 0 13 mmCB_COLOR0_FMASK 0 0x321 1 0 1 BASE_256B 0 31 mmCB_COLOR0_FMASK_SLICE 0 0x322 1 0 1 TILE_MAX 0 21 mmCB_COLOR0_CLEAR_WORD0 0 0x323 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR0_CLEAR_WORD1 0 0x324 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR0_DCC_BASE 0 0x325 1 0 1 BASE_256B 0 31 mmCB_COLOR1_BASE 0 0x327 1 0 1 BASE_256B 0 31 mmCB_COLOR1_PITCH 0 0x328 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR1_SLICE 0 0x329 1 0 1 TILE_MAX 0 21 mmCB_COLOR1_VIEW 0 0x32a 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR1_INFO 0 0x32b 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR1_ATTRIB 0 0x32c 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR1_DCC_CONTROL 0 0x32d 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR1_CMASK 0 0x32e 1 0 1 BASE_256B 0 31 mmCB_COLOR1_CMASK_SLICE 0 0x32f 1 0 1 TILE_MAX 0 13 mmCB_COLOR1_FMASK 0 0x330 1 0 1 BASE_256B 0 31 mmCB_COLOR1_FMASK_SLICE 0 0x331 1 0 1 TILE_MAX 0 21 mmCB_COLOR1_CLEAR_WORD0 0 0x332 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR1_CLEAR_WORD1 0 0x333 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR1_DCC_BASE 0 0x334 1 0 1 BASE_256B 0 31 mmCB_COLOR2_BASE 0 0x336 1 0 1 BASE_256B 0 31 mmCB_COLOR2_PITCH 0 0x337 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR2_SLICE 0 0x338 1 0 1 TILE_MAX 0 21 mmCB_COLOR2_VIEW 0 0x339 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR2_INFO 0 0x33a 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR2_ATTRIB 0 0x33b 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR2_DCC_CONTROL 0 0x33c 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR2_CMASK 0 0x33d 1 0 1 BASE_256B 0 31 mmCB_COLOR2_CMASK_SLICE 0 0x33e 1 0 1 TILE_MAX 0 13 mmCB_COLOR2_FMASK 0 0x33f 1 0 1 BASE_256B 0 31 mmCB_COLOR2_FMASK_SLICE 0 0x340 1 0 1 TILE_MAX 0 21 mmCB_COLOR2_CLEAR_WORD0 0 0x341 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR2_CLEAR_WORD1 0 0x342 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR2_DCC_BASE 0 0x343 1 0 1 BASE_256B 0 31 mmCB_COLOR3_BASE 0 0x345 1 0 1 BASE_256B 0 31 mmCB_COLOR3_PITCH 0 0x346 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR3_SLICE 0 0x347 1 0 1 TILE_MAX 0 21 mmCB_COLOR3_VIEW 0 0x348 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR3_INFO 0 0x349 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR3_ATTRIB 0 0x34a 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR3_DCC_CONTROL 0 0x34b 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR3_CMASK 0 0x34c 1 0 1 BASE_256B 0 31 mmCB_COLOR3_CMASK_SLICE 0 0x34d 1 0 1 TILE_MAX 0 13 mmCB_COLOR3_FMASK 0 0x34e 1 0 1 BASE_256B 0 31 mmCB_COLOR3_FMASK_SLICE 0 0x34f 1 0 1 TILE_MAX 0 21 mmCB_COLOR3_CLEAR_WORD0 0 0x350 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR3_CLEAR_WORD1 0 0x351 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR3_DCC_BASE 0 0x352 1 0 1 BASE_256B 0 31 mmCB_COLOR4_BASE 0 0x354 1 0 1 BASE_256B 0 31 mmCB_COLOR4_PITCH 0 0x355 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR4_SLICE 0 0x356 1 0 1 TILE_MAX 0 21 mmCB_COLOR4_VIEW 0 0x357 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR4_INFO 0 0x358 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR4_ATTRIB 0 0x359 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR4_DCC_CONTROL 0 0x35a 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR4_CMASK 0 0x35b 1 0 1 BASE_256B 0 31 mmCB_COLOR4_CMASK_SLICE 0 0x35c 1 0 1 TILE_MAX 0 13 mmCB_COLOR4_FMASK 0 0x35d 1 0 1 BASE_256B 0 31 mmCB_COLOR4_FMASK_SLICE 0 0x35e 1 0 1 TILE_MAX 0 21 mmCB_COLOR4_CLEAR_WORD0 0 0x35f 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR4_CLEAR_WORD1 0 0x360 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR4_DCC_BASE 0 0x361 1 0 1 BASE_256B 0 31 mmCB_COLOR5_BASE 0 0x363 1 0 1 BASE_256B 0 31 mmCB_COLOR5_PITCH 0 0x364 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR5_SLICE 0 0x365 1 0 1 TILE_MAX 0 21 mmCB_COLOR5_VIEW 0 0x366 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR5_INFO 0 0x367 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR5_ATTRIB 0 0x368 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR5_DCC_CONTROL 0 0x369 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR5_CMASK 0 0x36a 1 0 1 BASE_256B 0 31 mmCB_COLOR5_CMASK_SLICE 0 0x36b 1 0 1 TILE_MAX 0 13 mmCB_COLOR5_FMASK 0 0x36c 1 0 1 BASE_256B 0 31 mmCB_COLOR5_FMASK_SLICE 0 0x36d 1 0 1 TILE_MAX 0 21 mmCB_COLOR5_CLEAR_WORD0 0 0x36e 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR5_CLEAR_WORD1 0 0x36f 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR5_DCC_BASE 0 0x370 1 0 1 BASE_256B 0 31 mmCB_COLOR6_BASE 0 0x372 1 0 1 BASE_256B 0 31 mmCB_COLOR6_PITCH 0 0x373 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR6_SLICE 0 0x374 1 0 1 TILE_MAX 0 21 mmCB_COLOR6_VIEW 0 0x375 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR6_INFO 0 0x376 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR6_ATTRIB 0 0x377 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR6_DCC_CONTROL 0 0x378 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR6_CMASK 0 0x379 1 0 1 BASE_256B 0 31 mmCB_COLOR6_CMASK_SLICE 0 0x37a 1 0 1 TILE_MAX 0 13 mmCB_COLOR6_FMASK 0 0x37b 1 0 1 BASE_256B 0 31 mmCB_COLOR6_FMASK_SLICE 0 0x37c 1 0 1 TILE_MAX 0 21 mmCB_COLOR6_CLEAR_WORD0 0 0x37d 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR6_CLEAR_WORD1 0 0x37e 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR6_DCC_BASE 0 0x37f 1 0 1 BASE_256B 0 31 mmCB_COLOR7_BASE 0 0x381 1 0 1 BASE_256B 0 31 mmCB_COLOR7_PITCH 0 0x382 2 0 1 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR7_SLICE 0 0x383 1 0 1 TILE_MAX 0 21 mmCB_COLOR7_VIEW 0 0x384 3 0 1 SLICE_START 0 12 SLICE_MAX 13 25 MIP_LEVEL 26 29 mmCB_COLOR7_INFO 0 0x385 19 0 1 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 NBC_TILING 31 31 mmCB_COLOR7_ATTRIB 0 0x386 8 0 1 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 DISABLE_FMASK_NOFETCH_OPT 18 18 LIMIT_COLOR_FETCH_TO_256B_MAX 19 19 mmCB_COLOR7_DCC_CONTROL 0 0x387 14 0 1 OVERWRITE_COMBINER_DISABLE 0 0 KEY_CLEAR_ENABLE 1 1 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 INDEPENDENT_128B_BLOCKS 20 20 SKIP_LOW_COMP_RATIO 21 21 DCC_COMPRESS_DISABLE 22 22 mmCB_COLOR7_CMASK 0 0x388 1 0 1 BASE_256B 0 31 mmCB_COLOR7_CMASK_SLICE 0 0x389 1 0 1 TILE_MAX 0 13 mmCB_COLOR7_FMASK 0 0x38a 1 0 1 BASE_256B 0 31 mmCB_COLOR7_FMASK_SLICE 0 0x38b 1 0 1 TILE_MAX 0 21 mmCB_COLOR7_CLEAR_WORD0 0 0x38c 1 0 1 CLEAR_WORD0 0 31 mmCB_COLOR7_CLEAR_WORD1 0 0x38d 1 0 1 CLEAR_WORD1 0 31 mmCB_COLOR7_DCC_BASE 0 0x38e 1 0 1 BASE_256B 0 31 mmCB_COLOR0_BASE_EXT 0 0x390 1 0 1 BASE_256B 0 7 mmCB_COLOR1_BASE_EXT 0 0x391 1 0 1 BASE_256B 0 7 mmCB_COLOR2_BASE_EXT 0 0x392 1 0 1 BASE_256B 0 7 mmCB_COLOR3_BASE_EXT 0 0x393 1 0 1 BASE_256B 0 7 mmCB_COLOR4_BASE_EXT 0 0x394 1 0 1 BASE_256B 0 7 mmCB_COLOR5_BASE_EXT 0 0x395 1 0 1 BASE_256B 0 7 mmCB_COLOR6_BASE_EXT 0 0x396 1 0 1 BASE_256B 0 7 mmCB_COLOR7_BASE_EXT 0 0x397 1 0 1 BASE_256B 0 7 mmCB_COLOR0_CMASK_BASE_EXT 0 0x398 1 0 1 BASE_256B 0 7 mmCB_COLOR1_CMASK_BASE_EXT 0 0x399 1 0 1 BASE_256B 0 7 mmCB_COLOR2_CMASK_BASE_EXT 0 0x39a 1 0 1 BASE_256B 0 7 mmCB_COLOR3_CMASK_BASE_EXT 0 0x39b 1 0 1 BASE_256B 0 7 mmCB_COLOR4_CMASK_BASE_EXT 0 0x39c 1 0 1 BASE_256B 0 7 mmCB_COLOR5_CMASK_BASE_EXT 0 0x39d 1 0 1 BASE_256B 0 7 mmCB_COLOR6_CMASK_BASE_EXT 0 0x39e 1 0 1 BASE_256B 0 7 mmCB_COLOR7_CMASK_BASE_EXT 0 0x39f 1 0 1 BASE_256B 0 7 mmCB_COLOR0_FMASK_BASE_EXT 0 0x3a0 1 0 1 BASE_256B 0 7 mmCB_COLOR1_FMASK_BASE_EXT 0 0x3a1 1 0 1 BASE_256B 0 7 mmCB_COLOR2_FMASK_BASE_EXT 0 0x3a2 1 0 1 BASE_256B 0 7 mmCB_COLOR3_FMASK_BASE_EXT 0 0x3a3 1 0 1 BASE_256B 0 7 mmCB_COLOR4_FMASK_BASE_EXT 0 0x3a4 1 0 1 BASE_256B 0 7 mmCB_COLOR5_FMASK_BASE_EXT 0 0x3a5 1 0 1 BASE_256B 0 7 mmCB_COLOR6_FMASK_BASE_EXT 0 0x3a6 1 0 1 BASE_256B 0 7 mmCB_COLOR7_FMASK_BASE_EXT 0 0x3a7 1 0 1 BASE_256B 0 7 mmCB_COLOR0_DCC_BASE_EXT 0 0x3a8 1 0 1 BASE_256B 0 7 mmCB_COLOR1_DCC_BASE_EXT 0 0x3a9 1 0 1 BASE_256B 0 7 mmCB_COLOR2_DCC_BASE_EXT 0 0x3aa 1 0 1 BASE_256B 0 7 mmCB_COLOR3_DCC_BASE_EXT 0 0x3ab 1 0 1 BASE_256B 0 7 mmCB_COLOR4_DCC_BASE_EXT 0 0x3ac 1 0 1 BASE_256B 0 7 mmCB_COLOR5_DCC_BASE_EXT 0 0x3ad 1 0 1 BASE_256B 0 7 mmCB_COLOR6_DCC_BASE_EXT 0 0x3ae 1 0 1 BASE_256B 0 7 mmCB_COLOR7_DCC_BASE_EXT 0 0x3af 1 0 1 BASE_256B 0 7 mmCB_COLOR0_ATTRIB2 0 0x3b0 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR1_ATTRIB2 0 0x3b1 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR2_ATTRIB2 0 0x3b2 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR3_ATTRIB2 0 0x3b3 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR4_ATTRIB2 0 0x3b4 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR5_ATTRIB2 0 0x3b5 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR6_ATTRIB2 0 0x3b6 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR7_ATTRIB2 0 0x3b7 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 mmCB_COLOR0_ATTRIB3 0 0x3b8 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR1_ATTRIB3 0 0x3b9 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR2_ATTRIB3 0 0x3ba 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR3_ATTRIB3 0 0x3bb 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR4_ATTRIB3 0 0x3bc 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR5_ATTRIB3 0 0x3bd 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR6_ATTRIB3 0 0x3be 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCB_COLOR7_ATTRIB3 0 0x3bf 9 0 1 MIP0_DEPTH 0 12 META_LINEAR 13 13 COLOR_SW_MODE 14 18 FMASK_SW_MODE 19 23 RESOURCE_TYPE 24 25 CMASK_PIPE_ALIGNED 26 26 RESOURCE_LEVEL 27 29 DCC_PIPE_ALIGNED 30 30 VRS_RATE_HINT_ENABLE 31 31 mmCP_EOP_DONE_ADDR_LO 0 0x2000 1 0 1 ADDR_LO 2 31 mmCP_EOP_DONE_ADDR_HI 0 0x2001 1 0 1 ADDR_HI 0 15 mmCP_EOP_DONE_DATA_LO 0 0x2002 1 0 1 DATA_LO 0 31 mmCP_EOP_DONE_DATA_HI 0 0x2003 1 0 1 DATA_HI 0 31 mmCP_EOP_LAST_FENCE_LO 0 0x2004 1 0 1 LAST_FENCE_LO 0 31 mmCP_EOP_LAST_FENCE_HI 0 0x2005 1 0 1 LAST_FENCE_HI 0 31 mmCP_STREAM_OUT_ADDR_LO 0 0x2006 1 0 1 STREAM_OUT_ADDR_LO 2 31 mmCP_STREAM_OUT_ADDR_HI 0 0x2007 1 0 1 STREAM_OUT_ADDR_HI 0 15 mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0 0x2008 1 0 1 NUM_PRIM_WRITTEN_CNT0_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0 0x2009 1 0 1 NUM_PRIM_WRITTEN_CNT0_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0 0x200a 1 0 1 NUM_PRIM_NEEDED_CNT0_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0 0x200b 1 0 1 NUM_PRIM_NEEDED_CNT0_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0 0x200c 1 0 1 NUM_PRIM_WRITTEN_CNT1_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0 0x200d 1 0 1 NUM_PRIM_WRITTEN_CNT1_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0 0x200e 1 0 1 NUM_PRIM_NEEDED_CNT1_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0 0x200f 1 0 1 NUM_PRIM_NEEDED_CNT1_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0 0x2010 1 0 1 NUM_PRIM_WRITTEN_CNT2_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0 0x2011 1 0 1 NUM_PRIM_WRITTEN_CNT2_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0 0x2012 1 0 1 NUM_PRIM_NEEDED_CNT2_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0 0x2013 1 0 1 NUM_PRIM_NEEDED_CNT2_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0 0x2014 1 0 1 NUM_PRIM_WRITTEN_CNT3_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0 0x2015 1 0 1 NUM_PRIM_WRITTEN_CNT3_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0 0x2016 1 0 1 NUM_PRIM_NEEDED_CNT3_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0 0x2017 1 0 1 NUM_PRIM_NEEDED_CNT3_HI 0 31 mmCP_PIPE_STATS_ADDR_LO 0 0x2018 1 0 1 PIPE_STATS_ADDR_LO 2 31 mmCP_PIPE_STATS_ADDR_HI 0 0x2019 1 0 1 PIPE_STATS_ADDR_HI 0 15 mmCP_VGT_IAVERT_COUNT_LO 0 0x201a 1 0 1 IAVERT_COUNT_LO 0 31 mmCP_VGT_IAVERT_COUNT_HI 0 0x201b 1 0 1 IAVERT_COUNT_HI 0 31 mmCP_VGT_IAPRIM_COUNT_LO 0 0x201c 1 0 1 IAPRIM_COUNT_LO 0 31 mmCP_VGT_IAPRIM_COUNT_HI 0 0x201d 1 0 1 IAPRIM_COUNT_HI 0 31 mmCP_VGT_GSPRIM_COUNT_LO 0 0x201e 1 0 1 GSPRIM_COUNT_LO 0 31 mmCP_VGT_GSPRIM_COUNT_HI 0 0x201f 1 0 1 GSPRIM_COUNT_HI 0 31 mmCP_VGT_VSINVOC_COUNT_LO 0 0x2020 1 0 1 VSINVOC_COUNT_LO 0 31 mmCP_VGT_VSINVOC_COUNT_HI 0 0x2021 1 0 1 VSINVOC_COUNT_HI 0 31 mmCP_VGT_GSINVOC_COUNT_LO 0 0x2022 1 0 1 GSINVOC_COUNT_LO 0 31 mmCP_VGT_GSINVOC_COUNT_HI 0 0x2023 1 0 1 GSINVOC_COUNT_HI 0 31 mmCP_VGT_HSINVOC_COUNT_LO 0 0x2024 1 0 1 HSINVOC_COUNT_LO 0 31 mmCP_VGT_HSINVOC_COUNT_HI 0 0x2025 1 0 1 HSINVOC_COUNT_HI 0 31 mmCP_VGT_DSINVOC_COUNT_LO 0 0x2026 1 0 1 DSINVOC_COUNT_LO 0 31 mmCP_VGT_DSINVOC_COUNT_HI 0 0x2027 1 0 1 DSINVOC_COUNT_HI 0 31 mmCP_PA_CINVOC_COUNT_LO 0 0x2028 1 0 1 CINVOC_COUNT_LO 0 31 mmCP_PA_CINVOC_COUNT_HI 0 0x2029 1 0 1 CINVOC_COUNT_HI 0 31 mmCP_PA_CPRIM_COUNT_LO 0 0x202a 1 0 1 CPRIM_COUNT_LO 0 31 mmCP_PA_CPRIM_COUNT_HI 0 0x202b 1 0 1 CPRIM_COUNT_HI 0 31 mmCP_SC_PSINVOC_COUNT0_LO 0 0x202c 1 0 1 PSINVOC_COUNT0_LO 0 31 mmCP_SC_PSINVOC_COUNT0_HI 0 0x202d 1 0 1 PSINVOC_COUNT0_HI 0 31 mmCP_SC_PSINVOC_COUNT1_LO 0 0x202e 1 0 1 OBSOLETE 0 31 mmCP_SC_PSINVOC_COUNT1_HI 0 0x202f 1 0 1 OBSOLETE 0 31 mmCP_VGT_CSINVOC_COUNT_LO 0 0x2030 1 0 1 CSINVOC_COUNT_LO 0 31 mmCP_VGT_CSINVOC_COUNT_HI 0 0x2031 1 0 1 CSINVOC_COUNT_HI 0 31 mmCP_PIPE_STATS_CONTROL 0 0x203d 1 0 1 CACHE_POLICY 25 26 mmCP_STREAM_OUT_CONTROL 0 0x203e 1 0 1 CACHE_POLICY 25 26 mmCP_STRMOUT_CNTL 0 0x203f 1 0 1 OFFSET_UPDATE_DONE 0 0 mmSCRATCH_REG0 0 0x2040 1 0 1 SCRATCH_REG0 0 31 mmSCRATCH_REG1 0 0x2041 1 0 1 SCRATCH_REG1 0 31 mmSCRATCH_REG2 0 0x2042 1 0 1 SCRATCH_REG2 0 31 mmSCRATCH_REG3 0 0x2043 1 0 1 SCRATCH_REG3 0 31 mmSCRATCH_REG4 0 0x2044 1 0 1 SCRATCH_REG4 0 31 mmSCRATCH_REG5 0 0x2045 1 0 1 SCRATCH_REG5 0 31 mmSCRATCH_REG6 0 0x2046 1 0 1 SCRATCH_REG6 0 31 mmSCRATCH_REG7 0 0x2047 1 0 1 SCRATCH_REG7 0 31 mmSCRATCH_REG_ATOMIC 0 0x2048 5 0 1 IMMED 0 23 ID 24 26 reserved27 27 27 OP 28 30 reserved31 31 31 mmSCRATCH_REG_CMPSWAP_ATOMIC 0 0x2048 6 0 1 IMMED_COMPARE 0 11 IMMED_REPLACE 12 23 ID 24 26 reserved27 27 27 OP 28 30 reserved31 31 31 mmCP_APPEND_DDID_CNT 0 0x204b 1 0 1 DATA 0 7 mmCP_APPEND_DATA_HI 0 0x204c 1 0 1 DATA 0 31 mmCP_APPEND_LAST_CS_FENCE_HI 0 0x204d 1 0 1 LAST_FENCE 0 31 mmCP_APPEND_LAST_PS_FENCE_HI 0 0x204e 1 0 1 LAST_FENCE 0 31 mmSCRATCH_UMSK 0 0x2050 2 0 1 OBSOLETE_UMSK 0 7 OBSOLETE_SWAP 16 17 mmSCRATCH_ADDR 0 0x2051 1 0 1 OBSOLETE_ADDR 0 31 mmCP_PFP_ATOMIC_PREOP_LO 0 0x2052 1 0 1 ATOMIC_PREOP_LO 0 31 mmCP_PFP_ATOMIC_PREOP_HI 0 0x2053 1 0 1 ATOMIC_PREOP_HI 0 31 mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0 0x2054 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0 0x2055 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0 0x2056 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0 0x2057 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_APPEND_ADDR_LO 0 0x2058 1 0 1 MEM_ADDR_LO 2 31 mmCP_APPEND_ADDR_HI 0 0x2059 4 0 1 MEM_ADDR_HI 0 15 CS_PS_SEL 16 16 CACHE_POLICY 25 26 COMMAND 29 31 mmCP_APPEND_DATA 0 0x205a 1 0 1 DATA 0 31 mmCP_APPEND_DATA_LO 0 0x205a 1 0 1 DATA 0 31 mmCP_APPEND_LAST_CS_FENCE 0 0x205b 1 0 1 LAST_FENCE 0 31 mmCP_APPEND_LAST_CS_FENCE_LO 0 0x205b 1 0 1 LAST_FENCE 0 31 mmCP_APPEND_LAST_PS_FENCE 0 0x205c 1 0 1 LAST_FENCE 0 31 mmCP_APPEND_LAST_PS_FENCE_LO 0 0x205c 1 0 1 LAST_FENCE 0 31 mmCP_ATOMIC_PREOP_LO 0 0x205d 1 0 1 ATOMIC_PREOP_LO 0 31 mmCP_ME_ATOMIC_PREOP_LO 0 0x205d 1 0 1 ATOMIC_PREOP_LO 0 31 mmCP_ATOMIC_PREOP_HI 0 0x205e 1 0 1 ATOMIC_PREOP_HI 0 31 mmCP_ME_ATOMIC_PREOP_HI 0 0x205e 1 0 1 ATOMIC_PREOP_HI 0 31 mmCP_GDS_ATOMIC0_PREOP_LO 0 0x205f 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_ME_GDS_ATOMIC0_PREOP_LO 0 0x205f 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_GDS_ATOMIC0_PREOP_HI 0 0x2060 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_ME_GDS_ATOMIC0_PREOP_HI 0 0x2060 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_GDS_ATOMIC1_PREOP_LO 0 0x2061 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_ME_GDS_ATOMIC1_PREOP_LO 0 0x2061 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_GDS_ATOMIC1_PREOP_HI 0 0x2062 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_ME_GDS_ATOMIC1_PREOP_HI 0 0x2062 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_ME_MC_WADDR_LO 0 0x2069 1 0 1 ME_MC_WADDR_LO 2 31 mmCP_ME_MC_WADDR_HI 0 0x206a 2 0 1 ME_MC_WADDR_HI 0 15 CACHE_POLICY 22 23 mmCP_ME_MC_WDATA_LO 0 0x206b 1 0 1 ME_MC_WDATA_LO 0 31 mmCP_ME_MC_WDATA_HI 0 0x206c 1 0 1 ME_MC_WDATA_HI 0 31 mmCP_ME_MC_RADDR_LO 0 0x206d 1 0 1 ME_MC_RADDR_LO 2 31 mmCP_ME_MC_RADDR_HI 0 0x206e 2 0 1 ME_MC_RADDR_HI 0 15 CACHE_POLICY 22 23 mmCP_SEM_WAIT_TIMER 0 0x206f 1 0 1 SEM_WAIT_TIMER 0 31 mmCP_SIG_SEM_ADDR_LO 0 0x2070 2 0 1 SEM_PRIV 0 0 SEM_ADDR_LO 3 31 mmCP_SIG_SEM_ADDR_HI 0 0x2071 5 0 1 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 mmCP_WAIT_REG_MEM_TIMEOUT 0 0x2074 1 0 1 WAIT_REG_MEM_TIMEOUT 0 31 mmCP_WAIT_SEM_ADDR_LO 0 0x2075 2 0 1 SEM_PRIV 0 0 SEM_ADDR_LO 3 31 mmCP_WAIT_SEM_ADDR_HI 0 0x2076 5 0 1 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 mmCP_DMA_PFP_CONTROL 0 0x2077 7 0 1 MEMLOG_CLEAR 10 10 SRC_CACHE_POLICY 13 14 SRC_VOLATLE 15 15 DST_SELECT 20 21 DST_CACHE_POLICY 25 26 DST_VOLATLE 27 27 SRC_SELECT 29 30 mmCP_DMA_ME_CONTROL 0 0x2078 7 0 1 MEMLOG_CLEAR 10 10 SRC_CACHE_POLICY 13 14 SRC_VOLATLE 15 15 DST_SELECT 20 21 DST_CACHE_POLICY 25 26 DST_VOLATLE 27 27 SRC_SELECT 29 30 mmCP_COHER_BASE_HI 0 0x2079 1 0 1 COHER_BASE_HI_256B 0 7 mmCP_COHER_START_DELAY 0 0x207b 1 0 1 START_DELAY_COUNT 0 5 mmCP_COHER_CNTL 0 0x207c 13 0 1 TC_NC_ACTION_ENA 3 3 TC_WC_ACTION_ENA 4 4 TC_INV_METADATA_ACTION_ENA 5 5 TCL1_VOL_ACTION_ENA 15 15 TC_WB_ACTION_ENA 18 18 TCL1_ACTION_ENA 22 22 TC_ACTION_ENA 23 23 CB_ACTION_ENA 25 25 DB_ACTION_ENA 26 26 SH_KCACHE_ACTION_ENA 27 27 SH_KCACHE_VOL_ACTION_ENA 28 28 SH_ICACHE_ACTION_ENA 29 29 SH_KCACHE_WB_ACTION_ENA 30 30 mmCP_COHER_SIZE 0 0x207d 1 0 1 COHER_SIZE_256B 0 31 mmCP_COHER_BASE 0 0x207e 1 0 1 COHER_BASE_256B 0 31 mmCP_COHER_STATUS 0 0x207f 2 0 1 MEID 24 25 STATUS 31 31 mmCP_DMA_ME_SRC_ADDR 0 0x2080 1 0 1 SRC_ADDR 0 31 mmCP_DMA_ME_SRC_ADDR_HI 0 0x2081 1 0 1 SRC_ADDR_HI 0 15 mmCP_DMA_ME_DST_ADDR 0 0x2082 1 0 1 DST_ADDR 0 31 mmCP_DMA_ME_DST_ADDR_HI 0 0x2083 1 0 1 DST_ADDR_HI 0 15 mmCP_DMA_ME_COMMAND 0 0x2084 7 0 1 BYTE_COUNT 0 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 DIS_WC 31 31 mmCP_DMA_PFP_SRC_ADDR 0 0x2085 1 0 1 SRC_ADDR 0 31 mmCP_DMA_PFP_SRC_ADDR_HI 0 0x2086 1 0 1 SRC_ADDR_HI 0 15 mmCP_DMA_PFP_DST_ADDR 0 0x2087 1 0 1 DST_ADDR 0 31 mmCP_DMA_PFP_DST_ADDR_HI 0 0x2088 1 0 1 DST_ADDR_HI 0 15 mmCP_DMA_PFP_COMMAND 0 0x2089 7 0 1 BYTE_COUNT 0 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 DIS_WC 31 31 mmCP_DMA_CNTL 0 0x208a 7 0 1 UTCL1_FAULT_CONTROL 0 0 WATCH_CONTROL 1 1 MIN_AVAILSZ 4 5 BUFFER_DEPTH 16 24 PIO_FIFO_EMPTY 28 28 PIO_FIFO_FULL 29 29 PIO_COUNT 30 31 mmCP_DMA_READ_TAGS 0 0x208b 2 0 1 DMA_READ_TAG 0 25 DMA_READ_TAG_VALID 28 28 mmCP_COHER_SIZE_HI 0 0x208c 1 0 1 COHER_SIZE_HI_256B 0 7 mmCP_PFP_IB_CONTROL 0 0x208d 1 0 1 IB_EN 0 7 mmCP_PFP_LOAD_CONTROL 0 0x208e 5 0 1 CONFIG_REG_EN 0 0 CNTX_REG_EN 1 1 UCONFIG_REG_EN 15 15 SH_GFX_REG_EN 16 16 SH_CS_REG_EN 24 24 mmCP_SCRATCH_INDEX 0 0x208f 2 0 1 SCRATCH_INDEX 0 8 SCRATCH_INDEX_64BIT_MODE 31 31 mmCP_SCRATCH_DATA 0 0x2090 1 0 1 SCRATCH_DATA 0 31 mmCP_RB_OFFSET 0 0x2091 1 0 1 RB_OFFSET 0 19 mmCP_IB2_OFFSET 0 0x2093 1 0 1 IB2_OFFSET 0 19 mmCP_IB2_PREAMBLE_BEGIN 0 0x2096 1 0 1 IB2_PREAMBLE_BEGIN 0 19 mmCP_IB2_PREAMBLE_END 0 0x2097 1 0 1 IB2_PREAMBLE_END 0 19 mmCP_CE_IB1_OFFSET 0 0x2098 1 0 1 IB1_OFFSET 0 19 mmCP_CE_IB2_OFFSET 0 0x2099 1 0 1 IB2_OFFSET 0 19 mmCP_CE_COUNTER 0 0x209a 1 0 1 CONST_ENGINE_COUNT 0 31 mmCP_DMA_ME_CMD_ADDR_LO 0 0x209c 2 0 1 RSVD 0 1 ADDR_LO 2 31 mmCP_DMA_ME_CMD_ADDR_HI 0 0x209d 2 0 1 ADDR_HI 0 15 RSVD 16 31 mmCP_DMA_PFP_CMD_ADDR_LO 0 0x209e 2 0 1 RSVD 0 1 ADDR_LO 2 31 mmCP_DMA_PFP_CMD_ADDR_HI 0 0x209f 2 0 1 ADDR_HI 0 15 RSVD 16 31 mmCP_APPEND_CMD_ADDR_LO 0 0x20a0 2 0 1 RSVD 0 1 ADDR_LO 2 31 mmCP_APPEND_CMD_ADDR_HI 0 0x20a1 2 0 1 ADDR_HI 0 15 RSVD 16 31 mmUCONFIG_RESERVED_REG0 0 0x20a2 1 0 1 DATA 0 31 mmUCONFIG_RESERVED_REG1 0 0x20a3 1 0 1 DATA 0 31 mmCP_CE_ATOMIC_PREOP_LO 0 0x20a8 1 0 1 ATOMIC_PREOP_LO 0 31 mmCP_CE_ATOMIC_PREOP_HI 0 0x20a9 1 0 1 ATOMIC_PREOP_HI 0 31 mmCP_CE_GDS_ATOMIC0_PREOP_LO 0 0x20aa 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_CE_GDS_ATOMIC0_PREOP_HI 0 0x20ab 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_CE_GDS_ATOMIC1_PREOP_LO 0 0x20ac 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_CE_GDS_ATOMIC1_PREOP_HI 0 0x20ad 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_CE_INIT_CMD_BUFSZ 0 0x20bd 1 0 1 INIT_CMD_REQSZ 0 11 mmCP_CE_IB1_CMD_BUFSZ 0 0x20be 1 0 1 IB1_CMD_REQSZ 0 19 mmCP_CE_IB2_CMD_BUFSZ 0 0x20bf 1 0 1 IB2_CMD_REQSZ 0 19 mmCP_IB2_CMD_BUFSZ 0 0x20c1 1 0 1 IB2_CMD_REQSZ 0 19 mmCP_ST_CMD_BUFSZ 0 0x20c2 1 0 1 ST_CMD_REQSZ 0 19 mmCP_CE_INIT_BASE_LO 0 0x20c3 1 0 1 INIT_BASE_LO 5 31 mmCP_CE_INIT_BASE_HI 0 0x20c4 1 0 1 INIT_BASE_HI 0 15 mmCP_CE_INIT_BUFSZ 0 0x20c5 1 0 1 INIT_BUFSZ 0 11 mmCP_CE_IB1_BASE_LO 0 0x20c6 1 0 1 IB1_BASE_LO 2 31 mmCP_CE_IB1_BASE_HI 0 0x20c7 1 0 1 IB1_BASE_HI 0 15 mmCP_CE_IB1_BUFSZ 0 0x20c8 1 0 1 IB1_BUFSZ 0 19 mmCP_CE_IB2_BASE_LO 0 0x20c9 1 0 1 IB2_BASE_LO 2 31 mmCP_CE_IB2_BASE_HI 0 0x20ca 1 0 1 IB2_BASE_HI 0 15 mmCP_CE_IB2_BUFSZ 0 0x20cb 1 0 1 IB2_BUFSZ 0 19 mmCP_IB1_BASE_LO 0 0x20cc 1 0 1 IB1_BASE_LO 2 31 mmCP_IB1_BASE_HI 0 0x20cd 1 0 1 IB1_BASE_HI 0 15 mmCP_IB1_BUFSZ 0 0x20ce 1 0 1 IB1_BUFSZ 0 19 mmCP_IB2_BASE_LO 0 0x20cf 1 0 1 IB2_BASE_LO 2 31 mmCP_IB2_BASE_HI 0 0x20d0 1 0 1 IB2_BASE_HI 0 15 mmCP_IB2_BUFSZ 0 0x20d1 1 0 1 IB2_BUFSZ 0 19 mmCP_ST_BASE_LO 0 0x20d2 1 0 1 ST_BASE_LO 2 31 mmCP_ST_BASE_HI 0 0x20d3 1 0 1 ST_BASE_HI 0 15 mmCP_ST_BUFSZ 0 0x20d4 1 0 1 ST_BUFSZ 0 19 mmCP_EOP_DONE_EVENT_CNTL 0 0x20d5 4 0 1 GCR_CNTL 12 23 CACHE_POLICY 25 26 EOP_VOLATILE 27 27 EXECUTE 28 28 mmCP_EOP_DONE_DATA_CNTL 0 0x20d6 5 0 1 DST_SEL 16 17 ACTION_PIPE_ID 20 21 ACTION_ID 22 23 INT_SEL 24 26 DATA_SEL 29 31 mmCP_EOP_DONE_CNTX_ID 0 0x20d7 1 0 1 CNTX_ID 0 31 mmCP_DB_BASE_LO 0 0x20d8 1 0 1 DB_BASE_LO 2 31 mmCP_DB_BASE_HI 0 0x20d9 1 0 1 DB_BASE_HI 0 15 mmCP_DB_BUFSZ 0 0x20da 1 0 1 DB_BUFSZ 0 19 mmCP_DB_CMD_BUFSZ 0 0x20db 1 0 1 DB_CMD_REQSZ 0 19 mmCP_CE_DB_BASE_LO 0 0x20dc 1 0 1 DB_BASE_LO 2 31 mmCP_CE_DB_BASE_HI 0 0x20dd 1 0 1 DB_BASE_HI 0 15 mmCP_CE_DB_BUFSZ 0 0x20de 1 0 1 DB_BUFSZ 0 19 mmCP_CE_DB_CMD_BUFSZ 0 0x20df 1 0 1 DB_CMD_REQSZ 0 19 mmCP_PFP_COMPLETION_STATUS 0 0x20ec 1 0 1 STATUS 0 1 mmCP_CE_COMPLETION_STATUS 0 0x20ed 1 0 1 STATUS 0 1 mmCP_PRED_NOT_VISIBLE 0 0x20ee 1 0 1 NOT_VISIBLE 0 0 mmCP_PFP_METADATA_BASE_ADDR 0 0x20f0 1 0 1 ADDR_LO 0 31 mmCP_PFP_METADATA_BASE_ADDR_HI 0 0x20f1 1 0 1 ADDR_HI 0 15 mmCP_CE_METADATA_BASE_ADDR 0 0x20f2 1 0 1 ADDR_LO 0 31 mmCP_CE_METADATA_BASE_ADDR_HI 0 0x20f3 1 0 1 ADDR_HI 0 15 mmCP_DRAW_INDX_INDR_ADDR 0 0x20f4 1 0 1 ADDR_LO 0 31 mmCP_DRAW_INDX_INDR_ADDR_HI 0 0x20f5 1 0 1 ADDR_HI 0 15 mmCP_DISPATCH_INDR_ADDR 0 0x20f6 1 0 1 ADDR_LO 0 31 mmCP_DISPATCH_INDR_ADDR_HI 0 0x20f7 1 0 1 ADDR_HI 0 15 mmCP_INDEX_BASE_ADDR 0 0x20f8 1 0 1 ADDR_LO 0 31 mmCP_INDEX_BASE_ADDR_HI 0 0x20f9 1 0 1 ADDR_HI 0 15 mmCP_INDEX_TYPE 0 0x20fa 1 0 1 INDEX_TYPE 0 1 mmCP_GDS_BKUP_ADDR 0 0x20fb 1 0 1 ADDR_LO 0 31 mmCP_GDS_BKUP_ADDR_HI 0 0x20fc 1 0 1 ADDR_HI 0 15 mmCP_SAMPLE_STATUS 0 0x20fd 8 0 1 Z_PASS_ACITVE 0 0 STREAMOUT_ACTIVE 1 1 PIPELINE_ACTIVE 2 2 STIPPLE_ACTIVE 3 3 VGT_BUFFERS_ACTIVE 4 4 SCREEN_EXT_ACTIVE 5 5 DRAW_INDIRECT_ACTIVE 6 6 DISP_INDIRECT_ACTIVE 7 7 mmCP_ME_COHER_CNTL 0 0x20fe 13 0 1 DEST_BASE_0_ENA 0 0 DEST_BASE_1_ENA 1 1 CB0_DEST_BASE_ENA 6 6 CB1_DEST_BASE_ENA 7 7 CB2_DEST_BASE_ENA 8 8 CB3_DEST_BASE_ENA 9 9 CB4_DEST_BASE_ENA 10 10 CB5_DEST_BASE_ENA 11 11 CB6_DEST_BASE_ENA 12 12 CB7_DEST_BASE_ENA 13 13 DB_DEST_BASE_ENA 14 14 DEST_BASE_2_ENA 19 19 DEST_BASE_3_ENA 21 21 mmCP_ME_COHER_SIZE 0 0x20ff 1 0 1 COHER_SIZE_256B 0 31 mmCP_ME_COHER_SIZE_HI 0 0x2100 1 0 1 COHER_SIZE_HI_256B 0 7 mmCP_ME_COHER_BASE 0 0x2101 1 0 1 COHER_BASE_256B 0 31 mmCP_ME_COHER_BASE_HI 0 0x2102 1 0 1 COHER_BASE_HI_256B 0 7 mmCP_ME_COHER_STATUS 0 0x2103 2 0 1 MATCHING_GFX_CNTX 0 7 STATUS 31 31 mmRLC_GPM_PERF_COUNT_0 0 0x2140 8 0 1 FEATURE_SEL 0 3 SE_INDEX 4 7 SA_INDEX 8 11 WGP_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 mmRLC_GPM_PERF_COUNT_1 0 0x2141 8 0 1 FEATURE_SEL 0 3 SE_INDEX 4 7 SA_INDEX 8 11 WGP_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 mmGRBM_GFX_INDEX 0 0x2200 6 0 1 INSTANCE_INDEX 0 7 SA_INDEX 8 15 SE_INDEX 16 23 SA_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 mmVGT_ESGS_RING_SIZE_UMD 0 0x2240 1 0 1 MEM_SIZE 0 31 mmVGT_GSVS_RING_SIZE_UMD 0 0x2241 1 0 1 MEM_SIZE 0 31 mmVGT_PRIMITIVE_TYPE 0 0x2242 1 0 1 PRIM_TYPE 0 5 mmVGT_INDEX_TYPE 0 0x2243 2 0 1 INDEX_TYPE 0 1 DISABLE_INSTANCE_PACKING 14 14 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0 0x2244 1 0 1 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0 0x2245 1 0 1 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0 0x2246 1 0 1 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0 0x2247 1 0 1 SIZE 0 31 mmGE_MIN_VTX_INDX 0 0x2249 1 0 1 MIN_INDX 0 31 mmGE_INDX_OFFSET 0 0x224a 1 0 1 INDX_OFFSET 0 31 mmGE_MULTI_PRIM_IB_RESET_EN 0 0x224b 2 0 1 RESET_EN 0 0 MATCH_ALL_BITS 1 1 mmVGT_NUM_INDICES 0 0x224c 1 0 1 NUM_INDICES 0 31 mmVGT_NUM_INSTANCES 0 0x224d 1 0 1 NUM_INSTANCES 0 31 mmVGT_TF_RING_SIZE_UMD 0 0x224e 1 0 1 SIZE 0 15 mmVGT_HS_OFFCHIP_PARAM_UMD 0 0x224f 2 0 1 OFFCHIP_BUFFERING 0 9 OFFCHIP_GRANULARITY 10 11 mmVGT_TF_MEMORY_BASE_UMD 0 0x2250 1 0 1 BASE 0 31 mmGE_DMA_FIRST_INDEX 0 0x2251 1 0 1 FIRST_INDEX 0 31 mmWD_POS_BUF_BASE 0 0x2252 1 0 1 BASE 0 31 mmWD_POS_BUF_BASE_HI 0 0x2253 1 0 1 BASE_HI 0 7 mmWD_CNTL_SB_BUF_BASE 0 0x2254 1 0 1 BASE 0 31 mmWD_CNTL_SB_BUF_BASE_HI 0 0x2255 1 0 1 BASE_HI 0 7 mmWD_INDEX_BUF_BASE 0 0x2256 1 0 1 BASE 0 31 mmWD_INDEX_BUF_BASE_HI 0 0x2257 1 0 1 BASE_HI 0 7 mmIA_MULTI_VGT_PARAM_PIPED 0 0x2258 9 0 1 PRIMGROUP_SIZE 0 15 PARTIAL_VS_WAVE_ON 16 16 SWITCH_ON_EOP 17 17 PARTIAL_ES_WAVE_ON 18 18 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 EN_INST_OPT_BASIC 21 21 EN_INST_OPT_ADV 22 22 HW_USE_ONLY 23 23 mmGE_MAX_VTX_INDX 0 0x2259 1 0 1 MAX_INDX 0 31 mmVGT_INSTANCE_BASE_ID 0 0x225a 1 0 1 INSTANCE_BASE_ID 0 31 mmGE_CNTL 0 0x225b 4 0 1 PRIM_GRP_SIZE 0 8 VERT_GRP_SIZE 9 17 BREAK_WAVE_AT_EOI 18 18 PACKET_TO_ONE_PA 19 19 mmGE_USER_VGPR1 0 0x225c 1 0 1 DATA 0 31 mmGE_USER_VGPR2 0 0x225d 1 0 1 DATA 0 31 mmGE_USER_VGPR3 0 0x225e 1 0 1 DATA 0 31 mmGE_STEREO_CNTL 0 0x225f 3 0 1 RT_SLICE 0 2 VIEWPORT 3 6 EN_STEREO 8 8 mmGE_PC_ALLOC 0 0x2260 2 0 1 OVERSUB_EN 0 0 NUM_PC_LINES 1 10 mmVGT_TF_MEMORY_BASE_HI_UMD 0 0x2261 1 0 1 BASE_HI 0 7 mmGE_USER_VGPR_EN 0 0x2262 3 0 1 EN_USER_VGPR1 0 0 EN_USER_VGPR2 1 1 EN_USER_VGPR3 2 2 mmPA_SU_LINE_STIPPLE_VALUE 0 0x2280 1 0 1 LINE_STIPPLE_VALUE 0 23 mmPA_SC_LINE_STIPPLE_STATE 0 0x2281 2 0 1 CURRENT_PTR 0 3 CURRENT_COUNT 8 15 mmPA_SC_SCREEN_EXTENT_MIN_0 0 0x2284 2 0 1 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MAX_0 0 0x2285 2 0 1 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MIN_1 0 0x2286 2 0 1 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MAX_1 0 0x228b 2 0 1 X 0 15 Y 16 31 mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0 0x22a0 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_P3D_TRAP_SCREEN_H 0 0x22a1 1 0 1 X_COORD 0 13 mmPA_SC_P3D_TRAP_SCREEN_V 0 0x22a2 1 0 1 Y_COORD 0 13 mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0 0x22a3 1 0 1 COUNT 0 15 mmPA_SC_P3D_TRAP_SCREEN_COUNT 0 0x22a4 1 0 1 COUNT 0 15 mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0 0x22a8 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_HP3D_TRAP_SCREEN_H 0 0x22a9 1 0 1 X_COORD 0 13 mmPA_SC_HP3D_TRAP_SCREEN_V 0 0x22aa 1 0 1 Y_COORD 0 13 mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0 0x22ab 1 0 1 COUNT 0 15 mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0 0x22ac 1 0 1 COUNT 0 15 mmPA_SC_TRAP_SCREEN_HV_EN 0 0x22b0 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_TRAP_SCREEN_H 0 0x22b1 1 0 1 X_COORD 0 13 mmPA_SC_TRAP_SCREEN_V 0 0x22b2 1 0 1 Y_COORD 0 13 mmPA_SC_TRAP_SCREEN_OCCURRENCE 0 0x22b3 1 0 1 COUNT 0 15 mmPA_SC_TRAP_SCREEN_COUNT 0 0x22b4 1 0 1 COUNT 0 15 mmSQ_THREAD_TRACE_USERDATA_0 0 0x2340 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_1 0 0x2341 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_2 0 0x2342 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_3 0 0x2343 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_4 0 0x2344 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_5 0 0x2345 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_6 0 0x2346 1 0 1 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_7 0 0x2347 1 0 1 DATA 0 31 mmSQC_CACHES 0 0x2348 5 0 1 TARGET_INST 0 0 TARGET_DATA 1 1 INVALIDATE 2 2 COMPLETE 16 16 L2_WB_POLICY 17 18 mmTA_CS_BC_BASE_ADDR 0 0x2380 1 0 1 ADDRESS 0 31 mmTA_CS_BC_BASE_ADDR_HI 0 0x2381 1 0 1 ADDRESS 0 7 mmDB_OCCLUSION_COUNT0_LOW 0 0x23c0 1 0 1 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT0_HI 0 0x23c1 1 0 1 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT1_LOW 0 0x23c2 1 0 1 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT1_HI 0 0x23c3 1 0 1 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT2_LOW 0 0x23c4 1 0 1 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT2_HI 0 0x23c5 1 0 1 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT3_LOW 0 0x23c6 1 0 1 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT3_HI 0 0x23c7 1 0 1 COUNT_HI 0 30 mmDB_ZPASS_COUNT_LOW 0 0x23fe 1 0 1 COUNT_LOW 0 31 mmDB_ZPASS_COUNT_HI 0 0x23ff 1 0 1 COUNT_HI 0 30 mmGDS_RD_ADDR 0 0x2400 1 0 1 READ_ADDR 0 31 mmGDS_RD_DATA 0 0x2401 1 0 1 READ_DATA 0 31 mmGDS_RD_BURST_ADDR 0 0x2402 1 0 1 BURST_ADDR 0 31 mmGDS_RD_BURST_COUNT 0 0x2403 1 0 1 BURST_COUNT 0 31 mmGDS_RD_BURST_DATA 0 0x2404 1 0 1 BURST_DATA 0 31 mmGDS_WR_ADDR 0 0x2405 1 0 1 WRITE_ADDR 0 31 mmGDS_WR_DATA 0 0x2406 1 0 1 WRITE_DATA 0 31 mmGDS_WR_BURST_ADDR 0 0x2407 1 0 1 WRITE_ADDR 0 31 mmGDS_WR_BURST_DATA 0 0x2408 1 0 1 WRITE_DATA 0 31 mmGDS_WRITE_COMPLETE 0 0x2409 1 0 1 WRITE_COMPLETE 0 31 mmGDS_ATOM_CNTL 0 0x240a 4 0 1 AINC 0 5 UNUSED1 6 7 DMODE 8 9 UNUSED2 10 31 mmGDS_ATOM_COMPLETE 0 0x240b 2 0 1 COMPLETE 0 0 UNUSED 1 31 mmGDS_ATOM_BASE 0 0x240c 2 0 1 BASE 0 15 UNUSED 16 31 mmGDS_ATOM_SIZE 0 0x240d 2 0 1 SIZE 0 15 UNUSED 16 31 mmGDS_ATOM_OFFSET0 0 0x240e 2 0 1 OFFSET0 0 7 UNUSED 8 31 mmGDS_ATOM_OFFSET1 0 0x240f 2 0 1 OFFSET1 0 7 UNUSED 8 31 mmGDS_ATOM_DST 0 0x2410 1 0 1 DST 0 31 mmGDS_ATOM_OP 0 0x2411 2 0 1 OP 0 7 UNUSED 8 31 mmGDS_ATOM_SRC0 0 0x2412 1 0 1 DATA 0 31 mmGDS_ATOM_SRC0_U 0 0x2413 1 0 1 DATA 0 31 mmGDS_ATOM_SRC1 0 0x2414 1 0 1 DATA 0 31 mmGDS_ATOM_SRC1_U 0 0x2415 1 0 1 DATA 0 31 mmGDS_ATOM_READ0 0 0x2416 1 0 1 DATA 0 31 mmGDS_ATOM_READ0_U 0 0x2417 1 0 1 DATA 0 31 mmGDS_ATOM_READ1 0 0x2418 1 0 1 DATA 0 31 mmGDS_ATOM_READ1_U 0 0x2419 1 0 1 DATA 0 31 mmGDS_GWS_RESOURCE_CNTL 0 0x241a 2 0 1 INDEX 0 5 UNUSED 6 31 mmGDS_GWS_RESOURCE 0 0x241b 11 0 1 FLAG 0 0 COUNTER 1 12 TYPE 13 13 DED 14 14 RELEASE_ALL 15 15 HEAD_QUEUE 16 26 HEAD_VALID 27 27 HEAD_FLAG 28 28 HALTED 29 29 HEAD_QUEUE1 30 30 UNUSED1 31 31 mmGDS_GWS_RESOURCE_CNT 0 0x241c 2 0 1 RESOURCE_CNT 0 15 UNUSED 16 31 mmGDS_OA_CNTL 0 0x241d 2 0 1 INDEX 0 3 UNUSED 4 31 mmGDS_OA_COUNTER 0 0x241e 1 0 1 SPACE_AVAILABLE 0 31 mmGDS_OA_ADDRESS 0 0x241f 6 0 1 DS_ADDRESS 0 15 CRAWLER_TYPE 16 19 CRAWLER 20 23 UNUSED 24 29 NO_ALLOC 30 30 ENABLE 31 31 mmGDS_OA_INCDEC 0 0x2420 2 0 1 VALUE 0 30 INCDEC 31 31 mmGDS_OA_RING_SIZE 0 0x2421 1 0 1 RING_SIZE 0 31 mmSPI_CONFIG_CNTL_REMAP 0 0x2440 1 0 1 RESERVED 0 31 mmSPI_CONFIG_CNTL_1_REMAP 0 0x2441 1 0 1 RESERVED 0 31 mmSPI_CONFIG_CNTL_2_REMAP 0 0x2442 1 0 1 RESERVED 0 31 mmSPI_WAVE_LIMIT_CNTL_REMAP 0 0x2443 1 0 1 RESERVED 0 31 mmCP_MES_PRGRM_CNTR_START 0 0x2800 1 0 1 IP_START 0 19 mmCP_MES_INTR_ROUTINE_START 0 0x2801 1 0 1 IR_START 0 31 mmCP_MES_MTVEC_LO 0 0x2801 1 0 1 ADDR_LO 0 31 mmCP_MES_MTVEC_HI 0 0x2802 1 0 1 ADDR_LO 0 31 mmCP_MES_CNTL 0 0x2807 11 0 1 MES_INVALIDATE_ICACHE 4 4 MES_PIPE0_RESET 16 16 MES_PIPE1_RESET 17 17 MES_PIPE2_RESET 18 18 MES_PIPE3_RESET 19 19 MES_PIPE0_ACTIVE 26 26 MES_PIPE1_ACTIVE 27 27 MES_PIPE2_ACTIVE 28 28 MES_PIPE3_ACTIVE 29 29 MES_HALT 30 30 MES_STEP 31 31 mmCP_MES_PIPE_PRIORITY_CNTS 0 0x2808 4 0 1 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_MES_PIPE0_PRIORITY 0 0x2809 1 0 1 PRIORITY 0 1 mmCP_MES_PIPE1_PRIORITY 0 0x280a 1 0 1 PRIORITY 0 1 mmCP_MES_PIPE2_PRIORITY 0 0x280b 1 0 1 PRIORITY 0 1 mmCP_MES_PIPE3_PRIORITY 0 0x280c 1 0 1 PRIORITY 0 1 mmCP_MES_HEADER_DUMP 0 0x280d 1 0 1 HEADER_DUMP 0 31 mmCP_MES_MIE_LO 0 0x280e 1 0 1 MES_INT 0 31 mmCP_MES_MIE_HI 0 0x280f 1 0 1 MES_INT 0 31 mmCP_MES_INTERRUPT 0 0x2810 1 0 1 MES_INT 0 31 mmCP_MES_SCRATCH_INDEX 0 0x2811 2 0 1 SCRATCH_INDEX 0 8 SCRATCH_INDEX_64BIT_MODE 31 31 mmCP_MES_SCRATCH_DATA 0 0x2812 1 0 1 SCRATCH_DATA 0 31 mmCP_MES_INSTR_PNTR 0 0x2813 1 0 1 INSTR_PNTR 0 19 mmCP_MES_MSCRATCH_HI 0 0x2814 1 0 1 DATA 0 31 mmCP_MES_MSCRATCH_LO 0 0x2815 1 0 1 DATA 0 31 mmCP_MES_MSTATUS_LO 0 0x2816 1 0 1 STATUS_LO 0 31 mmCP_MES_MSTATUS_HI 0 0x2817 1 0 1 STATUS_HI 0 31 mmCP_MES_MEPC_LO 0 0x2818 1 0 1 MEPC_LO 0 31 mmCP_MES_MEPC_HI 0 0x2819 1 0 1 MEPC_HI 0 31 mmCP_MES_MCAUSE_LO 0 0x281a 1 0 1 CAUSE_LO 0 31 mmCP_MES_MCAUSE_HI 0 0x281b 1 0 1 CAUSE_HI 0 31 mmCP_MES_MBADADDR_LO 0 0x281c 1 0 1 ADDR_LO 0 31 mmCP_MES_MBADADDR_HI 0 0x281d 1 0 1 ADDR_HI 0 31 mmCP_MES_MIP_LO 0 0x281e 1 0 1 MIP_LO 0 31 mmCP_MES_MIP_HI 0 0x281f 1 0 1 MIP_HI 0 31 mmCP_MES_IC_OP_CNTL 0 0x2820 3 0 1 INVALIDATE_CACHE 0 0 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 mmCP_MES_MCYCLE_LO 0 0x2826 1 0 1 CYCLE_LO 0 31 mmCP_MES_MCYCLE_HI 0 0x2827 1 0 1 CYCLE_HI 0 31 mmCP_MES_MTIME_LO 0 0x2828 1 0 1 TIME_LO 0 31 mmCP_MES_MTIME_HI 0 0x2829 1 0 1 TIME_HI 0 31 mmCP_MES_MINSTRET_LO 0 0x282a 1 0 1 INSTRET_LO 0 31 mmCP_MES_MINSTRET_HI 0 0x282b 1 0 1 INSTRET_HI 0 31 mmCP_MES_MISA_LO 0 0x282c 1 0 1 MISA_LO 0 31 mmCP_MES_MISA_HI 0 0x282d 1 0 1 MISA_HI 0 31 mmCP_MES_MVENDORID_LO 0 0x282e 1 0 1 MVENDORID_LO 0 31 mmCP_MES_MVENDORID_HI 0 0x282f 1 0 1 MVENDORID_HI 0 31 mmCP_MES_MARCHID_LO 0 0x2830 1 0 1 MARCHID_LO 0 31 mmCP_MES_MARCHID_HI 0 0x2831 1 0 1 MARCHID_HI 0 31 mmCP_MES_MIMPID_LO 0 0x2832 1 0 1 MIMPID_LO 0 31 mmCP_MES_MIMPID_HI 0 0x2833 1 0 1 MIMPID_HI 0 31 mmCP_MES_MHARTID_LO 0 0x2834 1 0 1 MHARTID_LO 0 31 mmCP_MES_MHARTID_HI 0 0x2835 1 0 1 MHARTID_HI 0 31 mmCP_MES_DC_BASE_CNTL 0 0x2836 2 0 1 VMID 0 3 CACHE_POLICY 24 25 mmCP_MES_DC_OP_CNTL 0 0x2837 6 0 1 INVALIDATE_DCACHE 0 0 INVALIDATE_DCACHE_COMPLETE 1 1 BYPASS_ALL 2 2 BYPASS_UNCACHED 3 3 PRIME_DCACHE 4 4 DCACHE_PRIMED 5 5 mmCP_MES_MTIMECMP_LO 0 0x2838 1 0 1 TIME_LO 0 31 mmCP_MES_MTIMECMP_HI 0 0x2839 1 0 1 TIME_HI 0 31 mmCP_MES_PROCESS_QUANTUM_PIPE0 0 0x283a 4 0 1 QUANTUM_DURATION 0 27 TIMER_EXPIRED 28 28 QUANTUM_SCALE 29 30 QUANTUM_EN 31 31 mmCP_MES_PROCESS_QUANTUM_PIPE1 0 0x283b 4 0 1 QUANTUM_DURATION 0 27 TIMER_EXPIRED 28 28 QUANTUM_SCALE 29 30 QUANTUM_EN 31 31 mmCP_MES_DOORBELL_CONTROL1 0 0x283c 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_DOORBELL_CONTROL2 0 0x283d 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_DOORBELL_CONTROL3 0 0x283e 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_DOORBELL_CONTROL4 0 0x283f 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_DOORBELL_CONTROL5 0 0x2840 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_DOORBELL_CONTROL6 0 0x2841 3 0 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_MES_GP0_LO 0 0x2843 2 0 1 PG_VIRT_HALTED 0 0 DATA 1 31 mmCP_MES_GP0_HI 0 0x2844 1 0 1 M_RET_ADDR 0 31 mmCP_MES_GP1_LO 0 0x2845 1 0 1 RD_WR_SELECT_LO 0 31 mmCP_MES_GP1_HI 0 0x2846 1 0 1 RD_WR_SELECT_HI 0 31 mmCP_MES_GP2_LO 0 0x2847 1 0 1 STACK_PNTR_LO 0 31 mmCP_MES_GP2_HI 0 0x2848 1 0 1 STACK_PNTR_HI 0 31 mmCP_MES_GP3_LO 0 0x2849 1 0 1 DATA 0 31 mmCP_MES_GP3_HI 0 0x284a 1 0 1 DATA 0 31 mmCP_MES_GP4_LO 0 0x284b 1 0 1 DATA 0 31 mmCP_MES_GP4_HI 0 0x284c 1 0 1 DATA 0 31 mmCP_MES_GP5_LO 0 0x284d 2 0 1 PG_VIRT_HALTED 0 0 DATA 1 31 mmCP_MES_GP5_HI 0 0x284e 1 0 1 M_RET_ADDR 0 31 mmCP_MES_GP6_LO 0 0x284f 1 0 1 RD_WR_SELECT_LO 0 31 mmCP_MES_GP6_HI 0 0x2850 1 0 1 RD_WR_SELECT_HI 0 31 mmCP_MES_GP7_LO 0 0x2851 1 0 1 STACK_PNTR_LO 0 31 mmCP_MES_GP7_HI 0 0x2852 1 0 1 STACK_PNTR_HI 0 31 mmCP_MES_GP8_LO 0 0x2853 1 0 1 DATA 0 31 mmCP_MES_GP8_HI 0 0x2854 1 0 1 DATA 0 31 mmCP_MES_GP9_LO 0 0x2855 1 0 1 DATA 0 31 mmCP_MES_GP9_HI 0 0x2856 1 0 1 DATA 0 31 mmCP_MES_DM_INDEX_ADDR 0 0x2880 1 0 1 ADDR 0 31 mmCP_MES_DM_INDEX_DATA 0 0x2881 1 0 1 DATA 0 31 mmCP_MES_PERFCOUNT_CNTL 0 0x2899 1 0 1 EVENT_SEL 0 4 mmCP_MES_PENDING_INTERRUPT 0 0x289a 1 0 1 PENDING_INTERRUPT 0 31 mmGUS_IO_RD_COMBINE_FLUSH 0 0x2c00 6 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 GROUP4_TIMER 16 19 GROUP5_TIMER 20 23 mmGUS_IO_WR_COMBINE_FLUSH 0 0x2c01 6 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 GROUP4_TIMER 16 19 GROUP5_TIMER 20 23 mmGUS_IO_RD_PRI_AGE_RATE 0 0x2c02 6 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP4_AGING_RATE 12 14 GROUP5_AGING_RATE 15 17 mmGUS_IO_WR_PRI_AGE_RATE 0 0x2c03 6 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP4_AGING_RATE 12 14 GROUP5_AGING_RATE 15 17 mmGUS_IO_RD_PRI_AGE_COEFF 0 0x2c04 6 0 1 GROUP0_AGE_COEFFICIENT 0 2 GROUP1_AGE_COEFFICIENT 3 5 GROUP2_AGE_COEFFICIENT 6 8 GROUP3_AGE_COEFFICIENT 9 11 GROUP4_AGE_COEFFICIENT 12 14 GROUP5_AGE_COEFFICIENT 15 17 mmGUS_IO_WR_PRI_AGE_COEFF 0 0x2c05 6 0 1 GROUP0_AGE_COEFFICIENT 0 2 GROUP1_AGE_COEFFICIENT 3 5 GROUP2_AGE_COEFFICIENT 6 8 GROUP3_AGE_COEFFICIENT 9 11 GROUP4_AGE_COEFFICIENT 12 14 GROUP5_AGE_COEFFICIENT 15 17 mmGUS_IO_RD_PRI_QUEUING 0 0x2c06 6 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 GROUP4_QUEUING_COEFFICIENT 12 14 GROUP5_QUEUING_COEFFICIENT 15 17 mmGUS_IO_WR_PRI_QUEUING 0 0x2c07 6 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 GROUP4_QUEUING_COEFFICIENT 12 14 GROUP5_QUEUING_COEFFICIENT 15 17 mmGUS_IO_RD_PRI_FIXED 0 0x2c08 6 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 GROUP4_FIXED_COEFFICIENT 12 14 GROUP5_FIXED_COEFFICIENT 15 17 mmGUS_IO_WR_PRI_FIXED 0 0x2c09 6 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 GROUP4_FIXED_COEFFICIENT 12 14 GROUP5_FIXED_COEFFICIENT 15 17 mmGUS_IO_RD_PRI_URGENCY_COEFF 0 0x2c0a 6 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP4_URGENCY_COEFFICIENT 12 14 GROUP5_URGENCY_COEFFICIENT 15 17 mmGUS_IO_WR_PRI_URGENCY_COEFF 0 0x2c0b 6 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP4_URGENCY_COEFFICIENT 12 14 GROUP5_URGENCY_COEFFICIENT 15 17 mmGUS_IO_RD_PRI_URGENCY_MODE 0 0x2c0c 6 0 1 GROUP0_URGENCY_MODE 0 0 GROUP1_URGENCY_MODE 1 1 GROUP2_URGENCY_MODE 2 2 GROUP3_URGENCY_MODE 3 3 GROUP4_URGENCY_MODE 4 4 GROUP5_URGENCY_MODE 5 5 mmGUS_IO_WR_PRI_URGENCY_MODE 0 0x2c0d 6 0 1 GROUP0_URGENCY_MODE 0 0 GROUP1_URGENCY_MODE 1 1 GROUP2_URGENCY_MODE 2 2 GROUP3_URGENCY_MODE 3 3 GROUP4_URGENCY_MODE 4 4 GROUP5_URGENCY_MODE 5 5 mmGUS_IO_RD_PRI_QUANT_PRI1 0 0x2c0e 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_RD_PRI_QUANT_PRI2 0 0x2c0f 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_RD_PRI_QUANT_PRI3 0 0x2c10 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_RD_PRI_QUANT_PRI4 0 0x2c11 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_WR_PRI_QUANT_PRI1 0 0x2c12 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_WR_PRI_QUANT_PRI2 0 0x2c13 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_WR_PRI_QUANT_PRI3 0 0x2c14 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_WR_PRI_QUANT_PRI4 0 0x2c15 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_IO_RD_PRI_QUANT1_PRI1 0 0x2c16 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_RD_PRI_QUANT1_PRI2 0 0x2c17 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_RD_PRI_QUANT1_PRI3 0 0x2c18 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_RD_PRI_QUANT1_PRI4 0 0x2c19 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_WR_PRI_QUANT1_PRI1 0 0x2c1a 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_WR_PRI_QUANT1_PRI2 0 0x2c1b 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_WR_PRI_QUANT1_PRI3 0 0x2c1c 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_WR_PRI_QUANT1_PRI4 0 0x2c1d 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_DRAM_COMBINE_FLUSH 0 0x2c1e 6 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 GROUP4_TIMER 16 19 GROUP5_TIMER 20 23 mmGUS_DRAM_COMBINE_RD_WR_EN 0 0x2c1f 6 0 1 GROUP0_TIMER 0 1 GROUP1_TIMER 2 3 GROUP2_TIMER 4 5 GROUP3_TIMER 6 7 GROUP4_TIMER 8 9 GROUP5_TIMER 10 11 mmGUS_DRAM_PRI_AGE_RATE 0 0x2c20 6 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP4_AGING_RATE 12 14 GROUP5_AGING_RATE 15 17 mmGUS_DRAM_PRI_AGE_COEFF 0 0x2c21 6 0 1 GROUP0_AGE_COEFFICIENT 0 2 GROUP1_AGE_COEFFICIENT 3 5 GROUP2_AGE_COEFFICIENT 6 8 GROUP3_AGE_COEFFICIENT 9 11 GROUP4_AGE_COEFFICIENT 12 14 GROUP5_AGE_COEFFICIENT 15 17 mmGUS_DRAM_PRI_QUEUING 0 0x2c22 6 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 GROUP4_QUEUING_COEFFICIENT 12 14 GROUP5_QUEUING_COEFFICIENT 15 17 mmGUS_DRAM_PRI_FIXED 0 0x2c23 6 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 GROUP4_FIXED_COEFFICIENT 12 14 GROUP5_FIXED_COEFFICIENT 15 17 mmGUS_DRAM_PRI_URGENCY_COEFF 0 0x2c24 6 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP4_URGENCY_COEFFICIENT 12 14 GROUP5_URGENCY_COEFFICIENT 15 17 mmGUS_DRAM_PRI_URGENCY_MODE 0 0x2c25 6 0 1 GROUP0_URGENCY_MODE 0 0 GROUP1_URGENCY_MODE 1 1 GROUP2_URGENCY_MODE 2 2 GROUP3_URGENCY_MODE 3 3 GROUP4_URGENCY_MODE 4 4 GROUP5_URGENCY_MODE 5 5 mmGUS_DRAM_PRI_QUANT_PRI1 0 0x2c26 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_DRAM_PRI_QUANT_PRI2 0 0x2c27 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_DRAM_PRI_QUANT_PRI3 0 0x2c28 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_DRAM_PRI_QUANT_PRI4 0 0x2c29 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_DRAM_PRI_QUANT_PRI5 0 0x2c2a 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmGUS_DRAM_PRI_QUANT1_PRI1 0 0x2c2b 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_DRAM_PRI_QUANT1_PRI2 0 0x2c2c 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_DRAM_PRI_QUANT1_PRI3 0 0x2c2d 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_DRAM_PRI_QUANT1_PRI4 0 0x2c2e 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_DRAM_PRI_QUANT1_PRI5 0 0x2c2f 2 0 1 GROUP4_THRESHOLD 0 7 GROUP5_THRESHOLD 8 15 mmGUS_IO_GROUP_BURST 0 0x2c30 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmGUS_DRAM_GROUP_BURST 0 0x2c31 2 0 1 DRAM_LIMIT_LO 0 7 DRAM_LIMIT_HI 8 15 mmGUS_SDP_ARB_FINAL 0 0x2c32 6 0 1 HI_DRAM_BURST_LIMIT 0 4 DRAM_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 ERREVENT_ON_ERROR 17 17 HALTREQ_ON_ERROR 18 18 mmGUS_SDP_QOS_VC_PRIORITY 0 0x2c33 4 0 1 VC2_IORD 0 3 VC3_IOWR 4 7 VC4_DRAM 8 11 VC4_HI_DRAM 12 15 mmGUS_SDP_CREDITS 0 0x2c34 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmGUS_SDP_TAG_RESERVE0 0 0x2c35 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmGUS_SDP_TAG_RESERVE1 0 0x2c36 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmGUS_SDP_VCC_RESERVE0 0 0x2c37 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmGUS_SDP_VCC_RESERVE1 0 0x2c38 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmGUS_SDP_VCD_RESERVE0 0 0x2c39 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmGUS_SDP_VCD_RESERVE1 0 0x2c3a 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmGUS_SDP_REQ_CNTL 0 0x2c3b 5 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 INNER_DOMAIN_MODE 4 4 mmGUS_MISC 0 0x2c3c 9 0 1 RELATIVE_PRI_IN_DRAM_ARB 0 0 RELATIVE_PRI_IN_IO_RD_ARB 1 1 RELATIVE_PRI_IN_IO_WR_ARB 2 2 EARLY_SDP_ORIGDATA 3 3 LINKMGR_DYNAMIC_MODE 4 5 LINKMGR_HALT_THRESHOLD 6 7 LINKMGR_RECONNECT_DELAY 8 9 LINKMGR_IDLE_THRESHOLD 10 14 SEND0_IOWR_ONLY 15 15 mmGUS_LATENCY_SAMPLING 0 0x2c3d 14 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_IO 2 2 SAMPLER1_IO 3 3 SAMPLER0_READ 4 4 SAMPLER1_READ 5 5 SAMPLER0_WRITE 6 6 SAMPLER1_WRITE 7 7 SAMPLER0_ATOMIC_RET 8 8 SAMPLER1_ATOMIC_RET 9 9 SAMPLER0_ATOMIC_NORET 10 10 SAMPLER1_ATOMIC_NORET 11 11 SAMPLER0_VC 12 19 SAMPLER1_VC 20 27 mmGUS_ERR_STATUS 0 0x2c3e 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmGUS_MISC2 0 0x2c3f 14 0 1 IO_RDWR_PRIORITY_ENABLE 0 0 CH_L1_RO_MASK 1 1 SA0_L1_RO_MASK 2 2 SA1_L1_RO_MASK 3 3 SA2_L1_RO_MASK 4 4 SA3_L1_RO_MASK 5 5 CH_L1_PERF_MASK 6 6 SA0_L1_PERF_MASK 7 7 SA1_L1_PERF_MASK 8 8 SA2_L1_PERF_MASK 9 9 SA3_L1_PERF_MASK 10 10 FP_ATOMICS_ENABLE 11 11 L1_RET_CLKEN 12 12 FGCLKEN_HIGH 13 13 mmGUS_SDP_ENABLE 0 0x2c45 1 0 1 ENABLE 0 0 mmGUS_L1_CH0_CMD_IN 0 0x2c46 1 0 1 COUNT 0 31 mmGUS_L1_CH0_CMD_OUT 0 0x2c47 1 0 1 COUNT 0 31 mmGUS_L1_CH0_DATA_IN 0 0x2c48 1 0 1 COUNT 0 31 mmGUS_L1_CH0_DATA_OUT 0 0x2c49 1 0 1 COUNT 0 31 mmGUS_L1_CH0_DATA_U_IN 0 0x2c4a 1 0 1 COUNT 0 31 mmGUS_L1_CH0_DATA_U_OUT 0 0x2c4b 1 0 1 COUNT 0 31 mmGUS_L1_CH1_CMD_IN 0 0x2c4c 1 0 1 COUNT 0 31 mmGUS_L1_CH1_CMD_OUT 0 0x2c4d 1 0 1 COUNT 0 31 mmGUS_L1_CH1_DATA_IN 0 0x2c4e 1 0 1 COUNT 0 31 mmGUS_L1_CH1_DATA_OUT 0 0x2c4f 1 0 1 COUNT 0 31 mmGUS_L1_CH1_DATA_U_IN 0 0x2c50 1 0 1 COUNT 0 31 mmGUS_L1_CH1_DATA_U_OUT 0 0x2c51 1 0 1 COUNT 0 31 mmGUS_L1_SA0_CMD_IN 0 0x2c52 1 0 1 COUNT 0 31 mmGUS_L1_SA0_CMD_OUT 0 0x2c53 1 0 1 COUNT 0 31 mmGUS_L1_SA0_DATA_IN 0 0x2c54 1 0 1 COUNT 0 31 mmGUS_L1_SA0_DATA_OUT 0 0x2c55 1 0 1 COUNT 0 31 mmGUS_L1_SA0_DATA_U_IN 0 0x2c56 1 0 1 COUNT 0 31 mmGUS_L1_SA0_DATA_U_OUT 0 0x2c57 1 0 1 COUNT 0 31 mmGUS_L1_SA1_CMD_IN 0 0x2c58 1 0 1 COUNT 0 31 mmGUS_L1_SA1_CMD_OUT 0 0x2c59 1 0 1 COUNT 0 31 mmGUS_L1_SA1_DATA_IN 0 0x2c5a 1 0 1 COUNT 0 31 mmGUS_L1_SA1_DATA_OUT 0 0x2c5b 1 0 1 COUNT 0 31 mmGUS_L1_SA1_DATA_U_IN 0 0x2c5c 1 0 1 COUNT 0 31 mmGUS_L1_SA1_DATA_U_OUT 0 0x2c5d 1 0 1 COUNT 0 31 mmGUS_L1_SA2_CMD_IN 0 0x2c5e 1 0 1 COUNT 0 31 mmGUS_L1_SA2_CMD_OUT 0 0x2c5f 1 0 1 COUNT 0 31 mmGUS_L1_SA2_DATA_IN 0 0x2c60 1 0 1 COUNT 0 31 mmGUS_L1_SA2_DATA_OUT 0 0x2c61 1 0 1 COUNT 0 31 mmGUS_L1_SA2_DATA_U_IN 0 0x2c62 1 0 1 COUNT 0 31 mmGUS_L1_SA2_DATA_U_OUT 0 0x2c63 1 0 1 COUNT 0 31 mmGUS_L1_SA3_CMD_IN 0 0x2c64 1 0 1 COUNT 0 31 mmGUS_L1_SA3_CMD_OUT 0 0x2c65 1 0 1 COUNT 0 31 mmGUS_L1_SA3_DATA_IN 0 0x2c66 1 0 1 COUNT 0 31 mmGUS_L1_SA3_DATA_OUT 0 0x2c67 1 0 1 COUNT 0 31 mmGUS_L1_SA3_DATA_U_IN 0 0x2c68 1 0 1 COUNT 0 31 mmGUS_L1_SA3_DATA_U_OUT 0 0x2c69 1 0 1 COUNT 0 31 mmGUS_MISC3 0 0x2c6a 2 0 1 FP_ATOMICS_LOG 0 0 CLEAR_LOG 1 1 mmGUS_WRRSP_FIFO_CNTL 0 0x2c6b 1 0 1 THRESHOLD 0 5 mmGL1_DRAM_BURST_MASK 0 0x2d02 1 0 1 DRAM_BURST_ADDR_MASK 0 7 mmGL1_ARB_STATUS 0 0x2d03 2 0 1 REQ_ARB_BUSY 0 0 RET_ARB_BUSY 1 1 mmGL1_PIPE_STEER 0 0x2d10 4 0 1 PIPE0 0 1 PIPE1 2 3 PIPE2 4 5 PIPE3 6 7 mmGL1C_STATUS 0 0x2d41 20 0 1 INPUT_BUFFER_VC0_FIFO_FULL 0 0 OUTPUT_FIFOS_BUSY 1 1 SRC_DATA_FIFO_VC0_FULL 2 2 GL2_REQ_VC0_STALL 3 3 GL2_DATA_VC0_STALL 4 4 GL2_REQ_VC1_STALL 5 5 GL2_DATA_VC1_STALL 6 6 INPUT_BUFFER_VC0_BUSY 7 7 SRC_DATA_FIFO_VC0_BUSY 8 8 GL2_RH_BUSY 9 9 NUM_REQ_PENDING_FROM_L2 10 19 LATENCY_FIFO_FULL_STALL 20 20 TAG_STALL 21 21 TAG_BUSY 22 22 TAG_ACK_STALL 23 23 TAG_GCR_INV_STALL 24 24 TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL 25 25 TAG_EVICT 26 26 TAG_REQUEST_STATE_OPERATION 27 30 TRACKER_LAST_SET_MATCHES_CURRENT_SET 31 31 mmGL1C_UTCL0_CNTL2 0 0x2d43 13 0 1 SPARE 0 7 COMP_SYNC_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 ANY_LINE_VALID 10 10 GPUVM_INV_MODE 12 12 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 FORCE_FRAG_2M_TO_64K 26 26 PERM_MODE_OVRD 27 27 LINE_INVALIDATE_OPT 28 28 GPUVM_16K_DEFAULT 29 29 FGCG_DISABLE 30 30 BIG_PAGE_DISABLE 31 31 mmGL1C_UTCL0_STATUS 0 0x2d44 3 0 1 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 mmGL1C_UTCL0_RETRY 0 0x2d45 2 0 1 INCR 0 7 COUNT 8 11 mmCH_ARB_CTRL 0 0x2d80 4 0 1 NUM_MEM_PIPES 0 1 UC_IO_WR_PATH 2 2 FGCG_DISABLE 3 3 CHICKEN_BITS 4 11 mmCH_DRAM_BURST_MASK 0 0x2d82 1 0 1 DRAM_BURST_ADDR_MASK 0 7 mmCH_ARB_STATUS 0 0x2d83 2 0 1 REQ_ARB_BUSY 0 0 RET_ARB_BUSY 1 1 mmCH_DRAM_BURST_CTRL 0 0x2d84 7 0 1 MAX_DRAM_BURST 0 2 BURST_DISABLE 3 3 GATHER_64B_MEMORY_BURST_DISABLE 4 4 GATHER_64B_IO_BURST_DISABLE 5 5 GATHER_32B_MEMORY_BURST_DISABLE 6 6 GATHER_32B_IO_BURST_DISABLE 7 7 WRITE_BURSTABLE_STALL_DISABLE 8 8 mmCHA_CHC_CREDITS 0 0x2d88 2 0 1 CHC_REQ_CREDITS 0 7 CHCG_REQ_CREDITS 8 15 mmCHA_CLIENT_FREE_DELAY 0 0x2d89 10 0 1 CLIENT_TYPE_0_FREE_DELAY 0 2 CLIENT_TYPE_1_FREE_DELAY 3 5 CLIENT_TYPE_2_FREE_DELAY 6 8 CLIENT_TYPE_3_FREE_DELAY 9 11 CLIENT_TYPE_4_FREE_DELAY 12 14 CLIENT_TYPE_5_FREE_DELAY 15 17 CLIENT_TYPE_6_FREE_DELAY 18 20 CLIENT_TYPE_7_FREE_DELAY 21 23 CLIENT_TYPE_8_FREE_DELAY 24 26 CLIENT_TYPE_9_FREE_DELAY 27 29 mmCH_PIPE_STEER 0 0x2d90 4 0 1 PIPE0 0 1 PIPE1 2 3 PIPE2 4 5 PIPE3 6 7 mmCH_VC5_ENABLE 0 0x2d94 1 0 1 UTCL2_VC5_ENABLE 1 1 mmCHC_CTRL 0 0x2dc0 5 0 1 BUFFER_DEPTH_MAX 0 3 GL2_REQ_CREDITS 4 10 GL2_DATA_CREDITS 11 17 TO_L1_REPEATER_FGCG_DISABLE 18 18 TO_L2_REPEATER_FGCG_DISABLE 19 19 mmCHC_STATUS 0 0x2dc1 15 0 1 INPUT_BUFFER_VC0_FIFO_FULL 0 0 OUTPUT_FIFOS_BUSY 1 1 SRC_DATA_FIFO_VC0_FULL 2 2 GL2_REQ_VC0_STALL 3 3 GL2_DATA_VC0_STALL 4 4 GL2_REQ_VC1_STALL 5 5 GL2_DATA_VC1_STALL 6 6 INPUT_BUFFER_VC0_BUSY 7 7 SRC_DATA_FIFO_VC0_BUSY 8 8 GL2_RH_BUSY 9 9 NUM_REQ_PENDING_FROM_L2 10 19 VIRTUAL_FIFO_FULL_STALL 20 20 REQUEST_TRACKER_BUFFER_STALL 21 21 REQUEST_TRACKER_BUSY 22 22 BUFFER_FULL 23 23 mmCHCG_CTRL 0 0x2dc2 6 0 1 BUFFER_DEPTH_MAX 0 3 VC0_BUFFER_DEPTH_MAX 4 7 GL2_REQ_CREDITS 8 14 GL2_DATA_CREDITS 15 21 TO_L1_REPEATER_FGCG_DISABLE 22 22 TO_L2_REPEATER_FGCG_DISABLE 23 23 mmCHCG_STATUS 0 0x2dc3 19 0 1 INPUT_BUFFER_VC0_FIFO_FULL 0 0 OUTPUT_FIFOS_BUSY 1 1 SRC_DATA_FIFO_VC0_FULL 2 2 GL2_REQ_VC0_STALL 3 3 GL2_DATA_VC0_STALL 4 4 GL2_REQ_VC1_STALL 5 5 GL2_DATA_VC1_STALL 6 6 INPUT_BUFFER_VC0_BUSY 7 7 SRC_DATA_FIFO_VC0_BUSY 8 8 GL2_RH_BUSY 9 9 NUM_REQ_PENDING_FROM_L2 10 19 VIRTUAL_FIFO_FULL_STALL 20 20 REQUEST_TRACKER_BUFFER_STALL 21 21 REQUEST_TRACKER_BUSY 22 22 BUFFER_FULL 23 23 INPUT_BUFFER_VC1_BUSY 24 24 SRC_DATA_FIFO_VC1_BUSY 25 25 INPUT_BUFFER_VC1_FIFO_FULL 26 26 SRC_DATA_FIFO_VC1_FULL 27 27 mmGL2C_CTRL 0 0x2e00 12 0 1 CACHE_SIZE 0 1 RATE 2 3 WRITEBACK_MARGIN 4 7 METADATA_LATENCY_FIFO_SIZE 8 11 SRC_FIFO_SIZE 12 15 LATENCY_FIFO_SIZE 16 19 METADATA_TO_HI_PRIORITY 20 20 FORCE_HIT_QUEUE_POP 22 23 MDC_SIZE 24 25 METADATA_TO_HIT_QUEUE 26 26 IGNORE_FULLY_WRITTEN 27 27 MDC_SIDEBAND_FIFO_SIZE 28 31 mmGL2C_CTRL2 0 0x2e01 22 0 1 PROBE_FIFO_SIZE 0 3 ADDR_MATCH_DISABLE 4 4 FILL_SIZE_32 5 5 RB_TO_HI_PRIORITY 6 6 HIT_UNDER_MISS_DISABLE 7 7 RO_DISABLE 8 8 FORCE_MDC_INV 9 9 GCR_ARB_CTRL 10 12 GCR_ALL_SET 13 13 MDC_PF_BLOCK 14 15 MDC_PF_MAX_SIZE 16 16 FILL_SIZE_64 17 17 USE_EA_EARLYWRRET_ON_WRITEBACK 18 18 WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE 19 19 METADATA_VOLATILE_EN 20 20 RB_VOLATILE_EN 21 21 PROBE_UNSHARED_EN 22 22 MAX_MIN_CTRL 23 24 MDC_PF_LINEAR_METADATA 25 25 MDC_UC_TO_C_RO_EN 26 26 MDC_PF_MIN_PAGE_SIZE 27 28 MDC_PF_DISABLE 29 31 mmGL2C_ADDR_MATCH_MASK 0 0x2e03 1 0 1 ADDR_MASK 0 31 mmGL2C_ADDR_MATCH_SIZE 0 0x2e04 1 0 1 MAX_COUNT 0 2 mmGL2C_WBINVL2 0 0x2e05 1 0 1 DONE 4 4 mmGL2C_SOFT_RESET 0 0x2e06 1 0 1 HALT_FOR_RESET 0 0 mmGL2C_CM_CTRL0 0 0x2e07 0 0 1 mmGL2C_CM_CTRL1 0 0x2e08 10 0 1 BURST_TIMER 8 15 RVF_SIZE 16 19 WRITE_COH_MODE 23 24 MDC_ARB_MODE 25 25 READ_REQ_ONLY 26 26 COMP_TO_CONSTANT_EN 27 27 COMP_TO_SINGLE_EN 28 28 BURST_MODE 29 29 UNCOMP_READBACK_FILTER 30 30 WAIT_ATOMIC_RECOMP_WRITE 31 31 mmGL2C_CM_STALL 0 0x2e09 1 0 1 QUEUE 0 31 mmGL2C_MDC_PF_FLAG_CTRL 0 0x2e0a 1 0 1 TIMER 0 31 mmGL2C_LB_CTR_CTRL 0 0x2e0d 4 0 1 START 0 0 LOAD 1 1 CLEAR 2 2 PERF_CNTR_EN_OVERRIDE 31 31 mmGL2C_LB_DATA0 0 0x2e0e 1 0 1 DATA 0 31 mmGL2C_LB_DATA1 0 0x2e0f 1 0 1 DATA 0 31 mmGL2C_LB_DATA2 0 0x2e10 1 0 1 DATA 0 31 mmGL2C_LB_DATA3 0 0x2e11 1 0 1 DATA 0 31 mmGL2C_LB_CTR_SEL0 0 0x2e12 4 0 1 SEL0 0 7 DIV0 15 15 SEL1 16 23 DIV1 31 31 mmGL2C_LB_CTR_SEL1 0 0x2e13 4 0 1 SEL2 0 7 DIV2 15 15 SEL3 16 23 DIV3 31 31 mmGL2A_ADDR_MATCH_CTRL 0 0x2e20 1 0 1 DISABLE 0 31 mmGL2A_ADDR_MATCH_MASK 0 0x2e21 1 0 1 ADDR_MASK 0 31 mmGL2A_ADDR_MATCH_SIZE 0 0x2e22 1 0 1 MAX_COUNT 0 2 mmGL2A_PRIORITY_CTRL 0 0x2e23 1 0 1 DISABLE 0 31 mmGL2_PIPE_STEER_0 0 0x2e25 8 0 1 PIPE_0_TO_CHAN_IN_Q0 0 2 PIPE_1_TO_CHAN_IN_Q0 4 6 PIPE_2_TO_CHAN_IN_Q0 8 10 PIPE_3_TO_CHAN_IN_Q0 12 14 PIPE_0_TO_CHAN_IN_Q1 16 18 PIPE_1_TO_CHAN_IN_Q1 20 22 PIPE_2_TO_CHAN_IN_Q1 24 26 PIPE_3_TO_CHAN_IN_Q1 28 30 mmGL2_PIPE_STEER_1 0 0x2e26 8 0 1 PIPE_0_TO_CHAN_IN_Q2 0 2 PIPE_1_TO_CHAN_IN_Q2 4 6 PIPE_2_TO_CHAN_IN_Q2 8 10 PIPE_3_TO_CHAN_IN_Q2 12 14 PIPE_0_TO_CHAN_IN_Q3 16 18 PIPE_1_TO_CHAN_IN_Q3 20 22 PIPE_2_TO_CHAN_IN_Q3 24 26 PIPE_3_TO_CHAN_IN_Q3 28 30 mmCPG_PERFCOUNTER1_LO 0 0x3000 1 0 1 PERFCOUNTER_LO 0 31 mmCPG_PERFCOUNTER1_HI 0 0x3001 1 0 1 PERFCOUNTER_HI 0 31 mmCPG_PERFCOUNTER0_LO 0 0x3002 1 0 1 PERFCOUNTER_LO 0 31 mmCPG_PERFCOUNTER0_HI 0 0x3003 1 0 1 PERFCOUNTER_HI 0 31 mmCPC_PERFCOUNTER1_LO 0 0x3004 1 0 1 PERFCOUNTER_LO 0 31 mmCPC_PERFCOUNTER1_HI 0 0x3005 1 0 1 PERFCOUNTER_HI 0 31 mmCPC_PERFCOUNTER0_LO 0 0x3006 1 0 1 PERFCOUNTER_LO 0 31 mmCPC_PERFCOUNTER0_HI 0 0x3007 1 0 1 PERFCOUNTER_HI 0 31 mmCPF_PERFCOUNTER1_LO 0 0x3008 1 0 1 PERFCOUNTER_LO 0 31 mmCPF_PERFCOUNTER1_HI 0 0x3009 1 0 1 PERFCOUNTER_HI 0 31 mmCPF_PERFCOUNTER0_LO 0 0x300a 1 0 1 PERFCOUNTER_LO 0 31 mmCPF_PERFCOUNTER0_HI 0 0x300b 1 0 1 PERFCOUNTER_HI 0 31 mmCPF_LATENCY_STATS_DATA 0 0x300c 1 0 1 DATA 0 31 mmCPG_LATENCY_STATS_DATA 0 0x300d 1 0 1 DATA 0 31 mmCPC_LATENCY_STATS_DATA 0 0x300e 1 0 1 DATA 0 31 mmGRBM_PERFCOUNTER0_LO 0 0x3040 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_PERFCOUNTER0_HI 0 0x3041 1 0 1 PERFCOUNTER_HI 0 31 mmGRBM_PERFCOUNTER1_LO 0 0x3043 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_PERFCOUNTER1_HI 0 0x3044 1 0 1 PERFCOUNTER_HI 0 31 mmGRBM_SE0_PERFCOUNTER_LO 0 0x3045 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_SE0_PERFCOUNTER_HI 0 0x3046 1 0 1 PERFCOUNTER_HI 0 31 mmGRBM_SE1_PERFCOUNTER_LO 0 0x3047 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_SE1_PERFCOUNTER_HI 0 0x3048 1 0 1 PERFCOUNTER_HI 0 31 mmGRBM_SE2_PERFCOUNTER_LO 0 0x3049 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_SE2_PERFCOUNTER_HI 0 0x304a 1 0 1 PERFCOUNTER_HI 0 31 mmGRBM_SE3_PERFCOUNTER_LO 0 0x304b 1 0 1 PERFCOUNTER_LO 0 31 mmGRBM_SE3_PERFCOUNTER_HI 0 0x304c 1 0 1 PERFCOUNTER_HI 0 31 mmGE1_PERFCOUNTER0_LO 0 0x30a4 1 0 1 PERFCOUNTER_LO 0 31 mmGE1_PERFCOUNTER0_HI 0 0x30a5 1 0 1 PERFCOUNTER_HI 0 31 mmGE1_PERFCOUNTER1_LO 0 0x30a6 1 0 1 PERFCOUNTER_LO 0 31 mmGE1_PERFCOUNTER1_HI 0 0x30a7 1 0 1 PERFCOUNTER_HI 0 31 mmGE1_PERFCOUNTER2_LO 0 0x30a8 1 0 1 PERFCOUNTER_LO 0 31 mmGE1_PERFCOUNTER2_HI 0 0x30a9 1 0 1 PERFCOUNTER_HI 0 31 mmGE1_PERFCOUNTER3_LO 0 0x30aa 1 0 1 PERFCOUNTER_LO 0 31 mmGE1_PERFCOUNTER3_HI 0 0x30ab 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_DIST_PERFCOUNTER0_LO 0 0x30ac 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_DIST_PERFCOUNTER0_HI 0 0x30ad 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_DIST_PERFCOUNTER1_LO 0 0x30ae 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_DIST_PERFCOUNTER1_HI 0 0x30af 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_DIST_PERFCOUNTER2_LO 0 0x30b0 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_DIST_PERFCOUNTER2_HI 0 0x30b1 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_DIST_PERFCOUNTER3_LO 0 0x30b2 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_DIST_PERFCOUNTER3_HI 0 0x30b3 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_SE_PERFCOUNTER0_LO 0 0x30b4 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_SE_PERFCOUNTER0_HI 0 0x30b5 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_SE_PERFCOUNTER1_LO 0 0x30b6 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_SE_PERFCOUNTER1_HI 0 0x30b7 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_SE_PERFCOUNTER2_LO 0 0x30b8 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_SE_PERFCOUNTER2_HI 0 0x30b9 1 0 1 PERFCOUNTER_HI 0 31 mmGE2_SE_PERFCOUNTER3_LO 0 0x30ba 1 0 1 PERFCOUNTER_LO 0 31 mmGE2_SE_PERFCOUNTER3_HI 0 0x30bb 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SU_PERFCOUNTER0_LO 0 0x3100 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER0_HI 0 0x3101 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SU_PERFCOUNTER1_LO 0 0x3102 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER1_HI 0 0x3103 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SU_PERFCOUNTER2_LO 0 0x3104 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER2_HI 0 0x3105 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SU_PERFCOUNTER3_LO 0 0x3106 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER3_HI 0 0x3107 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER0_LO 0 0x3140 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER0_HI 0 0x3141 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER1_LO 0 0x3142 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER1_HI 0 0x3143 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER2_LO 0 0x3144 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER2_HI 0 0x3145 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER3_LO 0 0x3146 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER3_HI 0 0x3147 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER4_LO 0 0x3148 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER4_HI 0 0x3149 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER5_LO 0 0x314a 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER5_HI 0 0x314b 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER6_LO 0 0x314c 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER6_HI 0 0x314d 1 0 1 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER7_LO 0 0x314e 1 0 1 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER7_HI 0 0x314f 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER0_HI 0 0x3180 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER0_LO 0 0x3181 1 0 1 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER1_HI 0 0x3182 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER1_LO 0 0x3183 1 0 1 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER2_HI 0 0x3184 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER2_LO 0 0x3185 1 0 1 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER3_HI 0 0x3186 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER3_LO 0 0x3187 1 0 1 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER4_HI 0 0x3188 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER4_LO 0 0x3189 1 0 1 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER5_HI 0 0x318a 1 0 1 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER5_LO 0 0x318b 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER0_LO 0 0x31c0 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER0_HI 0 0x31c1 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER1_LO 0 0x31c2 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER1_HI 0 0x31c3 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER2_LO 0 0x31c4 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER2_HI 0 0x31c5 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER3_LO 0 0x31c6 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER3_HI 0 0x31c7 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER4_LO 0 0x31c8 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER4_HI 0 0x31c9 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER5_LO 0 0x31ca 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER5_HI 0 0x31cb 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER6_LO 0 0x31cc 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER6_HI 0 0x31cd 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER7_LO 0 0x31ce 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER7_HI 0 0x31cf 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER8_LO 0 0x31d0 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER8_HI 0 0x31d1 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER9_LO 0 0x31d2 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER9_HI 0 0x31d3 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER10_LO 0 0x31d4 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER10_HI 0 0x31d5 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER11_LO 0 0x31d6 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER11_HI 0 0x31d7 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER12_LO 0 0x31d8 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER12_HI 0 0x31d9 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER13_LO 0 0x31da 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER13_HI 0 0x31db 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER14_LO 0 0x31dc 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER14_HI 0 0x31dd 1 0 1 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER15_LO 0 0x31de 1 0 1 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER15_HI 0 0x31df 1 0 1 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER0_LO 0 0x3240 1 0 1 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER0_HI 0 0x3241 1 0 1 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER1_LO 0 0x3242 1 0 1 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER1_HI 0 0x3243 1 0 1 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER2_LO 0 0x3244 1 0 1 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER2_HI 0 0x3245 1 0 1 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER3_LO 0 0x3246 1 0 1 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER3_HI 0 0x3247 1 0 1 PERFCOUNTER_HI 0 31 mmGCEA_PERFCOUNTER2_LO 0 0x3260 1 0 1 PERFCOUNTER_LO 0 31 mmGCEA_PERFCOUNTER2_HI 0 0x3261 1 0 1 PERFCOUNTER_HI 0 31 mmGCEA_PERFCOUNTER_LO 0 0x3262 1 0 1 COUNTER_LO 0 31 mmGCEA_PERFCOUNTER_HI 0 0x3263 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmGDS_PERFCOUNTER0_LO 0 0x3280 1 0 1 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER0_HI 0 0x3281 1 0 1 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER1_LO 0 0x3282 1 0 1 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER1_HI 0 0x3283 1 0 1 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER2_LO 0 0x3284 1 0 1 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER2_HI 0 0x3285 1 0 1 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER3_LO 0 0x3286 1 0 1 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER3_HI 0 0x3287 1 0 1 PERFCOUNTER_HI 0 31 mmTA_PERFCOUNTER0_LO 0 0x32c0 1 0 1 PERFCOUNTER_LO 0 31 mmTA_PERFCOUNTER0_HI 0 0x32c1 1 0 1 PERFCOUNTER_HI 0 31 mmTA_PERFCOUNTER1_LO 0 0x32c2 1 0 1 PERFCOUNTER_LO 0 31 mmTA_PERFCOUNTER1_HI 0 0x32c3 1 0 1 PERFCOUNTER_HI 0 31 mmTD_PERFCOUNTER0_LO 0 0x3300 1 0 1 PERFCOUNTER_LO 0 31 mmTD_PERFCOUNTER0_HI 0 0x3301 1 0 1 PERFCOUNTER_HI 0 31 mmTD_PERFCOUNTER1_LO 0 0x3302 1 0 1 PERFCOUNTER_LO 0 31 mmTD_PERFCOUNTER1_HI 0 0x3303 1 0 1 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER0_LO 0 0x3340 1 0 1 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER0_HI 0 0x3341 1 0 1 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER1_LO 0 0x3342 1 0 1 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER1_HI 0 0x3343 1 0 1 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER2_LO 0 0x3344 1 0 1 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER2_HI 0 0x3345 1 0 1 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER3_LO 0 0x3346 1 0 1 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER3_HI 0 0x3347 1 0 1 PERFCOUNTER_HI 0 31 mmGL2C_PERFCOUNTER0_LO 0 0x3380 1 0 1 PERFCOUNTER_LO 0 31 mmGL2C_PERFCOUNTER0_HI 0 0x3381 1 0 1 PERFCOUNTER_HI 0 31 mmGL2C_PERFCOUNTER1_LO 0 0x3382 1 0 1 PERFCOUNTER_LO 0 31 mmGL2C_PERFCOUNTER1_HI 0 0x3383 1 0 1 PERFCOUNTER_HI 0 31 mmGL2C_PERFCOUNTER2_LO 0 0x3384 1 0 1 PERFCOUNTER_LO 0 31 mmGL2C_PERFCOUNTER2_HI 0 0x3385 1 0 1 PERFCOUNTER_HI 0 31 mmGL2C_PERFCOUNTER3_LO 0 0x3386 1 0 1 PERFCOUNTER_LO 0 31 mmGL2C_PERFCOUNTER3_HI 0 0x3387 1 0 1 PERFCOUNTER_HI 0 31 mmGL2A_PERFCOUNTER0_LO 0 0x3390 1 0 1 PERFCOUNTER_LO 0 31 mmGL2A_PERFCOUNTER0_HI 0 0x3391 1 0 1 PERFCOUNTER_HI 0 31 mmGL2A_PERFCOUNTER1_LO 0 0x3392 1 0 1 PERFCOUNTER_LO 0 31 mmGL2A_PERFCOUNTER1_HI 0 0x3393 1 0 1 PERFCOUNTER_HI 0 31 mmGL2A_PERFCOUNTER2_LO 0 0x3394 1 0 1 PERFCOUNTER_LO 0 31 mmGL2A_PERFCOUNTER2_HI 0 0x3395 1 0 1 PERFCOUNTER_HI 0 31 mmGL2A_PERFCOUNTER3_LO 0 0x3396 1 0 1 PERFCOUNTER_LO 0 31 mmGL2A_PERFCOUNTER3_HI 0 0x3397 1 0 1 PERFCOUNTER_HI 0 31 mmGL1C_PERFCOUNTER0_LO 0 0x33a0 1 0 1 PERFCOUNTER_LO 0 31 mmGL1C_PERFCOUNTER0_HI 0 0x33a1 1 0 1 PERFCOUNTER_HI 0 31 mmGL1C_PERFCOUNTER1_LO 0 0x33a2 1 0 1 PERFCOUNTER_LO 0 31 mmGL1C_PERFCOUNTER1_HI 0 0x33a3 1 0 1 PERFCOUNTER_HI 0 31 mmGL1C_PERFCOUNTER2_LO 0 0x33a4 1 0 1 PERFCOUNTER_LO 0 31 mmGL1C_PERFCOUNTER2_HI 0 0x33a5 1 0 1 PERFCOUNTER_HI 0 31 mmGL1C_PERFCOUNTER3_LO 0 0x33a6 1 0 1 PERFCOUNTER_LO 0 31 mmGL1C_PERFCOUNTER3_HI 0 0x33a7 1 0 1 PERFCOUNTER_HI 0 31 mmCHC_PERFCOUNTER0_LO 0 0x33c0 1 0 1 PERFCOUNTER_LO 0 31 mmCHC_PERFCOUNTER0_HI 0 0x33c1 1 0 1 PERFCOUNTER_HI 0 31 mmCHC_PERFCOUNTER1_LO 0 0x33c2 1 0 1 PERFCOUNTER_LO 0 31 mmCHC_PERFCOUNTER1_HI 0 0x33c3 1 0 1 PERFCOUNTER_HI 0 31 mmCHC_PERFCOUNTER2_LO 0 0x33c4 1 0 1 PERFCOUNTER_LO 0 31 mmCHC_PERFCOUNTER2_HI 0 0x33c5 1 0 1 PERFCOUNTER_HI 0 31 mmCHC_PERFCOUNTER3_LO 0 0x33c6 1 0 1 PERFCOUNTER_LO 0 31 mmCHC_PERFCOUNTER3_HI 0 0x33c7 1 0 1 PERFCOUNTER_HI 0 31 mmCHCG_PERFCOUNTER0_LO 0 0x33c8 1 0 1 PERFCOUNTER_LO 0 31 mmCHCG_PERFCOUNTER0_HI 0 0x33c9 1 0 1 PERFCOUNTER_HI 0 31 mmCHCG_PERFCOUNTER1_LO 0 0x33ca 1 0 1 PERFCOUNTER_LO 0 31 mmCHCG_PERFCOUNTER1_HI 0 0x33cb 1 0 1 PERFCOUNTER_HI 0 31 mmCHCG_PERFCOUNTER2_LO 0 0x33cc 1 0 1 PERFCOUNTER_LO 0 31 mmCHCG_PERFCOUNTER2_HI 0 0x33cd 1 0 1 PERFCOUNTER_HI 0 31 mmCHCG_PERFCOUNTER3_LO 0 0x33ce 1 0 1 PERFCOUNTER_LO 0 31 mmCHCG_PERFCOUNTER3_HI 0 0x33cf 1 0 1 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER0_LO 0 0x3406 1 0 1 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER0_HI 0 0x3407 1 0 1 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER1_LO 0 0x3408 1 0 1 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER1_HI 0 0x3409 1 0 1 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER2_LO 0 0x340a 1 0 1 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER2_HI 0 0x340b 1 0 1 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER3_LO 0 0x340c 1 0 1 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER3_HI 0 0x340d 1 0 1 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER0_LO 0 0x3440 1 0 1 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER0_HI 0 0x3441 1 0 1 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER1_LO 0 0x3442 1 0 1 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER1_HI 0 0x3443 1 0 1 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER2_LO 0 0x3444 1 0 1 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER2_HI 0 0x3445 1 0 1 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER3_LO 0 0x3446 1 0 1 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER3_HI 0 0x3447 1 0 1 PERFCOUNTER_HI 0 31 mmRLC_PERFCOUNTER0_LO 0 0x3480 1 0 1 PERFCOUNTER_LO 0 31 mmRLC_PERFCOUNTER0_HI 0 0x3481 1 0 1 PERFCOUNTER_HI 0 31 mmRLC_PERFCOUNTER1_LO 0 0x3482 1 0 1 PERFCOUNTER_LO 0 31 mmRLC_PERFCOUNTER1_HI 0 0x3483 1 0 1 PERFCOUNTER_HI 0 31 mmRMI_PERFCOUNTER0_LO 0 0x34c0 1 0 1 PERFCOUNTER_LO 0 31 mmRMI_PERFCOUNTER0_HI 0 0x34c1 1 0 1 PERFCOUNTER_HI 0 31 mmRMI_PERFCOUNTER1_LO 0 0x34c2 1 0 1 PERFCOUNTER_LO 0 31 mmRMI_PERFCOUNTER1_HI 0 0x34c3 1 0 1 PERFCOUNTER_HI 0 31 mmRMI_PERFCOUNTER2_LO 0 0x34c4 1 0 1 PERFCOUNTER_LO 0 31 mmRMI_PERFCOUNTER2_HI 0 0x34c5 1 0 1 PERFCOUNTER_HI 0 31 mmRMI_PERFCOUNTER3_LO 0 0x34c6 1 0 1 PERFCOUNTER_LO 0 31 mmRMI_PERFCOUNTER3_HI 0 0x34c7 1 0 1 PERFCOUNTER_HI 0 31 mmUTCL1_PERFCOUNTER0_LO 0 0x351c 1 0 1 PERFCOUNTER_LO 0 31 mmUTCL1_PERFCOUNTER0_HI 0 0x351d 1 0 1 PERFCOUNTER_HI 0 31 mmUTCL1_PERFCOUNTER1_LO 0 0x351e 1 0 1 PERFCOUNTER_LO 0 31 mmUTCL1_PERFCOUNTER1_HI 0 0x351f 1 0 1 PERFCOUNTER_HI 0 31 mmGCR_PERFCOUNTER0_LO 0 0x3520 1 0 1 PERFCOUNTER_LO 0 31 mmGCR_PERFCOUNTER0_HI 0 0x3521 1 0 1 PERFCOUNTER_HI 0 31 mmGCR_PERFCOUNTER1_LO 0 0x3522 1 0 1 PERFCOUNTER_LO 0 31 mmGCR_PERFCOUNTER1_HI 0 0x3523 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER0_LO 0 0x3580 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER0_HI 0 0x3581 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER1_LO 0 0x3582 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER1_HI 0 0x3583 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER2_LO 0 0x3584 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER2_HI 0 0x3585 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER3_LO 0 0x3586 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER3_HI 0 0x3587 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER4_LO 0 0x3588 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER4_HI 0 0x3589 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER5_LO 0 0x358a 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER5_HI 0 0x358b 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER6_LO 0 0x358c 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER6_HI 0 0x358d 1 0 1 PERFCOUNTER_HI 0 31 mmPA_PH_PERFCOUNTER7_LO 0 0x358e 1 0 1 PERFCOUNTER_LO 0 31 mmPA_PH_PERFCOUNTER7_HI 0 0x358f 1 0 1 PERFCOUNTER_HI 0 31 mmGL1A_PERFCOUNTER0_LO 0 0x35c0 1 0 1 PERFCOUNTER_LO 0 31 mmGL1A_PERFCOUNTER0_HI 0 0x35c1 1 0 1 PERFCOUNTER_HI 0 31 mmGL1A_PERFCOUNTER1_LO 0 0x35c2 1 0 1 PERFCOUNTER_LO 0 31 mmGL1A_PERFCOUNTER1_HI 0 0x35c3 1 0 1 PERFCOUNTER_HI 0 31 mmGL1A_PERFCOUNTER2_LO 0 0x35c4 1 0 1 PERFCOUNTER_LO 0 31 mmGL1A_PERFCOUNTER2_HI 0 0x35c5 1 0 1 PERFCOUNTER_HI 0 31 mmGL1A_PERFCOUNTER3_LO 0 0x35c6 1 0 1 PERFCOUNTER_LO 0 31 mmGL1A_PERFCOUNTER3_HI 0 0x35c7 1 0 1 PERFCOUNTER_HI 0 31 mmCHA_PERFCOUNTER0_LO 0 0x3600 1 0 1 PERFCOUNTER_LO 0 31 mmCHA_PERFCOUNTER0_HI 0 0x3601 1 0 1 PERFCOUNTER_HI 0 31 mmCHA_PERFCOUNTER1_LO 0 0x3602 1 0 1 PERFCOUNTER_LO 0 31 mmCHA_PERFCOUNTER1_HI 0 0x3603 1 0 1 PERFCOUNTER_HI 0 31 mmCHA_PERFCOUNTER2_LO 0 0x3604 1 0 1 PERFCOUNTER_LO 0 31 mmCHA_PERFCOUNTER2_HI 0 0x3605 1 0 1 PERFCOUNTER_HI 0 31 mmCHA_PERFCOUNTER3_LO 0 0x3606 1 0 1 PERFCOUNTER_LO 0 31 mmCHA_PERFCOUNTER3_HI 0 0x3607 1 0 1 PERFCOUNTER_HI 0 31 mmGUS_PERFCOUNTER2_LO 0 0x3640 1 0 1 PERFCOUNTER_LO 0 31 mmGUS_PERFCOUNTER2_HI 0 0x3641 1 0 1 PERFCOUNTER_HI 0 31 mmGUS_PERFCOUNTER_LO 0 0x3642 1 0 1 COUNTER_LO 0 31 mmGUS_PERFCOUNTER_HI 0 0x3643 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmGCMC_VM_L2_PERFCOUNTER_LO 0 0x34e8 1 0 1 COUNTER_LO 0 31 mmGCMC_VM_L2_PERFCOUNTER_HI 0 0x34e9 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmGCUTCL2_PERFCOUNTER_LO 0 0x34ea 1 0 1 COUNTER_LO 0 31 mmGCUTCL2_PERFCOUNTER_HI 0 0x34eb 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmGCVML2_PERFCOUNTER2_0_LO 0 0x34f8 1 0 1 PERFCOUNTER_LO 0 31 mmGCVML2_PERFCOUNTER2_1_LO 0 0x34f9 1 0 1 PERFCOUNTER_LO 0 31 mmGCVML2_PERFCOUNTER2_0_HI 0 0x34fa 1 0 1 PERFCOUNTER_HI 0 31 mmGCVML2_PERFCOUNTER2_1_HI 0 0x34fb 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA0_PERFCNT_PERFCOUNTER_LO 0 0x3660 1 0 1 COUNTER_LO 0 31 mmSDMA0_PERFCNT_PERFCOUNTER_HI 0 0x3661 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmSDMA0_PERFCOUNTER0_LO 0 0x3662 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA0_PERFCOUNTER0_HI 0 0x3663 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA0_PERFCOUNTER1_LO 0 0x3664 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA0_PERFCOUNTER1_HI 0 0x3665 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA1_PERFCNT_PERFCOUNTER_LO 0 0x366c 1 0 1 COUNTER_LO 0 31 mmSDMA1_PERFCNT_PERFCOUNTER_HI 0 0x366d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmSDMA1_PERFCOUNTER0_LO 0 0x366e 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA1_PERFCOUNTER0_HI 0 0x366f 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA1_PERFCOUNTER1_LO 0 0x3670 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA1_PERFCOUNTER1_HI 0 0x3671 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA2_PERFCNT_PERFCOUNTER_LO 0 0x3678 1 0 1 COUNTER_LO 0 31 mmSDMA2_PERFCNT_PERFCOUNTER_HI 0 0x3679 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmSDMA2_PERFCOUNTER0_LO 0 0x367a 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA2_PERFCOUNTER0_HI 0 0x367b 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA2_PERFCOUNTER1_LO 0 0x367c 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA2_PERFCOUNTER1_HI 0 0x367d 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA3_PERFCNT_PERFCOUNTER_LO 0 0x3684 1 0 1 COUNTER_LO 0 31 mmSDMA3_PERFCNT_PERFCOUNTER_HI 0 0x3685 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmSDMA3_PERFCOUNTER0_LO 0 0x3686 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA3_PERFCOUNTER0_HI 0 0x3687 1 0 1 PERFCOUNTER_HI 0 31 mmSDMA3_PERFCOUNTER1_LO 0 0x3688 1 0 1 PERFCOUNTER_LO 0 31 mmSDMA3_PERFCOUNTER1_HI 0 0x3689 1 0 1 PERFCOUNTER_HI 0 31 mmCPG_PERFCOUNTER1_SELECT 0 0x3800 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCPG_PERFCOUNTER0_SELECT1 0 0x3801 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 mmCPG_PERFCOUNTER0_SELECT 0 0x3802 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCPC_PERFCOUNTER1_SELECT 0 0x3803 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCPC_PERFCOUNTER0_SELECT1 0 0x3804 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 mmCPF_PERFCOUNTER1_SELECT 0 0x3805 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCPF_PERFCOUNTER0_SELECT1 0 0x3806 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 mmCPF_PERFCOUNTER0_SELECT 0 0x3807 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCP_PERFMON_CNTL 0 0x3808 4 0 1 PERFMON_STATE 0 3 SPM_PERFMON_STATE 4 7 PERFMON_ENABLE_MODE 8 9 PERFMON_SAMPLE_ENABLE 10 10 mmCPC_PERFCOUNTER0_SELECT 0 0x3809 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 mmCPF_TC_PERF_COUNTER_WINDOW_SELECT 0 0x380a 3 0 1 INDEX 0 2 ALWAYS 30 30 ENABLE 31 31 mmCPG_TC_PERF_COUNTER_WINDOW_SELECT 0 0x380b 3 0 1 INDEX 0 4 ALWAYS 30 30 ENABLE 31 31 mmCPF_LATENCY_STATS_SELECT 0 0x380c 3 0 1 INDEX 0 3 CLEAR 30 30 ENABLE 31 31 mmCPG_LATENCY_STATS_SELECT 0 0x380d 3 0 1 INDEX 0 4 CLEAR 30 30 ENABLE 31 31 mmCPC_LATENCY_STATS_SELECT 0 0x380e 3 0 1 INDEX 0 3 CLEAR 30 30 ENABLE 31 31 mmCP_DRAW_OBJECT 0 0x3810 1 0 1 OBJECT 0 31 mmCP_DRAW_OBJECT_COUNTER 0 0x3811 1 0 1 COUNT 0 15 mmCP_DRAW_WINDOW_MASK_HI 0 0x3812 1 0 1 WINDOW_MASK_HI 0 31 mmCP_DRAW_WINDOW_HI 0 0x3813 1 0 1 WINDOW_HI 0 31 mmCP_DRAW_WINDOW_LO 0 0x3814 2 0 1 MIN 0 15 MAX 16 31 mmCP_DRAW_WINDOW_CNTL 0 0x3815 4 0 1 DISABLE_DRAW_WINDOW_LO_MAX 0 0 DISABLE_DRAW_WINDOW_LO_MIN 1 1 DISABLE_DRAW_WINDOW_HI 2 2 MODE 8 8 mmGRBM_PERFCOUNTER0_SELECT 0 0x3840 20 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TCP_BUSY_USER_DEFINED_MASK 27 27 GE_BUSY_USER_DEFINED_MASK 28 28 UTCL2_BUSY_USER_DEFINED_MASK 29 29 EA_BUSY_USER_DEFINED_MASK 30 30 RMI_BUSY_USER_DEFINED_MASK 31 31 mmGRBM_PERFCOUNTER1_SELECT 0 0x3841 20 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TCP_BUSY_USER_DEFINED_MASK 27 27 GE_BUSY_USER_DEFINED_MASK 28 28 UTCL2_BUSY_USER_DEFINED_MASK 29 29 EA_BUSY_USER_DEFINED_MASK 30 30 RMI_BUSY_USER_DEFINED_MASK 31 31 mmGRBM_SE0_PERFCOUNTER_SELECT 0 0x3842 15 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 UTCL1_BUSY_USER_DEFINED_MASK 23 23 TCP_BUSY_USER_DEFINED_MASK 24 24 GL1CC_BUSY_USER_DEFINED_MASK 25 25 mmGRBM_SE1_PERFCOUNTER_SELECT 0 0x3843 15 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 UTCL1_BUSY_USER_DEFINED_MASK 23 23 TCP_BUSY_USER_DEFINED_MASK 24 24 GL1CC_BUSY_USER_DEFINED_MASK 25 25 mmGRBM_SE2_PERFCOUNTER_SELECT 0 0x3844 15 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 UTCL1_BUSY_USER_DEFINED_MASK 23 23 TCP_BUSY_USER_DEFINED_MASK 24 24 GL1CC_BUSY_USER_DEFINED_MASK 25 25 mmGRBM_SE3_PERFCOUNTER_SELECT 0 0x3845 15 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 UTCL1_BUSY_USER_DEFINED_MASK 23 23 TCP_BUSY_USER_DEFINED_MASK 24 24 GL1CC_BUSY_USER_DEFINED_MASK 25 25 mmGRBM_PERFCOUNTER0_SELECT_HI 0 0x384d 8 0 1 UTCL1_BUSY_USER_DEFINED_MASK 1 1 GL2CC_BUSY_USER_DEFINED_MASK 2 2 SDMA_BUSY_USER_DEFINED_MASK 3 3 CH_BUSY_USER_DEFINED_MASK 4 4 PH_BUSY_USER_DEFINED_MASK 5 5 PMM_BUSY_USER_DEFINED_MASK 6 6 GUS_BUSY_USER_DEFINED_MASK 7 7 GL1CC_BUSY_USER_DEFINED_MASK 8 8 mmGRBM_PERFCOUNTER1_SELECT_HI 0 0x384e 8 0 1 UTCL1_BUSY_USER_DEFINED_MASK 1 1 GL2CC_BUSY_USER_DEFINED_MASK 2 2 SDMA_BUSY_USER_DEFINED_MASK 3 3 CH_BUSY_USER_DEFINED_MASK 4 4 PH_BUSY_USER_DEFINED_MASK 5 5 PMM_BUSY_USER_DEFINED_MASK 6 6 GUS_BUSY_USER_DEFINED_MASK 7 7 GL1CC_BUSY_USER_DEFINED_MASK 8 8 mmGE1_PERFCOUNTER0_SELECT 0 0x38a4 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE1_PERFCOUNTER0_SELECT1 0 0x38a5 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE1_PERFCOUNTER1_SELECT 0 0x38a6 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE1_PERFCOUNTER1_SELECT1 0 0x38a7 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE1_PERFCOUNTER2_SELECT 0 0x38a8 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE1_PERFCOUNTER2_SELECT1 0 0x38a9 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE1_PERFCOUNTER3_SELECT 0 0x38aa 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE1_PERFCOUNTER3_SELECT1 0 0x38ab 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_DIST_PERFCOUNTER0_SELECT 0 0x38ac 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_DIST_PERFCOUNTER0_SELECT1 0 0x38ad 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_DIST_PERFCOUNTER1_SELECT 0 0x38ae 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_DIST_PERFCOUNTER1_SELECT1 0 0x38af 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_DIST_PERFCOUNTER2_SELECT 0 0x38b0 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_DIST_PERFCOUNTER2_SELECT1 0 0x38b1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_DIST_PERFCOUNTER3_SELECT 0 0x38b2 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_DIST_PERFCOUNTER3_SELECT1 0 0x38b3 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_SE_PERFCOUNTER0_SELECT 0 0x38b4 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_SE_PERFCOUNTER0_SELECT1 0 0x38b5 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_SE_PERFCOUNTER1_SELECT 0 0x38b6 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_SE_PERFCOUNTER1_SELECT1 0 0x38b7 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_SE_PERFCOUNTER2_SELECT 0 0x38b8 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_SE_PERFCOUNTER2_SELECT1 0 0x38b9 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGE2_SE_PERFCOUNTER3_SELECT 0 0x38ba 5 0 1 PERF_SEL0 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE0 24 27 PERF_MODE1 28 31 mmGE2_SE_PERFCOUNTER3_SELECT1 0 0x38bb 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmPA_SU_PERFCOUNTER0_SELECT 0 0x3900 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_SU_PERFCOUNTER0_SELECT1 0 0x3901 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_SU_PERFCOUNTER1_SELECT 0 0x3902 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_SU_PERFCOUNTER1_SELECT1 0 0x3903 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_SU_PERFCOUNTER2_SELECT 0 0x3904 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_SU_PERFCOUNTER2_SELECT1 0 0x3905 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_SU_PERFCOUNTER3_SELECT 0 0x3906 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_SU_PERFCOUNTER3_SELECT1 0 0x3907 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_SC_PERFCOUNTER0_SELECT 0 0x3940 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_SC_PERFCOUNTER0_SELECT1 0 0x3941 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_SC_PERFCOUNTER1_SELECT 0 0x3942 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER2_SELECT 0 0x3943 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER3_SELECT 0 0x3944 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER4_SELECT 0 0x3945 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER5_SELECT 0 0x3946 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER6_SELECT 0 0x3947 1 0 1 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER7_SELECT 0 0x3948 1 0 1 PERF_SEL 0 9 mmSPI_PERFCOUNTER0_SELECT 0 0x3980 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSPI_PERFCOUNTER1_SELECT 0 0x3981 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSPI_PERFCOUNTER2_SELECT 0 0x3982 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSPI_PERFCOUNTER3_SELECT 0 0x3983 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSPI_PERFCOUNTER0_SELECT1 0 0x3984 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSPI_PERFCOUNTER1_SELECT1 0 0x3985 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSPI_PERFCOUNTER2_SELECT1 0 0x3986 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSPI_PERFCOUNTER3_SELECT1 0 0x3987 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSPI_PERFCOUNTER4_SELECT 0 0x3988 1 0 1 PERF_SEL 0 9 mmSPI_PERFCOUNTER5_SELECT 0 0x3989 1 0 1 PERF_SEL 0 9 mmSPI_PERFCOUNTER_BINS 0 0x398a 8 0 1 BIN0_MIN 0 3 BIN0_MAX 4 7 BIN1_MIN 8 11 BIN1_MAX 12 15 BIN2_MIN 16 19 BIN2_MAX 20 23 BIN3_MIN 24 27 BIN3_MAX 28 31 mmSQ_PERFCOUNTER0_SELECT 0 0x39c0 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER1_SELECT 0 0x39c1 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER2_SELECT 0 0x39c2 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER3_SELECT 0 0x39c3 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER4_SELECT 0 0x39c4 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER5_SELECT 0 0x39c5 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER6_SELECT 0 0x39c6 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER7_SELECT 0 0x39c7 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER8_SELECT 0 0x39c8 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER9_SELECT 0 0x39c9 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER10_SELECT 0 0x39ca 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER11_SELECT 0 0x39cb 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER12_SELECT 0 0x39cc 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER13_SELECT 0 0x39cd 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER14_SELECT 0 0x39ce 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER15_SELECT 0 0x39cf 3 0 1 PERF_SEL 0 8 SPM_MODE 20 23 PERF_MODE 28 31 mmSQ_PERFCOUNTER_CTRL 0 0x39e0 15 0 1 PS_EN 0 0 VS_EN 1 1 GS_EN 2 2 ES_EN 3 3 HS_EN 4 4 LS_EN 5 5 CS_EN 6 6 CNTR_RATE 8 9 DISABLE_FLUSH 13 13 DISABLE_ME0PIPE0_PERF 14 14 DISABLE_ME0PIPE1_PERF 15 15 DISABLE_ME1PIPE0_PERF 16 16 DISABLE_ME1PIPE1_PERF 17 17 DISABLE_ME1PIPE2_PERF 18 18 DISABLE_ME1PIPE3_PERF 19 19 mmSQ_PERFCOUNTER_CTRL2 0 0x39e2 1 0 1 FORCE_EN 0 0 mmGCEA_PERFCOUNTER2_SELECT 0 0x3a00 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGCEA_PERFCOUNTER2_SELECT1 0 0x3a01 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGCEA_PERFCOUNTER2_MODE 0 0x3a02 8 0 1 COMPARE_MODE0 0 1 COMPARE_MODE1 2 3 COMPARE_MODE2 4 5 COMPARE_MODE3 6 7 COMPARE_VALUE0 8 11 COMPARE_VALUE1 12 15 COMPARE_VALUE2 16 19 COMPARE_VALUE3 20 23 mmGCEA_PERFCOUNTER0_CFG 0 0x3a03 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCEA_PERFCOUNTER1_CFG 0 0x3a04 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCEA_PERFCOUNTER_RSLT_CNTL 0 0x3a05 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmSX_PERFCOUNTER0_SELECT 0 0x3a40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSX_PERFCOUNTER1_SELECT 0 0x3a41 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSX_PERFCOUNTER2_SELECT 0 0x3a42 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmSX_PERFCOUNTER3_SELECT 0 0x3a43 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmSX_PERFCOUNTER0_SELECT1 0 0x3a44 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSX_PERFCOUNTER1_SELECT1 0 0x3a45 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGDS_PERFCOUNTER0_SELECT 0 0x3a80 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGDS_PERFCOUNTER1_SELECT 0 0x3a81 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGDS_PERFCOUNTER2_SELECT 0 0x3a82 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGDS_PERFCOUNTER3_SELECT 0 0x3a83 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGDS_PERFCOUNTER0_SELECT1 0 0x3a84 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGDS_PERFCOUNTER1_SELECT1 0 0x3a85 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGDS_PERFCOUNTER2_SELECT1 0 0x3a86 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGDS_PERFCOUNTER3_SELECT1 0 0x3a87 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTA_PERFCOUNTER0_SELECT 0 0x3ac0 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTA_PERFCOUNTER0_SELECT1 0 0x3ac1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTA_PERFCOUNTER1_SELECT 0 0x3ac2 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTD_PERFCOUNTER0_SELECT 0 0x3b00 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTD_PERFCOUNTER0_SELECT1 0 0x3b01 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTD_PERFCOUNTER1_SELECT 0 0x3b02 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCP_PERFCOUNTER0_SELECT 0 0x3b40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCP_PERFCOUNTER0_SELECT1 0 0x3b41 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTCP_PERFCOUNTER1_SELECT 0 0x3b42 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCP_PERFCOUNTER1_SELECT1 0 0x3b43 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTCP_PERFCOUNTER2_SELECT 0 0x3b44 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCP_PERFCOUNTER3_SELECT 0 0x3b45 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL2C_PERFCOUNTER0_SELECT 0 0x3b80 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL2C_PERFCOUNTER0_SELECT1 0 0x3b81 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL2C_PERFCOUNTER1_SELECT 0 0x3b82 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL2C_PERFCOUNTER1_SELECT1 0 0x3b83 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL2C_PERFCOUNTER2_SELECT 0 0x3b84 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL2C_PERFCOUNTER3_SELECT 0 0x3b85 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL2A_PERFCOUNTER0_SELECT 0 0x3b90 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL2A_PERFCOUNTER0_SELECT1 0 0x3b91 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL2A_PERFCOUNTER1_SELECT 0 0x3b92 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL2A_PERFCOUNTER1_SELECT1 0 0x3b93 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL2A_PERFCOUNTER2_SELECT 0 0x3b94 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL2A_PERFCOUNTER3_SELECT 0 0x3b95 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL1C_PERFCOUNTER0_SELECT 0 0x3ba0 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL1C_PERFCOUNTER0_SELECT1 0 0x3ba1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL1C_PERFCOUNTER1_SELECT 0 0x3ba2 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL1C_PERFCOUNTER2_SELECT 0 0x3ba3 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL1C_PERFCOUNTER3_SELECT 0 0x3ba4 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHC_PERFCOUNTER0_SELECT 0 0x3bc0 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmCHC_PERFCOUNTER0_SELECT1 0 0x3bc1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmCHC_PERFCOUNTER1_SELECT 0 0x3bc2 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHC_PERFCOUNTER2_SELECT 0 0x3bc3 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHC_PERFCOUNTER3_SELECT 0 0x3bc4 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHCG_PERFCOUNTER0_SELECT 0 0x3bc6 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmCHCG_PERFCOUNTER0_SELECT1 0 0x3bc7 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmCHCG_PERFCOUNTER1_SELECT 0 0x3bc8 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHCG_PERFCOUNTER2_SELECT 0 0x3bc9 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHCG_PERFCOUNTER3_SELECT 0 0x3bca 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCB_PERFCOUNTER_FILTER 0 0x3c00 12 0 1 OP_FILTER_ENABLE 0 0 OP_FILTER_SEL 1 3 FORMAT_FILTER_ENABLE 4 4 FORMAT_FILTER_SEL 5 9 CLEAR_FILTER_ENABLE 10 10 CLEAR_FILTER_SEL 11 11 MRT_FILTER_ENABLE 12 12 MRT_FILTER_SEL 13 15 NUM_SAMPLES_FILTER_ENABLE 17 17 NUM_SAMPLES_FILTER_SEL 18 20 NUM_FRAGMENTS_FILTER_ENABLE 21 21 NUM_FRAGMENTS_FILTER_SEL 22 23 mmCB_PERFCOUNTER0_SELECT 0 0x3c01 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmCB_PERFCOUNTER0_SELECT1 0 0x3c02 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 mmCB_PERFCOUNTER1_SELECT 0 0x3c03 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 mmCB_PERFCOUNTER2_SELECT 0 0x3c04 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 mmCB_PERFCOUNTER3_SELECT 0 0x3c05 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 mmDB_PERFCOUNTER0_SELECT 0 0x3c40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER0_SELECT1 0 0x3c41 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmDB_PERFCOUNTER1_SELECT 0 0x3c42 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER1_SELECT1 0 0x3c43 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmDB_PERFCOUNTER2_SELECT 0 0x3c44 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER3_SELECT 0 0x3c46 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmRLC_SPM_PERFMON_CNTL 0 0x3c80 4 0 1 RESERVED1 0 11 PERFMON_RING_MODE 12 13 RESERVED 14 15 PERFMON_SAMPLE_INTERVAL 16 31 mmRLC_SPM_PERFMON_RING_BASE_LO 0 0x3c81 1 0 1 RING_BASE_LO 0 31 mmRLC_SPM_PERFMON_RING_BASE_HI 0 0x3c82 2 0 1 RING_BASE_HI 0 15 RESERVED 16 31 mmRLC_SPM_PERFMON_RING_SIZE 0 0x3c83 1 0 1 RING_BASE_SIZE 0 31 mmRLC_SPM_PERFMON_SEGMENT_SIZE 0 0x3c84 7 0 1 PERFMON_SEGMENT_SIZE 0 7 RESERVED1 8 10 GLOBAL_NUM_LINE 11 15 SE0_NUM_LINE 16 20 SE1_NUM_LINE 21 25 SE2_NUM_LINE 26 30 RESERVED 31 31 mmRLC_SPM_RING_RDPTR 0 0x3c85 1 0 1 PERFMON_RING_RDPTR 0 31 mmRLC_SPM_SEGMENT_THRESHOLD 0 0x3c86 2 0 1 NUM_SEGMENT_THRESHOLD 0 7 RESERVED 8 31 mmRLC_SPM_SE_MUXSEL_ADDR 0 0x3c87 2 0 1 PERFMON_SEL_ADDR 0 8 RESERVED 9 31 mmRLC_SPM_SE_MUXSEL_DATA 0 0x3c88 1 0 1 PERFMON_SEL_DATA 0 31 mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0 0x3c89 2 0 1 PERFMON_SEL_ADDR 0 7 RESERVED 8 31 mmRLC_SPM_GLOBAL_MUXSEL_DATA 0 0x3c8a 1 0 1 PERFMON_SEL_DATA 0 31 mmRLC_SPM_DESER_START_SKEW 0 0x3c8b 2 0 1 DESER_START_SKEW 0 6 RESERVED 7 31 mmRLC_SPM_GLOBALS_SAMPLE_SKEW 0 0x3c8c 2 0 1 GLOBALS_SAMPLE_SKEW 0 6 RESERVED 7 31 mmRLC_SPM_GLOBALS_MUXSEL_SKEW 0 0x3c8d 2 0 1 GLOBALS_MUXSEL_SKEW 0 6 RESERVED 7 31 mmRLC_SPM_SE_SAMPLE_SKEW 0 0x3c8e 2 0 1 SE_SAMPLE_SKEW 0 6 RESERVED 7 31 mmRLC_SPM_SE_MUXSEL_SKEW 0 0x3c8f 2 0 1 SE_MUXSEL_SKEW 0 6 RESERVED 7 31 mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR 0 0x3c90 1 0 1 GLB_SAMPLEDELAY_INDEX 0 31 mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA 0 0x3c91 2 0 1 data 0 6 RESERVED 7 31 mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR 0 0x3c92 1 0 1 SE_SAMPLEDELAY_INDEX 0 31 mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA 0 0x3c93 2 0 1 data 0 6 RESERVED 7 31 mmRLC_SPM_RING_WRPTR 0 0x3c94 2 0 1 RESERVED 0 4 PERFMON_RING_WRPTR 5 31 mmRLC_SPM_ACCUM_DATARAM_ADDR 0 0x3c95 2 0 1 addr 0 6 RESERVED 7 31 mmRLC_SPM_ACCUM_DATARAM_DATA 0 0x3c96 1 0 1 data 0 31 mmRLC_SPM_ACCUM_CTRLRAM_ADDR 0 0x3c97 2 0 1 addr 0 10 RESERVED 11 31 mmRLC_SPM_ACCUM_CTRLRAM_DATA 0 0x3c98 2 0 1 data 0 7 RESERVED 8 31 mmRLC_SPM_ACCUM_STATUS 0 0x3c99 17 0 1 NumbSamplesCompleted 0 7 AccumDone 8 8 SpmDone 9 9 AccumOverflow 10 10 AccumArmed 11 11 SequenceInProgress 12 12 FinalSequenceInProgress 13 13 AllFifosEmpty 14 14 FSMIsIdle 15 15 SwaAccumDone 16 16 SwaSpmDone 17 17 SwaAccumOverflow 18 18 SwaAccumArmed 19 19 AllSegsDone 20 20 RearmSwaPending 21 21 RearmSppPending 22 22 RESERVED 23 31 mmRLC_SPM_ACCUM_CTRL 0 0x3c9a 9 0 1 StrobeResetPerfMonitors 0 0 StrobeStartAccumulation 1 1 StrobeRearmAccum 2 2 StrobeResetSpmBlock 3 3 StrobeStartSpm 4 7 StrobeRearmSwaAccum 8 8 StrobeStartSwa 9 9 StrobePerfmonSampleWires 10 10 RESERVED 11 31 mmRLC_SPM_ACCUM_MODE 0 0x3c9b 19 0 1 EnableAccum 0 0 EnableSpmWithAccumMode 1 1 EnableSPPMode 2 2 AutoResetPerfmonDisable 3 3 SwaAutoResetPerfmonDisable 4 4 AutoAccumEn 5 5 SwaAutoAccumEn 6 6 AutoSpmEn 7 7 SwaAutoSpmEn 8 8 Globals_LoadOverride 9 9 Globals_SwaLoadOverride 10 10 SE0_LoadOverride 11 11 SE0_SwaLoadOverride 12 12 SE1_LoadOverride 13 13 SE1_SwaLoadOverride 14 14 SE2_LoadOverride 15 15 SE2_SwaLoadOverride 16 16 SE3_LoadOverride 17 17 SE3_SwaLoadOverride 18 18 mmRLC_SPM_ACCUM_THRESHOLD 0 0x3c9c 1 0 1 Threshold 0 15 mmRLC_SPM_ACCUM_SAMPLES_REQUESTED 0 0x3c9d 1 0 1 SamplesRequested 0 7 mmRLC_SPM_ACCUM_DATARAM_WRCOUNT 0 0x3c9e 2 0 1 DataRamWrCount 0 18 RESERVED 19 31 mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE 0 0x3c9f 4 0 1 SE0_NUM_LINE 0 7 SE1_NUM_LINE 8 15 SE2_NUM_LINE 16 23 SE3_NUM_LINE 24 31 mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE 0 0x3ca0 3 0 1 PERFMON_SEGMENT_SIZE 0 7 GLOBAL_NUM_LINE 8 15 RESERVED 16 31 mmRLC_SPM_VIRT_CTRL 0 0x3ca1 1 0 1 PauseSpmSamplingRequest 0 0 mmRLC_SPM_PERFMON_SWA_SEGMENT_SIZE 0 0x3ca2 7 0 1 PERFMON_SEGMENT_SIZE 0 7 RESERVED1 8 10 GLOBAL_NUM_LINE 11 15 SE0_NUM_LINE 16 20 SE1_NUM_LINE 21 25 SE2_NUM_LINE 26 30 RESERVED 31 31 mmRLC_SPM_VIRT_STATUS 0 0x3ca3 1 0 1 SpmSamplingPaused 0 0 mmRLC_SPM_GFXCLOCK_HIGHCOUNT 0 0x3ca4 1 0 1 GFXCLOCK_HIGHCOUNT 0 31 mmRLC_SPM_GFXCLOCK_LOWCOUNT 0 0x3ca5 1 0 1 GFXCLOCK_LOWCOUNT 0 31 mmRLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE 0 0x3ca6 4 0 1 SE0_NUM_LINE 0 7 SE1_NUM_LINE 8 15 SE2_NUM_LINE 16 23 SE3_NUM_LINE 24 31 mmRLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET 0 0x3ca7 2 0 1 OFFSET 0 15 RESERVED 16 31 mmRLC_SPM_SE_MUXSEL_ADDR_OFFSET 0 0x3ca8 2 0 1 OFFSET 0 15 RESERVED 16 31 mmRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0 0x3ca9 2 0 1 addr 0 6 RESERVED 7 31 mmRLC_SPM_ACCUM_SWA_DATARAM_DATA 0 0x3caa 1 0 1 data 0 31 mmRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0 0x3cab 4 0 1 global_offset 0 7 spmwithaccum_se_offset 8 15 spmwithaccum_global_offset 16 23 RESERVED 24 31 mmRLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE 0 0x3cac 3 0 1 PERFMON_SEGMENT_SIZE 0 7 GLOBAL_NUM_LINE 8 15 RESERVED 16 31 mmRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0 0x3cad 3 0 1 spp_addr_region 0 7 swa_addr_region 8 15 RESERVED 16 31 mmRLC_PERFMON_CNTL 0 0x3cc0 2 0 1 PERFMON_STATE 0 2 PERFMON_SAMPLE_ENABLE 10 10 mmRLC_PERFCOUNTER0_SELECT 0 0x3cc1 1 0 1 PERFCOUNTER_SELECT 0 7 mmRLC_PERFCOUNTER1_SELECT 0 0x3cc2 1 0 1 PERFCOUNTER_SELECT 0 7 mmRLC_GPU_IOV_PERF_CNT_CNTL 0 0x3cc3 4 0 1 ENABLE 0 0 MODE_SELECT 1 1 RESET 2 2 RESERVED 3 31 mmRLC_GPU_IOV_PERF_CNT_WR_ADDR 0 0x3cc4 3 0 1 VFID 0 3 CNT_ID 4 5 RESERVED 6 31 mmRLC_GPU_IOV_PERF_CNT_WR_DATA 0 0x3cc5 1 0 1 DATA 0 31 mmRLC_GPU_IOV_PERF_CNT_RD_ADDR 0 0x3cc6 3 0 1 VFID 0 3 CNT_ID 4 5 RESERVED 6 31 mmRLC_GPU_IOV_PERF_CNT_RD_DATA 0 0x3cc7 1 0 1 DATA 0 31 mmRLC_PERFMON_CLK_CNTL 0 0x3ce4 1 0 1 PERFMON_CLOCK_STATE 0 0 mmRMI_PERFCOUNTER0_SELECT 0 0x3d00 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmRMI_PERFCOUNTER0_SELECT1 0 0x3d01 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 mmRMI_PERFCOUNTER1_SELECT 0 0x3d02 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 mmRMI_PERFCOUNTER2_SELECT 0 0x3d03 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmRMI_PERFCOUNTER2_SELECT1 0 0x3d04 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 mmRMI_PERFCOUNTER3_SELECT 0 0x3d05 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 mmRMI_PERF_COUNTER_CNTL 0 0x3d06 10 0 1 TRANS_BASED_PERF_EN_SEL 0 1 EVENT_BASED_PERF_EN_SEL 2 3 TC_PERF_EN_SEL 4 5 PERF_EVENT_WINDOW_MASK0 6 7 PERF_EVENT_WINDOW_MASK1 8 9 PERF_COUNTER_CID 10 13 PERF_COUNTER_VMID 14 18 PERF_COUNTER_BURST_LENGTH_THRESHOLD 19 24 PERF_SOFT_RESET 25 25 PERF_CNTR_SPM_SEL 26 26 mmGCR_PERFCOUNTER0_SELECT 0 0x3d60 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGCR_PERFCOUNTER0_SELECT1 0 0x3d61 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGCR_PERFCOUNTER1_SELECT 0 0x3d62 3 0 1 PERF_SEL 0 8 PERF_MODE 24 27 CNTL_MODE 28 31 mmUTCL1_PERFCOUNTER0_SELECT 0 0x3d63 2 0 1 PERF_SEL 0 9 COUNTER_MODE 28 31 mmUTCL1_PERFCOUNTER1_SELECT 0 0x3d64 2 0 1 PERF_SEL 0 9 COUNTER_MODE 28 31 mmPA_PH_PERFCOUNTER0_SELECT 0 0x3d80 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_PH_PERFCOUNTER0_SELECT1 0 0x3d81 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_PH_PERFCOUNTER1_SELECT 0 0x3d82 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_PH_PERFCOUNTER2_SELECT 0 0x3d83 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_PH_PERFCOUNTER3_SELECT 0 0x3d84 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmPA_PH_PERFCOUNTER4_SELECT 0 0x3d85 1 0 1 PERF_SEL 0 9 mmPA_PH_PERFCOUNTER5_SELECT 0 0x3d86 1 0 1 PERF_SEL 0 9 mmPA_PH_PERFCOUNTER6_SELECT 0 0x3d87 1 0 1 PERF_SEL 0 9 mmPA_PH_PERFCOUNTER7_SELECT 0 0x3d88 1 0 1 PERF_SEL 0 9 mmPA_PH_PERFCOUNTER1_SELECT1 0 0x3d90 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_PH_PERFCOUNTER2_SELECT1 0 0x3d91 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmPA_PH_PERFCOUNTER3_SELECT1 0 0x3d92 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGL1A_PERFCOUNTER0_SELECT 0 0x3dc0 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGL1A_PERFCOUNTER0_SELECT1 0 0x3dc1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmGL1A_PERFCOUNTER1_SELECT 0 0x3dc2 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL1A_PERFCOUNTER2_SELECT 0 0x3dc3 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGL1A_PERFCOUNTER3_SELECT 0 0x3dc4 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHA_PERFCOUNTER0_SELECT 0 0x3de0 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmCHA_PERFCOUNTER0_SELECT1 0 0x3de1 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmCHA_PERFCOUNTER1_SELECT 0 0x3de2 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHA_PERFCOUNTER2_SELECT 0 0x3de3 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmCHA_PERFCOUNTER3_SELECT 0 0x3de4 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmGUS_PERFCOUNTER2_SELECT 0 0x3e00 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGUS_PERFCOUNTER2_SELECT1 0 0x3e01 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGUS_PERFCOUNTER2_MODE 0 0x3e02 8 0 1 COMPARE_MODE0 0 1 COMPARE_MODE1 2 3 COMPARE_MODE2 4 5 COMPARE_MODE3 6 7 COMPARE_VALUE0 8 11 COMPARE_VALUE1 12 15 COMPARE_VALUE2 16 19 COMPARE_VALUE3 20 23 mmGUS_PERFCOUNTER0_CFG 0 0x3e03 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGUS_PERFCOUNTER1_CFG 0 0x3e04 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGUS_PERFCOUNTER_RSLT_CNTL 0 0x3e05 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmGCMC_VM_L2_PERFCOUNTER0_CFG 0 0x3d2c 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER1_CFG 0 0x3d2d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER2_CFG 0 0x3d2e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER3_CFG 0 0x3d2f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER4_CFG 0 0x3d30 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER5_CFG 0 0x3d31 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER6_CFG 0 0x3d32 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER7_CFG 0 0x3d33 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x3d34 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmGCUTCL2_PERFCOUNTER0_CFG 0 0x3d35 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCUTCL2_PERFCOUNTER1_CFG 0 0x3d36 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCUTCL2_PERFCOUNTER2_CFG 0 0x3d37 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCUTCL2_PERFCOUNTER3_CFG 0 0x3d38 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmGCUTCL2_PERFCOUNTER_RSLT_CNTL 0 0x3d39 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmGCVML2_PERFCOUNTER2_0_SELECT 0 0x3d3c 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGCVML2_PERFCOUNTER2_1_SELECT 0 0x3d3d 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmGCVML2_PERFCOUNTER2_0_SELECT1 0 0x3d3e 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGCVML2_PERFCOUNTER2_1_SELECT1 0 0x3d3f 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGCVML2_PERFCOUNTER2_0_MODE 0 0x3d40 8 0 1 COMPARE_MODE0 0 1 COMPARE_MODE1 2 3 COMPARE_MODE2 4 5 COMPARE_MODE3 6 7 COMPARE_VALUE0 8 11 COMPARE_VALUE1 12 15 COMPARE_VALUE2 16 19 COMPARE_VALUE3 20 23 mmGCVML2_PERFCOUNTER2_1_MODE 0 0x3d41 8 0 1 COMPARE_MODE0 0 1 COMPARE_MODE1 2 3 COMPARE_MODE2 4 5 COMPARE_MODE3 6 7 COMPARE_VALUE0 8 11 COMPARE_VALUE1 12 15 COMPARE_VALUE2 16 19 COMPARE_VALUE3 20 23 mmSDMA0_PERFCNT_PERFCOUNTER0_CFG 0 0x3e20 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA0_PERFCNT_PERFCOUNTER1_CFG 0 0x3e21 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x3e22 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmSDMA0_PERFCNT_MISC_CNTL 0 0x3e23 1 0 1 CMD_OP 0 15 mmSDMA0_PERFCOUNTER0_SELECT 0 0x3e24 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA0_PERFCOUNTER0_SELECT1 0 0x3e25 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA0_PERFCOUNTER1_SELECT 0 0x3e26 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA0_PERFCOUNTER1_SELECT1 0 0x3e27 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA1_PERFCNT_PERFCOUNTER0_CFG 0 0x3e2c 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA1_PERFCNT_PERFCOUNTER1_CFG 0 0x3e2d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x3e2e 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmSDMA1_PERFCNT_MISC_CNTL 0 0x3e2f 1 0 1 CMD_OP 0 15 mmSDMA1_PERFCOUNTER0_SELECT 0 0x3e30 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA1_PERFCOUNTER0_SELECT1 0 0x3e31 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA1_PERFCOUNTER1_SELECT 0 0x3e32 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA1_PERFCOUNTER1_SELECT1 0 0x3e33 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA2_PERFCNT_PERFCOUNTER0_CFG 0 0x3e38 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA2_PERFCNT_PERFCOUNTER1_CFG 0 0x3e39 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x3e3a 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmSDMA2_PERFCNT_MISC_CNTL 0 0x3e3b 1 0 1 CMD_OP 0 15 mmSDMA2_PERFCOUNTER0_SELECT 0 0x3e3c 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA2_PERFCOUNTER0_SELECT1 0 0x3e3d 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA2_PERFCOUNTER1_SELECT 0 0x3e3e 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA2_PERFCOUNTER1_SELECT1 0 0x3e3f 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA3_PERFCNT_PERFCOUNTER0_CFG 0 0x3e44 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA3_PERFCNT_PERFCOUNTER1_CFG 0 0x3e45 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x3e46 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmSDMA3_PERFCNT_MISC_CNTL 0 0x3e47 1 0 1 CMD_OP 0 15 mmSDMA3_PERFCOUNTER0_SELECT 0 0x3e48 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA3_PERFCOUNTER0_SELECT1 0 0x3e49 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmSDMA3_PERFCOUNTER1_SELECT 0 0x3e4a 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmSDMA3_PERFCOUNTER1_SELECT1 0 0x3e4b 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmGRTAVFS_RTAVFS_REG_ADDR 0 0x4b00 1 0 1 RTAVFSADDR 0 9 mmRTAVFS_RTAVFS_REG_ADDR 0 0x4b00 1 0 1 RTAVFSADDR 0 9 mmGRTAVFS_RTAVFS_WR_DATA 0 0x4b01 1 0 1 RTAVFSDATA 0 31 mmRTAVFS_RTAVFS_WR_DATA 0 0x4b01 1 0 1 RTAVFSDATA 0 31 mmGRTAVFS_GENERAL_0 0 0x4b02 1 0 1 DATA 0 31 mmGRTAVFS_RTAVFS_RD_DATA 0 0x4b03 1 0 1 RTAVFSDATA 0 31 mmGRTAVFS_RTAVFS_REG_CTRL 0 0x4b04 2 0 1 SET_WR_EN 0 0 SET_RD_EN 1 1 mmGRTAVFS_RTAVFS_REG_STATUS 0 0x4b05 2 0 1 RTAVFS_WR_ACK 0 0 RTAVFS_RD_DATA_VALID 1 1 mmGRTAVFS_TARG_FREQ 0 0x4b06 3 0 1 TARGET_FREQUENCY 0 15 REQUEST 16 16 RESERVED 17 31 mmGRTAVFS_TARG_VOLT 0 0x4b07 3 0 1 TARGET_VOLTAGE 0 9 VALID 10 10 RESERVED 11 31 mmGRTAVFS_SOFT_RESET 0 0x4b0f 2 0 1 RESETN_OVERRIDE 0 0 RESERVED 1 31 mmGRTAVFS_PSM_CNTL 0 0x4b10 3 0 1 PSM_COUNT 0 13 PSM_SAMPLE_EN 14 14 RESERVED 15 31 mmGRTAVFS_CLK_CNTL 0 0x4b11 3 0 1 GRTAVFS_MUX_CLK_SEL 0 0 FORCE_GRTAVFS_CLK_SEL 1 1 RESERVED 2 31 mmRLC_CNTL 0 0x4c00 5 0 1 RLC_ENABLE_F32 0 0 FORCE_RETRY 1 1 READ_CACHE_DISABLE 2 2 RLC_STEP_F32 3 3 RESERVED 4 31 mmRLC_F32_UCODE_VERSION 0 0x4c03 3 0 1 THREAD0_VERSION 0 9 THREAD1_VERSION 10 19 THREAD2_VERSION 20 29 mmRLC_STAT 0 0x4c04 9 0 1 RLC_BUSY 0 0 RLC_SRM_BUSY 1 1 RLC_GPM_BUSY 2 2 RLC_SPM_BUSY 3 3 MC_BUSY 4 4 RLC_THREAD_0_BUSY 5 5 RLC_THREAD_1_BUSY 6 6 RLC_THREAD_2_BUSY 7 7 RESERVED 8 31 mmRLC_MEM_SLP_CNTL 0 0x4c06 7 0 1 RLC_MEM_LS_EN 0 0 RLC_MEM_DS_EN 1 1 RESERVED 2 6 RLC_LS_DS_BUSY_OVERRIDE 7 7 RLC_MEM_LS_ON_DELAY 8 15 RLC_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 mmSMU_RLC_RESPONSE 0 0x4c07 1 0 1 RESP 0 31 mmRLC_RLCV_SAFE_MODE 0 0x4c08 5 0 1 CMD 0 0 MESSAGE 1 4 RESERVED1 5 7 RESPONSE 8 11 RESERVED 12 31 mmRLC_SMU_SAFE_MODE 0 0x4c09 5 0 1 CMD 0 0 MESSAGE 1 4 RESERVED1 5 7 RESPONSE 8 11 RESERVED 12 31 mmRLC_RLCV_COMMAND 0 0x4c0a 2 0 1 CMD 0 3 RESERVED 4 31 mmRLC_REFCLOCK_TIMESTAMP_LSB 0 0x4c0c 1 0 1 TIMESTAMP_LSB 0 31 mmRLC_REFCLOCK_TIMESTAMP_MSB 0 0x4c0d 1 0 1 TIMESTAMP_MSB 0 31 mmRLC_GPM_TIMER_INT_0 0 0x4c0e 1 0 1 TIMER 0 31 mmRLC_GPM_TIMER_INT_1 0 0x4c0f 1 0 1 TIMER 0 31 mmRLC_GPM_TIMER_INT_2 0 0x4c10 1 0 1 TIMER 0 31 mmRLC_GPM_TIMER_CTRL 0 0x4c11 16 0 1 TIMER_0_EN 0 0 TIMER_1_EN 1 1 TIMER_2_EN 2 2 TIMER_3_EN 3 3 TIMER_0_AUTO_REARM 4 4 TIMER_1_AUTO_REARM 5 5 TIMER_2_AUTO_REARM 6 6 TIMER_3_AUTO_REARM 7 7 TIMER_0_INT_CLEAR 8 8 TIMER_1_INT_CLEAR 9 9 TIMER_2_INT_CLEAR 10 10 TIMER_3_INT_CLEAR 11 11 TIMER_4_EN 12 12 TIMER_4_AUTO_REARM 13 13 TIMER_4_INT_CLEAR 14 14 RESERVED 15 31 mmRLC_LB_CNTR_MAX_1 0 0x4c12 1 0 1 LB_CNTR_MAX 0 31 mmRLC_GPM_TIMER_STAT 0 0x4c13 16 0 1 TIMER_0_STAT 0 0 TIMER_1_STAT 1 1 TIMER_2_STAT 2 2 TIMER_3_STAT 3 3 TIMER_4_STAT 4 4 TIMER_0_ENABLE_SYNC 8 8 TIMER_1_ENABLE_SYNC 9 9 TIMER_2_ENABLE_SYNC 10 10 TIMER_3_ENABLE_SYNC 11 11 TIMER_0_AUTO_REARM_SYNC 12 12 TIMER_1_AUTO_REARM_SYNC 13 13 TIMER_2_AUTO_REARM_SYNC 14 14 TIMER_3_AUTO_REARM_SYNC 15 15 TIMER_4_ENABLE_SYNC 16 16 TIMER_4_AUTO_REARM_SYNC 17 17 RESERVED 18 31 mmRLC_GPM_TIMER_INT_3 0 0x4c15 1 0 1 TIMER 0 31 mmRLC_GPM_LEGACY_INT_STAT 0 0x4c16 3 0 1 SPP_PVT_INT_CHANGED 0 0 CP_RLC_STAT_INVAL_PEND_CHANGED 1 1 RLC_EOF_INT_CHANGED 2 2 mmRLC_GPM_LEGACY_INT_CLEAR 0 0x4c17 3 0 1 SPP_PVT_INT_CHANGED 0 0 CP_RLC_STAT_INVAL_PEND_CHANGED 1 1 RLC_EOF_INT_CHANGED 2 2 mmRLC_INT_STAT 0 0x4c18 3 0 1 LAST_CP_RLC_INT_ID 0 7 CP_RLC_INT_PENDING 8 8 RESERVED 9 31 mmRLC_LB_CNTL 0 0x4c19 5 0 1 LOAD_BALANCE_ENABLE 0 0 LB_CNT_CP_BUSY 1 1 LB_CNT_SPIM_ACTIVE 2 2 LB_CNT_REG_INC 3 3 RESERVED 4 31 mmRLC_MGCG_CTRL 0 0x4c1a 8 0 1 MGCG_EN 0 0 SILICON_EN 1 1 SIMULATION_EN 2 2 ON_DELAY 3 6 OFF_HYSTERESIS 7 14 GC_CAC_MGCG_CLK_CNTL 15 15 SE_CAC_MGCG_CLK_CNTL 16 16 SPARE 17 31 mmRLC_LB_CNTR_INIT_1 0 0x4c1b 1 0 1 LB_CNTR_INIT 0 31 mmRLC_LB_CNTR_1 0 0x4c1c 1 0 1 RLC_LOAD_BALANCE_CNTR 0 31 mmRLC_JUMP_TABLE_RESTORE 0 0x4c1e 1 0 1 ADDR 0 31 mmRLC_PG_DELAY_2 0 0x4c1f 3 0 1 SERDES_TIMEOUT_VALUE 0 7 SERDES_CMD_DELAY 8 15 PERWGP_TIMEOUT_VALUE 16 31 mmRLC_GPU_CLOCK_COUNT_LSB 0 0x4c24 1 0 1 GPU_CLOCKS_LSB 0 31 mmRLC_GPU_CLOCK_COUNT_MSB 0 0x4c25 1 0 1 GPU_CLOCKS_MSB 0 31 mmRLC_CAPTURE_GPU_CLOCK_COUNT 0 0x4c26 2 0 1 CAPTURE 0 0 RESERVED 1 31 mmRLC_UCODE_CNTL 0 0x4c27 1 0 1 RLC_UCODE_FLAGS 0 31 mmRLC_GPM_THREAD_RESET 0 0x4c28 5 0 1 THREAD0_RESET 0 0 THREAD1_RESET 1 1 THREAD2_RESET 2 2 THREAD3_RESET 3 3 RESERVED 4 31 mmRLC_GPM_CP_DMA_COMPLETE_T0 0 0x4c29 2 0 1 DATA 0 0 RESERVED 1 31 mmRLC_GPM_CP_DMA_COMPLETE_T1 0 0x4c2a 2 0 1 DATA 0 0 RESERVED 1 31 mmRLC_LB_CNTR_INIT_2 0 0x4c2b 1 0 1 LB_CNTR_INIT 0 31 mmRLC_LB_CNTR_MAX_2 0 0x4c2c 1 0 1 LB_CNTR_MAX 0 31 mmRLC_LB_CONFIG_5 0 0x4c2e 1 0 1 DATA 0 31 mmRLC_GPM_TIMER_INT_4 0 0x4c2f 1 0 1 TIMER 0 31 mmRLC_CLK_COUNT_GFXCLK_LSB 0 0x4c30 1 0 1 COUNTER 0 31 mmRLC_CLK_COUNT_GFXCLK_MSB 0 0x4c31 1 0 1 COUNTER 0 31 mmRLC_CLK_COUNT_REFCLK_LSB 0 0x4c32 1 0 1 COUNTER 0 31 mmRLC_CLK_COUNT_REFCLK_MSB 0 0x4c33 1 0 1 COUNTER 0 31 mmRLC_CLK_COUNT_CTRL 0 0x4c34 6 0 1 GFXCLK_RUN 0 0 GFXCLK_RESET 1 1 GFXCLK_SAMPLE 2 2 REFCLK_RUN 3 3 REFCLK_RESET 4 4 REFCLK_SAMPLE 5 5 mmRLC_CLK_COUNT_STAT 0 0x4c35 6 0 1 GFXCLK_VALID 0 0 REFCLK_VALID 1 1 REFCLK_RUN_RESYNC 2 2 REFCLK_RESET_RESYNC 3 3 REFCLK_SAMPLE_RESYNC 4 4 RESERVED 5 31 mmRLC_RLCG_DOORBELL_CNTL 0 0x4c36 6 0 1 DOORBELL_0_MODE 0 1 DOORBELL_1_MODE 2 3 DOORBELL_2_MODE 4 5 DOORBELL_3_MODE 6 7 DOORBELL_ID 16 20 DOORBELL_ID_EN 21 21 mmRLC_RLCG_DOORBELL_STAT 0 0x4c37 4 0 1 DOORBELL_0_VALID 0 0 DOORBELL_1_VALID 1 1 DOORBELL_2_VALID 2 2 DOORBELL_3_VALID 3 3 mmRLC_RLCG_DOORBELL_0_DATA_LO 0 0x4c38 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_0_DATA_HI 0 0x4c39 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_1_DATA_LO 0 0x4c3a 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_1_DATA_HI 0 0x4c3b 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_2_DATA_LO 0 0x4c3c 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_2_DATA_HI 0 0x4c3d 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_3_DATA_LO 0 0x4c3e 1 0 1 DATA 0 31 mmRLC_RLCG_DOORBELL_3_DATA_HI 0 0x4c3f 1 0 1 DATA 0 31 mmRLC_GPU_CLOCK_32_RES_SEL 0 0x4c41 2 0 1 RES_SEL 0 5 RESERVED 6 31 mmRLC_GPU_CLOCK_32 0 0x4c42 1 0 1 GPU_CLOCK_32 0 31 mmRLC_PG_CNTL 0 0x4c43 15 0 1 GFX_POWER_GATING_ENABLE 0 0 GFX_POWER_GATING_SRC 1 1 DYN_PER_WGP_PG_ENABLE 2 2 STATIC_PER_WGP_PG_ENABLE 3 3 GFX_PIPELINE_PG_ENABLE 4 4 RESERVED 5 13 PG_OVERRIDE 14 14 CP_PG_DISABLE 15 15 CHUB_HANDSHAKE_ENABLE 16 16 SMU_CLK_SLOWDOWN_ON_PU_ENABLE 17 17 SMU_CLK_SLOWDOWN_ON_PD_ENABLE 18 18 SMU_HANDSHAKE_ENABLE 19 19 RESERVED1 20 20 Ultra_Low_Voltage_Enable 21 21 RESERVED2 22 23 mmRLC_GPM_THREAD_PRIORITY 0 0x4c44 4 0 1 THREAD0_PRIORITY 0 7 THREAD1_PRIORITY 8 15 THREAD2_PRIORITY 16 23 THREAD3_PRIORITY 24 31 mmRLC_GPM_THREAD_ENABLE 0 0x4c45 5 0 1 THREAD0_ENABLE 0 0 THREAD1_ENABLE 1 1 THREAD2_ENABLE 2 2 THREAD3_ENABLE 3 3 RESERVED 4 31 mmRLC_RLCG_DOORBELL_RANGE 0 0x4c47 4 0 1 LOWER_ADDR_RESERVED 0 1 LOWER_ADDR 2 11 UPPER_ADDR_RESERVED 16 17 UPPER_ADDR 18 27 mmRLC_CGTT_MGCG_OVERRIDE 0 0x4c48 12 0 1 RESERVED_0 0 0 RLC_CGTT_SCLK_OVERRIDE 1 1 GFXIP_MGCG_OVERRIDE 2 2 GFXIP_CGCG_OVERRIDE 3 3 GFXIP_CGLS_OVERRIDE 4 4 GRBM_CGTT_SCLK_OVERRIDE 5 5 GFXIP_MGLS_OVERRIDE 6 6 GFXIP_GFX3D_CG_OVERRIDE 7 7 GFXIP_FGCG_OVERRIDE 8 8 RESERVED_15_9 9 15 ENABLE_CGTS_LEGACY 16 16 RESERVED_31_17 17 31 mmRLC_CGCG_CGLS_CTRL 0 0x4c49 8 0 1 CGCG_EN 0 0 CGLS_EN 1 1 CGLS_REP_COMPANSAT_DELAY 2 7 CGCG_GFX_IDLE_THRESHOLD 8 26 CGCG_CONTROLLER 27 27 CGCG_REG_CTRL 28 28 SLEEP_MODE 29 30 SIM_SILICON_EN 31 31 mmRLC_CGCG_RAMP_CTRL 0 0x4c4a 6 0 1 DOWN_DIV_START_UNIT 0 3 DOWN_DIV_STEP_UNIT 4 7 UP_DIV_START_UNIT 8 11 UP_DIV_STEP_UNIT 12 15 STEP_DELAY_CNT 16 27 STEP_DELAY_UNIT 28 31 mmRLC_DYN_PG_STATUS 0 0x4c4b 1 0 1 PG_STATUS_WGP_MASK 0 31 mmRLC_DYN_PG_REQUEST 0 0x4c4c 1 0 1 PG_REQUEST_WGP_MASK 0 31 mmRLC_PG_DELAY 0 0x4c4d 4 0 1 POWER_UP_DELAY 0 7 POWER_DOWN_DELAY 8 15 CMD_PROPAGATE_DELAY 16 23 MEM_SLEEP_DELAY 24 31 mmRLC_WGP_STATUS 0 0x4c4e 1 0 1 WORK_PENDING 0 31 mmRLC_LB_INIT_WGP_MASK 0 0x4c4f 1 0 1 INIT_WGP_MASK 0 31 mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK 0 0x4c50 1 0 1 ALWAYS_ACTIVE_WGP_MASK 0 31 mmRLC_LB_PARAMS 0 0x4c51 4 0 1 SKIP_L2_CHECK 0 0 FIFO_SAMPLES 1 7 PG_IDLE_SAMPLES 8 15 PG_IDLE_SAMPLE_INTERVAL 16 31 mmRLC_LB_DELAY 0 0x4c52 4 0 1 WGP_IDLE_DELAY 0 7 LBPW_INNER_LOOP_DELAY 8 15 LBPW_OUTER_LOOP_DELAY 16 23 SPARE 24 31 mmRLC_PG_ALWAYS_ON_WGP_MASK 0 0x4c53 1 0 1 AON_WGP_MASK 0 31 mmRLC_MAX_PG_WGP 0 0x4c54 2 0 1 MAX_POWERED_UP_WGP 0 7 SPARE 8 31 mmRLC_AUTO_PG_CTRL 0 0x4c55 5 0 1 AUTO_PG_EN 0 0 AUTO_GRBM_REG_SAVE_ON_IDLE_EN 1 1 AUTO_WAKE_UP_EN 2 2 GRBM_REG_SAVE_GFX_IDLE_THRESHOLD 3 18 PG_AFTER_GRBM_REG_SAVE_THRESHOLD 19 31 mmRLC_SMU_GRBM_REG_SAVE_CTRL 0 0x4c56 2 0 1 START_GRBM_REG_SAVE 0 0 SPARE 1 31 mmRLC_SERDES_RD_INDEX 0 0x4c59 2 0 1 DATA_REG_ID 0 1 SPARE 2 31 mmRLC_SERDES_RD_DATA_0 0 0x4c5a 1 0 1 DATA 0 31 mmRLC_SERDES_RD_DATA_1 0 0x4c5b 1 0 1 DATA 0 31 mmRLC_SERDES_RD_DATA_2 0 0x4c5c 1 0 1 DATA 0 31 mmRLC_SERDES_RD_DATA_3 0 0x4c5d 1 0 1 DATA 0 31 mmRLC_SERDES_MASK 0 0x4c5e 8 0 1 GC_CENTER_HUB_0 0 0 GC_CENTER_HUB_1 1 1 RESERVED 2 15 GC_SE_0 16 16 GC_SE_1 17 17 GC_SE_2 18 18 GC_SE_3 19 19 RESERVED_1 20 31 mmRLC_SERDES_CTRL 0 0x4c5f 5 0 1 BPM_BROADCAST 0 0 BPM_REG_WRITE 1 1 BPM_LONG_CMD 2 2 BPM_ADDR 3 15 REG_ADDR 16 23 mmRLC_SERDES_DATA 0 0x4c60 1 0 1 DATA 0 31 mmRLC_SERDES_BUSY 0 0x4c61 10 0 1 GC_CENTER_HUB_0 0 0 GC_CENTER_HUB_1 1 1 RESERVED 2 15 GC_SE_0 16 16 GC_SE_1 17 17 GC_SE_2 18 18 GC_SE_3 19 19 RESERVED_29_20 20 29 RD_FIFO_NOT_EMPTY 30 30 RD_PENDING 31 31 mmRLC_GPM_GENERAL_0 0 0x4c63 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_1 0 0x4c64 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_2 0 0x4c65 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_3 0 0x4c66 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_4 0 0x4c67 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_5 0 0x4c68 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_6 0 0x4c69 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_7 0 0x4c6a 1 0 1 DATA 0 31 mmRLC_STATIC_PG_STATUS 0 0x4c6e 1 0 1 PG_STATUS_WGP_MASK 0 31 mmRLC_SPM_INT_INFO_1 0 0x4c6f 1 0 1 INTERRUPT_INFO_1 0 31 mmRLC_SPM_INT_INFO_2 0 0x4c70 3 0 1 INTERRUPT_INFO_2 0 15 INTERRUPT_ID 16 23 RESERVED 24 31 mmRLC_SPM_MC_CNTL 0 0x4c71 14 0 1 RLC_SPM_VMID 0 3 RLC_SPM_POLICY 4 5 RLC_SPM_PERF_CNTR 6 6 RLC_SPM_FED 7 7 RLC_SPM_MTYPE_OVER 8 8 RLC_SPM_MTYPE 9 11 RLC_SPM_BC 12 12 RLC_SPM_RO 13 13 RLC_SPM_VOL 14 14 RLC_SPM_NOFILL 15 15 RESERVED_3 16 17 RLC_SPM_LLC_NOALLOC 18 18 RLC_SPM_LLC_NOALLOC_OVER 19 19 RESERVED 20 31 mmRLC_SPM_INT_CNTL 0 0x4c72 2 0 1 RLC_SPM_INT_CNTL 0 0 RESERVED 1 31 mmRLC_SPM_INT_STATUS 0 0x4c73 2 0 1 RLC_SPM_INT_STATUS 0 0 RESERVED 1 31 mmRLC_SMU_MESSAGE 0 0x4c76 1 0 1 CMD 0 31 mmRLC_GPM_LOG_SIZE 0 0x4c77 1 0 1 SIZE 0 31 mmRLC_PG_DELAY_3 0 0x4c78 2 0 1 CGCG_ACTIVE_BEFORE_CGPG 0 7 RESERVED 8 31 mmRLC_GPR_REG1 0 0x4c79 1 0 1 DATA 0 31 mmRLC_GPR_REG2 0 0x4c7a 1 0 1 DATA 0 31 mmRLC_GPM_LOG_CONT 0 0x4c7b 1 0 1 CONT 0 31 mmRLC_GPM_INT_DISABLE_TH0 0 0x4c7c 1 0 1 DISABLE_INT 0 31 mmRLC_GPM_LEGACY_INT_DISABLE 0 0x4c7d 3 0 1 SPP_PVT_INT_CHANGED 0 0 CP_RLC_STAT_INVAL_PEND_CHANGED 1 1 RLC_EOF_INT_CHANGED 2 2 mmRLC_GPM_INT_FORCE_TH0 0 0x4c7e 1 0 1 FORCE_INT 0 31 mmRLC_SRM_CNTL 0 0x4c80 3 0 1 SRM_ENABLE 0 0 AUTO_INCR_ADDR 1 1 RESERVED 2 31 mmRLC_SRM_GPM_COMMAND 0 0x4c87 7 0 1 OP 0 0 INDEX_CNTL 1 1 INDEX_CNTL_NUM 2 4 SIZE 5 16 START_OFFSET 17 28 RESERVED1 29 30 DEST_MEMORY 31 31 mmRLC_SRM_GPM_COMMAND_STATUS 0 0x4c88 3 0 1 FIFO_EMPTY 0 0 FIFO_FULL 1 1 RESERVED 2 31 mmRLC_SRM_RLCV_COMMAND 0 0x4c89 6 0 1 OP 0 0 RESERVED 1 3 SIZE 4 15 START_OFFSET 16 27 RESERVED1 28 30 DEST_MEMORY 31 31 mmRLC_SRM_RLCV_COMMAND_STATUS 0 0x4c8a 3 0 1 FIFO_EMPTY 0 0 FIFO_FULL 1 1 RESERVED 2 31 mmRLC_SRM_INDEX_CNTL_ADDR_0 0 0x4c8b 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_1 0 0x4c8c 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_2 0 0x4c8d 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_3 0 0x4c8e 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_4 0 0x4c8f 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_5 0 0x4c90 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_6 0 0x4c91 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_ADDR_7 0 0x4c92 2 0 1 ADDRESS 0 15 RESERVED 16 31 mmRLC_SRM_INDEX_CNTL_DATA_0 0 0x4c93 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_1 0 0x4c94 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_2 0 0x4c95 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_3 0 0x4c96 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_4 0 0x4c97 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_5 0 0x4c98 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_6 0 0x4c99 1 0 1 DATA 0 31 mmRLC_SRM_INDEX_CNTL_DATA_7 0 0x4c9a 1 0 1 DATA 0 31 mmRLC_SRM_STAT 0 0x4c9b 3 0 1 SRM_BUSY 0 0 SRM_BUSY_DELAY 1 1 RESERVED 2 31 mmRLC_SRM_GPM_ABORT 0 0x4c9c 2 0 1 ABORT 0 0 RESERVED 1 31 mmRLC_SPARE_INT_2 0 0x4c9d 3 0 1 DATA 0 29 PROCESSING 30 30 COMPLETE 31 31 mmRLC_RLCV_SPARE_INT_1 0 0x4c9e 2 0 1 INTERRUPT 0 0 RESERVED 1 31 mmRLC_PACE_SPARE_INT_1 0 0x4c9f 2 0 1 INTERRUPT 0 0 RESERVED 1 31 mmRLC_SAFE_MODE 0 0x4ca0 5 0 1 CMD 0 0 MESSAGE 1 4 RESERVED1 5 7 RESPONSE 8 11 RESERVED 12 31 mmRLC_CP_SCHEDULERS 0 0x4ca1 4 0 1 scheduler0 0 7 scheduler1 8 15 scheduler2 16 23 scheduler3 24 31 mmRLC_CSIB_ADDR_LO 0 0x4ca2 1 0 1 ADDRESS 0 31 mmRLC_CSIB_ADDR_HI 0 0x4ca3 1 0 1 ADDRESS 0 15 mmRLC_CSIB_LENGTH 0 0x4ca4 1 0 1 LENGTH 0 31 mmRLC_SPARE_INT_0 0 0x4ca5 3 0 1 DATA 0 29 PROCESSING 30 30 COMPLETE 31 31 mmRLC_CP_EOF_INT_CNT 0 0x4ca6 1 0 1 CNT 0 31 mmRLC_CP_EOF_INT 0 0x4ca7 2 0 1 INTERRUPT 0 0 RESERVED 1 31 mmRLC_SMU_COMMAND 0 0x4ca9 1 0 1 CMD 0 31 mmRLC_SMU_ARGUMENT_1 0 0x4cab 1 0 1 ARG 0 31 mmRLC_SMU_ARGUMENT_2 0 0x4cac 1 0 1 ARG 0 31 mmRLC_GPM_GENERAL_8 0 0x4cad 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_9 0 0x4cae 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_10 0 0x4caf 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_11 0 0x4cb0 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_12 0 0x4cb1 1 0 1 DATA 0 31 mmRLC_GPM_UTCL1_CNTL_0 0 0x4cb2 7 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 RESERVED 30 31 mmRLC_GPM_UTCL1_CNTL_1 0 0x4cb3 7 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 RESERVED 30 31 mmRLC_GPM_UTCL1_CNTL_2 0 0x4cb4 7 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 RESERVED 30 31 mmRLC_SPM_UTCL1_CNTL 0 0x4cb5 7 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 RESERVED 30 31 mmRLC_UTCL1_STATUS_2 0 0x4cb6 11 0 1 GPM_TH0_UTCL1_BUSY 0 0 GPM_TH1_UTCL1_BUSY 1 1 GPM_TH2_UTCL1_BUSY 2 2 SPM_UTCL1_BUSY 3 3 PREWALKER_UTCL1_BUSY 4 4 GPM_TH0_UTCL1_StallOnTrans 5 5 GPM_TH1_UTCL1_StallOnTrans 6 6 GPM_TH2_UTCL1_StallOnTrans 7 7 SPM_UTCL1_StallOnTrans 8 8 PREWALKER_UTCL1_StallOnTrans 9 9 RESERVED 10 31 mmRLC_LB_CONFIG_2 0 0x4cb8 1 0 1 DATA 0 31 mmRLC_LB_CONFIG_3 0 0x4cb9 1 0 1 DATA 0 31 mmRLC_LB_CONFIG_4 0 0x4cba 1 0 1 DATA 0 31 mmRLC_SPM_UTCL1_ERROR_1 0 0x4cbc 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 mmRLC_SPM_UTCL1_ERROR_2 0 0x4cbd 1 0 1 Translated_ReqErrorAddr_LSB 0 31 mmRLC_GPM_UTCL1_TH0_ERROR_1 0 0x4cbe 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 mmRLC_LB_CONFIG_1 0 0x4cbf 1 0 1 DATA 0 31 mmRLC_GPM_UTCL1_TH0_ERROR_2 0 0x4cc0 1 0 1 Translated_ReqErrorAddr_LSB 0 31 mmRLC_GPM_UTCL1_TH1_ERROR_1 0 0x4cc1 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 mmRLC_GPM_UTCL1_TH1_ERROR_2 0 0x4cc2 1 0 1 Translated_ReqErrorAddr_LSB 0 31 mmRLC_GPM_UTCL1_TH2_ERROR_1 0 0x4cc3 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 mmRLC_GPM_UTCL1_TH2_ERROR_2 0 0x4cc4 1 0 1 Translated_ReqErrorAddr_LSB 0 31 mmRLC_CGCG_CGLS_CTRL_3D 0 0x4cc5 8 0 1 CGCG_EN 0 0 CGLS_EN 1 1 CGLS_REP_COMPANSAT_DELAY 2 7 CGCG_GFX_IDLE_THRESHOLD 8 26 CGCG_CONTROLLER 27 27 CGCG_REG_CTRL 28 28 SLEEP_MODE 29 30 SIM_SILICON_EN 31 31 mmRLC_CGCG_RAMP_CTRL_3D 0 0x4cc6 6 0 1 DOWN_DIV_START_UNIT 0 3 DOWN_DIV_STEP_UNIT 4 7 UP_DIV_START_UNIT 8 11 UP_DIV_STEP_UNIT 12 15 STEP_DELAY_CNT 16 27 STEP_DELAY_UNIT 28 31 mmRLC_SEMAPHORE_0 0 0x4cc7 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_SEMAPHORE_1 0 0x4cc8 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_PACE_INT_STAT 0 0x4ccc 1 0 1 STATUS 0 31 mmRLC_PREWALKER_UTCL1_CNTL 0 0x4ccd 7 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 RESERVED 30 31 mmRLC_PREWALKER_UTCL1_TRIG 0 0x4cce 8 0 1 VALID 0 0 VMID 1 4 PRIME_MODE 5 5 READ_PERM 6 6 WRITE_PERM 7 7 EXEC_PERM 8 8 RESERVED 9 30 READY 31 31 mmRLC_PREWALKER_UTCL1_ADDR_LSB 0 0x4ccf 1 0 1 ADDR_LSB 0 31 mmRLC_PREWALKER_UTCL1_ADDR_MSB 0 0x4cd0 1 0 1 ADDR_MSB 0 15 mmRLC_PREWALKER_UTCL1_SIZE_LSB 0 0x4cd1 1 0 1 SIZE_LSB 0 31 mmRLC_PREWALKER_UTCL1_SIZE_MSB 0 0x4cd2 1 0 1 SIZE_MSB 0 1 mmRLC_UTCL1_STATUS 0 0x4cd4 10 0 1 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 RESERVED 3 7 FAULT_UTCL1ID 8 13 RESERVED_1 14 15 RETRY_UTCL1ID 16 21 RESERVED_2 22 23 PRT_UTCL1ID 24 29 RESERVED_3 30 31 mmRLC_R2I_CNTL_0 0 0x4cd5 1 0 1 Data 0 31 mmRLC_R2I_CNTL_1 0 0x4cd6 1 0 1 Data 0 31 mmRLC_R2I_CNTL_2 0 0x4cd7 1 0 1 Data 0 31 mmRLC_R2I_CNTL_3 0 0x4cd8 1 0 1 Data 0 31 mmRLC_LB_WGP_STAT 0 0x4cda 2 0 1 MAX_WGP 0 15 ON_WGP 16 31 mmRLC_GPM_INT_STAT_TH0 0 0x4cdc 1 0 1 STATUS 0 31 mmRLC_GPM_GENERAL_13 0 0x4cdd 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_14 0 0x4cde 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_15 0 0x4cdf 1 0 1 DATA 0 31 mmRLC_SPARE_INT_1 0 0x4ce0 3 0 1 DATA 0 29 PROCESSING 30 30 COMPLETE 31 31 mmRLC_SEMAPHORE_2 0 0x4ce3 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_SEMAPHORE_3 0 0x4ce4 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_SMU_ARGUMENT_3 0 0x4ce5 1 0 1 ARG 0 31 mmRLC_SMU_ARGUMENT_4 0 0x4ce6 1 0 1 ARG 0 31 mmRLC_GPU_CLOCK_COUNT_LSB_1 0 0x4ce8 1 0 1 GPU_CLOCKS_LSB 0 31 mmRLC_GPU_CLOCK_COUNT_MSB_1 0 0x4ce9 1 0 1 GPU_CLOCKS_MSB 0 31 mmRLC_CAPTURE_GPU_CLOCK_COUNT_1 0 0x4cea 2 0 1 CAPTURE 0 0 RESERVED 1 31 mmRLC_GPU_CLOCK_COUNT_LSB_2 0 0x4ceb 1 0 1 GPU_CLOCKS_LSB 0 31 mmRLC_GPU_CLOCK_COUNT_MSB_2 0 0x4cec 1 0 1 GPU_CLOCKS_MSB 0 31 mmRLC_PACE_INT_DISABLE 0 0x4ced 1 0 1 DISABLE_INT 0 31 mmRLC_CAPTURE_GPU_CLOCK_COUNT_2 0 0x4cef 2 0 1 CAPTURE 0 0 RESERVED 1 31 mmRLC_RLCV_DOORBELL_RANGE 0 0x4cf0 4 0 1 LOWER_ADDR_RESERVED 0 1 LOWER_ADDR 2 11 UPPER_ADDR_RESERVED 16 17 UPPER_ADDR 18 27 mmRLC_RLCV_DOORBELL_CNTL 0 0x4cf1 6 0 1 DOORBELL_0_MODE 0 1 DOORBELL_1_MODE 2 3 DOORBELL_2_MODE 4 5 DOORBELL_3_MODE 6 7 DOORBELL_ID 16 20 DOORBELL_ID_EN 21 21 mmRLC_RLCV_DOORBELL_STAT 0 0x4cf2 4 0 1 DOORBELL_0_VALID 0 0 DOORBELL_1_VALID 1 1 DOORBELL_2_VALID 2 2 DOORBELL_3_VALID 3 3 mmRLC_RLCV_DOORBELL_0_DATA_LO 0 0x4cf3 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_0_DATA_HI 0 0x4cf4 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_1_DATA_LO 0 0x4cf5 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_1_DATA_HI 0 0x4cf6 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_2_DATA_LO 0 0x4cf7 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_2_DATA_HI 0 0x4cf8 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_3_DATA_LO 0 0x4cf9 1 0 1 DATA 0 31 mmRLC_RLCV_DOORBELL_3_DATA_HI 0 0x4cfa 1 0 1 DATA 0 31 mmRLC_RLCV_SPARE_INT 0 0x4d00 2 0 1 INTERRUPT 0 0 RESERVED 1 31 mmRLC_PACE_TIMER_INT_0 0 0x4d04 1 0 1 TIMER 0 31 mmRLC_PACE_TIMER_CTRL 0 0x4d05 7 0 1 TIMER_0_EN 0 0 TIMER_1_EN 1 1 TIMER_0_AUTO_REARM 2 2 TIMER_1_AUTO_REARM 3 3 TIMER_0_INT_CLEAR 4 4 TIMER_1_INT_CLEAR 5 5 RESERVED 6 31 mmRLC_PACE_TIMER_INT_1 0 0x4d06 1 0 1 TIMER 0 31 mmRLC_PACE_SPARE_INT 0 0x4d07 2 0 1 INTERRUPT 0 0 RESERVED 1 31 mmRLC_SMU_CLK_REQ 0 0x4d08 1 0 1 VALID 0 0 mmRLC_CP_STAT_INVAL_STAT 0 0x4d09 6 0 1 CPG_STAT_INVAL_PEND 0 0 CPC_STAT_INVAL_PEND 1 1 CPF_STAT_INVAL_PEND 2 2 CPG_STAT_INVAL_PEND_CHANGED 3 3 CPC_STAT_INVAL_PEND_CHANGED 4 4 CPF_STAT_INVAL_PEND_CHANGED 5 5 mmRLC_CP_STAT_INVAL_CTRL 0 0x4d0a 3 0 1 CPG_STAT_INVAL_PEND_EN 0 0 CPC_STAT_INVAL_PEND_EN 1 1 CPF_STAT_INVAL_PEND_EN 2 2 mmRLC_CLK_STATUS 0 0x4d0b 9 0 1 RLC_ALL_CLK_VALID 0 0 RLC_CMN_GPM_SCLK_DYN_VLD 1 1 RLC_CMN_TC_SCLK_DYN_VLD 2 2 RLC_CMN_SPP_SCLK_DYN_VLD 3 3 RLC_CMN_SRM_SCLK_DYN_VLD 5 5 RLC_SRM_CLK_BUSY 6 6 RLC_CMN_SPM_SCLK_DYN_VLD 7 7 RLC_SPM_CLK_BUSY 8 8 RESERVED 9 31 mmRLC_SPP_CTRL 0 0x4d0c 4 0 1 ENABLE 0 0 ENABLE_PPROF 1 1 ENABLE_PWR_OPT 2 2 PAUSE 3 3 mmRLC_SPP_SHADER_PROFILE_EN 0 0x4d0d 17 0 1 PS_ENABLE 0 0 VS_ENABLE 1 1 GS_ENABLE 2 2 HS_ENABLE 3 3 CSG_ENABLE 4 4 CS_ENABLE 5 5 PS_STOP_CONDITION 6 6 VS_STOP_CONDITION 7 7 GS_STOP_CONDITION 8 8 HS_STOP_CONDITION 9 9 CSG_STOP_CONDITION 10 10 CS_STOP_CONDITION 11 11 PS_START_CONDITION 12 12 CS_START_CONDITION 13 13 FORCE_MISS 14 14 FORCE_UNLOCKED 15 15 ENABLE_PROF_INFO_LOCK 16 16 mmRLC_SPP_SSF_CAPTURE_EN 0 0x4d0e 6 0 1 PS_ENABLE 0 0 VS_ENABLE 1 1 GS_ENABLE 2 2 HS_ENABLE 3 3 CSG_ENABLE 4 4 CS_ENABLE 5 5 mmRLC_SPP_SSF_THRESHOLD_0 0 0x4d0f 2 0 1 PS_THRESHOLD 0 15 VS_THRESHOLD 16 31 mmRLC_SPP_SSF_THRESHOLD_1 0 0x4d10 2 0 1 GS_THRESHOLD 0 15 HS_THRESHOLD 16 31 mmRLC_SPP_SSF_THRESHOLD_2 0 0x4d11 2 0 1 CSG_THRESHOLD 0 15 CS_THRESHOLD 16 31 mmRLC_SPP_INFLIGHT_RD_ADDR 0 0x4d12 1 0 1 ADDR 0 4 mmRLC_SPP_INFLIGHT_RD_DATA 0 0x4d13 1 0 1 DATA 0 31 mmRLC_GPM_GENERAL_16 0 0x4d14 1 0 1 DATA 0 31 mmRLC_SPP_PROF_INFO_1 0 0x4d18 1 0 1 SH_ID 0 31 mmRLC_SPP_PROF_INFO_2 0 0x4d19 4 0 1 SH_TYPE 0 3 CAM_HIT 4 4 CAM_LOCK 5 5 CAM_CONFLICT 6 6 mmRLC_SPP_GLOBAL_SH_ID 0 0x4d1a 1 0 1 SH_ID 0 31 mmRLC_SPP_GLOBAL_SH_ID_VALID 0 0x4d1b 1 0 1 VALID 0 0 mmRLC_SPP_STATUS 0 0x4d1c 4 0 1 RESERVED_0 0 0 SSF_BUSY 1 1 EVENT_ARB_BUSY 2 2 SPP_BUSY 31 31 mmRLC_SPP_PVT_STAT_0 0 0x4d1d 5 0 1 LEVEL_0_COUNTER 0 5 LEVEL_1_COUNTER 6 11 LEVEL_2_COUNTER 12 17 LEVEL_3_COUNTER 18 23 LEVEL_4_COUNTER 24 30 mmRLC_SPP_PVT_STAT_1 0 0x4d1e 5 0 1 LEVEL_5_COUNTER 0 5 LEVEL_6_COUNTER 6 11 LEVEL_7_COUNTER 12 17 LEVEL_8_COUNTER 18 23 LEVEL_9_COUNTER 24 30 mmRLC_SPP_PVT_STAT_2 0 0x4d1f 5 0 1 LEVEL_10_COUNTER 0 5 LEVEL_11_COUNTER 6 11 LEVEL_12_COUNTER 12 17 LEVEL_13_COUNTER 18 23 LEVEL_14_COUNTER 24 30 mmRLC_SPP_PVT_STAT_3 0 0x4d20 1 0 1 LEVEL_15_COUNTER 0 5 mmRLC_SPP_PVT_LEVEL_MAX 0 0x4d21 1 0 1 LEVEL 0 3 mmRLC_SPP_STALL_STATE_UPDATE 0 0x4d22 2 0 1 STALL 0 0 ENABLE 1 1 mmRLC_SPP_PBB_INFO 0 0x4d23 4 0 1 PIPE0_OVERRIDE 0 0 PIPE0_OVERRIDE_VALID 1 1 PIPE1_OVERRIDE 2 2 PIPE1_OVERRIDE_VALID 3 3 mmRLC_SPP_RESET 0 0x4d24 4 0 1 SSF_RESET 0 0 EVENT_ARB_RESET 1 1 CAM_RESET 2 2 PVT_RESET 3 3 mmRLC_SPM_SAMPLE_CNT 0 0x4d25 1 0 1 COUNT 0 31 mmRLC_RLCP_DOORBELL_RANGE 0 0x4d26 4 0 1 LOWER_ADDR_RESERVED 0 1 LOWER_ADDR 2 11 UPPER_ADDR_RESERVED 16 17 UPPER_ADDR 18 27 mmRLC_RLCP_DOORBELL_CNTL 0 0x4d27 6 0 1 DOORBELL_0_MODE 0 1 DOORBELL_1_MODE 2 3 DOORBELL_2_MODE 4 5 DOORBELL_3_MODE 6 7 DOORBELL_ID 16 20 DOORBELL_ID_EN 21 21 mmRLC_RLCP_DOORBELL_STAT 0 0x4d28 4 0 1 DOORBELL_0_VALID 0 0 DOORBELL_1_VALID 1 1 DOORBELL_2_VALID 2 2 DOORBELL_3_VALID 3 3 mmRLC_RLCP_DOORBELL_0_DATA_LO 0 0x4d29 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_0_DATA_HI 0 0x4d2a 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_1_DATA_LO 0 0x4d2b 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_1_DATA_HI 0 0x4d2c 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_2_DATA_LO 0 0x4d2d 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_2_DATA_HI 0 0x4d2e 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_3_DATA_LO 0 0x4d2f 1 0 1 DATA 0 31 mmRLC_RLCP_DOORBELL_3_DATA_HI 0 0x4d30 1 0 1 DATA 0 31 mmRLC_PCC_STRETCH_HYSTERESIS_CNTL 0 0x4d44 2 0 1 MAX_HYSTERESIS 0 7 HYSTERESIS_CNT 8 15 mmRLC_CAC_MASK_CNTL 0 0x4d45 1 0 1 RLC_CAC_MASK 0 31 mmRLC_GPU_CLOCK_COUNT_SPM_LSB 0 0x4de4 1 0 1 GPU_CLOCKS_LSB 0 31 mmRLC_GPU_CLOCK_COUNT_SPM_MSB 0 0x4de5 1 0 1 GPU_CLOCKS_MSB 0 31 mmRLC_SPM_THREAD_TRACE_CTRL 0 0x4de6 1 0 1 THREAD_TRACE_INT_EN 0 0 mmRLC_LB_CNTR_2 0 0x4de7 1 0 1 RLC_LOAD_BALANCE_CNTR 0 31 mmRLC_CPAXI_DOORBELL_MON_CTRL 0 0x4df1 2 0 1 EN 0 0 ID 1 5 mmRLC_CPAXI_DOORBELL_MON_STAT 0 0x4df2 3 0 1 ID_MATCH 0 0 MATCH_CLEAR 1 1 ADDR 2 27 mmRLC_CPAXI_DOORBELL_MON_DATA_LSB 0 0x4df3 1 0 1 DATA 0 31 mmRLC_CPAXI_DOORBELL_MON_DATA_MSB 0 0x4df4 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_RANGE 0 0x4df5 4 0 1 LOWER_ADDR_RESERVED 0 1 LOWER_ADDR 2 11 UPPER_ADDR_RESERVED 16 17 UPPER_ADDR 18 27 mmRLC_XT_DOORBELL_CNTL 0 0x4df6 6 0 1 DOORBELL_0_MODE 0 1 DOORBELL_1_MODE 2 3 DOORBELL_2_MODE 4 5 DOORBELL_3_MODE 6 7 DOORBELL_ID 16 20 DOORBELL_ID_EN 21 21 mmRLC_XT_DOORBELL_STAT 0 0x4df7 4 0 1 DOORBELL_0_VALID 0 0 DOORBELL_1_VALID 1 1 DOORBELL_2_VALID 2 2 DOORBELL_3_VALID 3 3 mmRLC_XT_DOORBELL_0_DATA_LO 0 0x4df8 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_0_DATA_HI 0 0x4df9 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_1_DATA_LO 0 0x4dfa 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_1_DATA_HI 0 0x4dfb 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_2_DATA_LO 0 0x4dfc 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_2_DATA_HI 0 0x4dfd 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_3_DATA_LO 0 0x4dfe 1 0 1 DATA 0 31 mmRLC_XT_DOORBELL_3_DATA_HI 0 0x4dff 1 0 1 DATA 0 31 mmRLC_SPP_CAM_ADDR 0 0x4e00 1 0 1 ADDR 0 7 mmRLC_SPP_CAM_DATA 0 0x4e01 2 0 1 DATA 0 7 TAG 8 31 mmRLC_SPP_CAM_EXT_ADDR 0 0x4e02 1 0 1 ADDR 0 7 mmRLC_SPP_CAM_EXT_DATA 0 0x4e03 2 0 1 VALID 0 0 LOCK 1 1 mmRLC_PACE_SCRATCH_ADDR 0 0x4e04 1 0 1 ADDR 0 15 mmRLC_PACE_SCRATCH_DATA 0 0x4e05 1 0 1 DATA 0 31 mmRLC_RLCS_DEC_START 0 0x4e60 0 0 1 mmRLC_RLCS_DEC_DUMP_ADDR 0 0x4e61 0 0 1 mmRLC_RLCS_EXCEPTION_REG_1 0 0x4e62 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_EXCEPTION_REG_2 0 0x4e63 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_EXCEPTION_REG_3 0 0x4e64 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_EXCEPTION_REG_4 0 0x4e65 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_GENERAL_6 0 0x4e66 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_7 0 0x4e67 1 0 1 DATA 0 31 mmRLC_RLCS_CGCG_REQUEST 0 0x4e68 3 0 1 CGCG_REQUEST 0 0 CGCG_REQUEST_3D 1 1 RESERVED 2 31 mmRLC_RLCS_CGCG_STATUS 0 0x4e69 5 0 1 CGCG_RAMP_STATUS 0 1 GFX_CLK_STATUS 2 2 CGCG_RAMP_STATUS_3D 3 4 GFX_CLK_STATUS_3D 5 5 RESERVED 6 31 mmRLC_RLCS_SMU_GFXCLK_STATUS 0 0x4e6a 4 0 1 SMU_GFXCLK_DONETOG 0 0 SMU_GFXMUX_CUR_VALUE 1 1 SMU_GFXCLK_STRETCH_PCC 2 2 SMU_GFXCLK_PCC_CTRL 3 3 mmRLC_RLCS_SMU_GFXCLK_CONTROL 0 0x4e6b 4 0 1 SMU_GFXCLK_CHGTOG 0 0 SMU_GFXCLK_DIVIDER 1 7 SMU_GFXMUX_SEL 8 8 RESERVED 9 31 mmRLC_RLCS_SOC_DS_CNTL 0 0x4e6c 13 0 1 SOC_CLK_DS_ALLOW 0 0 SOC_CLK_DS_RLC_BUSY_MASK 1 1 SOC_CLK_DS_CP_BUSY_MASK 2 2 SOC_CLK_DS_GFX_PWR_STALLED_MASK 6 6 SOC_CLK_DS_NON3D_PWR_STALLED_MASK 7 7 SOC_CLK_DS_SDMA_0_BUSY_MASK 16 16 SOC_CLK_DS_SDMA_1_BUSY_MASK 17 17 SOC_CLK_DS_SDMA_2_BUSY_MASK 18 18 SOC_CLK_DS_SDMA_3_BUSY_MASK 19 19 SOC_CLK_DS_SDMA_4_BUSY_MASK 20 20 SOC_CLK_DS_SDMA_5_BUSY_MASK 21 21 SOC_CLK_DS_SDMA_6_BUSY_MASK 22 22 SOC_CLK_DS_SDMA_7_BUSY_MASK 23 23 mmRLC_RLCS_GFX_DS_CNTL 0 0x4e6d 13 0 1 GFX_CLK_DS_ALLOW 0 0 GFX_CLK_DS_RLC_BUSY_MASK 1 1 GFX_CLK_DS_CP_BUSY_MASK 2 2 GFX_CLK_DS_GFX_PWR_STALLED_MASK 6 6 GFX_CLK_DS_NON3D_PWR_STALLED_MASK 7 7 GFX_CLK_DS_SDMA_0_BUSY_MASK 16 16 GFX_CLK_DS_SDMA_1_BUSY_MASK 17 17 GFX_CLK_DS_SDMA_2_BUSY_MASK 18 18 GFX_CLK_DS_SDMA_3_BUSY_MASK 19 19 GFX_CLK_DS_SDMA_4_BUSY_MASK 20 20 GFX_CLK_DS_SDMA_5_BUSY_MASK 21 21 GFX_CLK_DS_SDMA_6_BUSY_MASK 22 22 GFX_CLK_DS_SDMA_7_BUSY_MASK 23 23 mmRLC_GPM_STAT 0 0x4e6e 25 0 1 RLC_BUSY 0 0 GFX_POWER_STATUS 1 1 GFX_CLOCK_STATUS 2 2 GFX_LS_STATUS 3 3 GFX_PIPELINE_POWER_STATUS 4 4 CNTX_IDLE_BEING_PROCESSED 5 5 CNTX_BUSY_BEING_PROCESSED 6 6 GFX_IDLE_BEING_PROCESSED 7 7 CMP_BUSY_BEING_PROCESSED 8 8 SAVING_REGISTERS 9 9 RESTORING_REGISTERS 10 10 GFX3D_BLOCKS_CHANGING_POWER_STATE 11 11 CMP_BLOCKS_CHANGING_POWER_STATE 12 12 STATIC_WGP_POWERING_UP 13 13 STATIC_WGP_POWERING_DOWN 14 14 DYN_WGP_POWERING_UP 15 15 DYN_WGP_POWERING_DOWN 16 16 ABORTED_PD_SEQUENCE 17 17 CMP_power_status 18 18 GFX_LS_STATUS_3D 19 19 GFX_CLOCK_STATUS_3D 20 20 MGCG_OVERRIDE_STATUS 21 21 RLC_EXEC_ROM_CODE 22 22 FGCG_OVERRIDE_STATUS 23 23 PG_ERROR_STATUS 24 31 mmRLC_RLCS_GPM_STAT 0 0x4e6e 25 0 1 RLC_BUSY 0 0 GFX_POWER_STATUS 1 1 GFX_CLOCK_STATUS 2 2 GFX_LS_STATUS 3 3 GFX_PIPELINE_POWER_STATUS 4 4 CNTX_IDLE_BEING_PROCESSED 5 5 CNTX_BUSY_BEING_PROCESSED 6 6 GFX_IDLE_BEING_PROCESSED 7 7 CMP_BUSY_BEING_PROCESSED 8 8 SAVING_REGISTERS 9 9 RESTORING_REGISTERS 10 10 GFX3D_BLOCKS_CHANGING_POWER_STATE 11 11 CMP_BLOCKS_CHANGING_POWER_STATE 12 12 STATIC_WGP_POWERING_UP 13 13 STATIC_WGP_POWERING_DOWN 14 14 DYN_WGP_POWERING_UP 15 15 DYN_WGP_POWERING_DOWN 16 16 ABORTED_PD_SEQUENCE 17 17 CMP_POWER_STATUS 18 18 GFX_LS_STATUS_3D 19 19 GFX_CLOCK_STATUS_3D 20 20 MGCG_OVERRIDE_STATUS 21 21 RLC_EXEC_ROM_CODE 22 22 FGCG_OVERRIDE_STATUS 23 23 PG_ERROR_STATUS 24 31 mmRLC_RLCS_ABORTED_PD_SEQUENCE 0 0x4e6f 2 0 1 APS 0 15 RESERVED 16 31 mmRLC_RLCS_DIDT_FORCE_STALL 0 0x4e70 2 0 1 DFS 0 2 RESERVED 3 31 mmRLC_RLCS_IOV_CMD_STATUS 0 0x4e71 1 0 1 DATA 0 31 mmRLC_RLCS_IOV_CNTX_LOC_SIZE 0 0x4e72 2 0 1 DATA 0 7 RESERVED 8 31 mmRLC_RLCS_IOV_SCH_BLOCK 0 0x4e73 1 0 1 DATA 0 31 mmRLC_RLCS_IOV_VM_BUSY_STATUS 0 0x4e74 1 0 1 DATA 0 31 mmRLC_RLCS_GPM_STAT_2 0 0x4e75 6 0 1 TC_TRANS_ERROR 0 0 RLC_PWR_NON3D_STALLED 1 1 GFX_PWR_STALLED_STATUS 2 2 GFX_ULV_STATUS 3 3 GFX_GENERAL_STATUS 4 4 RESERVED 5 31 mmRLC_RLCS_GRBM_SOFT_RESET 0 0x4e76 2 0 1 RESET 0 0 RESERVED 1 31 mmRLC_RLCS_PG_CHANGE_STATUS 0 0x4e77 5 0 1 PG_CNTL_CHANGED 0 0 PG_REG_CHANGED 1 1 DYN_PG_STATUS_CHANGED 2 2 DYN_PG_REQ_CHANGED 3 3 RESERVED 4 31 mmRLC_RLCS_PG_CHANGE_READ 0 0x4e78 5 0 1 PG_CNTL_CHANGED 0 0 PG_REG_CHANGED 1 1 DYN_PG_STATUS_CHANGED 2 2 DYN_PG_REQ_CHANGED 3 3 RESERVED 4 31 mmRLC_RLCS_LB_STATUS 0 0x4e79 6 0 1 LB_CNTR_START 0 0 LB_CNTR_STOP 1 1 LB_CNTR_1_MAX_FLAG 2 2 LB_CNTR_2_MAX_FLAG 3 3 LBPW_DISABLE_FLAG 4 4 RESERVED 5 31 mmRLC_RLCS_LB_READ 0 0x4e7a 6 0 1 LB_CNTR_START 0 0 LB_CNTR_STOP 1 1 LB_CNTR_1_MAX_FLAG 2 2 LB_CNTR_2_MAX_FLAG 3 3 LBPW_DISABLE_FLAG 4 4 RESERVED 5 31 mmRLC_RLCS_LB_CONTROL 0 0x4e7b 3 0 1 NEW_LBPW_REQ 0 0 LB_CNTR_INC_CP_BUSY 1 1 RESERVED 2 31 mmRLC_RLCS_IH_SEMAPHORE 0 0x4e7c 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_RLCS_IH_COOKIE_SEMAPHORE 0 0x4e7d 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_RLCS_IH_CTRL_1 0 0x4e7e 1 0 1 IH_CONTEXT_ID_1 0 31 mmRLC_RLCS_IH_CTRL_2 0 0x4e7f 4 0 1 IH_CONTEXT_ID_2 0 7 IH_RING_ID 8 15 IH_VM_ID 16 19 RESERVED 20 31 mmRLC_RLCS_IH_CTRL_3 0 0x4e80 4 0 1 IH_SOURCE_ID 0 7 IH_VF_ID 8 12 IH_VF 13 13 RESERVED 14 31 mmRLC_RLCS_IH_STATUS 0 0x4e81 3 0 1 IH_CREDIT_COUNT 0 5 IH_BUSY 6 6 RESERVED 7 31 mmRLC_RLCS_WGP_STATUS 0 0x4e82 5 0 1 CS_WORK_ACTIVE 0 0 STATIC_WGP_STATUS_CHANGED 1 1 DYMANIC_WGP_STATUS_CHANGED 2 2 STATIC_PERWGP_PD_INCOMPLETE 3 3 RESERVED 4 31 mmRLC_RLCS_WGP_READ 0 0x4e83 4 0 1 CS_WORK_ACTIVE 0 0 STATIC_WGP_STATUS_CHANGED 1 1 DYMANIC_WGP_STATUS_CHANGED 2 2 RESERVED 3 31 mmRLC_RLCS_CP_INT_CTRL_1 0 0x4e84 2 0 1 INTERRUPT_ACK 0 0 RESERVED 1 31 mmRLC_RLCS_CP_INT_CTRL_2 0 0x4e85 3 0 1 IDLE_AUTO_ACK_EN 0 0 BUSY_AUTO_ACK_EN 1 1 RESERVED 2 31 mmRLC_RLCS_CP_INT_INFO_1 0 0x4e86 1 0 1 INTERRUPT_INFO_1 0 31 mmRLC_RLCS_CP_INT_INFO_2 0 0x4e87 3 0 1 INTERRUPT_INFO_2 0 15 INTERRUPT_ID 16 24 RESERVED 25 31 mmRLC_RLCS_SPM_INT_CTRL 0 0x4e88 2 0 1 INTERRUPT_ACK 0 0 RESERVED 1 31 mmRLC_RLCS_SPM_INT_INFO_1 0 0x4e89 1 0 1 INTERRUPT_INFO_1 0 31 mmRLC_RLCS_SPM_INT_INFO_2 0 0x4e8a 3 0 1 INTERRUPT_INFO_2 0 15 INTERRUPT_ID 16 24 RESERVED 25 31 mmRLC_RLCS_DSM_TRIG 0 0x4e8b 2 0 1 START 0 0 RESERVED 1 31 mmRLC_RLCS_BOOTLOAD_STATUS 0 0x4e8d 3 0 1 RLC_RLCG_IRAM_LOADED 0 0 RESERVED 1 30 BOOTLOAD_COMPLETE 31 31 mmRLC_RLCS_POWER_BRAKE_CNTL 0 0x4e8e 5 0 1 POWER_BRAKE 0 0 INT_CLEAR 1 1 MAX_HYSTERESIS 2 9 HYSTERESIS_CNT 10 17 RESERVED 18 31 mmRLC_RLCS_GENERAL_0 0 0x4e8f 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_1 0 0x4e90 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_2 0 0x4e91 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_3 0 0x4e92 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_4 0 0x4e93 1 0 1 DATA 0 31 mmRLC_RLCS_GENERAL_5 0 0x4e94 1 0 1 DATA 0 31 mmRLC_RLCS_GRBM_IDLE_BUSY_STAT 0 0x4ec1 17 0 1 GRBM_RLC_GC_STAT_IDLE 0 1 SDMA_0_BUSY 16 16 SDMA_1_BUSY 17 17 SDMA_2_BUSY 18 18 SDMA_3_BUSY 19 19 SDMA_4_BUSY 20 20 SDMA_5_BUSY 21 21 SDMA_6_BUSY 22 22 SDMA_7_BUSY 23 23 SDMA_0_BUSY_CHANGED 24 24 SDMA_1_BUSY_CHANGED 25 25 SDMA_2_BUSY_CHANGED 26 26 SDMA_3_BUSY_CHANGED 27 27 SDMA_4_BUSY_CHANGED 28 28 SDMA_5_BUSY_CHANGED 29 29 SDMA_6_BUSY_CHANGED 30 30 SDMA_7_BUSY_CHANGED 31 31 mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0 0x4ec2 8 0 1 SDMA0_BUSY_INT_CLEAR 0 0 SDMA1_BUSY_INT_CLEAR 1 1 SDMA2_BUSY_INT_CLEAR 2 2 SDMA3_BUSY_INT_CLEAR 3 3 SDMA4_BUSY_INT_CLEAR 4 4 SDMA5_BUSY_INT_CLEAR 5 5 SDMA6_BUSY_INT_CLEAR 6 6 SDMA7_BUSY_INT_CLEAR 7 7 mmRLC_RLCS_CMP_IDLE_CNTL 0 0x4ec3 6 0 1 INT_CLEAR 0 0 CMP_IDLE_HYST 1 1 CMP_IDLE 2 2 MAX_HYSTERESIS 3 10 HYSTERESIS_CNT 11 18 RESERVED 19 31 mmRLC_RLCS_POWER_BRAKE_CNTL_TH1 0 0x4ec4 5 0 1 POWER_BRAKE 0 0 INT_CLEAR 1 1 MAX_HYSTERESIS 2 9 HYSTERESIS_CNT 10 17 RESERVED 18 31 mmRLC_RLCS_AUXILIARY_REG_1 0 0x4ec5 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_AUXILIARY_REG_2 0 0x4ec6 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_AUXILIARY_REG_3 0 0x4ec7 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_AUXILIARY_REG_4 0 0x4ec8 2 0 1 ADDR 0 17 RESERVED 18 31 mmRLC_RLCS_SPM_SQTT_MODE 0 0x4ee0 1 0 1 MODE 0 0 mmRLC_RLCS_CP_DMA_SRCID_OVER 0 0x4ee4 1 0 1 SRCID_OVERRIDE 0 0 mmRLC_RLCS_UTCL2_CNTL 0 0x4ee6 6 0 1 MTYPE_NO_PTE_MODE 0 0 GPA_OVERRIDE 1 1 VF_OVERRIDE 2 2 GPA_OVERRIDE_VALUE 3 4 VF_OVERRIDE_VALUE 5 5 RESERVED 6 31 mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL 0 0x4ee8 3 0 1 INT_CLEAR 0 0 DOORBELL 1 1 RESERVED 2 31 mmRLC_RLCS_BOOTLOAD_ID_STATUS1 0 0x4eec 32 0 1 ID_0_LOADED 0 0 ID_1_LOADED 1 1 ID_2_LOADED 2 2 ID_3_LOADED 3 3 ID_4_LOADED 4 4 ID_5_LOADED 5 5 ID_6_LOADED 6 6 ID_7_LOADED 7 7 ID_8_LOADED 8 8 ID_9_LOADED 9 9 ID_10_LOADED 10 10 ID_11_LOADED 11 11 ID_12_LOADED 12 12 ID_13_LOADED 13 13 ID_14_LOADED 14 14 ID_15_LOADED 15 15 ID_16_LOADED 16 16 ID_17_LOADED 17 17 ID_18_LOADED 18 18 ID_19_LOADED 19 19 ID_20_LOADED 20 20 ID_21_LOADED 21 21 ID_22_LOADED 22 22 ID_23_LOADED 23 23 ID_24_LOADED 24 24 ID_25_LOADED 25 25 ID_26_LOADED 26 26 ID_27_LOADED 27 27 ID_28_LOADED 28 28 ID_29_LOADED 29 29 ID_30_LOADED 30 30 ID_31_LOADED 31 31 mmRLC_RLCS_BOOTLOAD_ID_STATUS2 0 0x4eed 32 0 1 ID_32_LOADED 0 0 ID_33_LOADED 1 1 ID_34_LOADED 2 2 ID_35_LOADED 3 3 ID_36_LOADED 4 4 ID_37_LOADED 5 5 ID_38_LOADED 6 6 ID_39_LOADED 7 7 ID_40_LOADED 8 8 ID_41_LOADED 9 9 ID_42_LOADED 10 10 ID_43_LOADED 11 11 ID_44_LOADED 12 12 ID_45_LOADED 13 13 ID_46_LOADED 14 14 ID_47_LOADED 15 15 ID_48_LOADED 16 16 ID_49_LOADED 17 17 ID_50_LOADED 18 18 ID_51_LOADED 19 19 ID_52_LOADED 20 20 ID_53_LOADED 21 21 ID_54_LOADED 22 22 ID_55_LOADED 23 23 ID_56_LOADED 24 24 ID_57_LOADED 25 25 ID_58_LOADED 26 26 ID_59_LOADED 27 27 ID_60_LOADED 28 28 ID_61_LOADED 29 29 ID_62_LOADED 30 30 ID_63_LOADED 31 31 mmRLC_RLCS_SMUIO_VIDCHG_CTRL 0 0x4eee 4 0 1 REQ 0 0 DATA 1 9 PSIEN 10 10 ACK 11 11 mmRLC_RLCS_EDC_INT_CNTL 0 0x4eef 1 0 1 EDC_EVENT_INT_CLEAR 0 0 mmRLC_RLCS_KMD_LOG_CNTL1 0 0x4ef1 1 0 1 DATA 0 31 mmRLC_RLCS_KMD_LOG_CNTL2 0 0x4ef2 1 0 1 DATA 0 31 mmRLC_RLCS_GPM_LEGACY_INT_STAT 0 0x4ef3 2 0 1 GC_CAC_EDC_EVENT_CHANGED 0 0 GFX_POWER_BRAKE_CHANGED 1 1 mmRLC_RLCS_GPM_LEGACY_INT_DISABLE 0 0x4ef4 2 0 1 GC_CAC_EDC_EVENT_CHANGED 0 0 GFX_POWER_BRAKE_CHANGED 1 1 mmRLC_RLCS_SRM_SRCID_CNTL 0 0x4efd 1 0 1 SRCID 0 2 mmRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0 0x4f03 1 0 1 PERFMON_CLOCK_STATE 0 0 mmRLC_RLCS_DEC_END 0 0x4fff 0 0 1 mmSQ_ALU_CLK_CTRL 0 0x508e 2 0 1 FORCE_WGP_ON_SA0 0 15 FORCE_WGP_ON_SA1 16 31 mmSQ_TEX_CLK_CTRL 0 0x508f 2 0 1 FORCE_WGP_ON_SA0 0 15 FORCE_WGP_ON_SA1 16 31 mmSQ_LDS_CLK_CTRL 0 0x5090 2 0 1 FORCE_WGP_ON_SA0 0 15 FORCE_WGP_ON_SA1 16 31 mmRLC_GFX_RM_CNTL 0 0x50b6 2 0 1 RLC_GFX_RM_VALID 0 0 RESERVED 1 31 mmCP_HYP_PFP_UCODE_ADDR 0 0x5814 1 0 1 UCODE_ADDR 0 19 mmCP_PFP_UCODE_ADDR 0 0x5814 1 0 1 UCODE_ADDR 0 19 mmCP_HYP_PFP_UCODE_DATA 0 0x5815 1 0 1 UCODE_DATA 0 31 mmCP_PFP_UCODE_DATA 0 0x5815 1 0 1 UCODE_DATA 0 31 mmCP_HYP_ME_UCODE_ADDR 0 0x5816 1 0 1 UCODE_ADDR 0 19 mmCP_ME_RAM_RADDR 0 0x5816 1 0 1 ME_RAM_RADDR 0 19 mmCP_ME_RAM_WADDR 0 0x5816 1 0 1 ME_RAM_WADDR 0 20 mmCP_HYP_ME_UCODE_DATA 0 0x5817 1 0 1 UCODE_DATA 0 31 mmCP_ME_RAM_DATA 0 0x5817 1 0 1 ME_RAM_DATA 0 31 mmCP_CE_UCODE_ADDR 0 0x5818 1 0 1 UCODE_ADDR 0 19 mmCP_HYP_CE_UCODE_ADDR 0 0x5818 1 0 1 UCODE_ADDR 0 19 mmCP_CE_UCODE_DATA 0 0x5819 1 0 1 UCODE_DATA 0 31 mmCP_HYP_CE_UCODE_DATA 0 0x5819 1 0 1 UCODE_DATA 0 31 mmCP_HYP_MEC1_UCODE_ADDR 0 0x581a 1 0 1 UCODE_ADDR 0 19 mmCP_MEC_ME1_UCODE_ADDR 0 0x581a 1 0 1 UCODE_ADDR 0 19 mmCP_HYP_MEC1_UCODE_DATA 0 0x581b 1 0 1 UCODE_DATA 0 31 mmCP_MEC_ME1_UCODE_DATA 0 0x581b 1 0 1 UCODE_DATA 0 31 mmCP_HYP_MEC2_UCODE_ADDR 0 0x581c 1 0 1 UCODE_ADDR 0 19 mmCP_MEC_ME2_UCODE_ADDR 0 0x581c 1 0 1 UCODE_ADDR 0 19 mmCP_HYP_MEC2_UCODE_DATA 0 0x581d 1 0 1 UCODE_DATA 0 31 mmCP_MEC_ME2_UCODE_DATA 0 0x581d 1 0 1 UCODE_DATA 0 31 mmCP_PFP_IC_BASE_LO 0 0x5840 1 0 1 IC_BASE_LO 12 31 mmCP_PFP_IC_BASE_HI 0 0x5841 1 0 1 IC_BASE_HI 0 15 mmCP_PFP_IC_BASE_CNTL 0 0x5842 4 0 1 VMID 0 3 ADDRESS_CLAMP 4 4 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_PFP_IC_OP_CNTL 0 0x5843 4 0 1 INVALIDATE_CACHE 0 0 INVALIDATE_CACHE_COMPLETE 1 1 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 mmCP_ME_IC_BASE_LO 0 0x5844 1 0 1 IC_BASE_LO 12 31 mmCP_ME_IC_BASE_HI 0 0x5845 1 0 1 IC_BASE_HI 0 15 mmCP_ME_IC_BASE_CNTL 0 0x5846 4 0 1 VMID 0 3 ADDRESS_CLAMP 4 4 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_ME_IC_OP_CNTL 0 0x5847 4 0 1 INVALIDATE_CACHE 0 0 INVALIDATE_CACHE_COMPLETE 1 1 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 mmCP_CE_IC_BASE_LO 0 0x5848 1 0 1 IC_BASE_LO 12 31 mmCP_CE_IC_BASE_HI 0 0x5849 1 0 1 IC_BASE_HI 0 15 mmCP_CE_IC_BASE_CNTL 0 0x584a 4 0 1 VMID 0 3 ADDRESS_CLAMP 4 4 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_CE_IC_OP_CNTL 0 0x584b 4 0 1 INVALIDATE_CACHE 0 0 INVALIDATE_CACHE_COMPLETE 1 1 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 mmCP_CPC_IC_BASE_LO 0 0x584c 1 0 1 IC_BASE_LO 12 31 mmCP_CPC_IC_BASE_HI 0 0x584d 1 0 1 IC_BASE_HI 0 15 mmCP_CPC_IC_BASE_CNTL 0 0x584e 4 0 1 VMID 0 3 ADDRESS_CLAMP 4 4 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_CPC_IC_OP_CNTL 0 0x584f 4 0 1 INVALIDATE_CACHE 0 0 INVALIDATE_CACHE_COMPLETE 1 1 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 mmCP_MES_IC_BASE_LO 0 0x5850 1 0 1 IC_BASE_LO 12 31 mmCP_MES_MIBASE_LO 0 0x5850 1 0 1 IC_BASE_LO 12 31 mmCP_MES_IC_BASE_HI 0 0x5851 1 0 1 IC_BASE_HI 0 15 mmCP_MES_MIBASE_HI 0 0x5851 1 0 1 IC_BASE_HI 0 15 mmCP_MES_IC_BASE_CNTL 0 0x5852 3 0 1 VMID 0 3 EXE_DISABLE 23 23 CACHE_POLICY 24 25 mmCP_MES_DC_BASE_LO 0 0x5854 1 0 1 DC_BASE_LO 16 31 mmCP_MES_MDBASE_LO 0 0x5854 1 0 1 BASE_LO 16 31 mmCP_MES_DC_BASE_HI 0 0x5855 1 0 1 DC_BASE_HI 0 15 mmCP_MES_MDBASE_HI 0 0x5855 1 0 1 BASE_HI 0 15 mmCP_MES_LOCAL_BASE0_LO 0 0x5856 1 0 1 BASE0_LO 16 31 mmCP_MES_LOCAL_BASE0_HI 0 0x5857 1 0 1 BASE0_HI 0 15 mmCP_MES_LOCAL_MASK0_LO 0 0x5858 1 0 1 MASK0_LO 16 31 mmCP_MES_LOCAL_MASK0_HI 0 0x5859 1 0 1 MASK0_HI 0 15 mmCP_MES_LOCAL_APERTURE 0 0x585a 1 0 1 APERTURE 0 1 mmCP_MES_MIBOUND_LO 0 0x585b 1 0 1 BOUND_LO 0 31 mmCP_MES_MIBOUND_HI 0 0x585c 1 0 1 BOUND_HI 0 31 mmCP_MES_MDBOUND_LO 0 0x585d 1 0 1 BOUND_LO 0 31 mmCP_MES_MDBOUND_HI 0 0x585e 1 0 1 BOUND_HI 0 31 mmGFX_PIPE_PRIORITY 0 0x587f 1 0 1 HP_PIPE_SELECT 0 0 mmGRBM_GFX_INDEX_SR_SELECT 0 0x5a00 2 0 1 INDEX 0 2 VF_PF 31 31 mmGRBM_GFX_INDEX_SR_DATA 0 0x5a01 6 0 1 INSTANCE_INDEX 0 7 SA_INDEX 8 15 SE_INDEX 16 23 SA_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 mmGRBM_GFX_CNTL_SR_SELECT 0 0x5a02 2 0 1 INDEX 0 2 VF_PF 31 31 mmGRBM_GFX_CNTL_SR_DATA 0 0x5a03 4 0 1 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 mmGRBM_CAM_INDEX 0 0x5a04 1 0 1 CAM_INDEX 0 3 mmGRBM_HYP_CAM_INDEX 0 0x5a04 1 0 1 CAM_INDEX 0 3 mmGRBM_CAM_DATA 0 0x5a05 2 0 1 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 mmGRBM_HYP_CAM_DATA 0 0x5a05 2 0 1 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 mmGRBM_CAM_DATA_UPPER 0 0x5a06 2 0 1 CAM_ADDR 0 1 CAM_REMAPADDR 16 17 mmGRBM_HYP_CAM_DATA_UPPER 0 0x5a06 2 0 1 CAM_ADDR 0 1 CAM_REMAPADDR 16 17 mmGC_IH_COOKIE_0_PTR 0 0x5a07 1 0 1 ADDR 0 19 mmGRBM_SE_REMAP_CNTL 0 0x5a08 16 0 1 SE0_REMAP_EN 0 0 SE0_REMAP 1 3 SE1_REMAP_EN 4 4 SE1_REMAP 5 7 SE2_REMAP_EN 8 8 SE2_REMAP 9 11 SE3_REMAP_EN 12 12 SE3_REMAP 13 15 SE4_REMAP_EN 16 16 SE4_REMAP 17 19 SE5_REMAP_EN 20 20 SE5_REMAP 21 23 SE6_REMAP_EN 24 24 SE6_REMAP 25 27 SE7_REMAP_EN 28 28 SE7_REMAP 29 31 mmRLC_GPU_IOV_VF_ENABLE 0 0x5b00 3 0 1 VF_ENABLE 0 0 RESERVED 1 15 VF_NUM 16 31 mmRLC_GPU_IOV_CFG_REG6 0 0x5b06 4 0 1 CNTXT_SIZE 0 6 CNTXT_LOCATION 7 7 RESERVED 8 9 CNTXT_OFFSET 10 31 mmRLC_SDMA0_STATUS 0 0x5b12 1 0 1 STATUS 0 31 mmRLC_SDMA1_STATUS 0 0x5b13 1 0 1 STATUS 0 31 mmRLC_SDMA2_STATUS 0 0x5b14 1 0 1 STATUS 0 31 mmRLC_SDMA3_STATUS 0 0x5b15 1 0 1 STATUS 0 31 mmRLC_SDMA0_BUSY_STATUS 0 0x5b16 1 0 1 BUSY_STATUS 0 31 mmRLC_SDMA1_BUSY_STATUS 0 0x5b17 1 0 1 BUSY_STATUS 0 31 mmRLC_SDMA2_BUSY_STATUS 0 0x5b18 1 0 1 BUSY_STATUS 0 31 mmRLC_SDMA3_BUSY_STATUS 0 0x5b19 1 0 1 BUSY_STATUS 0 31 mmRLC_GPU_IOV_CFG_REG8 0 0x5b20 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_RLCV_TIMER_INT_0 0 0x5b25 1 0 1 TIMER 0 31 mmRLC_RLCV_TIMER_CTRL 0 0x5b26 7 0 1 TIMER_0_EN 0 0 TIMER_1_EN 1 1 TIMER_0_AUTO_REARM 2 2 TIMER_1_AUTO_REARM 3 3 TIMER_0_INT_CLEAR 4 4 TIMER_1_INT_CLEAR 5 5 RESERVED 6 31 mmRLC_RLCV_TIMER_STAT 0 0x5b27 7 0 1 TIMER_0_STAT 0 0 TIMER_1_STAT 1 1 RESERVED 2 7 TIMER_0_ENABLE_SYNC 8 8 TIMER_1_ENABLE_SYNC 9 9 TIMER_0_AUTO_REARM_SYNC 10 10 TIMER_1_AUTO_REARM_SYNC 11 11 mmRLC_GPU_IOV_VF_DOORBELL_STATUS 0 0x5b2a 2 0 1 VF_DOORBELL_STATUS 0 30 PF_DOORBELL_STATUS 31 31 mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0 0x5b2b 2 0 1 VF_DOORBELL_STATUS_SET 0 30 PF_DOORBELL_STATUS_SET 31 31 mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0 0x5b2c 2 0 1 VF_DOORBELL_STATUS_CLR 0 30 PF_DOORBELL_STATUS_CLR 31 31 mmRLC_GPU_IOV_VF_MASK 0 0x5b2d 1 0 1 VF_MASK 0 30 mmRLC_HYP_SEMAPHORE_0 0 0x5b2e 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_HYP_SEMAPHORE_1 0 0x5b2f 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_BUSY_CLK_CNTL 0 0x5b30 1 0 1 BUSY_OFF_LATENCY 0 5 mmRLC_CLK_CNTL 0 0x5b31 13 0 1 RLC_SRM_CLK_CNTL 0 1 RLC_SPM_CLK_CNTL 2 3 RLC_GPM_CLK_CNTL 4 4 RLC_CMN_CLK_CNTL 5 5 RLC_TC_CLK_CNTL 6 6 RESERVED_7 7 7 RLC_SRAM_CLK_GATER_OVERRIDE 8 8 RESERVED_9 9 9 RLC_SPP_CLK_CNTL 10 11 RLC_TC_FGCG_REP_OVERRIDE 12 12 RESERVED_15 15 15 RLC_UTCL2_FGCG_OVERRIDE 18 18 RESERVED 19 31 mmRLC_PACE_TIMER_STAT 0 0x5b33 7 0 1 TIMER_0_STAT 0 0 TIMER_1_STAT 1 1 RESERVED 2 7 TIMER_0_ENABLE_SYNC 8 8 TIMER_1_ENABLE_SYNC 9 9 TIMER_0_AUTO_REARM_SYNC 10 10 TIMER_1_AUTO_REARM_SYNC 11 11 mmRLC_GPU_IOV_SCH_BLOCK 0 0x5b34 4 0 1 Sch_Block_ID 0 3 Sch_Block_Ver 4 7 Sch_Block_Size 8 14 RESERVED 16 30 mmRLC_GPU_IOV_CFG_REG1 0 0x5b35 7 0 1 CMD_TYPE 0 3 CMD_EXECUTE 4 4 CMD_EXECUTE_INTR_EN 5 5 RESERVED 6 7 FCN_ID 8 15 NEXT_FCN_ID 16 23 RESERVED1 24 31 mmRLC_GPU_IOV_CFG_REG2 0 0x5b36 2 0 1 CMD_STATUS 0 3 RESERVED 4 31 mmRLC_GPU_IOV_VM_BUSY_STATUS 0 0x5b37 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SCH_0 0 0x5b38 1 0 1 ACTIVE_FUNCTIONS 0 31 mmRLC_GPU_IOV_ACTIVE_FCN_ID 0 0x5b39 3 0 1 VF_ID 0 4 RESERVED 5 30 PF_VF 31 31 mmRLC_GPU_IOV_SCH_3 0 0x5b3a 1 0 1 Time_Quanta_Def 0 31 mmRLC_GPU_IOV_SCH_1 0 0x5b3b 1 0 1 DATA 0 31 mmRLC_GPU_IOV_SCH_2 0 0x5b3c 1 0 1 DATA 0 31 mmRLC_PACE_INT_FORCE 0 0x5b3d 1 0 1 FORCE_INT 0 31 mmRLC_PACE_INT_CLEAR 0 0x5b3e 2 0 1 SMU_STRETCH_PCC_CLEAR 0 0 SMU_PCC_CLEAR 1 1 mmRLC_GPU_IOV_INT_STAT 0 0x5b3f 1 0 1 STATUS 0 31 mmRLC_RLCV_TIMER_INT_1 0 0x5b40 1 0 1 TIMER 0 31 mmRLC_IH_COOKIE 0 0x5b41 1 0 1 DATA 0 31 mmRLC_IH_COOKIE_CNTL 0 0x5b42 2 0 1 CREDIT 0 1 RESET_COUNTER 2 2 mmRLC_HYP_RLCG_UCODE_CHKSUM 0 0x5b43 1 0 1 UCODE_CHKSUM 0 31 mmRLC_HYP_RLCP_UCODE_CHKSUM 0 0x5b44 1 0 1 UCODE_CHKSUM 0 31 mmRLC_HYP_RLCV_UCODE_CHKSUM 0 0x5b45 1 0 1 UCODE_CHKSUM 0 31 mmRLC_GPU_IOV_F32_CNTL 0 0x5b46 1 0 1 ENABLE 0 0 mmRLC_GPU_IOV_F32_RESET 0 0x5b47 1 0 1 RESET 0 0 mmRLC_GPU_IOV_SMU_RESPONSE 0 0x5b4a 1 0 1 RESP 0 31 mmRLC_GPU_IOV_VIRT_RESET_REQ 0 0x5b4c 2 0 1 VF_FLR 0 30 SOFT_PF_FLR 31 31 mmRLC_GPU_IOV_RLC_RESPONSE 0 0x5b4d 1 0 1 RESP 0 31 mmRLC_GPU_IOV_INT_DISABLE 0 0x5b4e 1 0 1 DISABLE_INT 0 31 mmRLC_GPU_IOV_INT_FORCE 0 0x5b4f 1 0 1 FORCE_INT 0 31 mmRLC_HYP_SEMAPHORE_2 0 0x5b52 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_HYP_SEMAPHORE_3 0 0x5b53 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 mmRLC_HYP_RESET_VECTOR 0 0x5b54 8 0 1 COLD_BOOT_EXIT 0 0 VDDGFX_EXIT 1 1 WARM_RESET_EXIT 2 2 VF_FLR_EXIT 3 3 RESERVED_4 4 4 RESERVED_5 5 5 RESERVED_6 6 6 RESERVED_7 7 7 mmRLC_HYP_BOOTLOAD_SIZE 0 0x5b5c 1 0 1 SIZE 0 25 mmRLC_HYP_BOOTLOAD_ADDR_LO 0 0x5b5d 1 0 1 ADDR_LO 0 31 mmRLC_HYP_BOOTLOAD_ADDR_HI 0 0x5b5e 1 0 1 ADDR_HI 0 31 mmRLC_GPM_IRAM_ADDR 0 0x5b5f 1 0 1 ADDR 0 31 mmRLC_GPM_IRAM_DATA 0 0x5b60 1 0 1 DATA 0 31 mmRLC_GPM_UCODE_ADDR 0 0x5b61 2 0 1 UCODE_ADDR 0 13 RESERVED 14 31 mmRLC_GPM_UCODE_DATA 0 0x5b62 1 0 1 UCODE_DATA 0 31 mmRLC_PACE_UCODE_ADDR 0 0x5b63 2 0 1 UCODE_ADDR 0 11 RESERVED 12 31 mmRLC_PACE_UCODE_DATA 0 0x5b64 1 0 1 UCODE_DATA 0 31 mmRLC_GPU_IOV_UCODE_ADDR 0 0x5b65 2 0 1 UCODE_ADDR 0 11 RESERVED 12 31 mmRLC_GPU_IOV_UCODE_DATA 0 0x5b66 1 0 1 UCODE_DATA 0 31 mmRLC_GPU_IOV_SCRATCH_ADDR 0 0x5b67 1 0 1 ADDR 0 15 mmRLC_GPU_IOV_SCRATCH_DATA 0 0x5b68 1 0 1 DATA 0 31 mmRLC_RLCV_IRAM_ADDR 0 0x5b69 1 0 1 ADDR 0 31 mmRLC_RLCV_IRAM_DATA 0 0x5b6a 1 0 1 DATA 0 31 mmRLC_RLCP_IRAM_ADDR 0 0x5b6b 1 0 1 ADDR 0 31 mmRLC_RLCP_IRAM_DATA 0 0x5b6c 1 0 1 DATA 0 31 mmRLC_SRM_DRAM_ADDR 0 0x5b71 2 0 1 ADDR 0 11 RESERVED 12 31 mmRLC_SRM_DRAM_DATA 0 0x5b72 1 0 1 DATA 0 31 mmRLC_SRM_ARAM_ADDR 0 0x5b73 2 0 1 ADDR 0 11 RESERVED 12 31 mmRLC_SRM_ARAM_DATA 0 0x5b74 1 0 1 DATA 0 31 mmRLC_GPM_SCRATCH_ADDR 0 0x5b75 1 0 1 ADDR 0 15 mmRLC_GPM_SCRATCH_DATA 0 0x5b76 1 0 1 DATA 0 31 mmRLC_GTS_OFFSET_LSB 0 0x5b79 1 0 1 DATA 0 31 mmRLC_GTS_OFFSET_MSB 0 0x5b7a 1 0 1 DATA 0 31 mmRLC_GPU_IOV_SDMA0_STATUS 0 0x5bc0 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA1_STATUS 0 0x5bc1 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA2_STATUS 0 0x5bc2 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA3_STATUS 0 0x5bc3 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA4_STATUS 0 0x5bc4 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA5_STATUS 0 0x5bc5 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA6_STATUS 0 0x5bc6 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA7_STATUS 0 0x5bc7 1 0 1 STATUS 0 31 mmRLC_GPU_IOV_SDMA0_BUSY_STATUS 0 0x5bc8 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA1_BUSY_STATUS 0 0x5bc9 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA2_BUSY_STATUS 0 0x5bca 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA3_BUSY_STATUS 0 0x5bcb 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA4_BUSY_STATUS 0 0x5bcc 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA5_BUSY_STATUS 0 0x5bcd 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA6_BUSY_STATUS 0 0x5bce 1 0 1 VM_BUSY_STATUS 0 31 mmRLC_GPU_IOV_SDMA7_BUSY_STATUS 0 0x5bcf 1 0 1 VM_BUSY_STATUS 0 31 mmSDMA0_UCODE_ADDR 0 0x5880 1 0 1 VALUE 0 13 mmSDMA0_UCODE_DATA 0 0x5881 1 0 1 VALUE 0 31 mmSDMA0_VM_CTX_LO 0 0x5882 1 0 1 ADDR 2 31 mmSDMA0_VM_CTX_HI 0 0x5883 1 0 1 ADDR 0 31 mmSDMA0_ACTIVE_FCN_ID 0 0x5884 3 0 1 VFID 0 4 RESERVED 5 30 VF 31 31 mmSDMA0_VM_CTX_CNTL 0 0x5885 2 0 1 PRIV 0 0 VMID 4 7 mmSDMA0_VIRT_RESET_REQ 0 0x5886 2 0 1 VF 0 30 PF 31 31 mmSDMA0_VF_ENABLE 0 0x5887 1 0 1 VF_ENABLE 0 0 mmSDMA0_CONTEXT_REG_TYPE0 0 0x5888 20 0 1 SDMA0_GFX_RB_CNTL 0 0 SDMA0_GFX_RB_BASE 1 1 SDMA0_GFX_RB_BASE_HI 2 2 SDMA0_GFX_RB_RPTR 3 3 SDMA0_GFX_RB_RPTR_HI 4 4 SDMA0_GFX_RB_WPTR 5 5 SDMA0_GFX_RB_WPTR_HI 6 6 SDMA0_GFX_RB_WPTR_POLL_CNTL 7 7 SDMA0_GFX_RB_RPTR_ADDR_HI 8 8 SDMA0_GFX_RB_RPTR_ADDR_LO 9 9 SDMA0_GFX_IB_CNTL 10 10 SDMA0_GFX_IB_RPTR 11 11 SDMA0_GFX_IB_OFFSET 12 12 SDMA0_GFX_IB_BASE_LO 13 13 SDMA0_GFX_IB_BASE_HI 14 14 SDMA0_GFX_IB_SIZE 15 15 SDMA0_GFX_SKIP_CNTL 16 16 SDMA0_GFX_CONTEXT_STATUS 17 17 SDMA0_GFX_DOORBELL 18 18 SDMA0_GFX_CONTEXT_CNTL 19 19 mmSDMA0_CONTEXT_REG_TYPE1 0 0x5889 15 0 1 SDMA0_GFX_STATUS 8 8 SDMA0_GFX_DOORBELL_LOG 9 9 SDMA0_GFX_WATERMARK 10 10 SDMA0_GFX_DOORBELL_OFFSET 11 11 SDMA0_GFX_CSA_ADDR_LO 12 12 SDMA0_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA0_GFX_IB_SUB_REMAIN 15 15 SDMA0_GFX_PREEMPT 16 16 SDMA0_GFX_DUMMY_REG 17 17 SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 18 18 SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 19 19 SDMA0_GFX_RB_AQL_CNTL 20 20 SDMA0_GFX_MINOR_PTR_UPDATE 21 21 RESERVED 24 31 mmSDMA0_CONTEXT_REG_TYPE2 0 0x588a 13 0 1 SDMA0_GFX_MIDCMD_DATA0 0 0 SDMA0_GFX_MIDCMD_DATA1 1 1 SDMA0_GFX_MIDCMD_DATA2 2 2 SDMA0_GFX_MIDCMD_DATA3 3 3 SDMA0_GFX_MIDCMD_DATA4 4 4 SDMA0_GFX_MIDCMD_DATA5 5 5 SDMA0_GFX_MIDCMD_DATA6 6 6 SDMA0_GFX_MIDCMD_DATA7 7 7 SDMA0_GFX_MIDCMD_DATA8 8 8 SDMA0_GFX_MIDCMD_DATA9 9 9 SDMA0_GFX_MIDCMD_DATA10 10 10 SDMA0_GFX_MIDCMD_CNTL 11 11 RESERVED 12 31 mmSDMA0_CONTEXT_REG_TYPE3 0 0x588b 1 0 1 RESERVED 0 31 mmSDMA0_PUB_REG_TYPE0 0 0x588c 28 0 1 SDMA0_UCODE_ADDR 0 0 SDMA0_UCODE_DATA 1 1 SDMA0_VM_CTX_LO 2 2 SDMA0_VM_CTX_HI 3 3 SDMA0_ACTIVE_FCN_ID 4 4 SDMA0_VM_CTX_CNTL 5 5 SDMA0_VIRT_RESET_REQ 6 6 SDMA0_VF_ENABLE 7 7 SDMA0_CONTEXT_REG_TYPE0 8 8 SDMA0_CONTEXT_REG_TYPE1 9 9 SDMA0_CONTEXT_REG_TYPE2 10 10 SDMA0_CONTEXT_REG_TYPE3 11 11 SDMA0_PUB_REG_TYPE0 12 12 SDMA0_PUB_REG_TYPE1 13 13 SDMA0_PUB_REG_TYPE2 14 14 SDMA0_PUB_REG_TYPE3 15 15 SDMA0_VM_CNTL 19 19 RESERVED_FOR_PSPSMU_ACCESS_ONLY 20 21 SDMA0_PG_CNTL 22 22 SDMA0_PG_CTX_LO 23 23 SDMA0_PG_CTX_HI 24 24 SDMA0_PG_CTX_CNTL 25 25 SDMA0_POWER_CNTL 26 26 SDMA0_CLK_CTRL 27 27 SDMA0_CNTL 28 28 SDMA0_CHICKEN_BITS 29 29 SDMA0_GB_ADDR_CONFIG 30 30 SDMA0_GB_ADDR_CONFIG_READ 31 31 mmSDMA0_PUB_REG_TYPE1 0 0x588d 28 0 1 SDMA0_RB_RPTR_FETCH_HI 0 0 SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 1 1 SDMA0_RB_RPTR_FETCH 2 2 SDMA0_IB_OFFSET_FETCH 3 3 SDMA0_PROGRAM 4 4 SDMA0_STATUS_REG 5 5 SDMA0_STATUS1_REG 6 6 SDMA0_RD_BURST_CNTL 7 7 SDMA0_HBM_PAGE_CONFIG 8 8 SDMA0_UCODE_CHECKSUM 9 9 SDMA0_F32_CNTL 10 10 SDMA0_FREEZE 11 11 SDMA0_PHASE0_QUANTUM 12 12 SDMA0_PHASE1_QUANTUM 13 13 SDMA0_EDC_CONFIG 18 18 SDMA0_BA_THRESHOLD 19 19 SDMA0_ID 20 20 SDMA0_VERSION 21 21 SDMA0_EDC_COUNTER 22 22 SDMA0_EDC_COUNTER_CLEAR 23 23 SDMA0_STATUS2_REG 24 24 SDMA0_ATOMIC_CNTL 25 25 SDMA0_ATOMIC_PREOP_LO 26 26 SDMA0_ATOMIC_PREOP_HI 27 27 SDMA0_UTCL1_CNTL 28 28 SDMA0_UTCL1_WATERMK 29 29 SDMA0_UTCL1_RD_STATUS 30 30 SDMA0_UTCL1_WR_STATUS 31 31 mmSDMA0_PUB_REG_TYPE2 0 0x588e 27 0 1 SDMA0_UTCL1_INV0 0 0 SDMA0_UTCL1_INV1 1 1 SDMA0_UTCL1_INV2 2 2 SDMA0_UTCL1_RD_XNACK0 3 3 SDMA0_UTCL1_RD_XNACK1 4 4 SDMA0_UTCL1_WR_XNACK0 5 5 SDMA0_UTCL1_WR_XNACK1 6 6 SDMA0_UTCL1_TIMEOUT 7 7 SDMA0_UTCL1_PAGE 8 8 SDMA0_RELAX_ORDERING_LUT 10 10 SDMA0_CHICKEN_BITS_2 11 11 SDMA0_STATUS3_REG 12 12 SDMA0_PHYSICAL_ADDR_LO 13 13 SDMA0_PHYSICAL_ADDR_HI 14 14 SDMA0_PHASE2_QUANTUM 15 15 SDMA0_ERROR_LOG 16 16 SDMA0_PUB_DUMMY_REG0 17 17 SDMA0_PUB_DUMMY_REG1 18 18 SDMA0_PUB_DUMMY_REG2 19 19 SDMA0_PUB_DUMMY_REG3 20 20 SDMA0_F32_COUNTER 21 21 SDMA0_PERFCNT_PERFCOUNTER0_CFG 23 23 SDMA0_PERFCNT_PERFCOUNTER1_CFG 24 24 SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 25 25 SDMA0_PERFCNT_MISC_CNTL 26 26 SDMA0_CRD_CNTL 27 27 SDMA0_AQL_STATUS 31 31 mmSDMA0_PUB_REG_TYPE3 0 0x588f 25 0 1 SDMA0_EA_DBIT_ADDR_DATA 0 0 SDMA0_EA_DBIT_ADDR_INDEX 1 1 SDMA0_TLBI_GCR_CNTL 2 2 SDMA0_TILING_CONFIG 3 3 SDMA0_PERFCOUNTER0_SELECT 8 8 SDMA0_PERFCOUNTER0_SELECT1 9 9 SDMA0_PERFCOUNTER0_LO 10 10 SDMA0_PERFCOUNTER0_HI 11 11 SDMA0_PERFCOUNTER1_SELECT 12 12 SDMA0_PERFCOUNTER1_SELECT1 13 13 SDMA0_PERFCOUNTER1_LO 14 14 SDMA0_PERFCOUNTER1_HI 15 15 SDMA0_INT_STATUS 16 16 SDMA0_HOLE_ADDR_LO 18 18 SDMA0_HOLE_ADDR_HI 19 19 SDMA0_CLOCK_GATING_REG 21 21 SDMA0_STATUS4_REG 22 22 SDMA0_SCRATCH_RAM_DATA 23 23 SDMA0_SCRATCH_RAM_ADDR 24 24 SDMA0_TIMESTAMP_CNTL 25 25 SDMA0_PERFCNT_PERFCOUNTER_LO 26 26 SDMA0_PERFCNT_PERFCOUNTER_HI 27 27 SDMA0_STATUS5_REG 28 28 SDMA0_QUEUE_RESET_REQ 29 29 RESERVED 30 31 mmSDMA0_VM_CNTL 0 0x5893 1 0 1 CMD 0 3 mmSDMA0_BROADCAST_UCODE_ADDR 0 0x589c 1 0 1 VALUE 0 13 mmSDMA0_BROADCAST_UCODE_DATA 0 0x589d 1 0 1 VALUE 0 31 mmSDMA1_UCODE_ADDR 0 0x58a0 1 0 1 VALUE 0 13 mmSDMA1_UCODE_DATA 0 0x58a1 1 0 1 VALUE 0 31 mmSDMA1_VM_CTX_LO 0 0x58a2 1 0 1 ADDR 2 31 mmSDMA1_VM_CTX_HI 0 0x58a3 1 0 1 ADDR 0 31 mmSDMA1_ACTIVE_FCN_ID 0 0x58a4 3 0 1 VFID 0 4 RESERVED 5 30 VF 31 31 mmSDMA1_VM_CTX_CNTL 0 0x58a5 2 0 1 PRIV 0 0 VMID 4 7 mmSDMA1_VIRT_RESET_REQ 0 0x58a6 2 0 1 VF 0 30 PF 31 31 mmSDMA1_VF_ENABLE 0 0x58a7 1 0 1 VF_ENABLE 0 0 mmSDMA1_CONTEXT_REG_TYPE0 0 0x58a8 20 0 1 SDMA1_GFX_RB_CNTL 0 0 SDMA1_GFX_RB_BASE 1 1 SDMA1_GFX_RB_BASE_HI 2 2 SDMA1_GFX_RB_RPTR 3 3 SDMA1_GFX_RB_RPTR_HI 4 4 SDMA1_GFX_RB_WPTR 5 5 SDMA1_GFX_RB_WPTR_HI 6 6 SDMA1_GFX_RB_WPTR_POLL_CNTL 7 7 SDMA1_GFX_RB_RPTR_ADDR_HI 8 8 SDMA1_GFX_RB_RPTR_ADDR_LO 9 9 SDMA1_GFX_IB_CNTL 10 10 SDMA1_GFX_IB_RPTR 11 11 SDMA1_GFX_IB_OFFSET 12 12 SDMA1_GFX_IB_BASE_LO 13 13 SDMA1_GFX_IB_BASE_HI 14 14 SDMA1_GFX_IB_SIZE 15 15 SDMA1_GFX_SKIP_CNTL 16 16 SDMA1_GFX_CONTEXT_STATUS 17 17 SDMA1_GFX_DOORBELL 18 18 SDMA1_GFX_CONTEXT_CNTL 19 19 mmSDMA1_CONTEXT_REG_TYPE1 0 0x58a9 15 0 1 SDMA1_GFX_STATUS 8 8 SDMA1_GFX_DOORBELL_LOG 9 9 SDMA1_GFX_WATERMARK 10 10 SDMA1_GFX_DOORBELL_OFFSET 11 11 SDMA1_GFX_CSA_ADDR_LO 12 12 SDMA1_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA1_GFX_IB_SUB_REMAIN 15 15 SDMA1_GFX_PREEMPT 16 16 SDMA1_GFX_DUMMY_REG 17 17 SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 18 18 SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 19 19 SDMA1_GFX_RB_AQL_CNTL 20 20 SDMA1_GFX_MINOR_PTR_UPDATE 21 21 RESERVED 24 31 mmSDMA1_CONTEXT_REG_TYPE2 0 0x58aa 13 0 1 SDMA1_GFX_MIDCMD_DATA0 0 0 SDMA1_GFX_MIDCMD_DATA1 1 1 SDMA1_GFX_MIDCMD_DATA2 2 2 SDMA1_GFX_MIDCMD_DATA3 3 3 SDMA1_GFX_MIDCMD_DATA4 4 4 SDMA1_GFX_MIDCMD_DATA5 5 5 SDMA1_GFX_MIDCMD_DATA6 6 6 SDMA1_GFX_MIDCMD_DATA7 7 7 SDMA1_GFX_MIDCMD_DATA8 8 8 SDMA1_GFX_MIDCMD_DATA9 9 9 SDMA1_GFX_MIDCMD_DATA10 10 10 SDMA1_GFX_MIDCMD_CNTL 11 11 RESERVED 12 31 mmSDMA1_CONTEXT_REG_TYPE3 0 0x58ab 1 0 1 RESERVED 0 31 mmSDMA1_PUB_REG_TYPE0 0 0x58ac 28 0 1 SDMA1_UCODE_ADDR 0 0 SDMA1_UCODE_DATA 1 1 SDMA1_VM_CTX_LO 2 2 SDMA1_VM_CTX_HI 3 3 SDMA1_ACTIVE_FCN_ID 4 4 SDMA1_VM_CTX_CNTL 5 5 SDMA1_VIRT_RESET_REQ 6 6 SDMA1_VF_ENABLE 7 7 SDMA1_CONTEXT_REG_TYPE0 8 8 SDMA1_CONTEXT_REG_TYPE1 9 9 SDMA1_CONTEXT_REG_TYPE2 10 10 SDMA1_CONTEXT_REG_TYPE3 11 11 SDMA1_PUB_REG_TYPE0 12 12 SDMA1_PUB_REG_TYPE1 13 13 SDMA1_PUB_REG_TYPE2 14 14 SDMA1_PUB_REG_TYPE3 15 15 SDMA1_VM_CNTL 19 19 RESERVED_FOR_PSPSMU_ACCESS_ONLY 20 21 SDMA1_PG_CNTL 22 22 SDMA1_PG_CTX_LO 23 23 SDMA1_PG_CTX_HI 24 24 SDMA1_PG_CTX_CNTL 25 25 SDMA1_POWER_CNTL 26 26 SDMA1_CLK_CTRL 27 27 SDMA1_CNTL 28 28 SDMA1_CHICKEN_BITS 29 29 SDMA1_GB_ADDR_CONFIG 30 30 SDMA1_GB_ADDR_CONFIG_READ 31 31 mmSDMA1_PUB_REG_TYPE1 0 0x58ad 28 0 1 SDMA1_RB_RPTR_FETCH_HI 0 0 SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 1 1 SDMA1_RB_RPTR_FETCH 2 2 SDMA1_IB_OFFSET_FETCH 3 3 SDMA1_PROGRAM 4 4 SDMA1_STATUS_REG 5 5 SDMA1_STATUS1_REG 6 6 SDMA1_RD_BURST_CNTL 7 7 SDMA1_HBM_PAGE_CONFIG 8 8 SDMA1_UCODE_CHECKSUM 9 9 SDMA1_F32_CNTL 10 10 SDMA1_FREEZE 11 11 SDMA1_PHASE0_QUANTUM 12 12 SDMA1_PHASE1_QUANTUM 13 13 SDMA1_EDC_CONFIG 18 18 SDMA1_BA_THRESHOLD 19 19 SDMA1_ID 20 20 SDMA1_VERSION 21 21 SDMA1_EDC_COUNTER 22 22 SDMA1_EDC_COUNTER_CLEAR 23 23 SDMA1_STATUS2_REG 24 24 SDMA1_ATOMIC_CNTL 25 25 SDMA1_ATOMIC_PREOP_LO 26 26 SDMA1_ATOMIC_PREOP_HI 27 27 SDMA1_UTCL1_CNTL 28 28 SDMA1_UTCL1_WATERMK 29 29 SDMA1_UTCL1_RD_STATUS 30 30 SDMA1_UTCL1_WR_STATUS 31 31 mmSDMA1_PUB_REG_TYPE2 0 0x58ae 27 0 1 SDMA1_UTCL1_INV0 0 0 SDMA1_UTCL1_INV1 1 1 SDMA1_UTCL1_INV2 2 2 SDMA1_UTCL1_RD_XNACK0 3 3 SDMA1_UTCL1_RD_XNACK1 4 4 SDMA1_UTCL1_WR_XNACK0 5 5 SDMA1_UTCL1_WR_XNACK1 6 6 SDMA1_UTCL1_TIMEOUT 7 7 SDMA1_UTCL1_PAGE 8 8 SDMA1_RELAX_ORDERING_LUT 10 10 SDMA1_CHICKEN_BITS_2 11 11 SDMA1_STATUS3_REG 12 12 SDMA1_PHYSICAL_ADDR_LO 13 13 SDMA1_PHYSICAL_ADDR_HI 14 14 SDMA1_PHASE2_QUANTUM 15 15 SDMA1_ERROR_LOG 16 16 SDMA1_PUB_DUMMY_REG0 17 17 SDMA1_PUB_DUMMY_REG1 18 18 SDMA1_PUB_DUMMY_REG2 19 19 SDMA1_PUB_DUMMY_REG3 20 20 SDMA1_F32_COUNTER 21 21 SDMA1_PERFCNT_PERFCOUNTER0_CFG 23 23 SDMA1_PERFCNT_PERFCOUNTER1_CFG 24 24 SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 25 25 SDMA1_PERFCNT_MISC_CNTL 26 26 SDMA1_CRD_CNTL 27 27 SDMA1_AQL_STATUS 31 31 mmSDMA1_PUB_REG_TYPE3 0 0x58af 25 0 1 SDMA1_EA_DBIT_ADDR_DATA 0 0 SDMA1_EA_DBIT_ADDR_INDEX 1 1 SDMA1_TLBI_GCR_CNTL 2 2 SDMA1_TILING_CONFIG 3 3 SDMA1_PERFCOUNTER0_SELECT 8 8 SDMA1_PERFCOUNTER0_SELECT1 9 9 SDMA1_PERFCOUNTER0_LO 10 10 SDMA1_PERFCOUNTER0_HI 11 11 SDMA1_PERFCOUNTER1_SELECT 12 12 SDMA1_PERFCOUNTER1_SELECT1 13 13 SDMA1_PERFCOUNTER1_LO 14 14 SDMA1_PERFCOUNTER1_HI 15 15 SDMA1_INT_STATUS 16 16 SDMA1_HOLE_ADDR_LO 18 18 SDMA1_HOLE_ADDR_HI 19 19 SDMA1_CLOCK_GATING_REG 21 21 SDMA1_STATUS4_REG 22 22 SDMA1_SCRATCH_RAM_DATA 23 23 SDMA1_SCRATCH_RAM_ADDR 24 24 SDMA1_TIMESTAMP_CNTL 25 25 SDMA1_PERFCNT_PERFCOUNTER_LO 26 26 SDMA1_PERFCNT_PERFCOUNTER_HI 27 27 SDMA1_STATUS5_REG 28 28 SDMA1_QUEUE_RESET_REQ 29 29 RESERVED 30 31 mmSDMA1_VM_CNTL 0 0x58b3 1 0 1 CMD 0 3 mmSDMA2_UCODE_ADDR 0 0x58c0 1 0 1 VALUE 0 13 mmSDMA2_UCODE_DATA 0 0x58c1 1 0 1 VALUE 0 31 mmSDMA2_VM_CTX_LO 0 0x58c2 1 0 1 ADDR 2 31 mmSDMA2_VM_CTX_HI 0 0x58c3 1 0 1 ADDR 0 31 mmSDMA2_ACTIVE_FCN_ID 0 0x58c4 3 0 1 VFID 0 4 RESERVED 5 30 VF 31 31 mmSDMA2_VM_CTX_CNTL 0 0x58c5 2 0 1 PRIV 0 0 VMID 4 7 mmSDMA2_VIRT_RESET_REQ 0 0x58c6 2 0 1 VF 0 30 PF 31 31 mmSDMA2_VF_ENABLE 0 0x58c7 1 0 1 VF_ENABLE 0 0 mmSDMA2_CONTEXT_REG_TYPE0 0 0x58c8 20 0 1 SDMA2_GFX_RB_CNTL 0 0 SDMA2_GFX_RB_BASE 1 1 SDMA2_GFX_RB_BASE_HI 2 2 SDMA2_GFX_RB_RPTR 3 3 SDMA2_GFX_RB_RPTR_HI 4 4 SDMA2_GFX_RB_WPTR 5 5 SDMA2_GFX_RB_WPTR_HI 6 6 SDMA2_GFX_RB_WPTR_POLL_CNTL 7 7 SDMA2_GFX_RB_RPTR_ADDR_HI 8 8 SDMA2_GFX_RB_RPTR_ADDR_LO 9 9 SDMA2_GFX_IB_CNTL 10 10 SDMA2_GFX_IB_RPTR 11 11 SDMA2_GFX_IB_OFFSET 12 12 SDMA2_GFX_IB_BASE_LO 13 13 SDMA2_GFX_IB_BASE_HI 14 14 SDMA2_GFX_IB_SIZE 15 15 SDMA2_GFX_SKIP_CNTL 16 16 SDMA2_GFX_CONTEXT_STATUS 17 17 SDMA2_GFX_DOORBELL 18 18 SDMA2_GFX_CONTEXT_CNTL 19 19 mmSDMA2_CONTEXT_REG_TYPE1 0 0x58c9 15 0 1 SDMA2_GFX_STATUS 8 8 SDMA2_GFX_DOORBELL_LOG 9 9 SDMA2_GFX_WATERMARK 10 10 SDMA2_GFX_DOORBELL_OFFSET 11 11 SDMA2_GFX_CSA_ADDR_LO 12 12 SDMA2_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA2_GFX_IB_SUB_REMAIN 15 15 SDMA2_GFX_PREEMPT 16 16 SDMA2_GFX_DUMMY_REG 17 17 SDMA2_GFX_RB_WPTR_POLL_ADDR_HI 18 18 SDMA2_GFX_RB_WPTR_POLL_ADDR_LO 19 19 SDMA2_GFX_RB_AQL_CNTL 20 20 SDMA2_GFX_MINOR_PTR_UPDATE 21 21 RESERVED 24 31 mmSDMA2_CONTEXT_REG_TYPE2 0 0x58ca 13 0 1 SDMA2_GFX_MIDCMD_DATA0 0 0 SDMA2_GFX_MIDCMD_DATA1 1 1 SDMA2_GFX_MIDCMD_DATA2 2 2 SDMA2_GFX_MIDCMD_DATA3 3 3 SDMA2_GFX_MIDCMD_DATA4 4 4 SDMA2_GFX_MIDCMD_DATA5 5 5 SDMA2_GFX_MIDCMD_DATA6 6 6 SDMA2_GFX_MIDCMD_DATA7 7 7 SDMA2_GFX_MIDCMD_DATA8 8 8 SDMA2_GFX_MIDCMD_DATA9 9 9 SDMA2_GFX_MIDCMD_DATA10 10 10 SDMA2_GFX_MIDCMD_CNTL 11 11 RESERVED 12 31 mmSDMA2_CONTEXT_REG_TYPE3 0 0x58cb 1 0 1 RESERVED 0 31 mmSDMA2_PUB_REG_TYPE0 0 0x58cc 28 0 1 SDMA2_UCODE_ADDR 0 0 SDMA2_UCODE_DATA 1 1 SDMA2_VM_CTX_LO 2 2 SDMA2_VM_CTX_HI 3 3 SDMA2_ACTIVE_FCN_ID 4 4 SDMA2_VM_CTX_CNTL 5 5 SDMA2_VIRT_RESET_REQ 6 6 SDMA2_VF_ENABLE 7 7 SDMA2_CONTEXT_REG_TYPE0 8 8 SDMA2_CONTEXT_REG_TYPE1 9 9 SDMA2_CONTEXT_REG_TYPE2 10 10 SDMA2_CONTEXT_REG_TYPE3 11 11 SDMA2_PUB_REG_TYPE0 12 12 SDMA2_PUB_REG_TYPE1 13 13 SDMA2_PUB_REG_TYPE2 14 14 SDMA2_PUB_REG_TYPE3 15 15 SDMA2_VM_CNTL 19 19 RESERVED_FOR_PSPSMU_ACCESS_ONLY 20 21 SDMA2_PG_CNTL 22 22 SDMA2_PG_CTX_LO 23 23 SDMA2_PG_CTX_HI 24 24 SDMA2_PG_CTX_CNTL 25 25 SDMA2_POWER_CNTL 26 26 SDMA2_CLK_CTRL 27 27 SDMA2_CNTL 28 28 SDMA2_CHICKEN_BITS 29 29 SDMA2_GB_ADDR_CONFIG 30 30 SDMA2_GB_ADDR_CONFIG_READ 31 31 mmSDMA2_PUB_REG_TYPE1 0 0x58cd 28 0 1 SDMA2_RB_RPTR_FETCH_HI 0 0 SDMA2_SEM_WAIT_FAIL_TIMER_CNTL 1 1 SDMA2_RB_RPTR_FETCH 2 2 SDMA2_IB_OFFSET_FETCH 3 3 SDMA2_PROGRAM 4 4 SDMA2_STATUS_REG 5 5 SDMA2_STATUS1_REG 6 6 SDMA2_RD_BURST_CNTL 7 7 SDMA2_HBM_PAGE_CONFIG 8 8 SDMA2_UCODE_CHECKSUM 9 9 SDMA2_F32_CNTL 10 10 SDMA2_FREEZE 11 11 SDMA2_PHASE0_QUANTUM 12 12 SDMA2_PHASE1_QUANTUM 13 13 SDMA2_EDC_CONFIG 18 18 SDMA2_BA_THRESHOLD 19 19 SDMA2_ID 20 20 SDMA2_VERSION 21 21 SDMA2_EDC_COUNTER 22 22 SDMA2_EDC_COUNTER_CLEAR 23 23 SDMA2_STATUS2_REG 24 24 SDMA2_ATOMIC_CNTL 25 25 SDMA2_ATOMIC_PREOP_LO 26 26 SDMA2_ATOMIC_PREOP_HI 27 27 SDMA2_UTCL1_CNTL 28 28 SDMA2_UTCL1_WATERMK 29 29 SDMA2_UTCL1_RD_STATUS 30 30 SDMA2_UTCL1_WR_STATUS 31 31 mmSDMA2_PUB_REG_TYPE2 0 0x58ce 27 0 1 SDMA2_UTCL1_INV0 0 0 SDMA2_UTCL1_INV1 1 1 SDMA2_UTCL1_INV2 2 2 SDMA2_UTCL1_RD_XNACK0 3 3 SDMA2_UTCL1_RD_XNACK1 4 4 SDMA2_UTCL1_WR_XNACK0 5 5 SDMA2_UTCL1_WR_XNACK1 6 6 SDMA2_UTCL1_TIMEOUT 7 7 SDMA2_UTCL1_PAGE 8 8 SDMA2_RELAX_ORDERING_LUT 10 10 SDMA2_CHICKEN_BITS_2 11 11 SDMA2_STATUS3_REG 12 12 SDMA2_PHYSICAL_ADDR_LO 13 13 SDMA2_PHYSICAL_ADDR_HI 14 14 SDMA2_PHASE2_QUANTUM 15 15 SDMA2_ERROR_LOG 16 16 SDMA2_PUB_DUMMY_REG0 17 17 SDMA2_PUB_DUMMY_REG1 18 18 SDMA2_PUB_DUMMY_REG2 19 19 SDMA2_PUB_DUMMY_REG3 20 20 SDMA2_F32_COUNTER 21 21 SDMA2_PERFCNT_PERFCOUNTER0_CFG 23 23 SDMA2_PERFCNT_PERFCOUNTER1_CFG 24 24 SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 25 25 SDMA2_PERFCNT_MISC_CNTL 26 26 SDMA2_CRD_CNTL 27 27 SDMA2_AQL_STATUS 31 31 mmSDMA2_PUB_REG_TYPE3 0 0x58cf 25 0 1 SDMA2_EA_DBIT_ADDR_DATA 0 0 SDMA2_EA_DBIT_ADDR_INDEX 1 1 SDMA2_TLBI_GCR_CNTL 2 2 SDMA2_TILING_CONFIG 3 3 SDMA2_PERFCOUNTER0_SELECT 8 8 SDMA2_PERFCOUNTER0_SELECT1 9 9 SDMA2_PERFCOUNTER0_LO 10 10 SDMA2_PERFCOUNTER0_HI 11 11 SDMA2_PERFCOUNTER1_SELECT 12 12 SDMA2_PERFCOUNTER1_SELECT1 13 13 SDMA2_PERFCOUNTER1_LO 14 14 SDMA2_PERFCOUNTER1_HI 15 15 SDMA2_INT_STATUS 16 16 SDMA2_HOLE_ADDR_LO 18 18 SDMA2_HOLE_ADDR_HI 19 19 SDMA2_CLOCK_GATING_REG 21 21 SDMA2_STATUS4_REG 22 22 SDMA2_SCRATCH_RAM_DATA 23 23 SDMA2_SCRATCH_RAM_ADDR 24 24 SDMA2_TIMESTAMP_CNTL 25 25 SDMA2_PERFCNT_PERFCOUNTER_LO 26 26 SDMA2_PERFCNT_PERFCOUNTER_HI 27 27 SDMA2_STATUS5_REG 28 28 SDMA2_QUEUE_RESET_REQ 29 29 RESERVED 30 31 mmSDMA2_VM_CNTL 0 0x58d3 1 0 1 CMD 0 3 mmSDMA3_UCODE_ADDR 0 0x58e0 1 0 1 VALUE 0 13 mmSDMA3_UCODE_DATA 0 0x58e1 1 0 1 VALUE 0 31 mmSDMA3_VM_CTX_LO 0 0x58e2 1 0 1 ADDR 2 31 mmSDMA3_VM_CTX_HI 0 0x58e3 1 0 1 ADDR 0 31 mmSDMA3_ACTIVE_FCN_ID 0 0x58e4 3 0 1 VFID 0 4 RESERVED 5 30 VF 31 31 mmSDMA3_VM_CTX_CNTL 0 0x58e5 2 0 1 PRIV 0 0 VMID 4 7 mmSDMA3_VIRT_RESET_REQ 0 0x58e6 2 0 1 VF 0 30 PF 31 31 mmSDMA3_VF_ENABLE 0 0x58e7 1 0 1 VF_ENABLE 0 0 mmSDMA3_CONTEXT_REG_TYPE0 0 0x58e8 20 0 1 SDMA3_GFX_RB_CNTL 0 0 SDMA3_GFX_RB_BASE 1 1 SDMA3_GFX_RB_BASE_HI 2 2 SDMA3_GFX_RB_RPTR 3 3 SDMA3_GFX_RB_RPTR_HI 4 4 SDMA3_GFX_RB_WPTR 5 5 SDMA3_GFX_RB_WPTR_HI 6 6 SDMA3_GFX_RB_WPTR_POLL_CNTL 7 7 SDMA3_GFX_RB_RPTR_ADDR_HI 8 8 SDMA3_GFX_RB_RPTR_ADDR_LO 9 9 SDMA3_GFX_IB_CNTL 10 10 SDMA3_GFX_IB_RPTR 11 11 SDMA3_GFX_IB_OFFSET 12 12 SDMA3_GFX_IB_BASE_LO 13 13 SDMA3_GFX_IB_BASE_HI 14 14 SDMA3_GFX_IB_SIZE 15 15 SDMA3_GFX_SKIP_CNTL 16 16 SDMA3_GFX_CONTEXT_STATUS 17 17 SDMA3_GFX_DOORBELL 18 18 SDMA3_GFX_CONTEXT_CNTL 19 19 mmSDMA3_CONTEXT_REG_TYPE1 0 0x58e9 15 0 1 SDMA3_GFX_STATUS 8 8 SDMA3_GFX_DOORBELL_LOG 9 9 SDMA3_GFX_WATERMARK 10 10 SDMA3_GFX_DOORBELL_OFFSET 11 11 SDMA3_GFX_CSA_ADDR_LO 12 12 SDMA3_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA3_GFX_IB_SUB_REMAIN 15 15 SDMA3_GFX_PREEMPT 16 16 SDMA3_GFX_DUMMY_REG 17 17 SDMA3_GFX_RB_WPTR_POLL_ADDR_HI 18 18 SDMA3_GFX_RB_WPTR_POLL_ADDR_LO 19 19 SDMA3_GFX_RB_AQL_CNTL 20 20 SDMA3_GFX_MINOR_PTR_UPDATE 21 21 RESERVED 24 31 mmSDMA3_CONTEXT_REG_TYPE2 0 0x58ea 13 0 1 SDMA3_GFX_MIDCMD_DATA0 0 0 SDMA3_GFX_MIDCMD_DATA1 1 1 SDMA3_GFX_MIDCMD_DATA2 2 2 SDMA3_GFX_MIDCMD_DATA3 3 3 SDMA3_GFX_MIDCMD_DATA4 4 4 SDMA3_GFX_MIDCMD_DATA5 5 5 SDMA3_GFX_MIDCMD_DATA6 6 6 SDMA3_GFX_MIDCMD_DATA7 7 7 SDMA3_GFX_MIDCMD_DATA8 8 8 SDMA3_GFX_MIDCMD_DATA9 9 9 SDMA3_GFX_MIDCMD_DATA10 10 10 SDMA3_GFX_MIDCMD_CNTL 11 11 RESERVED 12 31 mmSDMA3_CONTEXT_REG_TYPE3 0 0x58eb 1 0 1 RESERVED 0 31 mmSDMA3_PUB_REG_TYPE0 0 0x58ec 28 0 1 SDMA3_UCODE_ADDR 0 0 SDMA3_UCODE_DATA 1 1 SDMA3_VM_CTX_LO 2 2 SDMA3_VM_CTX_HI 3 3 SDMA3_ACTIVE_FCN_ID 4 4 SDMA3_VM_CTX_CNTL 5 5 SDMA3_VIRT_RESET_REQ 6 6 SDMA3_VF_ENABLE 7 7 SDMA3_CONTEXT_REG_TYPE0 8 8 SDMA3_CONTEXT_REG_TYPE1 9 9 SDMA3_CONTEXT_REG_TYPE2 10 10 SDMA3_CONTEXT_REG_TYPE3 11 11 SDMA3_PUB_REG_TYPE0 12 12 SDMA3_PUB_REG_TYPE1 13 13 SDMA3_PUB_REG_TYPE2 14 14 SDMA3_PUB_REG_TYPE3 15 15 SDMA3_VM_CNTL 19 19 RESERVED_FOR_PSPSMU_ACCESS_ONLY 20 21 SDMA3_PG_CNTL 22 22 SDMA3_PG_CTX_LO 23 23 SDMA3_PG_CTX_HI 24 24 SDMA3_PG_CTX_CNTL 25 25 SDMA3_POWER_CNTL 26 26 SDMA3_CLK_CTRL 27 27 SDMA3_CNTL 28 28 SDMA3_CHICKEN_BITS 29 29 SDMA3_GB_ADDR_CONFIG 30 30 SDMA3_GB_ADDR_CONFIG_READ 31 31 mmSDMA3_PUB_REG_TYPE1 0 0x58ed 28 0 1 SDMA3_RB_RPTR_FETCH_HI 0 0 SDMA3_SEM_WAIT_FAIL_TIMER_CNTL 1 1 SDMA3_RB_RPTR_FETCH 2 2 SDMA3_IB_OFFSET_FETCH 3 3 SDMA3_PROGRAM 4 4 SDMA3_STATUS_REG 5 5 SDMA3_STATUS1_REG 6 6 SDMA3_RD_BURST_CNTL 7 7 SDMA3_HBM_PAGE_CONFIG 8 8 SDMA3_UCODE_CHECKSUM 9 9 SDMA3_F32_CNTL 10 10 SDMA3_FREEZE 11 11 SDMA3_PHASE0_QUANTUM 12 12 SDMA3_PHASE1_QUANTUM 13 13 SDMA3_EDC_CONFIG 18 18 SDMA3_BA_THRESHOLD 19 19 SDMA3_ID 20 20 SDMA3_VERSION 21 21 SDMA3_EDC_COUNTER 22 22 SDMA3_EDC_COUNTER_CLEAR 23 23 SDMA3_STATUS2_REG 24 24 SDMA3_ATOMIC_CNTL 25 25 SDMA3_ATOMIC_PREOP_LO 26 26 SDMA3_ATOMIC_PREOP_HI 27 27 SDMA3_UTCL1_CNTL 28 28 SDMA3_UTCL1_WATERMK 29 29 SDMA3_UTCL1_RD_STATUS 30 30 SDMA3_UTCL1_WR_STATUS 31 31 mmSDMA3_PUB_REG_TYPE2 0 0x58ee 27 0 1 SDMA3_UTCL1_INV0 0 0 SDMA3_UTCL1_INV1 1 1 SDMA3_UTCL1_INV2 2 2 SDMA3_UTCL1_RD_XNACK0 3 3 SDMA3_UTCL1_RD_XNACK1 4 4 SDMA3_UTCL1_WR_XNACK0 5 5 SDMA3_UTCL1_WR_XNACK1 6 6 SDMA3_UTCL1_TIMEOUT 7 7 SDMA3_UTCL1_PAGE 8 8 SDMA3_RELAX_ORDERING_LUT 10 10 SDMA3_CHICKEN_BITS_2 11 11 SDMA3_STATUS3_REG 12 12 SDMA3_PHYSICAL_ADDR_LO 13 13 SDMA3_PHYSICAL_ADDR_HI 14 14 SDMA3_PHASE2_QUANTUM 15 15 SDMA3_ERROR_LOG 16 16 SDMA3_PUB_DUMMY_REG0 17 17 SDMA3_PUB_DUMMY_REG1 18 18 SDMA3_PUB_DUMMY_REG2 19 19 SDMA3_PUB_DUMMY_REG3 20 20 SDMA3_F32_COUNTER 21 21 SDMA3_PERFCNT_PERFCOUNTER0_CFG 23 23 SDMA3_PERFCNT_PERFCOUNTER1_CFG 24 24 SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 25 25 SDMA3_PERFCNT_MISC_CNTL 26 26 SDMA3_CRD_CNTL 27 27 SDMA3_AQL_STATUS 31 31 mmSDMA3_PUB_REG_TYPE3 0 0x58ef 25 0 1 SDMA3_EA_DBIT_ADDR_DATA 0 0 SDMA3_EA_DBIT_ADDR_INDEX 1 1 SDMA3_TLBI_GCR_CNTL 2 2 SDMA3_TILING_CONFIG 3 3 SDMA3_PERFCOUNTER0_SELECT 8 8 SDMA3_PERFCOUNTER0_SELECT1 9 9 SDMA3_PERFCOUNTER0_LO 10 10 SDMA3_PERFCOUNTER0_HI 11 11 SDMA3_PERFCOUNTER1_SELECT 12 12 SDMA3_PERFCOUNTER1_SELECT1 13 13 SDMA3_PERFCOUNTER1_LO 14 14 SDMA3_PERFCOUNTER1_HI 15 15 SDMA3_INT_STATUS 16 16 SDMA3_HOLE_ADDR_LO 18 18 SDMA3_HOLE_ADDR_HI 19 19 SDMA3_CLOCK_GATING_REG 21 21 SDMA3_STATUS4_REG 22 22 SDMA3_SCRATCH_RAM_DATA 23 23 SDMA3_SCRATCH_RAM_ADDR 24 24 SDMA3_TIMESTAMP_CNTL 25 25 SDMA3_PERFCNT_PERFCOUNTER_LO 26 26 SDMA3_PERFCNT_PERFCOUNTER_HI 27 27 SDMA3_STATUS5_REG 28 28 SDMA3_QUEUE_RESET_REQ 29 29 RESERVED 30 31 mmSDMA3_VM_CNTL 0 0x58f3 1 0 1 CMD 0 3 mmGCMC_VM_FB_SIZE_OFFSET_VF0 0 0x5a80 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF1 0 0x5a81 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF2 0 0x5a82 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF3 0 0x5a83 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF4 0 0x5a84 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF5 0 0x5a85 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF6 0 0x5a86 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF7 0 0x5a87 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF8 0 0x5a88 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF9 0 0x5a89 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF10 0 0x5a8a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF11 0 0x5a8b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF12 0 0x5a8c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF13 0 0x5a8d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF14 0 0x5a8e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF15 0 0x5a8f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF16 0 0x5a90 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF17 0 0x5a91 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF18 0 0x5a92 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF19 0 0x5a93 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF20 0 0x5a94 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF21 0 0x5a95 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF22 0 0x5a96 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF23 0 0x5a97 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF24 0 0x5a98 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF25 0 0x5a99 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF26 0 0x5a9a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF27 0 0x5a9b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF28 0 0x5a9c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF29 0 0x5a9d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF30 0 0x5a9e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCMC_VM_FB_SIZE_OFFSET_VF31 0 0x5a9f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmGCVM_IOMMU_MMIO_CNTRL_1 0 0x5aa0 1 0 1 MARC_EN 8 8 mmGCMC_VM_MARC_BASE_LO_0 0 0x5aa1 1 0 1 MARC_BASE_LO_0 12 31 mmGCMC_VM_MARC_BASE_LO_1 0 0x5aa2 1 0 1 MARC_BASE_LO_1 12 31 mmGCMC_VM_MARC_BASE_LO_2 0 0x5aa3 1 0 1 MARC_BASE_LO_2 12 31 mmGCMC_VM_MARC_BASE_LO_3 0 0x5aa4 1 0 1 MARC_BASE_LO_3 12 31 mmGCMC_VM_MARC_BASE_HI_0 0 0x5aa5 1 0 1 MARC_BASE_HI_0 0 19 mmGCMC_VM_MARC_BASE_HI_1 0 0x5aa6 1 0 1 MARC_BASE_HI_1 0 19 mmGCMC_VM_MARC_BASE_HI_2 0 0x5aa7 1 0 1 MARC_BASE_HI_2 0 19 mmGCMC_VM_MARC_BASE_HI_3 0 0x5aa8 1 0 1 MARC_BASE_HI_3 0 19 mmGCMC_VM_MARC_RELOC_LO_0 0 0x5aa9 3 0 1 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmGCMC_VM_MARC_RELOC_LO_1 0 0x5aaa 3 0 1 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmGCMC_VM_MARC_RELOC_LO_2 0 0x5aab 3 0 1 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmGCMC_VM_MARC_RELOC_LO_3 0 0x5aac 3 0 1 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmGCMC_VM_MARC_RELOC_HI_0 0 0x5aad 1 0 1 MARC_RELOC_HI_0 0 19 mmGCMC_VM_MARC_RELOC_HI_1 0 0x5aae 1 0 1 MARC_RELOC_HI_1 0 19 mmGCMC_VM_MARC_RELOC_HI_2 0 0x5aaf 1 0 1 MARC_RELOC_HI_2 0 19 mmGCMC_VM_MARC_RELOC_HI_3 0 0x5ab0 1 0 1 MARC_RELOC_HI_3 0 19 mmGCMC_VM_MARC_LEN_LO_0 0 0x5ab1 1 0 1 MARC_LEN_LO_0 12 31 mmGCMC_VM_MARC_LEN_LO_1 0 0x5ab2 1 0 1 MARC_LEN_LO_1 12 31 mmGCMC_VM_MARC_LEN_LO_2 0 0x5ab3 1 0 1 MARC_LEN_LO_2 12 31 mmGCMC_VM_MARC_LEN_LO_3 0 0x5ab4 1 0 1 MARC_LEN_LO_3 12 31 mmGCMC_VM_MARC_LEN_HI_0 0 0x5ab5 1 0 1 MARC_LEN_HI_0 0 19 mmGCMC_VM_MARC_LEN_HI_1 0 0x5ab6 1 0 1 MARC_LEN_HI_1 0 19 mmGCMC_VM_MARC_LEN_HI_2 0 0x5ab7 1 0 1 MARC_LEN_HI_2 0 19 mmGCMC_VM_MARC_LEN_HI_3 0 0x5ab8 1 0 1 MARC_LEN_HI_3 0 19 mmGCVM_IOMMU_CONTROL_REGISTER 0 0x5ab9 1 0 1 IOMMUEN 0 0 mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0 0x5aba 1 0 1 PERFOPTEN 13 13 mmGCMC_VM_XGMI_GPUIOV_ENABLE 0 0x5abb 32 0 1 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_VF16 16 16 ENABLE_VF17 17 17 ENABLE_VF18 18 18 ENABLE_VF19 19 19 ENABLE_VF20 20 20 ENABLE_VF21 21 21 ENABLE_VF22 22 22 ENABLE_VF23 23 23 ENABLE_VF24 24 24 ENABLE_VF25 25 25 ENABLE_VF26 26 26 ENABLE_VF27 27 27 ENABLE_VF28 28 28 ENABLE_VF29 29 29 ENABLE_VF30 30 30 ENABLE_PF 31 31 mmCPG_PSP_DEBUG 0 0x5c10 1 0 1 GPA_OVERRIDE 3 3 mmCPC_PSP_DEBUG 0 0x5c11 1 0 1 GPA_OVERRIDE 3 3 mmGRBM_SEC_CNTL 0 0x5e0d 0 0 1 mmRLC_FWL_FIRST_VIOL_ADDR 0 0x5f12 4 0 1 VIOL_ADDR 0 17 VIOL_APERTURE_ID 18 29 VIOL_OP 30 30 RESERVED 31 31 mmRLC_SRM_FWL_FIRST_VIOL_ADDR 0 0x5f3d 3 0 1 VIOL_ADDR 0 17 VIOL_OP 18 18 RESERVED 19 31 mmGCVM_L2_ID_CTRL0 0 0x5dc0 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL1 0 0x5dc1 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL2 0 0x5dc2 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL3 0 0x5dc3 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL4 0 0x5dc4 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL5 0 0x5dc5 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL6 0 0x5dc6 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL7 0 0x5dc7 2 0 1 VMID0_EN 0 15 VMID1_EN 16 31 mmGCVM_L2_ID_CTRL_HI 0 0x5dc8 1 0 1 VMID_EN_HI 0 15 mmGCVM_L2_ID_STATUS 0 0x5dc9 4 0 1 VMID_FAULT 0 3 CLIENTID_FAULT 4 12 GRPID_FAULT 13 16 VMID_INTR_ON 31 31 mmGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0 0x5dcb 2 0 1 TRANS_BYPASS_VMIDS 0 15 GPA_MODE_VMIDS 16 31 mmGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0 0x5dcd 1 0 1 GPU_HOST_TRANSLATION_ENABLE 0 0 mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0 0x5dce 1 0 1 ADDR 0 31 mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0 0x5dcf 10 0 1 ADDR 0 3 VMID 4 7 VFID 8 12 VF 13 13 GPA 14 15 RD_PERM 16 16 WR_PERM 17 17 EX_PERM 18 18 CLIENT_ID 19 27 REQ 31 31 mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0 0x5dd0 1 0 1 ADDR 0 31 mmGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0 0x5dd1 12 0 1 ADDR 0 3 PERMS 4 6 FRAGMENT_SIZE 7 12 SNOOP 13 13 SPA 14 14 IO 15 15 NO_PTE 17 17 MTYPE 18 20 MEMLOG 21 21 NACK 22 23 LLC_NOALLOC 24 24 ACK 31 31 mmSDMA2_DEC_START 0 0x0 1 0 2 START 0 31 mmSDMA2_GLOBAL_TIMESTAMP_LO 0 0xf 1 0 2 DATA 0 31 mmSDMA2_GLOBAL_TIMESTAMP_HI 0 0x10 1 0 2 DATA 0 31 mmSDMA2_PG_CNTL 0 0x16 2 0 2 CMD 0 3 STATUS 16 19 mmSDMA2_PG_CTX_LO 0 0x17 1 0 2 ADDR 0 31 mmSDMA2_PG_CTX_HI 0 0x18 1 0 2 ADDR 0 31 mmSDMA2_PG_CTX_CNTL 0 0x19 1 0 2 VMID 4 7 mmSDMA2_POWER_CNTL 0 0x1a 6 0 2 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 ON_OFF_STATUS_DURATION_TIME 26 31 mmSDMA2_CLK_CTRL 0 0x1b 10 0 2 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED_24_12 12 24 CGCG_EN_OVERRIDE 25 25 SOFT_OVERRIDE4 26 26 SOFT_OVERRIDE3 27 27 SOFT_OVERRIDE2 28 28 SOFT_OVERRIDE1 29 29 SOFT_OVERRIDE0 30 30 SOFT_OVERRIDER_REG 31 31 mmSDMA2_CNTL 0 0x1c 13 0 2 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 PAGE_INT_ENABLE 7 7 CH_PERFCNT_ENABLE 16 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA2_CHICKEN_BITS 0 0x1d 20 0 2 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 SOFT_OVERRIDE_DCGE 4 4 SOFT_OVERRIDE_SDMA_GRBM_FGCG 5 5 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 T2L_256B_ENABLE 18 18 GCR_FGCG_ENABLE 19 19 SRBM_POLL_RETRYING 20 20 CH_FGCG_ENABLE 21 21 UTCL2_INVREQ_FGCG_ENABLE 22 22 CG_STATUS_OUTPUT 23 23 UTCL1_FGCG_ENABLE 24 24 TIME_BASED_QOS 25 25 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA2_GB_ADDR_CONFIG 0 0x1e 6 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA2_GB_ADDR_CONFIG_READ 0 0x1f 6 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA2_RB_RPTR_FETCH_HI 0 0x20 1 0 2 OFFSET 0 31 mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0 0x21 1 0 2 TIMER 0 31 mmSDMA2_RB_RPTR_FETCH 0 0x22 1 0 2 OFFSET 2 31 mmSDMA2_IB_OFFSET_FETCH 0 0x23 1 0 2 OFFSET 2 21 mmSDMA2_PROGRAM 0 0x24 1 0 2 STREAM 0 31 mmSDMA2_STATUS_REG 0 0x25 29 0 2 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA2_STATUS1_REG 0 0x26 14 0 2 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA2_RD_BURST_CNTL 0 0x27 1 0 2 RD_BURST 0 1 mmSDMA2_HBM_PAGE_CONFIG 0 0x28 1 0 2 PAGE_SIZE_EXPONENT 0 0 mmSDMA2_UCODE_CHECKSUM 0 0x29 1 0 2 DATA 0 31 mmSDMA2_F32_CNTL 0 0x2a 4 0 2 HALT 0 0 STEP 1 1 CHECKSUM_CLR 8 8 RESET 9 9 mmSDMA2_FREEZE 0 0x2b 5 0 2 PREEMPT 0 0 FORCE_PREEMPT 1 1 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA2_PHASE0_QUANTUM 0 0x2c 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA2_PHASE1_QUANTUM 0 0x2d 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA2_EDC_CONFIG 0 0x32 2 0 2 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA2_BA_THRESHOLD 0 0x33 2 0 2 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA2_ID 0 0x34 1 0 2 DEVICE_ID 0 7 mmSDMA2_VERSION 0 0x35 3 0 2 MINVER 0 6 MAJVER 8 14 REV 16 21 mmSDMA2_EDC_COUNTER 0 0x36 17 0 2 SDMA_UCODE_BUF_DED 0 0 SDMA_UCODE_BUF_SEC 1 1 SDMA_RB_CMD_BUF_SED 2 2 SDMA_IB_CMD_BUF_SED 3 3 SDMA_UTCL1_RD_FIFO_SED 4 4 SDMA_UTCL1_RDBST_FIFO_SED 5 5 SDMA_DATA_LUT_FIFO_SED 6 6 SDMA_MBANK_DATA_BUF0_SED 7 7 SDMA_MBANK_DATA_BUF1_SED 8 8 SDMA_MBANK_DATA_BUF2_SED 9 9 SDMA_MBANK_DATA_BUF3_SED 10 10 SDMA_MBANK_DATA_BUF4_SED 11 11 SDMA_MBANK_DATA_BUF5_SED 12 12 SDMA_MBANK_DATA_BUF6_SED 13 13 SDMA_MBANK_DATA_BUF7_SED 14 14 SDMA_SPLIT_DAT_BUF_SED 15 15 SDMA_MC_WR_ADDR_FIFO_SED 16 16 mmSDMA2_EDC_COUNTER_CLEAR 0 0x37 1 0 2 DUMMY 0 0 mmSDMA2_STATUS2_REG 0 0x38 3 0 2 ID 0 1 F32_INSTR_PTR 2 15 CMD_OP 16 31 mmSDMA2_ATOMIC_CNTL 0 0x39 2 0 2 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA2_ATOMIC_PREOP_LO 0 0x3a 1 0 2 DATA 0 31 mmSDMA2_ATOMIC_PREOP_HI 0 0x3b 1 0 2 DATA 0 31 mmSDMA2_UTCL1_CNTL 0 0x3c 9 0 2 REDO_ENABLE 0 0 REDO_DELAY 1 5 REDO_WATERMK 6 8 RESP_MODE 9 11 FORCE_INVALIDATION 14 14 FORCE_INVREQ_HEAVY 15 15 INVACK_DELAY 16 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 mmSDMA2_UTCL1_WATERMK 0 0x3d 4 0 2 REQMC_WATERMK 0 9 REQPG_WATERMK 10 17 INVREQ_WATERMK 18 25 XNACK_WATERMK 26 31 mmSDMA2_UTCL1_RD_STATUS 0 0x3e 27 0 2 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_RD_VECTOR 17 20 MERGE_STATE 21 23 ADDR_RD_RTR 24 24 RD_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 HIT_CACHE 27 27 RD_DCC_ENABLE 28 28 NACK_TIMEOUT_SW 29 29 DCC_PAGE_FAULT 30 30 DCC_PAGE_NULL 31 31 mmSDMA2_UTCL1_WR_STATUS 0 0x3f 27 0 2 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_WR_VECTOR 17 20 MERGE_STATE 21 23 F32_WR_RTR 24 24 WR_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 ATOMIC_OP 27 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 mmSDMA2_UTCL1_INV0 0 0x40 14 0 2 CPF_INVREQ_EN 0 0 GPUVM_INVREQ_EN 1 1 CPF_GPA_INVREQ 2 2 GPUVM_INVREQ_LOW 3 3 GPUVM_INVREQ_HIGH 4 4 INVREQ_SIZE 5 10 INVREQ_IDLE 11 11 VMINV_PEND_CNT 12 15 GPUVM_LO_INV_VMID 16 19 GPUVM_HI_INV_VMID 20 23 GPUVM_INV_MODE 24 25 INVREQ_IS_HEAVY 26 26 INVREQ_FROM_CPF 27 27 GPUVM_INVREQ_TAG 28 31 mmSDMA2_UTCL1_INV1 0 0x41 1 0 2 INV_ADDR_LO 0 31 mmSDMA2_UTCL1_INV2 0 0x42 2 0 2 INV_VMID_VEC 0 15 RESERVED 16 31 mmSDMA2_UTCL1_RD_XNACK0 0 0x43 1 0 2 XNACK_ADDR_LO 0 31 mmSDMA2_UTCL1_RD_XNACK1 0 0x44 4 0 2 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA2_UTCL1_WR_XNACK0 0 0x45 1 0 2 XNACK_ADDR_LO 0 31 mmSDMA2_UTCL1_WR_XNACK1 0 0x46 4 0 2 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA2_UTCL1_TIMEOUT 0 0x47 2 0 2 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 mmSDMA2_UTCL1_PAGE 0 0x48 11 0 2 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 9 USE_PT_SNOOP 10 10 USE_IO 11 11 RD_L2_POLICY 12 13 WR_L2_POLICY 14 15 DMA_PAGE_SIZE 16 21 USE_BC 22 22 ADDR_IS_PA 23 23 LLC_NOALLOC 24 24 mmSDMA2_RELAX_ORDERING_LUT 0 0x4a 19 0 2 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 mmSDMA2_CHICKEN_BITS_2 0 0x4b 12 0 2 F32_CMD_PROC_DELAY 0 3 CE_BACKWARDS_SIZE_SEL 4 4 CE_DCC_READ_128B_ENABLE 5 5 UTCL1_FORCE_INV_RET_FIFO_FULL_EN 6 6 RESERVED0 7 10 LUT_FIFO_AFULL_MARGIN 11 14 LEGACY_WPTR_POLL_BEHAVIOR 15 15 RB_FIFO_WATERMARK 16 17 IB_FIFO_WATERMARK 18 19 REPEATER_FGCG_EN 20 20 F32_SEND_POSTCODE_EN 21 21 RESERVED 22 31 mmSDMA2_STATUS3_REG 0 0x4c 9 0 2 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 AQL_PREV_CMD_IDLE 21 21 TLBI_IDLE 22 22 GCR_IDLE 23 23 INVREQ_IDLE 24 24 QUEUE_ID_MATCH 25 25 INT_QUEUE_ID 26 29 mmSDMA2_PHYSICAL_ADDR_LO 0 0x4d 4 0 2 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 mmSDMA2_PHYSICAL_ADDR_HI 0 0x4e 1 0 2 ADDR 0 15 mmSDMA2_PHASE2_QUANTUM 0 0x4f 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA2_ERROR_LOG 0 0x50 2 0 2 OVERRIDE 0 15 STATUS 16 31 mmSDMA2_PUB_DUMMY_REG0 0 0x51 1 0 2 VALUE 0 31 mmSDMA2_PUB_DUMMY_REG1 0 0x52 1 0 2 VALUE 0 31 mmSDMA2_PUB_DUMMY_REG2 0 0x53 1 0 2 VALUE 0 31 mmSDMA2_PUB_DUMMY_REG3 0 0x54 1 0 2 VALUE 0 31 mmSDMA2_F32_COUNTER 0 0x55 1 0 2 VALUE 0 31 mmSDMA2_CRD_CNTL 0 0x5b 4 0 2 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 CH_WRREQ_CREDIT 19 24 CH_RDREQ_CREDIT 25 30 mmSDMA2_AQL_STATUS 0 0x5f 2 0 2 COMPLETE_SIGNAL_EMPTY 0 0 INVALID_CMD_EMPTY 1 1 mmSDMA2_EA_DBIT_ADDR_DATA 0 0x60 1 0 2 VALUE 0 31 mmSDMA2_EA_DBIT_ADDR_INDEX 0 0x61 1 0 2 VALUE 0 2 mmSDMA2_TLBI_GCR_CNTL 0 0x62 5 0 2 TLBI_CMD_DW 0 3 GCR_CMD_DW 4 7 GCR_CLKEN_CYCLE 8 11 TLBI_CREDIT 16 23 GCR_CREDIT 24 31 mmSDMA2_TILING_CONFIG 0 0x63 1 0 2 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA2_INT_STATUS 0 0x70 1 0 2 DATA 0 31 mmSDMA2_HOLE_ADDR_LO 0 0x72 1 0 2 VALUE 0 31 mmSDMA2_HOLE_ADDR_HI 0 0x73 1 0 2 VALUE 0 31 mmSDMA2_CLOCK_GATING_REG 0 0x75 6 0 2 DYN_CLK_GATE_STATUS 0 0 PTR_CLK_GATE_STATUS 1 1 CE_CLK_GATE_STATUS 2 2 CE_BC_CLK_GATE_STATUS 3 3 CE_NBC_CLK_GATE_STATUS 4 4 REG_CLK_GATE_STATUS 5 5 mmSDMA2_STATUS4_REG 0 0x76 16 0 2 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 CH_RD_OUTSTANDING 4 4 CH_WR_OUTSTANDING 5 5 GCR_OUTSTANDING 6 6 TLBI_OUTSTANDING 7 7 UTCL2_RD_OUTSTANDING 8 8 UTCL2_WR_OUTSTANDING 9 9 REG_POLLING 10 10 MEM_POLLING 11 11 UTCL2_RD_XNACK 12 13 UTCL2_WR_XNACK 14 15 ACTIVE_QUEUE_ID 16 19 SRIOV_WATING_RLCV_CMD 20 20 SRIOV_SDMA_EXECUTING_CMD 21 21 mmSDMA2_SCRATCH_RAM_DATA 0 0x77 1 0 2 DATA 0 31 mmSDMA2_SCRATCH_RAM_ADDR 0 0x78 1 0 2 ADDR 0 9 mmSDMA2_TIMESTAMP_CNTL 0 0x79 1 0 2 CAPTURE 0 0 mmSDMA2_STATUS5_REG 0 0x7a 11 0 2 GFX_RB_ENABLE_STATUS 0 0 PAGE_RB_ENABLE_STATUS 1 1 RLC0_RB_ENABLE_STATUS 2 2 RLC1_RB_ENABLE_STATUS 3 3 RLC2_RB_ENABLE_STATUS 4 4 RLC3_RB_ENABLE_STATUS 5 5 RLC4_RB_ENABLE_STATUS 6 6 RLC5_RB_ENABLE_STATUS 7 7 RLC6_RB_ENABLE_STATUS 8 8 RLC7_RB_ENABLE_STATUS 9 9 ACTIVE_QUEUE_ID 16 19 mmSDMA2_QUEUE_RESET_REQ 0 0x7b 11 0 2 GFX_QUEUE_RESET 0 0 PAGE_QUEUE_RESET 1 1 RLC0_QUEUE_RESET 2 2 RLC1_QUEUE_RESET 3 3 RLC2_QUEUE_RESET 4 4 RLC3_QUEUE_RESET 5 5 RLC4_QUEUE_RESET 6 6 RLC5_QUEUE_RESET 7 7 RLC6_QUEUE_RESET 8 8 RLC7_QUEUE_RESET 9 9 RESERVED 10 31 mmSDMA2_GFX_RB_CNTL 0 0x80 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_GFX_RB_BASE 0 0x81 1 0 2 ADDR 0 31 mmSDMA2_GFX_RB_BASE_HI 0 0x82 1 0 2 ADDR 0 23 mmSDMA2_GFX_RB_RPTR 0 0x83 1 0 2 OFFSET 0 31 mmSDMA2_GFX_RB_RPTR_HI 0 0x84 1 0 2 OFFSET 0 31 mmSDMA2_GFX_RB_WPTR 0 0x85 1 0 2 OFFSET 0 31 mmSDMA2_GFX_RB_WPTR_HI 0 0x86 1 0 2 OFFSET 0 31 mmSDMA2_GFX_RB_WPTR_POLL_CNTL 0 0x87 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_GFX_RB_RPTR_ADDR_HI 0 0x88 1 0 2 ADDR 0 31 mmSDMA2_GFX_RB_RPTR_ADDR_LO 0 0x89 1 0 2 ADDR 2 31 mmSDMA2_GFX_IB_CNTL 0 0x8a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_GFX_IB_RPTR 0 0x8b 1 0 2 OFFSET 2 21 mmSDMA2_GFX_IB_OFFSET 0 0x8c 1 0 2 OFFSET 2 21 mmSDMA2_GFX_IB_BASE_LO 0 0x8d 1 0 2 ADDR 5 31 mmSDMA2_GFX_IB_BASE_HI 0 0x8e 1 0 2 ADDR 0 31 mmSDMA2_GFX_IB_SIZE 0 0x8f 1 0 2 SIZE 0 19 mmSDMA2_GFX_SKIP_CNTL 0 0x90 1 0 2 SKIP_COUNT 0 19 mmSDMA2_GFX_CONTEXT_STATUS 0 0x91 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_GFX_DOORBELL 0 0x92 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_GFX_CONTEXT_CNTL 0 0x93 2 0 2 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA2_GFX_STATUS 0 0xa8 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_GFX_DOORBELL_LOG 0 0xa9 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_GFX_WATERMARK 0 0xaa 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_GFX_DOORBELL_OFFSET 0 0xab 1 0 2 OFFSET 2 27 mmSDMA2_GFX_CSA_ADDR_LO 0 0xac 1 0 2 ADDR 2 31 mmSDMA2_GFX_CSA_ADDR_HI 0 0xad 1 0 2 ADDR 0 31 mmSDMA2_GFX_IB_SUB_REMAIN 0 0xaf 1 0 2 SIZE 0 13 mmSDMA2_GFX_PREEMPT 0 0xb0 1 0 2 IB_PREEMPT 0 0 mmSDMA2_GFX_DUMMY_REG 0 0xb1 1 0 2 DUMMY 0 31 mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0 0xb2 1 0 2 ADDR 0 31 mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0 0xb3 1 0 2 ADDR 2 31 mmSDMA2_GFX_RB_AQL_CNTL 0 0xb4 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_GFX_MINOR_PTR_UPDATE 0 0xb5 1 0 2 ENABLE 0 0 mmSDMA2_GFX_MIDCMD_DATA0 0 0xc0 1 0 2 DATA0 0 31 mmSDMA2_GFX_MIDCMD_DATA1 0 0xc1 1 0 2 DATA1 0 31 mmSDMA2_GFX_MIDCMD_DATA2 0 0xc2 1 0 2 DATA2 0 31 mmSDMA2_GFX_MIDCMD_DATA3 0 0xc3 1 0 2 DATA3 0 31 mmSDMA2_GFX_MIDCMD_DATA4 0 0xc4 1 0 2 DATA4 0 31 mmSDMA2_GFX_MIDCMD_DATA5 0 0xc5 1 0 2 DATA5 0 31 mmSDMA2_GFX_MIDCMD_DATA6 0 0xc6 1 0 2 DATA6 0 31 mmSDMA2_GFX_MIDCMD_DATA7 0 0xc7 1 0 2 DATA7 0 31 mmSDMA2_GFX_MIDCMD_DATA8 0 0xc8 1 0 2 DATA8 0 31 mmSDMA2_GFX_MIDCMD_DATA9 0 0xc9 1 0 2 DATA9 0 31 mmSDMA2_GFX_MIDCMD_DATA10 0 0xca 1 0 2 DATA10 0 31 mmSDMA2_GFX_MIDCMD_CNTL 0 0xcb 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_PAGE_RB_CNTL 0 0xd8 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_PAGE_RB_BASE 0 0xd9 1 0 2 ADDR 0 31 mmSDMA2_PAGE_RB_BASE_HI 0 0xda 1 0 2 ADDR 0 23 mmSDMA2_PAGE_RB_RPTR 0 0xdb 1 0 2 OFFSET 0 31 mmSDMA2_PAGE_RB_RPTR_HI 0 0xdc 1 0 2 OFFSET 0 31 mmSDMA2_PAGE_RB_WPTR 0 0xdd 1 0 2 OFFSET 0 31 mmSDMA2_PAGE_RB_WPTR_HI 0 0xde 1 0 2 OFFSET 0 31 mmSDMA2_PAGE_RB_WPTR_POLL_CNTL 0 0xdf 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_PAGE_RB_RPTR_ADDR_HI 0 0xe0 1 0 2 ADDR 0 31 mmSDMA2_PAGE_RB_RPTR_ADDR_LO 0 0xe1 1 0 2 ADDR 2 31 mmSDMA2_PAGE_IB_CNTL 0 0xe2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_PAGE_IB_RPTR 0 0xe3 1 0 2 OFFSET 2 21 mmSDMA2_PAGE_IB_OFFSET 0 0xe4 1 0 2 OFFSET 2 21 mmSDMA2_PAGE_IB_BASE_LO 0 0xe5 1 0 2 ADDR 5 31 mmSDMA2_PAGE_IB_BASE_HI 0 0xe6 1 0 2 ADDR 0 31 mmSDMA2_PAGE_IB_SIZE 0 0xe7 1 0 2 SIZE 0 19 mmSDMA2_PAGE_SKIP_CNTL 0 0xe8 1 0 2 SKIP_COUNT 0 19 mmSDMA2_PAGE_CONTEXT_STATUS 0 0xe9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_PAGE_DOORBELL 0 0xea 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_PAGE_STATUS 0 0x100 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_PAGE_DOORBELL_LOG 0 0x101 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_PAGE_WATERMARK 0 0x102 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_PAGE_DOORBELL_OFFSET 0 0x103 1 0 2 OFFSET 2 27 mmSDMA2_PAGE_CSA_ADDR_LO 0 0x104 1 0 2 ADDR 2 31 mmSDMA2_PAGE_CSA_ADDR_HI 0 0x105 1 0 2 ADDR 0 31 mmSDMA2_PAGE_IB_SUB_REMAIN 0 0x107 1 0 2 SIZE 0 13 mmSDMA2_PAGE_PREEMPT 0 0x108 1 0 2 IB_PREEMPT 0 0 mmSDMA2_PAGE_DUMMY_REG 0 0x109 1 0 2 DUMMY 0 31 mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x10a 1 0 2 ADDR 0 31 mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x10b 1 0 2 ADDR 2 31 mmSDMA2_PAGE_RB_AQL_CNTL 0 0x10c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_PAGE_MINOR_PTR_UPDATE 0 0x10d 1 0 2 ENABLE 0 0 mmSDMA2_PAGE_MIDCMD_DATA0 0 0x118 1 0 2 DATA0 0 31 mmSDMA2_PAGE_MIDCMD_DATA1 0 0x119 1 0 2 DATA1 0 31 mmSDMA2_PAGE_MIDCMD_DATA2 0 0x11a 1 0 2 DATA2 0 31 mmSDMA2_PAGE_MIDCMD_DATA3 0 0x11b 1 0 2 DATA3 0 31 mmSDMA2_PAGE_MIDCMD_DATA4 0 0x11c 1 0 2 DATA4 0 31 mmSDMA2_PAGE_MIDCMD_DATA5 0 0x11d 1 0 2 DATA5 0 31 mmSDMA2_PAGE_MIDCMD_DATA6 0 0x11e 1 0 2 DATA6 0 31 mmSDMA2_PAGE_MIDCMD_DATA7 0 0x11f 1 0 2 DATA7 0 31 mmSDMA2_PAGE_MIDCMD_DATA8 0 0x120 1 0 2 DATA8 0 31 mmSDMA2_PAGE_MIDCMD_DATA9 0 0x121 1 0 2 DATA9 0 31 mmSDMA2_PAGE_MIDCMD_DATA10 0 0x122 1 0 2 DATA10 0 31 mmSDMA2_PAGE_MIDCMD_CNTL 0 0x123 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC0_RB_CNTL 0 0x130 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC0_RB_BASE 0 0x131 1 0 2 ADDR 0 31 mmSDMA2_RLC0_RB_BASE_HI 0 0x132 1 0 2 ADDR 0 23 mmSDMA2_RLC0_RB_RPTR 0 0x133 1 0 2 OFFSET 0 31 mmSDMA2_RLC0_RB_RPTR_HI 0 0x134 1 0 2 OFFSET 0 31 mmSDMA2_RLC0_RB_WPTR 0 0x135 1 0 2 OFFSET 0 31 mmSDMA2_RLC0_RB_WPTR_HI 0 0x136 1 0 2 OFFSET 0 31 mmSDMA2_RLC0_RB_WPTR_POLL_CNTL 0 0x137 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC0_RB_RPTR_ADDR_HI 0 0x138 1 0 2 ADDR 0 31 mmSDMA2_RLC0_RB_RPTR_ADDR_LO 0 0x139 1 0 2 ADDR 2 31 mmSDMA2_RLC0_IB_CNTL 0 0x13a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC0_IB_RPTR 0 0x13b 1 0 2 OFFSET 2 21 mmSDMA2_RLC0_IB_OFFSET 0 0x13c 1 0 2 OFFSET 2 21 mmSDMA2_RLC0_IB_BASE_LO 0 0x13d 1 0 2 ADDR 5 31 mmSDMA2_RLC0_IB_BASE_HI 0 0x13e 1 0 2 ADDR 0 31 mmSDMA2_RLC0_IB_SIZE 0 0x13f 1 0 2 SIZE 0 19 mmSDMA2_RLC0_SKIP_CNTL 0 0x140 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC0_CONTEXT_STATUS 0 0x141 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC0_DOORBELL 0 0x142 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC0_STATUS 0 0x158 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC0_DOORBELL_LOG 0 0x159 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC0_WATERMARK 0 0x15a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC0_DOORBELL_OFFSET 0 0x15b 1 0 2 OFFSET 2 27 mmSDMA2_RLC0_CSA_ADDR_LO 0 0x15c 1 0 2 ADDR 2 31 mmSDMA2_RLC0_CSA_ADDR_HI 0 0x15d 1 0 2 ADDR 0 31 mmSDMA2_RLC0_IB_SUB_REMAIN 0 0x15f 1 0 2 SIZE 0 13 mmSDMA2_RLC0_PREEMPT 0 0x160 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC0_DUMMY_REG 0 0x161 1 0 2 DUMMY 0 31 mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x162 1 0 2 ADDR 0 31 mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x163 1 0 2 ADDR 2 31 mmSDMA2_RLC0_RB_AQL_CNTL 0 0x164 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC0_MINOR_PTR_UPDATE 0 0x165 1 0 2 ENABLE 0 0 mmSDMA2_RLC0_MIDCMD_DATA0 0 0x170 1 0 2 DATA0 0 31 mmSDMA2_RLC0_MIDCMD_DATA1 0 0x171 1 0 2 DATA1 0 31 mmSDMA2_RLC0_MIDCMD_DATA2 0 0x172 1 0 2 DATA2 0 31 mmSDMA2_RLC0_MIDCMD_DATA3 0 0x173 1 0 2 DATA3 0 31 mmSDMA2_RLC0_MIDCMD_DATA4 0 0x174 1 0 2 DATA4 0 31 mmSDMA2_RLC0_MIDCMD_DATA5 0 0x175 1 0 2 DATA5 0 31 mmSDMA2_RLC0_MIDCMD_DATA6 0 0x176 1 0 2 DATA6 0 31 mmSDMA2_RLC0_MIDCMD_DATA7 0 0x177 1 0 2 DATA7 0 31 mmSDMA2_RLC0_MIDCMD_DATA8 0 0x178 1 0 2 DATA8 0 31 mmSDMA2_RLC0_MIDCMD_DATA9 0 0x179 1 0 2 DATA9 0 31 mmSDMA2_RLC0_MIDCMD_DATA10 0 0x17a 1 0 2 DATA10 0 31 mmSDMA2_RLC0_MIDCMD_CNTL 0 0x17b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC1_RB_CNTL 0 0x188 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC1_RB_BASE 0 0x189 1 0 2 ADDR 0 31 mmSDMA2_RLC1_RB_BASE_HI 0 0x18a 1 0 2 ADDR 0 23 mmSDMA2_RLC1_RB_RPTR 0 0x18b 1 0 2 OFFSET 0 31 mmSDMA2_RLC1_RB_RPTR_HI 0 0x18c 1 0 2 OFFSET 0 31 mmSDMA2_RLC1_RB_WPTR 0 0x18d 1 0 2 OFFSET 0 31 mmSDMA2_RLC1_RB_WPTR_HI 0 0x18e 1 0 2 OFFSET 0 31 mmSDMA2_RLC1_RB_WPTR_POLL_CNTL 0 0x18f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC1_RB_RPTR_ADDR_HI 0 0x190 1 0 2 ADDR 0 31 mmSDMA2_RLC1_RB_RPTR_ADDR_LO 0 0x191 1 0 2 ADDR 2 31 mmSDMA2_RLC1_IB_CNTL 0 0x192 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC1_IB_RPTR 0 0x193 1 0 2 OFFSET 2 21 mmSDMA2_RLC1_IB_OFFSET 0 0x194 1 0 2 OFFSET 2 21 mmSDMA2_RLC1_IB_BASE_LO 0 0x195 1 0 2 ADDR 5 31 mmSDMA2_RLC1_IB_BASE_HI 0 0x196 1 0 2 ADDR 0 31 mmSDMA2_RLC1_IB_SIZE 0 0x197 1 0 2 SIZE 0 19 mmSDMA2_RLC1_SKIP_CNTL 0 0x198 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC1_CONTEXT_STATUS 0 0x199 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC1_DOORBELL 0 0x19a 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC1_STATUS 0 0x1b0 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC1_DOORBELL_LOG 0 0x1b1 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC1_WATERMARK 0 0x1b2 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC1_DOORBELL_OFFSET 0 0x1b3 1 0 2 OFFSET 2 27 mmSDMA2_RLC1_CSA_ADDR_LO 0 0x1b4 1 0 2 ADDR 2 31 mmSDMA2_RLC1_CSA_ADDR_HI 0 0x1b5 1 0 2 ADDR 0 31 mmSDMA2_RLC1_IB_SUB_REMAIN 0 0x1b7 1 0 2 SIZE 0 13 mmSDMA2_RLC1_PREEMPT 0 0x1b8 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC1_DUMMY_REG 0 0x1b9 1 0 2 DUMMY 0 31 mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1ba 1 0 2 ADDR 0 31 mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1bb 1 0 2 ADDR 2 31 mmSDMA2_RLC1_RB_AQL_CNTL 0 0x1bc 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC1_MINOR_PTR_UPDATE 0 0x1bd 1 0 2 ENABLE 0 0 mmSDMA2_RLC1_MIDCMD_DATA0 0 0x1c8 1 0 2 DATA0 0 31 mmSDMA2_RLC1_MIDCMD_DATA1 0 0x1c9 1 0 2 DATA1 0 31 mmSDMA2_RLC1_MIDCMD_DATA2 0 0x1ca 1 0 2 DATA2 0 31 mmSDMA2_RLC1_MIDCMD_DATA3 0 0x1cb 1 0 2 DATA3 0 31 mmSDMA2_RLC1_MIDCMD_DATA4 0 0x1cc 1 0 2 DATA4 0 31 mmSDMA2_RLC1_MIDCMD_DATA5 0 0x1cd 1 0 2 DATA5 0 31 mmSDMA2_RLC1_MIDCMD_DATA6 0 0x1ce 1 0 2 DATA6 0 31 mmSDMA2_RLC1_MIDCMD_DATA7 0 0x1cf 1 0 2 DATA7 0 31 mmSDMA2_RLC1_MIDCMD_DATA8 0 0x1d0 1 0 2 DATA8 0 31 mmSDMA2_RLC1_MIDCMD_DATA9 0 0x1d1 1 0 2 DATA9 0 31 mmSDMA2_RLC1_MIDCMD_DATA10 0 0x1d2 1 0 2 DATA10 0 31 mmSDMA2_RLC1_MIDCMD_CNTL 0 0x1d3 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC2_RB_CNTL 0 0x1e0 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC2_RB_BASE 0 0x1e1 1 0 2 ADDR 0 31 mmSDMA2_RLC2_RB_BASE_HI 0 0x1e2 1 0 2 ADDR 0 23 mmSDMA2_RLC2_RB_RPTR 0 0x1e3 1 0 2 OFFSET 0 31 mmSDMA2_RLC2_RB_RPTR_HI 0 0x1e4 1 0 2 OFFSET 0 31 mmSDMA2_RLC2_RB_WPTR 0 0x1e5 1 0 2 OFFSET 0 31 mmSDMA2_RLC2_RB_WPTR_HI 0 0x1e6 1 0 2 OFFSET 0 31 mmSDMA2_RLC2_RB_WPTR_POLL_CNTL 0 0x1e7 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC2_RB_RPTR_ADDR_HI 0 0x1e8 1 0 2 ADDR 0 31 mmSDMA2_RLC2_RB_RPTR_ADDR_LO 0 0x1e9 1 0 2 ADDR 2 31 mmSDMA2_RLC2_IB_CNTL 0 0x1ea 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC2_IB_RPTR 0 0x1eb 1 0 2 OFFSET 2 21 mmSDMA2_RLC2_IB_OFFSET 0 0x1ec 1 0 2 OFFSET 2 21 mmSDMA2_RLC2_IB_BASE_LO 0 0x1ed 1 0 2 ADDR 5 31 mmSDMA2_RLC2_IB_BASE_HI 0 0x1ee 1 0 2 ADDR 0 31 mmSDMA2_RLC2_IB_SIZE 0 0x1ef 1 0 2 SIZE 0 19 mmSDMA2_RLC2_SKIP_CNTL 0 0x1f0 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC2_CONTEXT_STATUS 0 0x1f1 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC2_DOORBELL 0 0x1f2 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC2_STATUS 0 0x208 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC2_DOORBELL_LOG 0 0x209 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC2_WATERMARK 0 0x20a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC2_DOORBELL_OFFSET 0 0x20b 1 0 2 OFFSET 2 27 mmSDMA2_RLC2_CSA_ADDR_LO 0 0x20c 1 0 2 ADDR 2 31 mmSDMA2_RLC2_CSA_ADDR_HI 0 0x20d 1 0 2 ADDR 0 31 mmSDMA2_RLC2_IB_SUB_REMAIN 0 0x20f 1 0 2 SIZE 0 13 mmSDMA2_RLC2_PREEMPT 0 0x210 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC2_DUMMY_REG 0 0x211 1 0 2 DUMMY 0 31 mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x212 1 0 2 ADDR 0 31 mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x213 1 0 2 ADDR 2 31 mmSDMA2_RLC2_RB_AQL_CNTL 0 0x214 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC2_MINOR_PTR_UPDATE 0 0x215 1 0 2 ENABLE 0 0 mmSDMA2_RLC2_MIDCMD_DATA0 0 0x220 1 0 2 DATA0 0 31 mmSDMA2_RLC2_MIDCMD_DATA1 0 0x221 1 0 2 DATA1 0 31 mmSDMA2_RLC2_MIDCMD_DATA2 0 0x222 1 0 2 DATA2 0 31 mmSDMA2_RLC2_MIDCMD_DATA3 0 0x223 1 0 2 DATA3 0 31 mmSDMA2_RLC2_MIDCMD_DATA4 0 0x224 1 0 2 DATA4 0 31 mmSDMA2_RLC2_MIDCMD_DATA5 0 0x225 1 0 2 DATA5 0 31 mmSDMA2_RLC2_MIDCMD_DATA6 0 0x226 1 0 2 DATA6 0 31 mmSDMA2_RLC2_MIDCMD_DATA7 0 0x227 1 0 2 DATA7 0 31 mmSDMA2_RLC2_MIDCMD_DATA8 0 0x228 1 0 2 DATA8 0 31 mmSDMA2_RLC2_MIDCMD_DATA9 0 0x229 1 0 2 DATA9 0 31 mmSDMA2_RLC2_MIDCMD_DATA10 0 0x22a 1 0 2 DATA10 0 31 mmSDMA2_RLC2_MIDCMD_CNTL 0 0x22b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC3_RB_CNTL 0 0x238 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC3_RB_BASE 0 0x239 1 0 2 ADDR 0 31 mmSDMA2_RLC3_RB_BASE_HI 0 0x23a 1 0 2 ADDR 0 23 mmSDMA2_RLC3_RB_RPTR 0 0x23b 1 0 2 OFFSET 0 31 mmSDMA2_RLC3_RB_RPTR_HI 0 0x23c 1 0 2 OFFSET 0 31 mmSDMA2_RLC3_RB_WPTR 0 0x23d 1 0 2 OFFSET 0 31 mmSDMA2_RLC3_RB_WPTR_HI 0 0x23e 1 0 2 OFFSET 0 31 mmSDMA2_RLC3_RB_WPTR_POLL_CNTL 0 0x23f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC3_RB_RPTR_ADDR_HI 0 0x240 1 0 2 ADDR 0 31 mmSDMA2_RLC3_RB_RPTR_ADDR_LO 0 0x241 1 0 2 ADDR 2 31 mmSDMA2_RLC3_IB_CNTL 0 0x242 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC3_IB_RPTR 0 0x243 1 0 2 OFFSET 2 21 mmSDMA2_RLC3_IB_OFFSET 0 0x244 1 0 2 OFFSET 2 21 mmSDMA2_RLC3_IB_BASE_LO 0 0x245 1 0 2 ADDR 5 31 mmSDMA2_RLC3_IB_BASE_HI 0 0x246 1 0 2 ADDR 0 31 mmSDMA2_RLC3_IB_SIZE 0 0x247 1 0 2 SIZE 0 19 mmSDMA2_RLC3_SKIP_CNTL 0 0x248 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC3_CONTEXT_STATUS 0 0x249 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC3_DOORBELL 0 0x24a 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC3_STATUS 0 0x260 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC3_DOORBELL_LOG 0 0x261 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC3_WATERMARK 0 0x262 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC3_DOORBELL_OFFSET 0 0x263 1 0 2 OFFSET 2 27 mmSDMA2_RLC3_CSA_ADDR_LO 0 0x264 1 0 2 ADDR 2 31 mmSDMA2_RLC3_CSA_ADDR_HI 0 0x265 1 0 2 ADDR 0 31 mmSDMA2_RLC3_IB_SUB_REMAIN 0 0x267 1 0 2 SIZE 0 13 mmSDMA2_RLC3_PREEMPT 0 0x268 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC3_DUMMY_REG 0 0x269 1 0 2 DUMMY 0 31 mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x26a 1 0 2 ADDR 0 31 mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x26b 1 0 2 ADDR 2 31 mmSDMA2_RLC3_RB_AQL_CNTL 0 0x26c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC3_MINOR_PTR_UPDATE 0 0x26d 1 0 2 ENABLE 0 0 mmSDMA2_RLC3_MIDCMD_DATA0 0 0x278 1 0 2 DATA0 0 31 mmSDMA2_RLC3_MIDCMD_DATA1 0 0x279 1 0 2 DATA1 0 31 mmSDMA2_RLC3_MIDCMD_DATA2 0 0x27a 1 0 2 DATA2 0 31 mmSDMA2_RLC3_MIDCMD_DATA3 0 0x27b 1 0 2 DATA3 0 31 mmSDMA2_RLC3_MIDCMD_DATA4 0 0x27c 1 0 2 DATA4 0 31 mmSDMA2_RLC3_MIDCMD_DATA5 0 0x27d 1 0 2 DATA5 0 31 mmSDMA2_RLC3_MIDCMD_DATA6 0 0x27e 1 0 2 DATA6 0 31 mmSDMA2_RLC3_MIDCMD_DATA7 0 0x27f 1 0 2 DATA7 0 31 mmSDMA2_RLC3_MIDCMD_DATA8 0 0x280 1 0 2 DATA8 0 31 mmSDMA2_RLC3_MIDCMD_DATA9 0 0x281 1 0 2 DATA9 0 31 mmSDMA2_RLC3_MIDCMD_DATA10 0 0x282 1 0 2 DATA10 0 31 mmSDMA2_RLC3_MIDCMD_CNTL 0 0x283 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC4_RB_CNTL 0 0x290 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC4_RB_BASE 0 0x291 1 0 2 ADDR 0 31 mmSDMA2_RLC4_RB_BASE_HI 0 0x292 1 0 2 ADDR 0 23 mmSDMA2_RLC4_RB_RPTR 0 0x293 1 0 2 OFFSET 0 31 mmSDMA2_RLC4_RB_RPTR_HI 0 0x294 1 0 2 OFFSET 0 31 mmSDMA2_RLC4_RB_WPTR 0 0x295 1 0 2 OFFSET 0 31 mmSDMA2_RLC4_RB_WPTR_HI 0 0x296 1 0 2 OFFSET 0 31 mmSDMA2_RLC4_RB_WPTR_POLL_CNTL 0 0x297 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC4_RB_RPTR_ADDR_HI 0 0x298 1 0 2 ADDR 0 31 mmSDMA2_RLC4_RB_RPTR_ADDR_LO 0 0x299 1 0 2 ADDR 2 31 mmSDMA2_RLC4_IB_CNTL 0 0x29a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC4_IB_RPTR 0 0x29b 1 0 2 OFFSET 2 21 mmSDMA2_RLC4_IB_OFFSET 0 0x29c 1 0 2 OFFSET 2 21 mmSDMA2_RLC4_IB_BASE_LO 0 0x29d 1 0 2 ADDR 5 31 mmSDMA2_RLC4_IB_BASE_HI 0 0x29e 1 0 2 ADDR 0 31 mmSDMA2_RLC4_IB_SIZE 0 0x29f 1 0 2 SIZE 0 19 mmSDMA2_RLC4_SKIP_CNTL 0 0x2a0 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC4_CONTEXT_STATUS 0 0x2a1 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC4_DOORBELL 0 0x2a2 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC4_STATUS 0 0x2b8 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC4_DOORBELL_LOG 0 0x2b9 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC4_WATERMARK 0 0x2ba 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC4_DOORBELL_OFFSET 0 0x2bb 1 0 2 OFFSET 2 27 mmSDMA2_RLC4_CSA_ADDR_LO 0 0x2bc 1 0 2 ADDR 2 31 mmSDMA2_RLC4_CSA_ADDR_HI 0 0x2bd 1 0 2 ADDR 0 31 mmSDMA2_RLC4_IB_SUB_REMAIN 0 0x2bf 1 0 2 SIZE 0 13 mmSDMA2_RLC4_PREEMPT 0 0x2c0 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC4_DUMMY_REG 0 0x2c1 1 0 2 DUMMY 0 31 mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x2c2 1 0 2 ADDR 0 31 mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x2c3 1 0 2 ADDR 2 31 mmSDMA2_RLC4_RB_AQL_CNTL 0 0x2c4 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC4_MINOR_PTR_UPDATE 0 0x2c5 1 0 2 ENABLE 0 0 mmSDMA2_RLC4_MIDCMD_DATA0 0 0x2d0 1 0 2 DATA0 0 31 mmSDMA2_RLC4_MIDCMD_DATA1 0 0x2d1 1 0 2 DATA1 0 31 mmSDMA2_RLC4_MIDCMD_DATA2 0 0x2d2 1 0 2 DATA2 0 31 mmSDMA2_RLC4_MIDCMD_DATA3 0 0x2d3 1 0 2 DATA3 0 31 mmSDMA2_RLC4_MIDCMD_DATA4 0 0x2d4 1 0 2 DATA4 0 31 mmSDMA2_RLC4_MIDCMD_DATA5 0 0x2d5 1 0 2 DATA5 0 31 mmSDMA2_RLC4_MIDCMD_DATA6 0 0x2d6 1 0 2 DATA6 0 31 mmSDMA2_RLC4_MIDCMD_DATA7 0 0x2d7 1 0 2 DATA7 0 31 mmSDMA2_RLC4_MIDCMD_DATA8 0 0x2d8 1 0 2 DATA8 0 31 mmSDMA2_RLC4_MIDCMD_DATA9 0 0x2d9 1 0 2 DATA9 0 31 mmSDMA2_RLC4_MIDCMD_DATA10 0 0x2da 1 0 2 DATA10 0 31 mmSDMA2_RLC4_MIDCMD_CNTL 0 0x2db 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC5_RB_CNTL 0 0x2e8 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC5_RB_BASE 0 0x2e9 1 0 2 ADDR 0 31 mmSDMA2_RLC5_RB_BASE_HI 0 0x2ea 1 0 2 ADDR 0 23 mmSDMA2_RLC5_RB_RPTR 0 0x2eb 1 0 2 OFFSET 0 31 mmSDMA2_RLC5_RB_RPTR_HI 0 0x2ec 1 0 2 OFFSET 0 31 mmSDMA2_RLC5_RB_WPTR 0 0x2ed 1 0 2 OFFSET 0 31 mmSDMA2_RLC5_RB_WPTR_HI 0 0x2ee 1 0 2 OFFSET 0 31 mmSDMA2_RLC5_RB_WPTR_POLL_CNTL 0 0x2ef 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC5_RB_RPTR_ADDR_HI 0 0x2f0 1 0 2 ADDR 0 31 mmSDMA2_RLC5_RB_RPTR_ADDR_LO 0 0x2f1 1 0 2 ADDR 2 31 mmSDMA2_RLC5_IB_CNTL 0 0x2f2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC5_IB_RPTR 0 0x2f3 1 0 2 OFFSET 2 21 mmSDMA2_RLC5_IB_OFFSET 0 0x2f4 1 0 2 OFFSET 2 21 mmSDMA2_RLC5_IB_BASE_LO 0 0x2f5 1 0 2 ADDR 5 31 mmSDMA2_RLC5_IB_BASE_HI 0 0x2f6 1 0 2 ADDR 0 31 mmSDMA2_RLC5_IB_SIZE 0 0x2f7 1 0 2 SIZE 0 19 mmSDMA2_RLC5_SKIP_CNTL 0 0x2f8 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC5_CONTEXT_STATUS 0 0x2f9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC5_DOORBELL 0 0x2fa 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC5_STATUS 0 0x310 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC5_DOORBELL_LOG 0 0x311 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC5_WATERMARK 0 0x312 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC5_DOORBELL_OFFSET 0 0x313 1 0 2 OFFSET 2 27 mmSDMA2_RLC5_CSA_ADDR_LO 0 0x314 1 0 2 ADDR 2 31 mmSDMA2_RLC5_CSA_ADDR_HI 0 0x315 1 0 2 ADDR 0 31 mmSDMA2_RLC5_IB_SUB_REMAIN 0 0x317 1 0 2 SIZE 0 13 mmSDMA2_RLC5_PREEMPT 0 0x318 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC5_DUMMY_REG 0 0x319 1 0 2 DUMMY 0 31 mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x31a 1 0 2 ADDR 0 31 mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x31b 1 0 2 ADDR 2 31 mmSDMA2_RLC5_RB_AQL_CNTL 0 0x31c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC5_MINOR_PTR_UPDATE 0 0x31d 1 0 2 ENABLE 0 0 mmSDMA2_RLC5_MIDCMD_DATA0 0 0x328 1 0 2 DATA0 0 31 mmSDMA2_RLC5_MIDCMD_DATA1 0 0x329 1 0 2 DATA1 0 31 mmSDMA2_RLC5_MIDCMD_DATA2 0 0x32a 1 0 2 DATA2 0 31 mmSDMA2_RLC5_MIDCMD_DATA3 0 0x32b 1 0 2 DATA3 0 31 mmSDMA2_RLC5_MIDCMD_DATA4 0 0x32c 1 0 2 DATA4 0 31 mmSDMA2_RLC5_MIDCMD_DATA5 0 0x32d 1 0 2 DATA5 0 31 mmSDMA2_RLC5_MIDCMD_DATA6 0 0x32e 1 0 2 DATA6 0 31 mmSDMA2_RLC5_MIDCMD_DATA7 0 0x32f 1 0 2 DATA7 0 31 mmSDMA2_RLC5_MIDCMD_DATA8 0 0x330 1 0 2 DATA8 0 31 mmSDMA2_RLC5_MIDCMD_DATA9 0 0x331 1 0 2 DATA9 0 31 mmSDMA2_RLC5_MIDCMD_DATA10 0 0x332 1 0 2 DATA10 0 31 mmSDMA2_RLC5_MIDCMD_CNTL 0 0x333 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC6_RB_CNTL 0 0x340 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC6_RB_BASE 0 0x341 1 0 2 ADDR 0 31 mmSDMA2_RLC6_RB_BASE_HI 0 0x342 1 0 2 ADDR 0 23 mmSDMA2_RLC6_RB_RPTR 0 0x343 1 0 2 OFFSET 0 31 mmSDMA2_RLC6_RB_RPTR_HI 0 0x344 1 0 2 OFFSET 0 31 mmSDMA2_RLC6_RB_WPTR 0 0x345 1 0 2 OFFSET 0 31 mmSDMA2_RLC6_RB_WPTR_HI 0 0x346 1 0 2 OFFSET 0 31 mmSDMA2_RLC6_RB_WPTR_POLL_CNTL 0 0x347 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC6_RB_RPTR_ADDR_HI 0 0x348 1 0 2 ADDR 0 31 mmSDMA2_RLC6_RB_RPTR_ADDR_LO 0 0x349 1 0 2 ADDR 2 31 mmSDMA2_RLC6_IB_CNTL 0 0x34a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC6_IB_RPTR 0 0x34b 1 0 2 OFFSET 2 21 mmSDMA2_RLC6_IB_OFFSET 0 0x34c 1 0 2 OFFSET 2 21 mmSDMA2_RLC6_IB_BASE_LO 0 0x34d 1 0 2 ADDR 5 31 mmSDMA2_RLC6_IB_BASE_HI 0 0x34e 1 0 2 ADDR 0 31 mmSDMA2_RLC6_IB_SIZE 0 0x34f 1 0 2 SIZE 0 19 mmSDMA2_RLC6_SKIP_CNTL 0 0x350 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC6_CONTEXT_STATUS 0 0x351 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC6_DOORBELL 0 0x352 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC6_STATUS 0 0x368 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC6_DOORBELL_LOG 0 0x369 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC6_WATERMARK 0 0x36a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC6_DOORBELL_OFFSET 0 0x36b 1 0 2 OFFSET 2 27 mmSDMA2_RLC6_CSA_ADDR_LO 0 0x36c 1 0 2 ADDR 2 31 mmSDMA2_RLC6_CSA_ADDR_HI 0 0x36d 1 0 2 ADDR 0 31 mmSDMA2_RLC6_IB_SUB_REMAIN 0 0x36f 1 0 2 SIZE 0 13 mmSDMA2_RLC6_PREEMPT 0 0x370 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC6_DUMMY_REG 0 0x371 1 0 2 DUMMY 0 31 mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x372 1 0 2 ADDR 0 31 mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x373 1 0 2 ADDR 2 31 mmSDMA2_RLC6_RB_AQL_CNTL 0 0x374 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC6_MINOR_PTR_UPDATE 0 0x375 1 0 2 ENABLE 0 0 mmSDMA2_RLC6_MIDCMD_DATA0 0 0x380 1 0 2 DATA0 0 31 mmSDMA2_RLC6_MIDCMD_DATA1 0 0x381 1 0 2 DATA1 0 31 mmSDMA2_RLC6_MIDCMD_DATA2 0 0x382 1 0 2 DATA2 0 31 mmSDMA2_RLC6_MIDCMD_DATA3 0 0x383 1 0 2 DATA3 0 31 mmSDMA2_RLC6_MIDCMD_DATA4 0 0x384 1 0 2 DATA4 0 31 mmSDMA2_RLC6_MIDCMD_DATA5 0 0x385 1 0 2 DATA5 0 31 mmSDMA2_RLC6_MIDCMD_DATA6 0 0x386 1 0 2 DATA6 0 31 mmSDMA2_RLC6_MIDCMD_DATA7 0 0x387 1 0 2 DATA7 0 31 mmSDMA2_RLC6_MIDCMD_DATA8 0 0x388 1 0 2 DATA8 0 31 mmSDMA2_RLC6_MIDCMD_DATA9 0 0x389 1 0 2 DATA9 0 31 mmSDMA2_RLC6_MIDCMD_DATA10 0 0x38a 1 0 2 DATA10 0 31 mmSDMA2_RLC6_MIDCMD_CNTL 0 0x38b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA2_RLC7_RB_CNTL 0 0x398 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA2_RLC7_RB_BASE 0 0x399 1 0 2 ADDR 0 31 mmSDMA2_RLC7_RB_BASE_HI 0 0x39a 1 0 2 ADDR 0 23 mmSDMA2_RLC7_RB_RPTR 0 0x39b 1 0 2 OFFSET 0 31 mmSDMA2_RLC7_RB_RPTR_HI 0 0x39c 1 0 2 OFFSET 0 31 mmSDMA2_RLC7_RB_WPTR 0 0x39d 1 0 2 OFFSET 0 31 mmSDMA2_RLC7_RB_WPTR_HI 0 0x39e 1 0 2 OFFSET 0 31 mmSDMA2_RLC7_RB_WPTR_POLL_CNTL 0 0x39f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA2_RLC7_RB_RPTR_ADDR_HI 0 0x3a0 1 0 2 ADDR 0 31 mmSDMA2_RLC7_RB_RPTR_ADDR_LO 0 0x3a1 1 0 2 ADDR 2 31 mmSDMA2_RLC7_IB_CNTL 0 0x3a2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA2_RLC7_IB_RPTR 0 0x3a3 1 0 2 OFFSET 2 21 mmSDMA2_RLC7_IB_OFFSET 0 0x3a4 1 0 2 OFFSET 2 21 mmSDMA2_RLC7_IB_BASE_LO 0 0x3a5 1 0 2 ADDR 5 31 mmSDMA2_RLC7_IB_BASE_HI 0 0x3a6 1 0 2 ADDR 0 31 mmSDMA2_RLC7_IB_SIZE 0 0x3a7 1 0 2 SIZE 0 19 mmSDMA2_RLC7_SKIP_CNTL 0 0x3a8 1 0 2 SKIP_COUNT 0 19 mmSDMA2_RLC7_CONTEXT_STATUS 0 0x3a9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA2_RLC7_DOORBELL 0 0x3aa 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA2_RLC7_STATUS 0 0x3c0 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA2_RLC7_DOORBELL_LOG 0 0x3c1 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA2_RLC7_WATERMARK 0 0x3c2 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA2_RLC7_DOORBELL_OFFSET 0 0x3c3 1 0 2 OFFSET 2 27 mmSDMA2_RLC7_CSA_ADDR_LO 0 0x3c4 1 0 2 ADDR 2 31 mmSDMA2_RLC7_CSA_ADDR_HI 0 0x3c5 1 0 2 ADDR 0 31 mmSDMA2_RLC7_IB_SUB_REMAIN 0 0x3c7 1 0 2 SIZE 0 13 mmSDMA2_RLC7_PREEMPT 0 0x3c8 1 0 2 IB_PREEMPT 0 0 mmSDMA2_RLC7_DUMMY_REG 0 0x3c9 1 0 2 DUMMY 0 31 mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x3ca 1 0 2 ADDR 0 31 mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x3cb 1 0 2 ADDR 2 31 mmSDMA2_RLC7_RB_AQL_CNTL 0 0x3cc 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA2_RLC7_MINOR_PTR_UPDATE 0 0x3cd 1 0 2 ENABLE 0 0 mmSDMA2_RLC7_MIDCMD_DATA0 0 0x3d8 1 0 2 DATA0 0 31 mmSDMA2_RLC7_MIDCMD_DATA1 0 0x3d9 1 0 2 DATA1 0 31 mmSDMA2_RLC7_MIDCMD_DATA2 0 0x3da 1 0 2 DATA2 0 31 mmSDMA2_RLC7_MIDCMD_DATA3 0 0x3db 1 0 2 DATA3 0 31 mmSDMA2_RLC7_MIDCMD_DATA4 0 0x3dc 1 0 2 DATA4 0 31 mmSDMA2_RLC7_MIDCMD_DATA5 0 0x3dd 1 0 2 DATA5 0 31 mmSDMA2_RLC7_MIDCMD_DATA6 0 0x3de 1 0 2 DATA6 0 31 mmSDMA2_RLC7_MIDCMD_DATA7 0 0x3df 1 0 2 DATA7 0 31 mmSDMA2_RLC7_MIDCMD_DATA8 0 0x3e0 1 0 2 DATA8 0 31 mmSDMA2_RLC7_MIDCMD_DATA9 0 0x3e1 1 0 2 DATA9 0 31 mmSDMA2_RLC7_MIDCMD_DATA10 0 0x3e2 1 0 2 DATA10 0 31 mmSDMA2_RLC7_MIDCMD_CNTL 0 0x3e3 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_DEC_START 0 0x400 1 0 2 START 0 31 mmSDMA3_GLOBAL_TIMESTAMP_LO 0 0x40f 1 0 2 DATA 0 31 mmSDMA3_GLOBAL_TIMESTAMP_HI 0 0x410 1 0 2 DATA 0 31 mmSDMA3_PG_CNTL 0 0x416 2 0 2 CMD 0 3 STATUS 16 19 mmSDMA3_PG_CTX_LO 0 0x417 1 0 2 ADDR 0 31 mmSDMA3_PG_CTX_HI 0 0x418 1 0 2 ADDR 0 31 mmSDMA3_PG_CTX_CNTL 0 0x419 1 0 2 VMID 4 7 mmSDMA3_POWER_CNTL 0 0x41a 6 0 2 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 ON_OFF_STATUS_DURATION_TIME 26 31 mmSDMA3_CLK_CTRL 0 0x41b 10 0 2 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED_24_12 12 24 CGCG_EN_OVERRIDE 25 25 SOFT_OVERRIDE4 26 26 SOFT_OVERRIDE3 27 27 SOFT_OVERRIDE2 28 28 SOFT_OVERRIDE1 29 29 SOFT_OVERRIDE0 30 30 SOFT_OVERRIDER_REG 31 31 mmSDMA3_CNTL 0 0x41c 13 0 2 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 PAGE_INT_ENABLE 7 7 CH_PERFCNT_ENABLE 16 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA3_CHICKEN_BITS 0 0x41d 20 0 2 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 SOFT_OVERRIDE_DCGE 4 4 SOFT_OVERRIDE_SDMA_GRBM_FGCG 5 5 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 T2L_256B_ENABLE 18 18 GCR_FGCG_ENABLE 19 19 SRBM_POLL_RETRYING 20 20 CH_FGCG_ENABLE 21 21 UTCL2_INVREQ_FGCG_ENABLE 22 22 CG_STATUS_OUTPUT 23 23 UTCL1_FGCG_ENABLE 24 24 TIME_BASED_QOS 25 25 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA3_GB_ADDR_CONFIG 0 0x41e 6 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA3_GB_ADDR_CONFIG_READ 0 0x41f 6 0 2 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_SHADER_ENGINES 19 20 NUM_RB_PER_SE 26 27 mmSDMA3_RB_RPTR_FETCH_HI 0 0x420 1 0 2 OFFSET 0 31 mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0 0x421 1 0 2 TIMER 0 31 mmSDMA3_RB_RPTR_FETCH 0 0x422 1 0 2 OFFSET 2 31 mmSDMA3_IB_OFFSET_FETCH 0 0x423 1 0 2 OFFSET 2 21 mmSDMA3_PROGRAM 0 0x424 1 0 2 STREAM 0 31 mmSDMA3_STATUS_REG 0 0x425 29 0 2 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA3_STATUS1_REG 0 0x426 14 0 2 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA3_RD_BURST_CNTL 0 0x427 1 0 2 RD_BURST 0 1 mmSDMA3_HBM_PAGE_CONFIG 0 0x428 1 0 2 PAGE_SIZE_EXPONENT 0 0 mmSDMA3_UCODE_CHECKSUM 0 0x429 1 0 2 DATA 0 31 mmSDMA3_F32_CNTL 0 0x42a 4 0 2 HALT 0 0 STEP 1 1 CHECKSUM_CLR 8 8 RESET 9 9 mmSDMA3_FREEZE 0 0x42b 5 0 2 PREEMPT 0 0 FORCE_PREEMPT 1 1 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA3_PHASE0_QUANTUM 0 0x42c 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_PHASE1_QUANTUM 0 0x42d 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_EDC_CONFIG 0 0x432 2 0 2 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA3_BA_THRESHOLD 0 0x433 2 0 2 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA3_ID 0 0x434 1 0 2 DEVICE_ID 0 7 mmSDMA3_VERSION 0 0x435 3 0 2 MINVER 0 6 MAJVER 8 14 REV 16 21 mmSDMA3_EDC_COUNTER 0 0x436 17 0 2 SDMA_UCODE_BUF_DED 0 0 SDMA_UCODE_BUF_SEC 1 1 SDMA_RB_CMD_BUF_SED 2 2 SDMA_IB_CMD_BUF_SED 3 3 SDMA_UTCL1_RD_FIFO_SED 4 4 SDMA_UTCL1_RDBST_FIFO_SED 5 5 SDMA_DATA_LUT_FIFO_SED 6 6 SDMA_MBANK_DATA_BUF0_SED 7 7 SDMA_MBANK_DATA_BUF1_SED 8 8 SDMA_MBANK_DATA_BUF2_SED 9 9 SDMA_MBANK_DATA_BUF3_SED 10 10 SDMA_MBANK_DATA_BUF4_SED 11 11 SDMA_MBANK_DATA_BUF5_SED 12 12 SDMA_MBANK_DATA_BUF6_SED 13 13 SDMA_MBANK_DATA_BUF7_SED 14 14 SDMA_SPLIT_DAT_BUF_SED 15 15 SDMA_MC_WR_ADDR_FIFO_SED 16 16 mmSDMA3_EDC_COUNTER_CLEAR 0 0x437 1 0 2 DUMMY 0 0 mmSDMA3_STATUS2_REG 0 0x438 3 0 2 ID 0 1 F32_INSTR_PTR 2 15 CMD_OP 16 31 mmSDMA3_ATOMIC_CNTL 0 0x439 2 0 2 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA3_ATOMIC_PREOP_LO 0 0x43a 1 0 2 DATA 0 31 mmSDMA3_ATOMIC_PREOP_HI 0 0x43b 1 0 2 DATA 0 31 mmSDMA3_UTCL1_CNTL 0 0x43c 9 0 2 REDO_ENABLE 0 0 REDO_DELAY 1 5 REDO_WATERMK 6 8 RESP_MODE 9 11 FORCE_INVALIDATION 14 14 FORCE_INVREQ_HEAVY 15 15 INVACK_DELAY 16 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 mmSDMA3_UTCL1_WATERMK 0 0x43d 4 0 2 REQMC_WATERMK 0 9 REQPG_WATERMK 10 17 INVREQ_WATERMK 18 25 XNACK_WATERMK 26 31 mmSDMA3_UTCL1_RD_STATUS 0 0x43e 27 0 2 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_RD_VECTOR 17 20 MERGE_STATE 21 23 ADDR_RD_RTR 24 24 RD_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 HIT_CACHE 27 27 RD_DCC_ENABLE 28 28 NACK_TIMEOUT_SW 29 29 DCC_PAGE_FAULT 30 30 DCC_PAGE_NULL 31 31 mmSDMA3_UTCL1_WR_STATUS 0 0x43f 27 0 2 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_RET_ADDR_FIFO_FULL 1 1 RQMC_REQ_FIFO_EMPTY 2 2 RQMC_REQ_FIFO_FULL 3 3 RTPG_RET_BUF_EMPTY 4 4 RTPG_RET_BUF_FULL 5 5 RTPG_VADDR_FIFO_EMPTY 6 6 RTPG_VADDR_FIFO_FULL 7 7 RQPG_REDO_FIFO_EMPTY 8 8 RQPG_REDO_FIFO_FULL 9 9 RQPG_REQPAGE_FIFO_EMPTY 10 10 RQPG_REQPAGE_FIFO_FULL 11 11 REDO_ARR_EMPTY 12 12 REDO_ARR_FULL 13 13 PAGE_FAULT 14 14 PAGE_NULL 15 15 REQL2_IDLE 16 16 NEXT_WR_VECTOR 17 20 MERGE_STATE 21 23 F32_WR_RTR 24 24 WR_XNACK_TIMEOUT 25 25 PAGE_NULL_SW 26 26 ATOMIC_OP 27 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 mmSDMA3_UTCL1_INV0 0 0x440 14 0 2 CPF_INVREQ_EN 0 0 GPUVM_INVREQ_EN 1 1 CPF_GPA_INVREQ 2 2 GPUVM_INVREQ_LOW 3 3 GPUVM_INVREQ_HIGH 4 4 INVREQ_SIZE 5 10 INVREQ_IDLE 11 11 VMINV_PEND_CNT 12 15 GPUVM_LO_INV_VMID 16 19 GPUVM_HI_INV_VMID 20 23 GPUVM_INV_MODE 24 25 INVREQ_IS_HEAVY 26 26 INVREQ_FROM_CPF 27 27 GPUVM_INVREQ_TAG 28 31 mmSDMA3_UTCL1_INV1 0 0x441 1 0 2 INV_ADDR_LO 0 31 mmSDMA3_UTCL1_INV2 0 0x442 2 0 2 INV_VMID_VEC 0 15 RESERVED 16 31 mmSDMA3_UTCL1_RD_XNACK0 0 0x443 1 0 2 XNACK_ADDR_LO 0 31 mmSDMA3_UTCL1_RD_XNACK1 0 0x444 4 0 2 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA3_UTCL1_WR_XNACK0 0 0x445 1 0 2 XNACK_ADDR_LO 0 31 mmSDMA3_UTCL1_WR_XNACK1 0 0x446 4 0 2 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA3_UTCL1_TIMEOUT 0 0x447 2 0 2 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 mmSDMA3_UTCL1_PAGE 0 0x448 11 0 2 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 9 USE_PT_SNOOP 10 10 USE_IO 11 11 RD_L2_POLICY 12 13 WR_L2_POLICY 14 15 DMA_PAGE_SIZE 16 21 USE_BC 22 22 ADDR_IS_PA 23 23 LLC_NOALLOC 24 24 mmSDMA3_RELAX_ORDERING_LUT 0 0x44a 19 0 2 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 mmSDMA3_CHICKEN_BITS_2 0 0x44b 12 0 2 F32_CMD_PROC_DELAY 0 3 CE_BACKWARDS_SIZE_SEL 4 4 CE_DCC_READ_128B_ENABLE 5 5 UTCL1_FORCE_INV_RET_FIFO_FULL_EN 6 6 RESERVED0 7 10 LUT_FIFO_AFULL_MARGIN 11 14 LEGACY_WPTR_POLL_BEHAVIOR 15 15 RB_FIFO_WATERMARK 16 17 IB_FIFO_WATERMARK 18 19 REPEATER_FGCG_EN 20 20 F32_SEND_POSTCODE_EN 21 21 RESERVED 22 31 mmSDMA3_STATUS3_REG 0 0x44c 9 0 2 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 AQL_PREV_CMD_IDLE 21 21 TLBI_IDLE 22 22 GCR_IDLE 23 23 INVREQ_IDLE 24 24 QUEUE_ID_MATCH 25 25 INT_QUEUE_ID 26 29 mmSDMA3_PHYSICAL_ADDR_LO 0 0x44d 4 0 2 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 mmSDMA3_PHYSICAL_ADDR_HI 0 0x44e 1 0 2 ADDR 0 15 mmSDMA3_PHASE2_QUANTUM 0 0x44f 3 0 2 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_ERROR_LOG 0 0x450 2 0 2 OVERRIDE 0 15 STATUS 16 31 mmSDMA3_PUB_DUMMY_REG0 0 0x451 1 0 2 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG1 0 0x452 1 0 2 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG2 0 0x453 1 0 2 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG3 0 0x454 1 0 2 VALUE 0 31 mmSDMA3_F32_COUNTER 0 0x455 1 0 2 VALUE 0 31 mmSDMA3_CRD_CNTL 0 0x45b 4 0 2 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 CH_WRREQ_CREDIT 19 24 CH_RDREQ_CREDIT 25 30 mmSDMA3_AQL_STATUS 0 0x45f 2 0 2 COMPLETE_SIGNAL_EMPTY 0 0 INVALID_CMD_EMPTY 1 1 mmSDMA3_EA_DBIT_ADDR_DATA 0 0x460 1 0 2 VALUE 0 31 mmSDMA3_EA_DBIT_ADDR_INDEX 0 0x461 1 0 2 VALUE 0 2 mmSDMA3_TLBI_GCR_CNTL 0 0x462 5 0 2 TLBI_CMD_DW 0 3 GCR_CMD_DW 4 7 GCR_CLKEN_CYCLE 8 11 TLBI_CREDIT 16 23 GCR_CREDIT 24 31 mmSDMA3_TILING_CONFIG 0 0x463 1 0 2 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA3_INT_STATUS 0 0x470 1 0 2 DATA 0 31 mmSDMA3_HOLE_ADDR_LO 0 0x472 1 0 2 VALUE 0 31 mmSDMA3_HOLE_ADDR_HI 0 0x473 1 0 2 VALUE 0 31 mmSDMA3_CLOCK_GATING_REG 0 0x475 6 0 2 DYN_CLK_GATE_STATUS 0 0 PTR_CLK_GATE_STATUS 1 1 CE_CLK_GATE_STATUS 2 2 CE_BC_CLK_GATE_STATUS 3 3 CE_NBC_CLK_GATE_STATUS 4 4 REG_CLK_GATE_STATUS 5 5 mmSDMA3_STATUS4_REG 0 0x476 16 0 2 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 CH_RD_OUTSTANDING 4 4 CH_WR_OUTSTANDING 5 5 GCR_OUTSTANDING 6 6 TLBI_OUTSTANDING 7 7 UTCL2_RD_OUTSTANDING 8 8 UTCL2_WR_OUTSTANDING 9 9 REG_POLLING 10 10 MEM_POLLING 11 11 UTCL2_RD_XNACK 12 13 UTCL2_WR_XNACK 14 15 ACTIVE_QUEUE_ID 16 19 SRIOV_WATING_RLCV_CMD 20 20 SRIOV_SDMA_EXECUTING_CMD 21 21 mmSDMA3_SCRATCH_RAM_DATA 0 0x477 1 0 2 DATA 0 31 mmSDMA3_SCRATCH_RAM_ADDR 0 0x478 1 0 2 ADDR 0 9 mmSDMA3_TIMESTAMP_CNTL 0 0x479 1 0 2 CAPTURE 0 0 mmSDMA3_STATUS5_REG 0 0x47a 11 0 2 GFX_RB_ENABLE_STATUS 0 0 PAGE_RB_ENABLE_STATUS 1 1 RLC0_RB_ENABLE_STATUS 2 2 RLC1_RB_ENABLE_STATUS 3 3 RLC2_RB_ENABLE_STATUS 4 4 RLC3_RB_ENABLE_STATUS 5 5 RLC4_RB_ENABLE_STATUS 6 6 RLC5_RB_ENABLE_STATUS 7 7 RLC6_RB_ENABLE_STATUS 8 8 RLC7_RB_ENABLE_STATUS 9 9 ACTIVE_QUEUE_ID 16 19 mmSDMA3_QUEUE_RESET_REQ 0 0x47b 11 0 2 GFX_QUEUE_RESET 0 0 PAGE_QUEUE_RESET 1 1 RLC0_QUEUE_RESET 2 2 RLC1_QUEUE_RESET 3 3 RLC2_QUEUE_RESET 4 4 RLC3_QUEUE_RESET 5 5 RLC4_QUEUE_RESET 6 6 RLC5_QUEUE_RESET 7 7 RLC6_QUEUE_RESET 8 8 RLC7_QUEUE_RESET 9 9 RESERVED 10 31 mmSDMA3_GFX_RB_CNTL 0 0x480 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_GFX_RB_BASE 0 0x481 1 0 2 ADDR 0 31 mmSDMA3_GFX_RB_BASE_HI 0 0x482 1 0 2 ADDR 0 23 mmSDMA3_GFX_RB_RPTR 0 0x483 1 0 2 OFFSET 0 31 mmSDMA3_GFX_RB_RPTR_HI 0 0x484 1 0 2 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR 0 0x485 1 0 2 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR_HI 0 0x486 1 0 2 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0 0x487 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_GFX_RB_RPTR_ADDR_HI 0 0x488 1 0 2 ADDR 0 31 mmSDMA3_GFX_RB_RPTR_ADDR_LO 0 0x489 1 0 2 ADDR 2 31 mmSDMA3_GFX_IB_CNTL 0 0x48a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_GFX_IB_RPTR 0 0x48b 1 0 2 OFFSET 2 21 mmSDMA3_GFX_IB_OFFSET 0 0x48c 1 0 2 OFFSET 2 21 mmSDMA3_GFX_IB_BASE_LO 0 0x48d 1 0 2 ADDR 5 31 mmSDMA3_GFX_IB_BASE_HI 0 0x48e 1 0 2 ADDR 0 31 mmSDMA3_GFX_IB_SIZE 0 0x48f 1 0 2 SIZE 0 19 mmSDMA3_GFX_SKIP_CNTL 0 0x490 1 0 2 SKIP_COUNT 0 19 mmSDMA3_GFX_CONTEXT_STATUS 0 0x491 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_GFX_DOORBELL 0 0x492 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_GFX_CONTEXT_CNTL 0 0x493 2 0 2 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA3_GFX_STATUS 0 0x4a8 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_GFX_DOORBELL_LOG 0 0x4a9 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_GFX_WATERMARK 0 0x4aa 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_GFX_DOORBELL_OFFSET 0 0x4ab 1 0 2 OFFSET 2 27 mmSDMA3_GFX_CSA_ADDR_LO 0 0x4ac 1 0 2 ADDR 2 31 mmSDMA3_GFX_CSA_ADDR_HI 0 0x4ad 1 0 2 ADDR 0 31 mmSDMA3_GFX_IB_SUB_REMAIN 0 0x4af 1 0 2 SIZE 0 13 mmSDMA3_GFX_PREEMPT 0 0x4b0 1 0 2 IB_PREEMPT 0 0 mmSDMA3_GFX_DUMMY_REG 0 0x4b1 1 0 2 DUMMY 0 31 mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0 0x4b2 1 0 2 ADDR 0 31 mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0 0x4b3 1 0 2 ADDR 2 31 mmSDMA3_GFX_RB_AQL_CNTL 0 0x4b4 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_GFX_MINOR_PTR_UPDATE 0 0x4b5 1 0 2 ENABLE 0 0 mmSDMA3_GFX_MIDCMD_DATA0 0 0x4c0 1 0 2 DATA0 0 31 mmSDMA3_GFX_MIDCMD_DATA1 0 0x4c1 1 0 2 DATA1 0 31 mmSDMA3_GFX_MIDCMD_DATA2 0 0x4c2 1 0 2 DATA2 0 31 mmSDMA3_GFX_MIDCMD_DATA3 0 0x4c3 1 0 2 DATA3 0 31 mmSDMA3_GFX_MIDCMD_DATA4 0 0x4c4 1 0 2 DATA4 0 31 mmSDMA3_GFX_MIDCMD_DATA5 0 0x4c5 1 0 2 DATA5 0 31 mmSDMA3_GFX_MIDCMD_DATA6 0 0x4c6 1 0 2 DATA6 0 31 mmSDMA3_GFX_MIDCMD_DATA7 0 0x4c7 1 0 2 DATA7 0 31 mmSDMA3_GFX_MIDCMD_DATA8 0 0x4c8 1 0 2 DATA8 0 31 mmSDMA3_GFX_MIDCMD_DATA9 0 0x4c9 1 0 2 DATA9 0 31 mmSDMA3_GFX_MIDCMD_DATA10 0 0x4ca 1 0 2 DATA10 0 31 mmSDMA3_GFX_MIDCMD_CNTL 0 0x4cb 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_PAGE_RB_CNTL 0 0x4d8 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_PAGE_RB_BASE 0 0x4d9 1 0 2 ADDR 0 31 mmSDMA3_PAGE_RB_BASE_HI 0 0x4da 1 0 2 ADDR 0 23 mmSDMA3_PAGE_RB_RPTR 0 0x4db 1 0 2 OFFSET 0 31 mmSDMA3_PAGE_RB_RPTR_HI 0 0x4dc 1 0 2 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR 0 0x4dd 1 0 2 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR_HI 0 0x4de 1 0 2 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0 0x4df 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0 0x4e0 1 0 2 ADDR 0 31 mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0 0x4e1 1 0 2 ADDR 2 31 mmSDMA3_PAGE_IB_CNTL 0 0x4e2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_PAGE_IB_RPTR 0 0x4e3 1 0 2 OFFSET 2 21 mmSDMA3_PAGE_IB_OFFSET 0 0x4e4 1 0 2 OFFSET 2 21 mmSDMA3_PAGE_IB_BASE_LO 0 0x4e5 1 0 2 ADDR 5 31 mmSDMA3_PAGE_IB_BASE_HI 0 0x4e6 1 0 2 ADDR 0 31 mmSDMA3_PAGE_IB_SIZE 0 0x4e7 1 0 2 SIZE 0 19 mmSDMA3_PAGE_SKIP_CNTL 0 0x4e8 1 0 2 SKIP_COUNT 0 19 mmSDMA3_PAGE_CONTEXT_STATUS 0 0x4e9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_PAGE_DOORBELL 0 0x4ea 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_PAGE_STATUS 0 0x500 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_PAGE_DOORBELL_LOG 0 0x501 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_PAGE_WATERMARK 0 0x502 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_PAGE_DOORBELL_OFFSET 0 0x503 1 0 2 OFFSET 2 27 mmSDMA3_PAGE_CSA_ADDR_LO 0 0x504 1 0 2 ADDR 2 31 mmSDMA3_PAGE_CSA_ADDR_HI 0 0x505 1 0 2 ADDR 0 31 mmSDMA3_PAGE_IB_SUB_REMAIN 0 0x507 1 0 2 SIZE 0 13 mmSDMA3_PAGE_PREEMPT 0 0x508 1 0 2 IB_PREEMPT 0 0 mmSDMA3_PAGE_DUMMY_REG 0 0x509 1 0 2 DUMMY 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x50a 1 0 2 ADDR 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x50b 1 0 2 ADDR 2 31 mmSDMA3_PAGE_RB_AQL_CNTL 0 0x50c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_PAGE_MINOR_PTR_UPDATE 0 0x50d 1 0 2 ENABLE 0 0 mmSDMA3_PAGE_MIDCMD_DATA0 0 0x518 1 0 2 DATA0 0 31 mmSDMA3_PAGE_MIDCMD_DATA1 0 0x519 1 0 2 DATA1 0 31 mmSDMA3_PAGE_MIDCMD_DATA2 0 0x51a 1 0 2 DATA2 0 31 mmSDMA3_PAGE_MIDCMD_DATA3 0 0x51b 1 0 2 DATA3 0 31 mmSDMA3_PAGE_MIDCMD_DATA4 0 0x51c 1 0 2 DATA4 0 31 mmSDMA3_PAGE_MIDCMD_DATA5 0 0x51d 1 0 2 DATA5 0 31 mmSDMA3_PAGE_MIDCMD_DATA6 0 0x51e 1 0 2 DATA6 0 31 mmSDMA3_PAGE_MIDCMD_DATA7 0 0x51f 1 0 2 DATA7 0 31 mmSDMA3_PAGE_MIDCMD_DATA8 0 0x520 1 0 2 DATA8 0 31 mmSDMA3_PAGE_MIDCMD_DATA9 0 0x521 1 0 2 DATA9 0 31 mmSDMA3_PAGE_MIDCMD_DATA10 0 0x522 1 0 2 DATA10 0 31 mmSDMA3_PAGE_MIDCMD_CNTL 0 0x523 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC0_RB_CNTL 0 0x530 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC0_RB_BASE 0 0x531 1 0 2 ADDR 0 31 mmSDMA3_RLC0_RB_BASE_HI 0 0x532 1 0 2 ADDR 0 23 mmSDMA3_RLC0_RB_RPTR 0 0x533 1 0 2 OFFSET 0 31 mmSDMA3_RLC0_RB_RPTR_HI 0 0x534 1 0 2 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR 0 0x535 1 0 2 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR_HI 0 0x536 1 0 2 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0 0x537 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0 0x538 1 0 2 ADDR 0 31 mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0 0x539 1 0 2 ADDR 2 31 mmSDMA3_RLC0_IB_CNTL 0 0x53a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC0_IB_RPTR 0 0x53b 1 0 2 OFFSET 2 21 mmSDMA3_RLC0_IB_OFFSET 0 0x53c 1 0 2 OFFSET 2 21 mmSDMA3_RLC0_IB_BASE_LO 0 0x53d 1 0 2 ADDR 5 31 mmSDMA3_RLC0_IB_BASE_HI 0 0x53e 1 0 2 ADDR 0 31 mmSDMA3_RLC0_IB_SIZE 0 0x53f 1 0 2 SIZE 0 19 mmSDMA3_RLC0_SKIP_CNTL 0 0x540 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC0_CONTEXT_STATUS 0 0x541 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC0_DOORBELL 0 0x542 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC0_STATUS 0 0x558 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC0_DOORBELL_LOG 0 0x559 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC0_WATERMARK 0 0x55a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC0_DOORBELL_OFFSET 0 0x55b 1 0 2 OFFSET 2 27 mmSDMA3_RLC0_CSA_ADDR_LO 0 0x55c 1 0 2 ADDR 2 31 mmSDMA3_RLC0_CSA_ADDR_HI 0 0x55d 1 0 2 ADDR 0 31 mmSDMA3_RLC0_IB_SUB_REMAIN 0 0x55f 1 0 2 SIZE 0 13 mmSDMA3_RLC0_PREEMPT 0 0x560 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC0_DUMMY_REG 0 0x561 1 0 2 DUMMY 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x562 1 0 2 ADDR 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x563 1 0 2 ADDR 2 31 mmSDMA3_RLC0_RB_AQL_CNTL 0 0x564 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC0_MINOR_PTR_UPDATE 0 0x565 1 0 2 ENABLE 0 0 mmSDMA3_RLC0_MIDCMD_DATA0 0 0x570 1 0 2 DATA0 0 31 mmSDMA3_RLC0_MIDCMD_DATA1 0 0x571 1 0 2 DATA1 0 31 mmSDMA3_RLC0_MIDCMD_DATA2 0 0x572 1 0 2 DATA2 0 31 mmSDMA3_RLC0_MIDCMD_DATA3 0 0x573 1 0 2 DATA3 0 31 mmSDMA3_RLC0_MIDCMD_DATA4 0 0x574 1 0 2 DATA4 0 31 mmSDMA3_RLC0_MIDCMD_DATA5 0 0x575 1 0 2 DATA5 0 31 mmSDMA3_RLC0_MIDCMD_DATA6 0 0x576 1 0 2 DATA6 0 31 mmSDMA3_RLC0_MIDCMD_DATA7 0 0x577 1 0 2 DATA7 0 31 mmSDMA3_RLC0_MIDCMD_DATA8 0 0x578 1 0 2 DATA8 0 31 mmSDMA3_RLC0_MIDCMD_DATA9 0 0x579 1 0 2 DATA9 0 31 mmSDMA3_RLC0_MIDCMD_DATA10 0 0x57a 1 0 2 DATA10 0 31 mmSDMA3_RLC0_MIDCMD_CNTL 0 0x57b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC1_RB_CNTL 0 0x588 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC1_RB_BASE 0 0x589 1 0 2 ADDR 0 31 mmSDMA3_RLC1_RB_BASE_HI 0 0x58a 1 0 2 ADDR 0 23 mmSDMA3_RLC1_RB_RPTR 0 0x58b 1 0 2 OFFSET 0 31 mmSDMA3_RLC1_RB_RPTR_HI 0 0x58c 1 0 2 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR 0 0x58d 1 0 2 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR_HI 0 0x58e 1 0 2 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0 0x58f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0 0x590 1 0 2 ADDR 0 31 mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0 0x591 1 0 2 ADDR 2 31 mmSDMA3_RLC1_IB_CNTL 0 0x592 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC1_IB_RPTR 0 0x593 1 0 2 OFFSET 2 21 mmSDMA3_RLC1_IB_OFFSET 0 0x594 1 0 2 OFFSET 2 21 mmSDMA3_RLC1_IB_BASE_LO 0 0x595 1 0 2 ADDR 5 31 mmSDMA3_RLC1_IB_BASE_HI 0 0x596 1 0 2 ADDR 0 31 mmSDMA3_RLC1_IB_SIZE 0 0x597 1 0 2 SIZE 0 19 mmSDMA3_RLC1_SKIP_CNTL 0 0x598 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC1_CONTEXT_STATUS 0 0x599 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC1_DOORBELL 0 0x59a 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC1_STATUS 0 0x5b0 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC1_DOORBELL_LOG 0 0x5b1 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC1_WATERMARK 0 0x5b2 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC1_DOORBELL_OFFSET 0 0x5b3 1 0 2 OFFSET 2 27 mmSDMA3_RLC1_CSA_ADDR_LO 0 0x5b4 1 0 2 ADDR 2 31 mmSDMA3_RLC1_CSA_ADDR_HI 0 0x5b5 1 0 2 ADDR 0 31 mmSDMA3_RLC1_IB_SUB_REMAIN 0 0x5b7 1 0 2 SIZE 0 13 mmSDMA3_RLC1_PREEMPT 0 0x5b8 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC1_DUMMY_REG 0 0x5b9 1 0 2 DUMMY 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x5ba 1 0 2 ADDR 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x5bb 1 0 2 ADDR 2 31 mmSDMA3_RLC1_RB_AQL_CNTL 0 0x5bc 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC1_MINOR_PTR_UPDATE 0 0x5bd 1 0 2 ENABLE 0 0 mmSDMA3_RLC1_MIDCMD_DATA0 0 0x5c8 1 0 2 DATA0 0 31 mmSDMA3_RLC1_MIDCMD_DATA1 0 0x5c9 1 0 2 DATA1 0 31 mmSDMA3_RLC1_MIDCMD_DATA2 0 0x5ca 1 0 2 DATA2 0 31 mmSDMA3_RLC1_MIDCMD_DATA3 0 0x5cb 1 0 2 DATA3 0 31 mmSDMA3_RLC1_MIDCMD_DATA4 0 0x5cc 1 0 2 DATA4 0 31 mmSDMA3_RLC1_MIDCMD_DATA5 0 0x5cd 1 0 2 DATA5 0 31 mmSDMA3_RLC1_MIDCMD_DATA6 0 0x5ce 1 0 2 DATA6 0 31 mmSDMA3_RLC1_MIDCMD_DATA7 0 0x5cf 1 0 2 DATA7 0 31 mmSDMA3_RLC1_MIDCMD_DATA8 0 0x5d0 1 0 2 DATA8 0 31 mmSDMA3_RLC1_MIDCMD_DATA9 0 0x5d1 1 0 2 DATA9 0 31 mmSDMA3_RLC1_MIDCMD_DATA10 0 0x5d2 1 0 2 DATA10 0 31 mmSDMA3_RLC1_MIDCMD_CNTL 0 0x5d3 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC2_RB_CNTL 0 0x5e0 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC2_RB_BASE 0 0x5e1 1 0 2 ADDR 0 31 mmSDMA3_RLC2_RB_BASE_HI 0 0x5e2 1 0 2 ADDR 0 23 mmSDMA3_RLC2_RB_RPTR 0 0x5e3 1 0 2 OFFSET 0 31 mmSDMA3_RLC2_RB_RPTR_HI 0 0x5e4 1 0 2 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR 0 0x5e5 1 0 2 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR_HI 0 0x5e6 1 0 2 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0 0x5e7 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0 0x5e8 1 0 2 ADDR 0 31 mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0 0x5e9 1 0 2 ADDR 2 31 mmSDMA3_RLC2_IB_CNTL 0 0x5ea 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC2_IB_RPTR 0 0x5eb 1 0 2 OFFSET 2 21 mmSDMA3_RLC2_IB_OFFSET 0 0x5ec 1 0 2 OFFSET 2 21 mmSDMA3_RLC2_IB_BASE_LO 0 0x5ed 1 0 2 ADDR 5 31 mmSDMA3_RLC2_IB_BASE_HI 0 0x5ee 1 0 2 ADDR 0 31 mmSDMA3_RLC2_IB_SIZE 0 0x5ef 1 0 2 SIZE 0 19 mmSDMA3_RLC2_SKIP_CNTL 0 0x5f0 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC2_CONTEXT_STATUS 0 0x5f1 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC2_DOORBELL 0 0x5f2 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC2_STATUS 0 0x608 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC2_DOORBELL_LOG 0 0x609 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC2_WATERMARK 0 0x60a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC2_DOORBELL_OFFSET 0 0x60b 1 0 2 OFFSET 2 27 mmSDMA3_RLC2_CSA_ADDR_LO 0 0x60c 1 0 2 ADDR 2 31 mmSDMA3_RLC2_CSA_ADDR_HI 0 0x60d 1 0 2 ADDR 0 31 mmSDMA3_RLC2_IB_SUB_REMAIN 0 0x60f 1 0 2 SIZE 0 13 mmSDMA3_RLC2_PREEMPT 0 0x610 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC2_DUMMY_REG 0 0x611 1 0 2 DUMMY 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x612 1 0 2 ADDR 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x613 1 0 2 ADDR 2 31 mmSDMA3_RLC2_RB_AQL_CNTL 0 0x614 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC2_MINOR_PTR_UPDATE 0 0x615 1 0 2 ENABLE 0 0 mmSDMA3_RLC2_MIDCMD_DATA0 0 0x620 1 0 2 DATA0 0 31 mmSDMA3_RLC2_MIDCMD_DATA1 0 0x621 1 0 2 DATA1 0 31 mmSDMA3_RLC2_MIDCMD_DATA2 0 0x622 1 0 2 DATA2 0 31 mmSDMA3_RLC2_MIDCMD_DATA3 0 0x623 1 0 2 DATA3 0 31 mmSDMA3_RLC2_MIDCMD_DATA4 0 0x624 1 0 2 DATA4 0 31 mmSDMA3_RLC2_MIDCMD_DATA5 0 0x625 1 0 2 DATA5 0 31 mmSDMA3_RLC2_MIDCMD_DATA6 0 0x626 1 0 2 DATA6 0 31 mmSDMA3_RLC2_MIDCMD_DATA7 0 0x627 1 0 2 DATA7 0 31 mmSDMA3_RLC2_MIDCMD_DATA8 0 0x628 1 0 2 DATA8 0 31 mmSDMA3_RLC2_MIDCMD_DATA9 0 0x629 1 0 2 DATA9 0 31 mmSDMA3_RLC2_MIDCMD_DATA10 0 0x62a 1 0 2 DATA10 0 31 mmSDMA3_RLC2_MIDCMD_CNTL 0 0x62b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC3_RB_CNTL 0 0x638 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC3_RB_BASE 0 0x639 1 0 2 ADDR 0 31 mmSDMA3_RLC3_RB_BASE_HI 0 0x63a 1 0 2 ADDR 0 23 mmSDMA3_RLC3_RB_RPTR 0 0x63b 1 0 2 OFFSET 0 31 mmSDMA3_RLC3_RB_RPTR_HI 0 0x63c 1 0 2 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR 0 0x63d 1 0 2 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR_HI 0 0x63e 1 0 2 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0 0x63f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0 0x640 1 0 2 ADDR 0 31 mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0 0x641 1 0 2 ADDR 2 31 mmSDMA3_RLC3_IB_CNTL 0 0x642 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC3_IB_RPTR 0 0x643 1 0 2 OFFSET 2 21 mmSDMA3_RLC3_IB_OFFSET 0 0x644 1 0 2 OFFSET 2 21 mmSDMA3_RLC3_IB_BASE_LO 0 0x645 1 0 2 ADDR 5 31 mmSDMA3_RLC3_IB_BASE_HI 0 0x646 1 0 2 ADDR 0 31 mmSDMA3_RLC3_IB_SIZE 0 0x647 1 0 2 SIZE 0 19 mmSDMA3_RLC3_SKIP_CNTL 0 0x648 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC3_CONTEXT_STATUS 0 0x649 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC3_DOORBELL 0 0x64a 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC3_STATUS 0 0x660 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC3_DOORBELL_LOG 0 0x661 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC3_WATERMARK 0 0x662 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC3_DOORBELL_OFFSET 0 0x663 1 0 2 OFFSET 2 27 mmSDMA3_RLC3_CSA_ADDR_LO 0 0x664 1 0 2 ADDR 2 31 mmSDMA3_RLC3_CSA_ADDR_HI 0 0x665 1 0 2 ADDR 0 31 mmSDMA3_RLC3_IB_SUB_REMAIN 0 0x667 1 0 2 SIZE 0 13 mmSDMA3_RLC3_PREEMPT 0 0x668 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC3_DUMMY_REG 0 0x669 1 0 2 DUMMY 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x66a 1 0 2 ADDR 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x66b 1 0 2 ADDR 2 31 mmSDMA3_RLC3_RB_AQL_CNTL 0 0x66c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC3_MINOR_PTR_UPDATE 0 0x66d 1 0 2 ENABLE 0 0 mmSDMA3_RLC3_MIDCMD_DATA0 0 0x678 1 0 2 DATA0 0 31 mmSDMA3_RLC3_MIDCMD_DATA1 0 0x679 1 0 2 DATA1 0 31 mmSDMA3_RLC3_MIDCMD_DATA2 0 0x67a 1 0 2 DATA2 0 31 mmSDMA3_RLC3_MIDCMD_DATA3 0 0x67b 1 0 2 DATA3 0 31 mmSDMA3_RLC3_MIDCMD_DATA4 0 0x67c 1 0 2 DATA4 0 31 mmSDMA3_RLC3_MIDCMD_DATA5 0 0x67d 1 0 2 DATA5 0 31 mmSDMA3_RLC3_MIDCMD_DATA6 0 0x67e 1 0 2 DATA6 0 31 mmSDMA3_RLC3_MIDCMD_DATA7 0 0x67f 1 0 2 DATA7 0 31 mmSDMA3_RLC3_MIDCMD_DATA8 0 0x680 1 0 2 DATA8 0 31 mmSDMA3_RLC3_MIDCMD_DATA9 0 0x681 1 0 2 DATA9 0 31 mmSDMA3_RLC3_MIDCMD_DATA10 0 0x682 1 0 2 DATA10 0 31 mmSDMA3_RLC3_MIDCMD_CNTL 0 0x683 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC4_RB_CNTL 0 0x690 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC4_RB_BASE 0 0x691 1 0 2 ADDR 0 31 mmSDMA3_RLC4_RB_BASE_HI 0 0x692 1 0 2 ADDR 0 23 mmSDMA3_RLC4_RB_RPTR 0 0x693 1 0 2 OFFSET 0 31 mmSDMA3_RLC4_RB_RPTR_HI 0 0x694 1 0 2 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR 0 0x695 1 0 2 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR_HI 0 0x696 1 0 2 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0 0x697 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0 0x698 1 0 2 ADDR 0 31 mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0 0x699 1 0 2 ADDR 2 31 mmSDMA3_RLC4_IB_CNTL 0 0x69a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC4_IB_RPTR 0 0x69b 1 0 2 OFFSET 2 21 mmSDMA3_RLC4_IB_OFFSET 0 0x69c 1 0 2 OFFSET 2 21 mmSDMA3_RLC4_IB_BASE_LO 0 0x69d 1 0 2 ADDR 5 31 mmSDMA3_RLC4_IB_BASE_HI 0 0x69e 1 0 2 ADDR 0 31 mmSDMA3_RLC4_IB_SIZE 0 0x69f 1 0 2 SIZE 0 19 mmSDMA3_RLC4_SKIP_CNTL 0 0x6a0 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC4_CONTEXT_STATUS 0 0x6a1 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC4_DOORBELL 0 0x6a2 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC4_STATUS 0 0x6b8 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC4_DOORBELL_LOG 0 0x6b9 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC4_WATERMARK 0 0x6ba 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC4_DOORBELL_OFFSET 0 0x6bb 1 0 2 OFFSET 2 27 mmSDMA3_RLC4_CSA_ADDR_LO 0 0x6bc 1 0 2 ADDR 2 31 mmSDMA3_RLC4_CSA_ADDR_HI 0 0x6bd 1 0 2 ADDR 0 31 mmSDMA3_RLC4_IB_SUB_REMAIN 0 0x6bf 1 0 2 SIZE 0 13 mmSDMA3_RLC4_PREEMPT 0 0x6c0 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC4_DUMMY_REG 0 0x6c1 1 0 2 DUMMY 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x6c2 1 0 2 ADDR 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x6c3 1 0 2 ADDR 2 31 mmSDMA3_RLC4_RB_AQL_CNTL 0 0x6c4 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC4_MINOR_PTR_UPDATE 0 0x6c5 1 0 2 ENABLE 0 0 mmSDMA3_RLC4_MIDCMD_DATA0 0 0x6d0 1 0 2 DATA0 0 31 mmSDMA3_RLC4_MIDCMD_DATA1 0 0x6d1 1 0 2 DATA1 0 31 mmSDMA3_RLC4_MIDCMD_DATA2 0 0x6d2 1 0 2 DATA2 0 31 mmSDMA3_RLC4_MIDCMD_DATA3 0 0x6d3 1 0 2 DATA3 0 31 mmSDMA3_RLC4_MIDCMD_DATA4 0 0x6d4 1 0 2 DATA4 0 31 mmSDMA3_RLC4_MIDCMD_DATA5 0 0x6d5 1 0 2 DATA5 0 31 mmSDMA3_RLC4_MIDCMD_DATA6 0 0x6d6 1 0 2 DATA6 0 31 mmSDMA3_RLC4_MIDCMD_DATA7 0 0x6d7 1 0 2 DATA7 0 31 mmSDMA3_RLC4_MIDCMD_DATA8 0 0x6d8 1 0 2 DATA8 0 31 mmSDMA3_RLC4_MIDCMD_DATA9 0 0x6d9 1 0 2 DATA9 0 31 mmSDMA3_RLC4_MIDCMD_DATA10 0 0x6da 1 0 2 DATA10 0 31 mmSDMA3_RLC4_MIDCMD_CNTL 0 0x6db 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC5_RB_CNTL 0 0x6e8 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC5_RB_BASE 0 0x6e9 1 0 2 ADDR 0 31 mmSDMA3_RLC5_RB_BASE_HI 0 0x6ea 1 0 2 ADDR 0 23 mmSDMA3_RLC5_RB_RPTR 0 0x6eb 1 0 2 OFFSET 0 31 mmSDMA3_RLC5_RB_RPTR_HI 0 0x6ec 1 0 2 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR 0 0x6ed 1 0 2 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR_HI 0 0x6ee 1 0 2 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0 0x6ef 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0 0x6f0 1 0 2 ADDR 0 31 mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0 0x6f1 1 0 2 ADDR 2 31 mmSDMA3_RLC5_IB_CNTL 0 0x6f2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC5_IB_RPTR 0 0x6f3 1 0 2 OFFSET 2 21 mmSDMA3_RLC5_IB_OFFSET 0 0x6f4 1 0 2 OFFSET 2 21 mmSDMA3_RLC5_IB_BASE_LO 0 0x6f5 1 0 2 ADDR 5 31 mmSDMA3_RLC5_IB_BASE_HI 0 0x6f6 1 0 2 ADDR 0 31 mmSDMA3_RLC5_IB_SIZE 0 0x6f7 1 0 2 SIZE 0 19 mmSDMA3_RLC5_SKIP_CNTL 0 0x6f8 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC5_CONTEXT_STATUS 0 0x6f9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC5_DOORBELL 0 0x6fa 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC5_STATUS 0 0x710 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC5_DOORBELL_LOG 0 0x711 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC5_WATERMARK 0 0x712 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC5_DOORBELL_OFFSET 0 0x713 1 0 2 OFFSET 2 27 mmSDMA3_RLC5_CSA_ADDR_LO 0 0x714 1 0 2 ADDR 2 31 mmSDMA3_RLC5_CSA_ADDR_HI 0 0x715 1 0 2 ADDR 0 31 mmSDMA3_RLC5_IB_SUB_REMAIN 0 0x717 1 0 2 SIZE 0 13 mmSDMA3_RLC5_PREEMPT 0 0x718 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC5_DUMMY_REG 0 0x719 1 0 2 DUMMY 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x71a 1 0 2 ADDR 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x71b 1 0 2 ADDR 2 31 mmSDMA3_RLC5_RB_AQL_CNTL 0 0x71c 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC5_MINOR_PTR_UPDATE 0 0x71d 1 0 2 ENABLE 0 0 mmSDMA3_RLC5_MIDCMD_DATA0 0 0x728 1 0 2 DATA0 0 31 mmSDMA3_RLC5_MIDCMD_DATA1 0 0x729 1 0 2 DATA1 0 31 mmSDMA3_RLC5_MIDCMD_DATA2 0 0x72a 1 0 2 DATA2 0 31 mmSDMA3_RLC5_MIDCMD_DATA3 0 0x72b 1 0 2 DATA3 0 31 mmSDMA3_RLC5_MIDCMD_DATA4 0 0x72c 1 0 2 DATA4 0 31 mmSDMA3_RLC5_MIDCMD_DATA5 0 0x72d 1 0 2 DATA5 0 31 mmSDMA3_RLC5_MIDCMD_DATA6 0 0x72e 1 0 2 DATA6 0 31 mmSDMA3_RLC5_MIDCMD_DATA7 0 0x72f 1 0 2 DATA7 0 31 mmSDMA3_RLC5_MIDCMD_DATA8 0 0x730 1 0 2 DATA8 0 31 mmSDMA3_RLC5_MIDCMD_DATA9 0 0x731 1 0 2 DATA9 0 31 mmSDMA3_RLC5_MIDCMD_DATA10 0 0x732 1 0 2 DATA10 0 31 mmSDMA3_RLC5_MIDCMD_CNTL 0 0x733 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC6_RB_CNTL 0 0x740 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC6_RB_BASE 0 0x741 1 0 2 ADDR 0 31 mmSDMA3_RLC6_RB_BASE_HI 0 0x742 1 0 2 ADDR 0 23 mmSDMA3_RLC6_RB_RPTR 0 0x743 1 0 2 OFFSET 0 31 mmSDMA3_RLC6_RB_RPTR_HI 0 0x744 1 0 2 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR 0 0x745 1 0 2 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR_HI 0 0x746 1 0 2 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0 0x747 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0 0x748 1 0 2 ADDR 0 31 mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0 0x749 1 0 2 ADDR 2 31 mmSDMA3_RLC6_IB_CNTL 0 0x74a 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC6_IB_RPTR 0 0x74b 1 0 2 OFFSET 2 21 mmSDMA3_RLC6_IB_OFFSET 0 0x74c 1 0 2 OFFSET 2 21 mmSDMA3_RLC6_IB_BASE_LO 0 0x74d 1 0 2 ADDR 5 31 mmSDMA3_RLC6_IB_BASE_HI 0 0x74e 1 0 2 ADDR 0 31 mmSDMA3_RLC6_IB_SIZE 0 0x74f 1 0 2 SIZE 0 19 mmSDMA3_RLC6_SKIP_CNTL 0 0x750 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC6_CONTEXT_STATUS 0 0x751 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC6_DOORBELL 0 0x752 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC6_STATUS 0 0x768 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC6_DOORBELL_LOG 0 0x769 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC6_WATERMARK 0 0x76a 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC6_DOORBELL_OFFSET 0 0x76b 1 0 2 OFFSET 2 27 mmSDMA3_RLC6_CSA_ADDR_LO 0 0x76c 1 0 2 ADDR 2 31 mmSDMA3_RLC6_CSA_ADDR_HI 0 0x76d 1 0 2 ADDR 0 31 mmSDMA3_RLC6_IB_SUB_REMAIN 0 0x76f 1 0 2 SIZE 0 13 mmSDMA3_RLC6_PREEMPT 0 0x770 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC6_DUMMY_REG 0 0x771 1 0 2 DUMMY 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x772 1 0 2 ADDR 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x773 1 0 2 ADDR 2 31 mmSDMA3_RLC6_RB_AQL_CNTL 0 0x774 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC6_MINOR_PTR_UPDATE 0 0x775 1 0 2 ENABLE 0 0 mmSDMA3_RLC6_MIDCMD_DATA0 0 0x780 1 0 2 DATA0 0 31 mmSDMA3_RLC6_MIDCMD_DATA1 0 0x781 1 0 2 DATA1 0 31 mmSDMA3_RLC6_MIDCMD_DATA2 0 0x782 1 0 2 DATA2 0 31 mmSDMA3_RLC6_MIDCMD_DATA3 0 0x783 1 0 2 DATA3 0 31 mmSDMA3_RLC6_MIDCMD_DATA4 0 0x784 1 0 2 DATA4 0 31 mmSDMA3_RLC6_MIDCMD_DATA5 0 0x785 1 0 2 DATA5 0 31 mmSDMA3_RLC6_MIDCMD_DATA6 0 0x786 1 0 2 DATA6 0 31 mmSDMA3_RLC6_MIDCMD_DATA7 0 0x787 1 0 2 DATA7 0 31 mmSDMA3_RLC6_MIDCMD_DATA8 0 0x788 1 0 2 DATA8 0 31 mmSDMA3_RLC6_MIDCMD_DATA9 0 0x789 1 0 2 DATA9 0 31 mmSDMA3_RLC6_MIDCMD_DATA10 0 0x78a 1 0 2 DATA10 0 31 mmSDMA3_RLC6_MIDCMD_CNTL 0 0x78b 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC7_RB_CNTL 0 0x798 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 RPTR_WB_IDLE 31 31 mmSDMA3_RLC7_RB_BASE 0 0x799 1 0 2 ADDR 0 31 mmSDMA3_RLC7_RB_BASE_HI 0 0x79a 1 0 2 ADDR 0 23 mmSDMA3_RLC7_RB_RPTR 0 0x79b 1 0 2 OFFSET 0 31 mmSDMA3_RLC7_RB_RPTR_HI 0 0x79c 1 0 2 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR 0 0x79d 1 0 2 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR_HI 0 0x79e 1 0 2 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0 0x79f 5 0 2 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0 0x7a0 1 0 2 ADDR 0 31 mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0 0x7a1 1 0 2 ADDR 2 31 mmSDMA3_RLC7_IB_CNTL 0 0x7a2 4 0 2 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC7_IB_RPTR 0 0x7a3 1 0 2 OFFSET 2 21 mmSDMA3_RLC7_IB_OFFSET 0 0x7a4 1 0 2 OFFSET 2 21 mmSDMA3_RLC7_IB_BASE_LO 0 0x7a5 1 0 2 ADDR 5 31 mmSDMA3_RLC7_IB_BASE_HI 0 0x7a6 1 0 2 ADDR 0 31 mmSDMA3_RLC7_IB_SIZE 0 0x7a7 1 0 2 SIZE 0 19 mmSDMA3_RLC7_SKIP_CNTL 0 0x7a8 1 0 2 SKIP_COUNT 0 19 mmSDMA3_RLC7_CONTEXT_STATUS 0 0x7a9 8 0 2 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC7_DOORBELL 0 0x7aa 2 0 2 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC7_STATUS 0 0x7c0 2 0 2 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC7_DOORBELL_LOG 0 0x7c1 2 0 2 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC7_WATERMARK 0 0x7c2 2 0 2 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC7_DOORBELL_OFFSET 0 0x7c3 1 0 2 OFFSET 2 27 mmSDMA3_RLC7_CSA_ADDR_LO 0 0x7c4 1 0 2 ADDR 2 31 mmSDMA3_RLC7_CSA_ADDR_HI 0 0x7c5 1 0 2 ADDR 0 31 mmSDMA3_RLC7_IB_SUB_REMAIN 0 0x7c7 1 0 2 SIZE 0 13 mmSDMA3_RLC7_PREEMPT 0 0x7c8 1 0 2 IB_PREEMPT 0 0 mmSDMA3_RLC7_DUMMY_REG 0 0x7c9 1 0 2 DUMMY 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x7ca 1 0 2 ADDR 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x7cb 1 0 2 ADDR 2 31 mmSDMA3_RLC7_RB_AQL_CNTL 0 0x7cc 6 0 2 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 MIDCMD_PREEMPT_ENABLE 16 16 MIDCMD_PREEMPT_DATA_RESTORE 17 17 OVERLAP_ENABLE 18 18 mmSDMA3_RLC7_MINOR_PTR_UPDATE 0 0x7cd 1 0 2 ENABLE 0 0 mmSDMA3_RLC7_MIDCMD_DATA0 0 0x7d8 1 0 2 DATA0 0 31 mmSDMA3_RLC7_MIDCMD_DATA1 0 0x7d9 1 0 2 DATA1 0 31 mmSDMA3_RLC7_MIDCMD_DATA2 0 0x7da 1 0 2 DATA2 0 31 mmSDMA3_RLC7_MIDCMD_DATA3 0 0x7db 1 0 2 DATA3 0 31 mmSDMA3_RLC7_MIDCMD_DATA4 0 0x7dc 1 0 2 DATA4 0 31 mmSDMA3_RLC7_MIDCMD_DATA5 0 0x7dd 1 0 2 DATA5 0 31 mmSDMA3_RLC7_MIDCMD_DATA6 0 0x7de 1 0 2 DATA6 0 31 mmSDMA3_RLC7_MIDCMD_DATA7 0 0x7df 1 0 2 DATA7 0 31 mmSDMA3_RLC7_MIDCMD_DATA8 0 0x7e0 1 0 2 DATA8 0 31 mmSDMA3_RLC7_MIDCMD_DATA9 0 0x7e1 1 0 2 DATA9 0 31 mmSDMA3_RLC7_MIDCMD_DATA10 0 0x7e2 1 0 2 DATA10 0 31 mmSDMA3_RLC7_MIDCMD_CNTL 0 0x7e3 4 0 2 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 ixPCC_STALL_PATTERN_CTRL 2 0x0 7 0 4294967295 PCC_STEP_INTERVAL 0 9 PCC_BEGIN_STEP 10 14 PCC_END_STEP 15 19 PCC_THROTTLE_PATTERN_BIT_NUMS 20 23 PCC_INST_THROT_INCR 24 24 PCC_INST_THROT_DECR 25 25 PCC_DITHER_MODE 26 26 ixPWRBRK_STALL_PATTERN_CTRL 2 0x1 4 0 4294967295 PWRBRK_STEP_INTERVAL 0 9 PWRBRK_BEGIN_STEP 10 14 PWRBRK_END_STEP 15 19 PWRBRK_THROTTLE_PATTERN_BIT_NUMS 20 23 ixPCC_STALL_PATTERN_1_2 2 0x6 2 0 4294967295 PCC_STALL_PATTERN_1 0 14 PCC_STALL_PATTERN_2 16 30 ixPCC_STALL_PATTERN_3_4 2 0x7 2 0 4294967295 PCC_STALL_PATTERN_3 0 14 PCC_STALL_PATTERN_4 16 30 ixPCC_STALL_PATTERN_5_6 2 0x8 2 0 4294967295 PCC_STALL_PATTERN_5 0 14 PCC_STALL_PATTERN_6 16 30 ixPCC_STALL_PATTERN_7 2 0x9 1 0 4294967295 PCC_STALL_PATTERN_7 0 14 ixPWRBRK_STALL_PATTERN_1_2 2 0xa 2 0 4294967295 PWRBRK_STALL_PATTERN_1 0 14 PWRBRK_STALL_PATTERN_2 16 30 ixPWRBRK_STALL_PATTERN_3_4 2 0xb 2 0 4294967295 PWRBRK_STALL_PATTERN_3 0 14 PWRBRK_STALL_PATTERN_4 16 30 ixPWRBRK_STALL_PATTERN_5_6 2 0xc 2 0 4294967295 PWRBRK_STALL_PATTERN_5 0 14 PWRBRK_STALL_PATTERN_6 16 30 ixPWRBRK_STALL_PATTERN_7 2 0xd 1 0 4294967295 PWRBRK_STALL_PATTERN_7 0 14 ixPCC_PWRBRK_HYSTERESIS_CTRL 2 0xe 2 0 4294967295 PCC_MAX_HYSTERESIS 0 7 PWRBRK_MAX_HYSTERESIS 8 15 ixEDC_STRETCH_PERF_COUNTER 2 0xf 1 0 4294967295 STRETCH_PERF_COUNTER 0 31 ixEDC_UNSTRETCH_PERF_COUNTER 2 0x10 1 0 4294967295 UNSTRETCH_PERF_COUNTER 0 31 ixEDC_STRETCH_NUM_PERF_COUNTER 2 0x11 1 0 4294967295 STRETCH_NUM_PERF_COUNTER 0 31 ixGC_CAC_ID 2 0x20 3 0 4294967295 CAC_BLOCK_ID 0 5 CAC_SIGNAL_ID 6 13 UNUSED_0 14 31 ixGC_CAC_CNTL 2 0x21 3 0 4294967295 CAC_FORCE_DISABLE 0 0 CAC_THRESHOLD 1 16 UNUSED_0 17 31 ixGC_CAC_OVR_SEL 2 0x22 1 0 4294967295 CAC_OVR_SEL 0 31 ixGC_CAC_OVR_VAL 2 0x23 1 0 4294967295 CAC_OVR_VAL 0 31 ixGC_CAC_WEIGHT_BCI_0 2 0x24 2 0 4294967295 WEIGHT_BCI_SIG0 0 15 WEIGHT_BCI_SIG1 16 31 ixGC_CAC_WEIGHT_CB_0 2 0x25 2 0 4294967295 WEIGHT_CB_SIG0 0 15 WEIGHT_CB_SIG1 16 31 ixGC_CAC_WEIGHT_CB_1 2 0x26 2 0 4294967295 WEIGHT_CB_SIG2 0 15 WEIGHT_CB_SIG3 16 31 ixGC_CAC_WEIGHT_CB_2 2 0x27 2 0 4294967295 WEIGHT_CB_SIG4 0 15 WEIGHT_CB_SIG5 16 31 ixGC_CAC_WEIGHT_CB_3 2 0x28 2 0 4294967295 WEIGHT_CB_SIG6 0 15 WEIGHT_CB_SIG7 16 31 ixGC_CAC_WEIGHT_CB_4 2 0x29 2 0 4294967295 WEIGHT_CB_SIG8 0 15 WEIGHT_CB_SIG9 16 31 ixGC_CAC_WEIGHT_CP_0 2 0x2a 2 0 4294967295 WEIGHT_CP_SIG0 0 15 WEIGHT_CP_SIG1 16 31 ixGC_CAC_WEIGHT_CP_1 2 0x2b 2 0 4294967295 WEIGHT_CP_SIG2 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_DB_0 2 0x2c 2 0 4294967295 WEIGHT_DB_SIG0 0 15 WEIGHT_DB_SIG1 16 31 ixGC_CAC_WEIGHT_DB_1 2 0x2d 2 0 4294967295 WEIGHT_DB_SIG2 0 15 WEIGHT_DB_SIG3 16 31 ixGC_CAC_WEIGHT_DB_2 2 0x2e 2 0 4294967295 WEIGHT_DB_SIG4 0 15 WEIGHT_DB_SIG5 16 31 ixGC_CAC_WEIGHT_DB_3 2 0x2f 2 0 4294967295 WEIGHT_DB_SIG6 0 15 WEIGHT_DB_SIG7 16 31 ixGC_CAC_WEIGHT_DB_4 2 0x30 2 0 4294967295 WEIGHT_DB_SIG8 0 15 WEIGHT_DB_SIG9 16 31 ixGC_CAC_WEIGHT_GDS_0 2 0x31 2 0 4294967295 WEIGHT_GDS_SIG0 0 15 WEIGHT_GDS_SIG1 16 31 ixGC_CAC_WEIGHT_GDS_1 2 0x32 2 0 4294967295 WEIGHT_GDS_SIG2 0 15 WEIGHT_GDS_SIG3 16 31 ixGC_CAC_WEIGHT_GDS_2 2 0x33 1 0 4294967295 WEIGHT_GDS_SIG4 0 15 ixGC_CAC_WEIGHT_LDS_0 2 0x34 2 0 4294967295 WEIGHT_LDS_SIG0 0 15 WEIGHT_LDS_SIG1 16 31 ixGC_CAC_WEIGHT_LDS_1 2 0x35 2 0 4294967295 WEIGHT_LDS_SIG2 0 15 WEIGHT_LDS_SIG3 16 31 ixGC_CAC_WEIGHT_LDS_2 2 0x36 2 0 4294967295 WEIGHT_LDS_SIG4 0 15 WEIGHT_LDS_SIG5 16 31 ixGC_CAC_WEIGHT_LDS_3 2 0x37 2 0 4294967295 WEIGHT_LDS_SIG6 0 15 WEIGHT_LDS_SIG7 16 31 ixGC_CAC_WEIGHT_LDS_4 2 0x38 2 0 4294967295 WEIGHT_LDS_SIG8 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_PA_0 2 0x39 2 0 4294967295 WEIGHT_PA_SIG0 0 15 WEIGHT_PA_SIG1 16 31 ixGC_CAC_WEIGHT_PA_1 2 0x3a 2 0 4294967295 WEIGHT_PA_SIG2 0 15 WEIGHT_PA_SIG3 16 31 ixGC_CAC_WEIGHT_PA_2 2 0x3b 2 0 4294967295 WEIGHT_PA_SIG4 0 15 WEIGHT_PA_SIG5 16 31 ixGC_CAC_WEIGHT_PA_3 2 0x3c 2 0 4294967295 WEIGHT_PA_SIG6 0 15 WEIGHT_PA_SIG7 16 31 ixGC_CAC_WEIGHT_PC_0 2 0x3d 2 0 4294967295 WEIGHT_PC_SIG0 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_SC_0 2 0x3e 2 0 4294967295 WEIGHT_SC_SIG0 0 15 WEIGHT_SC_SIG1 16 31 ixGC_CAC_WEIGHT_SC_1 2 0x3f 2 0 4294967295 WEIGHT_SC_SIG2 0 15 WEIGHT_SC_SIG3 16 31 ixGC_CAC_WEIGHT_SC_2 2 0x40 2 0 4294967295 WEIGHT_SC_SIG4 0 15 WEIGHT_SC_SIG5 16 31 ixGC_CAC_WEIGHT_SC_3 2 0x41 2 0 4294967295 WEIGHT_SC_SIG6 0 15 WEIGHT_SC_SIG7 16 31 ixGC_CAC_WEIGHT_SPI_0 2 0x42 2 0 4294967295 WEIGHT_SPI_SIG0 0 15 WEIGHT_SPI_SIG1 16 31 ixGC_CAC_WEIGHT_SPI_1 2 0x43 2 0 4294967295 WEIGHT_SPI_SIG2 0 15 WEIGHT_SPI_SIG3 16 31 ixGC_CAC_WEIGHT_SPI_2 2 0x44 2 0 4294967295 WEIGHT_SPI_SIG4 0 15 WEIGHT_SPI_SIG5 16 31 ixGC_CAC_WEIGHT_SQ_0 2 0x45 2 0 4294967295 WEIGHT_SQ_SIG0 0 15 WEIGHT_SQ_SIG1 16 31 ixGC_CAC_WEIGHT_SQ_1 2 0x46 2 0 4294967295 WEIGHT_SQ_SIG2 0 15 WEIGHT_SQ_SIG3 16 31 ixGC_CAC_WEIGHT_SQ_2 2 0x47 2 0 4294967295 WEIGHT_SQ_SIG4 0 15 WEIGHT_SQ_SIG5 16 31 ixGC_CAC_WEIGHT_SQ_3 2 0x48 2 0 4294967295 WEIGHT_SQ_SIG6 0 15 WEIGHT_SQ_SIG7 16 31 ixGC_CAC_WEIGHT_SX_0 2 0x49 2 0 4294967295 WEIGHT_SX_SIG0 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_SXRB_0 2 0x4a 2 0 4294967295 WEIGHT_SXRB_SIG0 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_TA_0 2 0x4b 2 0 4294967295 WEIGHT_TA_SIG0 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_TCP_0 2 0x4c 2 0 4294967295 WEIGHT_TCP_SIG0 0 15 WEIGHT_TCP_SIG1 16 31 ixGC_CAC_WEIGHT_TCP_1 2 0x4d 2 0 4294967295 WEIGHT_TCP_SIG2 0 15 WEIGHT_TCP_SIG3 16 31 ixGC_CAC_WEIGHT_TCP_2 2 0x4e 2 0 4294967295 WEIGHT_TCP_SIG4 0 15 WEIGHT_TCP_SIG5 16 31 ixGC_CAC_WEIGHT_TCP_3 2 0x4f 2 0 4294967295 WEIGHT_TCP_SIG6 0 15 WEIGHT_TCP_SIG7 16 31 ixGC_CAC_WEIGHT_TD_0 2 0x50 2 0 4294967295 WEIGHT_TD_SIG0 0 15 WEIGHT_TD_SIG1 16 31 ixGC_CAC_WEIGHT_TD_1 2 0x51 2 0 4294967295 WEIGHT_TD_SIG2 0 15 WEIGHT_TD_SIG3 16 31 ixGC_CAC_WEIGHT_TD_2 2 0x52 2 0 4294967295 WEIGHT_TD_SIG4 0 15 WEIGHT_TD_SIG5 16 31 ixGC_CAC_WEIGHT_TD_3 2 0x53 2 0 4294967295 WEIGHT_TD_SIG6 0 15 WEIGHT_TD_SIG7 16 31 ixGC_CAC_WEIGHT_TD_4 2 0x54 2 0 4294967295 WEIGHT_TD_SIG8 0 15 WEIGHT_TD_SIG9 16 31 ixGC_CAC_WEIGHT_TD_5 2 0x55 1 0 4294967295 WEIGHT_TD_SIG10 0 15 ixGC_CAC_WEIGHT_RMI_0 2 0x56 2 0 4294967295 WEIGHT_RMI_SIG0 0 15 WEIGHT_RMI_SIG1 16 31 ixGC_CAC_WEIGHT_RMI_1 2 0x57 2 0 4294967295 WEIGHT_RMI_SIG2 0 15 WEIGHT_RMI_SIG3 16 31 ixGC_CAC_WEIGHT_EA_0 2 0x58 2 0 4294967295 WEIGHT_EA_SIG0 0 15 WEIGHT_EA_SIG1 16 31 ixGC_CAC_WEIGHT_EA_1 2 0x59 2 0 4294967295 WEIGHT_EA_SIG2 0 15 WEIGHT_EA_SIG3 16 31 ixGC_CAC_WEIGHT_EA_2 2 0x5a 2 0 4294967295 WEIGHT_EA_SIG4 0 15 WEIGHT_EA_SIG5 16 31 ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 2 0x5b 2 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG0 0 15 WEIGHT_UTCL2_ATCL2_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 2 0x5c 2 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG2 0 15 WEIGHT_UTCL2_ATCL2_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 2 0x5d 2 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG4 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 2 0x5e 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG0 0 15 WEIGHT_UTCL2_ROUTER_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 2 0x5f 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG2 0 15 WEIGHT_UTCL2_ROUTER_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 2 0x60 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG4 0 15 WEIGHT_UTCL2_ROUTER_SIG5 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 2 0x61 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG6 0 15 WEIGHT_UTCL2_ROUTER_SIG7 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 2 0x62 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG8 0 15 WEIGHT_UTCL2_ROUTER_SIG9 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_0 2 0x63 2 0 4294967295 WEIGHT_UTCL2_VML2_SIG0 0 15 WEIGHT_UTCL2_VML2_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_1 2 0x64 2 0 4294967295 WEIGHT_UTCL2_VML2_SIG2 0 15 WEIGHT_UTCL2_VML2_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_2 2 0x65 2 0 4294967295 WEIGHT_UTCL2_VML2_SIG4 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_UTCL2_WALKER_0 2 0x66 2 0 4294967295 WEIGHT_UTCL2_WALKER_SIG0 0 15 WEIGHT_UTCL2_WALKER_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_WALKER_1 2 0x67 2 0 4294967295 WEIGHT_UTCL2_WALKER_SIG2 0 15 WEIGHT_UTCL2_WALKER_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_WALKER_2 2 0x68 2 0 4294967295 WEIGHT_UTCL2_WALKER_SIG4 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_CU_0 2 0x69 2 0 4294967295 WEIGHT_CU_SIG0 0 15 UNUSED_0 16 31 ixGC_CAC_WEIGHT_UTCL1_0 2 0x6a 1 0 4294967295 WEIGHT_UTCL1_SIG0 0 15 ixGC_CAC_WEIGHT_GE_0 2 0x6b 2 0 4294967295 WEIGHT_GE_SIG0 0 15 WEIGHT_GE_SIG1 16 31 ixGC_CAC_WEIGHT_GE_1 2 0x6c 2 0 4294967295 WEIGHT_GE_SIG2 0 15 WEIGHT_GE_SIG3 16 31 ixGC_CAC_WEIGHT_GE_2 2 0x6d 2 0 4294967295 WEIGHT_GE_SIG4 0 15 WEIGHT_GE_SIG5 16 31 ixGC_CAC_WEIGHT_GE_3 2 0x6e 2 0 4294967295 WEIGHT_GE_SIG6 0 15 WEIGHT_GE_SIG7 16 31 ixGC_CAC_WEIGHT_GE_4 2 0x6f 2 0 4294967295 WEIGHT_GE_SIG8 0 15 WEIGHT_GE_SIG9 16 31 ixGC_CAC_WEIGHT_GE_5 2 0x70 2 0 4294967295 WEIGHT_GE_SIG10 0 15 WEIGHT_GE_SIG11 16 31 ixGC_CAC_WEIGHT_GE_6 2 0x71 2 0 4294967295 WEIGHT_GE_SIG12 0 15 WEIGHT_GE_SIG13 16 31 ixGC_CAC_WEIGHT_GE_7 2 0x72 2 0 4294967295 WEIGHT_GE_SIG14 0 15 WEIGHT_GE_SIG15 16 31 ixGC_CAC_WEIGHT_GE_8 2 0x73 2 0 4294967295 WEIGHT_GE_SIG16 0 15 WEIGHT_GE_SIG17 16 31 ixGC_CAC_WEIGHT_GE_9 2 0x74 2 0 4294967295 WEIGHT_GE_SIG18 0 15 WEIGHT_GE_SIG19 16 31 ixGC_CAC_WEIGHT_GE_10 2 0x75 1 0 4294967295 WEIGHT_GE_SIG20 0 15 ixGC_CAC_WEIGHT_PMM_0 2 0x76 1 0 4294967295 WEIGHT_PMM_SIG0 0 15 ixGC_CAC_WEIGHT_GL2C_0 2 0x77 2 0 4294967295 WEIGHT_GL2C_SIG0 0 15 WEIGHT_GL2C_SIG1 16 31 ixGC_CAC_WEIGHT_GL2C_1 2 0x78 2 0 4294967295 WEIGHT_GL2C_SIG2 0 15 WEIGHT_GL2C_SIG3 16 31 ixGC_CAC_WEIGHT_GL2C_2 2 0x79 1 0 4294967295 WEIGHT_GL2C_SIG4 0 15 ixGC_CAC_WEIGHT_GUS_0 2 0x7a 2 0 4294967295 WEIGHT_GUS_SIG0 0 15 WEIGHT_GUS_SIG1 16 31 ixGC_CAC_WEIGHT_GUS_1 2 0x7b 1 0 4294967295 WEIGHT_GUS_SIG2 0 15 ixGC_CAC_WEIGHT_PH_0 2 0x7c 2 0 4294967295 WEIGHT_PH_SIG0 0 15 WEIGHT_PH_SIG1 16 31 ixGC_CAC_WEIGHT_PH_1 2 0x7d 2 0 4294967295 WEIGHT_PH_SIG2 0 15 WEIGHT_PH_SIG3 16 31 ixGC_CAC_WEIGHT_PH_2 2 0x7e 2 0 4294967295 WEIGHT_PH_SIG4 0 15 WEIGHT_PH_SIG5 16 31 ixGC_CAC_WEIGHT_PH_3 2 0x7f 2 0 4294967295 WEIGHT_PH_SIG6 0 15 WEIGHT_PH_SIG7 16 31 ixGC_CAC_WEIGHT_SDMA_0 2 0x80 2 0 4294967295 WEIGHT_SDMA_SIG0 0 15 WEIGHT_SDMA_SIG1 16 31 ixGC_CAC_WEIGHT_SDMA_1 2 0x81 2 0 4294967295 WEIGHT_SDMA_SIG2 0 15 WEIGHT_SDMA_SIG3 16 31 ixGC_CAC_WEIGHT_SDMA_2 2 0x82 2 0 4294967295 WEIGHT_SDMA_SIG4 0 15 WEIGHT_SDMA_SIG5 16 31 ixGC_CAC_WEIGHT_SDMA_3 2 0x83 2 0 4294967295 WEIGHT_SDMA_SIG6 0 15 WEIGHT_SDMA_SIG7 16 31 ixGC_CAC_WEIGHT_SDMA_4 2 0x84 2 0 4294967295 WEIGHT_SDMA_SIG8 0 15 WEIGHT_SDMA_SIG9 16 31 ixGC_CAC_WEIGHT_SDMA_5 2 0x85 2 0 4294967295 WEIGHT_SDMA_SIG10 0 15 WEIGHT_SDMA_SIG11 16 31 ixGC_CAC_WEIGHT_SP_0 2 0x86 2 0 4294967295 WEIGHT_SP_SIG0 0 15 WEIGHT_SP_SIG1 16 31 ixGC_CAC_WEIGHT_SP_1 2 0x87 1 0 4294967295 WEIGHT_SP_SIG2 0 15 ixGC_CAC_WEIGHT_GL1C_0 2 0x88 2 0 4294967295 WEIGHT_GL1C_SIG0 0 15 WEIGHT_GL1C_SIG1 16 31 ixGC_CAC_WEIGHT_GL1C_1 2 0x89 2 0 4294967295 WEIGHT_GL1C_SIG2 0 15 WEIGHT_GL1C_SIG3 16 31 ixGC_CAC_WEIGHT_GL1C_2 2 0x8a 1 0 4294967295 WEIGHT_GL1C_SIG4 0 15 ixGC_CAC_WEIGHT_CHC_0 2 0x8b 2 0 4294967295 WEIGHT_CHC_SIG0 0 15 WEIGHT_CHC_SIG1 16 31 ixGC_CAC_WEIGHT_CHC_1 2 0x8c 1 0 4294967295 WEIGHT_CHC_SIG2 0 15 ixGC_CAC_WEIGHT_SQC_0 2 0x8d 2 0 4294967295 WEIGHT_SQC_SIG0 0 15 WEIGHT_SQC_SIG1 16 31 ixGC_CAC_WEIGHT_SQC_1 2 0x8e 1 0 4294967295 WEIGHT_SQC_SIG2 0 15 ixGC_CAC_WEIGHT_RLC_0 2 0x8f 1 0 4294967295 WEIGHT_RLC_SIG0 0 15 ixGC_CAC_ACC_LDS0 2 0x100 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS1 2 0x101 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS2 2 0x102 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS3 2 0x103 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS4 2 0x104 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS5 2 0x105 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS6 2 0x106 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS7 2 0x107 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS8 2 0x108 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_BCI0 2 0x109 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_BCI1 2 0x10a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB0 2 0x10b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB1 2 0x10c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB2 2 0x10d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB3 2 0x10e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB4 2 0x10f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB5 2 0x110 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB6 2 0x111 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB7 2 0x112 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB8 2 0x113 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB9 2 0x114 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP0 2 0x115 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP1 2 0x116 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP2 2 0x117 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB0 2 0x118 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB1 2 0x119 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB2 2 0x11a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB3 2 0x11b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB4 2 0x11c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB5 2 0x11d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB6 2 0x11e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB7 2 0x11f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB8 2 0x120 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB9 2 0x121 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS0 2 0x122 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS1 2 0x123 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS2 2 0x124 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS3 2 0x125 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS4 2 0x126 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS5 2 0x127 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS6 2 0x128 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA0 2 0x129 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA1 2 0x12a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA2 2 0x12b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA3 2 0x12c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA4 2 0x12d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA5 2 0x12e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA6 2 0x12f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA7 2 0x130 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PC0 2 0x131 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC0 2 0x132 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC1 2 0x133 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC2 2 0x134 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC3 2 0x135 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC4 2 0x136 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC5 2 0x137 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC6 2 0x138 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC7 2 0x139 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI0 2 0x13a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI1 2 0x13b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI2 2 0x13c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI3 2 0x13d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI4 2 0x13e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI5 2 0x13f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ0_LOWER 2 0x140 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ0_UPPER 2 0x141 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ1_LOWER 2 0x142 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ1_UPPER 2 0x143 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ2_LOWER 2 0x144 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ2_UPPER 2 0x145 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ3_LOWER 2 0x146 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ3_UPPER 2 0x147 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ4_LOWER 2 0x148 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ4_UPPER 2 0x149 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ5_LOWER 2 0x14a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ5_UPPER 2 0x14b 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ6_LOWER 2 0x14c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ6_UPPER 2 0x14d 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ7_LOWER 2 0x14e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ7_UPPER 2 0x14f 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SQ8_LOWER 2 0x150 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ8_UPPER 2 0x151 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SX0 2 0x152 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SXRB0 2 0x153 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TA0 2 0x154 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP0 2 0x155 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP1 2 0x156 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP2 2 0x157 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP3 2 0x158 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP4 2 0x159 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP5 2 0x15a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP6 2 0x15b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP7 2 0x15c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD0 2 0x15d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD1 2 0x15e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD2 2 0x15f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD3 2 0x160 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD4 2 0x161 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD5 2 0x162 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD6 2 0x163 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD7 2 0x164 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD8 2 0x165 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD9 2 0x166 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD10 2 0x167 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_RMI0 2 0x168 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_RMI1 2 0x169 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_RMI2 2 0x16a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_RMI3 2 0x16b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA0 2 0x16c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA1 2 0x16d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA2 2 0x16e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA3 2 0x16f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA4 2 0x170 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA5 2 0x171 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL20 2 0x172 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL21 2 0x173 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL22 2 0x174 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL23 2 0x175 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL24 2 0x176 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER0 2 0x177 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER1 2 0x178 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER2 2 0x179 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER3 2 0x17a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER4 2 0x17b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER5 2 0x17c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER6 2 0x17d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER7 2 0x17e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER8 2 0x17f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER9 2 0x180 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML20 2 0x181 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML21 2 0x182 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML22 2 0x183 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML23 2 0x184 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML24 2 0x185 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER0 2 0x186 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER1 2 0x187 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER2 2 0x188 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER3 2 0x189 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER4 2 0x18a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU0 2 0x18b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL10 2 0x18c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CHC0 2 0x18d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CHC1 2 0x18e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CHC2 2 0x18f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE0 2 0x190 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE1 2 0x191 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE2 2 0x192 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE3 2 0x193 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE4 2 0x194 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE5 2 0x195 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE6 2 0x196 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE7 2 0x197 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE8 2 0x198 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE9 2 0x199 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE10 2 0x19a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE11 2 0x19b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE12 2 0x19c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE13 2 0x19d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE14 2 0x19e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE15 2 0x19f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE16 2 0x1a0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE17 2 0x1a1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE18 2 0x1a2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE19 2 0x1a3 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GE20 2 0x1a4 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PMM0 2 0x1a5 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL2C0 2 0x1a6 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL2C1 2 0x1a7 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL2C2 2 0x1a8 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL2C3 2 0x1a9 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL2C4 2 0x1aa 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GUS0 2 0x1ab 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GUS1 2 0x1ac 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GUS2 2 0x1ad 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH0 2 0x1ae 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH1 2 0x1af 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH2 2 0x1b0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH3 2 0x1b1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH4 2 0x1b2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH5 2 0x1b3 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH6 2 0x1b4 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PH7 2 0x1b5 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA0 2 0x1b6 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA1 2 0x1b7 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA2 2 0x1b8 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA3 2 0x1b9 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA4 2 0x1ba 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA5 2 0x1bb 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA6 2 0x1bc 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA7 2 0x1bd 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA8 2 0x1be 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA9 2 0x1bf 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA10 2 0x1c0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SDMA11 2 0x1c1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SP0_LOWER 2 0x1c2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SP0_UPPER 2 0x1c3 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SP1_LOWER 2 0x1c4 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SP1_UPPER 2 0x1c5 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_SP2_LOWER 2 0x1c6 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SP2_UPPER 2 0x1c7 2 0 4294967295 ACCUMULATOR_39_32 0 7 UNUSED_0 8 31 ixGC_CAC_ACC_GL1C0 2 0x1c8 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL1C1 2 0x1c9 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL1C2 2 0x1ca 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL1C3 2 0x1cb 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GL1C4 2 0x1cc 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQC0 2 0x1cd 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQC1 2 0x1ce 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQC2 2 0x1cf 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_RLC0 2 0x1d0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_BCI 2 0x200 2 0 4294967295 OVRRD_SELECT 0 1 OVRRD_VALUE 2 3 ixGC_CAC_OVRD_CB 2 0x201 2 0 4294967295 OVRRD_SELECT 0 9 OVRRD_VALUE 10 19 ixGC_CAC_OVRD_CP 2 0x203 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_DB 2 0x204 2 0 4294967295 OVRRD_SELECT 0 9 OVRRD_VALUE 10 19 ixGC_CAC_OVRD_GDS 2 0x206 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_LDS 2 0x207 2 0 4294967295 OVRRD_SELECT 0 8 OVRRD_VALUE 9 17 ixGC_CAC_OVRD_PA 2 0x208 2 0 4294967295 OVRRD_SELECT 0 7 OVRRD_VALUE 8 15 ixGC_CAC_OVRD_PC 2 0x209 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SC 2 0x20a 2 0 4294967295 OVRRD_SELECT 0 7 OVRRD_VALUE 8 15 ixGC_CAC_OVRD_SPI 2 0x20b 2 0 4294967295 OVRRD_SELECT 0 5 OVRRD_VALUE 6 11 ixGC_CAC_OVRD_CU 2 0x20c 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SQ 2 0x20d 2 0 4294967295 OVRRD_SELECT 0 7 OVRRD_VALUE 8 15 ixGC_CAC_OVRD_SX 2 0x20e 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SXRB 2 0x20f 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_TA 2 0x210 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_TCP 2 0x211 2 0 4294967295 OVRRD_SELECT 0 7 OVRRD_VALUE 8 15 ixGC_CAC_OVRD_TD 2 0x212 2 0 4294967295 OVRRD_SELECT 0 10 OVRRD_VALUE 11 21 ixGC_CAC_OVRD_RMI 2 0x213 2 0 4294967295 OVRRD_SELECT 0 3 OVRRD_VALUE 4 7 ixGC_CAC_OVRD_EA 2 0x214 2 0 4294967295 OVRRD_SELECT 0 5 OVRRD_VALUE 6 11 ixGC_CAC_OVRD_UTCL2_ATCL2 2 0x215 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_UTCL2_ROUTER 2 0x216 2 0 4294967295 OVRRD_SELECT 0 9 OVRRD_VALUE 10 19 ixGC_CAC_OVRD_UTCL2_VML2 2 0x217 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_UTCL2_WALKER 2 0x218 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_SP 2 0x219 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_UTCL1 2 0x21a 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_CHC 2 0x21b 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_GE 2 0x21c 2 0 4294967295 OVRRD_SELECT 0 15 OVRRD_VALUE 16 31 ixGC_CAC_OVRD_PMM 2 0x21d 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_GL2C 2 0x21e 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_GUS 2 0x21f 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_PH 2 0x220 2 0 4294967295 OVRRD_SELECT 0 7 OVRRD_VALUE 8 15 ixGC_CAC_OVRD_SDMA 2 0x221 2 0 4294967295 OVRRD_SELECT 0 11 OVRRD_VALUE 12 23 ixGC_CAC_OVRD_GL1C 2 0x222 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_SQC 2 0x223 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_RLC 2 0x224 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_GE_HI 2 0x225 2 0 4294967295 OVRRD_SELECT 0 15 OVRRD_VALUE 16 31 ixRELEASE_TO_STALL_LUT_1_8 2 0x230 8 0 4294967295 FIRST_PATTERN_1 0 2 FIRST_PATTERN_2 4 6 FIRST_PATTERN_3 8 10 FIRST_PATTERN_4 12 14 FIRST_PATTERN_5 16 18 FIRST_PATTERN_6 20 22 FIRST_PATTERN_7 24 26 FIRST_PATTERN_8 28 30 ixRELEASE_TO_STALL_LUT_9_16 2 0x231 8 0 4294967295 FIRST_PATTERN_9 0 2 FIRST_PATTERN_10 4 6 FIRST_PATTERN_11 8 10 FIRST_PATTERN_12 12 14 FIRST_PATTERN_13 16 18 FIRST_PATTERN_14 20 22 FIRST_PATTERN_15 24 26 FIRST_PATTERN_16 28 30 ixRELEASE_TO_STALL_LUT_17_20 2 0x232 4 0 4294967295 FIRST_PATTERN_17 0 2 FIRST_PATTERN_18 4 6 FIRST_PATTERN_19 8 10 FIRST_PATTERN_20 12 14 ixSTALL_TO_RELEASE_LUT_1_4 2 0x233 4 0 4294967295 FIRST_PATTERN_1 0 4 FIRST_PATTERN_2 8 12 FIRST_PATTERN_3 16 20 FIRST_PATTERN_4 24 28 ixSTALL_TO_RELEASE_LUT_5_7 2 0x234 3 0 4294967295 FIRST_PATTERN_5 0 4 FIRST_PATTERN_6 8 12 FIRST_PATTERN_7 16 20 ixSTALL_TO_PWRBRK_LUT_1_4 2 0x235 4 0 4294967295 FIRST_PATTERN_1 0 2 FIRST_PATTERN_2 8 10 FIRST_PATTERN_3 16 18 FIRST_PATTERN_4 24 26 ixSTALL_TO_PWRBRK_LUT_5_7 2 0x236 3 0 4294967295 FIRST_PATTERN_5 0 2 FIRST_PATTERN_6 8 10 FIRST_PATTERN_7 16 18 ixPWRBRK_STALL_TO_RELEASE_LUT_1_4 2 0x237 4 0 4294967295 FIRST_PATTERN_1 0 4 FIRST_PATTERN_2 8 12 FIRST_PATTERN_3 16 20 FIRST_PATTERN_4 24 28 ixPWRBRK_STALL_TO_RELEASE_LUT_5_7 2 0x238 3 0 4294967295 FIRST_PATTERN_5 0 4 FIRST_PATTERN_6 8 12 FIRST_PATTERN_7 16 20 ixPWRBRK_RELEASE_TO_STALL_LUT_1_8 2 0x239 8 0 4294967295 FIRST_PATTERN_1 0 2 FIRST_PATTERN_2 4 6 FIRST_PATTERN_3 8 10 FIRST_PATTERN_4 12 14 FIRST_PATTERN_5 16 18 FIRST_PATTERN_6 20 22 FIRST_PATTERN_7 24 26 FIRST_PATTERN_8 28 30 ixPWRBRK_RELEASE_TO_STALL_LUT_9_16 2 0x23a 8 0 4294967295 FIRST_PATTERN_9 0 2 FIRST_PATTERN_10 4 6 FIRST_PATTERN_11 8 10 FIRST_PATTERN_12 12 14 FIRST_PATTERN_13 16 18 FIRST_PATTERN_14 20 22 FIRST_PATTERN_15 24 26 FIRST_PATTERN_16 28 30 ixPWRBRK_RELEASE_TO_STALL_LUT_17_20 2 0x23b 4 0 4294967295 FIRST_PATTERN_17 0 2 FIRST_PATTERN_18 4 6 FIRST_PATTERN_19 8 10 FIRST_PATTERN_20 12 14 ixFIXED_PATTERN_PERF_COUNTER_1 2 0x23c 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_2 2 0x23d 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_3 2 0x23e 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_4 2 0x23f 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_5 2 0x240 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_6 2 0x241 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_7 2 0x242 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_8 2 0x243 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_9 2 0x244 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_10 2 0x245 1 0 4294967295 PERF_COUNTER 0 16 ixHW_LUT_UPDATE_STATUS 2 0x246 15 0 4294967295 UPDATE_TABLE_1_DONE 0 0 UPDATE_TABLE_1_ERROR 1 1 UPDATE_TABLE_1_ERROR_STEP 2 4 UPDATE_TABLE_2_DONE 5 5 UPDATE_TABLE_2_ERROR 6 6 UPDATE_TABLE_2_ERROR_STEP 7 9 UPDATE_TABLE_3_DONE 10 10 UPDATE_TABLE_3_ERROR 11 11 UPDATE_TABLE_3_ERROR_STEP 12 16 UPDATE_TABLE_4_DONE 17 17 UPDATE_TABLE_4_ERROR 18 18 UPDATE_TABLE_4_ERROR_STEP 19 21 UPDATE_TABLE_5_DONE 22 22 UPDATE_TABLE_5_ERROR 23 23 UPDATE_TABLE_5_ERROR_STEP 24 28 ixSE_CAC_ID 2 0x0 3 0 4294967295 CAC_BLOCK_ID 0 5 CAC_SIGNAL_ID 6 13 UNUSED_0 14 31 ixSE_CAC_CNTL 2 0x1 3 0 4294967295 CAC_FORCE_DISABLE 0 0 CAC_THRESHOLD 1 16 UNUSED_0 17 31 ixSE_CAC_OVR_SEL 2 0x2 1 0 4294967295 CAC_OVR_SEL 0 31 ixSE_CAC_OVR_VAL 2 0x3 1 0 4294967295 CAC_OVR_VAL 0 31 ixGLB_CPG_SAMPLEDELAY 2 0x0 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CPC_SAMPLEDELAY 2 0x1 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CPF_SAMPLEDELAY 2 0x2 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GDS_SAMPLEDELAY 2 0x3 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GCR_SAMPLEDELAY 2 0x4 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_PH_SAMPLEDELAY 2 0x5 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE1_SAMPLEDELAY 2 0x6 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE2DIST_SAMPLEDELAY 2 0x7 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GUS_SAMPLEDELAY 2 0x8 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHA_SAMPLEDELAY 2 0x9 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHCG_SAMPLEDELAY 2 0xa 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_ATCL2_SAMPLEDELAY 2 0xb 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_VML2_SAMPLEDELAY 2 0xc 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_SDMA0_SAMPLEDELAY 2 0xd 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_SDMA1_SAMPLEDELAY 2 0xe 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_SDMA2_SAMPLEDELAY 2 0xf 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_SDMA3_SAMPLEDELAY 2 0x10 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2A0_SAMPLEDELAY 2 0x11 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2A1_SAMPLEDELAY 2 0x12 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2A2_SAMPLEDELAY 2 0x13 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2A3_SAMPLEDELAY 2 0x14 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C0_SAMPLEDELAY 2 0x15 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C1_SAMPLEDELAY 2 0x16 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C2_SAMPLEDELAY 2 0x17 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C3_SAMPLEDELAY 2 0x18 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C4_SAMPLEDELAY 2 0x19 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C5_SAMPLEDELAY 2 0x1a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C6_SAMPLEDELAY 2 0x1b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C7_SAMPLEDELAY 2 0x1c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C8_SAMPLEDELAY 2 0x1d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C9_SAMPLEDELAY 2 0x1e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C10_SAMPLEDELAY 2 0x1f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C11_SAMPLEDELAY 2 0x20 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C12_SAMPLEDELAY 2 0x21 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C13_SAMPLEDELAY 2 0x22 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C14_SAMPLEDELAY 2 0x23 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GL2C15_SAMPLEDELAY 2 0x24 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA0_SAMPLEDELAY 2 0x25 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA1_SAMPLEDELAY 2 0x26 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA2_SAMPLEDELAY 2 0x27 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA3_SAMPLEDELAY 2 0x28 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA4_SAMPLEDELAY 2 0x29 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA5_SAMPLEDELAY 2 0x2a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA6_SAMPLEDELAY 2 0x2b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA7_SAMPLEDELAY 2 0x2c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA8_SAMPLEDELAY 2 0x2d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA9_SAMPLEDELAY 2 0x2e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA10_SAMPLEDELAY 2 0x2f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA11_SAMPLEDELAY 2 0x30 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA12_SAMPLEDELAY 2 0x31 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA13_SAMPLEDELAY 2 0x32 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA14_SAMPLEDELAY 2 0x33 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_EA15_SAMPLEDELAY 2 0x34 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHC0_SAMPLEDELAY 2 0x35 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHC1_SAMPLEDELAY 2 0x36 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHC2_SAMPLEDELAY 2 0x37 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_CHC3_SAMPLEDELAY 2 0x38 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE2SE0_SAMPLEDELAY 2 0x39 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE2SE1_SAMPLEDELAY 2 0x3a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE2SE2_SAMPLEDELAY 2 0x3b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixGLB_GE2SE3_SAMPLEDELAY 2 0x3c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SPI_SAMPLEDELAY 2 0x0 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SQG_SAMPLEDELAY 2 0x1 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_CBR_SAMPLEDELAY 2 0x2 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_DBR_SAMPLEDELAY 2 0x3 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_PA_SAMPLEDELAY 2 0x4 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0SX_SAMPLEDELAY 2 0x5 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1A_SAMPLEDELAY 2 0x6 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1CG_SAMPLEDELAY 2 0x7 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0CB0_SAMPLEDELAY 2 0x8 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0CB1_SAMPLEDELAY 2 0x9 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0DB0_SAMPLEDELAY 2 0xa 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0DB1_SAMPLEDELAY 2 0xb 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0SC0_SAMPLEDELAY 2 0xc 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0SC1_SAMPLEDELAY 2 0xd 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0RMI0_SAMPLEDELAY 2 0xe 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0RMI1_SAMPLEDELAY 2 0xf 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1C0_SAMPLEDELAY 2 0x10 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1C1_SAMPLEDELAY 2 0x11 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1C2_SAMPLEDELAY 2 0x12 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0GL1C3_SAMPLEDELAY 2 0x13 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TA0_SAMPLEDELAY 2 0x14 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TA1_SAMPLEDELAY 2 0x15 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TD0_SAMPLEDELAY 2 0x16 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TD1_SAMPLEDELAY 2 0x17 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TCP0_SAMPLEDELAY 2 0x18 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP00TCP1_SAMPLEDELAY 2 0x19 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TA0_SAMPLEDELAY 2 0x1a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TA1_SAMPLEDELAY 2 0x1b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TD0_SAMPLEDELAY 2 0x1c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TD1_SAMPLEDELAY 2 0x1d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TCP0_SAMPLEDELAY 2 0x1e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP01TCP1_SAMPLEDELAY 2 0x1f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TA0_SAMPLEDELAY 2 0x20 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TA1_SAMPLEDELAY 2 0x21 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TD0_SAMPLEDELAY 2 0x22 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TD1_SAMPLEDELAY 2 0x23 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TCP0_SAMPLEDELAY 2 0x24 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP02TCP1_SAMPLEDELAY 2 0x25 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TA0_SAMPLEDELAY 2 0x26 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TA1_SAMPLEDELAY 2 0x27 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TD0_SAMPLEDELAY 2 0x28 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TD1_SAMPLEDELAY 2 0x29 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TCP0_SAMPLEDELAY 2 0x2a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP03TCP1_SAMPLEDELAY 2 0x2b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TA0_SAMPLEDELAY 2 0x2c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TA1_SAMPLEDELAY 2 0x2d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TD0_SAMPLEDELAY 2 0x2e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TD1_SAMPLEDELAY 2 0x2f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TCP0_SAMPLEDELAY 2 0x30 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA0WGP04TCP1_SAMPLEDELAY 2 0x31 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1SX_SAMPLEDELAY 2 0x32 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1A_SAMPLEDELAY 2 0x33 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1CG_SAMPLEDELAY 2 0x34 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1CB0_SAMPLEDELAY 2 0x35 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1CB1_SAMPLEDELAY 2 0x36 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1DB0_SAMPLEDELAY 2 0x37 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1DB1_SAMPLEDELAY 2 0x38 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1SC0_SAMPLEDELAY 2 0x39 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1SC1_SAMPLEDELAY 2 0x3a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1RMI0_SAMPLEDELAY 2 0x3b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1RMI1_SAMPLEDELAY 2 0x3c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1C0_SAMPLEDELAY 2 0x3d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1C1_SAMPLEDELAY 2 0x3e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1C2_SAMPLEDELAY 2 0x3f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1GL1C3_SAMPLEDELAY 2 0x40 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TA0_SAMPLEDELAY 2 0x41 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TA1_SAMPLEDELAY 2 0x42 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TD0_SAMPLEDELAY 2 0x43 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TD1_SAMPLEDELAY 2 0x44 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TCP0_SAMPLEDELAY 2 0x45 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP00TCP1_SAMPLEDELAY 2 0x46 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TA0_SAMPLEDELAY 2 0x47 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TA1_SAMPLEDELAY 2 0x48 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TD0_SAMPLEDELAY 2 0x49 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TD1_SAMPLEDELAY 2 0x4a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TCP0_SAMPLEDELAY 2 0x4b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP01TCP1_SAMPLEDELAY 2 0x4c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TA0_SAMPLEDELAY 2 0x4d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TA1_SAMPLEDELAY 2 0x4e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TD0_SAMPLEDELAY 2 0x4f 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TD1_SAMPLEDELAY 2 0x50 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TCP0_SAMPLEDELAY 2 0x51 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP02TCP1_SAMPLEDELAY 2 0x52 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TA0_SAMPLEDELAY 2 0x53 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TA1_SAMPLEDELAY 2 0x54 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TD0_SAMPLEDELAY 2 0x55 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TD1_SAMPLEDELAY 2 0x56 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TCP0_SAMPLEDELAY 2 0x57 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP03TCP1_SAMPLEDELAY 2 0x58 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TA0_SAMPLEDELAY 2 0x59 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TA1_SAMPLEDELAY 2 0x5a 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TD0_SAMPLEDELAY 2 0x5b 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TD1_SAMPLEDELAY 2 0x5c 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TCP0_SAMPLEDELAY 2 0x5d 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixSE_SA1WGP04TCP1_SAMPLEDELAY 2 0x5e 2 0 4294967295 SAMPLEDELAY 0 5 RESERVED 6 31 ixRTAVFS_REG0 2 0x0 2 0 4294967295 RTAVFSCPO0_STARTCNT 0 15 RTAVFSCPO0_STOPCNT 16 31 ixRTAVFS_REG1 2 0x1 2 0 4294967295 RTAVFSCPO0_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG2 2 0x2 2 0 4294967295 RTAVFSCPO1_STARTCNT 0 15 RTAVFSCPO1_STOPCNT 16 31 ixRTAVFS_REG3 2 0x3 2 0 4294967295 RTAVFSCPO1_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG4 2 0x4 2 0 4294967295 RTAVFSCPO2_STARTCNT 0 15 RTAVFSCPO2_STOPCNT 16 31 ixRTAVFS_REG5 2 0x5 2 0 4294967295 RTAVFSCPO2_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG6 2 0x6 2 0 4294967295 RTAVFSCPO3_STARTCNT 0 15 RTAVFSCPO3_STOPCNT 16 31 ixRTAVFS_REG7 2 0x7 2 0 4294967295 RTAVFSCPO3_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG8 2 0x8 2 0 4294967295 RTAVFSCPO4_STARTCNT 0 15 RTAVFSCPO4_STOPCNT 16 31 ixRTAVFS_REG9 2 0x9 2 0 4294967295 RTAVFSCPO4_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG10 2 0xa 2 0 4294967295 RTAVFSCPO5_STARTCNT 0 15 RTAVFSCPO5_STOPCNT 16 31 ixRTAVFS_REG11 2 0xb 2 0 4294967295 RTAVFSCPO5_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG12 2 0xc 2 0 4294967295 RTAVFSCPO6_STARTCNT 0 15 RTAVFSCPO6_STOPCNT 16 31 ixRTAVFS_REG13 2 0xd 2 0 4294967295 RTAVFSCPO6_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG14 2 0xe 2 0 4294967295 RTAVFSCPO7_STARTCNT 0 15 RTAVFSCPO7_STOPCNT 16 31 ixRTAVFS_REG15 2 0xf 2 0 4294967295 RTAVFSCPO7_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG16 2 0x10 2 0 4294967295 RTAVFSCPO8_STARTCNT 0 15 RTAVFSCPO8_STOPCNT 16 31 ixRTAVFS_REG17 2 0x11 2 0 4294967295 RTAVFSCPO8_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG18 2 0x12 2 0 4294967295 RTAVFSCPO9_STARTCNT 0 15 RTAVFSCPO9_STOPCNT 16 31 ixRTAVFS_REG19 2 0x13 2 0 4294967295 RTAVFSCPO9_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG20 2 0x14 2 0 4294967295 RTAVFSCPO10_STARTCNT 0 15 RTAVFSCPO10_STOPCNT 16 31 ixRTAVFS_REG21 2 0x15 2 0 4294967295 RTAVFSCPO10_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG22 2 0x16 2 0 4294967295 RTAVFSCPO11_STARTCNT 0 15 RTAVFSCPO11_STOPCNT 16 31 ixRTAVFS_REG23 2 0x17 2 0 4294967295 RTAVFSCPO11_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG24 2 0x18 2 0 4294967295 RTAVFSCPO12_STARTCNT 0 15 RTAVFSCPO12_STOPCNT 16 31 ixRTAVFS_REG25 2 0x19 2 0 4294967295 RTAVFSCPO12_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG26 2 0x1a 2 0 4294967295 RTAVFSCPO13_STARTCNT 0 15 RTAVFSCPO13_STOPCNT 16 31 ixRTAVFS_REG27 2 0x1b 2 0 4294967295 RTAVFSCPO13_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG28 2 0x1c 2 0 4294967295 RTAVFSCPO14_STARTCNT 0 15 RTAVFSCPO14_STOPCNT 16 31 ixRTAVFS_REG29 2 0x1d 2 0 4294967295 RTAVFSCPO14_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG30 2 0x1e 2 0 4294967295 RTAVFSCPO15_STARTCNT 0 15 RTAVFSCPO15_STOPCNT 16 31 ixRTAVFS_REG31 2 0x1f 2 0 4294967295 RTAVFSCPO15_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG32 2 0x20 2 0 4294967295 RTAVFSCPO16_STARTCNT 0 15 RTAVFSCPO16_STOPCNT 16 31 ixRTAVFS_REG33 2 0x21 2 0 4294967295 RTAVFSCPO16_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG34 2 0x22 2 0 4294967295 RTAVFSCPO17_STARTCNT 0 15 RTAVFSCPO17_STOPCNT 16 31 ixRTAVFS_REG35 2 0x23 2 0 4294967295 RTAVFSCPO17_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG36 2 0x24 2 0 4294967295 RTAVFSCPO18_STARTCNT 0 15 RTAVFSCPO18_STOPCNT 16 31 ixRTAVFS_REG37 2 0x25 2 0 4294967295 RTAVFSCPO18_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG38 2 0x26 2 0 4294967295 RTAVFSCPO19_STARTCNT 0 15 RTAVFSCPO19_STOPCNT 16 31 ixRTAVFS_REG39 2 0x27 2 0 4294967295 RTAVFSCPO19_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG40 2 0x28 2 0 4294967295 RTAVFSCPO20_STARTCNT 0 15 RTAVFSCPO20_STOPCNT 16 31 ixRTAVFS_REG41 2 0x29 2 0 4294967295 RTAVFSCPO20_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG42 2 0x2a 2 0 4294967295 RTAVFSCPO21_STARTCNT 0 15 RTAVFSCPO21_STOPCNT 16 31 ixRTAVFS_REG43 2 0x2b 2 0 4294967295 RTAVFSCPO21_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG44 2 0x2c 2 0 4294967295 RTAVFSCPO22_STARTCNT 0 15 RTAVFSCPO22_STOPCNT 16 31 ixRTAVFS_REG45 2 0x2d 2 0 4294967295 RTAVFSCPO22_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG46 2 0x2e 2 0 4294967295 RTAVFSCPO23_STARTCNT 0 15 RTAVFSCPO23_STOPCNT 16 31 ixRTAVFS_REG47 2 0x2f 2 0 4294967295 RTAVFSCPO23_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG48 2 0x30 2 0 4294967295 RTAVFSCPO24_STARTCNT 0 15 RTAVFSCPO24_STOPCNT 16 31 ixRTAVFS_REG49 2 0x31 2 0 4294967295 RTAVFSCPO24_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG50 2 0x32 2 0 4294967295 RTAVFSCPO25_STARTCNT 0 15 RTAVFSCPO25_STOPCNT 16 31 ixRTAVFS_REG51 2 0x33 2 0 4294967295 RTAVFSCPO25_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG52 2 0x34 2 0 4294967295 RTAVFSCPO26_STARTCNT 0 15 RTAVFSCPO26_STOPCNT 16 31 ixRTAVFS_REG53 2 0x35 2 0 4294967295 RTAVFSCPO26_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG54 2 0x36 2 0 4294967295 RTAVFSCPO27_STARTCNT 0 15 RTAVFSCPO27_STOPCNT 16 31 ixRTAVFS_REG55 2 0x37 2 0 4294967295 RTAVFSCPO27_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG56 2 0x38 2 0 4294967295 RTAVFSCPO28_STARTCNT 0 15 RTAVFSCPO28_STOPCNT 16 31 ixRTAVFS_REG57 2 0x39 2 0 4294967295 RTAVFSCPO28_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG58 2 0x3a 2 0 4294967295 RTAVFSCPO29_STARTCNT 0 15 RTAVFSCPO29_STOPCNT 16 31 ixRTAVFS_REG59 2 0x3b 2 0 4294967295 RTAVFSCPO29_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG60 2 0x3c 2 0 4294967295 RTAVFSCPO30_STARTCNT 0 15 RTAVFSCPO30_STOPCNT 16 31 ixRTAVFS_REG61 2 0x3d 2 0 4294967295 RTAVFSCPO30_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG62 2 0x3e 2 0 4294967295 RTAVFSCPO31_STARTCNT 0 15 RTAVFSCPO31_STOPCNT 16 31 ixRTAVFS_REG63 2 0x3f 2 0 4294967295 RTAVFSCPO31_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG64 2 0x40 2 0 4294967295 RTAVFSCPO32_STARTCNT 0 15 RTAVFSCPO32_STOPCNT 16 31 ixRTAVFS_REG65 2 0x41 2 0 4294967295 RTAVFSCPO32_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG66 2 0x42 2 0 4294967295 RTAVFSCPO33_STARTCNT 0 15 RTAVFSCPO33_STOPCNT 16 31 ixRTAVFS_REG67 2 0x43 2 0 4294967295 RTAVFSCPO33_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG68 2 0x44 2 0 4294967295 RTAVFSCPO34_STARTCNT 0 15 RTAVFSCPO34_STOPCNT 16 31 ixRTAVFS_REG69 2 0x45 2 0 4294967295 RTAVFSCPO34_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG70 2 0x46 2 0 4294967295 RTAVFSCPO35_STARTCNT 0 15 RTAVFSCPO35_STOPCNT 16 31 ixRTAVFS_REG71 2 0x47 2 0 4294967295 RTAVFSCPO35_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG72 2 0x48 2 0 4294967295 RTAVFSCPO36_STARTCNT 0 15 RTAVFSCPO36_STOPCNT 16 31 ixRTAVFS_REG73 2 0x49 2 0 4294967295 RTAVFSCPO36_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG74 2 0x4a 2 0 4294967295 RTAVFSCPO37_STARTCNT 0 15 RTAVFSCPO37_STOPCNT 16 31 ixRTAVFS_REG75 2 0x4b 2 0 4294967295 RTAVFSCPO37_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG76 2 0x4c 2 0 4294967295 RTAVFSCPO38_STARTCNT 0 15 RTAVFSCPO38_STOPCNT 16 31 ixRTAVFS_REG77 2 0x4d 2 0 4294967295 RTAVFSCPO38_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG78 2 0x4e 2 0 4294967295 RTAVFSCPO39_STARTCNT 0 15 RTAVFSCPO39_STOPCNT 16 31 ixRTAVFS_REG79 2 0x4f 2 0 4294967295 RTAVFSCPO39_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG80 2 0x50 2 0 4294967295 RTAVFSCPO40_STARTCNT 0 15 RTAVFSCPO40_STOPCNT 16 31 ixRTAVFS_REG81 2 0x51 2 0 4294967295 RTAVFSCPO40_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG82 2 0x52 2 0 4294967295 RTAVFSCPO41_STARTCNT 0 15 RTAVFSCPO41_STOPCNT 16 31 ixRTAVFS_REG83 2 0x53 2 0 4294967295 RTAVFSCPO41_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG84 2 0x54 2 0 4294967295 RTAVFSCPO42_STARTCNT 0 15 RTAVFSCPO42_STOPCNT 16 31 ixRTAVFS_REG85 2 0x55 2 0 4294967295 RTAVFSCPO42_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG86 2 0x56 2 0 4294967295 RTAVFSCPO43_STARTCNT 0 15 RTAVFSCPO43_STOPCNT 16 31 ixRTAVFS_REG87 2 0x57 2 0 4294967295 RTAVFSCPO43_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG88 2 0x58 2 0 4294967295 RTAVFSCPO44_STARTCNT 0 15 RTAVFSCPO44_STOPCNT 16 31 ixRTAVFS_REG89 2 0x59 2 0 4294967295 RTAVFSCPO44_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG90 2 0x5a 2 0 4294967295 RTAVFSCPO45_STARTCNT 0 15 RTAVFSCPO45_STOPCNT 16 31 ixRTAVFS_REG91 2 0x5b 2 0 4294967295 RTAVFSCPO45_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG92 2 0x5c 2 0 4294967295 RTAVFSCPO46_STARTCNT 0 15 RTAVFSCPO46_STOPCNT 16 31 ixRTAVFS_REG93 2 0x5d 2 0 4294967295 RTAVFSCPO46_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG94 2 0x5e 2 0 4294967295 RTAVFSCPO47_STARTCNT 0 15 RTAVFSCPO47_STOPCNT 16 31 ixRTAVFS_REG95 2 0x5f 2 0 4294967295 RTAVFSCPO47_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG96 2 0x60 2 0 4294967295 RTAVFSCPO48_STARTCNT 0 15 RTAVFSCPO48_STOPCNT 16 31 ixRTAVFS_REG97 2 0x61 2 0 4294967295 RTAVFSCPO48_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG98 2 0x62 2 0 4294967295 RTAVFSCPO49_STARTCNT 0 15 RTAVFSCPO49_STOPCNT 16 31 ixRTAVFS_REG99 2 0x63 2 0 4294967295 RTAVFSCPO49_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG100 2 0x64 2 0 4294967295 RTAVFSCPO50_STARTCNT 0 15 RTAVFSCPO50_STOPCNT 16 31 ixRTAVFS_REG101 2 0x65 2 0 4294967295 RTAVFSCPO50_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG102 2 0x66 2 0 4294967295 RTAVFSCPO51_STARTCNT 0 15 RTAVFSCPO51_STOPCNT 16 31 ixRTAVFS_REG103 2 0x67 2 0 4294967295 RTAVFSCPO51_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG104 2 0x68 2 0 4294967295 RTAVFSCPO52_STARTCNT 0 15 RTAVFSCPO52_STOPCNT 16 31 ixRTAVFS_REG105 2 0x69 2 0 4294967295 RTAVFSCPO52_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG106 2 0x6a 2 0 4294967295 RTAVFSCPO53_STARTCNT 0 15 RTAVFSCPO53_STOPCNT 16 31 ixRTAVFS_REG107 2 0x6b 2 0 4294967295 RTAVFSCPO53_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG108 2 0x6c 2 0 4294967295 RTAVFSCPO54_STARTCNT 0 15 RTAVFSCPO54_STOPCNT 16 31 ixRTAVFS_REG109 2 0x6d 2 0 4294967295 RTAVFSCPO54_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG110 2 0x6e 2 0 4294967295 RTAVFSCPO55_STARTCNT 0 15 RTAVFSCPO55_STOPCNT 16 31 ixRTAVFS_REG111 2 0x6f 2 0 4294967295 RTAVFSCPO55_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG112 2 0x70 2 0 4294967295 RTAVFSCPO56_STARTCNT 0 15 RTAVFSCPO56_STOPCNT 16 31 ixRTAVFS_REG113 2 0x71 2 0 4294967295 RTAVFSCPO56_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG114 2 0x72 2 0 4294967295 RTAVFSCPO57_STARTCNT 0 15 RTAVFSCPO57_STOPCNT 16 31 ixRTAVFS_REG115 2 0x73 2 0 4294967295 RTAVFSCPO57_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG116 2 0x74 2 0 4294967295 RTAVFSCPO58_STARTCNT 0 15 RTAVFSCPO58_STOPCNT 16 31 ixRTAVFS_REG117 2 0x75 2 0 4294967295 RTAVFSCPO58_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG118 2 0x76 2 0 4294967295 RTAVFSCPO59_STARTCNT 0 15 RTAVFSCPO59_STOPCNT 16 31 ixRTAVFS_REG119 2 0x77 2 0 4294967295 RTAVFSCPO59_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG120 2 0x78 2 0 4294967295 RTAVFSCPO60_STARTCNT 0 15 RTAVFSCPO60_STOPCNT 16 31 ixRTAVFS_REG121 2 0x79 2 0 4294967295 RTAVFSCPO60_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG122 2 0x7a 2 0 4294967295 RTAVFSCPO61_STARTCNT 0 15 RTAVFSCPO61_STOPCNT 16 31 ixRTAVFS_REG123 2 0x7b 2 0 4294967295 RTAVFSCPO61_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG124 2 0x7c 2 0 4294967295 RTAVFSCPO62_STARTCNT 0 15 RTAVFSCPO62_STOPCNT 16 31 ixRTAVFS_REG125 2 0x7d 2 0 4294967295 RTAVFSCPO62_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG126 2 0x7e 2 0 4294967295 RTAVFSCPO63_STARTCNT 0 15 RTAVFSCPO63_STOPCNT 16 31 ixRTAVFS_REG127 2 0x7f 2 0 4294967295 RTAVFSCPO63_RIPPLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG128 2 0x80 1 0 4294967295 RTAVFSCPOEN0 0 31 ixRTAVFS_REG129 2 0x81 1 0 4294967295 RTAVFSCPOEN1 0 31 ixRTAVFS_REG130 2 0x82 6 0 4294967295 RTAVFSVRBLEEDCNTRL 0 0 RTAVFSVRENABLE 1 1 RTAVFSVOLTCODEOVERRIDE 2 11 RTAVFSVOLTCODEOVERRIDESEL 12 12 RTAVFSLOWPWREN 13 13 RESERVED 14 31 ixRTAVFS_REG131 2 0x83 3 0 4294967295 RTAVFSTARGETFREQCNTOVERRIDE 0 15 RTAVFSTARGETFREQCNTOVERRIDESEL 16 16 RESERVED 17 31 ixRTAVFS_REG132 2 0x84 3 0 4294967295 RTAVFSCURRENTFREQCNTOVERRIDE 0 15 RTAVFSCURRENTFREQCNTOVERRIDESEL 16 16 RESERVED 17 31 ixRTAVFS_REG133 2 0x85 1 0 4294967295 RESERVED 22 31 ixRTAVFS_REG134 2 0x86 8 0 4294967295 RTAVFSKP 0 3 RTAVFSKI 4 7 RTAVFSPIENABLEANTIWINDUP 8 8 RTAVFSPISHIFT 9 12 RTAVFSPIERREN 13 13 RTAVFSPISHIFTOUT 14 17 RTAVFSUSELUTKPKI 18 18 RESERVED 19 31 ixRTAVFS_REG135 2 0x87 5 0 4294967295 RTAVFSVOLTCODEPIMIN 0 9 RTAVFSVOLTCODEPIMAX 10 19 RTAVFSPIERRMASK 20 26 RTAVFSFORCEDISABLEPI 27 27 RESERVED 28 31 ixRTAVFS_REG136 2 0x88 2 0 4294967295 RTAVFSPILOOPNITERATIONS 0 15 RTAVFSPIERRTHRESHOLD 16 31 ixRTAVFS_REG137 2 0x89 4 0 4294967295 RTAVFSVOLTCODEFROMPI 0 9 RTAVFSVOLTCODEFROMBINARYSEARCH 10 19 RTAVFSVDDREGON 20 20 RESERVED 21 31 ixRTAVFS_REG138 2 0x8a 7 0 4294967295 RTAVFSAVFSENABLE 0 0 RTAVFSCPOTURNONDELAY 1 4 RTAVFSSELECTMINMAX 5 5 RTAVFSIGNORERLCREQ 6 6 RTAVFSRIPPLECOUNTEROUTSEL 7 11 RTAVFSRUNLOOP 12 12 RESERVED 13 31 ixRTAVFS_REG139 2 0x8b 2 0 4294967295 RTAVFSAVFSSCALEDCPOCOUNT 0 15 RTAVFSAVFSFINALMINCPOCOUNT 16 31 ixRTAVFS_REG140 2 0x8c 8 0 4294967295 RTAVFSPSMRSTAVGVDD 0 0 RTAVFSPSMMEASMAXVDD 1 1 RTAVFSPSMCLKDIVVDD 2 3 RTAVFSPSMAVGDIVVDD 4 9 RTAVFSPSMOSCENVDD 10 10 RTAVFSPSMAVGENVDD 11 11 RTAVFSPSMRSTMINMAXVDD 12 12 RESERVED 13 31 ixRTAVFS_REG141 2 0x8d 3 0 4294967295 RTAVFSMINMAXPSMVDD 0 13 RTAVFSAVGPSMVDD 14 27 RESERVED 28 31 ixRTAVFS_REG142 2 0x8e 8 0 4294967295 RTAVFSPSMRSTAVGVREG 0 0 RTAVFSPSMMEASMAXVREG 1 1 RTAVFSPSMCLKDIVVREG 2 3 RTAVFSPSMAVGDIVVREG 4 9 RTAVFSPSMOSCENVREG 10 10 RTAVFSPSMAVGENVREG 11 11 RTAVFSPSMRSTMINMAXVREG 12 12 RESERVED 13 31 ixRTAVFS_REG143 2 0x8f 3 0 4294967295 RTAVFSMINMAXPSMVREG 0 13 RTAVFSAVGPSMVREG 14 27 RESERVED 28 31 ixRTAVFS_REG144 2 0x90 11 0 4294967295 RTAVFSTROSAMPLESIZE 0 11 RTAVFSTROSAMPLEDLY 12 13 RTAVFSTROCONTMODEEN 14 14 RTAVFSTROPWRSAVEEN 15 15 RTAVFSTROTMPAVEEN 16 16 RTAVFSTROTMPAVEDIV 17 22 RTAVFSTROCALIBDIS 23 23 RTAVFSTROOUTVALSEL 24 26 RTAVFSTROCMGAIN 27 28 RTAVFSTROCLKDIVSEL 29 30 RTAVFSTROTRODIS 31 31 ixRTAVFS_REG145 2 0x91 4 0 4294967295 RTAVFSTROTEMPDATA 0 15 RTAVFSTROSSTATE 16 19 RTAVFSTROCALIBDONE 20 20 RTAVFSTRORESERVED 21 31 ixRTAVFS_REG146 2 0x92 2 0 4294967295 RTAVFSTROTMP_M 0 15 RTAVFSTROTMP_C 16 31 ixRTAVFS_REG147 2 0x93 5 0 4294967295 RTAVFSTROTMP_OFFSET 0 4 RTAVFSTROTMPSAMPSIZE 5 16 RTAVFSTROTMPREADSKIPSCALE 17 17 RTAVFSTROTMPSKIPSCALEFIX 18 18 RESERVED 19 31 ixRTAVFS_REG148 2 0x94 4 0 4294967295 RTAVFSTROTMPOUT 0 11 RTAVFSTROTMPOUTVAL 12 12 RTAVFSTROCURTMP 13 23 RESERVED 24 31 ixRTAVFS_REG149 2 0x95 2 0 4294967295 RTAVFSFSMSTARTUPCNT 0 15 RESERVED 16 31 ixRTAVFS_REG150 2 0x96 2 0 4294967295 RTAVFSFSMIDLECNT 0 15 RESERVED 16 31 ixRTAVFS_REG151 2 0x97 2 0 4294967295 RTAVFSFSMRESETCPORIPPLECOUNTERSCNT 0 15 RESERVED 16 31 ixRTAVFS_REG152 2 0x98 2 0 4294967295 RTAVFSFSMSTARTCPOSCNT 0 15 RESERVED 16 31 ixRTAVFS_REG153 2 0x99 2 0 4294967295 RTAVFSFSMSTARTRIPPLECOUNTERSCNT 0 15 RESERVED 16 31 ixRTAVFS_REG154 2 0x9a 2 0 4294967295 RTAVFSFSMRIPPLECOUNTERSDONECNT 0 15 RESERVED 16 31 ixRTAVFS_REG155 2 0x9b 2 0 4294967295 RTAVFSFSMCPOFINALRESULTREADYCNT 0 15 RESERVED 16 31 ixRTAVFS_REG156 2 0x9c 2 0 4294967295 RTAVFSFSMVOLTCODEREADYCNT 0 15 RESERVED 16 31 ixRTAVFS_REG157 2 0x9d 2 0 4294967295 RTAVFSFSMTARGETVOLTAGEREADYCNT 0 15 RESERVED 16 31 ixRTAVFS_REG158 2 0x9e 2 0 4294967295 RTAVFSFSMSTOPCPOSCNT 0 15 RESERVED 16 31 ixRTAVFS_REG159 2 0x9f 2 0 4294967295 RTAVFSFSMWAITFORACKCNT 0 15 RESERVED 16 31 ixRTAVFS_REG160 2 0xa0 10 0 4294967295 RTAVFSCPOAVGDIV0 0 1 RTAVFSCPOAVGDIV1 2 3 RTAVFSCPOAVGDIV2 4 5 RTAVFSCPOAVGDIV3 6 7 RTAVFSCPOAVGDIV4 8 9 RTAVFSCPOAVGDIV5 10 11 RTAVFSCPOAVGDIV6 12 13 RTAVFSCPOAVGDIV7 14 15 RTAVFSCPOAVGDIVFINAL 16 17 RESERVED 18 31 ixRTAVFS_REG161 2 0xa1 8 0 4294967295 RTAVFSKP0 0 3 RTAVFSKP1 4 7 RTAVFSKP2 8 11 RTAVFSKP3 12 15 RTAVFSKI0 16 19 RTAVFSKI1 20 23 RTAVFSKI2 24 27 RTAVFSKI3 28 31 ixRTAVFS_REG162 2 0xa2 5 0 4294967295 RTAVFSV1 0 9 RTAVFSV2 10 19 RTAVFSV3 20 29 RTAVFSUSEBINARYSEARCH 30 30 RTAVFSVOLTCODEHWCAL 31 31 ixRTAVFS_REG163 2 0xa3 2 0 4294967295 RTAVFSFSMSTATE 0 15 RESERVED 16 31 ixRTAVFS_REG164 2 0xa4 4 0 4294967295 RTAVFSGB_V1 0 7 RTAVFSGB_V1V2 8 15 RTAVFSGB_V2V3 16 23 RTAVFSGB_V3 24 31 ixRTAVFS_REG165 2 0xa5 1 0 4294967295 RTAVFSRIPPLECNTREAD 0 31 ixSA_WGP_BLK_ID 2 0x0 3 0 4294967295 BLK_ID 0 3 WGP_SIDE 4 4 SA_ID 5 5 ixSQ_DEBUG_STS_LOCAL 2 0x8 9 0 4294967295 BUSY 0 0 WAVE_LEVEL 4 9 SQ_BUSY 12 12 IS_BUSY 13 13 IB_BUSY 14 14 ARB_BUSY 15 15 EXP_BUSY 16 16 BRMSG_BUSY 17 17 VM_BUSY 18 18 ixSQ_WAVE_ACTIVE 2 0xa 1 0 4294967295 WAVE_SLOT 0 19 ixSQ_WAVE_VALID_AND_IDLE 2 0xb 1 0 4294967295 WAVE_SLOT 0 19 ixSQ_WAVE_MODE 2 0x101 8 0 4294967295 FP_ROUND 0 3 FP_DENORM 4 7 DX10_CLAMP 8 8 IEEE 9 9 LOD_CLAMPED 10 10 EXCP_EN 12 20 FP16_OVFL 23 23 DISABLE_PERF 27 27 ixSQ_WAVE_STATUS 2 0x102 20 0 4294967295 SCC 0 0 SPI_PRIO 1 2 USER_PRIO 3 4 PRIV 5 5 TRAP_EN 6 6 TTRACE_EN 7 7 EXPORT_RDY 8 8 EXECZ 9 9 VCCZ 10 10 IN_TG 11 11 IN_BARRIER 12 12 HALT 13 13 TRAP 14 14 TTRACE_SIMD_EN 15 15 VALID 16 16 ECC_ERR 17 17 SKIP_EXPORT 18 18 PERF_EN 19 19 FATAL_HALT 23 23 MUST_EXPORT 27 27 ixSQ_WAVE_TRAPSTS 2 0x103 10 0 4294967295 EXCP 0 8 SAVECTX 10 10 ILLEGAL_INST 11 11 EXCP_HI 12 14 BUFFER_OOB 15 15 EXCP_CYCLE 16 19 EXCP_GROUP_MASK 20 23 EXCP_WAVE64HI 24 24 UTC_ERROR 28 28 DP_RATE 29 31 ixSQ_WAVE_HW_ID_LEGACY 2 0x104 12 0 4294967295 WAVE_ID 0 3 SIMD_ID 4 5 PIPE_ID 6 7 CU_ID 8 11 SH_ID 12 12 SE_ID 13 14 WAVE_ID_MSB 15 15 TG_ID 16 19 VM_ID 20 23 QUEUE_ID 24 26 STATE_ID 27 29 ME_ID 30 31 ixSQ_WAVE_GPR_ALLOC 2 0x105 4 0 4294967295 VGPR_BASE 0 7 VGPR_SIZE 8 15 SGPR_BASE 16 23 SGPR_SIZE 24 27 ixSQ_WAVE_LDS_ALLOC 2 0x106 3 0 4294967295 LDS_BASE 0 8 LDS_SIZE 12 20 VGPR_SHARED_SIZE 24 27 ixSQ_WAVE_IB_STS 2 0x107 8 0 4294967295 VM_CNT 0 3 EXP_CNT 4 6 LGKM_CNT_BIT4 7 7 LGKM_CNT 8 11 VALU_CNT 12 14 VM_CNT_HI 22 23 LGKM_CNT_BIT5 24 24 VS_CNT 26 31 ixSQ_WAVE_PC_LO 2 0x108 1 0 4294967295 PC_LO 0 31 ixSQ_WAVE_PC_HI 2 0x109 1 0 4294967295 PC_HI 0 15 ixSQ_WAVE_INST_DW0 2 0x10a 1 0 4294967295 INST_DW0 0 31 ixSQ_WAVE_IB_DBG1 2 0x10d 2 0 4294967295 WAVE_IDLE 24 24 MISC_CNT 25 31 ixSQ_WAVE_FLUSH_IB 2 0x10e 1 0 4294967295 UNUSED 0 31 ixSQ_WAVE_FLAT_SCRATCH_LO 2 0x114 1 0 4294967295 DATA 0 31 ixSQ_WAVE_FLAT_SCRATCH_HI 2 0x115 1 0 4294967295 DATA 0 31 ixSQ_WAVE_HW_ID1 2 0x117 5 0 4294967295 WAVE_ID 0 4 SIMD_ID 8 9 WGP_ID 10 13 SA_ID 16 16 SE_ID 18 19 ixSQ_WAVE_HW_ID2 2 0x118 6 0 4294967295 QUEUE_ID 0 3 PIPE_ID 4 5 ME_ID 8 9 STATE_ID 12 14 WG_ID 16 20 VM_ID 24 27 ixSQ_WAVE_POPS_PACKER 2 0x119 2 0 4294967295 POPS_EN 0 0 POPS_PACKER_ID 1 2 ixSQ_WAVE_SCHED_MODE 2 0x11a 1 0 4294967295 DEP_MODE 0 1 ixSQ_WAVE_VGPR_OFFSET 2 0x11b 4 0 4294967295 SRC0 0 5 SRC1 6 11 SRC2 12 17 DST 18 23 ixSQ_WAVE_IB_STS2 2 0x11c 5 0 4294967295 INST_PREFETCH 0 1 RESOURCE_OVERRIDE 7 7 MEM_ORDER 8 9 FWD_PROGRESS 10 10 WAVE64 11 11 ixSQ_WAVE_SHADER_CYCLES 2 0x11d 1 0 4294967295 CYCLES 0 19 ixSQ_WAVE_TTMP0 2 0x26c 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP1 2 0x26d 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP2 2 0x26e 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP3 2 0x26f 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP4 2 0x270 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP5 2 0x271 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP6 2 0x272 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP7 2 0x273 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP8 2 0x274 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP9 2 0x275 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP10 2 0x276 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP11 2 0x277 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP12 2 0x278 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP13 2 0x279 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP14 2 0x27a 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP15 2 0x27b 1 0 4294967295 DATA 0 31 ixSQ_WAVE_M0 2 0x27c 1 0 4294967295 M0 0 31 ixSQ_WAVE_EXEC_LO 2 0x27e 1 0 4294967295 EXEC_LO 0 31 ixSQ_WAVE_EXEC_HI 2 0x27f 1 0 4294967295 EXEC_HI 0 31 ixSQ_INTERRUPT_WORD_AUTO 2 0x20c0 7 1 4294967295 THREAD_TRACE 0 0 WLT 1 1 THREAD_TRACE_BUF0_FULL 2 2 THREAD_TRACE_BUF1_FULL 3 3 THREAD_TRACE_UTC_ERROR 8 8 SE_ID 36 37 ENCODING 38 39 ixSQ_INTERRUPT_WORD_ERROR 2 0x20c0 9 1 4294967295 ERR_DETAIL 0 18 ERR_TYPE 19 22 SA_ID 23 23 PRIV 24 24 WAVE_ID 25 29 SIMD_ID 30 31 WGP_ID 32 35 SE_ID 36 37 ENCODING 38 39 ixSQ_INTERRUPT_WORD_WAVE 2 0x20c0 8 1 4294967295 DATA 0 22 SA_ID 23 23 PRIV 24 24 WAVE_ID 25 29 SIMD_ID 30 31 WGP_ID 32 35 SE_ID 36 37 ENCODING 38 39 ixDIDT_SQ_CTRL0 2 0x0 14 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 DIDT_THROTTLE_MODE 29 29 ixDIDT_SQ_CTRL1 2 0x1 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_SQ_CTRL2 2 0x2 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_SQ_CTRL_OCP 2 0x3 1 0 4294967295 OCP_MAX_POWER 0 15 ixDIDT_SQ_STALL_CTRL 2 0x4 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_SQ_TUNING_CTRL 2 0x5 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 2 0x6 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_SQ_CTRL3 2 0x7 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_SQ_STALL_PATTERN_1_2 2 0x8 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_SQ_STALL_PATTERN_3_4 2 0x9 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_SQ_STALL_PATTERN_5_6 2 0xa 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_SQ_STALL_PATTERN_7 2 0xb 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_SQ_MPD_SCALE_FACTOR 2 0xc 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_SQ_STALL_RELEASE_CNTL0 2 0xd 4 0 4294967295 DIDT_STALL_RELEASE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_SQ_STALL_RELEASE_CNTL1 2 0xe 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS 2 0xf 1 0 4294967295 DIDT_STALL_RELEASE_CNTL_FSM_STATE 0 1 ixDIDT_SQ_WEIGHT0_3 2 0x10 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_SQ_WEIGHT4_7 2 0x11 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_SQ_WEIGHT8_11 2 0x12 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_SQ_EDC_CTRL 2 0x13 13 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 EDC_LEVEL_COMB_ADAPT_MODE_EN 24 24 ixDIDT_SQ_EDC_THRESHOLD 2 0x14 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_SQ_EDC_STALL_PATTERN_1_2 2 0x15 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_3_4 2 0x16 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_5_6 2 0x17 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_7 2 0x18 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_SQ_EDC_TIMER_PERIOD 2 0x19 1 0 4294967295 EDC_TIMER_PERIOD 0 13 ixDIDT_SQ_THROTTLE_CTRL 2 0x1a 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_SQ_EDC_STALL_DELAY_1 2 0x1b 5 0 4294967295 EDC_STALL_DELAY_SQ0 0 5 EDC_STALL_DELAY_SQ1 6 11 EDC_STALL_DELAY_SQ2 12 17 EDC_STALL_DELAY_SQ3 18 23 UNUSED 24 31 ixDIDT_SQ_EDC_STALL_DELAY_2 2 0x1c 5 0 4294967295 EDC_STALL_DELAY_SQ4 0 5 EDC_STALL_DELAY_SQ5 6 11 EDC_STALL_DELAY_SQ6 12 17 EDC_STALL_DELAY_SQ7 18 23 UNUSED 24 31 ixDIDT_SQ_EDC_STALL_DELAY_3 2 0x1d 3 0 4294967295 EDC_STALL_DELAY_SQ8 0 5 EDC_STALL_DELAY_SQ9 6 11 UNUSED 12 31 ixDIDT_SQ_EDC_STATUS 2 0x1f 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_SQ_EDC_OVERFLOW 2 0x20 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 2 0x21 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_SQ_EDC_PCC_PERF_COUNTER 2 0x22 1 0 4294967295 EDC_PCC_PERF_COUNTER 0 31 ixDIDT_DB_CTRL0 2 0x30 14 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 DIDT_THROTTLE_MODE 29 29 ixDIDT_DB_CTRL1 2 0x31 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_DB_CTRL2 2 0x32 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_DB_CTRL_OCP 2 0x33 1 0 4294967295 OCP_MAX_POWER 0 15 ixDIDT_DB_STALL_CTRL 2 0x34 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_DB_TUNING_CTRL 2 0x35 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 2 0x36 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_DB_CTRL3 2 0x37 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_DB_STALL_PATTERN_1_2 2 0x38 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_DB_STALL_PATTERN_3_4 2 0x39 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_DB_STALL_PATTERN_5_6 2 0x3a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_DB_STALL_PATTERN_7 2 0x3b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_DB_MPD_SCALE_FACTOR 2 0x3c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_DB_STALL_RELEASE_CNTL0 2 0x3d 4 0 4294967295 DIDT_STALL_RELEASE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_DB_STALL_RELEASE_CNTL1 2 0x3e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_DB_STALL_RELEASE_CNTL_STATUS 2 0x3f 1 0 4294967295 DIDT_STALL_RELEASE_CNTL_FSM_STATE 0 1 ixDIDT_DB_WEIGHT0_3 2 0x40 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_DB_WEIGHT4_7 2 0x41 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_DB_WEIGHT8_11 2 0x42 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_DB_EDC_CTRL 2 0x43 13 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 EDC_LEVEL_COMB_ADAPT_MODE_EN 24 24 ixDIDT_DB_EDC_THRESHOLD 2 0x44 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_DB_EDC_STALL_PATTERN_1_2 2 0x45 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_DB_EDC_STALL_PATTERN_3_4 2 0x46 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_DB_EDC_STALL_PATTERN_5_6 2 0x47 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_DB_EDC_STALL_PATTERN_7 2 0x48 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_DB_EDC_TIMER_PERIOD 2 0x49 1 0 4294967295 EDC_TIMER_PERIOD 0 13 ixDIDT_DB_THROTTLE_CTRL 2 0x4a 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_DB_EDC_STALL_DELAY_1 2 0x4b 3 0 4294967295 EDC_STALL_DELAY_DB0 0 3 EDC_STALL_DELAY_DB1 4 7 UNUSED 8 31 ixDIDT_DB_EDC_STATUS 2 0x4f 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_DB_EDC_OVERFLOW 2 0x50 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_DB_EDC_ROLLING_POWER_DELTA 2 0x51 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_DB_EDC_PCC_PERF_COUNTER 2 0x52 1 0 4294967295 EDC_PCC_PERF_COUNTER 0 31 ixDIDT_TD_CTRL0 2 0x60 14 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 DIDT_THROTTLE_MODE 29 29 ixDIDT_TD_CTRL1 2 0x61 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TD_CTRL2 2 0x62 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TD_CTRL_OCP 2 0x63 1 0 4294967295 OCP_MAX_POWER 0 15 ixDIDT_TD_STALL_CTRL 2 0x64 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_TD_TUNING_CTRL 2 0x65 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 2 0x66 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_TD_CTRL3 2 0x67 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_TD_STALL_PATTERN_1_2 2 0x68 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_TD_STALL_PATTERN_3_4 2 0x69 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_TD_STALL_PATTERN_5_6 2 0x6a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_TD_STALL_PATTERN_7 2 0x6b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_TD_MPD_SCALE_FACTOR 2 0x6c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_TD_STALL_RELEASE_CNTL0 2 0x6d 4 0 4294967295 DIDT_STALL_RELEASE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_TD_STALL_RELEASE_CNTL1 2 0x6e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_TD_STALL_RELEASE_CNTL_STATUS 2 0x6f 1 0 4294967295 DIDT_STALL_RELEASE_CNTL_FSM_STATE 0 1 ixDIDT_TD_WEIGHT0_3 2 0x70 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TD_WEIGHT4_7 2 0x71 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TD_WEIGHT8_11 2 0x72 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TD_EDC_CTRL 2 0x73 13 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 EDC_LEVEL_COMB_ADAPT_MODE_EN 24 24 ixDIDT_TD_EDC_THRESHOLD 2 0x74 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_TD_EDC_STALL_PATTERN_1_2 2 0x75 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_TD_EDC_STALL_PATTERN_3_4 2 0x76 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_TD_EDC_STALL_PATTERN_5_6 2 0x77 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_TD_EDC_STALL_PATTERN_7 2 0x78 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_TD_EDC_TIMER_PERIOD 2 0x79 1 0 4294967295 EDC_TIMER_PERIOD 0 13 ixDIDT_TD_THROTTLE_CTRL 2 0x7a 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_TD_EDC_STALL_DELAY_1 2 0x7b 5 0 4294967295 EDC_STALL_DELAY_TD0 0 5 EDC_STALL_DELAY_TD1 6 11 EDC_STALL_DELAY_TD2 12 17 EDC_STALL_DELAY_TD3 18 23 UNUSED 24 31 ixDIDT_TD_EDC_STALL_DELAY_2 2 0x7c 5 0 4294967295 EDC_STALL_DELAY_TD4 0 5 EDC_STALL_DELAY_TD5 6 11 EDC_STALL_DELAY_TD6 12 17 EDC_STALL_DELAY_TD7 18 23 UNUSED 24 31 ixDIDT_TD_EDC_STALL_DELAY_3 2 0x7d 3 0 4294967295 EDC_STALL_DELAY_TD8 0 5 EDC_STALL_DELAY_TD9 6 11 UNUSED 12 31 ixDIDT_TD_EDC_STATUS 2 0x7f 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_TD_EDC_OVERFLOW 2 0x80 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_TD_EDC_ROLLING_POWER_DELTA 2 0x81 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_TD_EDC_PCC_PERF_COUNTER 2 0x82 1 0 4294967295 EDC_PCC_PERF_COUNTER 0 31 ixDIDT_TCP_CTRL0 2 0x90 14 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 DIDT_THROTTLE_MODE 29 29 ixDIDT_TCP_CTRL1 2 0x91 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TCP_CTRL2 2 0x92 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TCP_CTRL_OCP 2 0x93 1 0 4294967295 OCP_MAX_POWER 0 15 ixDIDT_TCP_STALL_CTRL 2 0x94 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_TCP_TUNING_CTRL 2 0x95 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 2 0x96 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_TCP_CTRL3 2 0x97 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_TCP_STALL_PATTERN_1_2 2 0x98 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_TCP_STALL_PATTERN_3_4 2 0x99 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_TCP_STALL_PATTERN_5_6 2 0x9a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_TCP_STALL_PATTERN_7 2 0x9b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_TCP_MPD_SCALE_FACTOR 2 0x9c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_TCP_STALL_RELEASE_CNTL0 2 0x9d 4 0 4294967295 DIDT_STALL_RELEASE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_TCP_STALL_RELEASE_CNTL1 2 0x9e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS 2 0x9f 1 0 4294967295 DIDT_STALL_RELEASE_CNTL_FSM_STATE 0 1 ixDIDT_TCP_WEIGHT0_3 2 0xa0 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TCP_WEIGHT4_7 2 0xa1 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TCP_WEIGHT8_11 2 0xa2 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TCP_EDC_CTRL 2 0xa3 13 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 EDC_LEVEL_COMB_ADAPT_MODE_EN 24 24 ixDIDT_TCP_EDC_THRESHOLD 2 0xa4 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_TCP_EDC_STALL_PATTERN_1_2 2 0xa5 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_3_4 2 0xa6 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_5_6 2 0xa7 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_7 2 0xa8 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_TCP_EDC_TIMER_PERIOD 2 0xa9 1 0 4294967295 EDC_TIMER_PERIOD 0 13 ixDIDT_TCP_THROTTLE_CTRL 2 0xaa 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_TCP_EDC_STALL_DELAY_1 2 0xab 5 0 4294967295 EDC_STALL_DELAY_TCP0 0 5 EDC_STALL_DELAY_TCP1 6 11 EDC_STALL_DELAY_TCP2 12 17 EDC_STALL_DELAY_TCP3 18 23 UNUSED 24 31 ixDIDT_TCP_EDC_STALL_DELAY_2 2 0xac 5 0 4294967295 EDC_STALL_DELAY_TCP4 0 5 EDC_STALL_DELAY_TCP5 6 11 EDC_STALL_DELAY_TCP6 12 17 EDC_STALL_DELAY_TCP7 18 23 UNUSED 24 31 ixDIDT_TCP_EDC_STALL_DELAY_3 2 0xad 3 0 4294967295 EDC_STALL_DELAY_TCP8 0 5 EDC_STALL_DELAY_TCP9 6 11 UNUSED 12 31 ixDIDT_TCP_EDC_STATUS 2 0xaf 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_TCP_EDC_OVERFLOW 2 0xb0 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 2 0xb1 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_TCP_EDC_PCC_PERF_COUNTER 2 0xb2 1 0 4294967295 EDC_PCC_PERF_COUNTER 0 31 ixDIDT_SQ_STALL_EVENT_COUNTER 2 0xc0 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_DB_STALL_EVENT_COUNTER 2 0xc1 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_TD_STALL_EVENT_COUNTER 2 0xc2 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_TCP_STALL_EVENT_COUNTER 2 0xc3 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31