3947 ixDIDT_SQ_CTRL0 2 0x0 13 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 ixDIDT_SQ_CTRL2 2 0x2 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_SQ_STALL_CTRL 2 0x4 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_SQ_TUNING_CTRL 2 0x5 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 2 0x6 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_SQ_CTRL3 2 0x7 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_SQ_STALL_PATTERN_1_2 2 0x8 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_SQ_STALL_PATTERN_3_4 2 0x9 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_SQ_STALL_PATTERN_5_6 2 0xa 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_SQ_STALL_PATTERN_7 2 0xb 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_SQ_MPD_SCALE_FACTOR 2 0xc 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_SQ_THROTTLE_CNTL0 2 0xd 4 0 4294967295 DIDT_THROTTLE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_SQ_THROTTLE_CNTL1 2 0xe 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_SQ_THROTTLE_CNTL_STATUS 2 0xf 1 0 4294967295 DIDT_THROTTLE_CNTL_FSM_STATE 0 1 ixDIDT_SQ_WEIGHT0_3 2 0x10 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_SQ_WEIGHT4_7 2 0x11 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_SQ_WEIGHT8_11 2 0x12 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_SQ_EDC_CTRL 2 0x13 12 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 ixDIDT_SQ_THROTTLE_CTRL 2 0x14 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_SQ_EDC_STALL_PATTERN_1_2 2 0x15 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_3_4 2 0x16 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_5_6 2 0x17 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_SQ_EDC_STALL_PATTERN_7 2 0x18 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_SQ_EDC_STATUS 2 0x19 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_SQ_EDC_STALL_DELAY_1 2 0x1a 4 0 4294967295 EDC_STALL_DELAY_SQ0 0 7 EDC_STALL_DELAY_SQ1 8 15 EDC_STALL_DELAY_SQ2 16 23 EDC_STALL_DELAY_SQ3 24 31 ixDIDT_SQ_EDC_STALL_DELAY_2 2 0x1b 4 0 4294967295 EDC_STALL_DELAY_SQ4 0 7 EDC_STALL_DELAY_SQ5 8 15 EDC_STALL_DELAY_SQ6 16 23 EDC_STALL_DELAY_SQ7 24 31 ixDIDT_SQ_EDC_STALL_DELAY_3 2 0x1c 4 0 4294967295 EDC_STALL_DELAY_SQ8 0 7 EDC_STALL_DELAY_SQ9 8 15 EDC_STALL_DELAY_SQ10 16 23 EDC_STALL_DELAY_SQ11 24 31 ixDIDT_SQ_EDC_STALL_DELAY_4 2 0x1d 2 0 4294967295 EDC_STALL_DELAY_SQ12 0 7 EDC_STALL_DELAY_SQ13 8 15 ixDIDT_SQ_EDC_OVERFLOW 2 0x1e 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 2 0x1f 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_DB_CTRL0 2 0x20 13 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 ixDIDT_DB_CTRL2 2 0x22 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_DB_STALL_CTRL 2 0x24 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_DB_TUNING_CTRL 2 0x25 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 2 0x26 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_DB_CTRL3 2 0x27 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_DB_STALL_PATTERN_1_2 2 0x28 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_DB_STALL_PATTERN_3_4 2 0x29 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_DB_STALL_PATTERN_5_6 2 0x2a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_DB_STALL_PATTERN_7 2 0x2b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_DB_MPD_SCALE_FACTOR 2 0x2c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_DB_THROTTLE_CNTL0 2 0x2d 4 0 4294967295 DIDT_THROTTLE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_DB_THROTTLE_CNTL1 2 0x2e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_DB_THROTTLE_CNTL_STATUS 2 0x2f 1 0 4294967295 DIDT_THROTTLE_CNTL_FSM_STATE 0 1 ixDIDT_DB_WEIGHT0_3 2 0x30 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_DB_WEIGHT4_7 2 0x31 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_DB_WEIGHT8_11 2 0x32 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_DB_EDC_CTRL 2 0x33 12 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 ixDIDT_DB_THROTTLE_CTRL 2 0x34 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_DB_EDC_STALL_PATTERN_1_2 2 0x35 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_DB_EDC_STALL_PATTERN_3_4 2 0x36 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_DB_EDC_STALL_PATTERN_5_6 2 0x37 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_DB_EDC_STALL_PATTERN_7 2 0x38 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_DB_EDC_STATUS 2 0x39 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_DB_EDC_STALL_DELAY_1 2 0x3a 4 0 4294967295 EDC_STALL_DELAY_DB0 0 5 EDC_STALL_DELAY_DB1 6 11 EDC_STALL_DELAY_DB2 12 17 EDC_STALL_DELAY_DB3 18 23 ixDIDT_DB_EDC_OVERFLOW 2 0x3e 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_DB_EDC_ROLLING_POWER_DELTA 2 0x3f 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_TD_CTRL0 2 0x40 13 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 ixDIDT_TD_CTRL2 2 0x42 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TD_STALL_CTRL 2 0x44 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_TD_TUNING_CTRL 2 0x45 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 2 0x46 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_TD_CTRL3 2 0x47 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_TD_STALL_PATTERN_1_2 2 0x48 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_TD_STALL_PATTERN_3_4 2 0x49 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_TD_STALL_PATTERN_5_6 2 0x4a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_TD_STALL_PATTERN_7 2 0x4b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_TD_MPD_SCALE_FACTOR 2 0x4c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_TD_THROTTLE_CNTL0 2 0x4d 4 0 4294967295 DIDT_THROTTLE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_TD_THROTTLE_CNTL1 2 0x4e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_TD_THROTTLE_CNTL_STATUS 2 0x4f 1 0 4294967295 DIDT_THROTTLE_CNTL_FSM_STATE 0 1 ixDIDT_TD_WEIGHT0_3 2 0x50 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TD_WEIGHT4_7 2 0x51 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TD_WEIGHT8_11 2 0x52 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TD_EDC_CTRL 2 0x53 12 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 ixDIDT_TD_THROTTLE_CTRL 2 0x54 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_TD_EDC_STALL_PATTERN_1_2 2 0x55 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_TD_EDC_STALL_PATTERN_3_4 2 0x56 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_TD_EDC_STALL_PATTERN_5_6 2 0x57 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_TD_EDC_STALL_PATTERN_7 2 0x58 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_TD_EDC_STATUS 2 0x59 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_TD_EDC_STALL_DELAY_1 2 0x5a 4 0 4294967295 EDC_STALL_DELAY_TD0 0 7 EDC_STALL_DELAY_TD1 8 15 EDC_STALL_DELAY_TD2 16 23 EDC_STALL_DELAY_TD3 24 31 ixDIDT_TD_EDC_STALL_DELAY_2 2 0x5b 4 0 4294967295 EDC_STALL_DELAY_TD4 0 7 EDC_STALL_DELAY_TD5 8 15 EDC_STALL_DELAY_TD6 16 23 EDC_STALL_DELAY_TD7 24 31 ixDIDT_TD_EDC_STALL_DELAY_3 2 0x5c 4 0 4294967295 EDC_STALL_DELAY_TD8 0 7 EDC_STALL_DELAY_TD9 8 15 EDC_STALL_DELAY_TD10 16 23 EDC_STALL_DELAY_TD11 24 31 ixDIDT_TD_EDC_STALL_DELAY_4 2 0x5d 2 0 4294967295 EDC_STALL_DELAY_TD12 0 7 EDC_STALL_DELAY_TD13 8 15 ixDIDT_TD_EDC_OVERFLOW 2 0x5e 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_TD_EDC_ROLLING_POWER_DELTA 2 0x5f 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_TCP_CTRL0 2 0x60 13 0 4294967295 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_CTRL_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_STALL_CTRL_EN 5 5 DIDT_TUNING_CTRL_EN 6 6 DIDT_STALL_AUTO_RELEASE_EN 7 7 DIDT_HI_POWER_THRESHOLD 8 23 DIDT_AUTO_MPD_EN 24 24 DIDT_STALL_EVENT_EN 25 25 DIDT_STALL_EVENT_COUNTER_CLEAR 26 26 DIDT_RLC_FORCE_STALL_EN 27 27 DIDT_RLC_STALL_LEVEL_SEL 28 28 ixDIDT_TCP_CTRL2 2 0x62 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TCP_STALL_CTRL 2 0x64 4 0 4294967295 DIDT_STALL_DELAY_HI 0 5 DIDT_STALL_DELAY_LO 6 11 DIDT_MAX_STALLS_ALLOWED_HI 12 17 DIDT_MAX_STALLS_ALLOWED_LO 18 23 ixDIDT_TCP_TUNING_CTRL 2 0x65 2 0 4294967295 MAX_POWER_DELTA_HI 0 13 MAX_POWER_DELTA_LO 14 27 ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL 2 0x66 1 0 4294967295 DIDT_STALL_AUTO_RELEASE_TIME 0 23 ixDIDT_TCP_CTRL3 2 0x67 12 0 4294967295 GC_DIDT_ENABLE 0 0 GC_DIDT_CLK_EN_OVERRIDE 1 1 THROTTLE_POLICY 2 3 DIDT_TRIGGER_THROTTLE_LOWBIT 4 8 DIDT_POWER_LEVEL_LOWBIT 9 13 DIDT_STALL_PATTERN_BIT_NUMS 14 21 GC_DIDT_LEVEL_COMB_EN 22 22 SE_DIDT_LEVEL_COMB_EN 23 23 QUALIFY_STALL_EN 24 24 DIDT_STALL_SEL 25 26 DIDT_FORCE_STALL 27 27 DIDT_STALL_DELAY_EN 28 28 ixDIDT_TCP_STALL_PATTERN_1_2 2 0x68 2 0 4294967295 DIDT_STALL_PATTERN_1 0 14 DIDT_STALL_PATTERN_2 16 30 ixDIDT_TCP_STALL_PATTERN_3_4 2 0x69 2 0 4294967295 DIDT_STALL_PATTERN_3 0 14 DIDT_STALL_PATTERN_4 16 30 ixDIDT_TCP_STALL_PATTERN_5_6 2 0x6a 2 0 4294967295 DIDT_STALL_PATTERN_5 0 14 DIDT_STALL_PATTERN_6 16 30 ixDIDT_TCP_STALL_PATTERN_7 2 0x6b 1 0 4294967295 DIDT_STALL_PATTERN_7 0 14 ixDIDT_TCP_MPD_SCALE_FACTOR 2 0x6c 8 0 4294967295 MPD_RATIO_SCALE_LEVEL1 0 3 MPD_RATIO_SCALE_LEVEL2 4 7 MPD_RATIO_SCALE_LEVEL3 8 11 MPD_RATIO_SCALE_LEVEL4 12 15 MPD_SCALE_LEVEL0 16 19 MPD_SCALE_LEVEL1 20 23 MPD_SCALE_LEVEL2 24 27 MPD_SCALE_LEVEL3 28 31 ixDIDT_TCP_THROTTLE_CNTL0 2 0x6d 4 0 4294967295 DIDT_THROTTLE_CNTL_EN 0 0 DIDT_STALL_CNTL_SEL 1 1 DIDT_RELEASE_DELAY_HI 2 12 DIDT_RELEASE_DELAY_LO 13 23 ixDIDT_TCP_THROTTLE_CNTL1 2 0x6e 4 0 4294967295 DIDT_BASE_RELEASE_ALLOWED_HI 0 4 DIDT_INCR_RELEASE_ALLOWED_HI 5 9 DIDT_BASE_RELEASE_ALLOWED_LO 10 14 DIDT_INCR_RELEASE_ALLOWED_LO 15 19 ixDIDT_TCP_THROTTLE_CNTL_STATUS 2 0x6f 1 0 4294967295 DIDT_THROTTLE_CNTL_FSM_STATE 0 1 ixDIDT_TCP_WEIGHT0_3 2 0x70 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TCP_WEIGHT4_7 2 0x71 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TCP_WEIGHT8_11 2 0x72 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TCP_EDC_CTRL 2 0x73 12 0 4294967295 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_STALL_PATTERN_BIT_NUMS 9 16 EDC_ALLOW_WRITE_PWRDELTA 17 17 GC_EDC_EN 18 18 GC_EDC_STALL_POLICY 19 20 GC_EDC_LEVEL_COMB_EN 21 21 SE_EDC_LEVEL_COMB_EN 22 22 EDC_LEVEL_MODE_SEL 23 23 ixDIDT_TCP_THROTTLE_CTRL 2 0x74 4 0 4294967295 GC_EDC_STALL_EN 0 0 PCC_STALL_EN 1 1 PWRBRK_STALL_EN 2 2 GC_EDC_ONLY_MODE 3 3 ixDIDT_TCP_EDC_STALL_PATTERN_1_2 2 0x75 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_3_4 2 0x76 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_5_6 2 0x77 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixDIDT_TCP_EDC_STALL_PATTERN_7 2 0x78 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixDIDT_TCP_EDC_STATUS 2 0x79 2 0 4294967295 EDC_FSM_STATE 0 0 EDC_THROTTLE_LEVEL 1 3 ixDIDT_TCP_EDC_STALL_DELAY_1 2 0x7a 4 0 4294967295 EDC_STALL_DELAY_TCP0 0 7 EDC_STALL_DELAY_TCP1 8 15 EDC_STALL_DELAY_TCP2 16 23 EDC_STALL_DELAY_TCP3 24 31 ixDIDT_TCP_EDC_STALL_DELAY_2 2 0x7b 4 0 4294967295 EDC_STALL_DELAY_TCP4 0 7 EDC_STALL_DELAY_TCP5 8 15 EDC_STALL_DELAY_TCP6 16 23 EDC_STALL_DELAY_TCP7 24 31 ixDIDT_TCP_EDC_STALL_DELAY_3 2 0x7c 4 0 4294967295 EDC_STALL_DELAY_TCP8 0 7 EDC_STALL_DELAY_TCP9 8 15 EDC_STALL_DELAY_TCP10 16 23 EDC_STALL_DELAY_TCP11 24 31 ixDIDT_TCP_EDC_STALL_DELAY_4 2 0x7d 2 0 4294967295 EDC_STALL_DELAY_TCP12 0 7 EDC_STALL_DELAY_TCP13 8 15 ixDIDT_TCP_EDC_OVERFLOW 2 0x7e 2 0 4294967295 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 ixDIDT_TCP_EDC_ROLLING_POWER_DELTA 2 0x7f 1 0 4294967295 EDC_ROLLING_POWER_DELTA 0 31 ixDIDT_SQ_STALL_EVENT_COUNTER 2 0xa0 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_DB_STALL_EVENT_COUNTER 2 0xa1 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_TD_STALL_EVENT_COUNTER 2 0xa2 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_TCP_STALL_EVENT_COUNTER 2 0xa3 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_DBR_STALL_EVENT_COUNTER 2 0xa4 1 0 4294967295 DIDT_STALL_EVENT_COUNTER 0 31 ixDIDT_SQ_EDC_PCC_PERF_COUNTER 2 0xa5 1 0 4294967295 PERF_COUNTER 0 31 ixDIDT_TD_EDC_PCC_PERF_COUNTER 2 0xa6 1 0 4294967295 PERF_COUNTER 0 31 ixDIDT_TCP_EDC_PCC_PERF_COUNTER 2 0xa7 1 0 4294967295 PERF_COUNTER 0 31 ixDIDT_DB_EDC_PCC_PERF_COUNTER 2 0xa8 1 0 4294967295 PERF_COUNTER 0 31 ixDIDT_DBR_EDC_PCC_PERF_COUNTER 2 0xa9 1 0 4294967295 PERF_COUNTER 0 31 ixDIDT_SQ_CTRL1 2 0xb0 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_SQ_EDC_THRESHOLD 2 0xb1 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_DB_CTRL1 2 0xb2 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_DB_EDC_THRESHOLD 2 0xb3 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_TD_CTRL1 2 0xb4 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TD_EDC_THRESHOLD 2 0xb5 1 0 4294967295 EDC_THRESHOLD 0 31 ixDIDT_TCP_CTRL1 2 0xb6 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TCP_EDC_THRESHOLD 2 0xb7 1 0 4294967295 EDC_THRESHOLD 0 31 regCP_CPC_STATUS 0 0x84 16 0 0 MEC1_BUSY 0 0 MEC2_BUSY 1 1 DC0_BUSY 2 2 DC1_BUSY 3 3 RCIU1_BUSY 4 4 RCIU2_BUSY 5 5 ROQ1_BUSY 6 6 ROQ2_BUSY 7 7 TCIU_BUSY 10 10 SCRATCH_RAM_BUSY 11 11 QU_BUSY 12 12 UTCL2IU_BUSY 13 13 SAVE_RESTORE_BUSY 14 14 CPG_CPC_BUSY 29 29 CPF_CPC_BUSY 30 30 CPC_BUSY 31 31 regCP_CPC_BUSY_STAT 0 0x85 28 0 0 MEC1_LOAD_BUSY 0 0 MEC1_SEMAPOHRE_BUSY 1 1 MEC1_MUTEX_BUSY 2 2 MEC1_MESSAGE_BUSY 3 3 MEC1_EOP_QUEUE_BUSY 4 4 MEC1_IQ_QUEUE_BUSY 5 5 MEC1_IB_QUEUE_BUSY 6 6 MEC1_TC_BUSY 7 7 MEC1_DMA_BUSY 8 8 MEC1_PARTIAL_FLUSH_BUSY 9 9 MEC1_PIPE0_BUSY 10 10 MEC1_PIPE1_BUSY 11 11 MEC1_PIPE2_BUSY 12 12 MEC1_PIPE3_BUSY 13 13 MEC2_LOAD_BUSY 16 16 MEC2_SEMAPOHRE_BUSY 17 17 MEC2_MUTEX_BUSY 18 18 MEC2_MESSAGE_BUSY 19 19 MEC2_EOP_QUEUE_BUSY 20 20 MEC2_IQ_QUEUE_BUSY 21 21 MEC2_IB_QUEUE_BUSY 22 22 MEC2_TC_BUSY 23 23 MEC2_DMA_BUSY 24 24 MEC2_PARTIAL_FLUSH_BUSY 25 25 MEC2_PIPE0_BUSY 26 26 MEC2_PIPE1_BUSY 27 27 MEC2_PIPE2_BUSY 28 28 MEC2_PIPE3_BUSY 29 29 regCP_CPC_STALLED_STAT1 0 0x86 14 0 0 RCIU_TX_FREE_STALL 3 3 RCIU_PRIV_VIOLATION 4 4 TCIU_TX_FREE_STALL 6 6 MEC1_DECODING_PACKET 8 8 MEC1_WAIT_ON_RCIU 9 9 MEC1_WAIT_ON_RCIU_READ 10 10 MEC1_WAIT_ON_ROQ_DATA 13 13 MEC2_DECODING_PACKET 16 16 MEC2_WAIT_ON_RCIU 17 17 MEC2_WAIT_ON_RCIU_READ 18 18 MEC2_WAIT_ON_ROQ_DATA 21 21 UTCL2IU_WAITING_ON_FREE 22 22 UTCL2IU_WAITING_ON_TAGS 23 23 UTCL1_WAITING_ON_TRANS 24 24 regCP_CPF_STATUS 0 0x87 21 0 0 POST_WPTR_GFX_BUSY 0 0 CSF_BUSY 1 1 ROQ_ALIGN_BUSY 4 4 ROQ_RING_BUSY 5 5 ROQ_INDIRECT1_BUSY 6 6 ROQ_INDIRECT2_BUSY 7 7 ROQ_STATE_BUSY 8 8 ROQ_CE_RING_BUSY 9 9 ROQ_CE_INDIRECT1_BUSY 10 10 ROQ_CE_INDIRECT2_BUSY 11 11 SEMAPHORE_BUSY 12 12 INTERRUPT_BUSY 13 13 TCIU_BUSY 14 14 HQD_BUSY 15 15 PRT_BUSY 16 16 UTCL2IU_BUSY 17 17 CPF_GFX_BUSY 26 26 CPF_CMP_BUSY 27 27 GRBM_CPF_STAT_BUSY 28 29 CPC_CPF_BUSY 30 30 CPF_BUSY 31 31 regCP_CPF_BUSY_STAT 0 0x88 31 0 0 REG_BUS_FIFO_BUSY 0 0 CSF_RING_BUSY 1 1 CSF_INDIRECT1_BUSY 2 2 CSF_INDIRECT2_BUSY 3 3 CSF_STATE_BUSY 4 4 CSF_CE_INDR1_BUSY 5 5 CSF_CE_INDR2_BUSY 6 6 CSF_ARBITER_BUSY 7 7 CSF_INPUT_BUSY 8 8 OUTSTANDING_READ_TAGS 9 9 HPD_PROCESSING_EOP_BUSY 11 11 HQD_DISPATCH_BUSY 12 12 HQD_IQ_TIMER_BUSY 13 13 HQD_DMA_OFFLOAD_BUSY 14 14 HQD_WAIT_SEMAPHORE_BUSY 15 15 HQD_SIGNAL_SEMAPHORE_BUSY 16 16 HQD_MESSAGE_BUSY 17 17 HQD_PQ_FETCHER_BUSY 18 18 HQD_IB_FETCHER_BUSY 19 19 HQD_IQ_FETCHER_BUSY 20 20 HQD_EOP_FETCHER_BUSY 21 21 HQD_CONSUMED_RPTR_BUSY 22 22 HQD_FETCHER_ARB_BUSY 23 23 HQD_ROQ_ALIGN_BUSY 24 24 HQD_ROQ_EOP_BUSY 25 25 HQD_ROQ_IQ_BUSY 26 26 HQD_ROQ_PQ_BUSY 27 27 HQD_ROQ_IB_BUSY 28 28 HQD_WPTR_POLL_BUSY 29 29 HQD_PQ_BUSY 30 30 HQD_IB_BUSY 31 31 regCP_CPF_STALLED_STAT1 0 0x89 11 0 0 RING_FETCHING_DATA 0 0 INDR1_FETCHING_DATA 1 1 INDR2_FETCHING_DATA 2 2 STATE_FETCHING_DATA 3 3 TCIU_WAITING_ON_FREE 5 5 TCIU_WAITING_ON_TAGS 6 6 UTCL2IU_WAITING_ON_FREE 7 7 UTCL2IU_WAITING_ON_TAGS 8 8 GFX_UTCL1_WAITING_ON_TRANS 9 9 CMP_UTCL1_WAITING_ON_TRANS 10 10 RCIU_WAITING_ON_FREE 11 11 regCP_CPC_GRBM_FREE_COUNT 0 0x8b 1 0 0 FREE_COUNT 0 5 regCP_CPC_PRIV_VIOLATION_ADDR 0 0x8c 1 0 0 PRIV_VIOLATION_ADDR 0 15 regCP_MEC_CNTL 0 0x8d 11 0 0 MEC_INVALIDATE_ICACHE 4 4 MEC_ME1_PIPE0_RESET 16 16 MEC_ME1_PIPE1_RESET 17 17 MEC_ME1_PIPE2_RESET 18 18 MEC_ME1_PIPE3_RESET 19 19 MEC_ME2_PIPE0_RESET 20 20 MEC_ME2_PIPE1_RESET 21 21 MEC_ME2_HALT 28 28 MEC_ME2_STEP 29 29 MEC_ME1_HALT 30 30 MEC_ME1_STEP 31 31 regCP_MEC_ME1_HEADER_DUMP 0 0x8e 1 0 0 HEADER_DUMP 0 31 regCP_MEC_ME2_HEADER_DUMP 0 0x8f 1 0 0 HEADER_DUMP 0 31 regCP_CPC_SCRATCH_INDEX 0 0x90 1 0 0 SCRATCH_INDEX 0 8 regCP_CPC_SCRATCH_DATA 0 0x91 1 0 0 SCRATCH_DATA 0 31 regCP_CPF_GRBM_FREE_COUNT 0 0x92 1 0 0 FREE_COUNT 0 2 regCP_CPC_HALT_HYST_COUNT 0 0xa7 1 0 0 COUNT 0 3 regCP_CE_COMPARE_COUNT 0 0xc0 1 0 0 COMPARE_COUNT 0 31 regCP_CE_DE_COUNT 0 0xc1 1 0 0 DRAW_ENGINE_COUNT 0 31 regCP_DE_CE_COUNT 0 0xc2 1 0 0 CONST_ENGINE_COUNT 0 31 regCP_DE_LAST_INVAL_COUNT 0 0xc3 1 0 0 LAST_INVAL_COUNT 0 31 regCP_DE_DE_COUNT 0 0xc4 1 0 0 DRAW_ENGINE_COUNT 0 31 regCP_STALLED_STAT3 0 0x19c 19 0 0 CE_TO_CSF_NOT_RDY_TO_RCV 0 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV 1 1 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER 2 2 CE_TO_RAM_INIT_NOT_RDY 3 3 CE_TO_RAM_DUMP_NOT_RDY 4 4 CE_TO_RAM_WRITE_NOT_RDY 5 5 CE_TO_INC_FIFO_NOT_RDY_TO_RCV 6 6 CE_TO_WR_FIFO_NOT_RDY_TO_RCV 7 7 CE_WAITING_ON_BUFFER_DATA 10 10 CE_WAITING_ON_CE_BUFFER_FLAG 11 11 CE_WAITING_ON_DE_COUNTER 12 12 CE_WAITING_ON_DE_COUNTER_UNDERFLOW 13 13 TCIU_WAITING_ON_FREE 14 14 TCIU_WAITING_ON_TAGS 15 15 CE_STALLED_ON_TC_WR_CONFIRM 16 16 CE_STALLED_ON_ATOMIC_RTN_DATA 17 17 UTCL2IU_WAITING_ON_FREE 18 18 UTCL2IU_WAITING_ON_TAGS 19 19 UTCL1_WAITING_ON_TRANS 20 20 regCP_STALLED_STAT1 0 0x19d 16 0 0 RBIU_TO_DMA_NOT_RDY_TO_RCV 0 0 RBIU_TO_SEM_NOT_RDY_TO_RCV 2 2 RBIU_TO_MEMWR_NOT_RDY_TO_RCV 4 4 ME_HAS_ACTIVE_CE_BUFFER_FLAG 10 10 ME_HAS_ACTIVE_DE_BUFFER_FLAG 11 11 ME_STALLED_ON_TC_WR_CONFIRM 12 12 ME_STALLED_ON_ATOMIC_RTN_DATA 13 13 ME_WAITING_ON_TC_READ_DATA 14 14 ME_WAITING_ON_REG_READ_DATA 15 15 RCIU_WAITING_ON_GDS_FREE 23 23 RCIU_WAITING_ON_GRBM_FREE 24 24 RCIU_WAITING_ON_VGT_FREE 25 25 RCIU_STALLED_ON_ME_READ 26 26 RCIU_STALLED_ON_DMA_READ 27 27 RCIU_STALLED_ON_APPEND_READ 28 28 RCIU_HALTED_BY_REG_VIOLATION 29 29 regCP_STALLED_STAT2 0 0x19e 29 0 0 PFP_TO_CSF_NOT_RDY_TO_RCV 0 0 PFP_TO_MEQ_NOT_RDY_TO_RCV 1 1 PFP_TO_RCIU_NOT_RDY_TO_RCV 2 2 PFP_TO_VGT_WRITES_PENDING 4 4 PFP_RCIU_READ_PENDING 5 5 PFP_WAITING_ON_BUFFER_DATA 8 8 ME_WAIT_ON_CE_COUNTER 9 9 ME_WAIT_ON_AVAIL_BUFFER 10 10 GFX_CNTX_NOT_AVAIL_TO_ME 11 11 ME_RCIU_NOT_RDY_TO_RCV 12 12 ME_TO_CONST_NOT_RDY_TO_RCV 13 13 ME_WAITING_DATA_FROM_PFP 14 14 ME_WAITING_ON_PARTIAL_FLUSH 15 15 MEQ_TO_ME_NOT_RDY_TO_RCV 16 16 STQ_TO_ME_NOT_RDY_TO_RCV 17 17 ME_WAITING_DATA_FROM_STQ 18 18 PFP_STALLED_ON_TC_WR_CONFIRM 19 19 PFP_STALLED_ON_ATOMIC_RTN_DATA 20 20 EOPD_FIFO_NEEDS_SC_EOP_DONE 21 21 EOPD_FIFO_NEEDS_WR_CONFIRM 22 22 STRMO_WR_OF_PRIM_DATA_PENDING 23 23 PIPE_STATS_WR_DATA_PENDING 24 24 APPEND_RDY_WAIT_ON_CS_DONE 25 25 APPEND_RDY_WAIT_ON_PS_DONE 26 26 APPEND_WAIT_ON_WR_CONFIRM 27 27 APPEND_ACTIVE_PARTITION 28 28 APPEND_WAITING_TO_SEND_MEMWRITE 29 29 SURF_SYNC_NEEDS_IDLE_CNTXS 30 30 SURF_SYNC_NEEDS_ALL_CLEAN 31 31 regCP_BUSY_STAT 0 0x19f 16 0 0 REG_BUS_FIFO_BUSY 0 0 COHER_CNT_NEQ_ZERO 6 6 PFP_PARSING_PACKETS 7 7 ME_PARSING_PACKETS 8 8 RCIU_PFP_BUSY 9 9 RCIU_ME_BUSY 10 10 SEM_CMDFIFO_NOT_EMPTY 12 12 SEM_FAILED_AND_HOLDING 13 13 SEM_POLLING_FOR_PASS 14 14 GFX_CONTEXT_BUSY 15 15 ME_PARSER_BUSY 17 17 EOP_DONE_BUSY 18 18 STRM_OUT_BUSY 19 19 PIPE_STATS_BUSY 20 20 RCIU_CE_BUSY 21 21 CE_PARSING_PACKETS 22 22 regCP_STAT 0 0x1a0 22 0 0 ROQ_RING_BUSY 9 9 ROQ_INDIRECT1_BUSY 10 10 ROQ_INDIRECT2_BUSY 11 11 ROQ_STATE_BUSY 12 12 DC_BUSY 13 13 UTCL2IU_BUSY 14 14 PFP_BUSY 15 15 MEQ_BUSY 16 16 ME_BUSY 17 17 QUERY_BUSY 18 18 SEMAPHORE_BUSY 19 19 INTERRUPT_BUSY 20 20 SURFACE_SYNC_BUSY 21 21 DMA_BUSY 22 22 RCIU_BUSY 23 23 SCRATCH_RAM_BUSY 24 24 CE_BUSY 26 26 TCIU_BUSY 27 27 ROQ_CE_RING_BUSY 28 28 ROQ_CE_INDIRECT1_BUSY 29 29 ROQ_CE_INDIRECT2_BUSY 30 30 CP_BUSY 31 31 regCP_ME_HEADER_DUMP 0 0x1a1 1 0 0 ME_HEADER_DUMP 0 31 regCP_PFP_HEADER_DUMP 0 0x1a2 1 0 0 PFP_HEADER_DUMP 0 31 regCP_GRBM_FREE_COUNT 0 0x1a3 3 0 0 FREE_COUNT 0 5 FREE_COUNT_GDS 8 13 FREE_COUNT_PFP 16 21 regCP_CE_HEADER_DUMP 0 0x1a4 1 0 0 CE_HEADER_DUMP 0 31 regCP_PFP_INSTR_PNTR 0 0x1a5 1 0 0 INSTR_PNTR 0 15 regCP_ME_INSTR_PNTR 0 0x1a6 1 0 0 INSTR_PNTR 0 15 regCP_CE_INSTR_PNTR 0 0x1a7 1 0 0 INSTR_PNTR 0 15 regCP_MEC1_INSTR_PNTR 0 0x1a8 1 0 0 INSTR_PNTR 0 15 regCP_MEC2_INSTR_PNTR 0 0x1a9 1 0 0 INSTR_PNTR 0 15 regCP_CSF_STAT 0 0x1b4 1 0 0 BUFFER_REQUEST_COUNT 8 16 regCP_ME_CNTL 0 0x1b6 15 0 0 CE_INVALIDATE_ICACHE 4 4 PFP_INVALIDATE_ICACHE 6 6 ME_INVALIDATE_ICACHE 8 8 CE_PIPE0_RESET 16 16 CE_PIPE1_RESET 17 17 PFP_PIPE0_RESET 18 18 PFP_PIPE1_RESET 19 19 ME_PIPE0_RESET 20 20 ME_PIPE1_RESET 21 21 CE_HALT 24 24 CE_STEP 25 25 PFP_HALT 26 26 PFP_STEP 27 27 ME_HALT 28 28 ME_STEP 29 29 regCP_CNTX_STAT 0 0x1b8 4 0 0 ACTIVE_HP3D_CONTEXTS 0 7 CURRENT_HP3D_CONTEXT 8 10 ACTIVE_GFX_CONTEXTS 20 27 CURRENT_GFX_CONTEXT 28 30 regCP_ME_PREEMPTION 0 0x1b9 1 0 0 OBSOLETE 0 0 regCP_ROQ_THRESHOLDS 0 0x1bc 2 0 0 IB1_START 0 7 IB2_START 8 15 regCP_MEQ_STQ_THRESHOLD 0 0x1bd 1 0 0 STQ_START 0 7 regCP_RB2_RPTR 0 0x1be 1 0 0 RB_RPTR 0 19 regCP_RB1_RPTR 0 0x1bf 1 0 0 RB_RPTR 0 19 regCP_RB0_RPTR 0 0x1c0 1 0 0 RB_RPTR 0 19 regCP_RB_RPTR 0 0x1c0 1 0 0 RB_RPTR 0 19 regCP_RB_WPTR_DELAY 0 0x1c1 2 0 0 PRE_WRITE_TIMER 0 27 PRE_WRITE_LIMIT 28 31 regCP_RB_WPTR_POLL_CNTL 0 0x1c2 2 0 0 POLL_FREQUENCY 0 15 IDLE_POLL_COUNT 16 31 regCP_ROQ1_THRESHOLDS 0 0x1d5 4 0 0 RB1_START 0 7 RB2_START 8 15 R0_IB1_START 16 23 R1_IB1_START 24 31 regCP_ROQ2_THRESHOLDS 0 0x1d6 4 0 0 R2_IB1_START 0 7 R0_IB2_START 8 15 R1_IB2_START 16 23 R2_IB2_START 24 31 regCP_STQ_THRESHOLDS 0 0x1d7 3 0 0 STQ0_START 0 7 STQ1_START 8 15 STQ2_START 16 23 regCP_QUEUE_THRESHOLDS 0 0x1d8 2 0 0 ROQ_IB1_START 0 5 ROQ_IB2_START 8 13 regCP_MEQ_THRESHOLDS 0 0x1d9 2 0 0 MEQ1_START 0 7 MEQ2_START 8 15 regCP_ROQ_AVAIL 0 0x1da 2 0 0 ROQ_CNT_RING 0 10 ROQ_CNT_IB1 16 26 regCP_STQ_AVAIL 0 0x1db 1 0 0 STQ_CNT 0 8 regCP_ROQ2_AVAIL 0 0x1dc 1 0 0 ROQ_CNT_IB2 0 10 regCP_MEQ_AVAIL 0 0x1dd 1 0 0 MEQ_CNT 0 9 regCP_CMD_INDEX 0 0x1de 3 0 0 CMD_INDEX 0 10 CMD_ME_SEL 12 13 CMD_QUEUE_SEL 16 18 regCP_CMD_DATA 0 0x1df 1 0 0 CMD_DATA 0 31 regCP_ROQ_RB_STAT 0 0x1e0 2 0 0 ROQ_RPTR_PRIMARY 0 9 ROQ_WPTR_PRIMARY 16 25 regCP_ROQ_IB1_STAT 0 0x1e1 2 0 0 ROQ_RPTR_INDIRECT1 0 9 ROQ_WPTR_INDIRECT1 16 25 regCP_ROQ_IB2_STAT 0 0x1e2 2 0 0 ROQ_RPTR_INDIRECT2 0 9 ROQ_WPTR_INDIRECT2 16 25 regCP_STQ_STAT 0 0x1e3 1 0 0 STQ_RPTR 0 9 regCP_STQ_WR_STAT 0 0x1e4 1 0 0 STQ_WPTR 0 9 regCP_MEQ_STAT 0 0x1e5 2 0 0 MEQ_RPTR 0 9 MEQ_WPTR 16 25 regCP_CEQ1_AVAIL 0 0x1e6 2 0 0 CEQ_CNT_RING 0 10 CEQ_CNT_IB1 16 26 regCP_CEQ2_AVAIL 0 0x1e7 1 0 0 CEQ_CNT_IB2 0 10 regCP_CE_ROQ_RB_STAT 0 0x1e8 2 0 0 CEQ_RPTR_PRIMARY 0 9 CEQ_WPTR_PRIMARY 16 25 regCP_CE_ROQ_IB1_STAT 0 0x1e9 2 0 0 CEQ_RPTR_INDIRECT1 0 9 CEQ_WPTR_INDIRECT1 16 25 regCP_CE_ROQ_IB2_STAT 0 0x1ea 2 0 0 CEQ_RPTR_INDIRECT2 0 9 CEQ_WPTR_INDIRECT2 16 25 regCP_PRIV_VIOLATION_ADDR 0 0x1fa 1 0 0 PRIV_VIOLATION_ADDR 0 15 regCP_EOPQ_WAIT_TIME 0 0x1035 2 0 0 WAIT_TIME 0 9 SCALE_COUNT 10 17 regCP_CPC_MGCG_SYNC_CNTL 0 0x1036 2 0 0 COOLDOWN_PERIOD 0 7 WARMUP_PERIOD 8 15 regCPC_INT_INFO 0 0x1037 4 0 0 ADDR_HI 0 15 TYPE 16 16 VMID 20 23 QUEUE_ID 28 30 regCP_VIRT_STATUS 0 0x1038 1 0 0 VIRT_STATUS 0 31 regCPC_INT_ADDR 0 0x1039 1 0 0 ADDR 0 31 regCPC_INT_PASID 0 0x103a 1 0 0 PASID 0 15 regCP_GFX_ERROR 0 0x103b 29 0 0 EDC_ERROR_ID 0 3 SUA_ERROR 4 4 RSVD1_ERROR 5 5 RSVD2_ERROR 6 6 SEM_UTCL1_ERROR 7 7 QU_STRM_UTCL1_ERROR 8 8 QU_EOP_UTCL1_ERROR 9 9 QU_PIPE_UTCL1_ERROR 10 10 QU_READ_UTCL1_ERROR 11 11 SYNC_MEMRD_UTCL1_ERROR 12 12 SYNC_MEMWR_UTCL1_ERROR 13 13 SHADOW_UTCL1_ERROR 14 14 APPEND_UTCL1_ERROR 15 15 CE_DMA_UTCL1_ERROR 16 16 PFP_VGTDMA_UTCL1_ERROR 17 17 DMA_SRC_UTCL1_ERROR 18 18 DMA_DST_UTCL1_ERROR 19 19 PFP_TC_UTCL1_ERROR 20 20 ME_TC_UTCL1_ERROR 21 21 CE_TC_UTCL1_ERROR 22 22 PRT_LOD_UTCL1_ERROR 23 23 RDPTR_RPT_UTCL1_ERROR 24 24 RB_FETCHER_UTCL1_ERROR 25 25 I1_FETCHER_UTCL1_ERROR 26 26 I2_FETCHER_UTCL1_ERROR 27 27 C1_FETCHER_UTCL1_ERROR 28 28 C2_FETCHER_UTCL1_ERROR 29 29 ST_FETCHER_UTCL1_ERROR 30 30 CE_INIT_UTCL1_ERROR 31 31 regCPG_UTCL1_CNTL 0 0x103c 9 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 MTYPE_NO_PTE_MODE 30 30 regCPC_UTCL1_CNTL 0 0x103d 8 0 0 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 MTYPE_NO_PTE_MODE 30 30 regCPF_UTCL1_CNTL 0 0x103e 10 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 MTYPE_NO_PTE_MODE 30 30 FORCE_NO_EXE 31 31 regCP_AQL_SMM_STATUS 0 0x103f 1 0 0 AQL_QUEUE_SMM 0 31 regCP_RB0_BASE 0 0x1040 1 0 0 RB_BASE 0 31 regCP_RB_BASE 0 0x1040 1 0 0 RB_BASE 0 31 regCP_RB0_CNTL 0 0x1041 8 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 BUF_SWAP 17 18 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 24 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 regCP_RB_CNTL 0 0x1041 7 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 24 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 regCP_RB_RPTR_WR 0 0x1042 1 0 0 RB_RPTR_WR 0 19 regCP_RB0_RPTR_ADDR 0 0x1043 1 0 0 RB_RPTR_ADDR 2 31 regCP_RB_RPTR_ADDR 0 0x1043 1 0 0 RB_RPTR_ADDR 2 31 regCP_RB0_RPTR_ADDR_HI 0 0x1044 1 0 0 RB_RPTR_ADDR_HI 0 15 regCP_RB_RPTR_ADDR_HI 0 0x1044 1 0 0 RB_RPTR_ADDR_HI 0 15 regCP_RB0_BUFSZ_MASK 0 0x1045 1 0 0 DATA 0 19 regCP_RB_BUFSZ_MASK 0 0x1045 1 0 0 DATA 0 19 regCP_RB_WPTR_POLL_ADDR_LO 0 0x1046 1 0 0 RB_WPTR_POLL_ADDR_LO 2 31 regCP_RB_WPTR_POLL_ADDR_HI 0 0x1047 1 0 0 RB_WPTR_POLL_ADDR_HI 0 15 regCP_INT_CNTL 0 0x1049 16 0 0 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_INT_STATUS 0 0x104a 16 0 0 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 regCP_DEVICE_ID 0 0x104b 1 0 0 DEVICE_ID 0 7 regCP_ME0_PIPE_PRIORITY_CNTS 0 0x104c 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 regCP_RING_PRIORITY_CNTS 0 0x104c 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 regCP_ME0_PIPE0_PRIORITY 0 0x104d 1 0 0 PRIORITY 0 1 regCP_RING0_PRIORITY 0 0x104d 1 0 0 PRIORITY 0 1 regCP_ME0_PIPE1_PRIORITY 0 0x104e 1 0 0 PRIORITY 0 1 regCP_RING1_PRIORITY 0 0x104e 1 0 0 PRIORITY 0 1 regCP_ME0_PIPE2_PRIORITY 0 0x104f 1 0 0 PRIORITY 0 1 regCP_RING2_PRIORITY 0 0x104f 1 0 0 PRIORITY 0 1 regCP_FATAL_ERROR 0 0x1050 5 0 0 CPF_FATAL_ERROR 0 0 CPG_FATAL_ERROR 1 1 GFX_HALT_PROC 2 2 DIS_CPG_FATAL_ERROR 3 3 CPG_TAG_FATAL_ERROR_EN 4 4 regCP_RB_VMID 0 0x1051 3 0 0 RB0_VMID 0 3 RB1_VMID 8 11 RB2_VMID 16 19 regCP_ME0_PIPE0_VMID 0 0x1052 1 0 0 VMID 0 3 regCP_ME0_PIPE1_VMID 0 0x1053 1 0 0 VMID 0 3 regCP_RB0_WPTR 0 0x1054 1 0 0 RB_WPTR 0 31 regCP_RB_WPTR 0 0x1054 1 0 0 RB_WPTR 0 31 regCP_RB0_WPTR_HI 0 0x1055 1 0 0 RB_WPTR 0 31 regCP_RB_WPTR_HI 0 0x1055 1 0 0 RB_WPTR 0 31 regCP_RB1_WPTR 0 0x1056 1 0 0 RB_WPTR 0 31 regCP_RB1_WPTR_HI 0 0x1057 1 0 0 RB_WPTR 0 31 regCP_RB2_WPTR 0 0x1058 1 0 0 RB_WPTR 0 19 regCP_RB_DOORBELL_CONTROL 0 0x1059 4 0 0 DOORBELL_BIF_DROP 1 1 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_RANGE_LOWER 0 0x105a 1 0 0 DOORBELL_RANGE_LOWER 2 27 regCP_RB_DOORBELL_RANGE_UPPER 0 0x105b 1 0 0 DOORBELL_RANGE_UPPER 2 27 regCP_MEC_DOORBELL_RANGE_LOWER 0 0x105c 1 0 0 DOORBELL_RANGE_LOWER 2 27 regCP_MEC_DOORBELL_RANGE_UPPER 0 0x105d 1 0 0 DOORBELL_RANGE_UPPER 2 27 regCPG_UTCL1_ERROR 0 0x105e 1 0 0 ERROR_DETECTED_HALT 0 0 regCPC_UTCL1_ERROR 0 0x105f 1 0 0 ERROR_DETECTED_HALT 0 0 regCP_RB1_BASE 0 0x1060 1 0 0 RB_BASE 0 31 regCP_RB1_CNTL 0 0x1061 7 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 24 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 regCP_RB1_RPTR_ADDR 0 0x1062 1 0 0 RB_RPTR_ADDR 2 31 regCP_RB1_RPTR_ADDR_HI 0 0x1063 1 0 0 RB_RPTR_ADDR_HI 0 15 regCP_RB2_BASE 0 0x1065 1 0 0 RB_BASE 0 31 regCP_RB2_CNTL 0 0x1066 7 0 0 RB_BUFSZ 0 5 RB_BLKSZ 8 13 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 24 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 regCP_RB2_RPTR_ADDR 0 0x1067 1 0 0 RB_RPTR_ADDR 2 31 regCP_RB2_RPTR_ADDR_HI 0 0x1068 1 0 0 RB_RPTR_ADDR_HI 0 15 regCP_RB0_ACTIVE 0 0x1069 1 0 0 ACTIVE 0 0 regCP_RB_ACTIVE 0 0x1069 1 0 0 ACTIVE 0 0 regCP_INT_CNTL_RING0 0 0x106a 16 0 0 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_INT_CNTL_RING1 0 0x106b 16 0 0 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_INT_CNTL_RING2 0 0x106c 16 0 0 CP_VM_DOORBELL_WR_INT_ENABLE 11 11 CP_ECC_ERROR_INT_ENABLE 14 14 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CMP_BUSY_INT_ENABLE 18 18 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 GFX_IDLE_INT_ENABLE 21 21 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_INT_STATUS_RING0 0 0x106d 16 0 0 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 GCNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 regCP_INT_STATUS_RING1 0 0x106e 16 0 0 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 regCP_INT_STATUS_RING2 0 0x106f 16 0 0 CP_VM_DOORBELL_WR_INT_STAT 11 11 CP_ECC_ERROR_INT_STAT 14 14 GPF_INT_STAT 16 16 WRM_POLL_TIMEOUT_INT_STAT 17 17 CMP_BUSY_INT_STAT 18 18 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 GFX_IDLE_INT_STAT 21 21 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 regCP_ME_F32_INTERRUPT 0 0x1073 4 0 0 ECC_ERROR_INT 0 0 TIME_STAMP_INT 1 1 ME_F32_INT_2 2 2 ME_F32_INT_3 3 3 regCP_PFP_F32_INTERRUPT 0 0x1074 4 0 0 ECC_ERROR_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 PFP_F32_INT_3 3 3 regCP_CE_F32_INTERRUPT 0 0x1075 4 0 0 ECC_ERROR_INT 0 0 RESERVED_BIT_ERR_INT 1 1 CE_F32_INT_2 2 2 CE_F32_INT_3 3 3 regCP_MEC1_F32_INTERRUPT 0 0x1076 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 regCP_MEC2_F32_INTERRUPT 0 0x1077 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 regCP_PWR_CNTL 0 0x1078 10 0 0 GFX_CLK_HALT_ME0_PIPE0 0 0 GFX_CLK_HALT_ME0_PIPE1 1 1 CMP_CLK_HALT_ME1_PIPE0 8 8 CMP_CLK_HALT_ME1_PIPE1 9 9 CMP_CLK_HALT_ME1_PIPE2 10 10 CMP_CLK_HALT_ME1_PIPE3 11 11 CMP_CLK_HALT_ME2_PIPE0 16 16 CMP_CLK_HALT_ME2_PIPE1 17 17 CMP_CLK_HALT_ME2_PIPE2 18 18 CMP_CLK_HALT_ME2_PIPE3 19 19 regCP_MEM_SLP_CNTL 0 0x1079 7 0 0 CP_MEM_LS_EN 0 0 CP_MEM_DS_EN 1 1 RESERVED 2 6 CP_LS_DS_BUSY_OVERRIDE 7 7 CP_MEM_LS_ON_DELAY 8 15 CP_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 regCP_ECC_DMA_FIRST_OCCURRENCE 0 0x107a 6 0 0 INTERFACE 0 1 CLIENT 4 7 ME 8 9 PIPE 10 11 QUEUE 12 14 VMID 16 19 regCP_ECC_FIRSTOCCURRENCE 0 0x107a 6 0 0 INTERFACE 0 1 CLIENT 4 7 ME 8 9 PIPE 10 11 QUEUE 12 14 VMID 16 19 regCP_ECC_FIRSTOCCURRENCE_RING0 0 0x107b 1 0 0 OBSOLETE 0 31 regCP_ECC_FIRSTOCCURRENCE_RING1 0 0x107c 1 0 0 OBSOLETE 0 31 regCP_ECC_FIRSTOCCURRENCE_RING2 0 0x107d 1 0 0 OBSOLETE 0 31 regGB_EDC_MODE 0 0x107e 6 0 0 FORCE_SEC_ON_DED 15 15 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regCP_PQ_WPTR_POLL_CNTL 0 0x1083 4 0 0 PERIOD 0 7 DISABLE_PEND_REQ_ONE_SHOT 29 29 POLL_ACTIVE 30 30 EN 31 31 regCP_PQ_WPTR_POLL_CNTL1 0 0x1084 1 0 0 QUEUE_MASK 0 31 regCP_ME1_PIPE0_INT_CNTL 0 0x1085 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME1_PIPE1_INT_CNTL 0 0x1086 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME1_PIPE2_INT_CNTL 0 0x1087 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME1_PIPE3_INT_CNTL 0 0x1088 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME2_PIPE0_INT_CNTL 0 0x1089 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME2_PIPE1_INT_CNTL 0 0x108a 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME2_PIPE2_INT_CNTL 0 0x108b 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME2_PIPE3_INT_CNTL 0 0x108c 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCP_ME1_PIPE0_INT_STATUS 0 0x108d 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME1_PIPE1_INT_STATUS 0 0x108e 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME1_PIPE2_INT_STATUS 0 0x108f 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME1_PIPE3_INT_STATUS 0 0x1090 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME2_PIPE0_INT_STATUS 0 0x1091 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME2_PIPE1_INT_STATUS 0 0x1092 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME2_PIPE2_INT_STATUS 0 0x1093 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME2_PIPE3_INT_STATUS 0 0x1094 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_ME1_INT_STAT_DEBUG 0 0x1095 13 0 0 CMP_QUERY_STATUS_INT_ASSERTED 12 12 DEQUEUE_REQUEST_INT_ASSERTED 13 13 CP_ECC_ERROR_INT_ASSERTED 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_ASSERTED 16 16 WRM_POLL_TIMEOUT_INT_ASSERTED 17 17 PRIV_REG_INT_ASSERTED 23 23 OPCODE_ERROR_INT_ASSERTED 24 24 TIME_STAMP_INT_ASSERTED 26 26 RESERVED_BIT_ERROR_INT_ASSERTED 27 27 GENERIC2_INT_ASSERTED 29 29 GENERIC1_INT_ASSERTED 30 30 GENERIC0_INT_ASSERTED 31 31 regCP_ME2_INT_STAT_DEBUG 0 0x1096 13 0 0 CMP_QUERY_STATUS_INT_ASSERTED 12 12 DEQUEUE_REQUEST_INT_ASSERTED 13 13 CP_ECC_ERROR_INT_ASSERTED 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_ASSERTED 16 16 WRM_POLL_TIMEOUT_INT_ASSERTED 17 17 PRIV_REG_INT_ASSERTED 23 23 OPCODE_ERROR_INT_ASSERTED 24 24 TIME_STAMP_INT_ASSERTED 26 26 RESERVED_BIT_ERROR_INT_ASSERTED 27 27 GENERIC2_INT_ASSERTED 29 29 GENERIC1_INT_ASSERTED 30 30 GENERIC0_INT_ASSERTED 31 31 regCC_GC_EDC_CONFIG 0 0x1098 2 0 0 DIS_EDC 1 1 ENABLE_IRRITATOR_CLK 2 2 regCP_ME1_PIPE_PRIORITY_CNTS 0 0x1099 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 regCP_ME1_PIPE0_PRIORITY 0 0x109a 1 0 0 PRIORITY 0 1 regCP_ME1_PIPE1_PRIORITY 0 0x109b 1 0 0 PRIORITY 0 1 regCP_ME1_PIPE2_PRIORITY 0 0x109c 1 0 0 PRIORITY 0 1 regCP_ME1_PIPE3_PRIORITY 0 0x109d 1 0 0 PRIORITY 0 1 regCP_ME2_PIPE_PRIORITY_CNTS 0 0x109e 4 0 0 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 regCP_ME2_PIPE0_PRIORITY 0 0x109f 1 0 0 PRIORITY 0 1 regCP_ME2_PIPE1_PRIORITY 0 0x10a0 1 0 0 PRIORITY 0 1 regCP_ME2_PIPE2_PRIORITY 0 0x10a1 1 0 0 PRIORITY 0 1 regCP_ME2_PIPE3_PRIORITY 0 0x10a2 1 0 0 PRIORITY 0 1 regCP_CE_PRGRM_CNTR_START 0 0x10a3 1 0 0 IP_START 0 10 regCP_PFP_PRGRM_CNTR_START 0 0x10a4 1 0 0 IP_START 0 12 regCP_ME_PRGRM_CNTR_START 0 0x10a5 1 0 0 IP_START 0 11 regCP_MEC1_PRGRM_CNTR_START 0 0x10a6 1 0 0 IP_START 0 15 regCP_MEC2_PRGRM_CNTR_START 0 0x10a7 1 0 0 IP_START 0 15 regCP_CE_INTR_ROUTINE_START 0 0x10a8 1 0 0 IR_START 0 10 regCP_PFP_INTR_ROUTINE_START 0 0x10a9 1 0 0 IR_START 0 12 regCP_ME_INTR_ROUTINE_START 0 0x10aa 1 0 0 IR_START 0 11 regCP_MEC1_INTR_ROUTINE_START 0 0x10ab 1 0 0 IR_START 0 15 regCP_MEC2_INTR_ROUTINE_START 0 0x10ac 1 0 0 IR_START 0 15 regCP_CONTEXT_CNTL 0 0x10ad 4 0 0 ME0PIPE0_MAX_WD_CNTX 0 2 ME0PIPE0_MAX_PIPE_CNTX 4 6 ME0PIPE1_MAX_WD_CNTX 16 18 ME0PIPE1_MAX_PIPE_CNTX 20 22 regCP_MAX_CONTEXT 0 0x10ae 1 0 0 MAX_CONTEXT 0 2 regCP_IQ_WAIT_TIME1 0 0x10af 4 0 0 IB_OFFLOAD 0 7 ATOMIC_OFFLOAD 8 15 WRM_OFFLOAD 16 23 GWS 24 31 regCP_IQ_WAIT_TIME2 0 0x10b0 4 0 0 QUE_SLEEP 0 7 SCH_WAVE 8 15 SEM_REARM 16 23 DEQ_RETRY 24 31 regCP_RB0_BASE_HI 0 0x10b1 1 0 0 RB_BASE_HI 0 7 regCP_RB1_BASE_HI 0 0x10b2 1 0 0 RB_BASE_HI 0 7 regCP_VMID_RESET 0 0x10b3 1 0 0 RESET_REQUEST 0 15 regCPC_INT_CNTL 0 0x10b4 13 0 0 CMP_QUERY_STATUS_INT_ENABLE 12 12 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 SUA_VIOLATION_INT_ENABLE 15 15 GPF_INT_ENABLE 16 16 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 regCPC_INT_STATUS 0 0x10b5 13 0 0 CMP_QUERY_STATUS_INT_STATUS 12 12 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 SUA_VIOLATION_INT_STATUS 15 15 GPF_INT_STATUS 16 16 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 regCP_VMID_PREEMPT 0 0x10b6 2 0 0 PREEMPT_REQUEST 0 15 VIRT_COMMAND 16 19 regCPC_INT_CNTX_ID 0 0x10b7 1 0 0 CNTX_ID 0 31 regCP_PQ_STATUS 0 0x10b8 2 0 0 DOORBELL_UPDATED 0 0 DOORBELL_ENABLE 1 1 regCP_CPC_IC_BASE_LO 0 0x10b9 1 0 0 IC_BASE_LO 12 31 regCP_CPC_IC_BASE_HI 0 0x10ba 1 0 0 IC_BASE_HI 0 15 regCP_CPC_IC_BASE_CNTL 0 0x10bb 2 0 0 VMID 0 3 CACHE_POLICY 24 24 regCP_CPC_IC_OP_CNTL 0 0x10bc 4 0 0 INVALIDATE_CACHE 0 0 PRIME_ICACHE 4 4 ICACHE_PRIMED 5 5 ICACHE_INVALIDATED 6 6 regCP_MEC1_F32_INT_DIS 0 0x10bd 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 regCP_MEC2_F32_INT_DIS 0 0x10be 16 0 0 EDC_ROQ_FED_INT 0 0 PRIV_REG_INT 1 1 RESERVED_BIT_ERR_INT 2 2 EDC_TC_FED_INT 3 3 EDC_GDS_FED_INT 4 4 EDC_SCRATCH_FED_INT 5 5 WAVE_RESTORE_INT 6 6 SUA_VIOLATION_INT 7 7 EDC_DMA_FED_INT 8 8 IQ_TIMER_INT 9 9 GPF_INT_CPF 10 10 GPF_INT_DMA 11 11 GPF_INT_CPC 12 12 EDC_SR_MEM_FED_INT 13 13 QUEUE_MESSAGE_INT 14 14 FATAL_EDC_ERROR_INT 15 15 regCP_VMID_STATUS 0 0x10bf 2 0 0 PREEMPT_DE_STATUS 0 15 PREEMPT_CE_STATUS 16 31 regCP_RB_DOORBELL_CONTROL_SCH_0 0 0x1180 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_1 0 0x1181 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_2 0 0x1182 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_3 0 0x1183 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_4 0 0x1184 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_5 0 0x1185 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_6 0 0x1186 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CONTROL_SCH_7 0 0x1187 3 0 0 DOORBELL_OFFSET 2 27 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_RB_DOORBELL_CLEAR 0 0x1188 7 0 0 MAPPED_QUEUE 0 2 MAPPED_QUE_DOORBELL_EN_CLEAR 8 8 MAPPED_QUE_DOORBELL_HIT_CLEAR 9 9 MASTER_DOORBELL_EN_CLEAR 10 10 MASTER_DOORBELL_HIT_CLEAR 11 11 QUEUES_DOORBELL_EN_CLEAR 12 12 QUEUES_DOORBELL_HIT_CLEAR 13 13 regCPF_EDC_TAG_CNT 0 0x1189 2 0 0 DED_COUNT 0 1 SEC_COUNT 2 3 regCPF_EDC_ROQ_CNT 0 0x118a 4 0 0 DED_COUNT_ME1 0 1 SEC_COUNT_ME1 2 3 DED_COUNT_ME2 4 5 SEC_COUNT_ME2 6 7 regCPG_EDC_TAG_CNT 0 0x118b 2 0 0 DED_COUNT 0 1 SEC_COUNT 2 3 regCPG_EDC_DMA_CNT 0 0x118d 4 0 0 ROQ_DED_COUNT 0 1 ROQ_SEC_COUNT 2 3 TAG_DED_COUNT 4 5 TAG_SEC_COUNT 6 7 regCPC_EDC_SCRATCH_CNT 0 0x118e 2 0 0 DED_COUNT 0 1 SEC_COUNT 2 3 regCPC_EDC_UCODE_CNT 0 0x118f 2 0 0 DED_COUNT 0 1 SEC_COUNT 2 3 regDC_EDC_STATE_CNT 0 0x1191 2 0 0 DED_COUNT_ME1 0 1 SEC_COUNT_ME1 2 3 regDC_EDC_CSINVOC_CNT 0 0x1192 4 0 0 DED_COUNT_ME1 0 1 SEC_COUNT_ME1 2 3 DED_COUNT1_ME1 4 5 SEC_COUNT1_ME1 6 7 regDC_EDC_RESTORE_CNT 0 0x1193 4 0 0 DED_COUNT_ME1 0 1 SEC_COUNT_ME1 2 3 DED_COUNT1_ME1 4 5 SEC_COUNT1_ME1 6 7 regCP_CPF_DSM_CNTL 0 0x1194 6 0 0 CPF0_DSM_IRRITATOR_DATA 0 1 CPF0_ENABLE_SINGLE_WRITE 2 2 CPF1_DSM_IRRITATOR_DATA 3 4 CPF1_ENABLE_SINGLE_WRITE 5 5 CPF2_DSM_IRRITATOR_DATA 6 7 CPF2_ENABLE_SINGLE_WRITE 8 8 regCP_CPG_DSM_CNTL 0 0x1195 6 0 0 CPG0_DSM_IRRITATOR_DATA 0 1 CPG0_ENABLE_SINGLE_WRITE 2 2 CPG1_DSM_IRRITATOR_DATA 3 4 CPG1_ENABLE_SINGLE_WRITE 5 5 CPG2_DSM_IRRITATOR_DATA 6 7 CPG2_ENABLE_SINGLE_WRITE 8 8 regCP_CPC_DSM_CNTL 0 0x1196 18 0 0 CPC0_DSM_IRRITATOR_DATA 0 1 CPC0_ENABLE_SINGLE_WRITE 2 2 CPC1_DSM_IRRITATOR_DATA 3 4 CPC1_ENABLE_SINGLE_WRITE 5 5 CPC2_DSM_IRRITATOR_DATA 6 7 CPC2_ENABLE_SINGLE_WRITE 8 8 CPC3_DSM_IRRITATOR_DATA 9 10 CPC3_ENABLE_SINGLE_WRITE 11 11 CPC4_DSM_IRRITATOR_DATA 12 13 CPC4_ENABLE_SINGLE_WRITE 14 14 CPC5_DSM_IRRITATOR_DATA 15 16 CPC5_ENABLE_SINGLE_WRITE 17 17 CPC6_DSM_IRRITATOR_DATA 18 19 CPC6_ENABLE_SINGLE_WRITE 20 20 CPC7_DSM_IRRITATOR_DATA 21 22 CPC7_ENABLE_SINGLE_WRITE 23 23 CPC8_DSM_IRRITATOR_DATA 24 25 CPC8_ENABLE_SINGLE_WRITE 26 26 regCP_CPF_DSM_CNTL2 0 0x1197 6 0 0 CPF0_ENABLE_ERROR_INJECT 0 1 CPF0_SELECT_INJECT_DELAY 2 2 CPF1_ENABLE_ERROR_INJECT 3 4 CPF1_SELECT_INJECT_DELAY 5 5 CPF2_ENABLE_ERROR_INJECT 6 7 CPF2_SELECT_INJECT_DELAY 8 8 regCP_CPG_DSM_CNTL2 0 0x1198 6 0 0 CPG0_ENABLE_ERROR_INJECT 0 1 CPG0_SELECT_INJECT_DELAY 2 2 CPG1_ENABLE_ERROR_INJECT 3 4 CPG1_SELECT_INJECT_DELAY 5 5 CPG2_ENABLE_ERROR_INJECT 6 7 CPG2_SELECT_INJECT_DELAY 8 8 regCP_CPC_DSM_CNTL2 0 0x1199 18 0 0 CPC0_ENABLE_ERROR_INJECT 0 1 CPC0_SELECT_INJECT_DELAY 2 2 CPC1_ENABLE_ERROR_INJECT 3 4 CPC1_SELECT_INJECT_DELAY 5 5 CPC2_ENABLE_ERROR_INJECT 6 7 CPC2_SELECT_INJECT_DELAY 8 8 CPC3_ENABLE_ERROR_INJECT 9 10 CPC3_SELECT_INJECT_DELAY 11 11 CPC4_ENABLE_ERROR_INJECT 12 13 CPC4_SELECT_INJECT_DELAY 14 14 CPC5_ENABLE_ERROR_INJECT 15 16 CPC5_SELECT_INJECT_DELAY 17 17 CPC6_ENABLE_ERROR_INJECT 18 19 CPC6_SELECT_INJECT_DELAY 20 20 CPC7_ENABLE_ERROR_INJECT 21 22 CPC7_SELECT_INJECT_DELAY 23 23 CPC8_ENABLE_ERROR_INJECT 24 25 CPC8_SELECT_INJECT_DELAY 26 26 regCP_CPF_DSM_CNTL2A 0 0x119a 1 0 0 CPF_INJECT_DELAY 0 5 regCP_CPG_DSM_CNTL2A 0 0x119b 1 0 0 CPG_INJECT_DELAY 0 5 regCP_CPC_DSM_CNTL2A 0 0x119c 1 0 0 CPC_INJECT_DELAY 0 5 regCP_EDC_FUE_CNTL 0 0x119d 16 0 0 CP_FUE_MASK 0 0 SPI_FUE_MASK 1 1 GDS_FUE_MASK 2 2 TC_RLC_FUE_MASK 3 3 TC_CPG_FUE_MASK 4 4 TCA_FUE_MASK 5 5 TCC_FUE_MASK 6 6 UTCL2_FUE_MASK 7 7 CP_FUE_FLAG 16 16 SPI_FUE_FLAG 17 17 GDS_FUE_FLAG 18 18 TC_RLC_FUE_FLAG 19 19 TC_CPG_FUE_FLAG 20 20 TCA_FUE_FLAG 21 21 TCC_FUE_FLAG 22 22 UTCL2_FUE_FLAG 23 23 regCP_GFX_MQD_CONTROL 0 0x11a0 4 0 0 VMID 0 3 PRIV_STATE 8 8 EXE_DISABLE 23 23 CACHE_POLICY 24 24 regCP_GFX_MQD_BASE_ADDR 0 0x11a1 1 0 0 BASE_ADDR 2 31 regCP_GFX_MQD_BASE_ADDR_HI 0 0x11a2 1 0 0 BASE_ADDR_HI 0 15 regCP_RB_STATUS 0 0x11a3 2 0 0 DOORBELL_UPDATED 0 0 DOORBELL_ENABLE 1 1 regCPG_UTCL1_STATUS 0 0x11b4 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 regCPC_UTCL1_STATUS 0 0x11b5 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 regCPF_UTCL1_STATUS 0 0x11b6 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 regCP_SD_CNTL 0 0x11b7 10 0 0 CPF_EN 0 0 CPG_EN 1 1 CPC_EN 2 2 RLC_EN 3 3 SPI_EN 4 4 WD_EN 5 5 IA_EN 6 6 PA_EN 7 7 RMI_EN 8 8 EA_EN 9 9 regCP_SOFT_RESET_CNTL 0 0x11b9 7 0 0 CMP_ONLY_SOFT_RESET 0 0 GFX_ONLY_SOFT_RESET 1 1 CMP_HQD_REG_RESET 2 2 CMP_INTR_REG_RESET 3 3 CMP_HQD_QUEUE_DOORBELL_RESET 4 4 GFX_RB_DOORBELL_RESET 5 5 GFX_INTR_REG_RESET 6 6 regCP_CPC_GFX_CNTL 0 0x11ba 4 0 0 QUEUEID 0 2 PIPEID 3 4 MEID 5 6 VALID 7 7 regCP_HQD_GFX_CONTROL 0 0x123e 3 0 0 MESSAGE 0 3 MISC 4 14 DB_UPDATED_MSG_EN 15 15 regCP_HQD_GFX_STATUS 0 0x123f 1 0 0 STATUS 0 15 regCP_HPD_ROQ_OFFSETS 0 0x1240 3 0 0 IQ_OFFSET 0 2 PQ_OFFSET 8 13 IB_OFFSET 16 21 regCP_HPD_STATUS0 0 0x1241 8 0 0 QUEUE_STATE 0 4 MAPPED_QUEUE 5 7 QUEUE_AVAILABLE 8 15 FETCHING_MQD 16 16 PEND_TXFER_SIZE_PQIB 17 17 PEND_TXFER_SIZE_IQ 18 18 FORCE_QUEUE_STATE 20 24 FORCE_QUEUE 31 31 regCP_HPD_UTCL1_CNTL 0 0x1242 1 0 0 SELECT 0 3 regCP_HPD_UTCL1_ERROR 0 0x1243 3 0 0 ADDR_HI 0 15 TYPE 16 16 VMID 20 23 regCP_HPD_UTCL1_ERROR_ADDR 0 0x1244 1 0 0 ADDR 12 31 regCP_MQD_BASE_ADDR 0 0x1245 1 0 0 BASE_ADDR 2 31 regCP_MQD_BASE_ADDR_HI 0 0x1246 1 0 0 BASE_ADDR_HI 0 15 regCP_HQD_ACTIVE 0 0x1247 2 0 0 ACTIVE 0 0 BUSY_GATE 1 1 regCP_HQD_VMID 0 0x1248 3 0 0 VMID 0 3 IB_VMID 8 11 VQID 16 25 regCP_HQD_PERSISTENT_STATE 0 0x1249 13 0 0 PRELOAD_REQ 0 0 PRELOAD_SIZE 8 17 WPP_SWITCH_QOS_EN 21 21 IQ_SWITCH_QOS_EN 22 22 IB_SWITCH_QOS_EN 23 23 EOP_SWITCH_QOS_EN 24 24 PQ_SWITCH_QOS_EN 25 25 TC_OFFLOAD_QOS_EN 26 26 CACHE_FULL_PACKET_EN 27 27 RESTORE_ACTIVE 28 28 RELAUNCH_WAVES 29 29 QSWITCH_MODE 30 30 DISP_ACTIVE 31 31 regCP_HQD_PIPE_PRIORITY 0 0x124a 1 0 0 PIPE_PRIORITY 0 1 regCP_HQD_QUEUE_PRIORITY 0 0x124b 1 0 0 PRIORITY_LEVEL 0 3 regCP_HQD_QUANTUM 0 0x124c 4 0 0 QUANTUM_EN 0 0 QUANTUM_SCALE 4 4 QUANTUM_DURATION 8 13 QUANTUM_ACTIVE 31 31 regCP_HQD_PQ_BASE 0 0x124d 1 0 0 ADDR 0 31 regCP_HQD_PQ_BASE_HI 0 0x124e 1 0 0 ADDR_HI 0 7 regCP_HQD_PQ_RPTR 0 0x124f 1 0 0 CONSUMED_OFFSET 0 31 regCP_HQD_PQ_RPTR_REPORT_ADDR 0 0x1250 1 0 0 RPTR_REPORT_ADDR 2 31 regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0 0x1251 1 0 0 RPTR_REPORT_ADDR_HI 0 15 regCP_HQD_PQ_WPTR_POLL_ADDR 0 0x1252 1 0 0 WPTR_ADDR 3 31 regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0 0x1253 1 0 0 WPTR_ADDR_HI 0 15 regCP_HQD_PQ_DOORBELL_CONTROL 0 0x1254 7 0 0 DOORBELL_MODE 0 0 DOORBELL_BIF_DROP 1 1 DOORBELL_OFFSET 2 27 DOORBELL_SOURCE 28 28 DOORBELL_SCHD_HIT 29 29 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 regCP_HQD_PQ_CONTROL 0 0x1256 18 0 0 QUEUE_SIZE 0 5 WPTR_CARRY 6 6 RPTR_CARRY 7 7 RPTR_BLOCK_SIZE 8 13 QUEUE_FULL_EN 14 14 PQ_EMPTY 15 15 WPP_CLAMP_EN 16 16 ENDIAN_SWAP 17 18 MIN_AVAIL_SIZE 20 21 TMZ 22 22 EXE_DISABLE 23 23 CACHE_POLICY 24 24 SLOT_BASED_WPTR 25 26 NO_UPDATE_RPTR 27 27 UNORD_DISPATCH 28 28 ROQ_PQ_IB_FLIP 29 29 PRIV_STATE 30 30 KMD_QUEUE 31 31 regCP_HQD_IB_BASE_ADDR 0 0x1257 1 0 0 IB_BASE_ADDR 2 31 regCP_HQD_IB_BASE_ADDR_HI 0 0x1258 1 0 0 IB_BASE_ADDR_HI 0 15 regCP_HQD_IB_RPTR 0 0x1259 1 0 0 CONSUMED_OFFSET 0 19 regCP_HQD_IB_CONTROL 0 0x125a 5 0 0 IB_SIZE 0 19 MIN_IB_AVAIL_SIZE 20 21 IB_EXE_DISABLE 23 23 IB_CACHE_POLICY 24 24 PROCESSING_IB 31 31 regCP_HQD_IQ_TIMER 0 0x125b 14 0 0 WAIT_TIME 0 7 RETRY_TYPE 8 10 IMMEDIATE_EXPIRE 11 11 INTERRUPT_TYPE 12 13 CLOCK_COUNT 14 15 INTERRUPT_SIZE 16 21 QUANTUM_TIMER 22 22 EXE_DISABLE 23 23 CACHE_POLICY 24 24 QUEUE_TYPE 25 25 REARM_TIMER 28 28 PROCESS_IQ_EN 29 29 PROCESSING_IQ 30 30 ACTIVE 31 31 regCP_HQD_IQ_RPTR 0 0x125c 1 0 0 OFFSET 0 5 regCP_HQD_DEQUEUE_REQUEST 0 0x125d 5 0 0 DEQUEUE_REQ 0 2 IQ_REQ_PEND 4 4 DEQUEUE_INT 8 8 IQ_REQ_PEND_EN 9 9 DEQUEUE_REQ_EN 10 10 regCP_HQD_DMA_OFFLOAD 0 0x125e 1 0 0 DMA_OFFLOAD 0 0 regCP_HQD_OFFLOAD 0 0x125e 6 0 0 DMA_OFFLOAD 0 0 DMA_OFFLOAD_EN 1 1 AQL_OFFLOAD 2 2 AQL_OFFLOAD_EN 3 3 EOP_OFFLOAD 4 4 EOP_OFFLOAD_EN 5 5 regCP_HQD_SEMA_CMD 0 0x125f 2 0 0 RETRY 0 0 RESULT 1 2 regCP_HQD_MSG_TYPE 0 0x1260 2 0 0 ACTION 0 2 SAVE_STATE 4 6 regCP_HQD_ATOMIC0_PREOP_LO 0 0x1261 1 0 0 ATOMIC0_PREOP_LO 0 31 regCP_HQD_ATOMIC0_PREOP_HI 0 0x1262 1 0 0 ATOMIC0_PREOP_HI 0 31 regCP_HQD_ATOMIC1_PREOP_LO 0 0x1263 1 0 0 ATOMIC1_PREOP_LO 0 31 regCP_HQD_ATOMIC1_PREOP_HI 0 0x1264 1 0 0 ATOMIC1_PREOP_HI 0 31 regCP_HQD_HQ_SCHEDULER0 0 0x1265 1 0 0 SCHEDULER 0 31 regCP_HQD_HQ_STATUS0 0 0x1265 9 0 0 DEQUEUE_STATUS 0 1 DEQUEUE_RETRY_CNT 2 3 RSV_6_4 4 6 SCRATCH_RAM_INIT 7 7 TCL2_DIRTY 8 8 PG_ACTIVATED 9 9 RSVR_29_10 10 29 QUEUE_IDLE 30 30 DB_UPDATED_MSG_EN 31 31 regCP_HQD_HQ_CONTROL0 0 0x1266 1 0 0 CONTROL 0 31 regCP_HQD_HQ_SCHEDULER1 0 0x1266 1 0 0 SCHEDULER 0 31 regCP_MQD_CONTROL 0 0x1267 6 0 0 VMID 0 3 PRIV_STATE 8 8 PROCESSING_MQD 12 12 PROCESSING_MQD_EN 13 13 EXE_DISABLE 23 23 CACHE_POLICY 24 24 regCP_HQD_HQ_STATUS1 0 0x1268 1 0 0 STATUS 0 31 regCP_HQD_HQ_CONTROL1 0 0x1269 1 0 0 CONTROL 0 31 regCP_HQD_EOP_BASE_ADDR 0 0x126a 1 0 0 BASE_ADDR 0 31 regCP_HQD_EOP_BASE_ADDR_HI 0 0x126b 1 0 0 BASE_ADDR_HI 0 7 regCP_HQD_EOP_CONTROL 0 0x126c 11 0 0 EOP_SIZE 0 5 PROCESSING_EOP 8 8 PROCESS_EOP_EN 12 12 PROCESSING_EOPIB 13 13 PROCESS_EOPIB_EN 14 14 HALT_FETCHER 21 21 HALT_FETCHER_EN 22 22 EXE_DISABLE 23 23 CACHE_POLICY 24 24 SIG_SEM_RESULT 29 30 PEND_SIG_SEM 31 31 regCP_HQD_EOP_RPTR 0 0x126d 5 0 0 RPTR 0 12 RESET_FETCHER 28 28 DEQUEUE_PEND 29 29 RPTR_EQ_CSMD_WPTR 30 30 INIT_FETCHER 31 31 regCP_HQD_EOP_WPTR 0 0x126e 3 0 0 WPTR 0 12 EOP_EMPTY 15 15 EOP_AVAIL 16 28 regCP_HQD_EOP_EVENTS 0 0x126f 2 0 0 EVENT_COUNT 0 11 CS_PARTIAL_FLUSH_PEND 16 16 regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0 0x1270 1 0 0 ADDR 12 31 regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0 0x1271 1 0 0 ADDR_HI 0 15 regCP_HQD_CTX_SAVE_CONTROL 0 0x1272 2 0 0 POLICY 3 3 EXE_DISABLE 23 23 regCP_HQD_CNTL_STACK_OFFSET 0 0x1273 1 0 0 OFFSET 2 15 regCP_HQD_CNTL_STACK_SIZE 0 0x1274 1 0 0 SIZE 12 15 regCP_HQD_WG_STATE_OFFSET 0 0x1275 1 0 0 OFFSET 2 26 regCP_HQD_CTX_SAVE_SIZE 0 0x1276 1 0 0 SIZE 12 26 regCP_HQD_GDS_RESOURCE_STATE 0 0x1277 4 0 0 OA_REQUIRED 0 0 OA_ACQUIRED 1 1 GWS_SIZE 4 9 GWS_PNTR 12 17 regCP_HQD_ERROR 0 0x1278 15 0 0 EDC_ERROR_ID 0 3 SUA_ERROR 4 4 AQL_ERROR 5 5 PQ_UTCL1_ERROR 8 8 IB_UTCL1_ERROR 9 9 EOP_UTCL1_ERROR 10 10 IQ_UTCL1_ERROR 11 11 RRPT_UTCL1_ERROR 12 12 WPP_UTCL1_ERROR 13 13 SEM_UTCL1_ERROR 14 14 DMA_SRC_UTCL1_ERROR 15 15 DMA_DST_UTCL1_ERROR 16 16 SR_UTCL1_ERROR 17 17 QU_UTCL1_ERROR 18 18 TC_UTCL1_ERROR 19 19 regCP_HQD_EOP_WPTR_MEM 0 0x1279 1 0 0 WPTR 0 12 regCP_HQD_AQL_CONTROL 0 0x127a 4 0 0 CONTROL0 0 14 CONTROL0_EN 15 15 CONTROL1 16 30 CONTROL1_EN 31 31 regCP_HQD_PQ_WPTR_LO 0 0x127b 1 0 0 OFFSET 0 31 regCP_HQD_PQ_WPTR_HI 0 0x127c 1 0 0 DATA 0 31 regDIDT_IND_INDEX 0 0x1280 1 0 0 DIDT_IND_INDEX 0 31 regDIDT_IND_DATA 0 0x1281 1 0 0 DIDT_IND_DATA 0 31 regDIDT_INDEX_AUTO_INCR_EN 0 0x1282 1 0 0 DIDT_INDEX_AUTO_INCR_EN 0 0 regGCEA_DRAM_RD_CLI2GRP_MAP0 0 0xa00 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regGCEA_DRAM_RD_CLI2GRP_MAP1 0 0xa01 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regGCEA_DRAM_WR_CLI2GRP_MAP0 0 0xa02 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regGCEA_DRAM_WR_CLI2GRP_MAP1 0 0xa03 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regGCEA_DRAM_RD_GRP2VC_MAP 0 0xa04 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regGCEA_DRAM_WR_GRP2VC_MAP 0 0xa05 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regGCEA_DRAM_RD_LAZY 0 0xa06 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regGCEA_DRAM_WR_LAZY 0 0xa07 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regGCEA_DRAM_RD_CAM_CNTL 0 0xa08 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regGCEA_DRAM_WR_CAM_CNTL 0 0xa09 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regGCEA_DRAM_PAGE_BURST 0 0xa0a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regGCEA_DRAM_RD_PRI_AGE 0 0xa0b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regGCEA_DRAM_WR_PRI_AGE 0 0xa0c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regGCEA_DRAM_RD_PRI_QUEUING 0 0xa0d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regGCEA_DRAM_WR_PRI_QUEUING 0 0xa0e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regGCEA_DRAM_RD_PRI_FIXED 0 0xa0f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regGCEA_DRAM_WR_PRI_FIXED 0 0xa10 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regGCEA_DRAM_RD_PRI_URGENCY 0 0xa11 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regGCEA_DRAM_WR_PRI_URGENCY 0 0xa12 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regGCEA_DRAM_RD_PRI_QUANT_PRI1 0 0xa13 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_DRAM_RD_PRI_QUANT_PRI2 0 0xa14 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_DRAM_RD_PRI_QUANT_PRI3 0 0xa15 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_DRAM_WR_PRI_QUANT_PRI1 0 0xa16 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_DRAM_WR_PRI_QUANT_PRI2 0 0xa17 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_DRAM_WR_PRI_QUANT_PRI3 0 0xa18 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_ADDRNORM_BASE_ADDR0 0 0xa34 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_LIMIT_ADDR0 0 0xa35 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORM_BASE_ADDR1 0 0xa36 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_LIMIT_ADDR1 0 0xa37 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORM_OFFSET_ADDR1 0 0xa38 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regGCEA_ADDRNORM_BASE_ADDR2 0 0xa39 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_LIMIT_ADDR2 0 0xa3a 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORM_BASE_ADDR3 0 0xa3b 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_LIMIT_ADDR3 0 0xa3c 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORM_OFFSET_ADDR3 0 0xa3d 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regGCEA_ADDRNORM_MEGABASE_ADDR0 0 0xa3e 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_MEGALIMIT_ADDR0 0 0xa3f 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORM_MEGABASE_ADDR1 0 0xa40 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regGCEA_ADDRNORM_MEGALIMIT_ADDR1 0 0xa41 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regGCEA_ADDRNORMDRAM_HOLE_CNTL 0 0xa43 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regGCEA_ADDRNORMGMI_HOLE_CNTL 0 0xa44 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0xa45 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regGCEA_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0xa46 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regGCEA_ADDRDEC_BANK_CFG 0 0xa47 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regGCEA_ADDRDEC_MISC_CFG 0 0xa48 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regGCEA_ADDRDECDRAM_HARVEST_ENABLE 0 0xa53 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regGCEA_ADDRDECGMI_HARVEST_ENABLE 0 0xa5e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regGCEA_ADDRDEC0_BASE_ADDR_CS0 0 0xa5f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_CS1 0 0xa60 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_CS2 0 0xa61 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_CS3 0 0xa62 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_SECCS0 0 0xa63 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_SECCS1 0 0xa64 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_SECCS2 0 0xa65 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_BASE_ADDR_SECCS3 0 0xa66 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC0_ADDR_MASK_CS01 0 0xa67 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC0_ADDR_MASK_CS23 0 0xa68 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC0_ADDR_MASK_SECCS01 0 0xa69 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC0_ADDR_MASK_SECCS23 0 0xa6a 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC0_ADDR_CFG_CS01 0 0xa6b 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC0_ADDR_CFG_CS23 0 0xa6c 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC0_ADDR_SEL_CS01 0 0xa6d 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC0_ADDR_SEL_CS23 0 0xa6e 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC0_ADDR_SEL2_CS01 0 0xa6f 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC0_ADDR_SEL2_CS23 0 0xa70 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC0_COL_SEL_LO_CS01 0 0xa71 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC0_COL_SEL_LO_CS23 0 0xa72 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC0_COL_SEL_HI_CS01 0 0xa73 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC0_COL_SEL_HI_CS23 0 0xa74 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC0_RM_SEL_CS01 0 0xa75 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC0_RM_SEL_CS23 0 0xa76 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC0_RM_SEL_SECCS01 0 0xa77 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC0_RM_SEL_SECCS23 0 0xa78 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC1_BASE_ADDR_CS0 0 0xa79 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_CS1 0 0xa7a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_CS2 0 0xa7b 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_CS3 0 0xa7c 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_SECCS0 0 0xa7d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_SECCS1 0 0xa7e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_SECCS2 0 0xa7f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_BASE_ADDR_SECCS3 0 0xa80 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC1_ADDR_MASK_CS01 0 0xa81 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC1_ADDR_MASK_CS23 0 0xa82 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC1_ADDR_MASK_SECCS01 0 0xa83 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC1_ADDR_MASK_SECCS23 0 0xa84 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC1_ADDR_CFG_CS01 0 0xa85 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC1_ADDR_CFG_CS23 0 0xa86 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC1_ADDR_SEL_CS01 0 0xa87 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC1_ADDR_SEL_CS23 0 0xa88 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC1_ADDR_SEL2_CS01 0 0xa89 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC1_ADDR_SEL2_CS23 0 0xa8a 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC1_COL_SEL_LO_CS01 0 0xa8b 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC1_COL_SEL_LO_CS23 0 0xa8c 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC1_COL_SEL_HI_CS01 0 0xa8d 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC1_COL_SEL_HI_CS23 0 0xa8e 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC1_RM_SEL_CS01 0 0xa8f 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC1_RM_SEL_CS23 0 0xa90 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC1_RM_SEL_SECCS01 0 0xa91 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC1_RM_SEL_SECCS23 0 0xa92 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC2_BASE_ADDR_CS0 0 0xa93 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_CS1 0 0xa94 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_CS2 0 0xa95 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_CS3 0 0xa96 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_SECCS0 0 0xa97 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_SECCS1 0 0xa98 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_SECCS2 0 0xa99 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_BASE_ADDR_SECCS3 0 0xa9a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regGCEA_ADDRDEC2_ADDR_MASK_CS01 0 0xa9b 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC2_ADDR_MASK_CS23 0 0xa9c 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC2_ADDR_MASK_SECCS01 0 0xa9d 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC2_ADDR_MASK_SECCS23 0 0xa9e 1 0 0 ADDR_MASK 1 31 regGCEA_ADDRDEC2_ADDR_CFG_CS01 0 0xa9f 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC2_ADDR_CFG_CS23 0 0xaa0 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regGCEA_ADDRDEC2_ADDR_SEL_CS01 0 0xaa1 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC2_ADDR_SEL_CS23 0 0xaa2 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regGCEA_ADDRDEC2_ADDR_SEL2_CS01 0 0xaa3 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC2_ADDR_SEL2_CS23 0 0xaa4 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regGCEA_ADDRDEC2_COL_SEL_LO_CS01 0 0xaa5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC2_COL_SEL_LO_CS23 0 0xaa6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regGCEA_ADDRDEC2_COL_SEL_HI_CS01 0 0xaa7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC2_COL_SEL_HI_CS23 0 0xaa8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regGCEA_ADDRDEC2_RM_SEL_CS01 0 0xaa9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC2_RM_SEL_CS23 0 0xaaa 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC2_RM_SEL_SECCS01 0 0xaab 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRDEC2_RM_SEL_SECCS23 0 0xaac 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regGCEA_ADDRNORMDRAM_GLOBAL_CNTL 0 0xaad 0 0 0 regGCEA_ADDRNORMGMI_GLOBAL_CNTL 0 0xaae 0 0 0 regGCEA_ADDRNORM_MEGACONTROL_ADDR0 0 0xad1 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regGCEA_ADDRNORM_MEGACONTROL_ADDR1 0 0xad2 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regGCEA_ADDRNORMDRAM_MASKING 0 0xad3 1 0 0 ADDRHI_MASK 0 11 regGCEA_ADDRNORMGMI_MASKING 0 0xad4 1 0 0 ADDRHI_MASK 0 11 regGCEA_IO_RD_CLI2GRP_MAP0 0 0xad5 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regGCEA_IO_RD_CLI2GRP_MAP1 0 0xad6 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regGCEA_IO_WR_CLI2GRP_MAP0 0 0xad7 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regGCEA_IO_WR_CLI2GRP_MAP1 0 0xad8 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regGCEA_IO_RD_COMBINE_FLUSH 0 0xad9 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regGCEA_IO_WR_COMBINE_FLUSH 0 0xada 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regGCEA_IO_GROUP_BURST 0 0xadb 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regGCEA_IO_RD_PRI_AGE 0 0xadc 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regGCEA_IO_WR_PRI_AGE 0 0xadd 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regGCEA_IO_RD_PRI_QUEUING 0 0xade 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regGCEA_IO_WR_PRI_QUEUING 0 0xadf 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regGCEA_IO_RD_PRI_FIXED 0 0xae0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regGCEA_IO_WR_PRI_FIXED 0 0xae1 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regGCEA_IO_RD_PRI_URGENCY 0 0xae2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regGCEA_IO_WR_PRI_URGENCY 0 0xae3 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regGCEA_IO_RD_PRI_URGENCY_MASKING 0 0xae4 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regGCEA_IO_WR_PRI_URGENCY_MASKING 0 0xae5 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regGCEA_IO_RD_PRI_QUANT_PRI1 0 0xae6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_IO_RD_PRI_QUANT_PRI2 0 0xae7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_IO_RD_PRI_QUANT_PRI3 0 0xae8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_IO_WR_PRI_QUANT_PRI1 0 0xae9 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_IO_WR_PRI_QUANT_PRI2 0 0xaea 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_IO_WR_PRI_QUANT_PRI3 0 0xaeb 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regGCEA_MISC 0 0xafa 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regGCEA_LATENCY_SAMPLING 0 0xafb 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regGCEA_PERFCOUNTER_LO 0 0xafc 1 0 0 COUNTER_LO 0 31 regGCEA_PERFCOUNTER_HI 0 0xafd 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regGCEA_PERFCOUNTER0_CFG 0 0xafe 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regGCEA_PERFCOUNTER1_CFG 0 0xaff 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regGCEA_PERFCOUNTER_RSLT_CNTL 0 0x700 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regGCEA_EDC_CNT 0 0x706 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regGCEA_EDC_CNT2 0 0x707 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regGCEA_DSM_CNTL 0 0x708 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regGCEA_DSM_CNTLA 0 0x709 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regGCEA_DSM_CNTLB 0 0x70a 0 0 0 regGCEA_DSM_CNTL2 0 0x70b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regGCEA_DSM_CNTL2A 0 0x70c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regGCEA_DSM_CNTL2B 0 0x70d 0 0 0 regGCEA_TCC_XBR_CREDITS 0 0x70e 8 0 0 DRAM_RD_LIMIT 0 5 DRAM_RD_RESERVE 6 7 IO_RD_LIMIT 8 13 IO_RD_RESERVE 14 15 DRAM_WR_LIMIT 16 21 DRAM_WR_RESERVE 22 23 IO_WR_LIMIT 24 29 IO_WR_RESERVE 30 31 regGCEA_TCC_XBR_MAXBURST 0 0x70f 4 0 0 DRAM_RD 0 3 IO_RD 4 7 DRAM_WR 8 11 IO_WR 12 15 regGCEA_PROBE_CNTL 0 0x710 2 0 0 REQ2RSP_DELAY 0 4 PRB_FILTER_DISABLE 5 5 regGCEA_PROBE_MAP 0 0x711 17 0 0 CHADDR0_TO_RIGHTTCC 0 0 CHADDR1_TO_RIGHTTCC 1 1 CHADDR2_TO_RIGHTTCC 2 2 CHADDR3_TO_RIGHTTCC 3 3 CHADDR4_TO_RIGHTTCC 4 4 CHADDR5_TO_RIGHTTCC 5 5 CHADDR6_TO_RIGHTTCC 6 6 CHADDR7_TO_RIGHTTCC 7 7 CHADDR8_TO_RIGHTTCC 8 8 CHADDR9_TO_RIGHTTCC 9 9 CHADDR10_TO_RIGHTTCC 10 10 CHADDR11_TO_RIGHTTCC 11 11 CHADDR12_TO_RIGHTTCC 12 12 CHADDR13_TO_RIGHTTCC 13 13 CHADDR14_TO_RIGHTTCC 14 14 CHADDR15_TO_RIGHTTCC 15 15 INTLV_SIZE 16 17 regGCEA_ERR_STATUS 0 0x712 11 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 regGCEA_MISC2 0 0x713 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 BLOCK_REQUESTS 13 13 REQUESTS_BLOCKED 14 14 FGCLKEN_OVERRIDE 15 15 regGCEA_DRAM_BANK_ARB 0 0x714 5 0 0 AGEBASED_BANKARB 0 0 BANK_STAY_AWAY_CYCLIM 1 8 BANK_STAY_AWAY_REQLIM 9 14 BANK_STAY_AWAY_STALLMODE 15 15 DISABLE_STALLMODE_FIX 16 16 regGCEA_ADDRDEC_SELECT 0 0x71a 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regGCEA_EDC_CNT3 0 0x71b 16 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 MAM_A0MEM_SEC_COUNT 12 13 MAM_A0MEM_DED_COUNT 14 15 MAM_A1MEM_SEC_COUNT 16 17 MAM_A1MEM_DED_COUNT 18 19 MAM_A2MEM_SEC_COUNT 20 21 MAM_A2MEM_DED_COUNT 22 23 MAM_A3MEM_SEC_COUNT 24 25 MAM_A3MEM_DED_COUNT 26 27 MAM_AFMEM_SEC_COUNT 28 29 MAM_AFMEM_DED_COUNT 30 31 regGCEA_CGTT_CLK_CTRL 0 0x50c4 11 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regGC_CAC_CTRL_1 0 0x1284 2 0 0 CAC_WINDOW 0 23 TDP_WINDOW 24 31 regGC_CAC_CTRL_2 0 0x1285 4 0 0 CAC_ENABLE 0 0 CAC_SOFT_CTRL_ENABLE 1 1 GC_LCAC_ENABLE 2 2 SE_LCAC_ENABLE 3 3 regGC_CAC_INDEX_AUTO_INCR_EN 0 0x1286 1 0 0 GC_CAC_INDEX_AUTO_INCR_EN 0 0 regGC_CAC_AGGR_LOWER 0 0x1287 1 0 0 AGGR_31_0 0 31 regGC_CAC_AGGR_UPPER 0 0x1288 1 0 0 AGGR_63_32 0 31 regGC_EDC_PERF_COUNTER 0 0x1289 1 0 0 EDC_PERF_COUNTER 0 31 regPCC_PERF_COUNTER 0 0x128a 1 0 0 PCC_PERF_COUNTER 0 31 regGC_CAC_SOFT_CTRL 0 0x128d 1 0 0 SOFT_SNAP 0 0 regGC_DIDT_CTRL0 0 0x128e 5 0 0 DIDT_CTRL_EN 0 0 PHASE_OFFSET 1 2 DIDT_SW_RST 3 3 DIDT_CLK_EN_OVERRIDE 4 4 DIDT_TRIGGER_THROTTLE_LOWBIT 5 8 regGC_DIDT_CTRL1 0 0x128f 2 0 0 MIN_POWER 0 15 MAX_POWER 16 31 regGC_DIDT_CTRL2 0 0x1290 3 0 0 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 regGC_DIDT_WEIGHT 0 0x1291 4 0 0 SQ_WEIGHT 0 7 DB_WEIGHT 8 15 TD_WEIGHT 16 23 TCP_WEIGHT 24 31 regGC_THROTTLE_CTRL1 0 0x1292 13 0 0 PCC_FP_PROGRAM_STEP_EN 0 0 PCC_PROGRAM_MIN_STEP 1 4 PCC_PROGRAM_MAX_STEP 5 9 PCC_PROGRAM_UPWARDS_STEP_SIZE 10 12 PATTERN_EXTEND_EN 13 13 PATTERN_EXTEND_MODE 14 16 FIXED_PATTERN_SELECT 17 18 FP_PATTERN_CLAMP_EN 19 19 PWRBRK_STALL_EN 20 20 PWRBRK_OVERRIDE 21 21 PWRBRK_POLARITY_CNTL 22 22 PWRBRK_PERF_COUNTER_EN 23 23 PWRBRK_PROGRAM_UPWARDS_STEP_SIZE 24 26 regGC_EDC_CTRL 0 0x1293 12 0 0 EDC_EN 0 0 EDC_SW_RST 1 1 EDC_CLK_EN_OVERRIDE 2 2 EDC_FORCE_STALL 3 3 EDC_TRIGGER_THROTTLE_LOWBIT 4 8 EDC_ALLOW_WRITE_PWRDELTA 9 9 GC_EDC_ONLY_MODE 11 11 EDC_THROTTLE_PATTERN_BIT_NUMS 12 15 PCC_THROTTLE_PATTERN_BIT_NUMS 16 19 RELEASE_STEP_INTERVAL 20 29 EDC_LEVEL_SEL 30 30 PCC_DITHER_MODE 31 31 regGC_EDC_THRESHOLD 0 0x1294 1 0 0 EDC_THRESHOLD 0 31 regGC_EDC_STATUS 0 0x1295 2 0 0 EDC_THROTTLE_LEVEL 0 2 THROTTLE_PATTERN_INDEX 3 8 regGC_EDC_OVERFLOW 0 0x1296 2 0 0 EDC_ROLLING_POWER_DELTA_OVERFLOW 0 0 EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER 1 16 regGC_EDC_ROLLING_POWER_DELTA 0 0x1297 1 0 0 EDC_ROLLING_POWER_DELTA 0 31 regGC_EDC_CTRL1 0 0x1298 9 0 0 PSM_THROTTLE_SRC_SEL 0 3 THROTTLE_SRC0_MASK 4 4 THROTTLE_SRC1_MASK 5 5 THROTTLE_SRC2_MASK 6 6 THROTTLE_SRC3_MASK 7 7 THROTTLE_SRC4_MASK 8 8 THROTTLE_SRC5_MASK 9 9 THROTTLE_SRC6_MASK 10 10 THROTTLE_SRC7_MASK 11 11 regGC_THROTTLE_CTRL2 0 0x1299 3 0 0 PWRBRK_FP_PROGRAM_STEP_EN 0 0 PWRBRK_PROGRAM_MIN_STEP 1 4 PWRBRK_PROGRAM_MAX_STEP 5 9 regPWRBRK_PERF_COUNTER 0 0x129a 1 0 0 PWRBRK_PERF_COUNTER 0 31 regGC_THROTTLE_CTRL 0 0x129b 14 0 0 THROTTLE_CTRL_SW_RST 0 0 GC_EDC_STALL_EN 1 1 PCC_STALL_EN 2 2 PATTERN_MODE 3 3 GC_EDC_OVERRIDE 4 4 NON_DITHER 5 5 PCC_OVERRIDE 7 7 GC_EDC_PERF_COUNTER_EN 8 8 PCC_PERF_COUNTER_EN 9 9 PCC_THROT_INCR_STEP_INTERVAL 10 19 PCC_FIXED_PATTERN_MIN 20 24 PCC_FIXED_PATTERN_MAX 25 29 INST_THROT_INCR 30 30 INST_THROT_DECR 31 31 regGC_CAC_IND_INDEX 0 0x129c 1 0 0 GC_CAC_IND_ADDR 0 31 regGC_CAC_IND_DATA 0 0x129d 1 0 0 GC_CAC_IND_DATA 0 31 regSE_CAC_IND_INDEX 0 0x129e 1 0 0 SE_CAC_IND_ADDR 0 31 regSE_CAC_IND_DATA 0 0x129f 1 0 0 SE_CAC_IND_DATA 0 31 regGDS_CONFIG 0 0x5c0 8 0 0 SH0_GPR_PHASE_SEL 1 2 SH1_GPR_PHASE_SEL 3 4 SH2_GPR_PHASE_SEL 5 6 SH3_GPR_PHASE_SEL 7 8 SH4_GPR_PHASE_SEL 9 10 SH5_GPR_PHASE_SEL 11 12 SH6_GPR_PHASE_SEL 13 14 SH7_GPR_PHASE_SEL 15 16 regGDS_CNTL_STATUS 0 0x5c1 19 0 0 GDS_BUSY 0 0 GRBM_WBUF_BUSY 1 1 ORD_APP_BUSY 2 2 DS_BANK_CONFLICT 3 3 DS_ADDR_CONFLICT 4 4 DS_WR_CLAMP 5 5 DS_RD_CLAMP 6 6 GRBM_RBUF_BUSY 7 7 DS_BUSY 8 8 GWS_BUSY 9 9 ORD_FIFO_BUSY 10 10 CREDIT_BUSY0 11 11 CREDIT_BUSY1 12 12 CREDIT_BUSY2 13 13 CREDIT_BUSY3 14 14 CREDIT_BUSY4 15 15 CREDIT_BUSY5 16 16 CREDIT_BUSY6 17 17 CREDIT_BUSY7 18 18 regGDS_ENHANCE2 0 0x5c2 5 0 0 MISC 0 15 GDS_TD_INTERFACES_FGCG_OVERRIDE 16 16 GDS_PHY_CMD_RAM_FGCG_OVERRIDE 17 17 GDS_FED_IN_PROPAGATE 18 18 UNUSED 19 31 regGDS_PROTECTION_FAULT 0 0x5c3 8 0 0 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GRBM 2 2 SH_ID 3 5 CU_ID 6 9 SIMD_ID 10 11 WAVE_ID 12 15 ADDRESS 16 31 regGDS_VM_PROTECTION_FAULT 0 0x5c4 8 0 0 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GWS 2 2 OA 3 3 GRBM 4 4 TMZ 5 5 VMID 8 11 ADDRESS 16 31 regGDS_EDC_CNT 0 0x5c5 3 0 0 GDS_MEM_DED 0 1 GDS_MEM_SEC 4 5 UNUSED 6 31 regGDS_EDC_GRBM_CNT 0 0x5c6 3 0 0 DED 0 1 SEC 2 3 UNUSED 4 31 regGDS_EDC_OA_DED 0 0x5c7 13 0 0 ME0_GFXHP3D_PIX_DED 0 0 ME0_GFXHP3D_VTX_DED 1 1 ME0_CS_DED 2 2 ME0_GFXHP3D_GS_DED 3 3 ME1_PIPE0_DED 4 4 ME1_PIPE1_DED 5 5 ME1_PIPE2_DED 6 6 ME1_PIPE3_DED 7 7 ME2_PIPE0_DED 8 8 ME2_PIPE1_DED 9 9 ME2_PIPE2_DED 10 10 ME2_PIPE3_DED 11 11 UNUSED1 12 31 regGDS_DSM_CNTL 0 0x5ca 16 0 0 SEL_DSM_GDS_MEM_IRRITATOR_DATA_0 0 0 SEL_DSM_GDS_MEM_IRRITATOR_DATA_1 1 1 GDS_MEM_ENABLE_SINGLE_WRITE 2 2 SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0 3 3 SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1 4 4 GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE 5 5 SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0 6 6 SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1 7 7 GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE 8 8 SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0 9 9 SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1 10 10 GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE 11 11 SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0 12 12 SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1 13 13 GDS_PIPE_MEM_ENABLE_SINGLE_WRITE 14 14 UNUSED 15 31 regGDS_EDC_OA_PHY_CNT 0 0x5cb 7 0 0 ME0_CS_PIPE_MEM_SEC 0 1 ME0_CS_PIPE_MEM_DED 2 3 PHY_CMD_RAM_MEM_SEC 4 5 PHY_CMD_RAM_MEM_DED 6 7 PHY_DATA_RAM_MEM_SEC 8 9 PHY_DATA_RAM_MEM_DED 10 11 UNUSED1 12 31 regGDS_EDC_OA_PIPE_CNT 0 0x5cc 9 0 0 ME1_PIPE0_PIPE_MEM_SEC 0 1 ME1_PIPE0_PIPE_MEM_DED 2 3 ME1_PIPE1_PIPE_MEM_SEC 4 5 ME1_PIPE1_PIPE_MEM_DED 6 7 ME1_PIPE2_PIPE_MEM_SEC 8 9 ME1_PIPE2_PIPE_MEM_DED 10 11 ME1_PIPE3_PIPE_MEM_SEC 12 13 ME1_PIPE3_PIPE_MEM_DED 14 15 UNUSED 16 31 regGDS_DSM_CNTL2 0 0x5cd 12 0 0 GDS_MEM_ENABLE_ERROR_INJECT 0 1 GDS_MEM_SELECT_INJECT_DELAY 2 2 GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT 3 4 GDS_INPUT_QUEUE_SELECT_INJECT_DELAY 5 5 GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT 6 7 GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY 8 8 GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT 9 10 GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY 11 11 GDS_PIPE_MEM_ENABLE_ERROR_INJECT 12 13 GDS_PIPE_MEM_SELECT_INJECT_DELAY 14 14 UNUSED 15 25 GDS_INJECT_DELAY 26 31 regGDS_WD_GDS_CSB 0 0x5ce 2 0 0 COUNTER 0 12 UNUSED 13 31 regGDS_VMID0_BASE 0 0x1300 1 0 0 BASE 0 15 regGDS_VMID0_SIZE 0 0x1301 1 0 0 SIZE 0 16 regGDS_VMID1_BASE 0 0x1302 1 0 0 BASE 0 15 regGDS_VMID1_SIZE 0 0x1303 1 0 0 SIZE 0 16 regGDS_VMID2_BASE 0 0x1304 1 0 0 BASE 0 15 regGDS_VMID2_SIZE 0 0x1305 1 0 0 SIZE 0 16 regGDS_VMID3_BASE 0 0x1306 1 0 0 BASE 0 15 regGDS_VMID3_SIZE 0 0x1307 1 0 0 SIZE 0 16 regGDS_VMID4_BASE 0 0x1308 1 0 0 BASE 0 15 regGDS_VMID4_SIZE 0 0x1309 1 0 0 SIZE 0 16 regGDS_VMID5_BASE 0 0x130a 1 0 0 BASE 0 15 regGDS_VMID5_SIZE 0 0x130b 1 0 0 SIZE 0 16 regGDS_VMID6_BASE 0 0x130c 1 0 0 BASE 0 15 regGDS_VMID6_SIZE 0 0x130d 1 0 0 SIZE 0 16 regGDS_VMID7_BASE 0 0x130e 1 0 0 BASE 0 15 regGDS_VMID7_SIZE 0 0x130f 1 0 0 SIZE 0 16 regGDS_VMID8_BASE 0 0x1310 1 0 0 BASE 0 15 regGDS_VMID8_SIZE 0 0x1311 1 0 0 SIZE 0 16 regGDS_VMID9_BASE 0 0x1312 1 0 0 BASE 0 15 regGDS_VMID9_SIZE 0 0x1313 1 0 0 SIZE 0 16 regGDS_VMID10_BASE 0 0x1314 1 0 0 BASE 0 15 regGDS_VMID10_SIZE 0 0x1315 1 0 0 SIZE 0 16 regGDS_VMID11_BASE 0 0x1316 1 0 0 BASE 0 15 regGDS_VMID11_SIZE 0 0x1317 1 0 0 SIZE 0 16 regGDS_VMID12_BASE 0 0x1318 1 0 0 BASE 0 15 regGDS_VMID12_SIZE 0 0x1319 1 0 0 SIZE 0 16 regGDS_VMID13_BASE 0 0x131a 1 0 0 BASE 0 15 regGDS_VMID13_SIZE 0 0x131b 1 0 0 SIZE 0 16 regGDS_VMID14_BASE 0 0x131c 1 0 0 BASE 0 15 regGDS_VMID14_SIZE 0 0x131d 1 0 0 SIZE 0 16 regGDS_VMID15_BASE 0 0x131e 1 0 0 BASE 0 15 regGDS_VMID15_SIZE 0 0x131f 1 0 0 SIZE 0 16 regGDS_GWS_VMID0 0 0x1320 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID1 0 0x1321 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID2 0 0x1322 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID3 0 0x1323 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID4 0 0x1324 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID5 0 0x1325 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID6 0 0x1326 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID7 0 0x1327 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID8 0 0x1328 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID9 0 0x1329 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID10 0 0x132a 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID11 0 0x132b 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID12 0 0x132c 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID13 0 0x132d 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID14 0 0x132e 2 0 0 BASE 0 5 SIZE 16 22 regGDS_GWS_VMID15 0 0x132f 2 0 0 BASE 0 5 SIZE 16 22 regGDS_OA_VMID0 0 0x1330 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID1 0 0x1331 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID2 0 0x1332 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID3 0 0x1333 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID4 0 0x1334 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID5 0 0x1335 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID6 0 0x1336 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID7 0 0x1337 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID8 0 0x1338 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID9 0 0x1339 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID10 0 0x133a 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID11 0 0x133b 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID12 0 0x133c 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID13 0 0x133d 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID14 0 0x133e 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_OA_VMID15 0 0x133f 2 0 0 MASK 0 15 UNUSED 16 31 regGDS_GWS_RESET0 0 0x1344 32 0 0 RESOURCE0_RESET 0 0 RESOURCE1_RESET 1 1 RESOURCE2_RESET 2 2 RESOURCE3_RESET 3 3 RESOURCE4_RESET 4 4 RESOURCE5_RESET 5 5 RESOURCE6_RESET 6 6 RESOURCE7_RESET 7 7 RESOURCE8_RESET 8 8 RESOURCE9_RESET 9 9 RESOURCE10_RESET 10 10 RESOURCE11_RESET 11 11 RESOURCE12_RESET 12 12 RESOURCE13_RESET 13 13 RESOURCE14_RESET 14 14 RESOURCE15_RESET 15 15 RESOURCE16_RESET 16 16 RESOURCE17_RESET 17 17 RESOURCE18_RESET 18 18 RESOURCE19_RESET 19 19 RESOURCE20_RESET 20 20 RESOURCE21_RESET 21 21 RESOURCE22_RESET 22 22 RESOURCE23_RESET 23 23 RESOURCE24_RESET 24 24 RESOURCE25_RESET 25 25 RESOURCE26_RESET 26 26 RESOURCE27_RESET 27 27 RESOURCE28_RESET 28 28 RESOURCE29_RESET 29 29 RESOURCE30_RESET 30 30 RESOURCE31_RESET 31 31 regGDS_GWS_RESET1 0 0x1345 32 0 0 RESOURCE32_RESET 0 0 RESOURCE33_RESET 1 1 RESOURCE34_RESET 2 2 RESOURCE35_RESET 3 3 RESOURCE36_RESET 4 4 RESOURCE37_RESET 5 5 RESOURCE38_RESET 6 6 RESOURCE39_RESET 7 7 RESOURCE40_RESET 8 8 RESOURCE41_RESET 9 9 RESOURCE42_RESET 10 10 RESOURCE43_RESET 11 11 RESOURCE44_RESET 12 12 RESOURCE45_RESET 13 13 RESOURCE46_RESET 14 14 RESOURCE47_RESET 15 15 RESOURCE48_RESET 16 16 RESOURCE49_RESET 17 17 RESOURCE50_RESET 18 18 RESOURCE51_RESET 19 19 RESOURCE52_RESET 20 20 RESOURCE53_RESET 21 21 RESOURCE54_RESET 22 22 RESOURCE55_RESET 23 23 RESOURCE56_RESET 24 24 RESOURCE57_RESET 25 25 RESOURCE58_RESET 26 26 RESOURCE59_RESET 27 27 RESOURCE60_RESET 28 28 RESOURCE61_RESET 29 29 RESOURCE62_RESET 30 30 RESOURCE63_RESET 31 31 regGDS_GWS_RESOURCE_RESET 0 0x1346 2 0 0 RESET 0 0 RESOURCE_ID 8 15 regGDS_COMPUTE_MAX_WAVE_ID 0 0x1348 1 0 0 MAX_WAVE_ID 0 11 regGDS_OA_RESET_MASK 0 0x1349 13 0 0 ME0_GFXHP3D_PIX_RESET 0 0 ME0_GFXHP3D_VTX_RESET 1 1 ME0_CS_RESET 2 2 ME0_GFXHP3D_GS_RESET 3 3 ME1_PIPE0_RESET 4 4 ME1_PIPE1_RESET 5 5 ME1_PIPE2_RESET 6 6 ME1_PIPE3_RESET 7 7 ME2_PIPE0_RESET 8 8 ME2_PIPE1_RESET 9 9 ME2_PIPE2_RESET 10 10 ME2_PIPE3_RESET 11 11 UNUSED1 12 31 regGDS_OA_RESET 0 0x134a 2 0 0 RESET 0 0 PIPE_ID 8 15 regGDS_ENHANCE 0 0x134b 10 0 0 MISC 0 15 AUTO_INC_INDEX 16 16 CGPG_RESTORE 17 17 RD_BUF_TAG_MISS 18 18 GDSA_PC_CGTS_DIS 19 19 GDSO_PC_CGTS_DIS 20 20 WD_GDS_CSB_OVERRIDE 21 21 GDS_CLK_ENHANCE_DIS 22 22 DS_MEM_CLK_GATE_DIS 23 23 UNUSED 24 31 regGDS_OA_CGPG_RESTORE 0 0x134c 5 0 0 VMID 0 7 MEID 8 11 PIPEID 12 15 QUEUEID 16 19 UNUSED 20 31 regGDS_CS_CTXSW_STATUS 0 0x134d 3 0 0 R 0 0 W 1 1 UNUSED 2 31 regGDS_CS_CTXSW_CNT0 0 0x134e 2 0 0 UPDN 0 15 PTR 16 31 regGDS_CS_CTXSW_CNT1 0 0x134f 2 0 0 UPDN 0 15 PTR 16 31 regGDS_CS_CTXSW_CNT2 0 0x1350 2 0 0 UPDN 0 15 PTR 16 31 regGDS_CS_CTXSW_CNT3 0 0x1351 2 0 0 UPDN 0 15 PTR 16 31 regGDS_GFX_CTXSW_STATUS 0 0x1352 3 0 0 R 0 0 W 1 1 UNUSED 2 31 regGDS_VS_CTXSW_CNT0 0 0x1353 2 0 0 UPDN 0 15 PTR 16 31 regGDS_VS_CTXSW_CNT1 0 0x1354 2 0 0 UPDN 0 15 PTR 16 31 regGDS_VS_CTXSW_CNT2 0 0x1355 2 0 0 UPDN 0 15 PTR 16 31 regGDS_VS_CTXSW_CNT3 0 0x1356 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS0_CTXSW_CNT0 0 0x1357 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS0_CTXSW_CNT1 0 0x1358 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS0_CTXSW_CNT2 0 0x1359 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS0_CTXSW_CNT3 0 0x135a 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS1_CTXSW_CNT0 0 0x135b 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS1_CTXSW_CNT1 0 0x135c 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS1_CTXSW_CNT2 0 0x135d 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS1_CTXSW_CNT3 0 0x135e 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS2_CTXSW_CNT0 0 0x135f 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS2_CTXSW_CNT1 0 0x1360 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS2_CTXSW_CNT2 0 0x1361 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS2_CTXSW_CNT3 0 0x1362 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS3_CTXSW_CNT0 0 0x1363 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS3_CTXSW_CNT1 0 0x1364 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS3_CTXSW_CNT2 0 0x1365 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS3_CTXSW_CNT3 0 0x1366 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS4_CTXSW_CNT0 0 0x1367 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS4_CTXSW_CNT1 0 0x1368 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS4_CTXSW_CNT2 0 0x1369 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS4_CTXSW_CNT3 0 0x136a 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS5_CTXSW_CNT0 0 0x136b 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS5_CTXSW_CNT1 0 0x136c 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS5_CTXSW_CNT2 0 0x136d 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS5_CTXSW_CNT3 0 0x136e 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS6_CTXSW_CNT0 0 0x136f 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS6_CTXSW_CNT1 0 0x1370 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS6_CTXSW_CNT2 0 0x1371 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS6_CTXSW_CNT3 0 0x1372 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS7_CTXSW_CNT0 0 0x1373 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS7_CTXSW_CNT1 0 0x1374 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS7_CTXSW_CNT2 0 0x1375 2 0 0 UPDN 0 15 PTR 16 31 regGDS_PS7_CTXSW_CNT3 0 0x1376 2 0 0 UPDN 0 15 PTR 16 31 regGDS_GS_CTXSW_CNT0 0 0x1377 2 0 0 UPDN 0 15 PTR 16 31 regGDS_GS_CTXSW_CNT1 0 0x1378 2 0 0 UPDN 0 15 PTR 16 31 regGDS_GS_CTXSW_CNT2 0 0x1379 2 0 0 UPDN 0 15 PTR 16 31 regGDS_GS_CTXSW_CNT3 0 0x137a 2 0 0 UPDN 0 15 PTR 16 31 regDB_RENDER_CONTROL 0 0x0 10 0 1 DEPTH_CLEAR_ENABLE 0 0 STENCIL_CLEAR_ENABLE 1 1 DEPTH_COPY 2 2 STENCIL_COPY 3 3 RESUMMARIZE_ENABLE 4 4 STENCIL_COMPRESS_DISABLE 5 5 DEPTH_COMPRESS_DISABLE 6 6 COPY_CENTROID 7 7 COPY_SAMPLE 8 11 DECOMPRESS_ENABLE 12 12 regDB_COUNT_CONTROL 0 0x1 9 0 1 ZPASS_INCREMENT_DISABLE 0 0 PERFECT_ZPASS_COUNTS 1 1 SAMPLE_RATE 4 6 ZPASS_ENABLE 8 11 ZFAIL_ENABLE 12 15 SFAIL_ENABLE 16 19 DBFAIL_ENABLE 20 23 SLICE_EVEN_ENABLE 24 27 SLICE_ODD_ENABLE 28 31 regDB_DEPTH_VIEW 0 0x2 5 0 1 SLICE_START 0 10 SLICE_MAX 13 23 Z_READ_ONLY 24 24 STENCIL_READ_ONLY 25 25 MIPID 26 29 regDB_RENDER_OVERRIDE 0 0x3 23 0 1 FORCE_HIZ_ENABLE 0 1 FORCE_HIS_ENABLE0 2 3 FORCE_HIS_ENABLE1 4 5 FORCE_SHADER_Z_ORDER 6 6 FAST_Z_DISABLE 7 7 FAST_STENCIL_DISABLE 8 8 NOOP_CULL_DISABLE 9 9 FORCE_COLOR_KILL 10 10 FORCE_Z_READ 11 11 FORCE_STENCIL_READ 12 12 FORCE_FULL_Z_RANGE 13 14 FORCE_QC_SMASK_CONFLICT 15 15 DISABLE_VIEWPORT_CLAMP 16 16 IGNORE_SC_ZRANGE 17 17 DISABLE_FULLY_COVERED 18 18 FORCE_Z_LIMIT_SUMM 19 20 MAX_TILES_IN_DTT 21 25 DISABLE_TILE_RATE_TILES 26 26 FORCE_Z_DIRTY 27 27 FORCE_STENCIL_DIRTY 28 28 FORCE_Z_VALID 29 29 FORCE_STENCIL_VALID 30 30 PRESERVE_COMPRESSION 31 31 regDB_RENDER_OVERRIDE2 0 0x4 16 0 1 PARTIAL_SQUAD_LAUNCH_CONTROL 0 1 PARTIAL_SQUAD_LAUNCH_COUNTDOWN 2 4 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 5 5 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 6 6 DISABLE_COLOR_ON_VALIDATION 7 7 DECOMPRESS_Z_ON_FLUSH 8 8 DISABLE_REG_SNOOP 9 9 DEPTH_BOUNDS_HIER_DEPTH_DISABLE 10 10 SEPARATE_HIZS_FUNC_ENABLE 11 11 HIZ_ZFUNC 12 14 HIS_SFUNC_FF 15 17 HIS_SFUNC_BF 18 20 PRESERVE_ZRANGE 21 21 PRESERVE_SRESULTS 22 22 DISABLE_FAST_PASS 23 23 ALLOW_PARTIAL_RES_HIER_KILL 25 25 regDB_HTILE_DATA_BASE 0 0x5 1 0 1 BASE_256B 0 31 regDB_HTILE_DATA_BASE_HI 0 0x6 1 0 1 BASE_HI 0 7 regDB_DEPTH_SIZE 0 0x7 2 0 1 X_MAX 0 13 Y_MAX 16 29 regDB_DEPTH_BOUNDS_MIN 0 0x8 1 0 1 MIN 0 31 regDB_DEPTH_BOUNDS_MAX 0 0x9 1 0 1 MAX 0 31 regDB_STENCIL_CLEAR 0 0xa 1 0 1 CLEAR 0 7 regDB_DEPTH_CLEAR 0 0xb 1 0 1 DEPTH_CLEAR 0 31 regPA_SC_SCREEN_SCISSOR_TL 0 0xc 2 0 1 TL_X 0 15 TL_Y 16 31 regPA_SC_SCREEN_SCISSOR_BR 0 0xd 2 0 1 BR_X 0 15 BR_Y 16 31 regDB_Z_INFO 0 0xe 13 0 1 FORMAT 0 1 NUM_SAMPLES 2 3 SW_MODE 4 8 PARTIALLY_RESIDENT 12 12 FAULT_BEHAVIOR 13 14 ITERATE_FLUSH 15 15 MAXMIP 16 19 DECOMPRESS_ON_N_ZPLANES 23 26 ALLOW_EXPCLEAR 27 27 READ_SIZE 28 28 TILE_SURFACE_ENABLE 29 29 CLEAR_DISALLOWED 30 30 ZRANGE_PRECISION 31 31 regDB_STENCIL_INFO 0 0xf 8 0 1 FORMAT 0 0 SW_MODE 4 8 PARTIALLY_RESIDENT 12 12 FAULT_BEHAVIOR 13 14 ITERATE_FLUSH 15 15 ALLOW_EXPCLEAR 27 27 TILE_STENCIL_DISABLE 29 29 CLEAR_DISALLOWED 30 30 regDB_Z_READ_BASE 0 0x10 1 0 1 BASE_256B 0 31 regDB_Z_READ_BASE_HI 0 0x11 1 0 1 BASE_HI 0 7 regDB_STENCIL_READ_BASE 0 0x12 1 0 1 BASE_256B 0 31 regDB_STENCIL_READ_BASE_HI 0 0x13 1 0 1 BASE_HI 0 7 regDB_Z_WRITE_BASE 0 0x14 1 0 1 BASE_256B 0 31 regDB_Z_WRITE_BASE_HI 0 0x15 1 0 1 BASE_HI 0 7 regDB_STENCIL_WRITE_BASE 0 0x16 1 0 1 BASE_256B 0 31 regDB_STENCIL_WRITE_BASE_HI 0 0x17 1 0 1 BASE_HI 0 7 regDB_DFSM_CONTROL 0 0x18 3 0 1 PUNCHOUT_MODE 0 1 POPS_DRAIN_PS_ON_OVERLAP 2 2 DISALLOW_OVERFLOW 3 3 regDB_Z_INFO2 0 0x1a 1 0 1 EPITCH 0 15 regDB_STENCIL_INFO2 0 0x1b 1 0 1 EPITCH 0 15 regCOHER_DEST_BASE_HI_0 0 0x7a 1 0 1 DEST_BASE_HI_256B 0 7 regCOHER_DEST_BASE_HI_1 0 0x7b 1 0 1 DEST_BASE_HI_256B 0 7 regCOHER_DEST_BASE_HI_2 0 0x7c 1 0 1 DEST_BASE_HI_256B 0 7 regCOHER_DEST_BASE_HI_3 0 0x7d 1 0 1 DEST_BASE_HI_256B 0 7 regCOHER_DEST_BASE_2 0 0x7e 1 0 1 DEST_BASE_256B 0 31 regCOHER_DEST_BASE_3 0 0x7f 1 0 1 DEST_BASE_256B 0 31 regPA_SC_WINDOW_OFFSET 0 0x80 2 0 1 WINDOW_X_OFFSET 0 15 WINDOW_Y_OFFSET 16 31 regPA_SC_WINDOW_SCISSOR_TL 0 0x81 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_WINDOW_SCISSOR_BR 0 0x82 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_CLIPRECT_RULE 0 0x83 1 0 1 CLIP_RULE 0 15 regPA_SC_CLIPRECT_0_TL 0 0x84 2 0 1 TL_X 0 14 TL_Y 16 30 regPA_SC_CLIPRECT_0_BR 0 0x85 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_CLIPRECT_1_TL 0 0x86 2 0 1 TL_X 0 14 TL_Y 16 30 regPA_SC_CLIPRECT_1_BR 0 0x87 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_CLIPRECT_2_TL 0 0x88 2 0 1 TL_X 0 14 TL_Y 16 30 regPA_SC_CLIPRECT_2_BR 0 0x89 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_CLIPRECT_3_TL 0 0x8a 2 0 1 TL_X 0 14 TL_Y 16 30 regPA_SC_CLIPRECT_3_BR 0 0x8b 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_EDGERULE 0 0x8c 7 0 1 ER_TRI 0 3 ER_POINT 4 7 ER_RECT 8 11 ER_LINE_LR 12 17 ER_LINE_RL 18 23 ER_LINE_TB 24 27 ER_LINE_BT 28 31 regPA_SU_HARDWARE_SCREEN_OFFSET 0 0x8d 2 0 1 HW_SCREEN_OFFSET_X 0 8 HW_SCREEN_OFFSET_Y 16 24 regCB_TARGET_MASK 0 0x8e 8 0 1 TARGET0_ENABLE 0 3 TARGET1_ENABLE 4 7 TARGET2_ENABLE 8 11 TARGET3_ENABLE 12 15 TARGET4_ENABLE 16 19 TARGET5_ENABLE 20 23 TARGET6_ENABLE 24 27 TARGET7_ENABLE 28 31 regCB_SHADER_MASK 0 0x8f 8 0 1 OUTPUT0_ENABLE 0 3 OUTPUT1_ENABLE 4 7 OUTPUT2_ENABLE 8 11 OUTPUT3_ENABLE 12 15 OUTPUT4_ENABLE 16 19 OUTPUT5_ENABLE 20 23 OUTPUT6_ENABLE 24 27 OUTPUT7_ENABLE 28 31 regPA_SC_GENERIC_SCISSOR_TL 0 0x90 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_GENERIC_SCISSOR_BR 0 0x91 2 0 1 BR_X 0 14 BR_Y 16 30 regCOHER_DEST_BASE_0 0 0x92 1 0 1 DEST_BASE_256B 0 31 regCOHER_DEST_BASE_1 0 0x93 1 0 1 DEST_BASE_256B 0 31 regPA_SC_VPORT_SCISSOR_0_TL 0 0x94 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_0_BR 0 0x95 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_1_TL 0 0x96 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_1_BR 0 0x97 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_2_TL 0 0x98 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_2_BR 0 0x99 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_3_TL 0 0x9a 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_3_BR 0 0x9b 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_4_TL 0 0x9c 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_4_BR 0 0x9d 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_5_TL 0 0x9e 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_5_BR 0 0x9f 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_6_TL 0 0xa0 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_6_BR 0 0xa1 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_7_TL 0 0xa2 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_7_BR 0 0xa3 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_8_TL 0 0xa4 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_8_BR 0 0xa5 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_9_TL 0 0xa6 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_9_BR 0 0xa7 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_10_TL 0 0xa8 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_10_BR 0 0xa9 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_11_TL 0 0xaa 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_11_BR 0 0xab 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_12_TL 0 0xac 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_12_BR 0 0xad 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_13_TL 0 0xae 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_13_BR 0 0xaf 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_14_TL 0 0xb0 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_14_BR 0 0xb1 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_SCISSOR_15_TL 0 0xb2 3 0 1 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 regPA_SC_VPORT_SCISSOR_15_BR 0 0xb3 2 0 1 BR_X 0 14 BR_Y 16 30 regPA_SC_VPORT_ZMIN_0 0 0xb4 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_0 0 0xb5 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_1 0 0xb6 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_1 0 0xb7 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_2 0 0xb8 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_2 0 0xb9 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_3 0 0xba 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_3 0 0xbb 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_4 0 0xbc 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_4 0 0xbd 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_5 0 0xbe 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_5 0 0xbf 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_6 0 0xc0 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_6 0 0xc1 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_7 0 0xc2 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_7 0 0xc3 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_8 0 0xc4 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_8 0 0xc5 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_9 0 0xc6 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_9 0 0xc7 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_10 0 0xc8 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_10 0 0xc9 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_11 0 0xca 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_11 0 0xcb 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_12 0 0xcc 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_12 0 0xcd 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_13 0 0xce 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_13 0 0xcf 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_14 0 0xd0 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_14 0 0xd1 1 0 1 VPORT_ZMAX 0 31 regPA_SC_VPORT_ZMIN_15 0 0xd2 1 0 1 VPORT_ZMIN 0 31 regPA_SC_VPORT_ZMAX_15 0 0xd3 1 0 1 VPORT_ZMAX 0 31 regPA_SC_RASTER_CONFIG 0 0xd4 15 0 1 RB_MAP_PKR0 0 1 RB_MAP_PKR1 2 3 RB_XSEL2 4 5 RB_XSEL 6 6 RB_YSEL 7 7 PKR_MAP 8 9 PKR_XSEL 10 11 PKR_YSEL 12 13 PKR_XSEL2 14 15 SC_MAP 16 17 SC_XSEL 18 19 SC_YSEL 20 21 SE_MAP 24 25 SE_XSEL 26 28 SE_YSEL 29 31 regPA_SC_RASTER_CONFIG_1 0 0xd5 3 0 1 SE_PAIR_MAP 0 1 SE_PAIR_XSEL 2 4 SE_PAIR_YSEL 5 7 regPA_SC_SCREEN_EXTENT_CONTROL 0 0xd6 2 0 1 SLICE_EVEN_ENABLE 0 1 SLICE_ODD_ENABLE 2 3 regPA_SC_TILE_STEERING_OVERRIDE 0 0xd7 3 0 1 ENABLE 0 0 NUM_SE 1 2 NUM_RB_PER_SE 5 6 regCP_PERFMON_CNTX_CNTL 0 0xd8 1 0 1 PERFMON_ENABLE 31 31 regCP_PIPEID 0 0xd9 1 0 1 PIPE_ID 0 1 regCP_RINGID 0 0xd9 1 0 1 RINGID 0 1 regCP_VMID 0 0xda 1 0 1 VMID 0 3 regPA_SC_RIGHT_VERT_GRID 0 0xe8 4 0 1 LEFT_QTR 0 7 LEFT_HALF 8 15 RIGHT_HALF 16 23 RIGHT_QTR 24 31 regPA_SC_LEFT_VERT_GRID 0 0xe9 4 0 1 LEFT_QTR 0 7 LEFT_HALF 8 15 RIGHT_HALF 16 23 RIGHT_QTR 24 31 regPA_SC_HORIZ_GRID 0 0xea 4 0 1 TOP_QTR 0 7 TOP_HALF 8 15 BOT_HALF 16 23 BOT_QTR 24 31 regVGT_MULTI_PRIM_IB_RESET_INDX 0 0x103 1 0 1 RESET_INDX 0 31 regCB_BLEND_RED 0 0x105 1 0 1 BLEND_RED 0 31 regCB_BLEND_GREEN 0 0x106 1 0 1 BLEND_GREEN 0 31 regCB_BLEND_BLUE 0 0x107 1 0 1 BLEND_BLUE 0 31 regCB_BLEND_ALPHA 0 0x108 1 0 1 BLEND_ALPHA 0 31 regCB_DCC_CONTROL 0 0x109 9 0 1 OVERWRITE_COMBINER_DISABLE 0 0 OVERWRITE_COMBINER_MRT_SHARING_DISABLE 1 1 OVERWRITE_COMBINER_WATERMARK 2 6 DISABLE_CONSTANT_ENCODE_AC01 8 8 DISABLE_CONSTANT_ENCODE_SINGLE 9 9 DISABLE_CONSTANT_ENCODE_REG 10 10 DISABLE_ELIMFC_SKIP_OF_AC01 12 12 DISABLE_ELIMFC_SKIP_OF_SINGLE 13 13 ENABLE_ELIMFC_SKIP_OF_REG 14 14 regDB_STENCIL_CONTROL 0 0x10b 6 0 1 STENCILFAIL 0 3 STENCILZPASS 4 7 STENCILZFAIL 8 11 STENCILFAIL_BF 12 15 STENCILZPASS_BF 16 19 STENCILZFAIL_BF 20 23 regDB_STENCILREFMASK 0 0x10c 4 0 1 STENCILTESTVAL 0 7 STENCILMASK 8 15 STENCILWRITEMASK 16 23 STENCILOPVAL 24 31 regDB_STENCILREFMASK_BF 0 0x10d 4 0 1 STENCILTESTVAL_BF 0 7 STENCILMASK_BF 8 15 STENCILWRITEMASK_BF 16 23 STENCILOPVAL_BF 24 31 regPA_CL_VPORT_XSCALE 0 0x10f 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET 0 0x110 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE 0 0x111 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET 0 0x112 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE 0 0x113 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET 0 0x114 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_1 0 0x115 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_1 0 0x116 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_1 0 0x117 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_1 0 0x118 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_1 0 0x119 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_1 0 0x11a 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_2 0 0x11b 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_2 0 0x11c 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_2 0 0x11d 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_2 0 0x11e 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_2 0 0x11f 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_2 0 0x120 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_3 0 0x121 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_3 0 0x122 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_3 0 0x123 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_3 0 0x124 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_3 0 0x125 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_3 0 0x126 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_4 0 0x127 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_4 0 0x128 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_4 0 0x129 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_4 0 0x12a 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_4 0 0x12b 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_4 0 0x12c 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_5 0 0x12d 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_5 0 0x12e 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_5 0 0x12f 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_5 0 0x130 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_5 0 0x131 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_5 0 0x132 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_6 0 0x133 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_6 0 0x134 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_6 0 0x135 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_6 0 0x136 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_6 0 0x137 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_6 0 0x138 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_7 0 0x139 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_7 0 0x13a 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_7 0 0x13b 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_7 0 0x13c 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_7 0 0x13d 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_7 0 0x13e 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_8 0 0x13f 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_8 0 0x140 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_8 0 0x141 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_8 0 0x142 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_8 0 0x143 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_8 0 0x144 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_9 0 0x145 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_9 0 0x146 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_9 0 0x147 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_9 0 0x148 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_9 0 0x149 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_9 0 0x14a 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_10 0 0x14b 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_10 0 0x14c 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_10 0 0x14d 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_10 0 0x14e 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_10 0 0x14f 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_10 0 0x150 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_11 0 0x151 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_11 0 0x152 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_11 0 0x153 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_11 0 0x154 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_11 0 0x155 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_11 0 0x156 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_12 0 0x157 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_12 0 0x158 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_12 0 0x159 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_12 0 0x15a 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_12 0 0x15b 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_12 0 0x15c 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_13 0 0x15d 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_13 0 0x15e 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_13 0 0x15f 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_13 0 0x160 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_13 0 0x161 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_13 0 0x162 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_14 0 0x163 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_14 0 0x164 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_14 0 0x165 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_14 0 0x166 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_14 0 0x167 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_14 0 0x168 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_VPORT_XSCALE_15 0 0x169 1 0 1 VPORT_XSCALE 0 31 regPA_CL_VPORT_XOFFSET_15 0 0x16a 1 0 1 VPORT_XOFFSET 0 31 regPA_CL_VPORT_YSCALE_15 0 0x16b 1 0 1 VPORT_YSCALE 0 31 regPA_CL_VPORT_YOFFSET_15 0 0x16c 1 0 1 VPORT_YOFFSET 0 31 regPA_CL_VPORT_ZSCALE_15 0 0x16d 1 0 1 VPORT_ZSCALE 0 31 regPA_CL_VPORT_ZOFFSET_15 0 0x16e 1 0 1 VPORT_ZOFFSET 0 31 regPA_CL_UCP_0_X 0 0x16f 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_0_Y 0 0x170 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_0_Z 0 0x171 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_0_W 0 0x172 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_1_X 0 0x173 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_1_Y 0 0x174 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_1_Z 0 0x175 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_1_W 0 0x176 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_2_X 0 0x177 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_2_Y 0 0x178 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_2_Z 0 0x179 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_2_W 0 0x17a 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_3_X 0 0x17b 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_3_Y 0 0x17c 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_3_Z 0 0x17d 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_3_W 0 0x17e 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_4_X 0 0x17f 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_4_Y 0 0x180 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_4_Z 0 0x181 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_4_W 0 0x182 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_5_X 0 0x183 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_5_Y 0 0x184 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_5_Z 0 0x185 1 0 1 DATA_REGISTER 0 31 regPA_CL_UCP_5_W 0 0x186 1 0 1 DATA_REGISTER 0 31 regPA_CL_PROG_NEAR_CLIP_Z 0 0x187 1 0 1 DATA_REGISTER 0 31 regSPI_PS_INPUT_CNTL_0 0 0x191 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_1 0 0x192 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_2 0 0x193 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_3 0 0x194 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_4 0 0x195 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_5 0 0x196 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_6 0 0x197 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_7 0 0x198 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_8 0 0x199 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_9 0 0x19a 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_10 0 0x19b 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_11 0 0x19c 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_12 0 0x19d 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_13 0 0x19e 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_14 0 0x19f 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_15 0 0x1a0 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_16 0 0x1a1 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_17 0 0x1a2 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_18 0 0x1a3 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_19 0 0x1a4 12 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 PT_SPRITE_TEX_ATTR1 23 23 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_20 0 0x1a5 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_21 0 0x1a6 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_22 0 0x1a7 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_23 0 0x1a8 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_24 0 0x1a9 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_25 0 0x1aa 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_26 0 0x1ab 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_27 0 0x1ac 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_28 0 0x1ad 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_29 0 0x1ae 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_30 0 0x1af 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_PS_INPUT_CNTL_31 0 0x1b0 9 0 1 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 FP16_INTERP_MODE 19 19 USE_DEFAULT_ATTR1 20 20 DEFAULT_VAL_ATTR1 21 22 ATTR0_VALID 24 24 ATTR1_VALID 25 25 regSPI_VS_OUT_CONFIG 0 0x1b1 2 0 1 VS_EXPORT_COUNT 1 5 VS_HALF_PACK 6 6 regSPI_PS_INPUT_ENA 0 0x1b3 16 0 1 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 regSPI_PS_INPUT_ADDR 0 0x1b4 16 0 1 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 regSPI_INTERP_CONTROL_0 0 0x1b5 7 0 1 FLAT_SHADE_ENA 0 0 PNT_SPRITE_ENA 1 1 PNT_SPRITE_OVRD_X 2 4 PNT_SPRITE_OVRD_Y 5 7 PNT_SPRITE_OVRD_Z 8 10 PNT_SPRITE_OVRD_W 11 13 PNT_SPRITE_TOP_1 14 14 regSPI_PS_IN_CONTROL 0 0x1b6 4 0 1 NUM_INTERP 0 5 OFFCHIP_PARAM_EN 7 7 LATE_PC_DEALLOC 8 8 BC_OPTIMIZE_DISABLE 14 14 regSPI_BARYC_CNTL 0 0x1b8 7 0 1 PERSP_CENTER_CNTL 0 0 PERSP_CENTROID_CNTL 4 4 LINEAR_CENTER_CNTL 8 8 LINEAR_CENTROID_CNTL 12 12 POS_FLOAT_LOCATION 16 17 POS_FLOAT_ULC 20 20 FRONT_FACE_ALL_BITS 24 24 regSPI_TMPRING_SIZE 0 0x1ba 2 0 1 WAVES 0 11 WAVESIZE 12 24 regSPI_SHADER_POS_FORMAT 0 0x1c3 4 0 1 POS0_EXPORT_FORMAT 0 3 POS1_EXPORT_FORMAT 4 7 POS2_EXPORT_FORMAT 8 11 POS3_EXPORT_FORMAT 12 15 regSPI_SHADER_Z_FORMAT 0 0x1c4 1 0 1 Z_EXPORT_FORMAT 0 3 regSPI_SHADER_COL_FORMAT 0 0x1c5 8 0 1 COL0_EXPORT_FORMAT 0 3 COL1_EXPORT_FORMAT 4 7 COL2_EXPORT_FORMAT 8 11 COL3_EXPORT_FORMAT 12 15 COL4_EXPORT_FORMAT 16 19 COL5_EXPORT_FORMAT 20 23 COL6_EXPORT_FORMAT 24 27 COL7_EXPORT_FORMAT 28 31 regSX_PS_DOWNCONVERT 0 0x1d5 8 0 1 MRT0 0 3 MRT1 4 7 MRT2 8 11 MRT3 12 15 MRT4 16 19 MRT5 20 23 MRT6 24 27 MRT7 28 31 regSX_BLEND_OPT_EPSILON 0 0x1d6 8 0 1 MRT0_EPSILON 0 3 MRT1_EPSILON 4 7 MRT2_EPSILON 8 11 MRT3_EPSILON 12 15 MRT4_EPSILON 16 19 MRT5_EPSILON 20 23 MRT6_EPSILON 24 27 MRT7_EPSILON 28 31 regSX_BLEND_OPT_CONTROL 0 0x1d7 17 0 1 MRT0_COLOR_OPT_DISABLE 0 0 MRT0_ALPHA_OPT_DISABLE 1 1 MRT1_COLOR_OPT_DISABLE 4 4 MRT1_ALPHA_OPT_DISABLE 5 5 MRT2_COLOR_OPT_DISABLE 8 8 MRT2_ALPHA_OPT_DISABLE 9 9 MRT3_COLOR_OPT_DISABLE 12 12 MRT3_ALPHA_OPT_DISABLE 13 13 MRT4_COLOR_OPT_DISABLE 16 16 MRT4_ALPHA_OPT_DISABLE 17 17 MRT5_COLOR_OPT_DISABLE 20 20 MRT5_ALPHA_OPT_DISABLE 21 21 MRT6_COLOR_OPT_DISABLE 24 24 MRT6_ALPHA_OPT_DISABLE 25 25 MRT7_COLOR_OPT_DISABLE 28 28 MRT7_ALPHA_OPT_DISABLE 29 29 PIXEN_ZERO_OPT_DISABLE 31 31 regSX_MRT0_BLEND_OPT 0 0x1d8 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT1_BLEND_OPT 0 0x1d9 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT2_BLEND_OPT 0 0x1da 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT3_BLEND_OPT 0 0x1db 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT4_BLEND_OPT 0 0x1dc 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT5_BLEND_OPT 0 0x1dd 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT6_BLEND_OPT 0 0x1de 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regSX_MRT7_BLEND_OPT 0 0x1df 6 0 1 COLOR_SRC_OPT 0 2 COLOR_DST_OPT 4 6 COLOR_COMB_FCN 8 10 ALPHA_SRC_OPT 16 18 ALPHA_DST_OPT 20 22 ALPHA_COMB_FCN 24 26 regCB_BLEND0_CONTROL 0 0x1e0 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND1_CONTROL 0 0x1e1 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND2_CONTROL 0 0x1e2 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND3_CONTROL 0 0x1e3 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND4_CONTROL 0 0x1e4 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND5_CONTROL 0 0x1e5 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND6_CONTROL 0 0x1e6 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_BLEND7_CONTROL 0 0x1e7 9 0 1 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 regCB_MRT0_EPITCH 0 0x1e8 1 0 1 EPITCH 0 15 regCB_MRT1_EPITCH 0 0x1e9 1 0 1 EPITCH 0 15 regCB_MRT2_EPITCH 0 0x1ea 1 0 1 EPITCH 0 15 regCB_MRT3_EPITCH 0 0x1eb 1 0 1 EPITCH 0 15 regCB_MRT4_EPITCH 0 0x1ec 1 0 1 EPITCH 0 15 regCB_MRT5_EPITCH 0 0x1ed 1 0 1 EPITCH 0 15 regCB_MRT6_EPITCH 0 0x1ee 1 0 1 EPITCH 0 15 regCB_MRT7_EPITCH 0 0x1ef 1 0 1 EPITCH 0 15 regCS_COPY_STATE 0 0x1f3 1 0 1 SRC_STATE_ID 0 2 regGFX_COPY_STATE 0 0x1f4 1 0 1 SRC_STATE_ID 0 2 regPA_CL_POINT_X_RAD 0 0x1f5 1 0 1 DATA_REGISTER 0 31 regPA_CL_POINT_Y_RAD 0 0x1f6 1 0 1 DATA_REGISTER 0 31 regPA_CL_POINT_SIZE 0 0x1f7 1 0 1 DATA_REGISTER 0 31 regPA_CL_POINT_CULL_RAD 0 0x1f8 1 0 1 DATA_REGISTER 0 31 regVGT_DMA_BASE_HI 0 0x1f9 1 0 1 BASE_ADDR 0 15 regVGT_DMA_BASE 0 0x1fa 1 0 1 BASE_ADDR 0 31 regVGT_DRAW_INITIATOR 0 0x1fc 8 0 1 SOURCE_SELECT 0 1 MAJOR_MODE 2 3 SPRITE_EN_R6XX 4 4 NOT_EOP 5 5 USE_OPAQUE 6 6 UNROLLED_INST 7 7 GRBM_SKEW_NO_DEC 8 8 REG_RT_INDEX 29 31 regVGT_IMMED_DATA 0 0x1fd 1 0 1 DATA 0 31 regVGT_EVENT_ADDRESS_REG 0 0x1fe 1 0 1 ADDRESS_LOW 0 27 regDB_DEPTH_CONTROL 0 0x200 10 0 1 STENCIL_ENABLE 0 0 Z_ENABLE 1 1 Z_WRITE_ENABLE 2 2 DEPTH_BOUNDS_ENABLE 3 3 ZFUNC 4 6 BACKFACE_ENABLE 7 7 STENCILFUNC 8 10 STENCILFUNC_BF 20 22 ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 30 30 DISABLE_COLOR_WRITES_ON_DEPTH_PASS 31 31 regDB_EQAA 0 0x201 12 0 1 MAX_ANCHOR_SAMPLES 0 2 PS_ITER_SAMPLES 4 6 MASK_EXPORT_NUM_SAMPLES 8 10 ALPHA_TO_MASK_NUM_SAMPLES 12 14 HIGH_QUALITY_INTERSECTIONS 16 16 INCOHERENT_EQAA_READS 17 17 INTERPOLATE_COMP_Z 18 18 INTERPOLATE_SRC_Z 19 19 STATIC_ANCHOR_ASSOCIATIONS 20 20 ALPHA_TO_MASK_EQAA_DISABLE 21 21 OVERRASTERIZATION_AMOUNT 24 26 ENABLE_POSTZ_OVERRASTERIZATION 27 27 regCB_COLOR_CONTROL 0 0x202 4 0 1 DISABLE_DUAL_QUAD 0 0 DEGAMMA_ENABLE 3 3 MODE 4 6 ROP3 16 23 regDB_SHADER_CONTROL 0 0x203 16 0 1 Z_EXPORT_ENABLE 0 0 STENCIL_TEST_VAL_EXPORT_ENABLE 1 1 STENCIL_OP_VAL_EXPORT_ENABLE 2 2 Z_ORDER 4 5 KILL_ENABLE 6 6 COVERAGE_TO_MASK_ENABLE 7 7 MASK_EXPORT_ENABLE 8 8 EXEC_ON_HIER_FAIL 9 9 EXEC_ON_NOOP 10 10 ALPHA_TO_MASK_DISABLE 11 11 DEPTH_BEFORE_SHADER 12 12 CONSERVATIVE_Z_EXPORT 13 14 DUAL_QUAD_DISABLE 15 15 PRIMITIVE_ORDERED_PIXEL_SHADER 16 16 EXEC_IF_OVERLAPPED 17 17 POPS_OVERLAP_NUM_SAMPLES 20 22 regPA_CL_CLIP_CNTL 0 0x204 20 0 1 UCP_ENA_0 0 0 UCP_ENA_1 1 1 UCP_ENA_2 2 2 UCP_ENA_3 3 3 UCP_ENA_4 4 4 UCP_ENA_5 5 5 PS_UCP_Y_SCALE_NEG 13 13 PS_UCP_MODE 14 15 CLIP_DISABLE 16 16 UCP_CULL_ONLY_ENA 17 17 BOUNDARY_EDGE_FLAG_ENA 18 18 DX_CLIP_SPACE_DEF 19 19 DIS_CLIP_ERR_DETECT 20 20 VTX_KILL_OR 21 21 DX_RASTERIZATION_KILL 22 22 DX_LINEAR_ATTR_CLIP_ENA 24 24 VTE_VPORT_PROVOKE_DISABLE 25 25 ZCLIP_NEAR_DISABLE 26 26 ZCLIP_FAR_DISABLE 27 27 ZCLIP_PROG_NEAR_ENA 28 28 regPA_SU_SC_MODE_CNTL 0 0x205 15 0 1 CULL_FRONT 0 0 CULL_BACK 1 1 FACE 2 2 POLY_MODE 3 4 POLYMODE_FRONT_PTYPE 5 7 POLYMODE_BACK_PTYPE 8 10 POLY_OFFSET_FRONT_ENABLE 11 11 POLY_OFFSET_BACK_ENABLE 12 12 POLY_OFFSET_PARA_ENABLE 13 13 VTX_WINDOW_OFFSET_ENABLE 16 16 PROVOKING_VTX_LAST 19 19 PERSP_CORR_DIS 20 20 MULTI_PRIM_IB_ENA 21 21 RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF 22 22 NEW_QUAD_DECOMPOSITION 23 23 regPA_CL_VTE_CNTL 0 0x206 10 0 1 VPORT_X_SCALE_ENA 0 0 VPORT_X_OFFSET_ENA 1 1 VPORT_Y_SCALE_ENA 2 2 VPORT_Y_OFFSET_ENA 3 3 VPORT_Z_SCALE_ENA 4 4 VPORT_Z_OFFSET_ENA 5 5 VTX_XY_FMT 8 8 VTX_Z_FMT 9 9 VTX_W0_FMT 10 10 PERFCOUNTER_REF 11 11 regPA_CL_VS_OUT_CNTL 0 0x207 28 0 1 CLIP_DIST_ENA_0 0 0 CLIP_DIST_ENA_1 1 1 CLIP_DIST_ENA_2 2 2 CLIP_DIST_ENA_3 3 3 CLIP_DIST_ENA_4 4 4 CLIP_DIST_ENA_5 5 5 CLIP_DIST_ENA_6 6 6 CLIP_DIST_ENA_7 7 7 CULL_DIST_ENA_0 8 8 CULL_DIST_ENA_1 9 9 CULL_DIST_ENA_2 10 10 CULL_DIST_ENA_3 11 11 CULL_DIST_ENA_4 12 12 CULL_DIST_ENA_5 13 13 CULL_DIST_ENA_6 14 14 CULL_DIST_ENA_7 15 15 USE_VTX_POINT_SIZE 16 16 USE_VTX_EDGE_FLAG 17 17 USE_VTX_RENDER_TARGET_INDX 18 18 USE_VTX_VIEWPORT_INDX 19 19 USE_VTX_KILL_FLAG 20 20 VS_OUT_MISC_VEC_ENA 21 21 VS_OUT_CCDIST0_VEC_ENA 22 22 VS_OUT_CCDIST1_VEC_ENA 23 23 VS_OUT_MISC_SIDE_BUS_ENA 24 24 USE_VTX_GS_CUT_FLAG 25 25 USE_VTX_LINE_WIDTH 26 26 USE_VTX_SHD_OBJPRIM_ID 27 27 regPA_CL_NANINF_CNTL 0 0x208 16 0 1 VTE_XY_INF_DISCARD 0 0 VTE_Z_INF_DISCARD 1 1 VTE_W_INF_DISCARD 2 2 VTE_0XNANINF_IS_0 3 3 VTE_XY_NAN_RETAIN 4 4 VTE_Z_NAN_RETAIN 5 5 VTE_W_NAN_RETAIN 6 6 VTE_W_RECIP_NAN_IS_0 7 7 VS_XY_NAN_TO_INF 8 8 VS_XY_INF_RETAIN 9 9 VS_Z_NAN_TO_INF 10 10 VS_Z_INF_RETAIN 11 11 VS_W_NAN_TO_INF 12 12 VS_W_INF_RETAIN 13 13 VS_CLIP_DIST_INF_DISCARD 14 14 VTE_NO_OUTPUT_NEG_0 20 20 regPA_SU_LINE_STIPPLE_CNTL 0 0x209 4 0 1 LINE_STIPPLE_RESET 0 1 EXPAND_FULL_LENGTH 2 2 FRACTIONAL_ACCUM 3 3 DIAMOND_ADJUST 4 4 regPA_SU_LINE_STIPPLE_SCALE 0 0x20a 1 0 1 LINE_STIPPLE_SCALE 0 31 regPA_SU_PRIM_FILTER_CNTL 0 0x20b 11 0 1 TRIANGLE_FILTER_DISABLE 0 0 LINE_FILTER_DISABLE 1 1 POINT_FILTER_DISABLE 2 2 RECTANGLE_FILTER_DISABLE 3 3 TRIANGLE_EXPAND_ENA 4 4 LINE_EXPAND_ENA 5 5 POINT_EXPAND_ENA 6 6 RECTANGLE_EXPAND_ENA 7 7 PRIM_EXPAND_CONSTANT 8 15 XMAX_RIGHT_EXCLUSION 30 30 YMAX_BOTTOM_EXCLUSION 31 31 regPA_SU_SMALL_PRIM_FILTER_CNTL 0 0x20c 5 0 1 SMALL_PRIM_FILTER_ENABLE 0 0 TRIANGLE_FILTER_DISABLE 1 1 LINE_FILTER_DISABLE 2 2 POINT_FILTER_DISABLE 3 3 RECTANGLE_FILTER_DISABLE 4 4 regPA_CL_OBJPRIM_ID_CNTL 0 0x20d 3 0 1 OBJ_ID_SEL 0 0 ADD_PIPED_PRIM_ID 1 1 EN_32BIT_OBJPRIMID 2 2 regPA_CL_NGG_CNTL 0 0x20e 2 0 1 VERTEX_REUSE_OFF 0 0 INDEX_BUF_EDGE_FLAG_ENA 1 1 regPA_SU_OVER_RASTERIZATION_CNTL 0 0x20f 5 0 1 DISCARD_0_AREA_TRIANGLES 0 0 DISCARD_0_AREA_LINES 1 1 DISCARD_0_AREA_POINTS 2 2 DISCARD_0_AREA_RECTANGLES 3 3 USE_PROVOKING_ZW 4 4 regPA_STEREO_CNTL 0 0x210 6 0 1 EN_STEREO 0 0 STEREO_MODE 1 4 RT_SLICE_MODE 5 7 RT_SLICE_OFFSET 8 9 VP_ID_MODE 10 12 VP_ID_OFFSET 13 16 regPA_SU_POINT_SIZE 0 0x280 2 0 1 HEIGHT 0 15 WIDTH 16 31 regPA_SU_POINT_MINMAX 0 0x281 2 0 1 MIN_SIZE 0 15 MAX_SIZE 16 31 regPA_SU_LINE_CNTL 0 0x282 1 0 1 WIDTH 0 15 regPA_SC_LINE_STIPPLE 0 0x283 4 0 1 LINE_PATTERN 0 15 REPEAT_COUNT 16 23 PATTERN_BIT_ORDER 28 28 AUTO_RESET_CNTL 29 30 regVGT_OUTPUT_PATH_CNTL 0 0x284 1 0 1 PATH_SELECT 0 2 regVGT_HOS_CNTL 0 0x285 1 0 1 TESS_MODE 0 1 regVGT_HOS_MAX_TESS_LEVEL 0 0x286 1 0 1 MAX_TESS 0 31 regVGT_HOS_MIN_TESS_LEVEL 0 0x287 1 0 1 MIN_TESS 0 31 regVGT_HOS_REUSE_DEPTH 0 0x288 1 0 1 REUSE_DEPTH 0 7 regVGT_GROUP_PRIM_TYPE 0 0x289 4 0 1 PRIM_TYPE 0 4 RETAIN_ORDER 14 14 RETAIN_QUADS 15 15 PRIM_ORDER 16 18 regVGT_GROUP_FIRST_DECR 0 0x28a 1 0 1 FIRST_DECR 0 3 regVGT_GROUP_DECR 0 0x28b 1 0 1 DECR 0 3 regVGT_GROUP_VECT_0_CNTL 0 0x28c 6 0 1 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 regVGT_GROUP_VECT_1_CNTL 0 0x28d 6 0 1 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 regVGT_GROUP_VECT_0_FMT_CNTL 0 0x28e 8 0 1 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 regVGT_GROUP_VECT_1_FMT_CNTL 0 0x28f 8 0 1 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 regVGT_GS_MODE 0 0x290 15 0 1 MODE 0 2 RESERVED_0 3 3 CUT_MODE 4 5 RESERVED_1 6 10 GS_C_PACK_EN 11 11 RESERVED_2 12 12 ES_PASSTHRU 13 13 RESERVED_3 14 14 RESERVED_4 15 15 RESERVED_5 16 16 PARTIAL_THD_AT_EOI 17 17 SUPPRESS_CUTS 18 18 ES_WRITE_OPTIMIZE 19 19 GS_WRITE_OPTIMIZE 20 20 ONCHIP 21 22 regVGT_GS_ONCHIP_CNTL 0 0x291 3 0 1 ES_VERTS_PER_SUBGRP 0 10 GS_PRIMS_PER_SUBGRP 11 21 GS_INST_PRIMS_IN_SUBGRP 22 31 regPA_SC_MODE_CNTL_0 0 0x292 7 0 1 MSAA_ENABLE 0 0 VPORT_SCISSOR_ENABLE 1 1 LINE_STIPPLE_ENABLE 2 2 SEND_UNLIT_STILES_TO_PKR 3 3 SCALE_LINE_WIDTH_PAD 4 4 ALTERNATE_RBS_PER_TILE 5 5 COARSE_TILE_STARTS_ON_EVEN_RB 6 6 regPA_SC_MODE_CNTL_1 0 0x293 24 0 1 WALK_SIZE 0 0 WALK_ALIGNMENT 1 1 WALK_ALIGN8_PRIM_FITS_ST 2 2 WALK_FENCE_ENABLE 3 3 WALK_FENCE_SIZE 4 6 SUPERTILE_WALK_ORDER_ENABLE 7 7 TILE_WALK_ORDER_ENABLE 8 8 TILE_COVER_DISABLE 9 9 TILE_COVER_NO_SCISSOR 10 10 ZMM_LINE_EXTENT 11 11 ZMM_LINE_OFFSET 12 12 ZMM_RECT_EXTENT 13 13 KILL_PIX_POST_HI_Z 14 14 KILL_PIX_POST_DETAIL_MASK 15 15 PS_ITER_SAMPLE 16 16 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE 17 17 MULTI_GPU_SUPERTILE_ENABLE 18 18 GPU_ID_OVERRIDE_ENABLE 19 19 GPU_ID_OVERRIDE 20 23 MULTI_GPU_PRIM_DISCARD_ENABLE 24 24 FORCE_EOV_CNTDWN_ENABLE 25 25 FORCE_EOV_REZ_ENABLE 26 26 OUT_OF_ORDER_PRIMITIVE_ENABLE 27 27 OUT_OF_ORDER_WATER_MARK 28 30 regVGT_ENHANCE 0 0x294 1 0 1 MISC 0 31 regVGT_GS_PER_ES 0 0x295 1 0 1 GS_PER_ES 0 10 regVGT_ES_PER_GS 0 0x296 1 0 1 ES_PER_GS 0 10 regVGT_GS_PER_VS 0 0x297 1 0 1 GS_PER_VS 0 3 regVGT_GSVS_RING_OFFSET_1 0 0x298 1 0 1 OFFSET 0 14 regVGT_GSVS_RING_OFFSET_2 0 0x299 1 0 1 OFFSET 0 14 regVGT_GSVS_RING_OFFSET_3 0 0x29a 1 0 1 OFFSET 0 14 regVGT_GS_OUT_PRIM_TYPE 0 0x29b 5 0 1 OUTPRIM_TYPE 0 5 OUTPRIM_TYPE_1 8 13 OUTPRIM_TYPE_2 16 21 OUTPRIM_TYPE_3 22 27 UNIQUE_TYPE_PER_STREAM 31 31 regIA_ENHANCE 0 0x29c 1 0 1 MISC 0 31 regVGT_DMA_SIZE 0 0x29d 1 0 1 NUM_INDICES 0 31 regVGT_DMA_MAX_SIZE 0 0x29e 1 0 1 MAX_SIZE 0 31 regVGT_DMA_INDEX_TYPE 0 0x29f 7 0 1 INDEX_TYPE 0 1 SWAP_MODE 2 3 BUF_TYPE 4 5 RDREQ_POLICY 6 6 PRIMGEN_EN 8 8 NOT_EOP 9 9 REQ_PATH 10 10 regWD_ENHANCE 0 0x2a0 1 0 1 MISC 0 31 regVGT_PRIMITIVEID_EN 0 0x2a1 3 0 1 PRIMITIVEID_EN 0 0 DISABLE_RESET_ON_EOI 1 1 NGG_DISABLE_PROVOK_REUSE 2 2 regVGT_DMA_NUM_INSTANCES 0 0x2a2 1 0 1 NUM_INSTANCES 0 31 regVGT_PRIMITIVEID_RESET 0 0x2a3 1 0 1 VALUE 0 31 regVGT_EVENT_INITIATOR 0 0x2a4 3 0 1 EVENT_TYPE 0 5 ADDRESS_HI 10 26 EXTENDED_EVENT 27 27 regVGT_GS_MAX_PRIMS_PER_SUBGROUP 0 0x2a5 1 0 1 MAX_PRIMS_PER_SUBGROUP 0 15 regVGT_DRAW_PAYLOAD_CNTL 0 0x2a6 4 0 1 OBJPRIM_ID_EN 0 0 EN_REG_RT_INDEX 1 1 EN_PIPELINE_PRIMID 2 2 OBJECT_ID_INST_EN 3 3 regVGT_INSTANCE_STEP_RATE_0 0 0x2a8 1 0 1 STEP_RATE 0 31 regVGT_INSTANCE_STEP_RATE_1 0 0x2a9 1 0 1 STEP_RATE 0 31 regIA_MULTI_VGT_PARAM_BC 0 0x2aa 0 0 1 regVGT_ESGS_RING_ITEMSIZE 0 0x2ab 1 0 1 ITEMSIZE 0 14 regVGT_GSVS_RING_ITEMSIZE 0 0x2ac 1 0 1 ITEMSIZE 0 14 regVGT_REUSE_OFF 0 0x2ad 1 0 1 REUSE_OFF 0 0 regVGT_VTX_CNT_EN 0 0x2ae 1 0 1 VTX_CNT_EN 0 0 regDB_HTILE_SURFACE 0 0x2af 8 0 1 FULL_CACHE 1 1 HTILE_USES_PRELOAD_WIN 2 2 PRELOAD 3 3 PREFETCH_WIDTH 4 9 PREFETCH_HEIGHT 10 15 DST_OUTSIDE_ZERO_TO_ONE 16 16 PIPE_ALIGNED 18 18 RB_ALIGNED 19 19 regDB_SRESULTS_COMPARE_STATE0 0 0x2b0 4 0 1 COMPAREFUNC0 0 2 COMPAREVALUE0 4 11 COMPAREMASK0 12 19 ENABLE0 24 24 regDB_SRESULTS_COMPARE_STATE1 0 0x2b1 4 0 1 COMPAREFUNC1 0 2 COMPAREVALUE1 4 11 COMPAREMASK1 12 19 ENABLE1 24 24 regDB_PRELOAD_CONTROL 0 0x2b2 4 0 1 START_X 0 7 START_Y 8 15 MAX_X 16 23 MAX_Y 24 31 regVGT_STRMOUT_BUFFER_SIZE_0 0 0x2b4 1 0 1 SIZE 0 31 regVGT_STRMOUT_VTX_STRIDE_0 0 0x2b5 1 0 1 STRIDE 0 9 regVGT_STRMOUT_BUFFER_OFFSET_0 0 0x2b7 1 0 1 OFFSET 0 31 regVGT_STRMOUT_BUFFER_SIZE_1 0 0x2b8 1 0 1 SIZE 0 31 regVGT_STRMOUT_VTX_STRIDE_1 0 0x2b9 1 0 1 STRIDE 0 9 regVGT_STRMOUT_BUFFER_OFFSET_1 0 0x2bb 1 0 1 OFFSET 0 31 regVGT_STRMOUT_BUFFER_SIZE_2 0 0x2bc 1 0 1 SIZE 0 31 regVGT_STRMOUT_VTX_STRIDE_2 0 0x2bd 1 0 1 STRIDE 0 9 regVGT_STRMOUT_BUFFER_OFFSET_2 0 0x2bf 1 0 1 OFFSET 0 31 regVGT_STRMOUT_BUFFER_SIZE_3 0 0x2c0 1 0 1 SIZE 0 31 regVGT_STRMOUT_VTX_STRIDE_3 0 0x2c1 1 0 1 STRIDE 0 9 regVGT_STRMOUT_BUFFER_OFFSET_3 0 0x2c3 1 0 1 OFFSET 0 31 regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0 0x2ca 1 0 1 OFFSET 0 31 regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0 0x2cb 1 0 1 SIZE 0 31 regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0 0x2cc 1 0 1 VERTEX_STRIDE 0 8 regVGT_GS_MAX_VERT_OUT 0 0x2ce 1 0 1 MAX_VERT_OUT 0 10 regVGT_TESS_DISTRIBUTION 0 0x2d4 5 0 1 ACCUM_ISOLINE 0 7 ACCUM_TRI 8 15 ACCUM_QUAD 16 23 DONUT_SPLIT 24 28 TRAP_SPLIT 29 31 regVGT_SHADER_STAGES_EN 0 0x2d5 13 0 1 LS_EN 0 1 HS_EN 2 2 ES_EN 3 4 GS_EN 5 5 VS_EN 6 7 DISPATCH_DRAW_EN 9 9 DIS_DEALLOC_ACCUM_0 10 10 DIS_DEALLOC_ACCUM_1 11 11 VS_WAVE_ID_EN 12 12 PRIMGEN_EN 13 13 ORDERED_ID_MODE 14 14 MAX_PRIMGRP_IN_WAVE 15 18 GS_FAST_LAUNCH 19 20 regVGT_LS_HS_CONFIG 0 0x2d6 3 0 1 NUM_PATCHES 0 7 HS_NUM_INPUT_CP 8 13 HS_NUM_OUTPUT_CP 14 19 regVGT_GS_VERT_ITEMSIZE 0 0x2d7 1 0 1 ITEMSIZE 0 14 regVGT_GS_VERT_ITEMSIZE_1 0 0x2d8 1 0 1 ITEMSIZE 0 14 regVGT_GS_VERT_ITEMSIZE_2 0 0x2d9 1 0 1 ITEMSIZE 0 14 regVGT_GS_VERT_ITEMSIZE_3 0 0x2da 1 0 1 ITEMSIZE 0 14 regVGT_TF_PARAM 0 0x2db 7 0 1 TYPE 0 1 PARTITIONING 2 4 TOPOLOGY 5 7 DEPRECATED 9 9 DISABLE_DONUTS 14 14 RDREQ_POLICY 15 15 DISTRIBUTION_MODE 17 18 regDB_ALPHA_TO_MASK 0 0x2dc 6 0 1 ALPHA_TO_MASK_ENABLE 0 0 ALPHA_TO_MASK_OFFSET0 8 9 ALPHA_TO_MASK_OFFSET1 10 11 ALPHA_TO_MASK_OFFSET2 12 13 ALPHA_TO_MASK_OFFSET3 14 15 OFFSET_ROUND 16 16 regVGT_DISPATCH_DRAW_INDEX 0 0x2dd 1 0 1 MATCH_INDEX 0 31 regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0 0x2de 2 0 1 POLY_OFFSET_NEG_NUM_DB_BITS 0 7 POLY_OFFSET_DB_IS_FLOAT_FMT 8 8 regPA_SU_POLY_OFFSET_CLAMP 0 0x2df 1 0 1 CLAMP 0 31 regPA_SU_POLY_OFFSET_FRONT_SCALE 0 0x2e0 1 0 1 SCALE 0 31 regPA_SU_POLY_OFFSET_FRONT_OFFSET 0 0x2e1 1 0 1 OFFSET 0 31 regPA_SU_POLY_OFFSET_BACK_SCALE 0 0x2e2 1 0 1 SCALE 0 31 regPA_SU_POLY_OFFSET_BACK_OFFSET 0 0x2e3 1 0 1 OFFSET 0 31 regVGT_GS_INSTANCE_CNT 0 0x2e4 2 0 1 ENABLE 0 0 CNT 2 8 regVGT_STRMOUT_CONFIG 0 0x2e5 8 0 1 STREAMOUT_0_EN 0 0 STREAMOUT_1_EN 1 1 STREAMOUT_2_EN 2 2 STREAMOUT_3_EN 3 3 RAST_STREAM 4 6 EN_PRIMS_NEEDED_CNT 7 7 RAST_STREAM_MASK 8 11 USE_RAST_STREAM_MASK 31 31 regVGT_STRMOUT_BUFFER_CONFIG 0 0x2e6 4 0 1 STREAM_0_BUFFER_EN 0 3 STREAM_1_BUFFER_EN 4 7 STREAM_2_BUFFER_EN 8 11 STREAM_3_BUFFER_EN 12 15 regVGT_DMA_EVENT_INITIATOR 0 0x2e7 3 0 1 EVENT_TYPE 0 5 ADDRESS_HI 10 26 EXTENDED_EVENT 27 27 regPA_SC_CENTROID_PRIORITY_0 0 0x2f5 8 0 1 DISTANCE_0 0 3 DISTANCE_1 4 7 DISTANCE_2 8 11 DISTANCE_3 12 15 DISTANCE_4 16 19 DISTANCE_5 20 23 DISTANCE_6 24 27 DISTANCE_7 28 31 regPA_SC_CENTROID_PRIORITY_1 0 0x2f6 8 0 1 DISTANCE_8 0 3 DISTANCE_9 4 7 DISTANCE_10 8 11 DISTANCE_11 12 15 DISTANCE_12 16 19 DISTANCE_13 20 23 DISTANCE_14 24 27 DISTANCE_15 28 31 regPA_SC_LINE_CNTL 0 0x2f7 5 0 1 EXPAND_LINE_WIDTH 9 9 LAST_PIXEL 10 10 PERPENDICULAR_ENDCAP_ENA 11 11 DX10_DIAMOND_TEST_ENA 12 12 EXTRA_DX_DY_PRECISION 13 13 regPA_SC_AA_CONFIG 0 0x2f8 6 0 1 MSAA_NUM_SAMPLES 0 2 AA_MASK_CENTROID_DTMN 4 4 MAX_SAMPLE_DIST 13 16 MSAA_EXPOSED_SAMPLES 20 22 DETAIL_TO_EXPOSED_MODE 24 25 COVERAGE_TO_SHADER_SELECT 26 27 regPA_SU_VTX_CNTL 0 0x2f9 3 0 1 PIX_CENTER 0 0 ROUND_MODE 1 2 QUANT_MODE 3 5 regPA_CL_GB_VERT_CLIP_ADJ 0 0x2fa 1 0 1 DATA_REGISTER 0 31 regPA_CL_GB_VERT_DISC_ADJ 0 0x2fb 1 0 1 DATA_REGISTER 0 31 regPA_CL_GB_HORZ_CLIP_ADJ 0 0x2fc 1 0 1 DATA_REGISTER 0 31 regPA_CL_GB_HORZ_DISC_ADJ 0 0x2fd 1 0 1 DATA_REGISTER 0 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0 0x2fe 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0 0x2ff 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0 0x300 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0 0x301 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0 0x302 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0 0x303 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0 0x304 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0 0x305 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0 0x306 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0 0x307 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0 0x308 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0 0x309 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0 0x30a 8 0 1 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0 0x30b 8 0 1 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0 0x30c 8 0 1 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0 0x30d 8 0 1 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 regPA_SC_AA_MASK_X0Y0_X1Y0 0 0x30e 2 0 1 AA_MASK_X0Y0 0 15 AA_MASK_X1Y0 16 31 regPA_SC_AA_MASK_X0Y1_X1Y1 0 0x30f 2 0 1 AA_MASK_X0Y1 0 15 AA_MASK_X1Y1 16 31 regPA_SC_SHADER_CONTROL 0 0x310 3 0 1 REALIGN_DQUADS_AFTER_N_WAVES 0 1 LOAD_COLLISION_WAVEID 2 2 LOAD_INTRAWAVE_COLLISION 3 3 regPA_SC_BINNER_CNTL_0 0 0x311 11 0 1 BINNING_MODE 0 1 BIN_SIZE_X 2 2 BIN_SIZE_Y 3 3 BIN_SIZE_X_EXTEND 4 6 BIN_SIZE_Y_EXTEND 7 9 CONTEXT_STATES_PER_BIN 10 12 PERSISTENT_STATES_PER_BIN 13 17 DISABLE_START_OF_PRIM 18 18 FPOVS_PER_BATCH 19 26 OPTIMAL_BIN_SELECTION 27 27 FLUSH_ON_BINNING_TRANSITION 28 28 regPA_SC_BINNER_CNTL_1 0 0x312 2 0 1 MAX_ALLOC_COUNT 0 15 MAX_PRIM_PER_BATCH 16 31 regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0 0x313 18 0 1 OVER_RAST_ENABLE 0 0 OVER_RAST_SAMPLE_SELECT 1 4 UNDER_RAST_ENABLE 5 5 UNDER_RAST_SAMPLE_SELECT 6 9 PBB_UNCERTAINTY_REGION_ENABLE 10 10 ZMM_TRI_EXTENT 11 11 ZMM_TRI_OFFSET 12 12 OVERRIDE_OVER_RAST_INNER_TO_NORMAL 13 13 OVERRIDE_UNDER_RAST_INNER_TO_NORMAL 14 14 DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE 15 15 UNCERTAINTY_REGION_MODE 16 17 OUTER_UNCERTAINTY_EDGERULE_OVERRIDE 18 18 INNER_UNCERTAINTY_EDGERULE_OVERRIDE 19 19 NULL_SQUAD_AA_MASK_ENABLE 20 20 COVERAGE_AA_MASK_ENABLE 21 21 PREZ_AA_MASK_ENABLE 22 22 POSTZ_AA_MASK_ENABLE 23 23 CENTROID_SAMPLE_OVERRIDE 24 24 regPA_SC_NGG_MODE_CNTL 0 0x314 1 0 1 MAX_DEALLOCS_IN_WAVE 0 10 regVGT_VERTEX_REUSE_BLOCK_CNTL 0 0x316 1 0 1 VTX_REUSE_DEPTH 0 7 regVGT_OUT_DEALLOC_CNTL 0 0x317 1 0 1 DEALLOC_DIST 0 6 regCB_COLOR0_BASE 0 0x318 1 0 1 BASE_256B 0 31 regCB_COLOR0_BASE_EXT 0 0x319 1 0 1 BASE_256B 0 7 regCB_COLOR0_ATTRIB2 0 0x31a 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR0_VIEW 0 0x31b 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR0_INFO 0 0x31c 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR0_ATTRIB 0 0x31d 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR0_DCC_CONTROL 0 0x31e 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR0_CMASK 0 0x31f 1 0 1 BASE_256B 0 31 regCB_COLOR0_CMASK_BASE_EXT 0 0x320 1 0 1 BASE_256B 0 7 regCB_COLOR0_FMASK 0 0x321 1 0 1 BASE_256B 0 31 regCB_COLOR0_FMASK_BASE_EXT 0 0x322 1 0 1 BASE_256B 0 7 regCB_COLOR0_CLEAR_WORD0 0 0x323 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR0_CLEAR_WORD1 0 0x324 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR0_DCC_BASE 0 0x325 1 0 1 BASE_256B 0 31 regCB_COLOR0_DCC_BASE_EXT 0 0x326 1 0 1 BASE_256B 0 7 regCB_COLOR1_BASE 0 0x327 1 0 1 BASE_256B 0 31 regCB_COLOR1_BASE_EXT 0 0x328 1 0 1 BASE_256B 0 7 regCB_COLOR1_ATTRIB2 0 0x329 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR1_VIEW 0 0x32a 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR1_INFO 0 0x32b 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR1_ATTRIB 0 0x32c 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR1_DCC_CONTROL 0 0x32d 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR1_CMASK 0 0x32e 1 0 1 BASE_256B 0 31 regCB_COLOR1_CMASK_BASE_EXT 0 0x32f 1 0 1 BASE_256B 0 7 regCB_COLOR1_FMASK 0 0x330 1 0 1 BASE_256B 0 31 regCB_COLOR1_FMASK_BASE_EXT 0 0x331 1 0 1 BASE_256B 0 7 regCB_COLOR1_CLEAR_WORD0 0 0x332 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR1_CLEAR_WORD1 0 0x333 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR1_DCC_BASE 0 0x334 1 0 1 BASE_256B 0 31 regCB_COLOR1_DCC_BASE_EXT 0 0x335 1 0 1 BASE_256B 0 7 regCB_COLOR2_BASE 0 0x336 1 0 1 BASE_256B 0 31 regCB_COLOR2_BASE_EXT 0 0x337 1 0 1 BASE_256B 0 7 regCB_COLOR2_ATTRIB2 0 0x338 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR2_VIEW 0 0x339 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR2_INFO 0 0x33a 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR2_ATTRIB 0 0x33b 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR2_DCC_CONTROL 0 0x33c 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR2_CMASK 0 0x33d 1 0 1 BASE_256B 0 31 regCB_COLOR2_CMASK_BASE_EXT 0 0x33e 1 0 1 BASE_256B 0 7 regCB_COLOR2_FMASK 0 0x33f 1 0 1 BASE_256B 0 31 regCB_COLOR2_FMASK_BASE_EXT 0 0x340 1 0 1 BASE_256B 0 7 regCB_COLOR2_CLEAR_WORD0 0 0x341 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR2_CLEAR_WORD1 0 0x342 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR2_DCC_BASE 0 0x343 1 0 1 BASE_256B 0 31 regCB_COLOR2_DCC_BASE_EXT 0 0x344 1 0 1 BASE_256B 0 7 regCB_COLOR3_BASE 0 0x345 1 0 1 BASE_256B 0 31 regCB_COLOR3_BASE_EXT 0 0x346 1 0 1 BASE_256B 0 7 regCB_COLOR3_ATTRIB2 0 0x347 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR3_VIEW 0 0x348 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR3_INFO 0 0x349 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR3_ATTRIB 0 0x34a 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR3_DCC_CONTROL 0 0x34b 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR3_CMASK 0 0x34c 1 0 1 BASE_256B 0 31 regCB_COLOR3_CMASK_BASE_EXT 0 0x34d 1 0 1 BASE_256B 0 7 regCB_COLOR3_FMASK 0 0x34e 1 0 1 BASE_256B 0 31 regCB_COLOR3_FMASK_BASE_EXT 0 0x34f 1 0 1 BASE_256B 0 7 regCB_COLOR3_CLEAR_WORD0 0 0x350 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR3_CLEAR_WORD1 0 0x351 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR3_DCC_BASE 0 0x352 1 0 1 BASE_256B 0 31 regCB_COLOR3_DCC_BASE_EXT 0 0x353 1 0 1 BASE_256B 0 7 regCB_COLOR4_BASE 0 0x354 1 0 1 BASE_256B 0 31 regCB_COLOR4_BASE_EXT 0 0x355 1 0 1 BASE_256B 0 7 regCB_COLOR4_ATTRIB2 0 0x356 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR4_VIEW 0 0x357 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR4_INFO 0 0x358 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR4_ATTRIB 0 0x359 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR4_DCC_CONTROL 0 0x35a 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR4_CMASK 0 0x35b 1 0 1 BASE_256B 0 31 regCB_COLOR4_CMASK_BASE_EXT 0 0x35c 1 0 1 BASE_256B 0 7 regCB_COLOR4_FMASK 0 0x35d 1 0 1 BASE_256B 0 31 regCB_COLOR4_FMASK_BASE_EXT 0 0x35e 1 0 1 BASE_256B 0 7 regCB_COLOR4_CLEAR_WORD0 0 0x35f 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR4_CLEAR_WORD1 0 0x360 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR4_DCC_BASE 0 0x361 1 0 1 BASE_256B 0 31 regCB_COLOR4_DCC_BASE_EXT 0 0x362 1 0 1 BASE_256B 0 7 regCB_COLOR5_BASE 0 0x363 1 0 1 BASE_256B 0 31 regCB_COLOR5_BASE_EXT 0 0x364 1 0 1 BASE_256B 0 7 regCB_COLOR5_ATTRIB2 0 0x365 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR5_VIEW 0 0x366 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR5_INFO 0 0x367 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR5_ATTRIB 0 0x368 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR5_DCC_CONTROL 0 0x369 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR5_CMASK 0 0x36a 1 0 1 BASE_256B 0 31 regCB_COLOR5_CMASK_BASE_EXT 0 0x36b 1 0 1 BASE_256B 0 7 regCB_COLOR5_FMASK 0 0x36c 1 0 1 BASE_256B 0 31 regCB_COLOR5_FMASK_BASE_EXT 0 0x36d 1 0 1 BASE_256B 0 7 regCB_COLOR5_CLEAR_WORD0 0 0x36e 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR5_CLEAR_WORD1 0 0x36f 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR5_DCC_BASE 0 0x370 1 0 1 BASE_256B 0 31 regCB_COLOR5_DCC_BASE_EXT 0 0x371 1 0 1 BASE_256B 0 7 regCB_COLOR6_BASE 0 0x372 1 0 1 BASE_256B 0 31 regCB_COLOR6_BASE_EXT 0 0x373 1 0 1 BASE_256B 0 7 regCB_COLOR6_ATTRIB2 0 0x374 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR6_VIEW 0 0x375 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR6_INFO 0 0x376 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR6_ATTRIB 0 0x377 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR6_DCC_CONTROL 0 0x378 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR6_CMASK 0 0x379 1 0 1 BASE_256B 0 31 regCB_COLOR6_CMASK_BASE_EXT 0 0x37a 1 0 1 BASE_256B 0 7 regCB_COLOR6_FMASK 0 0x37b 1 0 1 BASE_256B 0 31 regCB_COLOR6_FMASK_BASE_EXT 0 0x37c 1 0 1 BASE_256B 0 7 regCB_COLOR6_CLEAR_WORD0 0 0x37d 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR6_CLEAR_WORD1 0 0x37e 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR6_DCC_BASE 0 0x37f 1 0 1 BASE_256B 0 31 regCB_COLOR6_DCC_BASE_EXT 0 0x380 1 0 1 BASE_256B 0 7 regCB_COLOR7_BASE 0 0x381 1 0 1 BASE_256B 0 31 regCB_COLOR7_BASE_EXT 0 0x382 1 0 1 BASE_256B 0 7 regCB_COLOR7_ATTRIB2 0 0x383 3 0 1 MIP0_HEIGHT 0 13 MIP0_WIDTH 14 27 MAX_MIP 28 31 regCB_COLOR7_VIEW 0 0x384 3 0 1 SLICE_START 0 10 SLICE_MAX 13 23 MIP_LEVEL 24 27 regCB_COLOR7_INFO 0 0x385 16 0 1 ENDIAN 0 1 FORMAT 2 6 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 FMASK_COMPRESS_1FRAG_ONLY 27 27 DCC_ENABLE 28 28 CMASK_ADDR_TYPE 29 30 regCB_COLOR7_ATTRIB 0 0x386 10 0 1 MIP0_DEPTH 0 10 META_LINEAR 11 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 COLOR_SW_MODE 18 22 FMASK_SW_MODE 23 27 RESOURCE_TYPE 28 29 RB_ALIGNED 30 30 PIPE_ALIGNED 31 31 regCB_COLOR7_DCC_CONTROL 0 0x387 10 0 1 OVERWRITE_COMBINER_DISABLE 0 0 MAX_UNCOMPRESSED_BLOCK_SIZE 2 3 MIN_COMPRESSED_BLOCK_SIZE 4 4 MAX_COMPRESSED_BLOCK_SIZE 5 6 COLOR_TRANSFORM 7 8 INDEPENDENT_64B_BLOCKS 9 9 LOSSY_RGB_PRECISION 10 13 LOSSY_ALPHA_PRECISION 14 17 DISABLE_CONSTANT_ENCODE_REG 18 18 ENABLE_CONSTANT_ENCODE_REG_WRITE 19 19 regCB_COLOR7_CMASK 0 0x388 1 0 1 BASE_256B 0 31 regCB_COLOR7_CMASK_BASE_EXT 0 0x389 1 0 1 BASE_256B 0 7 regCB_COLOR7_FMASK 0 0x38a 1 0 1 BASE_256B 0 31 regCB_COLOR7_FMASK_BASE_EXT 0 0x38b 1 0 1 BASE_256B 0 7 regCB_COLOR7_CLEAR_WORD0 0 0x38c 1 0 1 CLEAR_WORD0 0 31 regCB_COLOR7_CLEAR_WORD1 0 0x38d 1 0 1 CLEAR_WORD1 0 31 regCB_COLOR7_DCC_BASE 0 0x38e 1 0 1 BASE_256B 0 31 regCB_COLOR7_DCC_BASE_EXT 0 0x38f 1 0 1 BASE_256B 0 7 regCP_EOP_DONE_ADDR_LO 0 0x2000 1 0 1 ADDR_LO 2 31 regCP_EOP_DONE_ADDR_HI 0 0x2001 1 0 1 ADDR_HI 0 15 regCP_EOP_DONE_DATA_LO 0 0x2002 1 0 1 DATA_LO 0 31 regCP_EOP_DONE_DATA_HI 0 0x2003 1 0 1 DATA_HI 0 31 regCP_EOP_LAST_FENCE_LO 0 0x2004 1 0 1 LAST_FENCE_LO 0 31 regCP_EOP_LAST_FENCE_HI 0 0x2005 1 0 1 LAST_FENCE_HI 0 31 regCP_STREAM_OUT_ADDR_LO 0 0x2006 1 0 1 STREAM_OUT_ADDR_LO 2 31 regCP_STREAM_OUT_ADDR_HI 0 0x2007 1 0 1 STREAM_OUT_ADDR_HI 0 15 regCP_NUM_PRIM_WRITTEN_COUNT0_LO 0 0x2008 1 0 1 NUM_PRIM_WRITTEN_CNT0_LO 0 31 regCP_NUM_PRIM_WRITTEN_COUNT0_HI 0 0x2009 1 0 1 NUM_PRIM_WRITTEN_CNT0_HI 0 31 regCP_NUM_PRIM_NEEDED_COUNT0_LO 0 0x200a 1 0 1 NUM_PRIM_NEEDED_CNT0_LO 0 31 regCP_NUM_PRIM_NEEDED_COUNT0_HI 0 0x200b 1 0 1 NUM_PRIM_NEEDED_CNT0_HI 0 31 regCP_NUM_PRIM_WRITTEN_COUNT1_LO 0 0x200c 1 0 1 NUM_PRIM_WRITTEN_CNT1_LO 0 31 regCP_NUM_PRIM_WRITTEN_COUNT1_HI 0 0x200d 1 0 1 NUM_PRIM_WRITTEN_CNT1_HI 0 31 regCP_NUM_PRIM_NEEDED_COUNT1_LO 0 0x200e 1 0 1 NUM_PRIM_NEEDED_CNT1_LO 0 31 regCP_NUM_PRIM_NEEDED_COUNT1_HI 0 0x200f 1 0 1 NUM_PRIM_NEEDED_CNT1_HI 0 31 regCP_NUM_PRIM_WRITTEN_COUNT2_LO 0 0x2010 1 0 1 NUM_PRIM_WRITTEN_CNT2_LO 0 31 regCP_NUM_PRIM_WRITTEN_COUNT2_HI 0 0x2011 1 0 1 NUM_PRIM_WRITTEN_CNT2_HI 0 31 regCP_NUM_PRIM_NEEDED_COUNT2_LO 0 0x2012 1 0 1 NUM_PRIM_NEEDED_CNT2_LO 0 31 regCP_NUM_PRIM_NEEDED_COUNT2_HI 0 0x2013 1 0 1 NUM_PRIM_NEEDED_CNT2_HI 0 31 regCP_NUM_PRIM_WRITTEN_COUNT3_LO 0 0x2014 1 0 1 NUM_PRIM_WRITTEN_CNT3_LO 0 31 regCP_NUM_PRIM_WRITTEN_COUNT3_HI 0 0x2015 1 0 1 NUM_PRIM_WRITTEN_CNT3_HI 0 31 regCP_NUM_PRIM_NEEDED_COUNT3_LO 0 0x2016 1 0 1 NUM_PRIM_NEEDED_CNT3_LO 0 31 regCP_NUM_PRIM_NEEDED_COUNT3_HI 0 0x2017 1 0 1 NUM_PRIM_NEEDED_CNT3_HI 0 31 regCP_PIPE_STATS_ADDR_LO 0 0x2018 1 0 1 PIPE_STATS_ADDR_LO 2 31 regCP_PIPE_STATS_ADDR_HI 0 0x2019 1 0 1 PIPE_STATS_ADDR_HI 0 15 regCP_VGT_IAVERT_COUNT_LO 0 0x201a 1 0 1 IAVERT_COUNT_LO 0 31 regCP_VGT_IAVERT_COUNT_HI 0 0x201b 1 0 1 IAVERT_COUNT_HI 0 31 regCP_VGT_IAPRIM_COUNT_LO 0 0x201c 1 0 1 IAPRIM_COUNT_LO 0 31 regCP_VGT_IAPRIM_COUNT_HI 0 0x201d 1 0 1 IAPRIM_COUNT_HI 0 31 regCP_VGT_GSPRIM_COUNT_LO 0 0x201e 1 0 1 GSPRIM_COUNT_LO 0 31 regCP_VGT_GSPRIM_COUNT_HI 0 0x201f 1 0 1 GSPRIM_COUNT_HI 0 31 regCP_VGT_VSINVOC_COUNT_LO 0 0x2020 1 0 1 VSINVOC_COUNT_LO 0 31 regCP_VGT_VSINVOC_COUNT_HI 0 0x2021 1 0 1 VSINVOC_COUNT_HI 0 31 regCP_VGT_GSINVOC_COUNT_LO 0 0x2022 1 0 1 GSINVOC_COUNT_LO 0 31 regCP_VGT_GSINVOC_COUNT_HI 0 0x2023 1 0 1 GSINVOC_COUNT_HI 0 31 regCP_VGT_HSINVOC_COUNT_LO 0 0x2024 1 0 1 HSINVOC_COUNT_LO 0 31 regCP_VGT_HSINVOC_COUNT_HI 0 0x2025 1 0 1 HSINVOC_COUNT_HI 0 31 regCP_VGT_DSINVOC_COUNT_LO 0 0x2026 1 0 1 DSINVOC_COUNT_LO 0 31 regCP_VGT_DSINVOC_COUNT_HI 0 0x2027 1 0 1 DSINVOC_COUNT_HI 0 31 regCP_PA_CINVOC_COUNT_LO 0 0x2028 1 0 1 CINVOC_COUNT_LO 0 31 regCP_PA_CINVOC_COUNT_HI 0 0x2029 1 0 1 CINVOC_COUNT_HI 0 31 regCP_PA_CPRIM_COUNT_LO 0 0x202a 1 0 1 CPRIM_COUNT_LO 0 31 regCP_PA_CPRIM_COUNT_HI 0 0x202b 1 0 1 CPRIM_COUNT_HI 0 31 regCP_SC_PSINVOC_COUNT0_LO 0 0x202c 1 0 1 PSINVOC_COUNT0_LO 0 31 regCP_SC_PSINVOC_COUNT0_HI 0 0x202d 1 0 1 PSINVOC_COUNT0_HI 0 31 regCP_SC_PSINVOC_COUNT1_LO 0 0x202e 1 0 1 OBSOLETE 0 31 regCP_SC_PSINVOC_COUNT1_HI 0 0x202f 1 0 1 OBSOLETE 0 31 regCP_VGT_CSINVOC_COUNT_LO 0 0x2030 1 0 1 CSINVOC_COUNT_LO 0 31 regCP_VGT_CSINVOC_COUNT_HI 0 0x2031 1 0 1 CSINVOC_COUNT_HI 0 31 regCP_PIPE_STATS_CONTROL 0 0x203d 1 0 1 CACHE_POLICY 25 25 regCP_STREAM_OUT_CONTROL 0 0x203e 1 0 1 CACHE_POLICY 25 25 regCP_STRMOUT_CNTL 0 0x203f 1 0 1 OFFSET_UPDATE_DONE 0 0 regSCRATCH_REG0 0 0x2040 1 0 1 SCRATCH_REG0 0 31 regSCRATCH_REG1 0 0x2041 1 0 1 SCRATCH_REG1 0 31 regSCRATCH_REG2 0 0x2042 1 0 1 SCRATCH_REG2 0 31 regSCRATCH_REG3 0 0x2043 1 0 1 SCRATCH_REG3 0 31 regSCRATCH_REG4 0 0x2044 1 0 1 SCRATCH_REG4 0 31 regSCRATCH_REG5 0 0x2045 1 0 1 SCRATCH_REG5 0 31 regSCRATCH_REG6 0 0x2046 1 0 1 SCRATCH_REG6 0 31 regSCRATCH_REG7 0 0x2047 1 0 1 SCRATCH_REG7 0 31 regCP_APPEND_DATA_HI 0 0x204c 1 0 1 DATA 0 31 regCP_APPEND_LAST_CS_FENCE_HI 0 0x204d 1 0 1 LAST_FENCE 0 31 regCP_APPEND_LAST_PS_FENCE_HI 0 0x204e 1 0 1 LAST_FENCE 0 31 regSCRATCH_UMSK 0 0x2050 2 0 1 OBSOLETE_UMSK 0 7 OBSOLETE_SWAP 16 17 regSCRATCH_ADDR 0 0x2051 1 0 1 OBSOLETE_ADDR 0 31 regCP_PFP_ATOMIC_PREOP_LO 0 0x2052 1 0 1 ATOMIC_PREOP_LO 0 31 regCP_PFP_ATOMIC_PREOP_HI 0 0x2053 1 0 1 ATOMIC_PREOP_HI 0 31 regCP_PFP_GDS_ATOMIC0_PREOP_LO 0 0x2054 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 regCP_PFP_GDS_ATOMIC0_PREOP_HI 0 0x2055 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 regCP_PFP_GDS_ATOMIC1_PREOP_LO 0 0x2056 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 regCP_PFP_GDS_ATOMIC1_PREOP_HI 0 0x2057 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 regCP_APPEND_ADDR_LO 0 0x2058 1 0 1 MEM_ADDR_LO 2 31 regCP_APPEND_ADDR_HI 0 0x2059 4 0 1 MEM_ADDR_HI 0 15 CS_PS_SEL 16 16 CACHE_POLICY 25 25 COMMAND 29 31 regCP_APPEND_DATA_LO 0 0x205a 1 0 1 DATA 0 31 regCP_APPEND_LAST_CS_FENCE_LO 0 0x205b 1 0 1 LAST_FENCE 0 31 regCP_APPEND_LAST_PS_FENCE_LO 0 0x205c 1 0 1 LAST_FENCE 0 31 regCP_ATOMIC_PREOP_LO 0 0x205d 1 0 1 ATOMIC_PREOP_LO 0 31 regCP_ME_ATOMIC_PREOP_LO 0 0x205d 1 0 1 ATOMIC_PREOP_LO 0 31 regCP_ATOMIC_PREOP_HI 0 0x205e 1 0 1 ATOMIC_PREOP_HI 0 31 regCP_ME_ATOMIC_PREOP_HI 0 0x205e 1 0 1 ATOMIC_PREOP_HI 0 31 regCP_GDS_ATOMIC0_PREOP_LO 0 0x205f 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 regCP_ME_GDS_ATOMIC0_PREOP_LO 0 0x205f 1 0 1 GDS_ATOMIC0_PREOP_LO 0 31 regCP_GDS_ATOMIC0_PREOP_HI 0 0x2060 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 regCP_ME_GDS_ATOMIC0_PREOP_HI 0 0x2060 1 0 1 GDS_ATOMIC0_PREOP_HI 0 31 regCP_GDS_ATOMIC1_PREOP_LO 0 0x2061 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 regCP_ME_GDS_ATOMIC1_PREOP_LO 0 0x2061 1 0 1 GDS_ATOMIC1_PREOP_LO 0 31 regCP_GDS_ATOMIC1_PREOP_HI 0 0x2062 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 regCP_ME_GDS_ATOMIC1_PREOP_HI 0 0x2062 1 0 1 GDS_ATOMIC1_PREOP_HI 0 31 regCP_ME_MC_WADDR_LO 0 0x2069 1 0 1 ME_MC_WADDR_LO 2 31 regCP_ME_MC_WADDR_HI 0 0x206a 2 0 1 ME_MC_WADDR_HI 0 15 CACHE_POLICY 22 22 regCP_ME_MC_WDATA_LO 0 0x206b 1 0 1 ME_MC_WDATA_LO 0 31 regCP_ME_MC_WDATA_HI 0 0x206c 1 0 1 ME_MC_WDATA_HI 0 31 regCP_ME_MC_RADDR_LO 0 0x206d 1 0 1 ME_MC_RADDR_LO 2 31 regCP_ME_MC_RADDR_HI 0 0x206e 2 0 1 ME_MC_RADDR_HI 0 15 CACHE_POLICY 22 22 regCP_SEM_WAIT_TIMER 0 0x206f 1 0 1 SEM_WAIT_TIMER 0 31 regCP_SIG_SEM_ADDR_LO 0 0x2070 2 0 1 SEM_ADDR_SWAP 0 1 SEM_ADDR_LO 3 31 regCP_SIG_SEM_ADDR_HI 0 0x2071 5 0 1 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 regCP_WAIT_REG_MEM_TIMEOUT 0 0x2074 1 0 1 WAIT_REG_MEM_TIMEOUT 0 31 regCP_WAIT_SEM_ADDR_LO 0 0x2075 2 0 1 SEM_ADDR_SWAP 0 1 SEM_ADDR_LO 3 31 regCP_WAIT_SEM_ADDR_HI 0 0x2076 5 0 1 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 regCP_DMA_PFP_CONTROL 0 0x2077 5 0 1 MEMLOG_CLEAR 10 10 SRC_CACHE_POLICY 13 13 DST_SELECT 20 21 DST_CACHE_POLICY 25 25 SRC_SELECT 29 30 regCP_DMA_ME_CONTROL 0 0x2078 5 0 1 MEMLOG_CLEAR 10 10 SRC_CACHE_POLICY 13 13 DST_SELECT 20 21 DST_CACHE_POLICY 25 25 SRC_SELECT 29 30 regCP_COHER_BASE_HI 0 0x2079 1 0 1 COHER_BASE_HI_256B 0 7 regCP_COHER_START_DELAY 0 0x207b 1 0 1 START_DELAY_COUNT 0 5 regCP_COHER_CNTL 0 0x207c 13 0 1 TC_NC_ACTION_ENA 3 3 TC_WC_ACTION_ENA 4 4 TC_INV_METADATA_ACTION_ENA 5 5 TCL1_VOL_ACTION_ENA 15 15 TC_WB_ACTION_ENA 18 18 TCL1_ACTION_ENA 22 22 TC_ACTION_ENA 23 23 CB_ACTION_ENA 25 25 DB_ACTION_ENA 26 26 SH_KCACHE_ACTION_ENA 27 27 SH_KCACHE_VOL_ACTION_ENA 28 28 SH_ICACHE_ACTION_ENA 29 29 SH_KCACHE_WB_ACTION_ENA 30 30 regCP_COHER_SIZE 0 0x207d 1 0 1 COHER_SIZE_256B 0 31 regCP_COHER_BASE 0 0x207e 1 0 1 COHER_BASE_256B 0 31 regCP_COHER_STATUS 0 0x207f 2 0 1 MEID 24 25 STATUS 31 31 regCP_DMA_ME_SRC_ADDR 0 0x2080 1 0 1 SRC_ADDR 0 31 regCP_DMA_ME_SRC_ADDR_HI 0 0x2081 1 0 1 SRC_ADDR_HI 0 15 regCP_DMA_ME_DST_ADDR 0 0x2082 1 0 1 DST_ADDR 0 31 regCP_DMA_ME_DST_ADDR_HI 0 0x2083 1 0 1 DST_ADDR_HI 0 15 regCP_DMA_ME_COMMAND 0 0x2084 7 0 1 BYTE_COUNT 0 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 DIS_WC 31 31 regCP_DMA_PFP_SRC_ADDR 0 0x2085 1 0 1 SRC_ADDR 0 31 regCP_DMA_PFP_SRC_ADDR_HI 0 0x2086 1 0 1 SRC_ADDR_HI 0 15 regCP_DMA_PFP_DST_ADDR 0 0x2087 1 0 1 DST_ADDR 0 31 regCP_DMA_PFP_DST_ADDR_HI 0 0x2088 1 0 1 DST_ADDR_HI 0 15 regCP_DMA_PFP_COMMAND 0 0x2089 7 0 1 BYTE_COUNT 0 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 DIS_WC 31 31 regCP_DMA_CNTL 0 0x208a 6 0 1 UTCL1_FAULT_CONTROL 0 0 MIN_AVAILSZ 4 5 BUFFER_DEPTH 16 19 PIO_FIFO_EMPTY 28 28 PIO_FIFO_FULL 29 29 PIO_COUNT 30 31 regCP_DMA_READ_TAGS 0 0x208b 2 0 1 DMA_READ_TAG 0 25 DMA_READ_TAG_VALID 28 28 regCP_COHER_SIZE_HI 0 0x208c 1 0 1 COHER_SIZE_HI_256B 0 7 regCP_PFP_IB_CONTROL 0 0x208d 1 0 1 IB_EN 0 7 regCP_PFP_LOAD_CONTROL 0 0x208e 4 0 1 CONFIG_REG_EN 0 0 CNTX_REG_EN 1 1 SH_GFX_REG_EN 16 16 SH_CS_REG_EN 24 24 regCP_SCRATCH_INDEX 0 0x208f 1 0 1 SCRATCH_INDEX 0 7 regCP_SCRATCH_DATA 0 0x2090 1 0 1 SCRATCH_DATA 0 31 regCP_RB_OFFSET 0 0x2091 1 0 1 RB_OFFSET 0 19 regCP_IB2_OFFSET 0 0x2093 1 0 1 IB2_OFFSET 0 19 regCP_IB2_PREAMBLE_BEGIN 0 0x2096 1 0 1 IB2_PREAMBLE_BEGIN 0 19 regCP_IB2_PREAMBLE_END 0 0x2097 1 0 1 IB2_PREAMBLE_END 0 19 regCP_CE_IB1_OFFSET 0 0x2098 1 0 1 IB1_OFFSET 0 19 regCP_CE_IB2_OFFSET 0 0x2099 1 0 1 IB2_OFFSET 0 19 regCP_CE_COUNTER 0 0x209a 1 0 1 CONST_ENGINE_COUNT 0 31 regCP_CE_RB_OFFSET 0 0x209b 1 0 1 RB_OFFSET 0 19 regCP_CE_INIT_CMD_BUFSZ 0 0x20bd 1 0 1 INIT_CMD_REQSZ 0 11 regCP_CE_IB1_CMD_BUFSZ 0 0x20be 1 0 1 IB1_CMD_REQSZ 0 19 regCP_CE_IB2_CMD_BUFSZ 0 0x20bf 1 0 1 IB2_CMD_REQSZ 0 19 regCP_IB2_CMD_BUFSZ 0 0x20c1 1 0 1 IB2_CMD_REQSZ 0 19 regCP_ST_CMD_BUFSZ 0 0x20c2 1 0 1 ST_CMD_REQSZ 0 19 regCP_CE_INIT_BASE_LO 0 0x20c3 1 0 1 INIT_BASE_LO 5 31 regCP_CE_INIT_BASE_HI 0 0x20c4 1 0 1 INIT_BASE_HI 0 15 regCP_CE_INIT_BUFSZ 0 0x20c5 1 0 1 INIT_BUFSZ 0 11 regCP_CE_IB1_BASE_LO 0 0x20c6 1 0 1 IB1_BASE_LO 2 31 regCP_CE_IB1_BASE_HI 0 0x20c7 1 0 1 IB1_BASE_HI 0 15 regCP_CE_IB1_BUFSZ 0 0x20c8 1 0 1 IB1_BUFSZ 0 19 regCP_CE_IB2_BASE_LO 0 0x20c9 1 0 1 IB2_BASE_LO 2 31 regCP_CE_IB2_BASE_HI 0 0x20ca 1 0 1 IB2_BASE_HI 0 15 regCP_CE_IB2_BUFSZ 0 0x20cb 1 0 1 IB2_BUFSZ 0 19 regCP_IB2_BASE_LO 0 0x20cf 1 0 1 IB2_BASE_LO 2 31 regCP_IB2_BASE_HI 0 0x20d0 1 0 1 IB2_BASE_HI 0 15 regCP_IB2_BUFSZ 0 0x20d1 1 0 1 IB2_BUFSZ 0 19 regCP_ST_BASE_LO 0 0x20d2 1 0 1 ST_BASE_LO 2 31 regCP_ST_BASE_HI 0 0x20d3 1 0 1 ST_BASE_HI 0 15 regCP_ST_BUFSZ 0 0x20d4 1 0 1 ST_BUFSZ 0 19 regCP_EOP_DONE_EVENT_CNTL 0 0x20d5 4 0 1 WBINV_TC_OP 0 6 WBINV_ACTION_ENA 12 17 CACHE_POLICY 25 25 EXECUTE 28 28 regCP_EOP_DONE_DATA_CNTL 0 0x20d6 3 0 1 DST_SEL 16 17 INT_SEL 24 26 DATA_SEL 29 31 regCP_EOP_DONE_CNTX_ID 0 0x20d7 1 0 1 CNTX_ID 0 31 regCP_PFP_COMPLETION_STATUS 0 0x20ec 1 0 1 STATUS 0 1 regCP_CE_COMPLETION_STATUS 0 0x20ed 1 0 1 STATUS 0 1 regCP_PRED_NOT_VISIBLE 0 0x20ee 1 0 1 NOT_VISIBLE 0 0 regCP_PFP_METADATA_BASE_ADDR 0 0x20f0 1 0 1 ADDR_LO 0 31 regCP_PFP_METADATA_BASE_ADDR_HI 0 0x20f1 1 0 1 ADDR_HI 0 15 regCP_CE_METADATA_BASE_ADDR 0 0x20f2 1 0 1 ADDR_LO 0 31 regCP_CE_METADATA_BASE_ADDR_HI 0 0x20f3 1 0 1 ADDR_HI 0 15 regCP_DRAW_INDX_INDR_ADDR 0 0x20f4 1 0 1 ADDR_LO 0 31 regCP_DRAW_INDX_INDR_ADDR_HI 0 0x20f5 1 0 1 ADDR_HI 0 15 regCP_DISPATCH_INDR_ADDR 0 0x20f6 1 0 1 ADDR_LO 0 31 regCP_DISPATCH_INDR_ADDR_HI 0 0x20f7 1 0 1 ADDR_HI 0 15 regCP_INDEX_BASE_ADDR 0 0x20f8 1 0 1 ADDR_LO 0 31 regCP_INDEX_BASE_ADDR_HI 0 0x20f9 1 0 1 ADDR_HI 0 15 regCP_INDEX_TYPE 0 0x20fa 1 0 1 INDEX_TYPE 0 1 regCP_GDS_BKUP_ADDR 0 0x20fb 1 0 1 ADDR_LO 0 31 regCP_GDS_BKUP_ADDR_HI 0 0x20fc 1 0 1 ADDR_HI 0 15 regCP_SAMPLE_STATUS 0 0x20fd 8 0 1 Z_PASS_ACITVE 0 0 STREAMOUT_ACTIVE 1 1 PIPELINE_ACTIVE 2 2 STIPPLE_ACTIVE 3 3 VGT_BUFFERS_ACTIVE 4 4 SCREEN_EXT_ACTIVE 5 5 DRAW_INDIRECT_ACTIVE 6 6 DISP_INDIRECT_ACTIVE 7 7 regCP_ME_COHER_CNTL 0 0x20fe 13 0 1 DEST_BASE_0_ENA 0 0 DEST_BASE_1_ENA 1 1 CB0_DEST_BASE_ENA 6 6 CB1_DEST_BASE_ENA 7 7 CB2_DEST_BASE_ENA 8 8 CB3_DEST_BASE_ENA 9 9 CB4_DEST_BASE_ENA 10 10 CB5_DEST_BASE_ENA 11 11 CB6_DEST_BASE_ENA 12 12 CB7_DEST_BASE_ENA 13 13 DB_DEST_BASE_ENA 14 14 DEST_BASE_2_ENA 19 19 DEST_BASE_3_ENA 21 21 regCP_ME_COHER_SIZE 0 0x20ff 1 0 1 COHER_SIZE_256B 0 31 regCP_ME_COHER_SIZE_HI 0 0x2100 1 0 1 COHER_SIZE_HI_256B 0 7 regCP_ME_COHER_BASE 0 0x2101 1 0 1 COHER_BASE_256B 0 31 regCP_ME_COHER_BASE_HI 0 0x2102 1 0 1 COHER_BASE_HI_256B 0 7 regCP_ME_COHER_STATUS 0 0x2103 2 0 1 MATCHING_GFX_CNTX 0 7 STATUS 31 31 regRLC_GPM_PERF_COUNT_0 0 0x2140 8 0 1 FEATURE_SEL 0 3 SE_INDEX 4 7 SH_INDEX 8 11 CU_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 regRLC_GPM_PERF_COUNT_1 0 0x2141 8 0 1 FEATURE_SEL 0 3 SE_INDEX 4 7 SH_INDEX 8 11 CU_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 regGRBM_GFX_INDEX 0 0x2200 6 0 1 INSTANCE_INDEX 0 7 SH_INDEX 8 15 SE_INDEX 16 23 SH_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 regVGT_GSVS_RING_SIZE 0 0x2241 1 0 1 MEM_SIZE 0 31 regVGT_PRIMITIVE_TYPE 0 0x2242 1 0 1 PRIM_TYPE 0 5 regVGT_INDEX_TYPE 0 0x2243 2 0 1 INDEX_TYPE 0 1 PRIMGEN_EN 8 8 regVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0 0x2244 1 0 1 SIZE 0 31 regVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0 0x2245 1 0 1 SIZE 0 31 regVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0 0x2246 1 0 1 SIZE 0 31 regVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0 0x2247 1 0 1 SIZE 0 31 regVGT_MAX_VTX_INDX 0 0x2248 1 0 1 MAX_INDX 0 31 regVGT_MIN_VTX_INDX 0 0x2249 1 0 1 MIN_INDX 0 31 regVGT_INDX_OFFSET 0 0x224a 1 0 1 INDX_OFFSET 0 31 regVGT_MULTI_PRIM_IB_RESET_EN 0 0x224b 2 0 1 RESET_EN 0 0 MATCH_ALL_BITS 1 1 regVGT_NUM_INDICES 0 0x224c 1 0 1 NUM_INDICES 0 31 regVGT_NUM_INSTANCES 0 0x224d 1 0 1 NUM_INSTANCES 0 31 regVGT_TF_RING_SIZE 0 0x224e 1 0 1 SIZE 0 15 regVGT_HS_OFFCHIP_PARAM 0 0x224f 2 0 1 OFFCHIP_BUFFERING 0 8 OFFCHIP_GRANULARITY 9 10 regVGT_TF_MEMORY_BASE 0 0x2250 1 0 1 BASE 0 31 regVGT_TF_MEMORY_BASE_HI 0 0x2251 1 0 1 BASE_HI 0 7 regWD_POS_BUF_BASE 0 0x2252 1 0 1 BASE 0 31 regWD_POS_BUF_BASE_HI 0 0x2253 1 0 1 BASE_HI 0 7 regWD_CNTL_SB_BUF_BASE 0 0x2254 1 0 1 BASE 0 31 regWD_CNTL_SB_BUF_BASE_HI 0 0x2255 1 0 1 BASE_HI 0 7 regWD_INDEX_BUF_BASE 0 0x2256 1 0 1 BASE 0 31 regWD_INDEX_BUF_BASE_HI 0 0x2257 1 0 1 BASE_HI 0 7 regIA_MULTI_VGT_PARAM 0 0x2258 9 0 1 PRIMGROUP_SIZE 0 15 PARTIAL_VS_WAVE_ON 16 16 SWITCH_ON_EOP 17 17 PARTIAL_ES_WAVE_ON 18 18 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 EN_INST_OPT_BASIC 21 21 EN_INST_OPT_ADV 22 22 HW_USE_ONLY 23 23 regVGT_INSTANCE_BASE_ID 0 0x225a 1 0 1 INSTANCE_BASE_ID 0 31 regPA_SU_LINE_STIPPLE_VALUE 0 0x2280 1 0 1 LINE_STIPPLE_VALUE 0 23 regPA_SC_LINE_STIPPLE_STATE 0 0x2281 2 0 1 CURRENT_PTR 0 3 CURRENT_COUNT 8 15 regPA_SC_SCREEN_EXTENT_MIN_0 0 0x2284 2 0 1 X 0 15 Y 16 31 regPA_SC_SCREEN_EXTENT_MAX_0 0 0x2285 2 0 1 X 0 15 Y 16 31 regPA_SC_SCREEN_EXTENT_MIN_1 0 0x2286 2 0 1 X 0 15 Y 16 31 regPA_SC_SCREEN_EXTENT_MAX_1 0 0x228b 2 0 1 X 0 15 Y 16 31 regPA_SC_P3D_TRAP_SCREEN_HV_EN 0 0x22a0 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 regPA_SC_P3D_TRAP_SCREEN_H 0 0x22a1 1 0 1 X_COORD 0 13 regPA_SC_P3D_TRAP_SCREEN_V 0 0x22a2 1 0 1 Y_COORD 0 13 regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0 0x22a3 1 0 1 COUNT 0 15 regPA_SC_P3D_TRAP_SCREEN_COUNT 0 0x22a4 1 0 1 COUNT 0 15 regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0 0x22a8 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 regPA_SC_HP3D_TRAP_SCREEN_H 0 0x22a9 1 0 1 X_COORD 0 13 regPA_SC_HP3D_TRAP_SCREEN_V 0 0x22aa 1 0 1 Y_COORD 0 13 regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0 0x22ab 1 0 1 COUNT 0 15 regPA_SC_HP3D_TRAP_SCREEN_COUNT 0 0x22ac 1 0 1 COUNT 0 15 regPA_SC_TRAP_SCREEN_HV_EN 0 0x22b0 2 0 1 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 regPA_SC_TRAP_SCREEN_H 0 0x22b1 1 0 1 X_COORD 0 13 regPA_SC_TRAP_SCREEN_V 0 0x22b2 1 0 1 Y_COORD 0 13 regPA_SC_TRAP_SCREEN_OCCURRENCE 0 0x22b3 1 0 1 COUNT 0 15 regPA_SC_TRAP_SCREEN_COUNT 0 0x22b4 1 0 1 COUNT 0 15 regPA_STATE_STEREO_X 0 0x22b5 1 0 1 STEREO_X_OFFSET 0 31 regSQ_THREAD_TRACE_BASE 0 0x2330 1 0 1 ADDR 0 31 regSQ_THREAD_TRACE_SIZE 0 0x2331 1 0 1 SIZE 0 21 regSQ_THREAD_TRACE_MASK 0 0x2332 7 0 1 CU_SEL 0 4 SH_SEL 5 5 REG_STALL_EN 7 7 SIMD_EN 8 11 VM_ID_MASK 12 13 SPI_STALL_EN 14 14 SQ_STALL_EN 15 15 regSQ_THREAD_TRACE_TOKEN_MASK 0 0x2333 3 0 1 TOKEN_MASK 0 15 REG_MASK 16 23 REG_DROP_ON_STALL 24 24 regSQ_THREAD_TRACE_PERF_MASK 0 0x2334 2 0 1 SH0_MASK 0 15 SH1_MASK 16 31 regSQ_THREAD_TRACE_CTRL 0 0x2335 1 0 1 RESET_BUFFER 31 31 regSQ_THREAD_TRACE_MODE 0 0x2336 15 0 1 MASK_PS 0 2 MASK_VS 3 5 MASK_GS 6 8 MASK_ES 9 11 MASK_HS 12 14 MASK_LS 15 17 MASK_CS 18 20 MODE 21 22 CAPTURE_MODE 23 24 AUTOFLUSH_EN 25 25 TC_PERF_EN 26 26 ISSUE_MASK 27 28 TEST_MODE 29 29 INTERRUPT_EN 30 30 WRAP 31 31 regSQ_THREAD_TRACE_BASE2 0 0x2337 1 0 1 ADDR_HI 0 3 regSQ_THREAD_TRACE_TOKEN_MASK2 0 0x2338 1 0 1 INST_MASK 0 31 regSQ_THREAD_TRACE_WPTR 0 0x2339 2 0 1 WPTR 0 29 READ_OFFSET 30 31 regSQ_THREAD_TRACE_STATUS 0 0x233a 6 0 1 FINISH_PENDING 0 9 FINISH_DONE 16 25 UTC_ERROR 28 28 NEW_BUF 29 29 BUSY 30 30 FULL 31 31 regSQ_THREAD_TRACE_HIWATER 0 0x233b 1 0 1 HIWATER 0 2 regSQ_THREAD_TRACE_CNTR 0 0x233c 1 0 1 CNTR 0 31 regSQ_THREAD_TRACE_USERDATA_0 0 0x2340 1 0 1 DATA 0 31 regSQ_THREAD_TRACE_USERDATA_1 0 0x2341 1 0 1 DATA 0 31 regSQ_THREAD_TRACE_USERDATA_2 0 0x2342 1 0 1 DATA 0 31 regSQ_THREAD_TRACE_USERDATA_3 0 0x2343 1 0 1 DATA 0 31 regSQC_CACHES 0 0x2348 6 0 1 TARGET_INST 0 0 TARGET_DATA 1 1 INVALIDATE 2 2 WRITEBACK 3 3 VOL 4 4 COMPLETE 16 16 regSQC_WRITEBACK 0 0x2349 2 0 1 DWB 0 0 DIRTY 1 1 regDB_OCCLUSION_COUNT0_LOW 0 0x23c0 1 0 1 COUNT_LOW 0 31 regDB_OCCLUSION_COUNT0_HI 0 0x23c1 1 0 1 COUNT_HI 0 30 regDB_OCCLUSION_COUNT1_LOW 0 0x23c2 1 0 1 COUNT_LOW 0 31 regDB_OCCLUSION_COUNT1_HI 0 0x23c3 1 0 1 COUNT_HI 0 30 regDB_OCCLUSION_COUNT2_LOW 0 0x23c4 1 0 1 COUNT_LOW 0 31 regDB_OCCLUSION_COUNT2_HI 0 0x23c5 1 0 1 COUNT_HI 0 30 regDB_OCCLUSION_COUNT3_LOW 0 0x23c6 1 0 1 COUNT_LOW 0 31 regDB_OCCLUSION_COUNT3_HI 0 0x23c7 1 0 1 COUNT_HI 0 30 regDB_ZPASS_COUNT_LOW 0 0x23fe 1 0 1 COUNT_LOW 0 31 regDB_ZPASS_COUNT_HI 0 0x23ff 1 0 1 COUNT_HI 0 30 regGDS_RD_ADDR 0 0x2400 1 0 1 READ_ADDR 0 31 regGDS_RD_DATA 0 0x2401 1 0 1 READ_DATA 0 31 regGDS_RD_BURST_ADDR 0 0x2402 1 0 1 BURST_ADDR 0 31 regGDS_RD_BURST_COUNT 0 0x2403 1 0 1 BURST_COUNT 0 31 regGDS_RD_BURST_DATA 0 0x2404 1 0 1 BURST_DATA 0 31 regGDS_WR_ADDR 0 0x2405 1 0 1 WRITE_ADDR 0 31 regGDS_WR_DATA 0 0x2406 1 0 1 WRITE_DATA 0 31 regGDS_WR_BURST_ADDR 0 0x2407 1 0 1 WRITE_ADDR 0 31 regGDS_WR_BURST_DATA 0 0x2408 1 0 1 WRITE_DATA 0 31 regGDS_WRITE_COMPLETE 0 0x2409 1 0 1 WRITE_COMPLETE 0 31 regGDS_ATOM_CNTL 0 0x240a 4 0 1 AINC 0 5 UNUSED1 6 7 DMODE 8 9 UNUSED2 10 31 regGDS_ATOM_COMPLETE 0 0x240b 2 0 1 COMPLETE 0 0 UNUSED 1 31 regGDS_ATOM_BASE 0 0x240c 2 0 1 BASE 0 15 UNUSED 16 31 regGDS_ATOM_SIZE 0 0x240d 2 0 1 SIZE 0 15 UNUSED 16 31 regGDS_ATOM_OFFSET0 0 0x240e 2 0 1 OFFSET0 0 7 UNUSED 8 31 regGDS_ATOM_OFFSET1 0 0x240f 2 0 1 OFFSET1 0 7 UNUSED 8 31 regGDS_ATOM_DST 0 0x2410 1 0 1 DST 0 31 regGDS_ATOM_OP 0 0x2411 2 0 1 OP 0 7 UNUSED 8 31 regGDS_ATOM_SRC0 0 0x2412 1 0 1 DATA 0 31 regGDS_ATOM_SRC0_U 0 0x2413 1 0 1 DATA 0 31 regGDS_ATOM_SRC1 0 0x2414 1 0 1 DATA 0 31 regGDS_ATOM_SRC1_U 0 0x2415 1 0 1 DATA 0 31 regGDS_ATOM_READ0 0 0x2416 1 0 1 DATA 0 31 regGDS_ATOM_READ0_U 0 0x2417 1 0 1 DATA 0 31 regGDS_ATOM_READ1 0 0x2418 1 0 1 DATA 0 31 regGDS_ATOM_READ1_U 0 0x2419 1 0 1 DATA 0 31 regGDS_GWS_RESOURCE_CNTL 0 0x241a 2 0 1 INDEX 0 5 UNUSED 6 31 regGDS_GWS_RESOURCE 0 0x241b 9 0 1 FLAG 0 0 COUNTER 1 13 TYPE 14 14 DED 15 15 RELEASE_ALL 16 16 HEAD_QUEUE 17 28 HEAD_VALID 29 29 HEAD_FLAG 30 30 HALTED 31 31 regGDS_GWS_RESOURCE_CNT 0 0x241c 2 0 1 RESOURCE_CNT 0 15 UNUSED 16 31 regGDS_OA_CNTL 0 0x241d 2 0 1 INDEX 0 3 UNUSED 4 31 regGDS_OA_COUNTER 0 0x241e 1 0 1 SPACE_AVAILABLE 0 31 regGDS_OA_ADDRESS 0 0x241f 6 0 1 DS_ADDRESS 0 15 CRAWLER 16 19 CRAWLER_TYPE 20 21 UNUSED 22 29 NO_ALLOC 30 30 ENABLE 31 31 regGDS_OA_INCDEC 0 0x2420 2 0 1 VALUE 0 30 INCDEC 31 31 regGDS_OA_RING_SIZE 0 0x2421 1 0 1 RING_SIZE 0 31 regSPI_CONFIG_CNTL 0 0x2440 9 0 1 GPR_WRITE_PRIORITY 0 20 EXP_PRIORITY_ORDER 21 23 ENABLE_SQG_TOP_EVENTS 24 24 ENABLE_SQG_BOP_EVENTS 25 25 RSRC_MGMT_RESET 26 26 TTRACE_STALL_ALL 27 27 ALLOC_ARB_LRU_ENA 28 28 EXP_ARB_LRU_ENA 29 29 PS_PKR_PRIORITY_CNTL 30 31 regSPI_CONFIG_CNTL_1 0 0x2441 11 0 1 VTX_DONE_DELAY 0 3 INTERP_ONE_PRIM_PER_ROW 4 4 BATON_RESET_DISABLE 5 5 PC_LIMIT_ENABLE 6 6 PC_LIMIT_STRICT 7 7 CRC_SIMD_ID_WADDR_DISABLE 8 8 LBPW_CU_CHK_MODE 9 9 LBPW_CU_CHK_CNT 10 13 CSC_PWR_SAVE_DISABLE 14 14 CSG_PWR_SAVE_DISABLE 15 15 PC_LIMIT_SIZE 16 31 regSPI_CONFIG_CNTL_2 0 0x2442 2 0 1 CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD 0 3 CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD 4 7 regSPI_WAVE_LIMIT_CNTL 0 0x2443 4 0 1 PS_WAVE_GRAN 0 1 VS_WAVE_GRAN 2 3 GS_WAVE_GRAN 4 5 HS_WAVE_GRAN 6 7 regGRBM_CNTL 0 0x0 2 0 0 READ_TIMEOUT 0 7 REPORT_LAST_RDERR 31 31 regGRBM_SKEW_CNTL 0 0x1 2 0 0 SKEW_TOP_THRESHOLD 0 5 SKEW_COUNT 6 11 regGRBM_STATUS2 0 0x2 24 0 0 ME0PIPE1_CMDFIFO_AVAIL 0 3 ME0PIPE1_CF_RQ_PENDING 4 4 ME0PIPE1_PF_RQ_PENDING 5 5 ME1PIPE0_RQ_PENDING 6 6 ME1PIPE1_RQ_PENDING 7 7 ME1PIPE2_RQ_PENDING 8 8 ME1PIPE3_RQ_PENDING 9 9 ME2PIPE0_RQ_PENDING 10 10 ME2PIPE1_RQ_PENDING 11 11 ME2PIPE2_RQ_PENDING 12 12 ME2PIPE3_RQ_PENDING 13 13 RLC_RQ_PENDING 14 14 UTCL2_BUSY 15 15 EA_BUSY 16 16 RMI_BUSY 17 17 UTCL2_RQ_PENDING 18 18 CPF_RQ_PENDING 19 19 EA_LINK_BUSY 20 20 RLC_BUSY 24 24 TC_BUSY 25 25 TCC_CC_RESIDENT 26 26 CPF_BUSY 28 28 CPC_BUSY 29 29 CPG_BUSY 30 30 regGRBM_PWR_CNTL 0 0x3 6 0 0 ALL_REQ_TYPE 0 1 GFX_REQ_TYPE 2 3 ALL_RSP_TYPE 4 5 GFX_RSP_TYPE 6 7 GFX_REQ_EN 14 14 ALL_REQ_EN 15 15 regGRBM_STATUS 0 0x4 23 0 0 ME0PIPE0_CMDFIFO_AVAIL 0 3 ME0PIPE0_CF_RQ_PENDING 7 7 ME0PIPE0_PF_RQ_PENDING 8 8 GDS_DMA_RQ_PENDING 9 9 DB_CLEAN 12 12 CB_CLEAN 13 13 TA_BUSY 14 14 GDS_BUSY 15 15 WD_BUSY_NO_DMA 16 16 VGT_BUSY 17 17 IA_BUSY_NO_DMA 18 18 IA_BUSY 19 19 SX_BUSY 20 20 WD_BUSY 21 21 SPI_BUSY 22 22 BCI_BUSY 23 23 SC_BUSY 24 24 PA_BUSY 25 25 DB_BUSY 26 26 CP_COHERENCY_BUSY 28 28 CP_BUSY 29 29 CB_BUSY 30 30 GUI_ACTIVE 31 31 regGRBM_STATUS_SE0 0 0x5 15 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 TA_BUSY_SE4 3 3 SX_BUSY_SE4 4 4 SPI_BUSY_SE4 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 regGRBM_STATUS_SE1 0 0x6 15 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 TA_BUSY_SE5 3 3 SX_BUSY_SE5 4 4 SPI_BUSY_SE5 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 regGRBM_SOFT_RESET 0 0x8 8 0 0 SOFT_RESET_CP 0 0 SOFT_RESET_RLC 2 2 SOFT_RESET_GFX 16 16 SOFT_RESET_CPF 17 17 SOFT_RESET_CPC 18 18 SOFT_RESET_CPG 19 19 SOFT_RESET_CAC 20 20 SOFT_RESET_EA 22 22 regGRBM_GFX_CLKEN_CNTL 0 0xc 2 0 0 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 regGRBM_WAIT_IDLE_CLOCKS 0 0xd 1 0 0 WAIT_IDLE_CLOCKS 0 7 regGRBM_STATUS_SE2 0 0xe 15 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 TA_BUSY_SE6 3 3 SX_BUSY_SE6 4 4 SPI_BUSY_SE6 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 regGRBM_STATUS_SE3 0 0xf 15 0 0 DB_CLEAN 1 1 CB_CLEAN 2 2 TA_BUSY_SE7 3 3 SX_BUSY_SE7 4 4 SPI_BUSY_SE7 5 5 RMI_BUSY 21 21 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 regGRBM_READ_ERROR 0 0x16 4 0 0 READ_ADDRESS 2 17 READ_PIPEID 20 21 READ_MEID 22 23 READ_ERROR 31 31 regGRBM_READ_ERROR2 0 0x17 15 0 0 READ_REQUESTER_CPF 16 16 READ_REQUESTER_RLC 18 18 READ_REQUESTER_GDS_DMA 19 19 READ_REQUESTER_ME0PIPE0_CF 20 20 READ_REQUESTER_ME0PIPE0_PF 21 21 READ_REQUESTER_ME0PIPE1_CF 22 22 READ_REQUESTER_ME0PIPE1_PF 23 23 READ_REQUESTER_ME1PIPE0 24 24 READ_REQUESTER_ME1PIPE1 25 25 READ_REQUESTER_ME1PIPE2 26 26 READ_REQUESTER_ME1PIPE3 27 27 READ_REQUESTER_ME2PIPE0 28 28 READ_REQUESTER_ME2PIPE1 29 29 READ_REQUESTER_ME2PIPE2 30 30 READ_REQUESTER_ME2PIPE3 31 31 regGRBM_INT_CNTL 0 0x18 2 0 0 RDERR_INT_ENABLE 0 0 GUI_IDLE_INT_ENABLE 19 19 regGRBM_TRAP_OP 0 0x19 1 0 0 RW 0 0 regGRBM_TRAP_ADDR 0 0x1a 1 0 0 DATA 0 17 regGRBM_TRAP_ADDR_MSK 0 0x1b 1 0 0 DATA 0 17 regGRBM_TRAP_WD 0 0x1c 1 0 0 DATA 0 31 regGRBM_TRAP_WD_MSK 0 0x1d 1 0 0 DATA 0 31 regGRBM_WRITE_ERROR 0 0x1f 9 0 0 WRITE_REQUESTER_RLC 0 0 WRITE_SSRCID 2 4 WRITE_VFID 5 8 WRITE_VF 12 12 WRITE_VMID 13 16 TMZ 17 17 WRITE_PIPEID 20 21 WRITE_MEID 22 23 WRITE_ERROR 31 31 regGRBM_CHIP_REVISION 0 0x21 1 0 0 CHIP_REVISION 0 7 regGRBM_GFX_CNTL 0 0x22 4 0 0 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 regGRBM_IH_CREDIT 0 0x24 2 0 0 CREDIT_VALUE 0 1 IH_CLIENT_ID 16 23 regGRBM_PWR_CNTL2 0 0x25 2 0 0 PWR_REQUEST_HALT 16 16 PWR_GFX3D_REQUEST_HALT 20 20 regGRBM_UTCL2_INVAL_RANGE_START 0 0x26 1 0 0 DATA 0 17 regGRBM_UTCL2_INVAL_RANGE_END 0 0x27 1 0 0 DATA 0 17 regGRBM_CHICKEN_BITS 0 0x29 1 0 0 DISABLE_CP_VMID_RESET_REQ 0 0 regGRBM_FENCE_RANGE0 0 0x2a 2 0 0 START 0 15 END 16 31 regGRBM_FENCE_RANGE1 0 0x2b 2 0 0 START 0 15 END 16 31 regGRBM_NOWHERE 0 0x3f 1 0 0 DATA 0 31 regGRBM_SCRATCH_REG0 0 0x40 1 0 0 SCRATCH_REG0 0 31 regGRBM_SCRATCH_REG1 0 0x41 1 0 0 SCRATCH_REG1 0 31 regGRBM_SCRATCH_REG2 0 0x42 1 0 0 SCRATCH_REG2 0 31 regGRBM_SCRATCH_REG3 0 0x43 1 0 0 SCRATCH_REG3 0 31 regGRBM_SCRATCH_REG4 0 0x44 1 0 0 SCRATCH_REG4 0 31 regGRBM_SCRATCH_REG5 0 0x45 1 0 0 SCRATCH_REG5 0 31 regGRBM_SCRATCH_REG6 0 0x46 1 0 0 SCRATCH_REG6 0 31 regGRBM_SCRATCH_REG7 0 0x47 1 0 0 SCRATCH_REG7 0 31 regVIOLATION_DATA_ASYNC_VF_PROG 0 0x48 3 0 0 SSRCID 0 3 VFID 4 9 VIOLATION_ERROR 31 31 regCP_HYP_PFP_UCODE_ADDR 0 0x5814 1 0 1 UCODE_ADDR 0 13 regCP_PFP_UCODE_ADDR 0 0x5814 1 0 1 UCODE_ADDR 0 13 regCP_HYP_PFP_UCODE_DATA 0 0x5815 1 0 1 UCODE_DATA 0 31 regCP_PFP_UCODE_DATA 0 0x5815 1 0 1 UCODE_DATA 0 31 regCP_HYP_ME_UCODE_ADDR 0 0x5816 1 0 1 UCODE_ADDR 0 12 regCP_ME_RAM_RADDR 0 0x5816 1 0 1 ME_RAM_RADDR 0 12 regCP_ME_RAM_WADDR 0 0x5816 1 0 1 ME_RAM_WADDR 0 12 regCP_HYP_ME_UCODE_DATA 0 0x5817 1 0 1 UCODE_DATA 0 31 regCP_ME_RAM_DATA 0 0x5817 1 0 1 ME_RAM_DATA 0 31 regCP_CE_UCODE_ADDR 0 0x5818 1 0 1 UCODE_ADDR 0 11 regCP_HYP_CE_UCODE_ADDR 0 0x5818 1 0 1 UCODE_ADDR 0 11 regCP_CE_UCODE_DATA 0 0x5819 1 0 1 UCODE_DATA 0 31 regCP_HYP_CE_UCODE_DATA 0 0x5819 1 0 1 UCODE_DATA 0 31 regCP_HYP_MEC1_UCODE_ADDR 0 0x581a 1 0 1 UCODE_ADDR 0 16 regCP_MEC_ME1_UCODE_ADDR 0 0x581a 1 0 1 UCODE_ADDR 0 16 regCP_HYP_MEC1_UCODE_DATA 0 0x581b 1 0 1 UCODE_DATA 0 31 regCP_MEC_ME1_UCODE_DATA 0 0x581b 1 0 1 UCODE_DATA 0 31 regCP_HYP_MEC2_UCODE_ADDR 0 0x581c 1 0 1 UCODE_ADDR 0 16 regCP_MEC_ME2_UCODE_ADDR 0 0x581c 1 0 1 UCODE_ADDR 0 16 regCP_HYP_MEC2_UCODE_DATA 0 0x581d 1 0 1 UCODE_DATA 0 31 regCP_MEC_ME2_UCODE_DATA 0 0x581d 1 0 1 UCODE_DATA 0 31 regRLC_GPM_UCODE_ADDR 0 0x583c 2 0 1 UCODE_ADDR 0 13 RESERVED 14 31 regRLC_GPM_UCODE_DATA 0 0x583d 1 0 1 UCODE_DATA 0 31 regGRBM_GFX_INDEX_SR_SELECT 0 0x5a00 2 0 1 INDEX 0 2 VF_PF 31 31 regGRBM_GFX_INDEX_SR_DATA 0 0x5a01 6 0 1 INSTANCE_INDEX 0 7 SH_INDEX 8 15 SE_INDEX 16 23 SH_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 regGRBM_GFX_CNTL_SR_SELECT 0 0x5a02 2 0 1 INDEX 0 2 VF_PF 31 31 regGRBM_GFX_CNTL_SR_DATA 0 0x5a03 4 0 1 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 regGRBM_CAM_INDEX 0 0x5a04 1 0 1 CAM_INDEX 0 2 regGRBM_HYP_CAM_INDEX 0 0x5a04 1 0 1 CAM_INDEX 0 2 regGRBM_CAM_DATA 0 0x5a05 2 0 1 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 regGRBM_HYP_CAM_DATA 0 0x5a05 2 0 1 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 regRLC_GPU_IOV_VF_ENABLE 0 0x5b00 3 0 1 VF_ENABLE 0 0 RESERVED 1 15 VF_NUM 16 31 regRLC_GPU_IOV_CFG_REG6 0 0x5b06 4 0 1 CNTXT_SIZE 0 6 CNTXT_LOCATION 7 7 RESERVED 8 9 CNTXT_OFFSET 10 31 regRLC_GPU_IOV_CFG_REG8 0 0x5b20 1 0 1 VM_BUSY_STATUS 0 31 regRLC_RLCV_TIMER_INT_0 0 0x5b25 1 0 1 TIMER 0 31 regRLC_RLCV_TIMER_CTRL 0 0x5b26 3 0 1 TIMER_0_EN 0 0 TIMER_1_EN 1 1 RESERVED 2 31 regRLC_RLCV_TIMER_STAT 0 0x5b27 5 0 1 TIMER_0_STAT 0 0 TIMER_1_STAT 1 1 RESERVED 2 7 TIMER_0_ENABLE_SYNC 8 8 TIMER_1_ENABLE_SYNC 9 9 regRLC_GPU_IOV_VF_DOORBELL_STATUS 0 0x5b2a 3 0 1 VF_DOORBELL_STATUS 0 15 RESERVED 16 30 PF_DOORBELL_STATUS 31 31 regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0 0x5b2b 3 0 1 VF_DOORBELL_STATUS_SET 0 15 RESERVED 16 30 PF_DOORBELL_STATUS_SET 31 31 regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0 0x5b2c 3 0 1 VF_DOORBELL_STATUS_CLR 0 15 RESERVED 16 30 PF_DOORBELL_STATUS_CLR 31 31 regRLC_GPU_IOV_VF_MASK 0 0x5b2d 2 0 1 VF_MASK 0 15 RESERVED 16 31 regRLC_HYP_SEMAPHORE_0 0 0x5b2e 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_HYP_SEMAPHORE_1 0 0x5b2f 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_CLK_CNTL 0 0x5b31 13 0 1 RLC_SRM_CLK_CNTL 0 1 RLC_SPM_CLK_CNTL 2 3 RLC_GPM_CLK_CNTL 4 4 RLC_CMN_CLK_CNTL 5 5 RLC_TC_CLK_CNTL 6 6 RLC_SPP_CLK_CNTL 7 7 RLC_SRAM_CLK_GATER_OVERRIDE 8 8 RLC_EDC_OVERRIDE 9 9 RESERVED_11_10 10 11 RLC_TC_FGCG_REP_OVERRIDE 12 12 RESERVED_1 14 17 RLC_UTCL2_FGCG_OVERRIDE 18 18 RESERVED 19 31 regRLC_GPU_IOV_SCH_BLOCK 0 0x5b34 4 0 1 Sch_Block_ID 0 3 Sch_Block_Ver 4 7 Sch_Block_Size 8 14 RESERVED 16 30 regRLC_GPU_IOV_CFG_REG1 0 0x5b35 7 0 1 CMD_TYPE 0 3 CMD_EXECUTE 4 4 CMD_EXECUTE_INTR_EN 5 5 RESERVED 6 7 FCN_ID 8 15 NEXT_FCN_ID 16 23 RESERVED1 24 31 regRLC_GPU_IOV_CFG_REG2 0 0x5b36 2 0 1 CMD_STATUS 0 3 RESERVED 4 31 regRLC_GPU_IOV_VM_BUSY_STATUS 0 0x5b37 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SCH_0 0 0x5b38 1 0 1 ACTIVE_FUNCTIONS 0 31 regRLC_GPU_IOV_ACTIVE_FCN_ID 0 0x5b39 3 0 1 VF_ID 0 3 RESERVED 4 30 PF_VF 31 31 regRLC_GPU_IOV_SCH_3 0 0x5b3a 1 0 1 Time_Quanta_Def 0 31 regRLC_GPU_IOV_SCH_1 0 0x5b3b 1 0 1 DATA 0 31 regRLC_GPU_IOV_SCH_2 0 0x5b3c 1 0 1 DATA 0 31 regRLC_GPU_IOV_INT_STAT 0 0x5b3f 1 0 1 STATUS 0 31 regRLC_RLCV_TIMER_INT_1 0 0x5b40 1 0 1 TIMER 0 31 regRLC_GPU_IOV_UCODE_ADDR 0 0x5b42 2 0 1 UCODE_ADDR 0 11 RESERVED 12 31 regRLC_GPU_IOV_UCODE_DATA 0 0x5b43 1 0 1 UCODE_DATA 0 31 regRLC_GPU_IOV_SCRATCH_ADDR 0 0x5b44 2 0 1 ADDR 0 8 RESERVED 9 31 regRLC_GPU_IOV_SCRATCH_DATA 0 0x5b45 1 0 1 DATA 0 31 regRLC_GPU_IOV_F32_CNTL 0 0x5b46 2 0 1 ENABLE 0 0 RESERVED 1 31 regRLC_GPU_IOV_F32_RESET 0 0x5b47 2 0 1 RESET 0 0 RESERVED 1 31 regRLC_GPU_IOV_SDMA0_STATUS 0 0x5b48 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA1_STATUS 0 0x5b49 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_VIRT_RESET_REQ 0 0x5b4c 3 0 1 VF_FLR 0 15 RESERVED 16 30 SOFT_PF_FLR 31 31 regRLC_GPU_IOV_RLC_RESPONSE 0 0x5b4d 1 0 1 RESP 0 31 regRLC_GPU_IOV_INT_DISABLE 0 0x5b4e 1 0 1 DISABLE 0 31 regRLC_GPU_IOV_INT_FORCE 0 0x5b4f 1 0 1 FORCE 0 31 regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0 0x5b50 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0 0x5b51 1 0 1 VM_BUSY_STATUS 0 31 regRLC_HYP_SEMAPHORE_2 0 0x5b52 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_HYP_SEMAPHORE_3 0 0x5b53 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_GPU_IOV_SDMA2_STATUS 0 0x5b54 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA3_STATUS 0 0x5b55 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA4_STATUS 0 0x5b56 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA5_STATUS 0 0x5b57 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA6_STATUS 0 0x5b58 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA7_STATUS 0 0x5b59 6 0 1 PREEMPTED 0 0 RESERVED 1 7 SAVED 8 8 RESERVED1 9 11 RESTORED 12 12 RESERVED2 13 31 regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0 0x5b5a 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0 0x5b5b 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0 0x5b5c 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0 0x5b5d 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0 0x5b5e 1 0 1 VM_BUSY_STATUS 0 31 regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0 0x5b5f 1 0 1 VM_BUSY_STATUS 0 31 regVGT_VTX_VECT_EJECT_REG 0 0x22c 1 0 0 PRIM_COUNT 0 6 regVGT_DMA_DATA_FIFO_DEPTH 0 0x22d 2 0 0 DMA_DATA_FIFO_DEPTH 0 8 DMA2DRAW_FIFO_DEPTH 9 18 regVGT_DMA_REQ_FIFO_DEPTH 0 0x22e 1 0 0 DMA_REQ_FIFO_DEPTH 0 5 regVGT_DRAW_INIT_FIFO_DEPTH 0 0x22f 1 0 0 DRAW_INIT_FIFO_DEPTH 0 5 regVGT_LAST_COPY_STATE 0 0x230 2 0 0 SRC_STATE_ID 0 2 DST_STATE_ID 16 18 regVGT_CACHE_INVALIDATION 0 0x231 14 0 0 CACHE_INVALIDATION 0 1 DIS_INSTANCING_OPT 4 4 VS_NO_EXTRA_BUFFER 5 5 AUTO_INVLD_EN 6 7 USE_GS_DONE 9 9 DIS_RANGE_FULL_INVLD 11 11 GS_LATE_ALLOC_EN 12 12 STREAMOUT_FULL_FLUSH 13 13 ES_LIMIT 16 20 ENABLE_PING_PONG 21 21 OPT_FLOW_CNTL_1 22 24 OPT_FLOW_CNTL_2 25 27 EN_WAVE_MERGE 28 28 ENABLE_PING_PONG_EOI 29 29 regVGT_STRMOUT_DELAY 0 0x233 5 0 0 SKIP_DELAY 0 7 SE0_WD_DELAY 8 10 SE1_WD_DELAY 11 13 SE2_WD_DELAY 14 16 SE3_WD_DELAY 17 19 regVGT_FIFO_DEPTHS 0 0x234 4 0 0 VS_DEALLOC_TBL_DEPTH 0 6 RESERVED_0 7 7 CLIPP_FIFO_DEPTH 8 21 HSINPUT_FIFO_DEPTH 22 27 regVGT_GS_VERTEX_REUSE 0 0x235 1 0 0 VERT_REUSE 0 4 regVGT_MC_LAT_CNTL 0 0x236 1 0 0 MC_TIME_STAMP_RES 0 3 regIA_CNTL_STATUS 0 0x237 5 0 0 IA_BUSY 0 0 IA_DMA_BUSY 1 1 IA_DMA_REQ_BUSY 2 2 IA_GRP_BUSY 3 3 IA_ADC_BUSY 4 4 regVGT_CNTL_STATUS 0 0x23c 11 0 0 VGT_BUSY 0 0 VGT_OUT_INDX_BUSY 1 1 VGT_OUT_BUSY 2 2 VGT_PT_BUSY 3 3 VGT_TE_BUSY 4 4 VGT_VR_BUSY 5 5 VGT_PI_BUSY 6 6 VGT_GS_BUSY 7 7 VGT_HS_BUSY 8 8 VGT_TE11_BUSY 9 9 VGT_PRIMGEN_BUSY 10 10 regWD_CNTL_STATUS 0 0x23f 4 0 0 WD_BUSY 0 0 WD_SPL_DMA_BUSY 1 1 WD_SPL_DI_BUSY 2 2 WD_ADC_BUSY 3 3 regCC_GC_PRIM_CONFIG 0 0x240 2 0 0 INACTIVE_IA 16 17 INACTIVE_VGT_PA 24 27 regGC_USER_PRIM_CONFIG 0 0x241 2 0 0 INACTIVE_IA 16 17 INACTIVE_VGT_PA 24 27 regWD_QOS 0 0x242 1 0 0 DRAW_STALL 0 0 regWD_UTCL1_CNTL 0 0x243 8 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 regWD_UTCL1_STATUS 0 0x244 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 regIA_UTCL1_CNTL 0 0x246 8 0 0 XNACK_REDO_TIMER_CNT 0 19 VMID_RESET_MODE 23 23 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 regIA_UTCL1_STATUS 0 0x247 6 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 FAULT_UTCL1ID 8 13 RETRY_UTCL1ID 16 21 PRT_UTCL1ID 24 29 regVGT_SYS_CONFIG 0 0x263 3 0 0 DUAL_CORE_EN 0 0 MAX_LS_HS_THDGRP 1 6 ADC_EVENT_FILTER_DISABLE 7 7 regVGT_VS_MAX_WAVE_ID 0 0x268 1 0 0 MAX_WAVE_ID 0 11 regVGT_GS_MAX_WAVE_ID 0 0x269 1 0 0 MAX_WAVE_ID 0 11 regGFX_PIPE_CONTROL 0 0x26d 3 0 0 HYSTERESIS_CNT 0 12 RESERVED 13 15 CONTEXT_SUSPEND_EN 16 16 regCC_GC_SHADER_ARRAY_CONFIG 0 0x26f 1 0 0 INACTIVE_CUS 16 31 regGC_USER_SHADER_ARRAY_CONFIG 0 0x270 1 0 0 INACTIVE_CUS 16 31 regVGT_DMA_PRIMITIVE_TYPE 0 0x271 1 0 0 PRIM_TYPE 0 5 regVGT_DMA_CONTROL 0 0x272 7 0 0 PRIMGROUP_SIZE 0 15 IA_SWITCH_ON_EOP 17 17 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 EN_INST_OPT_BASIC 21 21 EN_INST_OPT_ADV 22 22 HW_USE_ONLY 23 23 regVGT_DMA_LS_HS_CONFIG 0 0x273 1 0 0 HS_NUM_INPUT_CP 8 13 regWD_BUF_RESOURCE_1 0 0x276 2 0 0 POS_BUF_SIZE 0 15 INDEX_BUF_SIZE 16 31 regWD_BUF_RESOURCE_2 0 0x277 3 0 0 PARAM_BUF_SIZE 0 12 ADDR_MODE 15 15 CNTL_SB_BUF_SIZE 16 31 regPA_CL_CNTL_STATUS 0 0x284 3 0 0 UTC_FAULT_DETECTED 0 0 UTC_RETRY_DETECTED 1 1 UTC_PRT_DETECTED 2 2 regPA_CL_ENHANCE 0 0x285 20 0 0 CLIP_VTX_REORDER_ENA 0 0 NUM_CLIP_SEQ 1 2 CLIPPED_PRIM_SEQ_STALL 3 3 VE_NAN_PROC_DISABLE 4 4 IGNORE_PIPELINE_RESET 6 6 KILL_INNER_EDGE_FLAGS 7 7 NGG_PA_TO_ALL_SC 8 8 TC_LATENCY_TIME_STAMP_RESOLUTION 9 10 NGG_BYPASS_PRIM_FILTER 11 11 NGG_SIDEBAND_MEMORY_DEPTH 12 13 NGG_PRIM_INDICES_FIFO_DEPTH 14 16 PROG_NEAR_CLIP_PLANE_ENABLE 17 17 OUTPUT_SWITCH_TO_LEGACY_EVENT 18 18 NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET 19 19 POLY_INNER_EDGE_FLAG_DISABLE 20 20 TC_REQUEST_PERF_CNTR_ENABLE 21 21 ECO_SPARE3 28 28 ECO_SPARE2 29 29 ECO_SPARE1 30 30 ECO_SPARE0 31 31 regPA_SU_CNTL_STATUS 0 0x294 1 0 0 SU_BUSY 31 31 regPA_SC_FIFO_DEPTH_CNTL 0 0x295 1 0 0 DEPTH 0 9 regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0 0x2c0 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0 0x2c1 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 regPA_SC_TRAP_SCREEN_HV_LOCK 0 0x2c2 1 0 0 DISABLE_NON_PRIV_WRITES 0 0 regPA_SC_FORCE_EOV_MAX_CNTS 0 0x2c9 2 0 0 FORCE_EOV_MAX_CLK_CNT 0 15 FORCE_EOV_MAX_REZ_CNT 16 31 regPA_SC_BINNER_EVENT_CNTL_0 0 0x2cc 16 0 0 RESERVED_0 0 1 SAMPLE_STREAMOUTSTATS1 2 3 SAMPLE_STREAMOUTSTATS2 4 5 SAMPLE_STREAMOUTSTATS3 6 7 CACHE_FLUSH_TS 8 9 CONTEXT_DONE 10 11 CACHE_FLUSH 12 13 CS_PARTIAL_FLUSH 14 15 VGT_STREAMOUT_SYNC 16 17 RESERVED_9 18 19 VGT_STREAMOUT_RESET 20 21 END_OF_PIPE_INCR_DE 22 23 END_OF_PIPE_IB_END 24 25 RST_PIX_CNT 26 27 BREAK_BATCH 28 29 VS_PARTIAL_FLUSH 30 31 regPA_SC_BINNER_EVENT_CNTL_1 0 0x2cd 16 0 0 PS_PARTIAL_FLUSH 0 1 FLUSH_HS_OUTPUT 2 3 FLUSH_DFSM 4 5 RESET_TO_LOWEST_VGT 6 7 CACHE_FLUSH_AND_INV_TS_EVENT 8 9 ZPASS_DONE 10 11 CACHE_FLUSH_AND_INV_EVENT 12 13 PERFCOUNTER_START 14 15 PERFCOUNTER_STOP 16 17 PIPELINESTAT_START 18 19 PIPELINESTAT_STOP 20 21 PERFCOUNTER_SAMPLE 22 23 FLUSH_ES_OUTPUT 24 25 FLUSH_GS_OUTPUT 26 27 SAMPLE_PIPELINESTAT 28 29 SO_VGTSTREAMOUT_FLUSH 30 31 regPA_SC_BINNER_EVENT_CNTL_2 0 0x2ce 16 0 0 SAMPLE_STREAMOUTSTATS 0 1 RESET_VTX_CNT 2 3 BLOCK_CONTEXT_DONE 4 5 CS_CONTEXT_DONE 6 7 VGT_FLUSH 8 9 TGID_ROLLOVER 10 11 SQ_NON_EVENT 12 13 SC_SEND_DB_VPZ 14 15 BOTTOM_OF_PIPE_TS 16 17 FLUSH_SX_TS 18 19 DB_CACHE_FLUSH_AND_INV 20 21 FLUSH_AND_INV_DB_DATA_TS 22 23 FLUSH_AND_INV_DB_META 24 25 FLUSH_AND_INV_CB_DATA_TS 26 27 FLUSH_AND_INV_CB_META 28 29 CS_DONE 30 31 regPA_SC_BINNER_EVENT_CNTL_3 0 0x2cf 16 0 0 PS_DONE 0 1 FLUSH_AND_INV_CB_PIXEL_DATA 2 3 SX_CB_RAT_ACK_REQUEST 4 5 THREAD_TRACE_START 6 7 THREAD_TRACE_STOP 8 9 THREAD_TRACE_MARKER 10 11 THREAD_TRACE_FLUSH 12 13 THREAD_TRACE_FINISH 14 15 PIXEL_PIPE_STAT_CONTROL 16 17 PIXEL_PIPE_STAT_DUMP 18 19 PIXEL_PIPE_STAT_RESET 20 21 CONTEXT_SUSPEND 22 23 OFFCHIP_HS_DEALLOC 24 25 ENABLE_NGG_PIPELINE 26 27 ENABLE_LEGACY_PIPELINE 28 29 RESERVED_63 30 31 regPA_SC_BINNER_TIMEOUT_COUNTER 0 0x2d0 1 0 0 THRESHOLD 0 31 regPA_SC_BINNER_PERF_CNTL_0 0 0x2d1 4 0 0 BIN_HIST_NUM_PRIMS_THRESHOLD 0 9 BATCH_HIST_NUM_PRIMS_THRESHOLD 10 19 BIN_HIST_NUM_CONTEXT_THRESHOLD 20 22 BATCH_HIST_NUM_CONTEXT_THRESHOLD 23 25 regPA_SC_BINNER_PERF_CNTL_1 0 0x2d2 3 0 0 BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD 0 4 BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD 5 9 BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD 10 25 regPA_SC_BINNER_PERF_CNTL_2 0 0x2d3 2 0 0 BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD 0 10 BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD 11 21 regPA_SC_BINNER_PERF_CNTL_3 0 0x2d4 1 0 0 BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD 0 31 regPA_SC_ENHANCE_2 0 0x2dc 9 0 0 RESERVED_0 0 0 RESERVED_1 1 1 RESERVED_2 2 2 RESERVED_3 3 3 RESERVED_4 4 4 RESERVED_5 5 5 ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN 6 6 ENABLE_SC_SEND_DB_VPZ_FOR_EN_PIPELINE_PRIMID 7 7 RSVD 8 31 regPA_SC_FIFO_SIZE 0 0x2f3 4 0 0 SC_FRONTEND_PRIM_FIFO_SIZE 0 5 SC_BACKEND_PRIM_FIFO_SIZE 6 14 SC_HIZ_TILE_FIFO_SIZE 15 20 SC_EARLYZ_TILE_FIFO_SIZE 21 31 regPA_SC_IF_FIFO_SIZE 0 0x2f5 4 0 0 SC_DB_TILE_IF_FIFO_SIZE 0 5 SC_DB_QUAD_IF_FIFO_SIZE 6 11 SC_SPI_IF_FIFO_SIZE 12 17 SC_BCI_IF_FIFO_SIZE 18 23 regPA_SC_PKR_WAVE_TABLE_CNTL 0 0x2f8 1 0 0 SIZE 0 5 regPA_UTCL1_CNTL1 0 0x2f9 17 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEFAULT 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 SPARE 16 16 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regPA_UTCL1_CNTL2 0 0x2fa 17 0 0 SPARE1 0 7 SPARE2 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 SPARE3 11 11 GPUVM_INV_MODE 12 12 ENABLE_SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 SPARE4 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 SPARE5 25 25 FORCE_FRAG_2M_TO_64K 26 26 RESERVED 27 31 regPA_SIDEBAND_REQUEST_DELAYS 0 0x2fb 2 0 0 RETRY_DELAY 0 15 INITIAL_DELAY 16 31 regPA_SC_ENHANCE 0 0x2fc 30 0 0 ENABLE_PA_SC_OUT_OF_ORDER 0 0 DISABLE_SC_DB_TILE_FIX 1 1 DISABLE_AA_MASK_FULL_FIX 2 2 ENABLE_1XMSAA_SAMPLE_LOCATIONS 3 3 ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 4 4 DISABLE_SCISSOR_FIX 5 5 SEND_UNLIT_STILES_TO_PACKER 6 6 DISABLE_DUALGRAD_PERF_OPTIMIZATION 7 7 DISABLE_SC_PROCESS_RESET_PRIM 8 8 DISABLE_SC_PROCESS_RESET_SUPERTILE 9 9 DISABLE_SC_PROCESS_RESET_TILE 10 10 DISABLE_PA_SC_GUIDANCE 11 11 DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS 12 12 ENABLE_MULTICYCLE_BUBBLE_FREEZE 13 13 DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE 14 14 ENABLE_OUT_OF_ORDER_POLY_MODE 15 15 DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST 16 16 DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING 17 17 ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY 18 18 DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING 19 19 DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING 20 20 DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS 21 21 ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID 22 22 DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO 23 23 OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT 24 24 OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING 25 25 DISABLE_EOP_LINE_STIPPLE_RESET 26 26 DISABLE_VPZ_EOP_LINE_STIPPLE_RESET 27 27 IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE 28 28 OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING 29 29 regPA_SC_ENHANCE_1 0 0x2fd 30 0 0 REALIGN_DQUADS_OVERRIDE_ENABLE 0 0 REALIGN_DQUADS_OVERRIDE 1 2 DISABLE_SC_BINNING 3 3 BYPASS_PBB 4 4 ECO_SPARE0 5 5 ECO_SPARE1 6 6 ECO_SPARE2 7 7 ECO_SPARE3 8 8 DISABLE_SC_PROCESS_RESET_PBB 9 9 DISABLE_PBB_SCISSOR_OPT 10 10 ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM 11 11 DISABLE_PACKER_GRAD_FDCE_ENHANCE 13 13 DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE 14 14 DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION 15 15 DISABLE_PACKER_ODC_ENHANCE 16 16 ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING 17 17 OPTIMAL_BIN_SELECTION 18 18 DISABLE_FORCE_SOP_ALL_EVENTS 19 19 DISABLE_PBB_CLK_OPTIMIZATION 20 20 DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION 21 21 DISABLE_PBB_BINNING_CLK_OPTIMIZATION 22 22 DISABLE_INTF_CG 23 23 IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT 24 24 DISABLE_SHADER_PROFILING_FOR_POWER 25 25 FLUSH_ON_BINNING_TRANSITION 26 26 DISABLE_QUAD_PROC_FDCE_ENHANCE 27 27 DISABLE_SC_PS_PA_ARBITER_FIX 28 28 DISABLE_SC_PS_PA_ARBITER_FIX_1 29 29 PASS_VPZ_EVENT_TO_SPI 30 30 RSVD 31 31 regPA_SC_DSM_CNTL 0 0x2fe 2 0 0 FORCE_EOV_REZ_0 0 0 FORCE_EOV_REZ_1 1 1 regPA_SC_TILE_STEERING_CREST_OVERRIDE 0 0x2ff 3 0 0 ONE_RB_MODE_ENABLE 0 0 SE_SELECT 1 2 RB_SELECT 5 6 regCPG_PERFCOUNTER1_LO 0 0x3000 1 0 1 PERFCOUNTER_LO 0 31 regCPG_PERFCOUNTER1_HI 0 0x3001 1 0 1 PERFCOUNTER_HI 0 31 regCPG_PERFCOUNTER0_LO 0 0x3002 1 0 1 PERFCOUNTER_LO 0 31 regCPG_PERFCOUNTER0_HI 0 0x3003 1 0 1 PERFCOUNTER_HI 0 31 regCPC_PERFCOUNTER1_LO 0 0x3004 1 0 1 PERFCOUNTER_LO 0 31 regCPC_PERFCOUNTER1_HI 0 0x3005 1 0 1 PERFCOUNTER_HI 0 31 regCPC_PERFCOUNTER0_LO 0 0x3006 1 0 1 PERFCOUNTER_LO 0 31 regCPC_PERFCOUNTER0_HI 0 0x3007 1 0 1 PERFCOUNTER_HI 0 31 regCPF_PERFCOUNTER1_LO 0 0x3008 1 0 1 PERFCOUNTER_LO 0 31 regCPF_PERFCOUNTER1_HI 0 0x3009 1 0 1 PERFCOUNTER_HI 0 31 regCPF_PERFCOUNTER0_LO 0 0x300a 1 0 1 PERFCOUNTER_LO 0 31 regCPF_PERFCOUNTER0_HI 0 0x300b 1 0 1 PERFCOUNTER_HI 0 31 regCPF_LATENCY_STATS_DATA 0 0x300c 1 0 1 DATA 0 31 regCPG_LATENCY_STATS_DATA 0 0x300d 1 0 1 DATA 0 31 regCPC_LATENCY_STATS_DATA 0 0x300e 1 0 1 DATA 0 31 regGRBM_PERFCOUNTER0_LO 0 0x3040 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_PERFCOUNTER0_HI 0 0x3041 1 0 1 PERFCOUNTER_HI 0 31 regGRBM_PERFCOUNTER1_LO 0 0x3043 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_PERFCOUNTER1_HI 0 0x3044 1 0 1 PERFCOUNTER_HI 0 31 regGRBM_SE0_PERFCOUNTER_LO 0 0x3045 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_SE0_PERFCOUNTER_HI 0 0x3046 1 0 1 PERFCOUNTER_HI 0 31 regGRBM_SE1_PERFCOUNTER_LO 0 0x3047 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_SE1_PERFCOUNTER_HI 0 0x3048 1 0 1 PERFCOUNTER_HI 0 31 regGRBM_SE2_PERFCOUNTER_LO 0 0x3049 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_SE2_PERFCOUNTER_HI 0 0x304a 1 0 1 PERFCOUNTER_HI 0 31 regGRBM_SE3_PERFCOUNTER_LO 0 0x304b 1 0 1 PERFCOUNTER_LO 0 31 regGRBM_SE3_PERFCOUNTER_HI 0 0x304c 1 0 1 PERFCOUNTER_HI 0 31 regWD_PERFCOUNTER0_LO 0 0x3080 1 0 1 PERFCOUNTER_LO 0 31 regWD_PERFCOUNTER0_HI 0 0x3081 1 0 1 PERFCOUNTER_HI 0 31 regWD_PERFCOUNTER1_LO 0 0x3082 1 0 1 PERFCOUNTER_LO 0 31 regWD_PERFCOUNTER1_HI 0 0x3083 1 0 1 PERFCOUNTER_HI 0 31 regWD_PERFCOUNTER2_LO 0 0x3084 1 0 1 PERFCOUNTER_LO 0 31 regWD_PERFCOUNTER2_HI 0 0x3085 1 0 1 PERFCOUNTER_HI 0 31 regWD_PERFCOUNTER3_LO 0 0x3086 1 0 1 PERFCOUNTER_LO 0 31 regWD_PERFCOUNTER3_HI 0 0x3087 1 0 1 PERFCOUNTER_HI 0 31 regIA_PERFCOUNTER0_LO 0 0x3088 1 0 1 PERFCOUNTER_LO 0 31 regIA_PERFCOUNTER0_HI 0 0x3089 1 0 1 PERFCOUNTER_HI 0 31 regIA_PERFCOUNTER1_LO 0 0x308a 1 0 1 PERFCOUNTER_LO 0 31 regIA_PERFCOUNTER1_HI 0 0x308b 1 0 1 PERFCOUNTER_HI 0 31 regIA_PERFCOUNTER2_LO 0 0x308c 1 0 1 PERFCOUNTER_LO 0 31 regIA_PERFCOUNTER2_HI 0 0x308d 1 0 1 PERFCOUNTER_HI 0 31 regIA_PERFCOUNTER3_LO 0 0x308e 1 0 1 PERFCOUNTER_LO 0 31 regIA_PERFCOUNTER3_HI 0 0x308f 1 0 1 PERFCOUNTER_HI 0 31 regVGT_PERFCOUNTER0_LO 0 0x3090 1 0 1 PERFCOUNTER_LO 0 31 regVGT_PERFCOUNTER0_HI 0 0x3091 1 0 1 PERFCOUNTER_HI 0 31 regVGT_PERFCOUNTER1_LO 0 0x3092 1 0 1 PERFCOUNTER_LO 0 31 regVGT_PERFCOUNTER1_HI 0 0x3093 1 0 1 PERFCOUNTER_HI 0 31 regVGT_PERFCOUNTER2_LO 0 0x3094 1 0 1 PERFCOUNTER_LO 0 31 regVGT_PERFCOUNTER2_HI 0 0x3095 1 0 1 PERFCOUNTER_HI 0 31 regVGT_PERFCOUNTER3_LO 0 0x3096 1 0 1 PERFCOUNTER_LO 0 31 regVGT_PERFCOUNTER3_HI 0 0x3097 1 0 1 PERFCOUNTER_HI 0 31 regPA_SU_PERFCOUNTER0_LO 0 0x3100 1 0 1 PERFCOUNTER_LO 0 31 regPA_SU_PERFCOUNTER0_HI 0 0x3101 1 0 1 PERFCOUNTER_HI 0 15 regPA_SU_PERFCOUNTER1_LO 0 0x3102 1 0 1 PERFCOUNTER_LO 0 31 regPA_SU_PERFCOUNTER1_HI 0 0x3103 1 0 1 PERFCOUNTER_HI 0 15 regPA_SU_PERFCOUNTER2_LO 0 0x3104 1 0 1 PERFCOUNTER_LO 0 31 regPA_SU_PERFCOUNTER2_HI 0 0x3105 1 0 1 PERFCOUNTER_HI 0 15 regPA_SU_PERFCOUNTER3_LO 0 0x3106 1 0 1 PERFCOUNTER_LO 0 31 regPA_SU_PERFCOUNTER3_HI 0 0x3107 1 0 1 PERFCOUNTER_HI 0 15 regPA_SC_PERFCOUNTER0_LO 0 0x3140 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER0_HI 0 0x3141 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER1_LO 0 0x3142 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER1_HI 0 0x3143 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER2_LO 0 0x3144 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER2_HI 0 0x3145 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER3_LO 0 0x3146 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER3_HI 0 0x3147 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER4_LO 0 0x3148 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER4_HI 0 0x3149 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER5_LO 0 0x314a 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER5_HI 0 0x314b 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER6_LO 0 0x314c 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER6_HI 0 0x314d 1 0 1 PERFCOUNTER_HI 0 31 regPA_SC_PERFCOUNTER7_LO 0 0x314e 1 0 1 PERFCOUNTER_LO 0 31 regPA_SC_PERFCOUNTER7_HI 0 0x314f 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER0_HI 0 0x3180 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER0_LO 0 0x3181 1 0 1 PERFCOUNTER_LO 0 31 regSPI_PERFCOUNTER1_HI 0 0x3182 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER1_LO 0 0x3183 1 0 1 PERFCOUNTER_LO 0 31 regSPI_PERFCOUNTER2_HI 0 0x3184 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER2_LO 0 0x3185 1 0 1 PERFCOUNTER_LO 0 31 regSPI_PERFCOUNTER3_HI 0 0x3186 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER3_LO 0 0x3187 1 0 1 PERFCOUNTER_LO 0 31 regSPI_PERFCOUNTER4_HI 0 0x3188 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER4_LO 0 0x3189 1 0 1 PERFCOUNTER_LO 0 31 regSPI_PERFCOUNTER5_HI 0 0x318a 1 0 1 PERFCOUNTER_HI 0 31 regSPI_PERFCOUNTER5_LO 0 0x318b 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER0_LO 0 0x31c0 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER0_HI 0 0x31c1 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER1_LO 0 0x31c2 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER1_HI 0 0x31c3 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER2_LO 0 0x31c4 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER2_HI 0 0x31c5 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER3_LO 0 0x31c6 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER3_HI 0 0x31c7 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER4_LO 0 0x31c8 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER4_HI 0 0x31c9 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER5_LO 0 0x31ca 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER5_HI 0 0x31cb 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER6_LO 0 0x31cc 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER6_HI 0 0x31cd 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER7_LO 0 0x31ce 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER7_HI 0 0x31cf 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER8_LO 0 0x31d0 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER8_HI 0 0x31d1 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER9_LO 0 0x31d2 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER9_HI 0 0x31d3 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER10_LO 0 0x31d4 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER10_HI 0 0x31d5 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER11_LO 0 0x31d6 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER11_HI 0 0x31d7 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER12_LO 0 0x31d8 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER12_HI 0 0x31d9 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER13_LO 0 0x31da 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER13_HI 0 0x31db 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER14_LO 0 0x31dc 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER14_HI 0 0x31dd 1 0 1 PERFCOUNTER_HI 0 31 regSQ_PERFCOUNTER15_LO 0 0x31de 1 0 1 PERFCOUNTER_LO 0 31 regSQ_PERFCOUNTER15_HI 0 0x31df 1 0 1 PERFCOUNTER_HI 0 31 regSX_PERFCOUNTER0_LO 0 0x3240 1 0 1 PERFCOUNTER_LO 0 31 regSX_PERFCOUNTER0_HI 0 0x3241 1 0 1 PERFCOUNTER_HI 0 31 regSX_PERFCOUNTER1_LO 0 0x3242 1 0 1 PERFCOUNTER_LO 0 31 regSX_PERFCOUNTER1_HI 0 0x3243 1 0 1 PERFCOUNTER_HI 0 31 regSX_PERFCOUNTER2_LO 0 0x3244 1 0 1 PERFCOUNTER_LO 0 31 regSX_PERFCOUNTER2_HI 0 0x3245 1 0 1 PERFCOUNTER_HI 0 31 regSX_PERFCOUNTER3_LO 0 0x3246 1 0 1 PERFCOUNTER_LO 0 31 regSX_PERFCOUNTER3_HI 0 0x3247 1 0 1 PERFCOUNTER_HI 0 31 regGDS_PERFCOUNTER0_LO 0 0x3280 1 0 1 PERFCOUNTER_LO 0 31 regGDS_PERFCOUNTER0_HI 0 0x3281 1 0 1 PERFCOUNTER_HI 0 31 regGDS_PERFCOUNTER1_LO 0 0x3282 1 0 1 PERFCOUNTER_LO 0 31 regGDS_PERFCOUNTER1_HI 0 0x3283 1 0 1 PERFCOUNTER_HI 0 31 regGDS_PERFCOUNTER2_LO 0 0x3284 1 0 1 PERFCOUNTER_LO 0 31 regGDS_PERFCOUNTER2_HI 0 0x3285 1 0 1 PERFCOUNTER_HI 0 31 regGDS_PERFCOUNTER3_LO 0 0x3286 1 0 1 PERFCOUNTER_LO 0 31 regGDS_PERFCOUNTER3_HI 0 0x3287 1 0 1 PERFCOUNTER_HI 0 31 regTA_PERFCOUNTER0_LO 0 0x32c0 1 0 1 PERFCOUNTER_LO 0 31 regTA_PERFCOUNTER0_HI 0 0x32c1 1 0 1 PERFCOUNTER_HI 0 31 regTA_PERFCOUNTER1_LO 0 0x32c2 1 0 1 PERFCOUNTER_LO 0 31 regTA_PERFCOUNTER1_HI 0 0x32c3 1 0 1 PERFCOUNTER_HI 0 31 regTD_PERFCOUNTER0_LO 0 0x3300 1 0 1 PERFCOUNTER_LO 0 31 regTD_PERFCOUNTER0_HI 0 0x3301 1 0 1 PERFCOUNTER_HI 0 31 regTD_PERFCOUNTER1_LO 0 0x3302 1 0 1 PERFCOUNTER_LO 0 31 regTD_PERFCOUNTER1_HI 0 0x3303 1 0 1 PERFCOUNTER_HI 0 31 regTCP_PERFCOUNTER0_LO 0 0x3340 1 0 1 PERFCOUNTER_LO 0 31 regTCP_PERFCOUNTER0_HI 0 0x3341 1 0 1 PERFCOUNTER_HI 0 31 regTCP_PERFCOUNTER1_LO 0 0x3342 1 0 1 PERFCOUNTER_LO 0 31 regTCP_PERFCOUNTER1_HI 0 0x3343 1 0 1 PERFCOUNTER_HI 0 31 regTCP_PERFCOUNTER2_LO 0 0x3344 1 0 1 PERFCOUNTER_LO 0 31 regTCP_PERFCOUNTER2_HI 0 0x3345 1 0 1 PERFCOUNTER_HI 0 31 regTCP_PERFCOUNTER3_LO 0 0x3346 1 0 1 PERFCOUNTER_LO 0 31 regTCP_PERFCOUNTER3_HI 0 0x3347 1 0 1 PERFCOUNTER_HI 0 31 regTCC_PERFCOUNTER0_LO 0 0x3380 1 0 1 PERFCOUNTER_LO 0 31 regTCC_PERFCOUNTER0_HI 0 0x3381 1 0 1 PERFCOUNTER_HI 0 31 regTCC_PERFCOUNTER1_LO 0 0x3382 1 0 1 PERFCOUNTER_LO 0 31 regTCC_PERFCOUNTER1_HI 0 0x3383 1 0 1 PERFCOUNTER_HI 0 31 regTCC_PERFCOUNTER2_LO 0 0x3384 1 0 1 PERFCOUNTER_LO 0 31 regTCC_PERFCOUNTER2_HI 0 0x3385 1 0 1 PERFCOUNTER_HI 0 31 regTCC_PERFCOUNTER3_LO 0 0x3386 1 0 1 PERFCOUNTER_LO 0 31 regTCC_PERFCOUNTER3_HI 0 0x3387 1 0 1 PERFCOUNTER_HI 0 31 regTCA_PERFCOUNTER0_LO 0 0x3390 1 0 1 PERFCOUNTER_LO 0 31 regTCA_PERFCOUNTER0_HI 0 0x3391 1 0 1 PERFCOUNTER_HI 0 31 regTCA_PERFCOUNTER1_LO 0 0x3392 1 0 1 PERFCOUNTER_LO 0 31 regTCA_PERFCOUNTER1_HI 0 0x3393 1 0 1 PERFCOUNTER_HI 0 31 regTCA_PERFCOUNTER2_LO 0 0x3394 1 0 1 PERFCOUNTER_LO 0 31 regTCA_PERFCOUNTER2_HI 0 0x3395 1 0 1 PERFCOUNTER_HI 0 31 regTCA_PERFCOUNTER3_LO 0 0x3396 1 0 1 PERFCOUNTER_LO 0 31 regTCA_PERFCOUNTER3_HI 0 0x3397 1 0 1 PERFCOUNTER_HI 0 31 regCB_PERFCOUNTER0_LO 0 0x3406 1 0 1 PERFCOUNTER_LO 0 31 regCB_PERFCOUNTER0_HI 0 0x3407 1 0 1 PERFCOUNTER_HI 0 31 regCB_PERFCOUNTER1_LO 0 0x3408 1 0 1 PERFCOUNTER_LO 0 31 regCB_PERFCOUNTER1_HI 0 0x3409 1 0 1 PERFCOUNTER_HI 0 31 regCB_PERFCOUNTER2_LO 0 0x340a 1 0 1 PERFCOUNTER_LO 0 31 regCB_PERFCOUNTER2_HI 0 0x340b 1 0 1 PERFCOUNTER_HI 0 31 regCB_PERFCOUNTER3_LO 0 0x340c 1 0 1 PERFCOUNTER_LO 0 31 regCB_PERFCOUNTER3_HI 0 0x340d 1 0 1 PERFCOUNTER_HI 0 31 regDB_PERFCOUNTER0_LO 0 0x3440 1 0 1 PERFCOUNTER_LO 0 31 regDB_PERFCOUNTER0_HI 0 0x3441 1 0 1 PERFCOUNTER_HI 0 31 regDB_PERFCOUNTER1_LO 0 0x3442 1 0 1 PERFCOUNTER_LO 0 31 regDB_PERFCOUNTER1_HI 0 0x3443 1 0 1 PERFCOUNTER_HI 0 31 regDB_PERFCOUNTER2_LO 0 0x3444 1 0 1 PERFCOUNTER_LO 0 31 regDB_PERFCOUNTER2_HI 0 0x3445 1 0 1 PERFCOUNTER_HI 0 31 regDB_PERFCOUNTER3_LO 0 0x3446 1 0 1 PERFCOUNTER_LO 0 31 regDB_PERFCOUNTER3_HI 0 0x3447 1 0 1 PERFCOUNTER_HI 0 31 regRLC_PERFCOUNTER0_LO 0 0x3480 1 0 1 PERFCOUNTER_LO 0 31 regRLC_PERFCOUNTER0_HI 0 0x3481 1 0 1 PERFCOUNTER_HI 0 31 regRLC_PERFCOUNTER1_LO 0 0x3482 1 0 1 PERFCOUNTER_LO 0 31 regRLC_PERFCOUNTER1_HI 0 0x3483 1 0 1 PERFCOUNTER_HI 0 31 regRMI_PERFCOUNTER0_LO 0 0x34c0 1 0 1 PERFCOUNTER_LO 0 31 regRMI_PERFCOUNTER0_HI 0 0x34c1 1 0 1 PERFCOUNTER_HI 0 31 regRMI_PERFCOUNTER1_LO 0 0x34c2 1 0 1 PERFCOUNTER_LO 0 31 regRMI_PERFCOUNTER1_HI 0 0x34c3 1 0 1 PERFCOUNTER_HI 0 31 regRMI_PERFCOUNTER2_LO 0 0x34c4 1 0 1 PERFCOUNTER_LO 0 31 regRMI_PERFCOUNTER2_HI 0 0x34c5 1 0 1 PERFCOUNTER_HI 0 31 regRMI_PERFCOUNTER3_LO 0 0x34c6 1 0 1 PERFCOUNTER_LO 0 31 regRMI_PERFCOUNTER3_HI 0 0x34c7 1 0 1 PERFCOUNTER_HI 0 31 regCPG_PERFCOUNTER1_SELECT 0 0x3800 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCPG_PERFCOUNTER0_SELECT1 0 0x3801 4 0 1 CNTR_SEL2 0 9 CNTR_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 regCPG_PERFCOUNTER0_SELECT 0 0x3802 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCPC_PERFCOUNTER1_SELECT 0 0x3803 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCPC_PERFCOUNTER0_SELECT1 0 0x3804 4 0 1 CNTR_SEL2 0 9 CNTR_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 regCPF_PERFCOUNTER1_SELECT 0 0x3805 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCPF_PERFCOUNTER0_SELECT1 0 0x3806 4 0 1 CNTR_SEL2 0 9 CNTR_SEL3 10 19 CNTR_MODE3 24 27 CNTR_MODE2 28 31 regCPF_PERFCOUNTER0_SELECT 0 0x3807 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCP_PERFMON_CNTL 0 0x3808 4 0 1 PERFMON_STATE 0 3 SPM_PERFMON_STATE 4 7 PERFMON_ENABLE_MODE 8 9 PERFMON_SAMPLE_ENABLE 10 10 regCPC_PERFCOUNTER0_SELECT 0 0x3809 5 0 1 CNTR_SEL0 0 9 CNTR_SEL1 10 19 SPM_MODE 20 23 CNTR_MODE1 24 27 CNTR_MODE0 28 31 regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0 0x380a 3 0 1 INDEX 0 2 ALWAYS 30 30 ENABLE 31 31 regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0 0x380b 3 0 1 INDEX 0 4 ALWAYS 30 30 ENABLE 31 31 regCPF_LATENCY_STATS_SELECT 0 0x380c 3 0 1 INDEX 0 3 CLEAR 30 30 ENABLE 31 31 regCPG_LATENCY_STATS_SELECT 0 0x380d 3 0 1 INDEX 0 4 CLEAR 30 30 ENABLE 31 31 regCPC_LATENCY_STATS_SELECT 0 0x380e 3 0 1 INDEX 0 2 CLEAR 30 30 ENABLE 31 31 regCP_DRAW_OBJECT 0 0x3810 1 0 1 OBJECT 0 31 regCP_DRAW_OBJECT_COUNTER 0 0x3811 1 0 1 COUNT 0 15 regCP_DRAW_WINDOW_MASK_HI 0 0x3812 1 0 1 WINDOW_MASK_HI 0 31 regCP_DRAW_WINDOW_HI 0 0x3813 1 0 1 WINDOW_HI 0 31 regCP_DRAW_WINDOW_LO 0 0x3814 2 0 1 MIN 0 15 MAX 16 31 regCP_DRAW_WINDOW_CNTL 0 0x3815 4 0 1 DISABLE_DRAW_WINDOW_LO_MAX 0 0 DISABLE_DRAW_WINDOW_LO_MIN 1 1 DISABLE_DRAW_WINDOW_HI 2 2 MODE 8 8 regGRBM_PERFCOUNTER0_SELECT 0 0x3840 22 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 VGT_BUSY_USER_DEFINED_MASK 12 12 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 IA_BUSY_USER_DEFINED_MASK 23 23 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TC_BUSY_USER_DEFINED_MASK 27 27 WD_BUSY_USER_DEFINED_MASK 28 28 UTCL2_BUSY_USER_DEFINED_MASK 29 29 EA_BUSY_USER_DEFINED_MASK 30 30 RMI_BUSY_USER_DEFINED_MASK 31 31 regGRBM_PERFCOUNTER1_SELECT 0 0x3841 22 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 VGT_BUSY_USER_DEFINED_MASK 12 12 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 IA_BUSY_USER_DEFINED_MASK 23 23 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TC_BUSY_USER_DEFINED_MASK 27 27 WD_BUSY_USER_DEFINED_MASK 28 28 UTCL2_BUSY_USER_DEFINED_MASK 29 29 EA_BUSY_USER_DEFINED_MASK 30 30 RMI_BUSY_USER_DEFINED_MASK 31 31 regGRBM_SE0_PERFCOUNTER_SELECT 0 0x3842 16 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 TA_BUSY_USER_DEFINED_MASK_SE4 23 23 SX_BUSY_USER_DEFINED_MASK_SE4 24 24 SPI_BUSY_USER_DEFINED_MASK_SE4 25 25 regGRBM_SE1_PERFCOUNTER_SELECT 0 0x3843 16 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 TA_BUSY_USER_DEFINED_MASK_SE5 23 23 SX_BUSY_USER_DEFINED_MASK_SE5 24 24 SPI_BUSY_USER_DEFINED_MASK_SE5 25 25 regGRBM_SE2_PERFCOUNTER_SELECT 0 0x3844 16 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 TA_BUSY_USER_DEFINED_MASK_SE6 23 23 SX_BUSY_USER_DEFINED_MASK_SE6 24 24 SPI_BUSY_USER_DEFINED_MASK_SE6 25 25 regGRBM_SE3_PERFCOUNTER_SELECT 0 0x3845 16 0 1 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 RMI_BUSY_USER_DEFINED_MASK 22 22 TA_BUSY_USER_DEFINED_MASK_SE7 23 23 SX_BUSY_USER_DEFINED_MASK_SE7 24 24 SPI_BUSY_USER_DEFINED_MASK_SE7 25 25 regWD_PERFCOUNTER0_SELECT 0 0x3880 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regWD_PERFCOUNTER1_SELECT 0 0x3881 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regWD_PERFCOUNTER2_SELECT 0 0x3882 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regWD_PERFCOUNTER3_SELECT 0 0x3883 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regIA_PERFCOUNTER0_SELECT 0 0x3884 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regIA_PERFCOUNTER1_SELECT 0 0x3885 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regIA_PERFCOUNTER2_SELECT 0 0x3886 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regIA_PERFCOUNTER3_SELECT 0 0x3887 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regIA_PERFCOUNTER0_SELECT1 0 0x3888 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regVGT_PERFCOUNTER0_SELECT 0 0x388c 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regVGT_PERFCOUNTER1_SELECT 0 0x388d 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regVGT_PERFCOUNTER2_SELECT 0 0x388e 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regVGT_PERFCOUNTER3_SELECT 0 0x388f 2 0 1 PERF_SEL 0 7 PERF_MODE 28 31 regVGT_PERFCOUNTER0_SELECT1 0 0x3890 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regVGT_PERFCOUNTER1_SELECT1 0 0x3891 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regVGT_PERFCOUNTER_SEID_MASK 0 0x3894 1 0 1 PERF_SEID_IGNORE_MASK 0 7 regPA_SU_PERFCOUNTER0_SELECT 0 0x3900 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regPA_SU_PERFCOUNTER0_SELECT1 0 0x3901 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regPA_SU_PERFCOUNTER1_SELECT 0 0x3902 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regPA_SU_PERFCOUNTER1_SELECT1 0 0x3903 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regPA_SU_PERFCOUNTER2_SELECT 0 0x3904 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regPA_SU_PERFCOUNTER3_SELECT 0 0x3905 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regPA_SC_PERFCOUNTER0_SELECT 0 0x3940 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regPA_SC_PERFCOUNTER0_SELECT1 0 0x3941 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regPA_SC_PERFCOUNTER1_SELECT 0 0x3942 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER2_SELECT 0 0x3943 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER3_SELECT 0 0x3944 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER4_SELECT 0 0x3945 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER5_SELECT 0 0x3946 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER6_SELECT 0 0x3947 1 0 1 PERF_SEL 0 9 regPA_SC_PERFCOUNTER7_SELECT 0 0x3948 1 0 1 PERF_SEL 0 9 regSPI_PERFCOUNTER0_SELECT 0 0x3980 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSPI_PERFCOUNTER1_SELECT 0 0x3981 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSPI_PERFCOUNTER2_SELECT 0 0x3982 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSPI_PERFCOUNTER3_SELECT 0 0x3983 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSPI_PERFCOUNTER0_SELECT1 0 0x3984 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regSPI_PERFCOUNTER1_SELECT1 0 0x3985 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regSPI_PERFCOUNTER2_SELECT1 0 0x3986 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regSPI_PERFCOUNTER3_SELECT1 0 0x3987 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regSPI_PERFCOUNTER4_SELECT 0 0x3988 1 0 1 PERF_SEL 0 7 regSPI_PERFCOUNTER5_SELECT 0 0x3989 1 0 1 PERF_SEL 0 7 regSPI_PERFCOUNTER_BINS 0 0x398a 8 0 1 BIN0_MIN 0 3 BIN0_MAX 4 7 BIN1_MIN 8 11 BIN1_MAX 12 15 BIN2_MIN 16 19 BIN2_MAX 20 23 BIN3_MIN 24 27 BIN3_MAX 28 31 regSQ_PERFCOUNTER0_SELECT 0 0x39c0 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER1_SELECT 0 0x39c1 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER2_SELECT 0 0x39c2 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER3_SELECT 0 0x39c3 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER4_SELECT 0 0x39c4 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER5_SELECT 0 0x39c5 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER6_SELECT 0 0x39c6 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER7_SELECT 0 0x39c7 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER8_SELECT 0 0x39c8 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER9_SELECT 0 0x39c9 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER10_SELECT 0 0x39ca 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER11_SELECT 0 0x39cb 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER12_SELECT 0 0x39cc 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER13_SELECT 0 0x39cd 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER14_SELECT 0 0x39ce 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER15_SELECT 0 0x39cf 6 0 1 PERF_SEL 0 8 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 regSQ_PERFCOUNTER_CTRL 0 0x39e0 10 0 1 PS_EN 0 0 VS_EN 1 1 GS_EN 2 2 ES_EN 3 3 HS_EN 4 4 LS_EN 5 5 CS_EN 6 6 CNTR_RATE 8 12 DISABLE_FLUSH 13 13 VMID_MASK 16 31 regSQ_PERFCOUNTER_MASK 0 0x39e1 2 0 1 SH0_MASK 0 15 SH1_MASK 16 31 regSQ_PERFCOUNTER_CTRL2 0 0x39e2 1 0 1 FORCE_EN 0 0 regSX_PERFCOUNTER0_SELECT 0 0x3a40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSX_PERFCOUNTER1_SELECT 0 0x3a41 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regSX_PERFCOUNTER2_SELECT 0 0x3a42 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regSX_PERFCOUNTER3_SELECT 0 0x3a43 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regSX_PERFCOUNTER0_SELECT1 0 0x3a44 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regSX_PERFCOUNTER1_SELECT1 0 0x3a45 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regGDS_PERFCOUNTER0_SELECT 0 0x3a80 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regGDS_PERFCOUNTER1_SELECT 0 0x3a81 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regGDS_PERFCOUNTER2_SELECT 0 0x3a82 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regGDS_PERFCOUNTER3_SELECT 0 0x3a83 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regGDS_PERFCOUNTER0_SELECT1 0 0x3a84 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regTA_PERFCOUNTER0_SELECT 0 0x3ac0 5 0 1 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTA_PERFCOUNTER0_SELECT1 0 0x3ac1 4 0 1 PERF_SEL2 0 7 PERF_SEL3 10 17 PERF_MODE3 24 27 PERF_MODE2 28 31 regTA_PERFCOUNTER1_SELECT 0 0x3ac2 3 0 1 PERF_SEL 0 7 CNTR_MODE 20 23 PERF_MODE 28 31 regTD_PERFCOUNTER0_SELECT 0 0x3b00 5 0 1 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTD_PERFCOUNTER0_SELECT1 0 0x3b01 4 0 1 PERF_SEL2 0 7 PERF_SEL3 10 17 PERF_MODE3 24 27 PERF_MODE2 28 31 regTD_PERFCOUNTER1_SELECT 0 0x3b02 3 0 1 PERF_SEL 0 7 CNTR_MODE 20 23 PERF_MODE 28 31 regTCP_PERFCOUNTER0_SELECT 0 0x3b40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCP_PERFCOUNTER0_SELECT1 0 0x3b41 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regTCP_PERFCOUNTER1_SELECT 0 0x3b42 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCP_PERFCOUNTER1_SELECT1 0 0x3b43 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regTCP_PERFCOUNTER2_SELECT 0 0x3b44 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regTCP_PERFCOUNTER3_SELECT 0 0x3b45 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regTCC_PERFCOUNTER0_SELECT 0 0x3b80 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCC_PERFCOUNTER0_SELECT1 0 0x3b81 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 regTCC_PERFCOUNTER1_SELECT 0 0x3b82 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCC_PERFCOUNTER1_SELECT1 0 0x3b83 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 regTCC_PERFCOUNTER2_SELECT 0 0x3b84 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regTCC_PERFCOUNTER3_SELECT 0 0x3b85 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regTCA_PERFCOUNTER0_SELECT 0 0x3b90 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCA_PERFCOUNTER0_SELECT1 0 0x3b91 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 regTCA_PERFCOUNTER1_SELECT 0 0x3b92 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regTCA_PERFCOUNTER1_SELECT1 0 0x3b93 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 regTCA_PERFCOUNTER2_SELECT 0 0x3b94 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regTCA_PERFCOUNTER3_SELECT 0 0x3b95 3 0 1 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 regCB_PERFCOUNTER_FILTER 0 0x3c00 12 0 1 OP_FILTER_ENABLE 0 0 OP_FILTER_SEL 1 3 FORMAT_FILTER_ENABLE 4 4 FORMAT_FILTER_SEL 5 9 CLEAR_FILTER_ENABLE 10 10 CLEAR_FILTER_SEL 11 11 MRT_FILTER_ENABLE 12 12 MRT_FILTER_SEL 13 15 NUM_SAMPLES_FILTER_ENABLE 17 17 NUM_SAMPLES_FILTER_SEL 18 20 NUM_FRAGMENTS_FILTER_ENABLE 21 21 NUM_FRAGMENTS_FILTER_SEL 22 23 regCB_PERFCOUNTER0_SELECT 0 0x3c01 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regCB_PERFCOUNTER0_SELECT1 0 0x3c02 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 regCB_PERFCOUNTER1_SELECT 0 0x3c03 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 regCB_PERFCOUNTER2_SELECT 0 0x3c04 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 regCB_PERFCOUNTER3_SELECT 0 0x3c05 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 regDB_PERFCOUNTER0_SELECT 0 0x3c40 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regDB_PERFCOUNTER0_SELECT1 0 0x3c41 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regDB_PERFCOUNTER1_SELECT 0 0x3c42 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regDB_PERFCOUNTER1_SELECT1 0 0x3c43 4 0 1 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 regDB_PERFCOUNTER2_SELECT 0 0x3c44 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regDB_PERFCOUNTER3_SELECT 0 0x3c46 5 0 1 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regRLC_SPM_PERFMON_CNTL 0 0x3c80 4 0 1 RESERVED1 0 11 PERFMON_RING_MODE 12 13 RESERVED 14 15 PERFMON_SAMPLE_INTERVAL 16 31 regRLC_SPM_PERFMON_RING_BASE_LO 0 0x3c81 1 0 1 RING_BASE_LO 0 31 regRLC_SPM_PERFMON_RING_BASE_HI 0 0x3c82 2 0 1 RING_BASE_HI 0 15 RESERVED 16 31 regRLC_SPM_PERFMON_RING_SIZE 0 0x3c83 1 0 1 RING_BASE_SIZE 0 31 regRLC_SPM_PERFMON_SEGMENT_SIZE 0 0x3c84 7 0 1 PERFMON_SEGMENT_SIZE 0 7 RESERVED1 8 10 GLOBAL_NUM_LINE 11 15 SE0_NUM_LINE 16 20 SE1_NUM_LINE 21 25 SE2_NUM_LINE 26 30 RESERVED 31 31 regRLC_SPM_SE_MUXSEL_ADDR 0 0x3c85 1 0 1 PERFMON_SEL_ADDR 0 31 regRLC_SPM_SE_MUXSEL_DATA 0 0x3c86 1 0 1 PERFMON_SEL_DATA 0 31 regRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0 0x3c87 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0 0x3c88 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0 0x3c89 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0 0x3c8a 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0 0x3c8b 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0 0x3c8c 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0 0x3c8d 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0 0x3c8e 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0 0x3c90 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0 0x3c91 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0 0x3c92 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0 0x3c93 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0 0x3c94 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0 0x3c95 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0 0x3c96 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0 0x3c97 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0 0x3c98 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0 0x3c9a 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_GLOBAL_MUXSEL_ADDR 0 0x3c9b 1 0 1 PERFMON_SEL_ADDR 0 31 regRLC_SPM_GLOBAL_MUXSEL_DATA 0 0x3c9c 1 0 1 PERFMON_SEL_DATA 0 31 regRLC_SPM_RING_RDPTR 0 0x3c9d 1 0 1 PERFMON_RING_RDPTR 0 31 regRLC_SPM_SEGMENT_THRESHOLD 0 0x3c9e 1 0 1 NUM_SEGMENT_THRESHOLD 0 31 regRLC_SPM_RMI_PERFMON_SAMPLE_DELAY 0 0x3ca3 2 0 1 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_PERFMON_SAMPLE_DELAY_MAX 0 0x3ca4 2 0 1 PERFMON_MAX_SAMPLE_DELAY 0 7 RESERVED 8 31 regRLC_SPM_PERFMON_SEGMENT_SIZE_CORE1 0 0x3caf 6 0 1 PERFMON_SEGMENT_SIZE_CORE1 0 6 RESERVED1 7 11 SE4_NUM_LINE 12 16 SE5_NUM_LINE 17 21 SE6_NUM_LINE 22 26 SE7_NUM_LINE 27 31 regRLC_PERFMON_CLK_CNTL_UCODE 0 0x3cbe 1 0 1 PERFMON_CLOCK_STATE 0 0 regRLC_PERFMON_CLK_CNTL 0 0x3cbf 1 0 1 PERFMON_CLOCK_STATE 0 0 regRLC_PERFMON_CNTL 0 0x3cc0 2 0 1 PERFMON_STATE 0 2 PERFMON_SAMPLE_ENABLE 10 10 regRLC_PERFCOUNTER0_SELECT 0 0x3cc1 1 0 1 PERFCOUNTER_SELECT 0 7 regRLC_PERFCOUNTER1_SELECT 0 0x3cc2 1 0 1 PERFCOUNTER_SELECT 0 7 regRLC_GPU_IOV_PERF_CNT_CNTL 0 0x3cc3 4 0 1 ENABLE 0 0 MODE_SELECT 1 1 RESET 2 2 RESERVED 3 31 regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0 0x3cc4 3 0 1 VFID 0 3 CNT_ID 4 5 RESERVED 6 31 regRLC_GPU_IOV_PERF_CNT_WR_DATA 0 0x3cc5 1 0 1 DATA 0 3 regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0 0x3cc6 3 0 1 VFID 0 3 CNT_ID 4 5 RESERVED 6 31 regRLC_GPU_IOV_PERF_CNT_RD_DATA 0 0x3cc7 1 0 1 DATA 0 3 regRMI_PERFCOUNTER0_SELECT 0 0x3d00 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regRMI_PERFCOUNTER0_SELECT1 0 0x3d01 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 regRMI_PERFCOUNTER1_SELECT 0 0x3d02 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 regRMI_PERFCOUNTER2_SELECT 0 0x3d03 5 0 1 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 regRMI_PERFCOUNTER2_SELECT1 0 0x3d04 4 0 1 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 regRMI_PERFCOUNTER3_SELECT 0 0x3d05 2 0 1 PERF_SEL 0 8 PERF_MODE 28 31 regRMI_PERF_COUNTER_CNTL 0 0x3d06 10 0 1 TRANS_BASED_PERF_EN_SEL 0 1 EVENT_BASED_PERF_EN_SEL 2 3 TC_PERF_EN_SEL 4 5 PERF_EVENT_WINDOW_MASK0 6 7 PERF_EVENT_WINDOW_MASK1 8 9 PERF_COUNTER_CID 10 13 PERF_COUNTER_VMID 14 18 PERF_COUNTER_BURST_LENGTH_THRESHOLD 19 24 PERF_SOFT_RESET 25 25 PERF_CNTR_SPM_SEL 26 26 regCGTS_SM_CTRL_REG 0 0x5000 10 0 1 ON_SEQ_DELAY 0 3 OFF_SEQ_DELAY 4 11 MGCG_ENABLED 12 12 BASE_MODE 16 16 SM_MODE 17 19 SM_MODE_ENABLE 20 20 OVERRIDE 21 21 LS_OVERRIDE 22 22 ON_MONITOR_ADD_EN 23 23 ON_MONITOR_ADD 24 31 regCGTS_RD_CTRL_REG 0 0x5001 2 0 1 ROW_MUX_SEL 0 4 REG_MUX_SEL 8 12 regCGTS_RD_REG 0 0x5002 1 0 1 READ_DATA 0 13 regCGTS_TCC_DISABLE 0 0x5003 1 0 1 TCC_DISABLE 16 31 regCGTS_USER_TCC_DISABLE 0 0x5004 1 0 1 TCC_DISABLE 16 31 regCGTS_TCC_DISABLE2 0 0x5005 1 0 1 TCC_DISABLE 16 31 regCGTS_USER_TCC_DISABLE2 0 0x5006 1 0 1 TCC_DISABLE 16 31 regCGTS_CU0_SP0_CTRL_REG 0 0x5008 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU0_LDS_SQ_CTRL_REG 0 0x5009 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU0_TA_SQC_CTRL_REG 0 0x500a 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU0_SP1_CTRL_REG 0 0x500b 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU1_SP0_CTRL_REG 0 0x500d 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU1_LDS_SQ_CTRL_REG 0 0x500e 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU1_TA_SQC_CTRL_REG 0 0x500f 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU1_SP1_CTRL_REG 0 0x5010 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU2_SP0_CTRL_REG 0 0x5012 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU2_LDS_SQ_CTRL_REG 0 0x5013 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU2_TA_SQC_CTRL_REG 0 0x5014 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU2_SP1_CTRL_REG 0 0x5015 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU3_SP0_CTRL_REG 0 0x5017 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU3_LDS_SQ_CTRL_REG 0 0x5018 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU3_TA_SQC_CTRL_REG 0 0x5019 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU3_SP1_CTRL_REG 0 0x501a 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU4_SP0_CTRL_REG 0 0x501c 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU4_LDS_SQ_CTRL_REG 0 0x501d 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU4_TA_SQC_CTRL_REG 0 0x501e 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU4_SP1_CTRL_REG 0 0x501f 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU5_SP0_CTRL_REG 0 0x5021 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU5_LDS_SQ_CTRL_REG 0 0x5022 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU5_TA_SQC_CTRL_REG 0 0x5023 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU5_SP1_CTRL_REG 0 0x5024 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU6_SP0_CTRL_REG 0 0x5026 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU6_LDS_SQ_CTRL_REG 0 0x5027 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU6_TA_SQC_CTRL_REG 0 0x5028 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU6_SP1_CTRL_REG 0 0x5029 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU7_SP0_CTRL_REG 0 0x502b 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU7_LDS_SQ_CTRL_REG 0 0x502c 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU7_TA_SQC_CTRL_REG 0 0x502d 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU7_SP1_CTRL_REG 0 0x502e 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU8_SP0_CTRL_REG 0 0x5030 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU8_LDS_SQ_CTRL_REG 0 0x5031 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU8_TA_SQC_CTRL_REG 0 0x5032 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU8_SP1_CTRL_REG 0 0x5033 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU9_SP0_CTRL_REG 0 0x5035 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU9_LDS_SQ_CTRL_REG 0 0x5036 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU9_TA_SQC_CTRL_REG 0 0x5037 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU9_SP1_CTRL_REG 0 0x5038 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU10_SP0_CTRL_REG 0 0x503a 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU10_LDS_SQ_CTRL_REG 0 0x503b 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU10_TA_SQC_CTRL_REG 0 0x503c 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU10_SP1_CTRL_REG 0 0x503d 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU11_SP0_CTRL_REG 0 0x503f 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU11_LDS_SQ_CTRL_REG 0 0x5040 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU11_TA_SQC_CTRL_REG 0 0x5041 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU11_SP1_CTRL_REG 0 0x5042 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU12_SP0_CTRL_REG 0 0x5044 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU12_LDS_SQ_CTRL_REG 0 0x5045 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU12_TA_SQC_CTRL_REG 0 0x5046 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU12_SP1_CTRL_REG 0 0x5047 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU13_SP0_CTRL_REG 0 0x5049 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU13_LDS_SQ_CTRL_REG 0 0x504a 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU13_TA_SQC_CTRL_REG 0 0x504b 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU13_SP1_CTRL_REG 0 0x504c 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU14_SP0_CTRL_REG 0 0x504e 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU14_LDS_SQ_CTRL_REG 0 0x504f 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU14_TA_SQC_CTRL_REG 0 0x5050 10 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU14_SP1_CTRL_REG 0 0x5051 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU15_SP0_CTRL_REG 0 0x5053 10 0 1 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU15_LDS_SQ_CTRL_REG 0 0x5054 10 0 1 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU15_TA_SQC_CTRL_REG 0 0x5055 5 0 1 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 regCGTS_CU15_SP1_CTRL_REG 0 0x5056 10 0 1 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 regCGTS_CU0_TCPI_CTRL_REG 0 0x5058 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU1_TCPI_CTRL_REG 0 0x5059 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU2_TCPI_CTRL_REG 0 0x505a 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU3_TCPI_CTRL_REG 0 0x505b 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU4_TCPI_CTRL_REG 0 0x505c 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU5_TCPI_CTRL_REG 0 0x505d 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU6_TCPI_CTRL_REG 0 0x505e 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU7_TCPI_CTRL_REG 0 0x505f 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU8_TCPI_CTRL_REG 0 0x5060 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU9_TCPI_CTRL_REG 0 0x5061 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU10_TCPI_CTRL_REG 0 0x5062 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU11_TCPI_CTRL_REG 0 0x5063 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU12_TCPI_CTRL_REG 0 0x5064 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU13_TCPI_CTRL_REG 0 0x5065 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU14_TCPI_CTRL_REG 0 0x5066 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTS_CU15_TCPI_CTRL_REG 0 0x5067 6 0 1 TCPI 0 6 TCPI_OVERRIDE 7 7 TCPI_BUSY_OVERRIDE 8 9 TCPI_LS_OVERRIDE 10 10 TCPI_SIMDBUSY_OVERRIDE 11 11 RESERVED 12 31 regCGTT_SPI_PS_CLK_CTRL 0 0x507d 17 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE6 16 16 SOFT_STALL_OVERRIDE5 17 17 SOFT_STALL_OVERRIDE4 18 18 SOFT_STALL_OVERRIDE3 19 19 SOFT_STALL_OVERRIDE2 20 20 SOFT_STALL_OVERRIDE1 21 21 SOFT_STALL_OVERRIDE0 22 22 GRP6_OVERRIDE 24 24 GRP5_OVERRIDE 25 25 GRP4_OVERRIDE 26 26 GRP3_OVERRIDE 27 27 GRP2_OVERRIDE 28 28 GRP1_OVERRIDE 29 29 GRP0_OVERRIDE 30 30 REG_OVERRIDE 31 31 regCGTT_SPIS_CLK_CTRL 0 0x507e 17 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE6 16 16 SOFT_STALL_OVERRIDE5 17 17 SOFT_STALL_OVERRIDE4 18 18 SOFT_STALL_OVERRIDE3 19 19 SOFT_STALL_OVERRIDE2 20 20 SOFT_STALL_OVERRIDE1 21 21 SOFT_STALL_OVERRIDE0 22 22 GRP6_OVERRIDE 24 24 GRP5_OVERRIDE 25 25 GRP4_OVERRIDE 26 26 GRP3_OVERRIDE 27 27 GRP2_OVERRIDE 28 28 GRP1_OVERRIDE 29 29 GRP0_OVERRIDE 30 30 REG_OVERRIDE 31 31 regCGTT_SPI_CLK_CTRL 0 0x5080 9 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE2 20 20 SOFT_STALL_OVERRIDE1 21 21 SOFT_STALL_OVERRIDE0 22 22 GRP2_OVERRIDE 28 28 GRP1_OVERRIDE 29 29 GRP0_OVERRIDE 30 30 REG_OVERRIDE 31 31 regCGTT_PC_CLK_CTRL 0 0x5081 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 PC_RAM_FGCG_OVERRIDE 17 17 GRP5_CG_OFF_HYST 18 23 GRP5_CG_OVERRIDE 24 24 PC_WRITE_CLK_EN_OVERRIDE 25 25 PC_READ_CLK_EN_OVERRIDE 26 26 CORE3_OVERRIDE 27 27 CORE2_OVERRIDE 28 28 CORE1_OVERRIDE 29 29 CORE0_OVERRIDE 30 30 REG_OVERRIDE 31 31 regCGTT_BCI_CLK_CTRL 0 0x5082 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 CORE6_OVERRIDE 24 24 CORE5_OVERRIDE 25 25 CORE4_OVERRIDE 26 26 CORE3_OVERRIDE 27 27 CORE2_OVERRIDE 28 28 CORE1_OVERRIDE 29 29 CORE0_OVERRIDE 30 30 REG_OVERRIDE 31 31 regCGTT_PA_CLK_CTRL 0 0x5088 17 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SU_CLK_OVERRIDE 29 29 CL_CLK_OVERRIDE 30 30 REG_CLK_OVERRIDE 31 31 regCGTT_SC_CLK_CTRL0 0 0x5089 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 PFF_ZFF_MEM_CLK_STALL_OVERRIDE 16 16 SOFT_STALL_OVERRIDE5 17 17 SOFT_STALL_OVERRIDE4 18 18 SOFT_STALL_OVERRIDE3 19 19 SOFT_STALL_OVERRIDE2 20 20 SOFT_STALL_OVERRIDE1 21 21 SOFT_STALL_OVERRIDE0 22 22 REG_CLK_STALL_OVERRIDE 23 23 PFF_ZFF_MEM_CLK_OVERRIDE 24 24 SOFT_OVERRIDE5 25 25 SOFT_OVERRIDE4 26 26 SOFT_OVERRIDE3 27 27 SOFT_OVERRIDE2 28 28 SOFT_OVERRIDE1 29 29 SOFT_OVERRIDE0 30 30 REG_CLK_OVERRIDE 31 31 regCGTT_SC_CLK_CTRL1 0 0x508a 14 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 PBB_BINNING_CLK_STALL_OVERRIDE 17 17 PBB_SCISSOR_CLK_STALL_OVERRIDE 18 18 OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE 19 19 SCREEN_EXT_REG_CLK_STALL_OVERRIDE 20 20 VPORT_REG_MEM_CLK_STALL_OVERRIDE 21 21 PBB_CLK_STALL_OVERRIDE 22 22 PBB_BINNING_CLK_OVERRIDE 25 25 PBB_SCISSOR_CLK_OVERRIDE 26 26 OTHER_SPECIAL_SC_REG_CLK_OVERRIDE 27 27 SCREEN_EXT_REG_CLK_OVERRIDE 28 28 VPORT_REG_MEM_CLK_OVERRIDE 29 29 PBB_CLK_OVERRIDE 30 30 regCGTT_SC_CLK_CTRL2 0 0x508b 6 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SCF_SCB_INTF_CLK_OVERRIDE 27 27 SC_PKR_INTF_CLK_OVERRIDE 28 28 SC_DB_INTF_CLK_OVERRIDE 29 29 PA_SC_INTF_CLK_OVERRIDE 30 30 regCGTT_SQG_CLK_CTRL 0 0x508d 14 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 TTRACE_OVERRIDE 28 28 PERFMON_OVERRIDE 29 29 CORE_OVERRIDE 30 30 REG_OVERRIDE 31 31 regSQ_ALU_CLK_CTRL 0 0x508e 2 0 1 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 regSQ_TEX_CLK_CTRL 0 0x508f 2 0 1 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 regSQ_LDS_CLK_CTRL 0 0x5090 2 0 1 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 regSQ_POWER_THROTTLE 0 0x5091 3 0 1 MIN_POWER 0 13 MAX_POWER 16 29 PHASE_OFFSET 30 31 regSQ_POWER_THROTTLE2 0 0x5092 4 0 1 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 USE_REF_CLOCK 31 31 regCGTT_SX_CLK_CTRL0 0 0x5094 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_SX_CLK_CTRL1 0 0x5095 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_SX_CLK_CTRL2 0 0x5096 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 13 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_SX_CLK_CTRL3 0 0x5097 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 13 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_SX_CLK_CTRL4 0 0x5098 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regTD_CGTT_CTRL 0 0x509c 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regTA_CGTT_CTRL 0 0x509d 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_TCI_CLK_CTRL 0 0x509f 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_GDS_CLK_CTRL 0 0x50a0 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_TCP_TCR_CLK_CTRL 0 0x50a1 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_TCI_TCR_CLK_CTRL 0 0x50a2 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regTCX_CGTT_SCLK_CTRL 0 0x50a3 6 0 1 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 regDB_CGTT_CLK_CTRL_0 0 0x50a4 19 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCB_CGTT_SCLK_CTRL 0 0x50a8 18 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regTCC_CGTT_SCLK_CTRL 0 0x50ac 8 0 1 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regTCC_CGTT_SCLK_CTRL2 0 0x50ad 5 0 1 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 regTCC_CGTT_SCLK_CTRL3 0 0x50ae 19 0 1 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE18 12 12 SOFT_OVERRIDE17 13 13 SOFT_OVERRIDE16 14 14 SOFT_OVERRIDE15 15 15 SOFT_OVERRIDE14 16 16 SOFT_OVERRIDE13 17 17 SOFT_OVERRIDE12 18 18 SOFT_OVERRIDE11 19 19 SOFT_OVERRIDE10 20 20 SOFT_OVERRIDE9 21 21 SOFT_OVERRIDE8 23 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 regTCA_CGTT_SCLK_CTRL 0 0x50af 8 0 1 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regCGTT_CP_CLK_CTRL 0 0x50b0 14 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE_PERFMON 29 29 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regCGTT_CPF_CLK_CTRL 0 0x50b1 14 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE_PERFMON 29 29 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regCGTT_CPC_CLK_CTRL 0 0x50b2 14 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE_PERFMON 29 29 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regCGTT_RLC_CLK_CTRL 0 0x50b5 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regRLC_GFX_RM_CNTL 0 0x50b6 2 0 1 RLC_GFX_RM_VALID 0 0 RESERVED 1 31 regRMI_CGTT_SCLK_CTRL 0 0x50c0 17 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSE_CAC_CGTT_CLK_CTRL 0 0x50d0 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DIDT_REG 29 29 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regGC_CAC_CGTT_CLK_CTRL 0 0x50d8 4 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 regGRBM_CGTT_CLK_CNTL 0 0x50e0 11 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE7 16 16 SOFT_STALL_OVERRIDE6 17 17 SOFT_STALL_OVERRIDE5 18 18 SOFT_STALL_OVERRIDE4 19 19 SOFT_STALL_OVERRIDE3 20 20 SOFT_STALL_OVERRIDE2 21 21 SOFT_STALL_OVERRIDE1 22 22 SOFT_STALL_OVERRIDE0 23 23 SOFT_OVERRIDE_DYN 30 30 regDB_DEBUG 0 0x60c 24 0 0 DEBUG_STENCIL_COMPRESS_DISABLE 0 0 DEBUG_DEPTH_COMPRESS_DISABLE 1 1 FETCH_FULL_Z_TILE 2 2 FETCH_FULL_STENCIL_TILE 3 3 FORCE_Z_MODE 4 5 DEBUG_FORCE_DEPTH_READ 6 6 DEBUG_FORCE_STENCIL_READ 7 7 DEBUG_FORCE_HIZ_ENABLE 8 9 DEBUG_FORCE_HIS_ENABLE0 10 11 DEBUG_FORCE_HIS_ENABLE1 12 13 DEBUG_FAST_Z_DISABLE 14 14 DEBUG_FAST_STENCIL_DISABLE 15 15 DEBUG_NOOP_CULL_DISABLE 16 16 DISABLE_SUMM_SQUADS 17 17 DEPTH_CACHE_FORCE_MISS 18 18 DEBUG_FORCE_FULL_Z_RANGE 19 20 NEVER_FREE_Z_ONLY 21 21 ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS 22 22 DISABLE_VPORT_ZPLANE_OPTIMIZATION 23 23 DECOMPRESS_AFTER_N_ZPLANES 24 27 ONE_FREE_IN_FLIGHT 28 28 FORCE_MISS_IF_NOT_INFLIGHT 29 29 DISABLE_DEPTH_SURFACE_SYNC 30 30 DISABLE_HTILE_SURFACE_SYNC 31 31 regDB_DEBUG2 0 0x60d 22 0 0 ALLOW_COMPZ_BYTE_MASKING 0 0 DISABLE_TC_ZRANGE_L0_CACHE 1 1 DISABLE_TC_MASK_L0_CACHE 2 2 DTR_ROUND_ROBIN_ARB 3 3 DTR_PREZ_STALLS_FOR_ETF_ROOM 4 4 DISABLE_PREZL_FIFO_STALL 5 5 DISABLE_PREZL_FIFO_STALL_REZ 6 6 ENABLE_VIEWPORT_STALL_ON_ALL 7 7 OPTIMIZE_HIZ_MATCHES_FB_DISABLE 8 8 CLK_OFF_DELAY 9 13 DISABLE_TILE_COVERED_FOR_PS_ITER 14 14 ENABLE_SUBTILE_GROUPING 15 15 RESERVED 16 16 DISABLE_NULL_EOT_FORWARDING 17 17 DISABLE_DTT_DATA_FORWARDING 18 18 DISABLE_QUAD_COHERENCY_STALL 19 19 DISABLE_VR_OBJ_PRIM_ID 26 26 DISABLE_VR_PS_INVOKE 27 27 ENABLE_PREZ_OF_REZ_SUMM 28 28 DISABLE_PREZL_VIEWPORT_STALL 29 29 DISABLE_SINGLE_STENCIL_QUAD_SUMM 30 30 DISABLE_WRITE_STALL_ON_RDWR_CONFLICT 31 31 regDB_DEBUG3 0 0x60e 32 0 0 DISABLE_CLEAR_ZRANGE_CORRECTION 0 0 ROUND_ZRANGE_CORRECTION 1 1 FORCE_DB_IS_GOOD 2 2 DISABLE_TL_SSO_NULL_SUPPRESSION 3 3 DISABLE_HIZ_ON_VPORT_CLAMP 4 4 EQAA_INTERPOLATE_COMP_Z 5 5 EQAA_INTERPOLATE_SRC_Z 6 6 DISABLE_TCP_CAM_BYPASS 7 7 DISABLE_ZCMP_DIRTY_SUPPRESSION 8 8 DISABLE_REDUNDANT_PLANE_FLUSHES_OPT 9 9 DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP 10 10 ENABLE_INCOHERENT_EQAA_READS 11 11 DISABLE_OP_Z_DATA_FORWARDING 12 12 DISABLE_OP_DF_BYPASS 13 13 DISABLE_OP_DF_WRITE_COMBINE 14 14 DISABLE_OP_DF_DIRECT_FEEDBACK 15 15 ALLOW_RF2P_RW_COLLISION 16 16 SLOW_PREZ_TO_A2M_OMASK_RATE 17 17 DISABLE_OP_S_DATA_FORWARDING 18 18 DISABLE_TC_UPDATE_WRITE_COMBINE 19 19 DISABLE_HZ_TC_WRITE_COMBINE 20 20 ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT 21 21 ENABLE_TC_MA_ROUND_ROBIN_ARB 22 22 DISABLE_RAM_READ_SUPPRESION_ON_FWD 23 23 DISABLE_EQAA_A2M_PERF_OPT 24 24 DISABLE_DI_DT_STALL 25 25 ENABLE_DB_PROCESS_RESET 26 26 DISABLE_OVERRASTERIZATION_FIX 27 27 DONT_INSERT_CONTEXT_SUSPEND 28 28 DONT_DELETE_CONTEXT_SUSPEND 29 29 DISABLE_4XAA_2P_DELAYED_WRITE 30 30 DISABLE_4XAA_2P_INTERLEAVED_PMASK 31 31 regDB_DEBUG4 0 0x60f 22 0 0 DISABLE_QC_Z_MASK_SUMMATION 0 0 DISABLE_QC_STENCIL_MASK_SUMMATION 1 1 DISABLE_RESUMM_TO_SINGLE_STENCIL 2 2 DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL 3 3 DISABLE_4XAA_2P_ZD_HOLDOFF 4 4 ENABLE_A2M_DQUAD_OPTIMIZATION 5 5 ENABLE_DBCB_SLOW_FORMAT_COLLAPSE 6 6 ALWAYS_ON_RMI_CLK_EN 7 7 DFSM_CONVERT_PASSTHROUGH_TO_BYPASS 8 8 DISABLE_UNMAPPED_Z_INDICATOR 9 9 DISABLE_UNMAPPED_S_INDICATOR 10 10 DISABLE_UNMAPPED_H_INDICATOR 11 11 DISABLE_SEPARATE_DFSM_CLK 12 12 DISABLE_DTT_FAST_HTILENACK_LOOKUP 13 13 DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION 14 14 DISABLE_TS_WRITE_L0 15 15 DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE 16 16 DISABLE_HIZ_Q1_TS_COLLISION_DETECT 17 17 DISABLE_HIZ_Q2_TS_COLLISION_DETECT 18 18 DB_EXTRA_DEBUG4 19 29 DISABLE_8PPC_OBJPRIMID_WHEN_NO_SHADER_EXPORTS 30 30 FULL_TILE_CACHE_EVICT_ON_HALF_FULL 31 31 regDB_CREDIT_LIMIT 0 0x614 4 0 0 DB_SC_TILE_CREDITS 0 4 DB_SC_QUAD_CREDITS 5 9 DB_CB_LQUAD_CREDITS 10 12 DB_CB_TILE_CREDITS 24 30 regDB_WATERMARKS 0 0x615 7 0 0 DEPTH_FREE 0 4 DEPTH_FLUSH 5 10 FORCE_SUMMARIZE 11 14 DEPTH_PENDING_FREE 15 19 DEPTH_CACHELINE_FREE 20 27 AUTO_FLUSH_HTILE 30 30 AUTO_FLUSH_QUAD 31 31 regDB_SUBTILE_CONTROL 0 0x616 10 0 0 MSAA1_X 0 1 MSAA1_Y 2 3 MSAA2_X 4 5 MSAA2_Y 6 7 MSAA4_X 8 9 MSAA4_Y 10 11 MSAA8_X 12 13 MSAA8_Y 14 15 MSAA16_X 16 17 MSAA16_Y 18 19 regDB_FREE_CACHELINES 0 0x617 5 0 0 FREE_DTILE_DEPTH 0 6 FREE_PLANE_DEPTH 7 13 FREE_Z_DEPTH 14 19 FREE_HTILE_DEPTH 20 23 QUAD_READ_REQS 24 31 regDB_FIFO_DEPTH1 0 0x618 5 0 0 DB_RMI_RDREQ_CREDITS 0 4 DB_RMI_WRREQ_CREDITS 5 9 MCC_DEPTH 10 15 QC_DEPTH 16 20 LTILE_PROBE_FIFO_DEPTH 21 28 regDB_FIFO_DEPTH2 0 0x619 4 0 0 EQUAD_FIFO_DEPTH 0 7 ETILE_OP_FIFO_DEPTH 8 14 LQUAD_FIFO_DEPTH 15 24 LTILE_OP_FIFO_DEPTH 25 31 regDB_EXCEPTION_CONTROL 0 0x61a 3 0 0 EARLY_Z_PANIC_DISABLE 0 0 LATE_Z_PANIC_DISABLE 1 1 RE_Z_PANIC_DISABLE 2 2 regDB_RING_CONTROL 0 0x61b 1 0 0 COUNTER_CONTROL 0 1 regDB_MEM_ARB_WATERMARKS 0 0x61c 4 0 0 CLIENT0_WATERMARK 0 2 CLIENT1_WATERMARK 8 10 CLIENT2_WATERMARK 16 18 CLIENT3_WATERMARK 24 26 regDB_RMI_CACHE_POLICY 0 0x61e 15 0 0 Z_RD 0 0 S_RD 1 1 HTILE_RD 2 2 Z_WR 8 8 S_WR 9 9 HTILE_WR 10 10 ZPCPSD_WR 11 11 CC_RD 16 16 FMASK_RD 17 17 CMASK_RD 18 18 DCC_RD 19 19 CC_WR 24 24 FMASK_WR 25 25 CMASK_WR 26 26 DCC_WR 27 27 regDB_DFSM_CONFIG 0 0x630 5 0 0 BYPASS_DFSM 0 0 DISABLE_PUNCHOUT 1 1 DISABLE_POPS 2 2 FORCE_FLUSH 3 3 MIDDLE_PIPE_MAX_DEPTH 8 14 regDB_DFSM_WATERMARK 0 0x631 2 0 0 DFSM_HIGH_WATERMARK 0 15 POPS_HIGH_WATERMARK 16 31 regDB_DFSM_TILES_IN_FLIGHT 0 0x632 2 0 0 HIGH_WATERMARK 0 15 HARD_LIMIT 16 31 regDB_DFSM_PRIMS_IN_FLIGHT 0 0x633 2 0 0 HIGH_WATERMARK 0 15 HARD_LIMIT 16 31 regDB_DFSM_WATCHDOG 0 0x634 1 0 0 TIMER_TARGET 0 31 regDB_DFSM_FLUSH_ENABLE 0 0x635 3 0 0 PRIMARY_EVENTS 0 9 AUX_FORCE_PASSTHRU 24 27 AUX_EVENTS 28 31 regDB_DFSM_FLUSH_AUX_EVENT 0 0x636 4 0 0 EVENT_A 0 7 EVENT_B 8 15 EVENT_C 16 23 EVENT_D 24 31 regCC_RB_REDUNDANCY 0 0x63c 4 0 0 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 regCC_RB_BACKEND_DISABLE 0 0x63d 1 0 0 BACKEND_DISABLE 16 23 regGB_ADDR_CONFIG 0 0x63e 13 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 regGB_BACKEND_MAP 0 0x63f 1 0 0 BACKEND_MAP 0 31 regGB_GPU_ID 0 0x640 1 0 0 GPU_ID 0 3 regCC_RB_DAISY_CHAIN 0 0x641 8 0 0 RB_0 0 3 RB_1 4 7 RB_2 8 11 RB_3 12 15 RB_4 16 19 RB_5 20 23 RB_6 24 27 RB_7 28 31 regGB_ADDR_CONFIG_READ 0 0x642 13 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 regGB_TILE_MODE0 0 0x644 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE1 0 0x645 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE2 0 0x646 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE3 0 0x647 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE4 0 0x648 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE5 0 0x649 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE6 0 0x64a 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE7 0 0x64b 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE8 0 0x64c 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE9 0 0x64d 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE10 0 0x64e 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE11 0 0x64f 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE12 0 0x650 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE13 0 0x651 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE14 0 0x652 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE15 0 0x653 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE16 0 0x654 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE17 0 0x655 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE18 0 0x656 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE19 0 0x657 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE20 0 0x658 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE21 0 0x659 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE22 0 0x65a 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE23 0 0x65b 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE24 0 0x65c 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE25 0 0x65d 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE26 0 0x65e 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE27 0 0x65f 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE28 0 0x660 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE29 0 0x661 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE30 0 0x662 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_TILE_MODE31 0 0x663 5 0 0 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 regGB_MACROTILE_MODE0 0 0x664 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE1 0 0x665 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE2 0 0x666 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE3 0 0x667 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE4 0 0x668 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE5 0 0x669 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE6 0 0x66a 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE7 0 0x66b 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE8 0 0x66c 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE9 0 0x66d 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE10 0 0x66e 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE11 0 0x66f 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE12 0 0x670 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE13 0 0x671 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE14 0 0x672 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regGB_MACROTILE_MODE15 0 0x673 4 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 regCB_HW_CONTROL 0 0x680 18 0 0 CM_CACHE_EVICT_POINT 0 3 FC_CACHE_EVICT_POINT 6 9 CC_CACHE_EVICT_POINT 12 15 ALLOW_MRT_WITH_DUAL_SOURCE 16 16 DISABLE_INTNORM_LE11BPC_CLAMPING 18 18 FORCE_NEEDS_DST 19 19 FORCE_ALWAYS_TOGGLE 20 20 DISABLE_BLEND_OPT_RESULT_EQ_DEST 21 21 DISABLE_FULL_WRITE_MASK 22 22 DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG 23 23 DISABLE_BLEND_OPT_DONT_RD_DST 24 24 DISABLE_BLEND_OPT_BYPASS 25 25 DISABLE_BLEND_OPT_DISCARD_PIXEL 26 26 DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED 27 27 PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT 28 28 PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT 29 29 DISABLE_CC_IB_SERIALIZER_STATE_OPT 30 30 DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE 31 31 regCB_HW_CONTROL_1 0 0x681 5 0 0 CM_CACHE_NUM_TAGS 0 4 FC_CACHE_NUM_TAGS 5 10 CC_CACHE_NUM_TAGS 11 16 CM_TILE_FIFO_DEPTH 17 25 RMI_CREDITS 26 31 regCB_HW_CONTROL_2 0 0x682 5 0 0 CC_EVEN_ODD_FIFO_DEPTH 0 7 FC_RDLAT_TILE_FIFO_DEPTH 8 14 FC_RDLAT_QUAD_FIFO_DEPTH 15 22 DRR_ASSUMED_FIFO_DEPTH_DIV8 24 27 CHICKEN_BITS 28 31 regCB_HW_CONTROL_3 0 0x683 28 0 0 DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL 0 0 RAM_ADDRESS_CONFLICTS_DISALLOWED 1 1 DISABLE_FAST_CLEAR_FETCH_OPT 2 2 DISABLE_QUAD_MARKER_DROP_STOP 3 3 DISABLE_OVERWRITE_COMBINER_CAM_CLR 4 4 DISABLE_CC_CACHE_OVWR_STATUS_ACCUM 5 5 DISABLE_CC_CACHE_PANIC_GATING 7 7 DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION 8 8 SPLIT_ALL_FAST_MODE_TRANSFERS 9 9 DISABLE_SHADER_BLEND_OPTS 10 10 DISABLE_CMASK_LAST_QUAD_INSERTION 11 11 DISABLE_ROP3_FIXES_OF_BUG_511967 12 12 DISABLE_ROP3_FIXES_OF_BUG_520657 13 13 DISABLE_OC_FIXES_OF_BUG_522542 14 14 FORCE_RMI_LAST_HIGH 15 15 FORCE_RMI_CLKEN_HIGH 16 16 DISABLE_EARLY_WRACKS_CC 17 17 DISABLE_EARLY_WRACKS_FC 18 18 DISABLE_EARLY_WRACKS_DC 19 19 DISABLE_EARLY_WRACKS_CM 20 20 DISABLE_NACK_PROCESSING_CC 21 21 DISABLE_NACK_PROCESSING_FC 22 22 DISABLE_NACK_PROCESSING_DC 23 23 DISABLE_NACK_PROCESSING_CM 24 24 DISABLE_NACK_COLOR_RD_WR_OPT 25 25 DISABLE_BLENDER_CLOCK_GATING 26 26 DISABLE_DUALSRC_WITH_OBJPRIMID_FIX 27 27 COLOR_CACHE_PREFETCH_NUM_CLS 28 29 regCB_HW_MEM_ARBITER_RD 0 0x686 13 0 0 MODE 0 1 IGNORE_URGENT_AGE 2 5 BREAK_GROUP_AGE 6 9 WEIGHT_CC 10 11 WEIGHT_FC 12 13 WEIGHT_CM 14 15 WEIGHT_DC 16 17 WEIGHT_DECAY_REQS 18 19 WEIGHT_DECAY_NOREQS 20 21 WEIGHT_IGNORE_NUM_TIDS 22 22 SCALE_AGE 23 25 SCALE_WEIGHT 26 28 SEND_LASTS_WITHIN_GROUPS 29 29 regCB_HW_MEM_ARBITER_WR 0 0x687 13 0 0 MODE 0 1 IGNORE_URGENT_AGE 2 5 BREAK_GROUP_AGE 6 9 WEIGHT_CC 10 11 WEIGHT_FC 12 13 WEIGHT_CM 14 15 WEIGHT_DC 16 17 WEIGHT_DECAY_REQS 18 19 WEIGHT_DECAY_NOREQS 20 21 WEIGHT_IGNORE_BYTE_MASK 22 22 SCALE_AGE 23 25 SCALE_WEIGHT 26 28 SEND_LASTS_WITHIN_GROUPS 29 29 regCB_DCC_CONFIG 0 0x688 7 0 0 OVERWRITE_COMBINER_DEPTH 0 4 OVERWRITE_COMBINER_DISABLE 5 5 OVERWRITE_COMBINER_CC_POP_DISABLE 6 6 DISABLE_CONSTANT_ENCODE 7 7 READ_RETURN_SKID_FIFO_DEPTH 16 22 DCC_CACHE_EVICT_POINT 24 27 DCC_CACHE_NUM_TAGS 28 31 regGC_USER_RB_REDUNDANCY 0 0x6de 4 0 0 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 regGC_USER_RB_BACKEND_DISABLE 0 0x6df 1 0 0 BACKEND_DISABLE 16 23 regRLC_CNTL 0 0x4c00 5 0 1 RLC_ENABLE_F32 0 0 FORCE_RETRY 1 1 READ_CACHE_DISABLE 2 2 RLC_STEP_F32 3 3 RESERVED 4 31 regRLC_STAT 0 0x4c04 9 0 1 RLC_BUSY 0 0 RLC_SRM_BUSY 1 1 RLC_GPM_BUSY 2 2 RLC_SPM_BUSY 3 3 MC_BUSY 4 4 RLC_THREAD_0_BUSY 5 5 RLC_THREAD_1_BUSY 6 6 RLC_THREAD_2_BUSY 7 7 RESERVED 8 31 regRLC_SAFE_MODE 0 0x4c05 5 0 1 CMD 0 0 MESSAGE 1 4 RESERVED1 5 7 RESPONSE 8 11 RESERVED 12 31 regRLC_MEM_SLP_CNTL 0 0x4c06 7 0 1 RLC_MEM_LS_EN 0 0 RLC_MEM_DS_EN 1 1 RESERVED 2 6 RLC_LS_DS_BUSY_OVERRIDE 7 7 RLC_MEM_LS_ON_DELAY 8 15 RLC_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 regRLC_RLCV_SAFE_MODE 0 0x4c08 5 0 1 CMD 0 0 MESSAGE 1 4 RESERVED1 5 7 RESPONSE 8 11 RESERVED 12 31 regRLC_RLCV_COMMAND 0 0x4c0a 2 0 1 CMD 0 3 RESERVED 4 31 regRLC_REFCLOCK_TIMESTAMP_LSB 0 0x4c0c 1 0 1 TIMESTAMP_LSB 0 31 regRLC_REFCLOCK_TIMESTAMP_MSB 0 0x4c0d 1 0 1 TIMESTAMP_MSB 0 31 regRLC_GPM_TIMER_INT_0 0 0x4c0e 1 0 1 TIMER 0 31 regRLC_GPM_TIMER_INT_1 0 0x4c0f 1 0 1 TIMER 0 31 regRLC_GPM_TIMER_INT_2 0 0x4c10 1 0 1 TIMER 0 31 regRLC_GPM_TIMER_CTRL 0 0x4c11 5 0 1 TIMER_0_EN 0 0 TIMER_1_EN 1 1 TIMER_2_EN 2 2 TIMER_3_EN 3 3 RESERVED 4 31 regRLC_LB_CNTR_MAX 0 0x4c12 1 0 1 LB_CNTR_MAX 0 31 regRLC_GPM_TIMER_STAT 0 0x4c13 9 0 1 TIMER_0_STAT 0 0 TIMER_1_STAT 1 1 TIMER_2_STAT 2 2 TIMER_3_STAT 3 3 TIMER_0_ENABLE_SYNC 8 8 TIMER_1_ENABLE_SYNC 9 9 TIMER_2_ENABLE_SYNC 10 10 TIMER_3_ENABLE_SYNC 11 11 RESERVED 12 31 regRLC_GPM_TIMER_INT_3 0 0x4c15 1 0 1 TIMER 0 31 regRLC_SERDES_WR_NONCU_MASTER_MASK_1 0 0x4c16 11 0 1 SE_MASTER_MASK_1 0 15 GC_MASTER_MASK_1 16 16 GC_GFX_MASTER_MASK_1 17 17 TC0_1_MASTER_MASK 18 18 RESERVED_1 19 19 SPARE4_MASTER_MASK 20 20 SPARE5_MASTER_MASK 21 21 SPARE6_MASTER_MASK 22 22 SPARE7_MASTER_MASK 23 23 EA_1_MASTER_MASK 24 24 RESERVED 25 31 regRLC_SERDES_NONCU_MASTER_BUSY_1 0 0x4c17 11 0 1 SE_MASTER_BUSY_1 0 15 GC_MASTER_BUSY_1 16 16 GC_GFX_MASTER_BUSY_1 17 17 TC0_MASTER_BUSY_1 18 18 RESERVED_1 19 19 SPARE4_MASTER_BUSY 20 20 SPARE5_MASTER_BUSY 21 21 SPARE6_MASTER_BUSY 22 22 SPARE7_MASTER_BUSY 23 23 EA_1_MASTER_BUSY 24 24 RESERVED 25 31 regRLC_INT_STAT 0 0x4c18 3 0 1 LAST_CP_RLC_INT_ID 0 7 CP_RLC_INT_PENDING 8 8 RESERVED 9 31 regRLC_LB_CNTL 0 0x4c19 6 0 1 LOAD_BALANCE_ENABLE 0 0 LB_CNT_CP_BUSY 1 1 LB_CNT_SPIM_ACTIVE 2 2 LB_CNT_REG_INC 3 3 CU_MASK_USED_OFF_HYST 4 11 RESERVED 12 31 regRLC_MGCG_CTRL 0 0x4c1a 8 0 1 MGCG_EN 0 0 SILICON_EN 1 1 SIMULATION_EN 2 2 ON_DELAY 3 6 OFF_HYSTERESIS 7 14 GC_CAC_MGCG_CLK_CNTL 15 15 SE_CAC_MGCG_CLK_CNTL 16 16 SPARE 17 31 regRLC_LB_CNTR_INIT 0 0x4c1b 1 0 1 LB_CNTR_INIT 0 31 regRLC_LOAD_BALANCE_CNTR 0 0x4c1c 1 0 1 RLC_LOAD_BALANCE_CNTR 0 31 regRLC_JUMP_TABLE_RESTORE 0 0x4c1e 1 0 1 ADDR 0 31 regRLC_PG_DELAY_2 0 0x4c1f 3 0 1 SERDES_TIMEOUT_VALUE 0 7 SERDES_CMD_DELAY 8 15 PERCU_TIMEOUT_VALUE 16 31 regRLC_GPU_CLOCK_COUNT_LSB 0 0x4c24 1 0 1 GPU_CLOCKS_LSB 0 31 regRLC_GPU_CLOCK_COUNT_MSB 0 0x4c25 1 0 1 GPU_CLOCKS_MSB 0 31 regRLC_CAPTURE_GPU_CLOCK_COUNT 0 0x4c26 2 0 1 CAPTURE 0 0 RESERVED 1 31 regRLC_UCODE_CNTL 0 0x4c27 1 0 1 RLC_UCODE_FLAGS 0 31 regRLC_GPM_THREAD_RESET 0 0x4c28 5 0 1 THREAD0_RESET 0 0 THREAD1_RESET 1 1 THREAD2_RESET 2 2 THREAD3_RESET 3 3 RESERVED 4 31 regRLC_GPM_CP_DMA_COMPLETE_T0 0 0x4c29 2 0 1 DATA 0 0 RESERVED 1 31 regRLC_GPM_CP_DMA_COMPLETE_T1 0 0x4c2a 2 0 1 DATA 0 0 RESERVED 1 31 regRLC_CLK_COUNT_GFXCLK_LSB 0 0x4c30 1 0 1 COUNTER 0 31 regRLC_CLK_COUNT_GFXCLK_MSB 0 0x4c31 1 0 1 COUNTER 0 31 regRLC_CLK_COUNT_REFCLK_LSB 0 0x4c32 1 0 1 COUNTER 0 31 regRLC_CLK_COUNT_REFCLK_MSB 0 0x4c33 1 0 1 COUNTER 0 31 regRLC_CLK_COUNT_CTRL 0 0x4c34 6 0 1 GFXCLK_RUN 0 0 GFXCLK_RESET 1 1 GFXCLK_SAMPLE 2 2 REFCLK_RUN 3 3 REFCLK_RESET 4 4 REFCLK_SAMPLE 5 5 regRLC_CLK_COUNT_STAT 0 0x4c35 6 0 1 GFXCLK_VALID 0 0 REFCLK_VALID 1 1 REFCLK_RUN_RESYNC 2 2 REFCLK_RESET_RESYNC 3 3 REFCLK_SAMPLE_RESYNC 4 4 RESERVED 5 31 regRLC_GPM_STAT 0 0x4c40 24 0 1 RLC_BUSY 0 0 GFX_POWER_STATUS 1 1 GFX_CLOCK_STATUS 2 2 GFX_LS_STATUS 3 3 GFX_PIPELINE_POWER_STATUS 4 4 CNTX_IDLE_BEING_PROCESSED 5 5 CNTX_BUSY_BEING_PROCESSED 6 6 GFX_IDLE_BEING_PROCESSED 7 7 CMP_BUSY_BEING_PROCESSED 8 8 SAVING_REGISTERS 9 9 RESTORING_REGISTERS 10 10 GFX3D_BLOCKS_CHANGING_POWER_STATE 11 11 CMP_BLOCKS_CHANGING_POWER_STATE 12 12 STATIC_CU_POWERING_UP 13 13 STATIC_CU_POWERING_DOWN 14 14 DYN_CU_POWERING_UP 15 15 DYN_CU_POWERING_DOWN 16 16 ABORTED_PD_SEQUENCE 17 17 CMP_power_status 18 18 RESERVED_1 19 20 MGCG_OVERRIDE_STATUS 21 21 RLC_EXEC_ROM_CODE 22 22 FGCG_OVERRIDE_STATUS 23 23 PG_ERROR_STATUS 24 31 regRLC_GPU_CLOCK_32_RES_SEL 0 0x4c41 2 0 1 RES_SEL 0 5 RESERVED 6 31 regRLC_GPU_CLOCK_32 0 0x4c42 1 0 1 GPU_CLOCK_32 0 31 regRLC_PG_CNTL 0 0x4c43 12 0 1 GFX_POWER_GATING_ENABLE 0 0 GFX_POWER_GATING_SRC 1 1 DYN_PER_CU_PG_ENABLE 2 2 STATIC_PER_CU_PG_ENABLE 3 3 GFX_PIPELINE_PG_ENABLE 4 4 RESERVED 5 13 PG_OVERRIDE 14 14 CP_PG_DISABLE 15 15 CHUB_HANDSHAKE_ENABLE 16 16 RESERVED1 20 20 Ultra_Low_Voltage_Enable 21 21 RESERVED2 22 23 regRLC_GPM_THREAD_PRIORITY 0 0x4c44 4 0 1 THREAD0_PRIORITY 0 7 THREAD1_PRIORITY 8 15 THREAD2_PRIORITY 16 23 THREAD3_PRIORITY 24 31 regRLC_GPM_THREAD_ENABLE 0 0x4c45 5 0 1 THREAD0_ENABLE 0 0 THREAD1_ENABLE 1 1 THREAD2_ENABLE 2 2 THREAD3_ENABLE 3 3 RESERVED 4 31 regRLC_CGTT_MGCG_OVERRIDE 0 0x4c48 13 0 1 RESERVED_0 0 0 RLC_CGTT_SCLK_OVERRIDE 1 1 GFXIP_MGCG_OVERRIDE 2 2 GFXIP_CGCG_OVERRIDE 3 3 GFXIP_CGLS_OVERRIDE 4 4 GRBM_CGTT_SCLK_OVERRIDE 5 5 GFXIP_MGLS_OVERRIDE 6 6 GFXIP_GFX3D_CG_OVERRIDE 7 7 GFXIP_FGCG_OVERRIDE 8 8 GFXIP_REP_FGCG_OVERRIDE 9 9 RESERVED_15_10 10 15 ENABLE_CGTS_LEGACY 16 16 RESERVED_31_17 17 31 regRLC_CGCG_CGLS_CTRL 0 0x4c49 8 0 1 CGCG_EN 0 0 CGLS_EN 1 1 CGLS_REP_COMPANSAT_DELAY 2 7 CGCG_GFX_IDLE_THRESHOLD 8 26 CGCG_CONTROLLER 27 27 CGCG_REG_CTRL 28 28 SLEEP_MODE 29 30 SIM_SILICON_EN 31 31 regRLC_CGCG_RAMP_CTRL 0 0x4c4a 6 0 1 DOWN_DIV_START_UNIT 0 3 DOWN_DIV_STEP_UNIT 4 7 UP_DIV_START_UNIT 8 11 UP_DIV_STEP_UNIT 12 15 STEP_DELAY_CNT 16 27 STEP_DELAY_UNIT 28 31 regRLC_DYN_PG_STATUS 0 0x4c4b 1 0 1 PG_STATUS_CU_MASK 0 31 regRLC_DYN_PG_REQUEST 0 0x4c4c 1 0 1 PG_REQUEST_CU_MASK 0 31 regRLC_PG_DELAY 0 0x4c4d 4 0 1 POWER_UP_DELAY 0 7 POWER_DOWN_DELAY 8 15 CMD_PROPAGATE_DELAY 16 23 MEM_SLEEP_DELAY 24 31 regRLC_CU_STATUS 0 0x4c4e 1 0 1 WORK_PENDING 0 31 regRLC_LB_INIT_CU_MASK 0 0x4c4f 1 0 1 INIT_CU_MASK 0 31 regRLC_LB_ALWAYS_ACTIVE_CU_MASK 0 0x4c50 1 0 1 ALWAYS_ACTIVE_CU_MASK 0 31 regRLC_LB_PARAMS 0 0x4c51 4 0 1 SKIP_L2_CHECK 0 0 FIFO_SAMPLES 1 7 PG_IDLE_SAMPLES 8 15 PG_IDLE_SAMPLE_INTERVAL 16 31 regRLC_THREAD1_DELAY 0 0x4c52 4 0 1 CU_IDEL_DELAY 0 7 LBPW_INNER_LOOP_DELAY 8 15 LBPW_OUTER_LOOP_DELAY 16 23 SPARE 24 31 regRLC_PG_ALWAYS_ON_CU_MASK 0 0x4c53 1 0 1 AON_CU_MASK 0 31 regRLC_MAX_PG_CU 0 0x4c54 2 0 1 MAX_POWERED_UP_CU 0 7 SPARE 8 31 regRLC_AUTO_PG_CTRL 0 0x4c55 5 0 1 AUTO_PG_EN 0 0 AUTO_GRBM_REG_SAVE_ON_IDLE_EN 1 1 AUTO_WAKE_UP_EN 2 2 GRBM_REG_SAVE_GFX_IDLE_THRESHOLD 3 18 PG_AFTER_GRBM_REG_SAVE_THRESHOLD 19 31 regRLC_SERDES_RD_PENDING 0 0x4c58 1 0 1 RD_PENDING 0 0 regRLC_SERDES_RD_MASTER_INDEX 0 0x4c59 8 0 1 CU_ID 0 3 SH_ID 4 5 SE_ID 6 8 SE_NONCU_ID 9 11 SE_NONCU 12 12 NON_SE 13 16 DATA_REG_ID 17 18 SPARE 19 31 regRLC_SERDES_RD_DATA_0 0 0x4c5a 1 0 1 DATA 0 31 regRLC_SERDES_RD_DATA_1 0 0x4c5b 1 0 1 DATA 0 31 regRLC_SERDES_RD_DATA_2 0 0x4c5c 1 0 1 DATA 0 31 regRLC_SERDES_WR_CU_MASTER_MASK 0 0x4c5d 1 0 1 MASTER_MASK 0 31 regRLC_SERDES_WR_NONCU_MASTER_MASK 0 0x4c5e 12 0 1 SE_MASTER_MASK 0 15 GC_MASTER_MASK 16 16 GC_GFX_MASTER_MASK 17 17 TC0_MASTER_MASK 18 18 TC1_MASTER_MASK 19 19 SPARE0_MASTER_MASK 20 20 SPARE1_MASTER_MASK 21 21 SPARE2_MASTER_MASK 22 22 SPARE3_MASTER_MASK 23 23 EA_0_MASTER_MASK 24 24 TC2_MASTER_MASK 25 25 RESERVED 26 31 regRLC_SERDES_WR_CTRL 0 0x4c5f 13 0 1 BPM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE_COMMAND 12 12 READ_COMMAND 13 13 RDDATA_RESET 14 14 SHORT_FORMAT 15 15 BPM_DATA 16 25 SRBM_OVERRIDE 26 26 RSVD_BPM_ADDR 27 27 REG_ADDR 28 31 regRLC_SERDES_WR_DATA 0 0x4c60 1 0 1 DATA 0 31 regRLC_SERDES_CU_MASTER_BUSY 0 0x4c61 1 0 1 BUSY_BUSY 0 31 regRLC_SERDES_NONCU_MASTER_BUSY 0 0x4c62 12 0 1 SE_MASTER_BUSY 0 15 GC_MASTER_BUSY 16 16 GC_GFX_MASTER_BUSY 17 17 TC0_MASTER_BUSY 18 18 TC1_MASTER_BUSY 19 19 SPARE0_MASTER_BUSY 20 20 SPARE1_MASTER_BUSY 21 21 SPARE2_MASTER_BUSY 22 22 SPARE3_MASTER_BUSY 23 23 EA_0_MASTER_BUSY 24 24 TC2_MASTER_BUSY 25 25 RESERVED 26 31 regRLC_GPM_GENERAL_0 0 0x4c63 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_1 0 0x4c64 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_2 0 0x4c65 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_3 0 0x4c66 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_4 0 0x4c67 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_5 0 0x4c68 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_6 0 0x4c69 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_7 0 0x4c6a 1 0 1 DATA 0 31 regRLC_GPM_SCRATCH_ADDR 0 0x4c6c 2 0 1 ADDR 0 8 RESERVED 9 31 regRLC_GPM_SCRATCH_DATA 0 0x4c6d 1 0 1 DATA 0 31 regRLC_STATIC_PG_STATUS 0 0x4c6e 1 0 1 PG_STATUS_CU_MASK 0 31 regRLC_SPM_MC_CNTL 0 0x4c71 7 0 1 RLC_SPM_VMID 0 3 RLC_SPM_POLICY 4 4 RLC_SPM_PERF_CNTR 5 5 RLC_SPM_FED 6 6 RLC_SPM_MTYPE_OVER 7 7 RLC_SPM_MTYPE 8 9 RESERVED 10 31 regRLC_SPM_INT_CNTL 0 0x4c72 2 0 1 RLC_SPM_INT_CNTL 0 0 RESERVED 1 31 regRLC_SPM_INT_STATUS 0 0x4c73 2 0 1 RLC_SPM_INT_STATUS 0 0 RESERVED 1 31 regRLC_GPM_LOG_SIZE 0 0x4c77 1 0 1 SIZE 0 31 regRLC_PG_DELAY_3 0 0x4c78 2 0 1 CGCG_ACTIVE_BEFORE_CGPG 0 7 RESERVED 8 31 regRLC_GPR_REG1 0 0x4c79 1 0 1 DATA 0 31 regRLC_GPR_REG2 0 0x4c7a 1 0 1 DATA 0 31 regRLC_GPM_LOG_CONT 0 0x4c7b 1 0 1 CONT 0 31 regRLC_GPM_INT_DISABLE_TH0 0 0x4c7c 1 0 1 DISABLE 0 31 regRLC_GPM_INT_FORCE_TH0 0 0x4c7e 1 0 1 FORCE 0 31 regRLC_GPM_INT_FORCE_TH1 0 0x4c7f 1 0 1 FORCE 0 31 regRLC_SRM_CNTL 0 0x4c80 3 0 1 SRM_ENABLE 0 0 AUTO_INCR_ADDR 1 1 RESERVED 2 31 regRLC_SRM_ARAM_ADDR 0 0x4c83 2 0 1 ADDR 0 11 RESERVED 12 31 regRLC_SRM_ARAM_DATA 0 0x4c84 1 0 1 DATA 0 31 regRLC_SRM_DRAM_ADDR 0 0x4c85 2 0 1 ADDR 0 11 RESERVED 12 31 regRLC_SRM_DRAM_DATA 0 0x4c86 1 0 1 DATA 0 31 regRLC_SRM_GPM_COMMAND 0 0x4c87 8 0 1 OP 0 0 INDEX_CNTL 1 1 INDEX_CNTL_NUM 2 4 SIZE 5 15 RESERVED_16 16 16 START_OFFSET 17 28 RESERVED_30_29 29 30 DEST_MEMORY 31 31 regRLC_SRM_GPM_COMMAND_STATUS 0 0x4c88 3 0 1 FIFO_EMPTY 0 0 FIFO_FULL 1 1 RESERVED 2 31 regRLC_SRM_RLCV_COMMAND 0 0x4c89 6 0 1 OP 0 0 RESERVED 1 3 SIZE 4 15 START_OFFSET 16 27 RESERVED1 28 30 DEST_MEMORY 31 31 regRLC_SRM_RLCV_COMMAND_STATUS 0 0x4c8a 3 0 1 FIFO_EMPTY 0 0 FIFO_FULL 1 1 RESERVED 2 31 regRLC_SRM_INDEX_CNTL_ADDR_0 0 0x4c8b 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_1 0 0x4c8c 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_2 0 0x4c8d 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_3 0 0x4c8e 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_4 0 0x4c8f 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_5 0 0x4c90 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_6 0 0x4c91 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_ADDR_7 0 0x4c92 2 0 1 ADDRESS 0 15 RESERVED 16 31 regRLC_SRM_INDEX_CNTL_DATA_0 0 0x4c93 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_1 0 0x4c94 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_2 0 0x4c95 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_3 0 0x4c96 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_4 0 0x4c97 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_5 0 0x4c98 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_6 0 0x4c99 1 0 1 DATA 0 31 regRLC_SRM_INDEX_CNTL_DATA_7 0 0x4c9a 1 0 1 DATA 0 31 regRLC_SRM_STAT 0 0x4c9b 3 0 1 SRM_BUSY 0 0 SRM_BUSY_DELAY 1 1 RESERVED 2 31 regRLC_SRM_GPM_ABORT 0 0x4c9c 2 0 1 ABORT 0 0 RESERVED 1 31 regRLC_CSIB_ADDR_LO 0 0x4ca2 1 0 1 ADDRESS 0 31 regRLC_CSIB_ADDR_HI 0 0x4ca3 1 0 1 ADDRESS 0 15 regRLC_CSIB_LENGTH 0 0x4ca4 1 0 1 LENGTH 0 31 regRLC_CP_SCHEDULERS 0 0x4caa 4 0 1 scheduler0 0 7 scheduler1 8 15 scheduler2 16 23 scheduler3 24 31 regRLC_GPM_GENERAL_8 0 0x4cad 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_9 0 0x4cae 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_10 0 0x4caf 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_11 0 0x4cb0 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_12 0 0x4cb1 1 0 1 DATA 0 31 regRLC_GPM_UTCL1_CNTL_0 0 0x4cb2 8 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 RESERVED 30 31 regRLC_GPM_UTCL1_CNTL_1 0 0x4cb3 8 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 RESERVED 30 31 regRLC_GPM_UTCL1_CNTL_2 0 0x4cb4 8 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 RESERVED 30 31 regRLC_SPM_UTCL1_CNTL 0 0x4cb5 8 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 RESERVED 30 31 regRLC_UTCL1_STATUS_2 0 0x4cb6 11 0 1 GPM_TH0_UTCL1_BUSY 0 0 GPM_TH1_UTCL1_BUSY 1 1 GPM_TH2_UTCL1_BUSY 2 2 SPM_UTCL1_BUSY 3 3 PREWALKER_UTCL1_BUSY 4 4 GPM_TH0_UTCL1_StallOnTrans 5 5 GPM_TH1_UTCL1_StallOnTrans 6 6 GPM_TH2_UTCL1_StallOnTrans 7 7 SPM_UTCL1_StallOnTrans 8 8 PREWALKER_UTCL1_StallOnTrans 9 9 RESERVED 10 31 regRLC_LB_THR_CONFIG_2 0 0x4cb8 1 0 1 DATA 0 31 regRLC_LB_THR_CONFIG_3 0 0x4cb9 1 0 1 DATA 0 31 regRLC_LB_THR_CONFIG_4 0 0x4cba 1 0 1 DATA 0 31 regRLC_SPM_UTCL1_ERROR_1 0 0x4cbc 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 regRLC_SPM_UTCL1_ERROR_2 0 0x4cbd 1 0 1 Translated_ReqErrorAddr_LSB 0 31 regRLC_GPM_UTCL1_TH0_ERROR_1 0 0x4cbe 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 regRLC_LB_THR_CONFIG_1 0 0x4cbf 1 0 1 DATA 0 31 regRLC_GPM_UTCL1_TH0_ERROR_2 0 0x4cc0 1 0 1 Translated_ReqErrorAddr_LSB 0 31 regRLC_GPM_UTCL1_TH1_ERROR_1 0 0x4cc1 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 regRLC_GPM_UTCL1_TH1_ERROR_2 0 0x4cc2 1 0 1 Translated_ReqErrorAddr_LSB 0 31 regRLC_GPM_UTCL1_TH2_ERROR_1 0 0x4cc3 3 0 1 Translated_ReqError 0 1 Translated_ReqErrorVmid 2 5 Translated_ReqErrorAddr_MSB 6 9 regRLC_GPM_UTCL1_TH2_ERROR_2 0 0x4cc4 1 0 1 Translated_ReqErrorAddr_LSB 0 31 regRLC_SEMAPHORE_0 0 0x4cc7 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_SEMAPHORE_1 0 0x4cc8 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_CP_EOF_INT 0 0x4cca 2 0 1 INTERRUPT 0 0 RESERVED 1 31 regRLC_CP_EOF_INT_CNT 0 0x4ccb 1 0 1 CNT 0 31 regRLC_SPARE_INT 0 0x4ccc 2 0 1 INTERRUPT 0 0 RESERVED 1 31 regRLC_PREWALKER_UTCL1_CNTL 0 0x4ccd 8 0 1 XNACK_REDO_TIMER_CNT 0 19 DROP_MODE 24 24 BYPASS 25 25 INVALIDATE 26 26 FRAG_LIMIT_MODE 27 27 FORCE_SNOOP 28 28 FORCE_SD_VMID_DIRTY 29 29 RESERVED 30 31 regRLC_PREWALKER_UTCL1_TRIG 0 0x4cce 8 0 1 VALID 0 0 VMID 1 4 PRIME_MODE 5 5 READ_PERM 6 6 WRITE_PERM 7 7 EXEC_PERM 8 8 RESERVED 9 30 READY 31 31 regRLC_PREWALKER_UTCL1_ADDR_LSB 0 0x4ccf 1 0 1 ADDR_LSB 0 31 regRLC_PREWALKER_UTCL1_ADDR_MSB 0 0x4cd0 1 0 1 ADDR_MSB 0 15 regRLC_PREWALKER_UTCL1_SIZE_LSB 0 0x4cd1 1 0 1 SIZE_LSB 0 31 regRLC_PREWALKER_UTCL1_SIZE_MSB 0 0x4cd2 1 0 1 SIZE_MSB 0 1 regRLC_DSM_TRIG 0 0x4cd3 1 0 1 START 0 0 regRLC_UTCL1_STATUS 0 0x4cd4 10 0 1 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 RESERVED 3 7 FAULT_UTCL1ID 8 13 RESERVED_1 14 15 RETRY_UTCL1ID 16 21 RESERVED_2 22 23 PRT_UTCL1ID 24 29 RESERVED_3 30 31 regRLC_R2I_CNTL_0 0 0x4cd5 1 0 1 Data 0 31 regRLC_R2I_CNTL_1 0 0x4cd6 1 0 1 Data 0 31 regRLC_R2I_CNTL_2 0 0x4cd7 1 0 1 Data 0 31 regRLC_R2I_CNTL_3 0 0x4cd8 1 0 1 Data 0 31 regRLC_UTCL2_CNTL 0 0x4cd9 2 0 1 MTYPE_NO_PTE_MODE 0 0 RESERVED 1 31 regRLC_LBPW_CU_STAT 0 0x4cda 2 0 1 MAX_CU 0 15 ON_CU 16 31 regRLC_DS_CNTL 0 0x4cdb 6 0 1 GFX_CLK_DS_RLC_BUSY_MASK 0 0 GFX_CLK_DS_CP_BUSY_MASK 1 1 RESRVED 2 15 SOC_CLK_DS_RLC_BUSY_MASK 16 16 SOC_CLK_DS_CP_BUSY_MASK 17 17 RESRVED_1 18 31 regRLC_GPM_INT_STAT_TH0 0 0x4cdc 1 0 1 STATUS 0 31 regRLC_GPM_GENERAL_13 0 0x4cdd 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_14 0 0x4cde 1 0 1 DATA 0 31 regRLC_GPM_GENERAL_15 0 0x4cdf 1 0 1 DATA 0 31 regRLC_SPARE_INT_1 0 0x4ce0 2 0 1 INTERRUPT 0 0 RESERVED 1 31 regRLC_RLCV_SPARE_INT_1 0 0x4ce1 2 0 1 INTERRUPT 0 0 RESERVED 1 31 regRLC_SEMAPHORE_2 0 0x4ce3 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_SEMAPHORE_3 0 0x4ce4 2 0 1 CLIENT_ID 0 4 RESERVED 5 31 regRLC_GPU_CLOCK_COUNT_LSB_1 0 0x4ce8 1 0 1 GPU_CLOCKS_LSB 0 31 regRLC_GPU_CLOCK_COUNT_MSB_1 0 0x4ce9 1 0 1 GPU_CLOCKS_MSB 0 31 regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0 0x4cea 2 0 1 CAPTURE 0 0 RESERVED 1 31 regRLC_GPU_CLOCK_COUNT_LSB_2 0 0x4ceb 1 0 1 GPU_CLOCKS_LSB 0 31 regRLC_GPU_CLOCK_COUNT_MSB_2 0 0x4cec 1 0 1 GPU_CLOCKS_MSB 0 31 regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0 0x4cef 2 0 1 CAPTURE 0 0 RESERVED 1 31 regRLC_CPG_STAT_INVAL 0 0x4d09 1 0 1 CPG_stat_inval 0 0 regRLC_EDC_CNT 0 0x4d40 16 0 1 RLCG_INSTR_RAM_SEC_COUNT 0 1 RLCG_INSTR_RAM_DED_COUNT 2 3 RLCG_SCRATCH_RAM_SEC_COUNT 4 5 RLCG_SCRATCH_RAM_DED_COUNT 6 7 RLCV_INSTR_RAM_SEC_COUNT 8 9 RLCV_INSTR_RAM_DED_COUNT 10 11 RLCV_SCRATCH_RAM_SEC_COUNT 12 13 RLCV_SCRATCH_RAM_DED_COUNT 14 15 RLC_TCTAG_RAM_SEC_COUNT 16 17 RLC_TCTAG_RAM_DED_COUNT 18 19 RLC_SPM_SCRATCH_RAM_SEC_COUNT 20 21 RLC_SPM_SCRATCH_RAM_DED_COUNT 22 23 RLC_SRM_DATA_RAM_SEC_COUNT 24 25 RLC_SRM_DATA_RAM_DED_COUNT 26 27 RLC_SRM_ADDR_RAM_SEC_COUNT 28 29 RLC_SRM_ADDR_RAM_DED_COUNT 30 31 regRLC_EDC_CNT2 0 0x4d41 16 0 1 RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT 0 1 RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT 2 3 RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT 4 5 RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT 6 7 RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT 8 9 RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT 10 11 RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT 12 13 RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT 14 15 RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT 16 17 RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT 18 19 RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT 20 21 RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT 22 23 RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT 24 25 RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT 26 27 RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT 28 29 RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT 30 31 regRLC_DSM_CNTL 0 0x4d42 16 0 1 RLCG_INSTR_RAM_IRRITATOR_DATA_SEL 0 1 RLCG_INSTR_RAM_IRRITATOR_SINGLE_WRITE 2 2 RLCG_SCRATCH_RAM_IRRITATOR_DATA_SEL 3 4 RLCG_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 5 5 RLCV_INSTR_RAM_IRRITATOR_DATA_SEL 6 7 RLCV_INSTR_RAM_IRRITATOR_SINGLE_WRITE 8 8 RLCV_SCRATCH_RAM_IRRITATOR_DATA_SEL 9 10 RLCV_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 11 11 RLC_TCTAG_RAM_IRRITATOR_DATA_SEL 12 13 RLC_TCTAG_RAM_IRRITATOR_SINGLE_WRITE 14 14 RLC_SPM_SCRATCH_RAM_IRRITATOR_DATA_SEL 15 16 RLC_SPM_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 17 17 RLC_SRM_DATA_RAM_IRRITATOR_DATA_SEL 18 19 RLC_SRM_DATA_RAM_IRRITATOR_SINGLE_WRITE 20 20 RLC_SRM_ADDR_RAM_IRRITATOR_DATA_SEL 21 22 RLC_SRM_ADDR_RAM_IRRITATOR_SINGLE_WRITE 23 23 regRLC_DSM_CNTLA 0 0x4d43 16 0 1 RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_DATA_SEL 0 1 RLC_SPM_SE0_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 2 2 RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_DATA_SEL 3 4 RLC_SPM_SE1_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 5 5 RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_DATA_SEL 6 7 RLC_SPM_SE2_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 8 8 RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_DATA_SEL 9 10 RLC_SPM_SE3_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 11 11 RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_DATA_SEL 12 13 RLC_SPM_SE4_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 14 14 RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_DATA_SEL 15 16 RLC_SPM_SE5_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 17 17 RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_DATA_SEL 18 19 RLC_SPM_SE6_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 20 20 RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_DATA_SEL 21 22 RLC_SPM_SE7_SCRATCH_RAM_IRRITATOR_SINGLE_WRITE 23 23 regRLC_DSM_CNTL2 0 0x4d44 17 0 1 RLCG_INSTR_RAM_ENABLE_ERROR_INJECT 0 1 RLCG_INSTR_RAM_SELECT_INJECT_DELAY 2 2 RLCG_SCRATCH_RAM_ENABLE_ERROR_INJECT 3 4 RLCG_SCRATCH_RAM_SELECT_INJECT_DELAY 5 5 RLCV_INSTR_RAM_ENABLE_ERROR_INJECT 6 7 RLCV_INSTR_RAM_SELECT_INJECT_DELAY 8 8 RLCV_SCRATCH_RAM_ENABLE_ERROR_INJECT 9 10 RLCV_SCRATCH_RAM_SELECT_INJECT_DELAY 11 11 RLC_TCTAG_RAM_ENABLE_ERROR_INJECT 12 13 RLC_TCTAG_RAM_SELECT_INJECT_DELAY 14 14 RLC_SPM_SCRATCH_RAM_ENABLE_ERROR_INJECT 15 16 RLC_SPM_SCRATCH_RAM_SELECT_INJECT_DELAY 17 17 RLC_SRM_DATA_RAM_ENABLE_ERROR_INJECT 18 19 RLC_SRM_DATA_RAM_SELECT_INJECT_DELAY 20 20 RLC_SRM_ADDR_RAM_ENABLE_ERROR_INJECT 21 22 RLC_SRM_ADDR_RAM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regRLC_DSM_CNTL2A 0 0x4d45 16 0 1 RLC_SPM_SE0_SCRATCH_RAM_ENABLE_ERROR_INJECT 0 1 RLC_SPM_SE0_SCRATCH_RAM_SELECT_INJECT_DELAY 2 2 RLC_SPM_SE1_SCRATCH_RAM_ENABLE_ERROR_INJECT 3 4 RLC_SPM_SE1_SCRATCH_RAM_SELECT_INJECT_DELAY 5 5 RLC_SPM_SE2_SCRATCH_RAM_ENABLE_ERROR_INJECT 6 7 RLC_SPM_SE2_SCRATCH_RAM_SELECT_INJECT_DELAY 8 8 RLC_SPM_SE3_SCRATCH_RAM_ENABLE_ERROR_INJECT 9 10 RLC_SPM_SE3_SCRATCH_RAM_SELECT_INJECT_DELAY 11 11 RLC_SPM_SE4_SCRATCH_RAM_ENABLE_ERROR_INJECT 12 13 RLC_SPM_SE4_SCRATCH_RAM_SELECT_INJECT_DELAY 14 14 RLC_SPM_SE5_SCRATCH_RAM_ENABLE_ERROR_INJECT 15 16 RLC_SPM_SE5_SCRATCH_RAM_SELECT_INJECT_DELAY 17 17 RLC_SPM_SE6_SCRATCH_RAM_ENABLE_ERROR_INJECT 18 19 RLC_SPM_SE6_SCRATCH_RAM_SELECT_INJECT_DELAY 20 20 RLC_SPM_SE7_SCRATCH_RAM_ENABLE_ERROR_INJECT 21 22 RLC_SPM_SE7_SCRATCH_RAM_SELECT_INJECT_DELAY 23 23 regRLC_RLCV_SPARE_INT 0 0x4f30 2 0 1 INTERRUPT 0 0 RESERVED 1 31 regRMI_GENERAL_CNTL 0 0x780 12 0 0 BURST_DISABLE 0 0 VMID_BYPASS_ENABLE 1 16 XBAR_MUX_CONFIG 17 18 RB0_HARVEST_EN 19 19 RB1_HARVEST_EN 20 20 LOOPBACK_DIS_BY_REQ_TYPE 21 24 XBAR_MUX_CONFIG_UPDATE 25 25 SKID_FIFO_0_OVERFLOW_ERROR_MASK 26 26 SKID_FIFO_0_UNDERFLOW_ERROR_MASK 27 27 SKID_FIFO_1_OVERFLOW_ERROR_MASK 28 28 SKID_FIFO_1_UNDERFLOW_ERROR_MASK 29 29 SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 30 30 regRMI_GENERAL_CNTL1 0 0x781 8 0 0 EARLY_WRACK_ENABLE_PER_MTYPE 0 3 TCIW0_64B_RD_STALL_MODE 4 5 TCIW1_64B_RD_STALL_MODE 6 7 EARLY_WRACK_DISABLE_FOR_LOOPBACK 8 8 POLICY_OVERRIDE_VALUE 9 9 POLICY_OVERRIDE 10 10 UTCL1_PROBE0_RR_ARB_BURST_HINT_EN 11 11 UTCL1_PROBE1_RR_ARB_BURST_HINT_EN 12 12 regRMI_GENERAL_STATUS 0 0x782 25 0 0 GENERAL_RMI_ERRORS_COMBINED 0 0 SKID_FIFO_0_OVERFLOW_ERROR 1 1 SKID_FIFO_0_UNDERFLOW_ERROR 2 2 SKID_FIFO_1_OVERFLOW_ERROR 3 3 SKID_FIFO_1_UNDERFLOW_ERROR 4 4 RMI_XBAR_BUSY 5 5 RMI_UTCL1_BUSY 6 6 RMI_SCOREBOARD_BUSY 7 7 TCIW0_PRT_FIFO_BUSY 8 8 TCIW_FRMTR0_BUSY 9 9 TCIW_RTN_FRMTR0_BUSY 10 10 WRREQ_CONSUMER_FIFO_0_BUSY 11 11 RDREQ_CONSUMER_FIFO_0_BUSY 12 12 TCIW1_PRT_FIFO_BUSY 13 13 TCIW_FRMTR1_BUSY 14 14 TCIW_RTN_FRMTR1_BUSY 15 15 WRREQ_CONSUMER_FIFO_1_BUSY 16 16 RDREQ_CONSUMER_FIFO_1_BUSY 17 17 UTC_PROBE1_BUSY 18 18 UTC_PROBE0_BUSY 19 19 RMI_XNACK_BUSY 20 20 XNACK_FIFO_NUM_USED 21 28 XNACK_FIFO_EMPTY 29 29 XNACK_FIFO_FULL 30 30 SKID_FIFO_FREESPACE_IS_ZERO_ERROR 31 31 regRMI_SUBBLOCK_STATUS0 0 0x783 7 0 0 UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0 0 6 UTC_EXT_LAT_HID_FIFO_FULL_PROBE0 7 7 UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0 8 8 UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1 9 15 UTC_EXT_LAT_HID_FIFO_FULL_PROBE1 16 16 UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1 17 17 TCIW0_INFLIGHT_CNT 18 27 regRMI_SUBBLOCK_STATUS1 0 0x784 3 0 0 SKID_FIFO_0_FREE_SPACE 0 9 SKID_FIFO_1_FREE_SPACE 10 19 TCIW1_INFLIGHT_CNT 20 29 regRMI_SUBBLOCK_STATUS2 0 0x785 2 0 0 PRT_FIFO_0_NUM_USED 0 8 PRT_FIFO_1_NUM_USED 9 17 regRMI_SUBBLOCK_STATUS3 0 0x786 2 0 0 SKID_FIFO_0_FREE_SPACE_TOTAL 0 9 SKID_FIFO_1_FREE_SPACE_TOTAL 10 19 regRMI_XBAR_CONFIG 0 0x787 8 0 0 XBAR_MUX_CONFIG_OVERRIDE 0 1 XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE 2 5 XBAR_MUX_CONFIG_CB_DB_OVERRIDE 6 6 ARBITER_DIS 7 7 XBAR_EN_IN_REQ 8 11 XBAR_EN_IN_REQ_OVERRIDE 12 12 XBAR_EN_IN_RB0 13 13 XBAR_EN_IN_RB1 14 14 regRMI_PROBE_POP_LOGIC_CNTL 0 0x788 5 0 0 EXT_LAT_FIFO_0_MAX_DEPTH 0 6 XLAT_COMBINE0_DIS 7 7 REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2 8 9 EXT_LAT_FIFO_1_MAX_DEPTH 10 16 XLAT_COMBINE1_DIS 17 17 regRMI_UTC_XNACK_N_MISC_CNTL 0 0x789 4 0 0 MASTER_XNACK_TIMER_INC 0 7 IND_XNACK_TIMER_START_VALUE 8 11 UTCL1_PERM_MODE 12 12 CP_VMID_RESET_REQUEST_DISABLE 13 13 regRMI_DEMUX_CNTL 0 0x78a 10 0 0 DEMUX_ARB0_STALL 0 0 DEMUX_ARB0_BREAK_LOB_ON_IDLEIN 1 1 DEMUX_ARB0_STALL_TIMER_OVERRIDE 4 5 DEMUX_ARB0_STALL_TIMER_START_VALUE 6 13 DEMUX_ARB0_MODE 14 15 DEMUX_ARB1_STALL 16 16 DEMUX_ARB1_BREAK_LOB_ON_IDLEIN 17 17 DEMUX_ARB1_STALL_TIMER_OVERRIDE 20 21 DEMUX_ARB1_STALL_TIMER_START_VALUE 22 29 DEMUX_ARB1_MODE 30 31 regRMI_UTCL1_CNTL1 0 0x78b 17 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 USERVM_DIS 16 16 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regRMI_UTCL1_CNTL2 0 0x78c 15 0 0 UTC_SPARE 0 7 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 UTCL1_ARB_BURST_MODE 16 17 UTCL1_ENABLE_PERF_EVENT_RD_WR 18 18 UTCL1_PERF_EVENT_RD_WR 19 19 UTCL1_ENABLE_PERF_EVENT_VMID 20 20 UTCL1_PERF_EVENT_VMID 21 24 UTCL1_DIS_DUAL_L2_REQ 25 25 UTCL1_FORCE_FRAG_2M_TO_64K 26 26 regRMI_UTC_UNIT_CONFIG 0 0x78d 1 0 0 TMZ_REQ_EN 0 15 regRMI_TCIW_FORMATTER0_CNTL 0 0x78e 9 0 0 WR_COMBINE0_DIS_OVERRIDE 0 0 WR_COMBINE0_TIME_OUT_WINDOW 1 8 TCIW0_MAX_ALLOWED_INFLIGHT_REQ 9 18 SKID_FIFO_0_FREE_SPACE_DELTA 19 26 SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE 27 27 TCIW0_REQ_SAFE_MODE 28 28 RMI_IN0_REORDER_DIS 29 29 WR_COMBINE0_DIS_AT_LAST_OF_BURST 30 30 ALL_FAULT_RET0_DATA 31 31 regRMI_TCIW_FORMATTER1_CNTL 0 0x78f 9 0 0 WR_COMBINE1_DIS_OVERRIDE 0 0 WR_COMBINE1_TIME_OUT_WINDOW 1 8 TCIW1_MAX_ALLOWED_INFLIGHT_REQ 9 18 SKID_FIFO_1_FREE_SPACE_DELTA 19 26 SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE 27 27 TCIW1_REQ_SAFE_MODE 28 28 RMI_IN1_REORDER_DIS 29 29 WR_COMBINE1_DIS_AT_LAST_OF_BURST 30 30 ALL_FAULT_RET1_DATA 31 31 regRMI_SCOREBOARD_CNTL 0 0x790 10 0 0 COMPLETE_RB0_FLUSH 0 0 REQ_IN_RE_EN_AFTER_FLUSH_RB0 1 1 COMPLETE_RB1_FLUSH 2 2 REQ_IN_RE_EN_AFTER_FLUSH_RB1 3 3 TIME_STAMP_FLUSH_RB1 4 4 VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN 5 5 VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE 6 6 TIME_STAMP_FLUSH_RB0 7 7 FORCE_VMID_INVAL_DONE_EN 8 8 FORCE_VMID_INVAL_DONE_TIMER_START_VALUE 9 20 regRMI_SCOREBOARD_STATUS0 0 0x791 7 0 0 CURRENT_SESSION_ID 0 0 CP_VMID_INV_IN_PROG 1 1 CP_VMID_INV_REQ_VMID 2 17 CP_VMID_INV_UTC_DONE 18 18 CP_VMID_INV_DONE 19 19 CP_VMID_INV_FLUSH_TYPE 20 20 FORCE_VMID_INV_DONE 21 21 regRMI_SCOREBOARD_STATUS1 0 0x792 9 0 0 RUNNING_CNT_RB0 0 11 RUNNING_CNT_UNDERFLOW_RB0 12 12 RUNNING_CNT_OVERFLOW_RB0 13 13 MULTI_VMID_INVAL_FROM_CP_DETECTED 14 14 RUNNING_CNT_RB1 15 26 RUNNING_CNT_UNDERFLOW_RB1 27 27 RUNNING_CNT_OVERFLOW_RB1 28 28 COM_FLUSH_IN_PROG_RB1 29 29 COM_FLUSH_IN_PROG_RB0 30 30 regRMI_SCOREBOARD_STATUS2 0 0x793 10 0 0 SNAPSHOT_CNT_RB0 0 11 SNAPSHOT_CNT_UNDERFLOW_RB0 12 12 SNAPSHOT_CNT_RB1 13 24 SNAPSHOT_CNT_UNDERFLOW_RB1 25 25 COM_FLUSH_DONE_RB1 26 26 COM_FLUSH_DONE_RB0 27 27 TIME_STAMP_FLUSH_IN_PROG_RB0 28 28 TIME_STAMP_FLUSH_IN_PROG_RB1 29 29 TIME_STAMP_FLUSH_DONE_RB0 30 30 TIME_STAMP_FLUSH_DONE_RB1 31 31 regRMI_XBAR_ARBITER_CONFIG 0 0x794 12 0 0 XBAR_ARB0_MODE 0 1 XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR 2 2 XBAR_ARB0_STALL 3 3 XBAR_ARB0_BREAK_LOB_ON_IDLEIN 4 4 XBAR_ARB0_STALL_TIMER_OVERRIDE 6 7 XBAR_ARB0_STALL_TIMER_START_VALUE 8 15 XBAR_ARB1_MODE 16 17 XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR 18 18 XBAR_ARB1_STALL 19 19 XBAR_ARB1_BREAK_LOB_ON_IDLEIN 20 20 XBAR_ARB1_STALL_TIMER_OVERRIDE 22 23 XBAR_ARB1_STALL_TIMER_START_VALUE 24 31 regRMI_XBAR_ARBITER_CONFIG_1 0 0x795 4 0 0 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD 0 7 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR 8 15 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD 16 23 XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR 24 31 regRMI_CLOCK_CNTRL 0 0x796 6 0 0 DYN_CLK_RB0_BUSY_MASK 0 4 DYN_CLK_CMN_BUSY_MASK 5 9 DYN_CLK_RB0_WAKEUP_MASK 10 14 DYN_CLK_CMN_WAKEUP_MASK 15 19 DYN_CLK_RB1_BUSY_MASK 20 24 DYN_CLK_RB1_WAKEUP_MASK 25 29 regRMI_UTCL1_STATUS 0 0x797 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 regRMI_SPARE 0 0x79e 10 0 0 RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING 0 0 SPARE_BIT_1 1 1 SPARE_BIT_2 2 2 SPARE_BIT_3 3 3 SPARE_BIT_4 4 4 SPARE_BIT_5 5 5 SPARE_BIT_6 6 6 SPARE_BIT_7 7 7 SPARE_BIT_8_0 8 15 SPARE_BIT_16_0 16 31 regRMI_SPARE_1 0 0x79f 10 0 0 SPARE_BIT_8 0 0 SPARE_BIT_9 1 1 SPARE_BIT_10 2 2 SPARE_BIT_11 3 3 SPARE_BIT_12 4 4 SPARE_BIT_13 5 5 SPARE_BIT_14 6 6 SPARE_BIT_15 7 7 SPARE_BIT_8_1 8 15 SPARE_BIT_16_1 16 31 regRMI_SPARE_2 0 0x7a0 12 0 0 SPARE_BIT_16 0 0 SPARE_BIT_17 1 1 SPARE_BIT_18 2 2 SPARE_BIT_19 3 3 SPARE_BIT_20 4 4 SPARE_BIT_21 5 5 SPARE_BIT_22 6 6 SPARE_BIT_23 7 7 SPARE_BIT_4_0 8 11 SPARE_BIT_4_1 12 15 SPARE_BIT_8_2 16 23 SPARE_BIT_8_3 24 31 regSPI_SHADER_PGM_RSRC3_PS 0 0xc07 4 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 SIMD_DISABLE 26 29 regSPI_SHADER_PGM_LO_PS 0 0xc08 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_PS 0 0xc09 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC1_PS 0 0xc0a 9 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 CU_GROUP_DISABLE 24 24 FP16_OVFL 29 29 regSPI_SHADER_PGM_RSRC2_PS 0 0xc0b 10 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 WAVE_CNT_EN 7 7 EXTRA_LDS_SIZE 8 15 EXCP_EN 16 24 LOAD_COLLISION_WAVEID 25 25 LOAD_INTRAWAVE_COLLISION 26 26 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 regSPI_SHADER_USER_DATA_PS_0 0 0xc0c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_1 0 0xc0d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_2 0 0xc0e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_3 0 0xc0f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_4 0 0xc10 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_5 0 0xc11 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_6 0 0xc12 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_7 0 0xc13 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_8 0 0xc14 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_9 0 0xc15 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_10 0 0xc16 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_11 0 0xc17 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_12 0 0xc18 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_13 0 0xc19 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_14 0 0xc1a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_15 0 0xc1b 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_16 0 0xc1c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_17 0 0xc1d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_18 0 0xc1e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_19 0 0xc1f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_20 0 0xc20 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_21 0 0xc21 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_22 0 0xc22 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_23 0 0xc23 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_24 0 0xc24 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_25 0 0xc25 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_26 0 0xc26 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_27 0 0xc27 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_28 0 0xc28 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_29 0 0xc29 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_30 0 0xc2a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_PS_31 0 0xc2b 1 0 0 DATA 0 31 regSPI_SHADER_PGM_RSRC3_VS 0 0xc46 4 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 SIMD_DISABLE 26 29 regSPI_SHADER_LATE_ALLOC_VS 0 0xc47 1 0 0 LIMIT 0 5 regSPI_SHADER_PGM_LO_VS 0 0xc48 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_VS 0 0xc49 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC1_VS 0 0xc4a 10 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 VGPR_COMP_CNT 24 25 CU_GROUP_ENABLE 26 26 FP16_OVFL 31 31 regSPI_SHADER_PGM_RSRC2_VS 0 0xc4b 14 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 SO_BASE0_EN 8 8 SO_BASE1_EN 9 9 SO_BASE2_EN 10 10 SO_BASE3_EN 11 11 SO_EN 12 12 EXCP_EN 13 21 PC_BASE_EN 22 22 DISPATCH_DRAW_EN 24 24 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 regSPI_SHADER_USER_DATA_VS_0 0 0xc4c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_1 0 0xc4d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_2 0 0xc4e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_3 0 0xc4f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_4 0 0xc50 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_5 0 0xc51 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_6 0 0xc52 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_7 0 0xc53 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_8 0 0xc54 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_9 0 0xc55 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_10 0 0xc56 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_11 0 0xc57 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_12 0 0xc58 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_13 0 0xc59 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_14 0 0xc5a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_15 0 0xc5b 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_16 0 0xc5c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_17 0 0xc5d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_18 0 0xc5e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_19 0 0xc5f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_20 0 0xc60 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_21 0 0xc61 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_22 0 0xc62 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_23 0 0xc63 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_24 0 0xc64 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_25 0 0xc65 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_26 0 0xc66 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_27 0 0xc67 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_28 0 0xc68 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_29 0 0xc69 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_30 0 0xc6a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_VS_31 0 0xc6b 1 0 0 DATA 0 31 regSPI_SHADER_PGM_RSRC2_GS_VS 0 0xc7c 9 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 VGPR_COMP_CNT 16 17 OC_LDS_EN 18 18 LDS_SIZE 19 26 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 regSPI_SHADER_PGM_RSRC4_GS 0 0xc81 2 0 0 GROUP_FIFO_DEPTH 0 6 SPI_SHADER_LATE_ALLOC_GS 7 13 regSPI_SHADER_USER_DATA_ADDR_LO_GS 0 0xc82 1 0 0 MEM_BASE 0 31 regSPI_SHADER_USER_DATA_ADDR_HI_GS 0 0xc83 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_LO_ES 0 0xc84 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_ES 0 0xc85 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC3_GS 0 0xc87 4 0 0 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 SIMD_DISABLE 26 29 regSPI_SHADER_PGM_LO_GS 0 0xc88 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_GS 0 0xc89 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC1_GS 0 0xc8a 10 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 CU_GROUP_ENABLE 24 24 GS_VGPR_COMP_CNT 29 30 FP16_OVFL 31 31 regSPI_SHADER_PGM_RSRC2_GS 0 0xc8b 9 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 ES_VGPR_COMP_CNT 16 17 OC_LDS_EN 18 18 LDS_SIZE 19 26 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 regSPI_SHADER_USER_DATA_ES_0 0 0xccc 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_1 0 0xccd 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_2 0 0xcce 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_3 0 0xccf 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_4 0 0xcd0 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_5 0 0xcd1 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_6 0 0xcd2 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_7 0 0xcd3 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_8 0 0xcd4 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_9 0 0xcd5 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_10 0 0xcd6 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_11 0 0xcd7 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_12 0 0xcd8 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_13 0 0xcd9 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_14 0 0xcda 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_15 0 0xcdb 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_16 0 0xcdc 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_17 0 0xcdd 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_18 0 0xcde 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_19 0 0xcdf 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_20 0 0xce0 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_21 0 0xce1 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_22 0 0xce2 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_23 0 0xce3 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_24 0 0xce4 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_25 0 0xce5 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_26 0 0xce6 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_27 0 0xce7 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_28 0 0xce8 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_29 0 0xce9 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_30 0 0xcea 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_ES_31 0 0xceb 1 0 0 DATA 0 31 regSPI_SHADER_PGM_RSRC4_HS 0 0xd01 1 0 0 GROUP_FIFO_DEPTH 0 6 regSPI_SHADER_USER_DATA_ADDR_LO_HS 0 0xd02 1 0 0 MEM_BASE 0 31 regSPI_SHADER_USER_DATA_ADDR_HI_HS 0 0xd03 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_LO_LS 0 0xd04 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_LS 0 0xd05 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC3_HS 0 0xd07 4 0 0 WAVE_LIMIT 0 5 LOCK_LOW_THRESHOLD 6 9 SIMD_DISABLE 10 13 CU_EN 16 31 regSPI_SHADER_PGM_LO_HS 0 0xd08 1 0 0 MEM_BASE 0 31 regSPI_SHADER_PGM_HI_HS 0 0xd09 1 0 0 MEM_BASE 0 7 regSPI_SHADER_PGM_RSRC1_HS 0 0xd0a 9 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 LS_VGPR_COMP_CNT 28 29 FP16_OVFL 30 30 regSPI_SHADER_PGM_RSRC2_HS 0 0xd0b 7 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 LDS_SIZE 16 24 SKIP_USGPR0 27 27 USER_SGPR_MSB 28 28 regSPI_SHADER_USER_DATA_LS_0 0 0xd0c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_1 0 0xd0d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_2 0 0xd0e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_3 0 0xd0f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_4 0 0xd10 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_5 0 0xd11 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_6 0 0xd12 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_7 0 0xd13 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_8 0 0xd14 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_9 0 0xd15 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_10 0 0xd16 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_11 0 0xd17 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_12 0 0xd18 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_13 0 0xd19 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_14 0 0xd1a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_15 0 0xd1b 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_16 0 0xd1c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_17 0 0xd1d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_18 0 0xd1e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_19 0 0xd1f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_20 0 0xd20 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_21 0 0xd21 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_22 0 0xd22 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_23 0 0xd23 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_24 0 0xd24 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_25 0 0xd25 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_26 0 0xd26 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_27 0 0xd27 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_28 0 0xd28 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_29 0 0xd29 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_30 0 0xd2a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_LS_31 0 0xd2b 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_0 0 0xd4c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_1 0 0xd4d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_2 0 0xd4e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_3 0 0xd4f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_4 0 0xd50 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_5 0 0xd51 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_6 0 0xd52 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_7 0 0xd53 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_8 0 0xd54 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_9 0 0xd55 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_10 0 0xd56 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_11 0 0xd57 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_12 0 0xd58 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_13 0 0xd59 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_14 0 0xd5a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_15 0 0xd5b 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_16 0 0xd5c 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_17 0 0xd5d 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_18 0 0xd5e 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_19 0 0xd5f 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_20 0 0xd60 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_21 0 0xd61 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_22 0 0xd62 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_23 0 0xd63 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_24 0 0xd64 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_25 0 0xd65 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_26 0 0xd66 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_27 0 0xd67 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_28 0 0xd68 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_29 0 0xd69 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_30 0 0xd6a 1 0 0 DATA 0 31 regSPI_SHADER_USER_DATA_COMMON_31 0 0xd6b 1 0 0 DATA 0 31 regCOMPUTE_DISPATCH_INITIATOR 0 0xe00 11 0 0 COMPUTE_SHADER_EN 0 0 PARTIAL_TG_EN 1 1 FORCE_START_AT_000 2 2 ORDERED_APPEND_ENBL 3 3 ORDERED_APPEND_MODE 4 4 USE_THREAD_DIMENSIONS 5 5 ORDER_MODE 6 6 SCALAR_L1_INV_VOL 10 10 VECTOR_L1_INV_VOL 11 11 RESERVED 12 12 RESTORE 14 14 regCOMPUTE_DIM_X 0 0xe01 1 0 0 SIZE 0 31 regCOMPUTE_DIM_Y 0 0xe02 1 0 0 SIZE 0 31 regCOMPUTE_DIM_Z 0 0xe03 1 0 0 SIZE 0 31 regCOMPUTE_START_X 0 0xe04 1 0 0 START 0 31 regCOMPUTE_START_Y 0 0xe05 1 0 0 START 0 31 regCOMPUTE_START_Z 0 0xe06 1 0 0 START 0 31 regCOMPUTE_NUM_THREAD_X 0 0xe07 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 regCOMPUTE_NUM_THREAD_Y 0 0xe08 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 regCOMPUTE_NUM_THREAD_Z 0 0xe09 2 0 0 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 regCOMPUTE_PIPELINESTAT_ENABLE 0 0xe0a 1 0 0 PIPELINESTAT_ENABLE 0 0 regCOMPUTE_PERFCOUNT_ENABLE 0 0xe0b 1 0 0 PERFCOUNT_ENABLE 0 0 regCOMPUTE_PGM_LO 0 0xe0c 1 0 0 DATA 0 31 regCOMPUTE_PGM_HI 0 0xe0d 1 0 0 DATA 0 7 regCOMPUTE_DISPATCH_PKT_ADDR_LO 0 0xe0e 1 0 0 DATA 0 31 regCOMPUTE_DISPATCH_PKT_ADDR_HI 0 0xe0f 1 0 0 DATA 0 7 regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0 0xe10 1 0 0 DATA 0 31 regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0 0xe11 1 0 0 DATA 0 7 regCOMPUTE_PGM_RSRC1 0 0xe12 9 0 0 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 IEEE_MODE 23 23 BULKY 24 24 FP16_OVFL 26 26 regCOMPUTE_PGM_RSRC2 0 0xe13 12 0 0 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 TGID_X_EN 7 7 TGID_Y_EN 8 8 TGID_Z_EN 9 9 TG_SIZE_EN 10 10 TIDIG_COMP_CNT 11 12 EXCP_EN_MSB 13 14 LDS_SIZE 15 23 EXCP_EN 24 30 SKIP_USGPR0 31 31 regCOMPUTE_VMID 0 0xe14 1 0 0 DATA 0 3 regCOMPUTE_RESOURCE_LIMITS 0 0xe15 7 0 0 WAVES_PER_SH 0 9 TG_PER_CU 12 15 LOCK_THRESHOLD 16 21 SIMD_DEST_CNTL 22 22 FORCE_SIMD_DIST 23 23 CU_GROUP_COUNT 24 26 SIMD_DISABLE 27 30 regCOMPUTE_STATIC_THREAD_MGMT_SE0 0 0xe16 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_STATIC_THREAD_MGMT_SE1 0 0xe17 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_TMPRING_SIZE 0 0xe18 2 0 0 WAVES 0 11 WAVESIZE 12 24 regCOMPUTE_STATIC_THREAD_MGMT_SE2 0 0xe19 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_STATIC_THREAD_MGMT_SE3 0 0xe1a 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_RESTART_X 0 0xe1b 1 0 0 RESTART 0 31 regCOMPUTE_RESTART_Y 0 0xe1c 1 0 0 RESTART 0 31 regCOMPUTE_RESTART_Z 0 0xe1d 1 0 0 RESTART 0 31 regCOMPUTE_THREAD_TRACE_ENABLE 0 0xe1e 1 0 0 THREAD_TRACE_ENABLE 0 0 regCOMPUTE_MISC_RESERVED 0 0xe1f 6 0 0 SEND_SEID 0 1 SEND_SEID_CORE1 2 3 RESTORE_CORE_ID 4 4 WAVE_ID_BASE 5 16 CRAWLER_DONE_CORE0 17 17 CRAWLER_DONE_CORE1 18 18 regCOMPUTE_DISPATCH_ID 0 0xe20 1 0 0 DISPATCH_ID 0 31 regCOMPUTE_THREADGROUP_ID 0 0xe21 1 0 0 THREADGROUP_ID 0 31 regCOMPUTE_RELAUNCH 0 0xe22 3 0 0 PAYLOAD 0 29 IS_EVENT 30 30 IS_STATE 31 31 regCOMPUTE_WAVE_RESTORE_ADDR_LO 0 0xe23 1 0 0 ADDR 0 31 regCOMPUTE_WAVE_RESTORE_ADDR_HI 0 0xe24 1 0 0 ADDR 0 15 regCOMPUTE_STATIC_THREAD_MGMT_SE4 0 0xe25 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_STATIC_THREAD_MGMT_SE5 0 0xe26 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_STATIC_THREAD_MGMT_SE6 0 0xe27 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_STATIC_THREAD_MGMT_SE7 0 0xe28 2 0 0 SH0_CU_EN 0 15 SH1_CU_EN 16 31 regCOMPUTE_RESTART_X2 0 0xe29 1 0 0 RESTART 0 31 regCOMPUTE_RESTART_Y2 0 0xe2a 1 0 0 RESTART 0 31 regCOMPUTE_RESTART_Z2 0 0xe2b 1 0 0 RESTART 0 31 regCOMPUTE_SHADER_CHKSUM 0 0xe2c 1 0 0 CHECKSUM 0 31 regCOMPUTE_PGM_RSRC3 0 0xe2d 2 0 0 ACCUM_OFFSET 0 5 TG_SPLIT 16 16 regCOMPUTE_USER_DATA_0 0 0xe40 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_1 0 0xe41 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_2 0 0xe42 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_3 0 0xe43 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_4 0 0xe44 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_5 0 0xe45 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_6 0 0xe46 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_7 0 0xe47 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_8 0 0xe48 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_9 0 0xe49 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_10 0 0xe4a 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_11 0 0xe4b 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_12 0 0xe4c 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_13 0 0xe4d 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_14 0 0xe4e 1 0 0 DATA 0 31 regCOMPUTE_USER_DATA_15 0 0xe4f 1 0 0 DATA 0 31 regCOMPUTE_DISPATCH_END 0 0xe7e 1 0 0 DATA 0 31 regCOMPUTE_NOWHERE 0 0xe7f 1 0 0 DATA 0 31 regSX_DEBUG_1 0 0x419 8 0 0 SX_DB_QUAD_CREDIT 0 6 DISABLE_BLEND_OPT_DONT_RD_DST 8 8 DISABLE_BLEND_OPT_BYPASS 9 9 DISABLE_BLEND_OPT_DISCARD_PIXEL 10 10 DISABLE_QUAD_PAIR_OPT 11 11 DISABLE_PIX_EN_ZERO_OPT 12 12 DISABLE_REP_FGCG 13 13 DEBUG_DATA 14 31 regSPI_PS_MAX_WAVE_ID 0 0x43a 2 0 0 MAX_WAVE_ID 0 11 MAX_COLLISION_WAVE_ID 16 25 regSPI_START_PHASE 0 0x43b 4 0 0 VGPR_START_PHASE 0 1 SGPR_START_PHASE 2 3 WAVE_START_PHASE 4 5 SPI_TD_GAP 6 9 regSPI_GFX_CNTL 0 0x43c 1 0 0 RESET_COUNTS 0 0 regSPI_DSM_CNTL 0 0x443 9 0 0 SPI_SR_MEM_DSM_IRRITATOR_DATA 0 1 SPI_SR_MEM_ENABLE_SINGLE_WRITE 2 2 SPI_GDS_EXPREQ_MEM_DSM_IRRITATOR_DATA 3 4 SPI_GDS_EXPREQ_MEM_ENABLE_SINGLE_WRITE 5 5 SPI_WB_GRANT_30_MEM_DSM_IRRITATOR_DATA 6 7 SPI_WB_GRANT_30_MEM_ENABLE_SINGLE_WRITE 8 8 SPI_LIFE_CNT_MEM_DSM_IRRITATOR_DATA 12 13 SPI_LIFE_CNT_MEM_ENABLE_SINGLE_WRITE 14 14 UNUSED 15 31 regSPI_DSM_CNTL2 0 0x444 10 0 0 SPI_SR_MEM_ENABLE_ERROR_INJECT 0 1 SPI_SR_MEM_SELECT_INJECT_DELAY 2 2 SPI_SR_MEM_INJECT_DELAY 4 9 SPI_GDS_EXPREQ_MEM_ENABLE_ERROR_INJECT 10 11 SPI_GDS_EXPREQ_MEM_SELECT_INJECT_DELAY 12 12 SPI_WB_GRANT_30_MEM_ENABLE_ERROR_INJECT 13 14 SPI_WB_GRANT_30_MEM_SELECT_INJECT_DELAY 15 15 SPI_LIFE_CNT_MEM_ENABLE_ERROR_INJECT 19 20 SPI_LIFE_CNT_MEM_SELECT_INJECT_DELAY 21 21 UNUSED 22 31 regSPI_EDC_CNT 0 0x445 8 0 0 SPI_SR_MEM_SEC_COUNT 0 1 SPI_SR_MEM_DED_COUNT 2 3 SPI_GDS_EXPREQ_SEC_COUNT 4 5 SPI_GDS_EXPREQ_DED_COUNT 6 7 SPI_WB_GRANT_30_SEC_COUNT 8 9 SPI_WB_GRANT_30_DED_COUNT 10 11 SPI_LIFE_CNT_SEC_COUNT 16 17 SPI_LIFE_CNT_DED_COUNT 18 19 regSPI_CONFIG_PS_CU_EN 0 0x452 3 0 0 ENABLE 0 0 PKR0_CU_EN 1 15 PKR1_CU_EN 16 31 regSPI_WF_LIFETIME_CNTL 0 0x4aa 2 0 0 SAMPLE_PERIOD 0 3 EN 4 4 regSPI_WF_LIFETIME_LIMIT_0 0 0x4ab 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_1 0 0x4ac 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_2 0 0x4ad 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_3 0 0x4ae 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_4 0 0x4af 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_5 0 0x4b0 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_6 0 0x4b1 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_7 0 0x4b2 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_8 0 0x4b3 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_LIMIT_9 0 0x4b4 2 0 0 MAX_CNT 0 30 EN_WARN 31 31 regSPI_WF_LIFETIME_STATUS_0 0 0x4b5 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_1 0 0x4b6 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_2 0 0x4b7 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_3 0 0x4b8 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_4 0 0x4b9 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_5 0 0x4ba 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_6 0 0x4bb 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_7 0 0x4bc 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_8 0 0x4bd 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_9 0 0x4be 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_10 0 0x4bf 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_11 0 0x4c0 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_12 0 0x4c1 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_13 0 0x4c2 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_14 0 0x4c3 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_15 0 0x4c4 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_16 0 0x4c5 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_17 0 0x4c6 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_18 0 0x4c7 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_19 0 0x4c8 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_WF_LIFETIME_STATUS_20 0 0x4c9 2 0 0 MAX_CNT 0 30 INT_SENT 31 31 regSPI_LB_CTR_CTRL 0 0x4d4 4 0 0 LOAD 0 0 WAVES_SELECT 1 2 CLEAR_ON_READ 3 3 RESET_COUNTS 4 4 regSPI_LB_CU_MASK 0 0x4d5 1 0 0 CU_MASK 0 15 regSPI_LB_DATA_REG 0 0x4d6 1 0 0 CNT_DATA 0 31 regSPI_PG_ENABLE_STATIC_CU_MASK 0 0x4d7 1 0 0 CU_MASK 0 15 regSPI_GDS_CREDITS 0 0x4d8 3 0 0 DS_DATA_CREDITS 0 7 DS_CMD_CREDITS 8 15 UNUSED 16 31 regSPI_SX_EXPORT_BUFFER_SIZES 0 0x4d9 2 0 0 COLOR_BUFFER_SIZE 0 15 POSITION_BUFFER_SIZE 16 31 regSPI_SX_SCOREBOARD_BUFFER_SIZES 0 0x4da 2 0 0 COLOR_SCOREBOARD_SIZE 0 15 POSITION_SCOREBOARD_SIZE 16 31 regSPI_CSQ_WF_ACTIVE_STATUS 0 0x4db 1 0 0 ACTIVE 0 31 regSPI_CSQ_WF_ACTIVE_COUNT_0 0 0x4dc 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_1 0 0x4dd 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_2 0 0x4de 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_3 0 0x4df 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_4 0 0x4e0 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_5 0 0x4e1 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_6 0 0x4e2 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_CSQ_WF_ACTIVE_COUNT_7 0 0x4e3 2 0 0 COUNT 0 8 EVENTS 16 24 regSPI_LB_DATA_WAVES 0 0x4e4 2 0 0 COUNT0 0 15 COUNT1 16 31 regSPI_LB_DATA_PERCU_WAVE_HSGS 0 0x4e5 2 0 0 CU_USED_HS 0 15 CU_USED_GS 16 31 regSPI_LB_DATA_PERCU_WAVE_VSPS 0 0x4e6 2 0 0 CU_USED_VS 0 15 CU_USED_PS 16 31 regSPI_LB_DATA_PERCU_WAVE_CS 0 0x4e7 1 0 0 ACTIVE 0 15 regSPI_P0_TRAP_SCREEN_PSBA_LO 0 0x4ec 1 0 0 MEM_BASE 0 31 regSPI_P0_TRAP_SCREEN_PSBA_HI 0 0x4ed 1 0 0 MEM_BASE 0 7 regSPI_P0_TRAP_SCREEN_PSMA_LO 0 0x4ee 1 0 0 MEM_BASE 0 31 regSPI_P0_TRAP_SCREEN_PSMA_HI 0 0x4ef 1 0 0 MEM_BASE 0 7 regSPI_P0_TRAP_SCREEN_GPR_MIN 0 0x4f0 2 0 0 VGPR_MIN 0 5 SGPR_MIN 6 9 regSPI_P1_TRAP_SCREEN_PSBA_LO 0 0x4f1 1 0 0 MEM_BASE 0 31 regSPI_P1_TRAP_SCREEN_PSBA_HI 0 0x4f2 1 0 0 MEM_BASE 0 7 regSPI_P1_TRAP_SCREEN_PSMA_LO 0 0x4f3 1 0 0 MEM_BASE 0 31 regSPI_P1_TRAP_SCREEN_PSMA_HI 0 0x4f4 1 0 0 MEM_BASE 0 7 regSPI_P1_TRAP_SCREEN_GPR_MIN 0 0x4f5 2 0 0 VGPR_MIN 0 5 SGPR_MIN 6 9 regSPI_ARB_PRIORITY 0 0x11c0 8 0 0 PIPE_ORDER_TS0 0 2 PIPE_ORDER_TS1 3 5 PIPE_ORDER_TS2 6 8 PIPE_ORDER_TS3 9 11 TS0_DUR_MULT 12 13 TS1_DUR_MULT 14 15 TS2_DUR_MULT 16 17 TS3_DUR_MULT 18 19 regSPI_ARB_CYCLES_0 0 0x11c1 2 0 0 TS0_DURATION 0 15 TS1_DURATION 16 31 regSPI_ARB_CYCLES_1 0 0x11c2 2 0 0 TS2_DURATION 0 15 TS3_DURATION 16 31 regSPI_WCL_PIPE_PERCENT_GFX 0 0x11c7 5 0 0 VALUE 0 6 LS_GRP_VALUE 7 11 HS_GRP_VALUE 12 16 ES_GRP_VALUE 17 21 GS_GRP_VALUE 22 26 regSPI_WCL_PIPE_PERCENT_HP3D 0 0x11c8 3 0 0 VALUE 0 6 HS_GRP_VALUE 12 16 GS_GRP_VALUE 22 26 regSPI_WCL_PIPE_PERCENT_CS0 0 0x11c9 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS1 0 0x11ca 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS2 0 0x11cb 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS3 0 0x11cc 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS4 0 0x11cd 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS5 0 0x11ce 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS6 0 0x11cf 1 0 0 VALUE 0 6 regSPI_WCL_PIPE_PERCENT_CS7 0 0x11d0 1 0 0 VALUE 0 6 regSPI_GDBG_WAVE_CNTL 0 0x11d1 1 0 0 STALL_RA 0 0 regSPI_GDBG_TRAP_CONFIG 0 0x11d2 4 0 0 PIPE0_EN 0 7 PIPE1_EN 8 15 PIPE2_EN 16 23 PIPE3_EN 24 31 regSPI_GDBG_PER_VMID_CNTL 0 0x11d3 5 0 0 STALL_VMID 0 0 LAUNCH_MODE 1 2 TRAP_EN 3 3 EXCP_EN 4 12 EXCP_REPLACE 13 13 regSPI_GDBG_WAVE_CNTL3 0 0x11d5 15 0 0 STALL_PS 0 0 STALL_VS 1 1 STALL_GS 2 2 STALL_HS 3 3 STALL_CSG 4 4 STALL_CS0 5 5 STALL_CS1 6 6 STALL_CS2 7 7 STALL_CS3 8 8 STALL_CS4 9 9 STALL_CS5 10 10 STALL_CS6 11 11 STALL_CS7 12 12 STALL_DURATION 13 27 STALL_MULT 28 28 regSPI_GDBG_TRAP_DATA0 0 0x11d8 1 0 0 DATA 0 31 regSPI_GDBG_TRAP_DATA1 0 0x11d9 1 0 0 DATA 0 31 regSPI_COMPUTE_QUEUE_RESET 0 0x11db 1 0 0 RESET 0 0 regSPI_RESOURCE_RESERVE_CU_0 0 0x11dc 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_1 0 0x11dd 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_2 0 0x11de 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_3 0 0x11df 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_4 0 0x11e0 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_5 0 0x11e1 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_6 0 0x11e2 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_7 0 0x11e3 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_8 0 0x11e4 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_9 0 0x11e5 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_EN_CU_0 0 0x11e6 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_1 0 0x11e7 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_2 0 0x11e8 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_3 0 0x11e9 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_4 0 0x11ea 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_5 0 0x11eb 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_6 0 0x11ec 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_7 0 0x11ed 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_8 0 0x11ee 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_9 0 0x11ef 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_CU_10 0 0x11f0 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_11 0 0x11f1 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_EN_CU_10 0 0x11f2 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_11 0 0x11f3 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_CU_12 0 0x11f4 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_13 0 0x11f5 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_14 0 0x11f6 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_CU_15 0 0x11f7 5 0 0 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 regSPI_RESOURCE_RESERVE_EN_CU_12 0 0x11f8 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_13 0 0x11f9 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_14 0 0x11fa 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_RESOURCE_RESERVE_EN_CU_15 0 0x11fb 4 0 0 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 regSPI_COMPUTE_WF_CTX_SAVE 0 0x11fc 5 0 0 INITIATE 0 0 GDS_INTERRUPT_EN 1 1 DONE_INTERRUPT_EN 2 2 GDS_REQ_BUSY 30 30 SAVE_BUSY 31 31 regSPI_ARB_CNTL_0 0 0x11fd 3 0 0 EXP_ARB_COL_WT 0 3 EXP_ARB_POS_WT 4 7 EXP_ARB_GDS_WT 8 11 regSQ_CONFIG 0 0x300 22 0 0 DISABLE_BARRIER_WAITCNT 0 0 DISABLE_REPEATER_FGCG_CLOCK_GATING 1 1 DISABLE_SPIPRIO_OVER_USERPRIO 2 2 OVERRIDE_SP_MAI_ALU_BUSY 3 3 DISABLE_RAM_CLOCK_GATING 4 4 DISABLE_MAI_CO_EXEC 5 5 OVERRIDE_MAI_ALU_BUSY 6 6 OVERRIDE_ALU_BUSY 7 7 OVERRIDE_LDS_IDX_BUSY 11 11 EARLY_TA_DONE_DISABLE 12 12 DUA_FLAT_LOCK_ENABLE 13 13 DUA_LDS_BYPASS_DISABLE 14 14 DUA_FLAT_LDS_PINGPONG_DISABLE 15 15 DISABLE_VMEM_SOFT_CLAUSE 16 16 DISABLE_SMEM_SOFT_CLAUSE 17 17 ENABLE_HIPRIO_ON_EXP_RDY_VS 18 18 PRIO_VAL_ON_EXP_RDY_VS 19 20 REPLAY_SLEEP_CNT 21 27 DISABLE_SP_VGPR_WRITE_SKIP 28 28 DISABLE_SP_REDUNDANT_THREAD_GATING 29 29 DISABLE_FLAT_SOFT_CLAUSE 30 30 DISABLE_MIMG_SOFT_CLAUSE 31 31 regSQC_CONFIG 0 0x301 15 0 0 INST_CACHE_SIZE 0 1 DATA_CACHE_SIZE 2 3 MISS_FIFO_DEPTH 4 5 HIT_FIFO_DEPTH 6 6 FORCE_ALWAYS_MISS 7 7 FORCE_IN_ORDER 8 8 PER_VMID_INV_DISABLE 11 11 EVICT_LRU 12 13 FORCE_2_BANK 14 14 FORCE_1_BANK 15 15 LS_DISABLE_CLOCKS 16 23 INST_PRF_COUNT 24 28 INST_PRF_FILTER_DIS 29 29 DISABLE_PREFETCH_CROSS_4K_BOUNDARY_CHECK 30 30 MEM_LS_DISABLE 31 31 regLDS_CONFIG 0 0x302 8 0 0 ADDR_OUT_OF_RANGE_REPORTING 0 0 TMZ_VIOLATION_REPORTING 1 1 DISABLE_RAM_CLOCK_GATING 2 2 DISABLE_IDXCLK_MGCG 3 3 DISABLE_MEMCLK_MGCG 4 4 DISABLE_ATTRCLK_MGCG 5 5 DISABLE_ATODFPCLK_MGCG 6 6 DISABLE_PHASE_FGCG 7 7 regSQ_RANDOM_WAVE_PRI 0 0x303 3 0 0 RET 0 6 RUI 7 9 RNG 10 22 regSQ_REG_CREDITS 0 0x304 6 0 0 SRBM_CREDITS 0 5 CMD_CREDITS 8 11 REG_BUSY 28 28 SRBM_OVERFLOW 29 29 IMMED_OVERFLOW 30 30 CMD_OVERFLOW 31 31 regSQ_FIFO_SIZES 0 0x305 4 0 0 INTERRUPT_FIFO_SIZE 0 3 TTRACE_FIFO_SIZE 8 11 EXPORT_BUF_SIZE 16 17 VMEM_DATA_FIFO_SIZE 18 19 regSQ_DSM_CNTL 0 0x306 16 0 0 WAVEFRONT_STALL_0 0 0 WAVEFRONT_STALL_1 1 1 SPI_BACKPRESSURE_0 2 2 SPI_BACKPRESSURE_1 3 3 SEL_DSM_SGPR_IRRITATOR_DATA0 8 8 SEL_DSM_SGPR_IRRITATOR_DATA1 9 9 SGPR_ENABLE_SINGLE_WRITE 10 10 SEL_DSM_LDS_IRRITATOR_DATA0 16 16 SEL_DSM_LDS_IRRITATOR_DATA1 17 17 LDS_ENABLE_SINGLE_WRITE01 18 18 SEL_DSM_LDS_IRRITATOR_DATA2 19 19 SEL_DSM_LDS_IRRITATOR_DATA3 20 20 LDS_ENABLE_SINGLE_WRITE23 21 21 SEL_DSM_SP_IRRITATOR_DATA0 24 24 SEL_DSM_SP_IRRITATOR_DATA1 25 25 SP_ENABLE_SINGLE_WRITE 26 26 regSQ_DSM_CNTL2 0 0x307 11 0 0 SGPR_ENABLE_ERROR_INJECT 0 1 SGPR_SELECT_INJECT_DELAY 2 2 LDS_D_ENABLE_ERROR_INJECT 3 4 LDS_D_SELECT_INJECT_DELAY 5 5 LDS_I_ENABLE_ERROR_INJECT 6 7 LDS_I_SELECT_INJECT_DELAY 8 8 SP_ENABLE_ERROR_INJECT 9 10 SP_SELECT_INJECT_DELAY 11 11 LDS_INJECT_DELAY 14 19 SP_INJECT_DELAY 20 25 SQ_INJECT_DELAY 26 31 regSQ_RUNTIME_CONFIG 0 0x308 1 0 0 ENABLE_TEX_ARB_OLDEST 0 0 regSQ_DEBUG_STS_GLOBAL 0 0x309 4 0 0 BUSY 0 0 INTERRUPT_MSG_BUSY 1 1 WAVE_LEVEL_SH0 4 15 WAVE_LEVEL_SH1 16 27 regSH_MEM_BASES 0 0x30a 2 0 0 PRIVATE_BASE 0 15 SHARED_BASE 16 31 regSQ_TIMEOUT_CONFIG 0 0x30b 2 0 0 PERIOD_SEL 0 5 TIMEOUT_FATAL_DISABLE 6 6 regSQ_TIMEOUT_STATUS 0 0x30c 1 0 0 WAVE_TIMEOUT 0 31 regSH_MEM_CONFIG 0 0x30d 4 0 0 ADDRESS_MODE 0 0 ALIGNMENT_MODE 3 4 RETRY_DISABLE 12 12 PRIVATE_NV 13 13 regSP_MFMA_PORTD_RD_CONFIG 0 0x30e 4 0 0 SET 0 0 TYPE 1 3 LAST_PASS 4 8 PORTD_PATTERN 9 28 regSH_CAC_CONFIG 0 0x30f 11 0 0 SQG_UTCL1_REPEATER_FGCG_DISABLE 0 0 SQC_UTCL1_REPEATER_FGCG_DISABLE 1 1 SPI_SQ_CMD_REPEATER_FGCG_DISABLE 2 2 SQ_MSG_REPEATER_FGCG_DISABLE 3 3 SQC_TC_REPEATER_FGCG_DISABLE 4 4 SQC_SQ_REPEATER_FGCG_DISABLE 5 5 SQG_TC_REPEATER_FGCG_DISABLE 6 6 SQC_DISABLE_RAM_CLOCK_GATING 8 8 SQG_DISABLE_RAM_CLOCK_GATING 9 9 SQC_MGCG_CLOCK_OFF_DELAY_CNT 16 19 SQC_MGCG_DISABLE 20 27 regSQ_DEBUG_STS_GLOBAL2 0 0x310 4 0 0 FIFO_LEVEL_GFX0 0 7 FIFO_LEVEL_GFX1 8 15 FIFO_LEVEL_IMMED 16 23 FIFO_LEVEL_HOST 24 31 regSQ_DEBUG_STS_GLOBAL3 0 0x311 2 0 0 FIFO_LEVEL_HOST_CMD 0 3 FIFO_LEVEL_HOST_REG 4 9 regCC_GC_SHADER_RATE_CONFIG 0 0x312 3 0 0 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 HALF_LDS 4 4 regGC_USER_SHADER_RATE_CONFIG 0 0x313 3 0 0 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 HALF_LDS 4 4 regSQ_INTERRUPT_AUTO_MASK 0 0x314 1 0 0 MASK 0 23 regSQ_INTERRUPT_MSG_CTRL 0 0x315 1 0 0 STALL 0 0 regSQ_DEBUG_PERFCOUNT_TRAP 0 0x316 3 0 0 ENABLE 0 0 COUNTER 1 3 LIMIT 4 27 regSQ_UTCL1_CNTL1 0 0x317 17 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 USERVM_DIS 16 16 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INVALIDATE_VMID 19 22 REG_INVALIDATE_ALL_VMID 23 23 REG_INVALIDATE_TOGGLE 24 24 REG_INVALIDATE_ALL 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regSQ_UTCL1_CNTL2 0 0x318 12 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 RETRY_TIMER 16 22 FORCE_FRAG_2M_TO_64K 26 26 PREFETCH_PAGE 28 31 regSQ_UTCL1_STATUS 0 0x319 5 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 RESERVED 3 15 UNUSED 16 31 regSQ_FED_INTERRUPT_STATUS 0 0x31a 7 0 0 INTERRUPT_STATUS 0 0 INTERRUPT_SIMD_ID 2 3 INTERRUPT_WAVE_ID 4 7 INTERRUPT_CU_ID 8 11 INTERRUPT_VM_ID 12 15 TO_IH_DISABLE 17 17 FED_HALT_DISABLE 18 18 regSQ_CGTS_CONFIG 0 0x31b 6 0 0 DGEMM_EXTRA_BUSY_PASS 0 3 XDL_EXTRA_BUSY_PASS 4 7 VALU_EXTRA_BUSY_PASS 8 11 DLOP_EXTRA_BUSY_PASS 12 15 XDL_EXTRA_GAP_PASS 16 17 DGEMM_EXTRA_GAP_PASS 18 19 regSQ_SHADER_TBA_LO 0 0x31c 1 0 0 ADDR_LO 0 31 regSQ_SHADER_TBA_HI 0 0x31d 1 0 0 ADDR_HI 0 7 regSQ_SHADER_TMA_LO 0 0x31e 1 0 0 ADDR_LO 0 31 regSQ_SHADER_TMA_HI 0 0x31f 1 0 0 ADDR_HI 0 7 regSQC_DSM_CNTL 0 0x320 18 0 0 INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA 0 1 INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE 2 2 DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA 3 4 DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE 5 5 DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA 6 7 DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE 8 8 DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA 9 10 DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE 11 11 DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA 12 13 DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE 14 14 DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA 15 16 DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE 17 17 DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA 18 19 DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE 20 20 DATA_CU3_WRITE_DATA_BUF_DSM_IRRITATOR_DATA 21 22 DATA_CU3_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE 23 23 DATA_CU3_UTCL1_LFIFO_DSM_IRRITATOR_DATA 24 25 DATA_CU3_UTCL1_LFIFO_ENABLE_SINGLE_WRITE 26 26 regSQC_DSM_CNTLA 0 0x321 18 0 0 INST_TAG_RAM_DSM_IRRITATOR_DATA 0 1 INST_TAG_RAM_ENABLE_SINGLE_WRITE 2 2 INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA 3 4 INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE 5 5 INST_MISS_FIFO_DSM_IRRITATOR_DATA 6 7 INST_MISS_FIFO_ENABLE_SINGLE_WRITE 8 8 INST_BANK_RAM_DSM_IRRITATOR_DATA 9 10 INST_BANK_RAM_ENABLE_SINGLE_WRITE 11 11 DATA_TAG_RAM_DSM_IRRITATOR_DATA 12 13 DATA_TAG_RAM_ENABLE_SINGLE_WRITE 14 14 DATA_HIT_FIFO_DSM_IRRITATOR_DATA 15 16 DATA_HIT_FIFO_ENABLE_SINGLE_WRITE 17 17 DATA_MISS_FIFO_DSM_IRRITATOR_DATA 18 19 DATA_MISS_FIFO_ENABLE_SINGLE_WRITE 20 20 DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA 21 22 DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE 23 23 DATA_BANK_RAM_DSM_IRRITATOR_DATA 24 25 DATA_BANK_RAM_ENABLE_SINGLE_WRITE 26 26 regSQC_DSM_CNTLB 0 0x322 18 0 0 INST_TAG_RAM_DSM_IRRITATOR_DATA 0 1 INST_TAG_RAM_ENABLE_SINGLE_WRITE 2 2 INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA 3 4 INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE 5 5 INST_MISS_FIFO_DSM_IRRITATOR_DATA 6 7 INST_MISS_FIFO_ENABLE_SINGLE_WRITE 8 8 INST_BANK_RAM_DSM_IRRITATOR_DATA 9 10 INST_BANK_RAM_ENABLE_SINGLE_WRITE 11 11 DATA_TAG_RAM_DSM_IRRITATOR_DATA 12 13 DATA_TAG_RAM_ENABLE_SINGLE_WRITE 14 14 DATA_HIT_FIFO_DSM_IRRITATOR_DATA 15 16 DATA_HIT_FIFO_ENABLE_SINGLE_WRITE 17 17 DATA_MISS_FIFO_DSM_IRRITATOR_DATA 18 19 DATA_MISS_FIFO_ENABLE_SINGLE_WRITE 20 20 DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA 21 22 DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE 23 23 DATA_BANK_RAM_DSM_IRRITATOR_DATA 24 25 DATA_BANK_RAM_ENABLE_SINGLE_WRITE 26 26 regSQC_DSM_CNTL2 0 0x325 15 0 0 INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT 0 1 INST_UTCL1_LFIFO_SELECT_INJECT_DELAY 2 2 DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT 3 4 DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY 5 5 DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT 6 7 DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY 8 8 DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT 9 10 DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY 11 11 DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT 12 13 DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY 14 14 DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT 15 16 DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY 17 17 DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT 18 19 DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY 20 20 INJECT_DELAY 26 31 regSQC_DSM_CNTL2A 0 0x326 18 0 0 INST_TAG_RAM_ENABLE_ERROR_INJECT 0 1 INST_TAG_RAM_SELECT_INJECT_DELAY 2 2 INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT 3 4 INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY 5 5 INST_MISS_FIFO_ENABLE_ERROR_INJECT 6 7 INST_MISS_FIFO_SELECT_INJECT_DELAY 8 8 INST_BANK_RAM_ENABLE_ERROR_INJECT 9 10 INST_BANK_RAM_SELECT_INJECT_DELAY 11 11 DATA_TAG_RAM_ENABLE_ERROR_INJECT 12 13 DATA_TAG_RAM_SELECT_INJECT_DELAY 14 14 DATA_HIT_FIFO_ENABLE_ERROR_INJECT 15 16 DATA_HIT_FIFO_SELECT_INJECT_DELAY 17 17 DATA_MISS_FIFO_ENABLE_ERROR_INJECT 18 19 DATA_MISS_FIFO_SELECT_INJECT_DELAY 20 20 DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT 21 22 DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY 23 23 DATA_BANK_RAM_ENABLE_ERROR_INJECT 24 25 DATA_BANK_RAM_SELECT_INJECT_DELAY 26 26 regSQC_DSM_CNTL2B 0 0x327 18 0 0 INST_TAG_RAM_ENABLE_ERROR_INJECT 0 1 INST_TAG_RAM_SELECT_INJECT_DELAY 2 2 INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT 3 4 INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY 5 5 INST_MISS_FIFO_ENABLE_ERROR_INJECT 6 7 INST_MISS_FIFO_SELECT_INJECT_DELAY 8 8 INST_BANK_RAM_ENABLE_ERROR_INJECT 9 10 INST_BANK_RAM_SELECT_INJECT_DELAY 11 11 DATA_TAG_RAM_ENABLE_ERROR_INJECT 12 13 DATA_TAG_RAM_SELECT_INJECT_DELAY 14 14 DATA_HIT_FIFO_ENABLE_ERROR_INJECT 15 16 DATA_HIT_FIFO_SELECT_INJECT_DELAY 17 17 DATA_MISS_FIFO_ENABLE_ERROR_INJECT 18 19 DATA_MISS_FIFO_SELECT_INJECT_DELAY 20 20 DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT 21 22 DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY 23 23 DATA_BANK_RAM_ENABLE_ERROR_INJECT 24 25 DATA_BANK_RAM_SELECT_INJECT_DELAY 26 26 regSQC_DSM_CNTL2E 0 0x32a 4 0 0 DATA_CU3_WRITE_DATA_BUF_ENABLE_ERROR_INJECT 0 1 DATA_CU3_WRITE_DATA_BUF_SELECT_INJECT_DELAY 2 2 DATA_CU3_UTCL1_LFIFO_ENABLE_ERROR_INJECT 3 4 DATA_CU3_UTCL1_LFIFO_SELECT_INJECT_DELAY 5 5 regSQC_EDC_FUE_CNTL 0 0x32b 2 0 0 BLOCK_FUE_FLAGS 0 15 FUE_INTERRUPT_ENABLES 16 31 regSQC_EDC_CNT2 0 0x32c 12 0 0 INST_BANKA_TAG_RAM_SEC_COUNT 0 1 INST_BANKA_TAG_RAM_DED_COUNT 2 3 INST_BANKA_BANK_RAM_SEC_COUNT 4 5 INST_BANKA_BANK_RAM_DED_COUNT 6 7 DATA_BANKA_TAG_RAM_SEC_COUNT 8 9 DATA_BANKA_TAG_RAM_DED_COUNT 10 11 DATA_BANKA_BANK_RAM_SEC_COUNT 12 13 DATA_BANKA_BANK_RAM_DED_COUNT 14 15 INST_UTCL1_LFIFO_SEC_COUNT 16 17 INST_UTCL1_LFIFO_DED_COUNT 18 19 DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT 20 21 DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT 22 23 regSQC_EDC_CNT3 0 0x32d 10 0 0 INST_BANKB_TAG_RAM_SEC_COUNT 0 1 INST_BANKB_TAG_RAM_DED_COUNT 2 3 INST_BANKB_BANK_RAM_SEC_COUNT 4 5 INST_BANKB_BANK_RAM_DED_COUNT 6 7 DATA_BANKB_TAG_RAM_SEC_COUNT 8 9 DATA_BANKB_TAG_RAM_DED_COUNT 10 11 DATA_BANKB_BANK_RAM_SEC_COUNT 12 13 DATA_BANKB_BANK_RAM_DED_COUNT 14 15 DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT 16 17 DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT 18 19 regSQC_EDC_PARITY_CNT3 0 0x32e 16 0 0 INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT 0 1 INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT 2 3 INST_BANKA_MISS_FIFO_SEC_COUNT 4 5 INST_BANKA_MISS_FIFO_DED_COUNT 6 7 DATA_BANKA_HIT_FIFO_SEC_COUNT 8 9 DATA_BANKA_HIT_FIFO_DED_COUNT 10 11 DATA_BANKA_MISS_FIFO_SEC_COUNT 12 13 DATA_BANKA_MISS_FIFO_DED_COUNT 14 15 INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT 16 17 INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT 18 19 INST_BANKB_MISS_FIFO_SEC_COUNT 20 21 INST_BANKB_MISS_FIFO_DED_COUNT 22 23 DATA_BANKB_HIT_FIFO_SEC_COUNT 24 25 DATA_BANKB_HIT_FIFO_DED_COUNT 26 27 DATA_BANKB_MISS_FIFO_SEC_COUNT 28 29 DATA_BANKB_MISS_FIFO_DED_COUNT 30 31 regSQ_DEBUG 0 0x332 1 0 0 SINGLE_MEMOP 0 0 regSQ_REG_TIMESTAMP 0 0x374 1 0 0 TIMESTAMP 0 7 regSQ_CMD_TIMESTAMP 0 0x375 1 0 0 TIMESTAMP 0 7 regSQ_HOSTTRAP_STATUS 0 0x376 2 0 0 HTPENDINGCOUNT 0 7 HTPENDING_OVERRIDE 8 8 regSQ_IND_INDEX 0 0x378 8 0 0 WAVE_ID 0 3 SIMD_ID 4 5 THREAD_ID 6 11 AUTO_INCR 12 12 FORCE_READ 13 13 READ_TIMEOUT 14 14 UNINDEXED 15 15 INDEX 16 31 regSQ_IND_DATA 0 0x379 1 0 0 DATA 0 31 regSQ_CONFIG1 0 0x37a 19 0 0 DISABLE_XDL_PORTD_CO_EXEC 0 0 DISABLE_MGCG_ON_IBUF 1 1 DISABLE_MGCG_ON_PERF 2 2 DISABLE_MGCG_ON_EXP 3 3 DISABLE_MGCG_ON_SCA 4 4 DISABLE_MGCG_ON_SREG 5 5 DISABLE_MGCG_ON_VDEC 6 6 DISABLE_XNACK_CHECK_IN_RETRY_DISABLE 12 12 DISABLE_BARRIER_ADDR_WATCH 13 13 DISABLE_BARRIER_MEMVIOL_WAIT 14 14 DISABLE_BARRIER_MEMVIOL_BACKOFF 15 15 SP_FGCG_REP_OVERRIDE 24 24 DPMACC_MGCG_OVERRIDE 25 25 XDLMACC_MGCG_OVERRIDE 26 26 TRANSMACC_MGCG_OVERRIDE 27 27 SPMACC_MGCG_OVERRIDE 28 28 DPMACC_DGEMM2X_MGCG_OVERRIDE 29 29 DISABLE_SP_VGPR_READ_SKIP 30 30 SP_SRC_1ST_BUFFER_MGCG_OVERRIDE 31 31 regSQ_CMD 0 0x37b 8 0 0 CMD 0 2 MODE 4 6 CHECK_VMID 7 7 DATA 8 11 WAVE_ID 16 19 SIMD_ID 20 21 QUEUE_ID 24 26 VM_ID 28 31 regSQ_TIME_HI 0 0x37c 1 0 0 TIME 0 31 regSQ_TIME_LO 0 0x37d 1 0 0 TIME 0 31 regSQ_DS_0 0 0x37f 6 0 0 OFFSET0 0 7 OFFSET1 8 15 GDS 16 16 OP 17 24 ACC 25 25 ENCODING 26 31 regSQ_DS_1 0 0x37f 4 0 0 ADDR 0 7 DATA0 8 15 DATA1 16 23 VDST 24 31 regSQ_EXP_0 0 0x37f 6 0 0 EN 0 3 TGT 4 9 COMPR 10 10 DONE 11 11 VM 12 12 ENCODING 26 31 regSQ_EXP_1 0 0x37f 4 0 0 VSRC0 0 7 VSRC1 8 15 VSRC2 16 23 VSRC3 24 31 regSQ_FLAT_0 0 0x37f 8 0 0 OFFSET 0 11 LDS 13 13 SEG 14 15 GLC 16 16 SLC 17 17 OP 18 24 SCC 25 25 ENCODING 26 31 regSQ_FLAT_1 0 0x37f 5 0 0 ADDR 0 7 DATA 8 15 SADDR 16 22 ACC 23 23 VDST 24 31 regSQ_GLBL_0 0 0x37f 8 0 0 OFFSET 0 12 LDS 13 13 SEG 14 15 GLC 16 16 SLC 17 17 OP 18 24 SCC 25 25 ENCODING 26 31 regSQ_GLBL_1 0 0x37f 5 0 0 ADDR 0 7 DATA 8 15 SADDR 16 22 ACC 23 23 VDST 24 31 regSQ_INST 0 0x37f 1 0 0 ENCODING 0 31 regSQ_MIMG_0 0 0x37f 12 0 0 OPM 0 0 SCC 7 7 DMASK 8 11 UNORM 12 12 GLC 13 13 DA 14 14 A16 15 15 ACC 16 16 LWE 17 17 OP 18 24 SLC 25 25 ENCODING 26 31 regSQ_MIMG_1 0 0x37f 5 0 0 VADDR 0 7 VDATA 8 15 SRSRC 16 20 SSAMP 21 25 D16 31 31 regSQ_MTBUF_0 0 0x37f 8 0 0 OFFSET 0 11 OFFEN 12 12 IDXEN 13 13 GLC 14 14 OP 15 18 DFMT 19 22 NFMT 23 25 ENCODING 26 31 regSQ_MTBUF_1 0 0x37f 7 0 0 VADDR 0 7 VDATA 8 15 SRSRC 16 20 SCC 21 21 SLC 22 22 ACC 23 23 SOFFSET 24 31 regSQ_MUBUF_0 0 0x37f 9 0 0 OFFSET 0 11 OFFEN 12 12 IDXEN 13 13 GLC 14 14 SCC 15 15 LDS 16 16 SLC 17 17 OP 18 24 ENCODING 26 31 regSQ_MUBUF_1 0 0x37f 5 0 0 VADDR 0 7 VDATA 8 15 SRSRC 16 20 ACC 23 23 SOFFSET 24 31 regSQ_SCRATCH_0 0 0x37f 8 0 0 OFFSET 0 12 LDS 13 13 SEG 14 15 GLC 16 16 SLC 17 17 OP 18 24 SCC 25 25 ENCODING 26 31 regSQ_SCRATCH_1 0 0x37f 5 0 0 ADDR 0 7 DATA 8 15 SADDR 16 22 ACC 23 23 VDST 24 31 regSQ_SMEM_0 0 0x37f 8 0 0 SBASE 0 5 SDATA 6 12 SOFFSET_EN 14 14 NV 15 15 GLC 16 16 IMM 17 17 OP 18 25 ENCODING 26 31 regSQ_SMEM_1 0 0x37f 2 0 0 OFFSET 0 20 SOFFSET 25 31 regSQ_SOP1 0 0x37f 4 0 0 SSRC0 0 7 OP 8 15 SDST 16 22 ENCODING 23 31 regSQ_SOP2 0 0x37f 5 0 0 SSRC0 0 7 SSRC1 8 15 SDST 16 22 OP 23 29 ENCODING 30 31 regSQ_SOPC 0 0x37f 4 0 0 SSRC0 0 7 SSRC1 8 15 OP 16 22 ENCODING 23 31 regSQ_SOPK 0 0x37f 4 0 0 SIMM16 0 15 SDST 16 22 OP 23 27 ENCODING 28 31 regSQ_SOPP 0 0x37f 3 0 0 SIMM16 0 15 OP 16 22 ENCODING 23 31 regSQ_VINTRP 0 0x37f 6 0 0 VSRC 0 7 ATTRCHAN 8 9 ATTR 10 15 OP 16 17 VDST 18 25 ENCODING 26 31 regSQ_VOP1 0 0x37f 4 0 0 SRC0 0 8 OP 9 16 VDST 17 24 ENCODING 25 31 regSQ_VOP2 0 0x37f 5 0 0 SRC0 0 8 VSRC1 9 16 VDST 17 24 OP 25 30 ENCODING 31 31 regSQ_VOP3P_0 0 0x37f 7 0 0 VDST 0 7 NEG_HI 8 10 OP_SEL 11 13 OP_SEL_HI_2 14 14 CLAMP 15 15 OP 16 22 ENCODING 23 31 regSQ_VOP3P_1 0 0x37f 5 0 0 SRC0 0 8 SRC1 9 17 SRC2 18 26 OP_SEL_HI 27 28 NEG 29 31 regSQ_VOP3P_MFMA_0 0 0x37f 6 0 0 VDST 0 7 CBSZ 8 10 ABID 11 14 ACC_CD 15 15 OP 16 22 ENCODING 23 31 regSQ_VOP3P_MFMA_1 0 0x37f 5 0 0 SRC0 0 8 SRC1 9 17 SRC2 18 26 ACC 27 28 BLGP 29 31 regSQ_VOP3_0 0 0x37f 6 0 0 VDST 0 7 ABS 8 10 OP_SEL 11 14 CLAMP 15 15 OP 16 25 ENCODING 26 31 regSQ_VOP3_0_SDST_ENC 0 0x37f 5 0 0 VDST 0 7 SDST 8 14 CLAMP 15 15 OP 16 25 ENCODING 26 31 regSQ_VOP3_1 0 0x37f 5 0 0 SRC0 0 8 SRC1 9 17 SRC2 18 26 OMOD 27 28 NEG 29 31 regSQ_VOPC 0 0x37f 4 0 0 SRC0 0 8 VSRC1 9 16 OP 17 24 ENCODING 25 31 regSQ_VOP_DPP 0 0x37f 9 0 0 SRC0 0 7 DPP_CTRL 8 16 BOUND_CTRL 19 19 SRC0_NEG 20 20 SRC0_ABS 21 21 SRC1_NEG 22 22 SRC1_ABS 23 23 BANK_MASK 24 27 ROW_MASK 28 31 regSQ_VOP_SDWA 0 0x37f 15 0 0 SRC0 0 7 DST_SEL 8 10 DST_UNUSED 11 12 CLAMP 13 13 OMOD 14 15 SRC0_SEL 16 18 SRC0_SEXT 19 19 SRC0_NEG 20 20 SRC0_ABS 21 21 S0 23 23 SRC1_SEL 24 26 SRC1_SEXT 27 27 SRC1_NEG 28 28 SRC1_ABS 29 29 S1 31 31 regSQ_VOP_SDWA_SDST_ENC 0 0x37f 13 0 0 SRC0 0 7 SDST 8 14 SD 15 15 SRC0_SEL 16 18 SRC0_SEXT 19 19 SRC0_NEG 20 20 SRC0_ABS 21 21 S0 23 23 SRC1_SEL 24 26 SRC1_SEXT 27 27 SRC1_NEG 28 28 SRC1_ABS 29 29 S1 31 31 regSQ_LB_CTR_CTRL 0 0x398 3 0 0 START 0 0 LOAD 1 1 CLEAR 2 2 regSQ_LB_DATA0 0 0x399 1 0 0 DATA 0 31 regSQ_LB_DATA1 0 0x39a 1 0 0 DATA 0 31 regSQ_LB_DATA2 0 0x39b 1 0 0 DATA 0 31 regSQ_LB_DATA3 0 0x39c 1 0 0 DATA 0 31 regSQ_LB_CTR_SEL 0 0x39d 4 0 0 SEL0 0 3 SEL1 4 7 SEL2 8 11 SEL3 12 15 regSQ_LB_CTR0_CU 0 0x39e 2 0 0 SH0_MASK 0 15 SH1_MASK 16 31 regSQ_LB_CTR1_CU 0 0x39f 2 0 0 SH0_MASK 0 15 SH1_MASK 16 31 regSQ_LB_CTR2_CU 0 0x3a0 2 0 0 SH0_MASK 0 15 SH1_MASK 16 31 regSQ_LB_CTR3_CU 0 0x3a1 2 0 0 SH0_MASK 0 15 SH1_MASK 16 31 regSQC_EDC_CNT 0 0x3a2 16 0 0 DATA_CU0_WRITE_DATA_BUF_SEC_COUNT 0 1 DATA_CU0_WRITE_DATA_BUF_DED_COUNT 2 3 DATA_CU0_UTCL1_LFIFO_SEC_COUNT 4 5 DATA_CU0_UTCL1_LFIFO_DED_COUNT 6 7 DATA_CU1_WRITE_DATA_BUF_SEC_COUNT 8 9 DATA_CU1_WRITE_DATA_BUF_DED_COUNT 10 11 DATA_CU1_UTCL1_LFIFO_SEC_COUNT 12 13 DATA_CU1_UTCL1_LFIFO_DED_COUNT 14 15 DATA_CU2_WRITE_DATA_BUF_SEC_COUNT 16 17 DATA_CU2_WRITE_DATA_BUF_DED_COUNT 18 19 DATA_CU2_UTCL1_LFIFO_SEC_COUNT 20 21 DATA_CU2_UTCL1_LFIFO_DED_COUNT 22 23 DATA_CU3_WRITE_DATA_BUF_SEC_COUNT 24 25 DATA_CU3_WRITE_DATA_BUF_DED_COUNT 26 27 DATA_CU3_UTCL1_LFIFO_SEC_COUNT 28 29 DATA_CU3_UTCL1_LFIFO_DED_COUNT 30 31 regSQ_EDC_SEC_CNT 0 0x3a3 3 0 0 LDS_SEC 0 7 SGPR_SEC 8 15 VGPR_SEC 16 23 regSQ_EDC_DED_CNT 0 0x3a4 3 0 0 LDS_DED 0 7 SGPR_DED 8 15 VGPR_DED 16 23 regSQ_EDC_INFO 0 0x3a5 4 0 0 WAVE_ID 0 3 SIMD_ID 4 5 SOURCE 6 8 VM_ID 9 12 regSQ_EDC_CNT 0 0x3a6 14 0 0 LDS_D_SEC_COUNT 0 1 LDS_D_DED_COUNT 2 3 LDS_I_SEC_COUNT 4 5 LDS_I_DED_COUNT 6 7 SGPR_SEC_COUNT 8 9 SGPR_DED_COUNT 10 11 VGPR0_SEC_COUNT 12 13 VGPR0_DED_COUNT 14 15 VGPR1_SEC_COUNT 16 17 VGPR1_DED_COUNT 18 19 VGPR2_SEC_COUNT 20 21 VGPR2_DED_COUNT 22 23 VGPR3_SEC_COUNT 24 25 VGPR3_DED_COUNT 26 27 regSQ_EDC_FUE_CNTL 0 0x3a7 2 0 0 BLOCK_FUE_FLAGS 0 15 FUE_INTERRUPT_ENABLES 16 31 regSQ_THREAD_TRACE_WORD_CMN 0 0x3b0 2 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 regSQ_THREAD_TRACE_WORD_EVENT 0 0x3b0 5 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 STAGE 6 8 EVENT_TYPE 10 15 regSQ_THREAD_TRACE_WORD_INST 0 0x3b0 5 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 WAVE_ID 5 8 SIMD_ID 9 10 INST_TYPE 11 15 regSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0 0x3b0 6 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 WAVE_ID 5 8 SIMD_ID 9 10 TRAP_ERROR 15 15 PC_LO 16 31 regSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0 0x3b0 7 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 DATA_LO 16 31 regSQ_THREAD_TRACE_WORD_ISSUE 0 0x3b0 13 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SIMD_ID 5 6 INST0 8 9 INST1 10 11 INST2 12 13 INST3 14 15 INST4 16 17 INST5 18 19 INST6 20 21 INST7 22 23 INST8 24 25 INST9 26 27 regSQ_THREAD_TRACE_WORD_MISC 0 0x3b0 4 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 11 SH_ID 12 12 MISC_TOKEN_TYPE 13 15 regSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0 0x3b0 7 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 CNTR_BANK 10 11 CNTR0 12 24 CNTR1_LO 25 31 regSQ_THREAD_TRACE_WORD_REG_1_OF_2 0 0x3b0 9 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 PIPE_ID 5 6 ME_ID 7 8 REG_DROPPED_PREV 9 9 REG_TYPE 10 12 REG_PRIV 14 14 REG_OP 15 15 REG_ADDR 16 31 regSQ_THREAD_TRACE_WORD_REG_2_OF_2 0 0x3b0 1 0 0 DATA 0 31 regSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0 0x3b0 6 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 PIPE_ID 5 6 ME_ID 7 8 REG_ADDR 9 15 DATA_LO 16 31 regSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0 0x3b0 1 0 0 DATA_HI 0 15 regSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0 0x3b0 2 0 0 TOKEN_TYPE 0 3 TIME_LO 16 31 regSQ_THREAD_TRACE_WORD_WAVE 0 0x3b0 6 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 regSQ_THREAD_TRACE_WORD_WAVE_START 0 0x3b0 10 0 0 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 DISPATCHER 16 20 VS_NO_ALLOC_OR_GROUPED 21 21 COUNT 22 28 TG_ID 29 31 regSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0 0x3b1 1 0 0 PC_HI 0 23 regSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0 0x3b1 1 0 0 DATA_HI 0 15 regSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0 0x3b1 3 0 0 CNTR1_HI 0 5 CNTR2 6 18 CNTR3 19 31 regSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0 0x3b1 1 0 0 TIME_HI 0 31 regSQ_WREXEC_EXEC_HI 0 0x3b1 5 0 0 ADDR_HI 0 15 FIRST_WAVE 26 26 ATC 27 27 MTYPE 28 30 MSB 31 31 regSQ_WREXEC_EXEC_LO 0 0x3b1 1 0 0 ADDR_LO 0 31 regSQ_BUF_RSRC_WORD0 0 0x3c0 1 0 0 BASE_ADDRESS 0 31 regSQ_BUF_RSRC_WORD1 0 0x3c1 4 0 0 BASE_ADDRESS_HI 0 15 STRIDE 16 29 CACHE_SWIZZLE 30 30 SWIZZLE_ENABLE 31 31 regSQ_BUF_RSRC_WORD2 0 0x3c2 1 0 0 NUM_RECORDS 0 31 regSQ_BUF_RSRC_WORD3 0 0x3c3 12 0 0 DST_SEL_X 0 2 DST_SEL_Y 3 5 DST_SEL_Z 6 8 DST_SEL_W 9 11 NUM_FORMAT 12 14 DATA_FORMAT 15 18 USER_VM_ENABLE 19 19 USER_VM_MODE 20 20 INDEX_STRIDE 21 22 ADD_TID_ENABLE 23 23 NV 27 27 TYPE 30 31 regSQ_IMG_RSRC_WORD0 0 0x3c4 1 0 0 BASE_ADDRESS 0 31 regSQ_IMG_RSRC_WORD1 0 0x3c5 6 0 0 BASE_ADDRESS_HI 0 7 MIN_LOD 8 19 DATA_FORMAT 20 25 NUM_FORMAT 26 29 NV 30 30 META_DIRECT 31 31 regSQ_IMG_RSRC_WORD2 0 0x3c6 3 0 0 WIDTH 0 13 HEIGHT 14 27 PERF_MOD 28 30 regSQ_IMG_RSRC_WORD3 0 0x3c7 8 0 0 DST_SEL_X 0 2 DST_SEL_Y 3 5 DST_SEL_Z 6 8 DST_SEL_W 9 11 BASE_LEVEL 12 15 LAST_LEVEL 16 19 SW_MODE 20 24 TYPE 28 31 regSQ_IMG_RSRC_WORD4 0 0x3c8 3 0 0 DEPTH 0 12 PITCH 13 28 BC_SWIZZLE 29 31 regSQ_IMG_RSRC_WORD5 0 0x3c9 7 0 0 BASE_ARRAY 0 12 ARRAY_PITCH 13 16 META_DATA_ADDRESS 17 24 META_LINEAR 25 25 META_PIPE_ALIGNED 26 26 META_RB_ALIGNED 27 27 MAX_MIP 28 31 regSQ_IMG_RSRC_WORD6 0 0x3ca 8 0 0 MIN_LOD_WARN 0 11 COUNTER_BANK_ID 12 19 LOD_HDW_CNT_EN 20 20 COMPRESSION_EN 21 21 ALPHA_IS_ON_MSB 22 22 COLOR_TRANSFORM 23 23 LOST_ALPHA_BITS 24 27 LOST_COLOR_BITS 28 31 regSQ_IMG_RSRC_WORD7 0 0x3cb 1 0 0 META_DATA_ADDRESS 0 31 regSQ_IMG_SAMP_WORD0 0 0x3cc 13 0 0 CLAMP_X 0 2 CLAMP_Y 3 5 CLAMP_Z 6 8 MAX_ANISO_RATIO 9 11 DEPTH_COMPARE_FUNC 12 14 FORCE_UNNORMALIZED 15 15 ANISO_THRESHOLD 16 18 MC_COORD_TRUNC 19 19 FORCE_DEGAMMA 20 20 ANISO_BIAS 21 26 TRUNC_COORD 27 27 DISABLE_CUBE_WRAP 28 28 FILTER_MODE 29 30 regSQ_IMG_SAMP_WORD1 0 0x3cd 4 0 0 MIN_LOD 0 11 MAX_LOD 12 23 PERF_MIP 24 27 PERF_Z 28 31 regSQ_IMG_SAMP_WORD2 0 0x3ce 10 0 0 LOD_BIAS 0 13 LOD_BIAS_SEC 14 19 XY_MAG_FILTER 20 21 XY_MIN_FILTER 22 23 Z_FILTER 24 25 MIP_FILTER 26 27 MIP_POINT_PRECLAMP 28 28 BLEND_ZERO_PRT 29 29 FILTER_PREC_FIX 30 30 ANISO_OVERRIDE 31 31 regSQ_IMG_SAMP_WORD3 0 0x3cf 3 0 0 BORDER_COLOR_PTR 0 11 SKIP_DEGAMMA 12 12 BORDER_COLOR_TYPE 30 31 regSQ_FLAT_SCRATCH_WORD0 0 0x3d0 1 0 0 SIZE 0 18 regSQ_FLAT_SCRATCH_WORD1 0 0x3d1 1 0 0 OFFSET 0 23 regSQ_M0_GPR_IDX_WORD 0 0x3d2 5 0 0 INDEX 0 7 VSRC0_REL 12 12 VSRC1_REL 13 13 VSRC2_REL 14 14 VDST_REL 15 15 regSQC_ICACHE_UTCL1_CNTL1 0 0x3d3 16 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INVALIDATE_VMID 19 22 REG_INVALIDATE_ALL_VMID 23 23 REG_INVALIDATE_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regSQC_ICACHE_UTCL1_CNTL2 0 0x3d4 15 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 ARB_BURST_MODE 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 FORCE_FRAG_2M_TO_64K 26 26 regSQC_DCACHE_UTCL1_CNTL1 0 0x3d5 16 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEF 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 ENABLE_PUSH_LFIFO 17 17 ENABLE_LFIFO_PRI_ARB 18 18 REG_INVALIDATE_VMID 19 22 REG_INVALIDATE_ALL_VMID 23 23 REG_INVALIDATE_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regSQC_DCACHE_UTCL1_CNTL2 0 0x3d6 15 0 0 SPARE 0 7 LFIFO_SCAN_DISABLE 8 8 MTYPE_OVRD_DIS 9 9 LINE_VALID 10 10 DIS_EDC 11 11 GPUVM_INV_MODE 12 12 SHOOTDOWN_OPT 13 13 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 ARB_BURST_MODE 16 17 ENABLE_PERF_EVENT_RD_WR 18 18 PERF_EVENT_RD_WR 19 19 ENABLE_PERF_EVENT_VMID 20 20 PERF_EVENT_VMID 21 24 FORCE_FRAG_2M_TO_64K 26 26 regSQC_ICACHE_UTCL1_STATUS 0 0x3d7 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 regSQC_DCACHE_UTCL1_STATUS 0 0x3d8 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 regTCP_INVALIDATE 0 0xb00 1 0 0 START 0 0 regTCP_STATUS 0 0xb01 9 0 0 TCP_BUSY 0 0 INPUT_BUSY 1 1 ADRS_BUSY 2 2 TAGRAMS_BUSY 3 3 CNTRL_BUSY 4 4 LFIFO_BUSY 5 5 READ_BUSY 6 6 FORMAT_BUSY 7 7 VM_BUSY 8 8 regTCP_CHAN_STEER_0 0 0xb03 6 0 0 CHAN0 0 4 CHAN1 5 9 CHAN2 10 14 CHAN3 15 19 CHAN4 20 24 CHAN5 25 29 regTCP_CHAN_STEER_1 0 0xb04 5 0 0 CHAN6 0 4 CHAN7 5 9 CHAN8 10 14 CHAN9 15 19 CHANA 20 24 regTCP_ADDR_CONFIG 0 0xb05 7 0 0 NUM_TCC_BANKS 0 4 NUM_BANKS 5 6 COLHI_WIDTH 7 9 RB_SPLIT_COLHI 10 10 ENABLE64KHASH 11 11 ENABLE2MHASH 12 12 ENABLE1GHASH 13 13 regTCP_CHAN_STEER_2 0 0xb09 6 0 0 CHANC 0 4 CHAND 5 9 CHANE 10 14 CHANF 15 19 CHAN10 20 24 CHAN11 25 29 regTCP_CHAN_STEER_3 0 0xb0a 6 0 0 CHAN12 0 4 CHAN13 5 9 CHAN14 10 14 CHAN15 15 19 CHAN16 20 24 CHAN17 25 29 regTCP_CHAN_STEER_4 0 0xb0b 6 0 0 CHAN18 0 4 CHAN19 5 9 CHAN1A 10 14 CHAN1B 15 19 CHAN1C 20 24 CHAN1D 25 29 regTCP_CHAN_STEER_5 0 0xb0c 2 0 0 CHAN1E 0 4 CHAN1F 5 9 regTCP_EDC_CNT 0 0xb17 3 0 0 SEC_COUNT 0 7 LFIFO_SED_COUNT 8 15 DED_COUNT 16 23 regTCP_EDC_CNT_NEW 0 0xb18 14 0 0 CACHE_RAM_SEC_COUNT 0 1 CACHE_RAM_DED_COUNT 2 3 LFIFO_RAM_SEC_COUNT 4 5 LFIFO_RAM_DED_COUNT 6 7 CMD_FIFO_SEC_COUNT 8 9 CMD_FIFO_DED_COUNT 10 11 VM_FIFO_SEC_COUNT 12 13 VM_FIFO_DED_COUNT 14 15 DB_RAM_SEC_COUNT 16 17 DB_RAM_DED_COUNT 18 19 UTCL1_LFIFO0_SEC_COUNT 20 21 UTCL1_LFIFO0_DED_COUNT 22 23 UTCL1_LFIFO1_SEC_COUNT 24 25 UTCL1_LFIFO1_DED_COUNT 26 27 regTC_CFG_L1_LOAD_POLICY0 0 0xb1a 16 0 0 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 regTC_CFG_L1_LOAD_POLICY1 0 0xb1b 16 0 0 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 regTC_CFG_L1_STORE_POLICY 0 0xb1c 32 0 0 POLICY_0 0 0 POLICY_1 1 1 POLICY_2 2 2 POLICY_3 3 3 POLICY_4 4 4 POLICY_5 5 5 POLICY_6 6 6 POLICY_7 7 7 POLICY_8 8 8 POLICY_9 9 9 POLICY_10 10 10 POLICY_11 11 11 POLICY_12 12 12 POLICY_13 13 13 POLICY_14 14 14 POLICY_15 15 15 POLICY_16 16 16 POLICY_17 17 17 POLICY_18 18 18 POLICY_19 19 19 POLICY_20 20 20 POLICY_21 21 21 POLICY_22 22 22 POLICY_23 23 23 POLICY_24 24 24 POLICY_25 25 25 POLICY_26 26 26 POLICY_27 27 27 POLICY_28 28 28 POLICY_29 29 29 POLICY_30 30 30 POLICY_31 31 31 regTC_CFG_L2_LOAD_POLICY0 0 0xb1d 16 0 0 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 regTC_CFG_L2_LOAD_POLICY1 0 0xb1e 16 0 0 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 regTC_CFG_L2_STORE_POLICY0 0 0xb1f 16 0 0 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 regTC_CFG_L2_STORE_POLICY1 0 0xb20 16 0 0 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 regTC_CFG_L2_ATOMIC_POLICY 0 0xb21 16 0 0 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 regTC_CFG_L1_VOLATILE 0 0xb22 1 0 0 VOL 0 3 regTC_CFG_L2_VOLATILE 0 0xb23 1 0 0 VOL 0 3 regTCI_MISC 0 0xb5c 2 0 0 FGCG_REPEATER_DISABLE 0 0 LEGACY_MGCG_DISABLE 1 1 regTCI_CNTL_3 0 0xb5d 4 0 0 DISABLE_DOUBLING_L2_BANDWIDTH 0 1 COMBINING_DELAY_WINDOW 2 3 CHICKEN_BIT_TCR_MGCG 4 6 TCR_FGCG_REPEATER_DISABLE 7 7 regTCI_DSM_CNTL 0 0xb5e 2 0 0 WRITE_RAM_IRRITATOR_DATA_SEL 0 1 WRITE_RAM_IRRITATOR_SINGLE_WRITE 2 2 regTCI_DSM_CNTL2 0 0xb5f 3 0 0 WRITE_RAM_ENABLE_ERROR_INJECT 0 1 WRITE_RAM_SELECT_INJECT_DELAY 2 2 TCI_INJECT_DELAY 26 31 regTCI_EDC_CNT 0 0xb60 2 0 0 WRITE_RAM_SEC_COUNT 0 1 WRITE_RAM_DED_COUNT 2 3 regTCI_STATUS 0 0xb61 1 0 0 TCI_BUSY 0 0 regTCI_CNTL_1 0 0xb62 3 0 0 WBINVL1_NUM_CYCLES 0 15 REQ_FIFO_DEPTH 16 23 WDATA_RAM_DEPTH 24 31 regTCI_CNTL_2 0 0xb63 2 0 0 L1_INVAL_ON_WBINVL2 0 0 TCA_MAX_CREDIT 1 8 regTCC_CTRL 0 0xb80 11 0 0 CACHE_SIZE 0 1 RATE 2 3 WRITEBACK_MARGIN 4 7 SRC_FIFO_SIZE 12 15 LATENCY_FIFO_SIZE 16 19 OUTPUT_FIFO_CLK_MODE 22 22 EXECUTE_CLK_MODE 23 24 RETURN_BUFFER_CLK_MODE 25 25 SRC_FIFO_CLK_MODE 26 26 MC_WRITE_CLK_MODE 27 27 LATENCY_FIFO_CLK_MODE 28 28 regTCC_CTRL2 0 0xb81 11 0 0 PROBE_FIFO_SIZE 0 3 INF_NAN_CLAMP 16 16 PROBE_FILTER_CTRL 17 17 WAIT_CLK_STABLE_CNT 18 22 TCC_TCX_REPEATER_FGCG_DISABLE 23 23 TCC_EA0_RDREQ_FGCG_DISABLE 24 24 TCC_EA0_WRREQ_FGCG_DISABLE 25 25 TCC_TCX_ACK_REPEATER_FGCG_DISABLE 26 26 TCC_TCA_HOLE_REPEATER_FGCG_DISABLE 27 27 TCC_TCA_RTN_REPEATER_FGCG_DISABLE 28 28 USE_EA_EARLYWRRET_ON_WRITEBACK 29 29 regTCC_EDC_CNT 0 0xb82 14 0 0 CACHE_DATA_SEC_COUNT 0 1 CACHE_DATA_DED_COUNT 2 3 CACHE_DIRTY_SEC_COUNT 4 5 CACHE_DIRTY_DED_COUNT 6 7 HIGH_RATE_TAG_SEC_COUNT 8 9 HIGH_RATE_TAG_DED_COUNT 10 11 LOW_RATE_TAG_SEC_COUNT 12 13 LOW_RATE_TAG_DED_COUNT 14 15 SRC_FIFO_SEC_COUNT 16 17 SRC_FIFO_DED_COUNT 18 19 LATENCY_FIFO_SEC_COUNT 20 21 LATENCY_FIFO_DED_COUNT 22 23 LATENCY_FIFO_NEXT_RAM_SEC_COUNT 24 25 LATENCY_FIFO_NEXT_RAM_DED_COUNT 26 27 regTCC_EDC_CNT2 0 0xb83 16 0 0 CACHE_TAG_PROBE_FIFO_SEC_COUNT 0 1 CACHE_TAG_PROBE_FIFO_DED_COUNT 2 3 UC_ATOMIC_FIFO_SEC_COUNT 4 5 UC_ATOMIC_FIFO_DED_COUNT 6 7 WRITE_CACHE_READ_SEC_COUNT 8 9 WRITE_CACHE_READ_DED_COUNT 10 11 RETURN_CONTROL_SEC_COUNT 12 13 RETURN_CONTROL_DED_COUNT 14 15 IN_USE_TRANSFER_SEC_COUNT 16 17 IN_USE_TRANSFER_DED_COUNT 18 19 IN_USE_DEC_SEC_COUNT 20 21 IN_USE_DEC_DED_COUNT 22 23 WRITE_RETURN_SEC_COUNT 24 25 WRITE_RETURN_DED_COUNT 26 27 RETURN_DATA_SEC_COUNT 28 29 RETURN_DATA_DED_COUNT 30 31 regTCC_REDUNDANCY 0 0xb84 2 0 0 MC_SEL0 0 0 MC_SEL1 1 1 regTCC_EXE_DISABLE 0 0xb85 1 0 0 EXE_DISABLE 1 1 regTCC_DSM_CNTL 0 0xb86 20 0 0 CACHE_DATA_IRRITATOR_DATA_SEL 0 1 CACHE_DATA_IRRITATOR_SINGLE_WRITE 2 2 CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL 3 4 CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE 5 5 CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL 6 7 CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE 8 8 CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL 9 10 CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE 11 11 CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL 12 13 CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE 14 14 CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL 15 16 CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE 17 17 HIGH_RATE_TAG_IRRITATOR_DATA_SEL 18 19 HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE 20 20 LOW_RATE_TAG_IRRITATOR_DATA_SEL 21 22 LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE 23 23 IN_USE_DEC_IRRITATOR_DATA_SEL 24 25 IN_USE_DEC_IRRITATOR_SINGLE_WRITE 26 26 IN_USE_TRANSFER_IRRITATOR_DATA_SEL 27 28 IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE 29 29 regTCC_DSM_CNTLA 0 0xb87 20 0 0 SRC_FIFO_IRRITATOR_DATA_SEL 0 1 SRC_FIFO_IRRITATOR_SINGLE_WRITE 2 2 UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL 3 4 UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE 5 5 WRITE_RETURN_IRRITATOR_DATA_SEL 6 7 WRITE_RETURN_IRRITATOR_SINGLE_WRITE 8 8 WRITE_CACHE_READ_IRRITATOR_DATA_SEL 9 10 WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE 11 11 LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL 12 13 LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE 14 14 CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL 15 16 CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE 17 17 LATENCY_FIFO_IRRITATOR_DATA_SEL 18 19 LATENCY_FIFO_IRRITATOR_SINGLE_WRITE 20 20 RETURN_DATA_IRRITATOR_DATA_SEL 21 22 RETURN_DATA_IRRITATOR_SINGLE_WRITE 23 23 RETURN_CONTROL_IRRITATOR_DATA_SEL 24 25 RETURN_CONTROL_IRRITATOR_SINGLE_WRITE 26 26 OUTPUT_FIFOS_IRRITATOR_DATA_SEL 27 28 OUTPUT_FIFOS_IRRITATOR_SINGLE_WRITE 29 29 regTCC_DSM_CNTL2 0 0xb88 17 0 0 CACHE_DATA_ENABLE_ERROR_INJECT 0 1 CACHE_DATA_SELECT_INJECT_DELAY 2 2 CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT 3 4 CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY 5 5 CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT 6 7 CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY 8 8 CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT 9 10 CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY 11 11 CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT 12 13 CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY 14 14 CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT 15 16 CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY 17 17 HIGH_RATE_TAG_ENABLE_ERROR_INJECT 18 19 HIGH_RATE_TAG_SELECT_INJECT_DELAY 20 20 LOW_RATE_TAG_ENABLE_ERROR_INJECT 21 22 LOW_RATE_TAG_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regTCC_DSM_CNTL2A 0 0xb89 20 0 0 IN_USE_DEC_ENABLE_ERROR_INJECT 0 1 IN_USE_DEC_SELECT_INJECT_DELAY 2 2 IN_USE_TRANSFER_ENABLE_ERROR_INJECT 3 4 IN_USE_TRANSFER_SELECT_INJECT_DELAY 5 5 RETURN_DATA_ENABLE_ERROR_INJECT 6 7 RETURN_DATA_SELECT_INJECT_DELAY 8 8 RETURN_CONTROL_ENABLE_ERROR_INJECT 9 10 RETURN_CONTROL_SELECT_INJECT_DELAY 11 11 UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT 12 13 UC_ATOMIC_FIFO_SELECT_INJECT_DELAY 14 14 WRITE_RETURN_ENABLE_ERROR_INJECT 15 16 WRITE_RETURN_SELECT_INJECT_DELAY 17 17 WRITE_CACHE_READ_ENABLE_ERROR_INJECT 18 19 WRITE_CACHE_READ_SELECT_INJECT_DELAY 20 20 SRC_FIFO_ENABLE_ERROR_INJECT 21 22 SRC_FIFO_SELECT_INJECT_DELAY 23 23 CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT 24 25 CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY 26 26 OUTPUT_FIFOS_ENABLE_ERROR_INJECT 27 28 OUTPUT_FIFOS_SELECT_INJECT_DELAY 29 29 regTCC_DSM_CNTL2B 0 0xb8a 10 0 0 LATENCY_FIFO_ENABLE_ERROR_INJECT 0 1 LATENCY_FIFO_SELECT_INJECT_DELAY 2 2 LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT 3 4 LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY 5 5 WRITE_EARLY_RETURN_ENABLE_ERROR_INJECT 12 13 WRITE_EARLY_RETURN_SELECT_INJECT_DELAY 14 14 WRITE_EARLY_RETURN_IRRITATOR_DATA_SEL 15 16 WRITE_EARLY_RETURN_IRRITATOR_SINGLE_WRITE 17 17 RETRUN_BUFFER_LEVEL_BUBBLE_THRESHOLD 18 23 RTN_GO_FIFO_BUBBLE_THRESHOLD 24 28 regTCC_WBINVL2 0 0xb8b 1 0 0 DONE 4 4 regTCC_SOFT_RESET 0 0xb8c 1 0 0 HALT_FOR_RESET 0 0 regTCC_DSM_CNTL3 0 0xb8e 16 0 0 CACHE_DATA_BANK_0_2_IRRITATOR_DATA_SEL 0 1 CACHE_DATA_BANK_0_2_IRRITATOR_SINGLE_WRITE 2 2 CACHE_DATA_BANK_0_3_IRRITATOR_DATA_SEL 3 4 CACHE_DATA_BANK_0_3_IRRITATOR_SINGLE_WRITE 5 5 CACHE_DATA_BANK_1_2_IRRITATOR_DATA_SEL 6 7 CACHE_DATA_BANK_1_2_IRRITATOR_SINGLE_WRITE 8 8 CACHE_DATA_BANK_1_3_IRRITATOR_DATA_SEL 9 10 CACHE_DATA_BANK_1_3_IRRITATOR_SINGLE_WRITE 11 11 CACHE_DATA_BANK_0_2_ENABLE_ERROR_INJECT 12 13 CACHE_DATA_BANK_0_2_SELECT_INJECT_DELAY 14 14 CACHE_DATA_BANK_0_3_ENABLE_ERROR_INJECT 15 16 CACHE_DATA_BANK_0_3_SELECT_INJECT_DELAY 17 17 CACHE_DATA_BANK_1_2_ENABLE_ERROR_INJECT 18 19 CACHE_DATA_BANK_1_2_SELECT_INJECT_DELAY 20 20 CACHE_DATA_BANK_1_3_ENABLE_ERROR_INJECT 21 22 CACHE_DATA_BANK_1_3_SELECT_INJECT_DELAY 23 23 regTCA_CTRL 0 0xbc0 12 0 0 HOLE_TIMEOUT 0 3 RB_STILL_4_PHASE 4 4 RB_AS_TCI 5 5 DISABLE_UTCL2_PRIORITY 6 6 DISABLE_RB_ONLY_TCA_ARBITER 7 7 TCA_TCC_FGCG_DISABLE 8 8 TCA_TCA_FGCG_DISABLE 9 9 TCA_TCH_FGCG_DISABLE 10 10 TCA_TCX_FGCG_DISABLE 11 11 TCA_RANDOM_REVERSE_PRIORITY_ENABLE 12 12 RTN_CREDIT_THRESHOLD 13 15 ACK_CREDIT_THRESHOLD 16 18 regTCA_BURST_MASK 0 0xbc1 1 0 0 ADDR_MASK 0 31 regTCA_BURST_CTRL 0 0xbc2 9 0 0 MAX_BURST 0 2 TCP_DISABLE 4 4 SQC_DISABLE 5 5 CPF_DISABLE 6 6 CPG_DISABLE 7 7 SQG_DISABLE 10 10 UTCL2_DISABLE 11 11 TPI_DISABLE 12 12 RLC_DISABLE 13 13 regTCA_DSM_CNTL 0 0xbc3 4 0 0 HOLE_FIFO_SED_IRRITATOR_DATA_SEL 0 1 HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE 2 2 REQ_FIFO_SED_IRRITATOR_DATA_SEL 3 4 REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE 5 5 regTCA_DSM_CNTL2 0 0xbc4 5 0 0 HOLE_FIFO_SED_ENABLE_ERROR_INJECT 0 1 HOLE_FIFO_SED_SELECT_INJECT_DELAY 2 2 REQ_FIFO_SED_ENABLE_ERROR_INJECT 3 4 REQ_FIFO_SED_SELECT_INJECT_DELAY 5 5 INJECT_DELAY 26 31 regTCA_EDC_CNT 0 0xbc5 4 0 0 HOLE_FIFO_SEC_COUNT 0 1 HOLE_FIFO_DED_COUNT 2 3 REQ_FIFO_SEC_COUNT 4 5 REQ_FIFO_DED_COUNT 6 7 regTCX_CTRL 0 0xbc6 3 0 0 TCX_TCX_FGCG_DISABLE 0 0 TCX_TCR_FGCG_DISABLE 1 1 TCX_TCC_FGCG_DISABLE 2 2 regTCX_DSM_CNTL 0 0xbc7 16 0 0 GROUP0_SED_IRRITATOR_DATA_SEL 0 1 GROUP1_SED_IRRITATOR_DATA_SEL 2 3 GROUP2_SED_IRRITATOR_DATA_SEL 4 5 GROUP3_SED_IRRITATOR_DATA_SEL 6 7 GROUP4_SED_IRRITATOR_DATA_SEL 8 9 GROUP5_SED_IRRITATOR_DATA_SEL 10 11 GROUP6_SED_IRRITATOR_DATA_SEL 12 13 GROUP7_SED_IRRITATOR_DATA_SEL 14 15 GROUP8_SED_IRRITATOR_DATA_SEL 16 17 GROUP9_SED_IRRITATOR_DATA_SEL 18 19 GROUP10_SED_IRRITATOR_DATA_SEL 20 21 GROUP11_SED_IRRITATOR_DATA_SEL 22 23 GROUP12_SED_IRRITATOR_DATA_SEL 24 25 GROUP13_SED_IRRITATOR_DATA_SEL 26 27 GROUP14_SED_IRRITATOR_DATA_SEL 28 29 SED_IRRITATOR_SINGLE_WRITE 30 30 regTCX_DSM_CNTL2 0 0xbc8 3 0 0 SED_ENABLE_ERROR_INJECT 0 1 SED_SELECT_INJECT_DELAY 2 2 INJECT_DELAY 26 31 regTCX_EDC_CNT 0 0xbc9 16 0 0 GROUP0_SEC_COUNT 0 1 GROUP0_DED_COUNT 2 3 GROUP1_SEC_COUNT 4 5 GROUP1_DED_COUNT 6 7 GROUP2_SEC_COUNT 8 9 GROUP2_DED_COUNT 10 11 GROUP3_SEC_COUNT 12 13 GROUP3_DED_COUNT 14 15 GROUP4_SEC_COUNT 16 17 GROUP4_DED_COUNT 18 19 GROUP5_SED_COUNT 20 21 GROUP6_SED_COUNT 22 23 GROUP7_SED_COUNT 24 25 GROUP8_SED_COUNT 26 27 GROUP9_SED_COUNT 28 29 GROUP10_SED_COUNT 30 31 regTCX_EDC_CNT2 0 0xbca 4 0 0 GROUP11_SED_COUNT 0 1 GROUP12_SED_COUNT 2 3 GROUP13_SED_COUNT 4 5 GROUP14_SED_COUNT 6 7 regTCP_WATCH0_ADDR_H 0 0x12a0 1 0 0 ADDR 0 15 regTCP_WATCH0_ADDR_L 0 0x12a1 1 0 0 ADDR 6 31 regTCP_WATCH0_CNTL 0 0x12a2 5 0 0 MASK 0 23 VMID 24 27 ATC 28 28 MODE 29 30 VALID 31 31 regTCP_WATCH1_ADDR_H 0 0x12a3 1 0 0 ADDR 0 15 regTCP_WATCH1_ADDR_L 0 0x12a4 1 0 0 ADDR 6 31 regTCP_WATCH1_CNTL 0 0x12a5 5 0 0 MASK 0 23 VMID 24 27 ATC 28 28 MODE 29 30 VALID 31 31 regTCP_WATCH2_ADDR_H 0 0x12a6 1 0 0 ADDR 0 15 regTCP_WATCH2_ADDR_L 0 0x12a7 1 0 0 ADDR 6 31 regTCP_WATCH2_CNTL 0 0x12a8 5 0 0 MASK 0 23 VMID 24 27 ATC 28 28 MODE 29 30 VALID 31 31 regTCP_WATCH3_ADDR_H 0 0x12a9 1 0 0 ADDR 0 15 regTCP_WATCH3_ADDR_L 0 0x12aa 1 0 0 ADDR 6 31 regTCP_WATCH3_CNTL 0 0x12ab 5 0 0 MASK 0 23 VMID 24 27 ATC 28 28 MODE 29 30 VALID 31 31 regTCP_GATCL1_CNTL 0 0x12b0 5 0 0 INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 FORCE_IN_ORDER 27 27 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regTCP_ATC_EDC_GATCL1_CNT 0 0x12b1 1 0 0 DATA_SEC 0 7 regTCP_GATCL1_DSM_CNTL 0 0x12b2 3 0 0 SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0 0 0 SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1 1 1 TCP_GATCL1_ENABLE_SINGLE_WRITE_A 2 2 regTCP_DSM_CNTL 0 0x12b3 14 0 0 CACHE_RAM_IRRITATOR_DATA_SEL 0 1 CACHE_RAM_IRRITATOR_SINGLE_WRITE 2 2 LFIFO_RAM_IRRITATOR_DATA_SEL 3 4 LFIFO_RAM_IRRITATOR_SINGLE_WRITE 5 5 CMD_FIFO_IRRITATOR_DATA_SEL 6 7 CMD_FIFO_IRRITATOR_SINGLE_WRITE 8 8 VM_FIFO_IRRITATOR_DATA_SEL 9 10 VM_FIFO_IRRITATOR_SINGLE_WRITE 11 11 DB_RAM_IRRITATOR_DATA_SEL 12 13 DB_RAM_IRRITATOR_SINGLE_WRITE 14 14 UTCL1_LFIFO0_IRRITATOR_DATA_SEL 15 16 UTCL1_LFIFO0_IRRITATOR_SINGLE_WRITE 17 17 UTCL1_LFIFO1_IRRITATOR_DATA_SEL 18 19 UTCL1_LFIFO1_IRRITATOR_SINGLE_WRITE 20 20 regTCP_UTCL1_CNTL1 0 0x12b5 14 0 0 FORCE_4K_L2_RESP 0 0 GPUVM_64K_DEFAULT 1 1 GPUVM_PERM_MODE 2 2 RESP_MODE 3 4 RESP_FAULT_MODE 5 6 CLIENTID 7 15 UTCL1_FGCG_REPEATER_DISABLE 16 16 REG_INV_VMID 19 22 REG_INV_ALL_VMID 23 23 REG_INV_TOGGLE 24 24 CLIENT_INVALIDATE_ALL_VMID 25 25 FORCE_MISS 26 26 REDUCE_FIFO_DEPTH_BY_2 28 29 REDUCE_CACHE_SIZE_BY_2 30 31 regTCP_UTCL1_CNTL2 0 0x12b6 7 0 0 SPARE 0 7 MTYPE_OVRD_DIS 9 9 ANY_LINE_VALID 10 10 GPUVM_INV_MODE 12 12 FORCE_SNOOP 14 14 FORCE_GPUVM_INV_ACK 15 15 FORCE_FRAG_2M_TO_64K 26 26 regTCP_UTCL1_STATUS 0 0x12b7 3 0 0 FAULT_DETECTED 0 0 RETRY_DETECTED 1 1 PRT_DETECTED 2 2 regTCP_DSM_CNTL2 0 0x12b8 15 0 0 CACHE_RAM_ENABLE_ERROR_INJECT 0 1 CACHE_RAM_SELECT_INJECT_DELAY 2 2 LFIFO_RAM_ENABLE_ERROR_INJECT 3 4 LFIFO_RAM_SELECT_INJECT_DELAY 5 5 CMD_FIFO_ENABLE_ERROR_INJECT 6 7 CMD_FIFO_SELECT_INJECT_DELAY 8 8 VM_FIFO_ENABLE_ERROR_INJECT 9 10 VM_FIFO_SELECT_INJECT_DELAY 11 11 DB_RAM_ENABLE_ERROR_INJECT 12 13 DB_RAM_SELECT_INJECT_DELAY 14 14 UTCL1_LFIFO0_ENABLE_ERROR_INJECT 15 16 UTCL1_LFIFO0_SELECT_INJECT_DELAY 17 17 UTCL1_LFIFO1_ENABLE_ERROR_INJECT 18 19 UTCL1_LFIFO1_SELECT_INJECT_DELAY 20 20 TCP_INJECT_DELAY 26 31 regTCP_PERFCOUNTER_FILTER 0 0x12b9 12 0 0 BUFFER 0 0 FLAT 1 1 DIM 2 4 DATA_FORMAT 5 10 NUM_FORMAT 11 14 SW_MODE 15 19 NUM_SAMPLES 20 21 OPCODE_TYPE 22 24 GLC 25 25 SLC 26 26 COMPRESSION_ENABLE 27 27 ADDR_MODE 28 30 regTCP_PERFCOUNTER_FILTER_EN 0 0x12ba 12 0 0 BUFFER 0 0 FLAT 1 1 DIM 2 2 DATA_FORMAT 3 3 NUM_FORMAT 4 4 SW_MODE 5 5 NUM_SAMPLES 6 6 OPCODE_TYPE 7 7 GLC 8 8 SLC 9 9 COMPRESSION_ENABLE 10 10 ADDR_MODE 11 11 regTD_STATUS 0 0x526 1 0 0 BUSY 31 31 regTD_EDC_CNT 0 0x52e 6 0 0 SS_FIFO_LO_SEC_COUNT 0 1 SS_FIFO_LO_DED_COUNT 2 3 SS_FIFO_HI_SEC_COUNT 4 5 SS_FIFO_HI_DED_COUNT 6 7 CS_FIFO_SEC_COUNT 8 9 CS_FIFO_DED_COUNT 10 11 regTD_DSM_CNTL 0 0x52f 6 0 0 TD_SS_FIFO_LO_DSM_IRRITATOR_DATA 0 1 TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE 2 2 TD_SS_FIFO_HI_DSM_IRRITATOR_DATA 3 4 TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE 5 5 TD_CS_FIFO_DSM_IRRITATOR_DATA 6 7 TD_CS_FIFO_ENABLE_SINGLE_WRITE 8 8 regTD_DSM_CNTL2 0 0x530 7 0 0 TD_SS_FIFO_LO_ENABLE_ERROR_INJECT 0 1 TD_SS_FIFO_LO_SELECT_INJECT_DELAY 2 2 TD_SS_FIFO_HI_ENABLE_ERROR_INJECT 3 4 TD_SS_FIFO_HI_SELECT_INJECT_DELAY 5 5 TD_CS_FIFO_ENABLE_ERROR_INJECT 6 7 TD_CS_FIFO_SELECT_INJECT_DELAY 8 8 TD_INJECT_DELAY 26 31 regTD_SCRATCH 0 0x533 1 0 0 SCRATCH 0 31 regTA_CNTL 0 0x541 5 0 0 FX_XNACK_CREDIT 0 6 SQ_XNACK_CREDIT 9 12 TC_DATA_CREDIT 13 15 ALIGNER_CREDIT 16 20 TD_FIFO_CREDIT 22 31 regTA_CNTL_AUX 0 0x542 26 0 0 SCOAL_DSWIZZLE_N 0 0 RESERVED 1 3 TFAULT_EN_OVERRIDE 5 5 GATHERH_DST_SEL 6 6 DISABLE_GATHER4_BC_SWIZZLE 7 7 NONIMG_ANISO_BYPASS 9 9 ANISO_HALF_THRESH 10 11 ANISO_ERROR_FP_VBIAS 12 12 ANISO_STEP_ORDER 13 13 ANISO_STEP 14 14 MINMAG_UNNORM 15 15 ANISO_WEIGHT_MODE 16 16 ANISO_RATIO_LUT 17 17 ANISO_TAP 18 18 ANISO_MIP_ADJ_MODE 19 19 DETERMINISM_RESERVED_DISABLE 20 20 DETERMINISM_OPCODE_STRICT_DISABLE 21 21 DETERMINISM_MISC_DISABLE 22 22 DETERMINISM_SAMPLE_C_DFMT_DISABLE 23 23 DETERMINISM_SAMPLER_MSAA_DISABLE 24 24 DETERMINISM_WRITEOP_READFMT_DISABLE 25 25 DETERMINISM_DFMT_NFMT_DISABLE 26 26 DISABLE_DWORD_X2_COALESCE 27 27 CUBEMAP_SLICE_CLAMP 28 28 TRUNC_SMALL_NEG 29 29 ARRAY_ROUND_MODE 30 31 regTA_FEATURE_CNTL 0 0x543 5 0 0 ATOMIC_COALESCING_EN 4 5 NONIMG_TA_FASTPATH 10 10 TA_ACFIFO_CHICKEN 11 11 TA_CAC_CHICKEN 12 12 AFIFO_SPLIT_CHICKEN 13 13 regTA_STATUS 0 0x548 17 0 0 FG_PFIFO_EMPTYB 12 12 FG_LFIFO_EMPTYB 13 13 FG_SFIFO_EMPTYB 14 14 FL_PFIFO_EMPTYB 16 16 FL_LFIFO_EMPTYB 17 17 FL_SFIFO_EMPTYB 18 18 FA_PFIFO_EMPTYB 20 20 FA_LFIFO_EMPTYB 21 21 FA_SFIFO_EMPTYB 22 22 IN_BUSY 24 24 FG_BUSY 25 25 LA_BUSY 26 26 FL_BUSY 27 27 TA_BUSY 28 28 FA_BUSY 29 29 AL_BUSY 30 30 BUSY 31 31 regTA_SCRATCH 0 0x564 1 0 0 SCRATCH 0 31 regTA_DSM_CNTL 0 0x584 12 0 0 TA_FS_DFIFO_DSM_IRRITATOR_DATA 0 1 TA_FS_DFIFO_ENABLE_SINGLE_WRITE 2 2 TA_FL_LFIFO_DSM_IRRITATOR_DATA 6 7 TA_FL_LFIFO_ENABLE_SINGLE_WRITE 8 8 TA_FX_LFIFO_DSM_IRRITATOR_DATA 9 10 TA_FX_LFIFO_ENABLE_SINGLE_WRITE 11 11 TA_FS_CFIFO_DSM_IRRITATOR_DATA 12 13 TA_FS_CFIFO_ENABLE_SINGLE_WRITE 14 14 TA_FS_AFIFO_LO_DSM_IRRITATOR_DATA 15 16 TA_FS_AFIFO_LO_ENABLE_SINGLE_WRITE 17 17 TA_FS_AFIFO_HI_DSM_IRRITATOR_DATA 18 19 TA_FS_AFIFO_HI_ENABLE_SINGLE_WRITE 20 20 regTA_DSM_CNTL2 0 0x585 13 0 0 TA_FS_DFIFO_ENABLE_ERROR_INJECT 0 1 TA_FS_DFIFO_SELECT_INJECT_DELAY 2 2 TA_FL_LFIFO_ENABLE_ERROR_INJECT 6 7 TA_FL_LFIFO_SELECT_INJECT_DELAY 8 8 TA_FX_LFIFO_ENABLE_ERROR_INJECT 9 10 TA_FX_LFIFO_SELECT_INJECT_DELAY 11 11 TA_FS_CFIFO_ENABLE_ERROR_INJECT 12 13 TA_FS_CFIFO_SELECT_INJECT_DELAY 14 14 TA_FS_AFIFO_LO_ENABLE_ERROR_INJECT 15 16 TA_FS_AFIFO_LO_SELECT_INJECT_DELAY 17 17 TA_FS_AFIFO_HI_ENABLE_ERROR_INJECT 18 19 TA_FS_AFIFO_HI_SELECT_INJECT_DELAY 20 20 TA_INJECT_DELAY 26 31 regTA_EDC_CNT 0 0x586 12 0 0 TA_FS_DFIFO_SEC_COUNT 0 1 TA_FS_DFIFO_DED_COUNT 2 3 TA_FS_AFIFO_LO_SEC_COUNT 4 5 TA_FS_AFIFO_LO_DED_COUNT 6 7 TA_FL_LFIFO_SEC_COUNT 8 9 TA_FL_LFIFO_DED_COUNT 10 11 TA_FX_LFIFO_SEC_COUNT 12 13 TA_FX_LFIFO_DED_COUNT 14 15 TA_FS_CFIFO_SEC_COUNT 16 17 TA_FS_CFIFO_DED_COUNT 18 19 TA_FS_AFIFO_HI_SEC_COUNT 20 21 TA_FS_AFIFO_HI_DED_COUNT 22 23 regATC_L2_CNTL 0 0x800 12 0 0 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS 8 9 NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS 11 12 NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 14 14 NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 15 15 CACHE_INVALIDATE_MODE 16 18 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 19 19 FRAG_APT_INTXN_MODE 20 21 CLI_GPA_REQ_FRAG_SIZE 22 27 regATC_L2_CNTL2 0 0x801 7 0 0 BANK_SELECT 0 5 NUM_BANKS_LOG2 6 8 L2_CACHE_UPDATE_MODE 9 10 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 11 11 L2_CACHE_SWAP_TAG_INDEX_LSBS 12 14 L2_CACHE_VMID_MODE 15 17 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 18 23 regATC_L2_CACHE_DATA0 0 0x804 4 0 0 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 22 VIRTUAL_PAGE_ADDRESS_HIGH 23 26 regATC_L2_CACHE_DATA1 0 0x805 1 0 0 VIRTUAL_PAGE_ADDRESS_LOW 0 31 regATC_L2_CACHE_DATA2 0 0x806 1 0 0 PHYSICAL_PAGE_ADDRESS 0 31 regATC_L2_CACHE_DATA3 0 0x807 1 0 0 PHYSICAL_PAGE_ADDRESS 0 31 regATC_L2_CNTL3 0 0x808 7 0 0 L2_SMALLK_FRAGMENT_SIZE 0 5 L2_MIDK_FRAGMENT_SIZE 6 11 L2_BIGK_FRAGMENT_SIZE 12 17 DELAY_SEND_INVALIDATION_REQUEST 18 20 ATS_REQUEST_CREDIT_MINUS1 21 26 COMPCLKREQ_OFF_HYSTERESIS 27 29 REPEATER_FGCG_OFF 30 30 regATC_L2_STATUS 0 0x809 1 0 0 BUSY 0 0 regATC_L2_STATUS2 0 0x80a 4 0 0 UCE_MEM_ADDR 0 11 UCE_MEM_INST 12 17 UCE_SRT_CACHE 18 18 UCE 19 19 regATC_L2_MISC_CG 0 0x80b 3 0 0 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 regATC_L2_MEM_POWER_LS 0 0x80c 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 regATC_L2_CGTT_CLK_CTRL 0 0x80d 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regATC_L2_CACHE_4K_DSM_INDEX 0 0x80e 1 0 0 INDEX 0 7 regATC_L2_CACHE_32K_DSM_INDEX 0 0x80f 1 0 0 INDEX 0 7 regATC_L2_CACHE_2M_DSM_INDEX 0 0x810 1 0 0 INDEX 0 7 regATC_L2_CACHE_4K_DSM_CNTL 0 0x811 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CACHE_32K_DSM_CNTL 0 0x812 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CACHE_2M_DSM_CNTL 0 0x813 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CNTL4 0 0x814 2 0 0 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 0 9 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 10 19 regATC_L2_MM_GROUP_RT_CLASSES 0 0x815 1 0 0 GROUP_RT_CLASS 0 31 regATC_L2_PERFCOUNTER0_CFG 0 0x3d40 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regATC_L2_PERFCOUNTER1_CFG 0 0x3d41 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regATC_L2_PERFCOUNTER_RSLT_CNTL 0 0x3d42 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regATC_L2_PERFCOUNTER_LO 0 0x3500 1 0 1 COUNTER_LO 0 31 regATC_L2_PERFCOUNTER_HI 0 0x3501 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regL2TLB_TLB0_STATUS 0 0x991 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0 0x993 1 0 0 ADDR 0 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0 0x994 10 0 0 ADDR 0 3 VMID 4 7 VFID 9 12 VF 13 13 GPA 14 15 RD_PERM 16 16 WR_PERM 17 17 EX_PERM 18 18 CLIENT_ID 19 27 REQ 31 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0 0x995 1 0 0 ADDR 0 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0 0x996 12 0 0 ADDR 0 3 PERMS 4 6 FRAGMENT_SIZE 7 12 SNOOP 13 13 SPA 14 14 IO 15 15 PTE_TMZ 16 16 NO_PTE 17 17 MTYPE 18 19 MEMLOG 20 20 NACK 21 22 ACK 30 30 regL2TLB_PERFCOUNTER0_CFG 0 0x3d5c 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER1_CFG 0 0x3d5d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER2_CFG 0 0x3d5e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER3_CFG 0 0x3d5f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER_RSLT_CNTL 0 0x3d60 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regL2TLB_PERFCOUNTER_LO 0 0x3518 1 0 1 COUNTER_LO 0 31 regL2TLB_PERFCOUNTER_HI 0 0x3519 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regVM_L2_CNTL 0 0x840 14 0 0 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 regVM_L2_CNTL2 0 0x841 7 0 0 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 regVM_L2_CNTL3 0 0x842 11 0 0 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 regVM_L2_STATUS 0 0x843 7 0 0 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 regVM_DUMMY_PAGE_FAULT_CNTL 0 0x844 3 0 0 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x845 1 0 0 DUMMY_PAGE_ADDR_LO32 0 31 regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x846 1 0 0 DUMMY_PAGE_ADDR_HI4 0 3 regVM_L2_PROTECTION_FAULT_CNTL 0 0x847 17 0 0 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 regVM_L2_PROTECTION_FAULT_CNTL2 0 0x848 5 0 0 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 regVM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x849 1 0 0 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 regVM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x84a 1 0 0 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 regVM_L2_PROTECTION_FAULT_STATUS 0 0x84b 12 0 0 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 28 UCE 29 29 FED 30 30 regVM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x84c 1 0 0 LOGICAL_PAGE_ADDR_LO32 0 31 regVM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x84d 1 0 0 LOGICAL_PAGE_ADDR_HI4 0 3 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x84e 1 0 0 PHYSICAL_PAGE_ADDR_LO32 0 31 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x84f 1 0 0 PHYSICAL_PAGE_ADDR_HI4 0 3 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x851 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x852 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x853 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x854 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x855 1 0 0 PHYSICAL_PAGE_OFFSET_LO32 0 31 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x856 1 0 0 PHYSICAL_PAGE_OFFSET_HI4 0 3 regVM_L2_CNTL4 0 0x857 8 0 0 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 GC_CH_FGCG_OFF 29 29 VFIFO_HEAD_OF_QUEUE 30 30 regVM_L2_MM_GROUP_RT_CLASSES 0 0x858 32 0 0 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 regVM_L2_BANK_SELECT_RESERVED_CID 0 0x859 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 regVM_L2_BANK_SELECT_RESERVED_CID2 0 0x85a 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 regVM_L2_CACHE_PARITY_CNTL 0 0x85b 9 0 0 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 regVM_L2_CGTT_CLK_CTRL 0 0x85e 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regVM_L2_CGTT_BUSY_CTRL 0 0x85f 2 0 0 READ_DELAY 0 3 ALWAYS_BUSY 4 4 regVML2_MEM_ECC_INDEX 0 0x861 1 0 0 INDEX 0 7 regVML2_WALKER_MEM_ECC_INDEX 0 0x862 1 0 0 INDEX 0 7 regUTCL2_MEM_ECC_INDEX 0 0x863 1 0 0 INDEX 0 7 regVML2_MEM_ECC_CNTL 0 0x864 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regVML2_WALKER_MEM_ECC_CNTL 0 0x865 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regUTCL2_MEM_ECC_CNTL 0 0x866 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regVML2_MEM_ECC_STATUS 0 0x867 2 0 0 UCE 0 0 FED 1 1 regVML2_WALKER_MEM_ECC_STATUS 0 0x868 2 0 0 UCE 0 0 FED 1 1 regUTCL2_MEM_ECC_STATUS 0 0x869 2 0 0 UCE 0 0 FED 1 1 regUTCL2_EDC_MODE 0 0x86a 6 0 0 FORCE_SEC_ON_DED 15 15 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regUTCL2_EDC_CONFIG 0 0x86b 1 0 0 DIS_EDC 1 1 regMC_VM_L2_PERFCOUNTER0_CFG 0 0x3d4c 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER1_CFG 0 0x3d4d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER2_CFG 0 0x3d4e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER3_CFG 0 0x3d4f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER4_CFG 0 0x3d50 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER5_CFG 0 0x3d51 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER6_CFG 0 0x3d52 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER7_CFG 0 0x3d53 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x3d54 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMC_VM_L2_PERFCOUNTER_LO 0 0x3508 1 0 1 COUNTER_LO 0 31 regMC_VM_L2_PERFCOUNTER_HI 0 0x3509 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regVM_CONTEXT0_CNTL 0 0x880 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT1_CNTL 0 0x881 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT2_CNTL 0 0x882 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT3_CNTL 0 0x883 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT4_CNTL 0 0x884 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT5_CNTL 0 0x885 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT6_CNTL 0 0x886 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT7_CNTL 0 0x887 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT8_CNTL 0 0x888 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT9_CNTL 0 0x889 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT10_CNTL 0 0x88a 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT11_CNTL 0 0x88b 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT12_CNTL 0 0x88c 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT13_CNTL 0 0x88d 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT14_CNTL 0 0x88e 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT15_CNTL 0 0x88f 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXTS_DISABLE 0 0x890 16 0 0 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 regVM_INVALIDATE_ENG0_SEM 0 0x891 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG1_SEM 0 0x892 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG2_SEM 0 0x893 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG3_SEM 0 0x894 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG4_SEM 0 0x895 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG5_SEM 0 0x896 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG6_SEM 0 0x897 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG7_SEM 0 0x898 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG8_SEM 0 0x899 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG9_SEM 0 0x89a 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG10_SEM 0 0x89b 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG11_SEM 0 0x89c 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG12_SEM 0 0x89d 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG13_SEM 0 0x89e 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG14_SEM 0 0x89f 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG15_SEM 0 0x8a0 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG16_SEM 0 0x8a1 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG17_SEM 0 0x8a2 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG0_REQ 0 0x8a3 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG1_REQ 0 0x8a4 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG2_REQ 0 0x8a5 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG3_REQ 0 0x8a6 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG4_REQ 0 0x8a7 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG5_REQ 0 0x8a8 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG6_REQ 0 0x8a9 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG7_REQ 0 0x8aa 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG8_REQ 0 0x8ab 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG9_REQ 0 0x8ac 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG10_REQ 0 0x8ad 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG11_REQ 0 0x8ae 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG12_REQ 0 0x8af 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG13_REQ 0 0x8b0 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG14_REQ 0 0x8b1 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG15_REQ 0 0x8b2 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG16_REQ 0 0x8b3 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG17_REQ 0 0x8b4 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG0_ACK 0 0x8b5 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG1_ACK 0 0x8b6 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG2_ACK 0 0x8b7 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG3_ACK 0 0x8b8 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG4_ACK 0 0x8b9 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG5_ACK 0 0x8ba 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG6_ACK 0 0x8bb 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG7_ACK 0 0x8bc 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG8_ACK 0 0x8bd 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG9_ACK 0 0x8be 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG10_ACK 0 0x8bf 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG11_ACK 0 0x8c0 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG12_ACK 0 0x8c1 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG13_ACK 0 0x8c2 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG14_ACK 0 0x8c3 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG15_ACK 0 0x8c4 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG16_ACK 0 0x8c5 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG17_ACK 0 0x8c6 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0x8c7 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0x8c8 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0x8c9 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0x8ca 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0x8cb 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0x8cc 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0x8cd 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0x8ce 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0x8cf 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0x8d0 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0x8d1 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0x8d2 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0x8d3 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0x8d4 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0x8d5 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0x8d6 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0x8d7 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0x8d8 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0x8d9 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0x8da 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0x8db 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0x8dc 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0x8dd 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0x8de 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0x8df 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0x8e0 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0x8e1 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0x8e2 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0x8e3 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0x8e4 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0x8e5 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0x8e6 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0x8e7 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0x8e8 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0x8e9 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0x8ea 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x8eb 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x8ec 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x8ed 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x8ee 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x8ef 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x8f0 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x8f1 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x8f2 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x8f3 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x8f4 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x8f5 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x8f6 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x8f7 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x8f8 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x8f9 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x8fa 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x8fb 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x8fc 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x8fd 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x8fe 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x8ff 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x900 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x901 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x902 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x903 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x904 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x905 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x906 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x907 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x908 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x909 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x90a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x90b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x90c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x90d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x90e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x90f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x910 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x911 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x912 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x913 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x914 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x915 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x916 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x917 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x918 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x919 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x91a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x91b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x91c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x91d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x91e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x91f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x920 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x921 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x922 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x923 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x924 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x925 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x926 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x927 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x928 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x929 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x92a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x92b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x92c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x92d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x92e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x92f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x930 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x931 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x932 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x933 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x934 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x935 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x936 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x937 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x938 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x939 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x93a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x93b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x93c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x93d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x93e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x93f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x940 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x941 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x942 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x943 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x944 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x945 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x946 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x947 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x948 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x949 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x94a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regMC_VM_FB_SIZE_OFFSET_VF0 0 0x5a80 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF1 0 0x5a81 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF2 0 0x5a82 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF3 0 0x5a83 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF4 0 0x5a84 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF5 0 0x5a85 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF6 0 0x5a86 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF7 0 0x5a87 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF8 0 0x5a88 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF9 0 0x5a89 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF10 0 0x5a8a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF11 0 0x5a8b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF12 0 0x5a8c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF13 0 0x5a8d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF14 0 0x5a8e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF15 0 0x5a8f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_MARC_BASE_LO_0 0 0x5a91 1 0 1 MARC_BASE_LO_0 12 31 regMC_VM_MARC_BASE_LO_1 0 0x5a92 1 0 1 MARC_BASE_LO_1 12 31 regMC_VM_MARC_BASE_LO_2 0 0x5a93 1 0 1 MARC_BASE_LO_2 12 31 regMC_VM_MARC_BASE_LO_3 0 0x5a94 1 0 1 MARC_BASE_LO_3 12 31 regMC_VM_MARC_BASE_HI_0 0 0x5a95 1 0 1 MARC_BASE_HI_0 0 19 regMC_VM_MARC_BASE_HI_1 0 0x5a96 1 0 1 MARC_BASE_HI_1 0 19 regMC_VM_MARC_BASE_HI_2 0 0x5a97 1 0 1 MARC_BASE_HI_2 0 19 regMC_VM_MARC_BASE_HI_3 0 0x5a98 1 0 1 MARC_BASE_HI_3 0 19 regMC_VM_MARC_RELOC_LO_0 0 0x5a99 3 0 1 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 regMC_VM_MARC_RELOC_LO_1 0 0x5a9a 3 0 1 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 regMC_VM_MARC_RELOC_LO_2 0 0x5a9b 3 0 1 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 regMC_VM_MARC_RELOC_LO_3 0 0x5a9c 3 0 1 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 regMC_VM_MARC_RELOC_HI_0 0 0x5a9d 1 0 1 MARC_RELOC_HI_0 0 19 regMC_VM_MARC_RELOC_HI_1 0 0x5a9e 1 0 1 MARC_RELOC_HI_1 0 19 regMC_VM_MARC_RELOC_HI_2 0 0x5a9f 1 0 1 MARC_RELOC_HI_2 0 19 regMC_VM_MARC_RELOC_HI_3 0 0x5aa0 1 0 1 MARC_RELOC_HI_3 0 19 regMC_VM_MARC_LEN_LO_0 0 0x5aa1 1 0 1 MARC_LEN_LO_0 12 31 regMC_VM_MARC_LEN_LO_1 0 0x5aa2 1 0 1 MARC_LEN_LO_1 12 31 regMC_VM_MARC_LEN_LO_2 0 0x5aa3 1 0 1 MARC_LEN_LO_2 12 31 regMC_VM_MARC_LEN_LO_3 0 0x5aa4 1 0 1 MARC_LEN_LO_3 12 31 regMC_VM_MARC_LEN_HI_0 0 0x5aa5 1 0 1 MARC_LEN_HI_0 0 19 regMC_VM_MARC_LEN_HI_1 0 0x5aa6 1 0 1 MARC_LEN_HI_1 0 19 regMC_VM_MARC_LEN_HI_2 0 0x5aa7 1 0 1 MARC_LEN_HI_2 0 19 regMC_VM_MARC_LEN_HI_3 0 0x5aa8 1 0 1 MARC_LEN_HI_3 0 19 regVM_PCIE_ATS_CNTL 0 0x5aab 2 0 1 STU 16 20 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_0 0 0x5aac 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_1 0 0x5aad 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_2 0 0x5aae 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_3 0 0x5aaf 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_4 0 0x5ab0 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_5 0 0x5ab1 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_6 0 0x5ab2 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_7 0 0x5ab3 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_8 0 0x5ab4 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_9 0 0x5ab5 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_10 0 0x5ab6 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_11 0 0x5ab7 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_12 0 0x5ab8 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_13 0 0x5ab9 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_14 0 0x5aba 1 0 1 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_15 0 0x5abb 1 0 1 ATC_ENABLE 31 31 regMC_SHARED_ACTIVE_FCN_ID 0 0x5abc 2 0 1 VFID 0 3 VF 31 31 regMC_VM_XGMI_GPUIOV_ENABLE 0 0x5abd 17 0 1 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_PF 31 31 regMC_VM_FB_OFFSET 0 0x96b 1 0 0 FB_OFFSET 0 23 regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x96c 1 0 0 PHYSICAL_PAGE_NUMBER_LSB 0 31 regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x96d 1 0 0 PHYSICAL_PAGE_NUMBER_MSB 0 3 regMC_VM_STEERING 0 0x96e 1 0 0 DEFAULT_STEERING 0 1 regMC_SHARED_VIRT_RESET_REQ 0 0x96f 2 0 0 VF 0 15 PF 31 31 regMC_MEM_POWER_LS 0 0x970 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0x971 1 0 0 ADDRESS 0 23 regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0x972 1 0 0 ADDRESS 0 23 regMC_VM_APT_CNTL 0 0x973 4 0 0 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 CHECK_IS_LOCAL 2 2 PERMS_GRANTED 3 3 regMC_VM_LOCAL_HBM_ADDRESS_START 0 0x974 1 0 0 ADDRESS 0 23 regMC_VM_LOCAL_HBM_ADDRESS_END 0 0x975 1 0 0 ADDRESS 0 23 regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x976 1 0 0 LOCK 0 0 regUTCL2_CGTT_CLK_CTRL 0 0x977 6 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regMC_VM_XGMI_LFB_CNTL 0 0x978 2 0 0 PF_LFB_REGION 0 3 PF_MAX_REGION 4 7 regMC_VM_XGMI_LFB_SIZE 0 0x979 1 0 0 PF_LFB_SIZE 0 16 regMC_VM_CACHEABLE_DRAM_CNTL 0 0x97a 1 0 0 ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE 0 0 regMC_VM_HOST_MAPPING 0 0x97b 1 0 0 MODE 0 0 regMC_VM_FB_LOCATION_BASE 0 0x980 1 0 0 FB_BASE 0 23 regMC_VM_FB_LOCATION_TOP 0 0x981 1 0 0 FB_TOP 0 23 regMC_VM_AGP_TOP 0 0x982 1 0 0 AGP_TOP 0 23 regMC_VM_AGP_BOT 0 0x983 1 0 0 AGP_BOT 0 23 regMC_VM_AGP_BASE 0 0x984 1 0 0 AGP_BASE 0 23 regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x985 1 0 0 LOGICAL_ADDR 0 29 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x986 1 0 0 LOGICAL_ADDR 0 29 regMC_VM_MX_L1_TLB_CNTL 0 0x987 7 0 0 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 12 ATC_EN 13 13 ixGC_CAC_CNTL 2 0x0 4 0 4294967295 CAC_FORCE_DISABLE 0 0 CAC_THRESHOLD 1 16 CAC_BLOCK_ID 17 22 CAC_SIGNAL_ID 23 30 ixGC_CAC_OVR_SEL 2 0x1 1 0 4294967295 CAC_OVR_SEL 0 31 ixGC_CAC_OVR_VAL 2 0x2 1 0 4294967295 CAC_OVR_VAL 0 31 ixGC_CAC_WEIGHT_BCI_0 2 0x3 2 0 4294967295 WEIGHT_BCI_SIG0 0 15 WEIGHT_BCI_SIG1 16 31 ixGC_CAC_WEIGHT_CB_0 2 0x4 2 0 4294967295 WEIGHT_CB_SIG0 0 15 WEIGHT_CB_SIG1 16 31 ixGC_CAC_WEIGHT_CB_1 2 0x5 2 0 4294967295 WEIGHT_CB_SIG2 0 15 WEIGHT_CB_SIG3 16 31 ixGC_CAC_WEIGHT_CP_0 2 0x8 2 0 4294967295 WEIGHT_CP_SIG0 0 15 WEIGHT_CP_SIG1 16 31 ixGC_CAC_WEIGHT_CP_1 2 0x9 1 0 4294967295 WEIGHT_CP_SIG2 0 15 ixGC_CAC_WEIGHT_DB_0 2 0xa 2 0 4294967295 WEIGHT_DB_SIG0 0 15 WEIGHT_DB_SIG1 16 31 ixGC_CAC_WEIGHT_DB_1 2 0xb 2 0 4294967295 WEIGHT_DB_SIG2 0 15 WEIGHT_DB_SIG3 16 31 ixGC_CAC_WEIGHT_GDS_0 2 0xe 2 0 4294967295 WEIGHT_GDS_SIG0 0 15 WEIGHT_GDS_SIG1 16 31 ixGC_CAC_WEIGHT_GDS_1 2 0xf 2 0 4294967295 WEIGHT_GDS_SIG2 0 15 WEIGHT_GDS_SIG3 16 31 ixGC_CAC_WEIGHT_IA_0 2 0x10 1 0 4294967295 WEIGHT_IA_SIG0 0 15 ixGC_CAC_WEIGHT_LDS_0 2 0x11 2 0 4294967295 WEIGHT_LDS_SIG0 0 15 WEIGHT_LDS_SIG1 16 31 ixGC_CAC_WEIGHT_LDS_1 2 0x12 2 0 4294967295 WEIGHT_LDS_SIG2 0 15 WEIGHT_LDS_SIG3 16 31 ixGC_CAC_WEIGHT_PA_0 2 0x13 2 0 4294967295 WEIGHT_PA_SIG0 0 15 WEIGHT_PA_SIG1 16 31 ixGC_CAC_WEIGHT_PC_0 2 0x14 1 0 4294967295 WEIGHT_PC_SIG0 0 15 ixGC_CAC_WEIGHT_SC_0 2 0x15 1 0 4294967295 WEIGHT_SC_SIG0 0 15 ixGC_CAC_WEIGHT_SPI_0 2 0x16 2 0 4294967295 WEIGHT_SPI_SIG0 0 15 WEIGHT_SPI_SIG1 16 31 ixGC_CAC_WEIGHT_SPI_1 2 0x17 2 0 4294967295 WEIGHT_SPI_SIG2 0 15 WEIGHT_SPI_SIG3 16 31 ixGC_CAC_WEIGHT_SPI_2 2 0x18 2 0 4294967295 WEIGHT_SPI_SIG4 0 15 WEIGHT_SPI_SIG5 16 31 ixGC_CAC_WEIGHT_SQ_0 2 0x1a 2 0 4294967295 WEIGHT_SQ_SIG0 0 15 WEIGHT_SQ_SIG1 16 31 ixGC_CAC_WEIGHT_SQ_1 2 0x1b 2 0 4294967295 WEIGHT_SQ_SIG2 0 15 WEIGHT_SQ_SIG3 16 31 ixGC_CAC_WEIGHT_SQ_2 2 0x1c 2 0 4294967295 WEIGHT_SQ_SIG4 0 15 WEIGHT_SQ_SIG5 16 31 ixGC_CAC_WEIGHT_SQ_3 2 0x1d 2 0 4294967295 WEIGHT_SQ_SIG6 0 15 WEIGHT_SQ_SIG7 16 31 ixGC_CAC_WEIGHT_SQ_4 2 0x1e 1 0 4294967295 WEIGHT_SQ_SIG8 0 15 ixGC_CAC_WEIGHT_SX_0 2 0x1f 1 0 4294967295 WEIGHT_SX_SIG0 0 15 ixGC_CAC_WEIGHT_SXRB_0 2 0x20 1 0 4294967295 WEIGHT_SXRB_SIG0 0 15 ixGC_CAC_WEIGHT_TA_0 2 0x21 1 0 4294967295 WEIGHT_TA_SIG0 0 15 ixGC_CAC_WEIGHT_TCC_0 2 0x22 2 0 4294967295 WEIGHT_TCC_SIG0 0 15 WEIGHT_TCC_SIG1 16 31 ixGC_CAC_WEIGHT_TCC_1 2 0x23 2 0 4294967295 WEIGHT_TCC_SIG2 0 15 WEIGHT_TCC_SIG3 16 31 ixGC_CAC_WEIGHT_TCC_2 2 0x24 1 0 4294967295 WEIGHT_TCC_SIG4 0 15 ixGC_CAC_WEIGHT_TCP_0 2 0x25 2 0 4294967295 WEIGHT_TCP_SIG0 0 15 WEIGHT_TCP_SIG1 16 31 ixGC_CAC_WEIGHT_TCP_1 2 0x26 2 0 4294967295 WEIGHT_TCP_SIG2 0 15 WEIGHT_TCP_SIG3 16 31 ixGC_CAC_WEIGHT_TCP_2 2 0x27 1 0 4294967295 WEIGHT_TCP_SIG4 0 15 ixGC_CAC_WEIGHT_TD_0 2 0x28 2 0 4294967295 WEIGHT_TD_SIG0 0 15 WEIGHT_TD_SIG1 16 31 ixGC_CAC_WEIGHT_TD_1 2 0x29 2 0 4294967295 WEIGHT_TD_SIG2 0 15 WEIGHT_TD_SIG3 16 31 ixGC_CAC_WEIGHT_TD_2 2 0x2a 2 0 4294967295 WEIGHT_TD_SIG4 0 15 WEIGHT_TD_SIG5 16 31 ixGC_CAC_WEIGHT_VGT_0 2 0x2b 2 0 4294967295 WEIGHT_VGT_SIG0 0 15 WEIGHT_VGT_SIG1 16 31 ixGC_CAC_WEIGHT_VGT_1 2 0x2c 1 0 4294967295 WEIGHT_VGT_SIG2 0 15 ixGC_CAC_WEIGHT_WD_0 2 0x2d 1 0 4294967295 WEIGHT_WD_SIG0 0 15 ixGC_CAC_WEIGHT_CU_0 2 0x32 1 0 4294967295 WEIGHT_CU_SIG0 0 15 ixGC_CAC_ACC_BCI0 2 0x42 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB0 2 0x43 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB1 2 0x44 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB2 2 0x45 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CB3 2 0x46 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP0 2 0x4b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP1 2 0x4c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CP2 2 0x4d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB0 2 0x4e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB1 2 0x4f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB2 2 0x50 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_DB3 2 0x51 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS0 2 0x56 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS1 2 0x57 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS2 2 0x58 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_GDS3 2 0x59 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_IA0 2 0x5a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS0 2 0x5b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS1 2 0x5c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS2 2 0x5d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_LDS3 2 0x5e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA0 2 0x5f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PA1 2 0x60 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_PC0 2 0x61 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SC0 2 0x62 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI0 2 0x63 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI1 2 0x64 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI2 2 0x65 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI3 2 0x66 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI4 2 0x67 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SPI5 2 0x68 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_WEIGHT_UTCL2_ATCL2_0 2 0x6f 2 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG0 0 15 WEIGHT_UTCL2_ATCL2_SIG1 16 31 ixGC_CAC_ACC_EA0 2 0x70 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA1 2 0x71 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA2 2 0x72 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA3 2 0x73 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL20 2 0x74 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_EA 2 0x75 2 0 4294967295 OVRRD_SELECT 0 5 OVRRD_VALUE 6 11 ixGC_CAC_OVRD_UTCL2_ATCL2 2 0x76 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_WEIGHT_EA_0 2 0x77 2 0 4294967295 WEIGHT_EA_SIG0 0 15 WEIGHT_EA_SIG1 16 31 ixGC_CAC_WEIGHT_EA_1 2 0x78 2 0 4294967295 WEIGHT_EA_SIG2 0 15 WEIGHT_EA_SIG3 16 31 ixGC_CAC_WEIGHT_RMI_0 2 0x79 1 0 4294967295 WEIGHT_RMI_SIG0 0 15 ixGC_CAC_ACC_RMI0 2 0x7a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_RMI 2 0x7b 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_WEIGHT_UTCL2_ATCL2_1 2 0x7c 2 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG2 0 15 WEIGHT_UTCL2_ATCL2_SIG3 16 31 ixGC_CAC_ACC_UTCL2_ATCL21 2 0x7d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL22 2 0x7e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ATCL23 2 0x7f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA4 2 0x80 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_EA5 2 0x81 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_WEIGHT_EA_2 2 0x82 2 0 4294967295 WEIGHT_EA_SIG4 0 15 WEIGHT_EA_SIG5 16 31 ixGC_CAC_ACC_SQ0_LOWER 2 0x89 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ0_UPPER 2 0x8a 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ1_LOWER 2 0x8b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ1_UPPER 2 0x8c 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ2_LOWER 2 0x8d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ2_UPPER 2 0x8e 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ3_LOWER 2 0x8f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ3_UPPER 2 0x90 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ4_LOWER 2 0x91 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ4_UPPER 2 0x92 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ5_LOWER 2 0x93 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ5_UPPER 2 0x94 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ6_LOWER 2 0x95 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ6_UPPER 2 0x96 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ7_LOWER 2 0x97 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ7_UPPER 2 0x98 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SQ8_LOWER 2 0x99 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SQ8_UPPER 2 0x9a 1 0 4294967295 ACCUMULATOR_39_32 0 7 ixGC_CAC_ACC_SX0 2 0x9b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SXRB0 2 0x9c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_SXRB1 2 0x9d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TA0 2 0x9e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCC0 2 0x9f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCC1 2 0xa0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCC2 2 0xa1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCC3 2 0xa2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCC4 2 0xa3 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP0 2 0xa4 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP1 2 0xa5 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP2 2 0xa6 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP3 2 0xa7 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TCP4 2 0xa8 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD0 2 0xa9 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD1 2 0xaa 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD2 2 0xab 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD3 2 0xac 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD4 2 0xad 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_TD5 2 0xae 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_VGT0 2 0xaf 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_VGT1 2 0xb0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_VGT2 2 0xb1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_WD0 2 0xb2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU0 2 0xba 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU1 2 0xbb 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU2 2 0xbc 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU3 2 0xbd 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU4 2 0xbe 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU5 2 0xbf 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU6 2 0xc0 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU7 2 0xc1 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU8 2 0xc2 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU9 2 0xc3 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU10 2 0xc4 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU11 2 0xc5 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU12 2 0xc6 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_CU13 2 0xc7 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_BCI 2 0xda 2 0 4294967295 OVRRD_SELECT 0 1 OVRRD_VALUE 2 3 ixGC_CAC_OVRD_CB 2 0xdb 2 0 4294967295 OVRRD_SELECT 0 3 OVRRD_VALUE 4 7 ixGC_CAC_OVRD_CP 2 0xdd 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_DB 2 0xde 2 0 4294967295 OVRRD_SELECT 0 3 OVRRD_VALUE 4 7 ixGC_CAC_OVRD_GDS 2 0xe0 2 0 4294967295 OVRRD_SELECT 0 3 OVRRD_VALUE 4 7 ixGC_CAC_OVRD_IA 2 0xe1 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_LDS 2 0xe2 2 0 4294967295 OVRRD_SELECT 0 3 OVRRD_VALUE 4 7 ixGC_CAC_OVRD_PA 2 0xe3 2 0 4294967295 OVRRD_SELECT 0 1 OVRRD_VALUE 2 3 ixGC_CAC_OVRD_PC 2 0xe4 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SC 2 0xe5 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SPI 2 0xe6 2 0 4294967295 OVRRD_SELECT 0 5 OVRRD_VALUE 6 11 ixGC_CAC_OVRD_CU 2 0xe7 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SQ 2 0xe8 2 0 4294967295 OVRRD_SELECT 0 8 OVRRD_VALUE 9 17 ixGC_CAC_OVRD_SX 2 0xe9 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_SXRB 2 0xea 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_TA 2 0xeb 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_OVRD_TCC 2 0xec 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_TCP 2 0xed 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_OVRD_TD 2 0xee 2 0 4294967295 OVRRD_SELECT 0 5 OVRRD_VALUE 6 11 ixGC_CAC_OVRD_VGT 2 0xef 2 0 4294967295 OVRRD_SELECT 0 2 OVRRD_VALUE 3 5 ixGC_CAC_OVRD_WD 2 0xf0 2 0 4294967295 OVRRD_SELECT 0 0 OVRRD_VALUE 1 1 ixGC_CAC_ACC_BCI1 2 0xff 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_WEIGHT_UTCL2_ATCL2_2 2 0x100 1 0 4294967295 WEIGHT_UTCL2_ATCL2_SIG4 0 15 ixGC_CAC_WEIGHT_UTCL2_ROUTER_0 2 0x101 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG0 0 15 WEIGHT_UTCL2_ROUTER_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_1 2 0x102 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG2 0 15 WEIGHT_UTCL2_ROUTER_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_2 2 0x103 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG4 0 15 WEIGHT_UTCL2_ROUTER_SIG5 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_3 2 0x104 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG6 0 15 WEIGHT_UTCL2_ROUTER_SIG7 16 31 ixGC_CAC_WEIGHT_UTCL2_ROUTER_4 2 0x105 2 0 4294967295 WEIGHT_UTCL2_ROUTER_SIG8 0 15 WEIGHT_UTCL2_ROUTER_SIG9 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_0 2 0x106 2 0 4294967295 WEIGHT_UTCL2_VML2_SIG0 0 15 WEIGHT_UTCL2_VML2_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_1 2 0x107 2 0 4294967295 WEIGHT_UTCL2_VML2_SIG2 0 15 WEIGHT_UTCL2_VML2_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_VML2_2 2 0x108 1 0 4294967295 WEIGHT_UTCL2_VML2_SIG4 0 15 ixGC_CAC_ACC_UTCL2_ATCL24 2 0x109 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER0 2 0x10a 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER1 2 0x10b 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER2 2 0x10c 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER3 2 0x10d 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER4 2 0x10e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER5 2 0x10f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER6 2 0x110 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER7 2 0x111 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER8 2 0x112 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_ROUTER9 2 0x113 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML20 2 0x114 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML21 2 0x115 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML22 2 0x116 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML23 2 0x117 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_VML24 2 0x118 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_UTCL2_ROUTER 2 0x119 2 0 4294967295 OVRRD_SELECT 0 9 OVRRD_VALUE 10 19 ixGC_CAC_OVRD_UTCL2_VML2 2 0x11a 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixGC_CAC_WEIGHT_UTCL2_WALKER_0 2 0x11b 2 0 4294967295 WEIGHT_UTCL2_WALKER_SIG0 0 15 WEIGHT_UTCL2_WALKER_SIG1 16 31 ixGC_CAC_WEIGHT_UTCL2_WALKER_1 2 0x11c 2 0 4294967295 WEIGHT_UTCL2_WALKER_SIG2 0 15 WEIGHT_UTCL2_WALKER_SIG3 16 31 ixGC_CAC_WEIGHT_UTCL2_WALKER_2 2 0x11d 1 0 4294967295 WEIGHT_UTCL2_WALKER_SIG4 0 15 ixGC_CAC_ACC_UTCL2_WALKER0 2 0x11e 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER1 2 0x11f 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER2 2 0x120 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER3 2 0x121 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_ACC_UTCL2_WALKER4 2 0x122 1 0 4294967295 ACCUMULATOR_31_0 0 31 ixGC_CAC_OVRD_UTCL2_WALKER 2 0x123 2 0 4294967295 OVRRD_SELECT 0 4 OVRRD_VALUE 5 9 ixEDC_STALL_PATTERN_1_2 2 0x130 2 0 4294967295 EDC_STALL_PATTERN_1 0 14 EDC_STALL_PATTERN_2 16 30 ixEDC_STALL_PATTERN_3_4 2 0x131 2 0 4294967295 EDC_STALL_PATTERN_3 0 14 EDC_STALL_PATTERN_4 16 30 ixEDC_STALL_PATTERN_5_6 2 0x132 2 0 4294967295 EDC_STALL_PATTERN_5 0 14 EDC_STALL_PATTERN_6 16 30 ixEDC_STALL_PATTERN_7 2 0x133 1 0 4294967295 EDC_STALL_PATTERN_7 0 14 ixPCC_STALL_PATTERN_1_2 2 0x134 2 0 4294967295 PCC_STALL_PATTERN_1 0 14 PCC_STALL_PATTERN_2 16 30 ixPCC_STALL_PATTERN_3_4 2 0x135 2 0 4294967295 PCC_STALL_PATTERN_3 0 14 PCC_STALL_PATTERN_4 16 30 ixPCC_STALL_PATTERN_5_6 2 0x136 2 0 4294967295 PCC_STALL_PATTERN_5 0 14 PCC_STALL_PATTERN_6 16 30 ixPCC_STALL_PATTERN_7 2 0x137 1 0 4294967295 PCC_STALL_PATTERN_7 0 14 ixPCC_THROT_REINCR_FIRST_PATN_1_8 2 0x138 8 0 4294967295 FIRST_PATTERN_1 0 2 FIRST_PATTERN_2 4 6 FIRST_PATTERN_3 8 10 FIRST_PATTERN_4 12 14 FIRST_PATTERN_5 16 18 FIRST_PATTERN_6 20 22 FIRST_PATTERN_7 24 26 FIRST_PATTERN_8 28 30 ixPCC_THROT_REINCR_FIRST_PATN_9_16 2 0x139 8 0 4294967295 FIRST_PATTERN_9 0 2 FIRST_PATTERN_10 4 6 FIRST_PATTERN_11 8 10 FIRST_PATTERN_12 12 14 FIRST_PATTERN_13 16 18 FIRST_PATTERN_14 20 22 FIRST_PATTERN_15 24 26 FIRST_PATTERN_16 28 30 ixPCC_THROT_REINCR_FIRST_PATN_17_20 2 0x140 4 0 4294967295 FIRST_PATTERN_17 0 2 FIRST_PATTERN_18 4 6 FIRST_PATTERN_19 8 10 FIRST_PATTERN_20 12 14 ixPCC_THROT_DECR_FIRST_PATN_1_4 2 0x141 4 0 4294967295 FIRST_PATTERN_1 0 4 FIRST_PATTERN_2 8 12 FIRST_PATTERN_3 16 20 FIRST_PATTERN_4 24 28 ixPCC_THROT_DECR_FIRST_PATN_5_7 2 0x142 3 0 4294967295 FIRST_PATTERN_5 0 4 FIRST_PATTERN_6 8 12 FIRST_PATTERN_7 16 20 ixPWRBRK_STALL_PATTERN_CTRL 2 0x143 4 0 4294967295 PWRBRK_STEP_INTERVAL 0 9 PWRBRK_BEGIN_STEP 10 14 PWRBRK_END_STEP 15 19 PWRBRK_THROTTLE_PATTERN_BIT_NUMS 20 23 ixPWRBRK_STALL_PATTERN_1_2 2 0x144 2 0 4294967295 PWRBRK_STALL_PATTERN_1 0 14 PWRBRK_STALL_PATTERN_2 16 30 ixPWRBRK_STALL_PATTERN_3_4 2 0x145 2 0 4294967295 PWRBRK_STALL_PATTERN_3 0 14 PWRBRK_STALL_PATTERN_4 16 30 ixPWRBRK_STALL_PATTERN_5_6 2 0x146 2 0 4294967295 PWRBRK_STALL_PATTERN_5 0 14 PWRBRK_STALL_PATTERN_6 16 30 ixPWRBRK_STALL_PATTERN_7 2 0x147 1 0 4294967295 PWRBRK_STALL_PATTERN_7 0 14 ixPCC_PWRBRK_HYSTERESIS_CTRL 2 0x148 1 0 4294967295 PWRBRK_MAX_HYSTERESIS 0 7 ixFIXED_PATTERN_PERF_COUNTER_CTRL 2 0x15f 2 0 4294967295 FIXED_PATTERN_PERF_COUNTER_EN 0 0 FIXED_PATTERN_LOG_INDEX 1 5 ixFIXED_PATTERN_PERF_COUNTER_1 2 0x160 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_2 2 0x161 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_3 2 0x162 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_4 2 0x163 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_5 2 0x164 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_6 2 0x165 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_7 2 0x166 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_8 2 0x167 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_9 2 0x168 1 0 4294967295 PERF_COUNTER 0 16 ixFIXED_PATTERN_PERF_COUNTER_10 2 0x169 1 0 4294967295 PERF_COUNTER 0 16 ixSE_CAC_CNTL 2 0x0 4 0 4294967295 CAC_FORCE_DISABLE 0 0 CAC_THRESHOLD 1 16 CAC_BLOCK_ID 17 22 CAC_SIGNAL_ID 23 30 ixSE_CAC_OVR_SEL 2 0x1 1 0 4294967295 CAC_OVR_SEL 0 31 ixSE_CAC_OVR_VAL 2 0x2 1 0 4294967295 CAC_OVR_VAL 0 31 ixSQ_DEBUG_STS_LOCAL 2 0x8 2 0 4294967295 BUSY 0 0 WAVE_LEVEL 4 9 ixSQ_DEBUG_CTRL_LOCAL 2 0x9 3 0 4294967295 UNUSED 0 7 PERF_SEL_INSTS_VALU_MFMA_NON_WAVE 8 8 PERF_SEL_INSTS_VALU_MFMA_MOPS_NON_WAVE 9 9 ixSQ_WAVE_VALID_AND_IDLE 2 0xa 1 0 4294967295 WAVE_SLOT 0 31 ixSQ_WAVE_MODE 2 0x11 13 0 4294967295 FP_ROUND 0 3 FP_DENORM 4 7 DX10_CLAMP 8 8 IEEE 9 9 LOD_CLAMPED 10 10 EXCP_EN 12 20 FP16_OVFL 23 23 POPS_PACKER0 24 24 POPS_PACKER1 25 25 DISABLE_PERF 26 26 GPR_IDX_EN 27 27 VSKIP 28 28 CSP 29 31 ixSQ_WAVE_STATUS 2 0x12 21 0 4294967295 SCC 0 0 SPI_PRIO 1 2 USER_PRIO 3 4 PRIV 5 5 TRAP_EN 6 6 TTRACE_EN 7 7 EXPORT_RDY 8 8 EXECZ 9 9 VCCZ 10 10 IN_TG 11 11 IN_BARRIER 12 12 HALT 13 13 TRAP 14 14 TTRACE_CU_EN 15 15 VALID 16 16 ECC_ERR 17 17 SKIP_EXPORT 18 18 PERF_EN 19 19 ALLOW_REPLAY 22 22 FATAL_HALT 23 23 MUST_EXPORT 27 27 ixSQ_WAVE_TRAPSTS 2 0x13 7 0 4294967295 EXCP 0 8 SAVECTX 10 10 ILLEGAL_INST 11 11 EXCP_HI 12 14 EXCP_CYCLE 16 21 XNACK_ERROR 28 28 DP_RATE 29 31 ixSQ_WAVE_HW_ID 2 0x14 11 0 4294967295 WAVE_ID 0 3 SIMD_ID 4 5 PIPE_ID 6 7 CU_ID 8 11 SH_ID 12 12 SE_ID 13 15 TG_ID 16 19 VM_ID 20 23 QUEUE_ID 24 26 STATE_ID 27 29 ME_ID 30 31 ixSQ_WAVE_GPR_ALLOC 2 0x15 5 0 4294967295 VGPR_BASE 0 5 VGPR_SIZE 6 11 ACCV_OFFSET 12 17 SGPR_BASE 18 23 SGPR_SIZE 24 27 ixSQ_WAVE_LDS_ALLOC 2 0x16 2 0 4294967295 LDS_BASE 0 7 LDS_SIZE 12 20 ixSQ_WAVE_IB_STS 2 0x17 7 0 4294967295 VM_CNT 0 3 EXP_CNT 4 6 LGKM_CNT 8 11 VALU_CNT 12 14 FIRST_REPLAY 15 15 RCNT 16 20 VM_CNT_HI 22 23 ixSQ_WAVE_PC_LO 2 0x18 1 0 4294967295 PC_LO 0 31 ixSQ_WAVE_PC_HI 2 0x19 1 0 4294967295 PC_HI 0 15 ixSQ_WAVE_INST_DW0 2 0x1a 1 0 4294967295 INST_DW0 0 31 ixSQ_WAVE_INST_DW1 2 0x1b 1 0 4294967295 INST_DW1 0 31 ixSQ_WAVE_IB_DBG0 2 0x1c 13 0 4294967295 IBUF_ST 0 2 PC_INVALID 3 3 NEED_NEXT_DW 4 4 NO_PREFETCH_CNT 5 7 IBUF_RPTR 8 9 IBUF_WPTR 10 11 INST_STR_ST 16 19 ECC_ST 24 25 IS_HYB 26 26 HYB_CNT 27 28 KILL 29 29 NEED_KILL_IFETCH 30 30 NO_PREFETCH_CNT_HI 31 31 ixSQ_WAVE_IB_DBG1 2 0x1d 7 0 4294967295 IXNACK 0 0 XNACK 1 1 TA_NEED_RESET 2 2 XCNT 4 8 QCNT 11 15 RCNT 18 22 MISC_CNT 25 31 ixSQ_WAVE_FLUSH_IB 2 0x1e 1 0 4294967295 UNUSED 0 31 ixSQ_WAVE_TTMP0 2 0x26c 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP1 2 0x26d 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP3 2 0x26f 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP4 2 0x270 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP5 2 0x271 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP6 2 0x272 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP7 2 0x273 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP8 2 0x274 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP9 2 0x275 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP10 2 0x276 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP11 2 0x277 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP12 2 0x278 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP13 2 0x279 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP14 2 0x27a 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP15 2 0x27b 1 0 4294967295 DATA 0 31 ixSQ_WAVE_M0 2 0x27c 1 0 4294967295 M0 0 31 ixSQ_WAVE_EXEC_LO 2 0x27e 1 0 4294967295 EXEC_LO 0 31 ixSQ_WAVE_EXEC_HI 2 0x27f 1 0 4294967295 EXEC_HI 0 31 ixSQ_INTERRUPT_WORD_AUTO_CTXID 2 0x20c0 11 0 4294967295 THREAD_TRACE 0 0 WLT 1 1 THREAD_TRACE_BUF_FULL 2 2 REG_TIMESTAMP 3 3 CMD_TIMESTAMP 4 4 HOST_CMD_OVERFLOW 5 5 HOST_REG_OVERFLOW 6 6 IMMED_OVERFLOW 7 7 THREAD_TRACE_UTC_ERROR 8 8 SE_ID 24 25 ENCODING 26 27 ixSQ_INTERRUPT_WORD_AUTO_HI 2 0x20c0 2 0 4294967295 SE_ID 8 9 ENCODING 10 11 ixSQ_INTERRUPT_WORD_AUTO_LO 2 0x20c0 9 0 4294967295 THREAD_TRACE 0 0 WLT 1 1 THREAD_TRACE_BUF_FULL 2 2 REG_TIMESTAMP 3 3 CMD_TIMESTAMP 4 4 HOST_CMD_OVERFLOW 5 5 HOST_REG_OVERFLOW 6 6 IMMED_OVERFLOW 7 7 THREAD_TRACE_UTC_ERROR 8 8 ixSQ_INTERRUPT_WORD_CMN_CTXID 2 0x20c0 2 0 4294967295 SE_ID 24 25 ENCODING 26 27 ixSQ_INTERRUPT_WORD_CMN_HI 2 0x20c0 2 0 4294967295 SE_ID 8 9 ENCODING 10 11 ixSQ_INTERRUPT_WORD_WAVE_CTXID 2 0x20c0 8 0 4294967295 DATA 0 11 SH_ID 12 12 PRIV 13 13 WAVE_ID 14 17 SIMD_ID 18 19 CU_ID 20 23 SE_ID 24 25 ENCODING 26 27 ixSQ_INTERRUPT_WORD_WAVE_HI 2 0x20c0 4 0 4294967295 CU_ID 0 3 VM_ID 4 7 SE_ID 8 9 ENCODING 10 11 ixSQ_INTERRUPT_WORD_WAVE_LO 2 0x20c0 5 0 4294967295 DATA 0 23 SH_ID 24 24 PRIV 25 25 WAVE_ID 26 29 SIMD_ID 30 31