2504 mmCB_BLEND_RED 0 0xa105 1 0 4294967295 BLEND_RED 0 31 mmCB_BLEND_GREEN 0 0xa106 1 0 4294967295 BLEND_GREEN 0 31 mmCB_BLEND_BLUE 0 0xa107 1 0 4294967295 BLEND_BLUE 0 31 mmCB_BLEND_ALPHA 0 0xa108 1 0 4294967295 BLEND_ALPHA 0 31 mmCB_COLOR_CONTROL 0 0xa202 3 0 4294967295 DEGAMMA_ENABLE 3 3 MODE 4 6 ROP3 16 23 mmCB_BLEND0_CONTROL 0 0xa1e0 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND1_CONTROL 0 0xa1e1 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND2_CONTROL 0 0xa1e2 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND3_CONTROL 0 0xa1e3 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND4_CONTROL 0 0xa1e4 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND5_CONTROL 0 0xa1e5 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND6_CONTROL 0 0xa1e6 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_BLEND7_CONTROL 0 0xa1e7 9 0 4294967295 COLOR_SRCBLEND 0 4 COLOR_COMB_FCN 5 7 COLOR_DESTBLEND 8 12 ALPHA_SRCBLEND 16 20 ALPHA_COMB_FCN 21 23 ALPHA_DESTBLEND 24 28 SEPARATE_ALPHA_BLEND 29 29 ENABLE 30 30 DISABLE_ROP3 31 31 mmCB_COLOR0_BASE 0 0xa318 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR1_BASE 0 0xa327 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR2_BASE 0 0xa336 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR3_BASE 0 0xa345 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR4_BASE 0 0xa354 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR5_BASE 0 0xa363 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR6_BASE 0 0xa372 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR7_BASE 0 0xa381 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR0_PITCH 0 0xa319 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR1_PITCH 0 0xa328 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR2_PITCH 0 0xa337 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR3_PITCH 0 0xa346 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR4_PITCH 0 0xa355 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR5_PITCH 0 0xa364 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR6_PITCH 0 0xa373 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR7_PITCH 0 0xa382 2 0 4294967295 TILE_MAX 0 10 FMASK_TILE_MAX 20 30 mmCB_COLOR0_SLICE 0 0xa31a 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR1_SLICE 0 0xa329 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR2_SLICE 0 0xa338 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR3_SLICE 0 0xa347 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR4_SLICE 0 0xa356 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR5_SLICE 0 0xa365 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR6_SLICE 0 0xa374 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR7_SLICE 0 0xa383 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR0_VIEW 0 0xa31b 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR1_VIEW 0 0xa32a 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR2_VIEW 0 0xa339 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR3_VIEW 0 0xa348 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR4_VIEW 0 0xa357 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR5_VIEW 0 0xa366 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR6_VIEW 0 0xa375 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR7_VIEW 0 0xa384 2 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 mmCB_COLOR0_INFO 0 0xa31c 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR1_INFO 0 0xa32b 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR2_INFO 0 0xa33a 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR3_INFO 0 0xa349 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR4_INFO 0 0xa358 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR5_INFO 0 0xa367 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR6_INFO 0 0xa376 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR7_INFO 0 0xa385 15 0 4294967295 ENDIAN 0 1 FORMAT 2 6 LINEAR_GENERAL 7 7 NUMBER_TYPE 8 10 COMP_SWAP 11 12 FAST_CLEAR 13 13 COMPRESSION 14 14 BLEND_CLAMP 15 15 BLEND_BYPASS 16 16 SIMPLE_FLOAT 17 17 ROUND_MODE 18 18 CMASK_IS_LINEAR 19 19 BLEND_OPT_DONT_RD_DST 20 22 BLEND_OPT_DISCARD_PIXEL 23 25 FMASK_COMPRESSION_DISABLE 26 26 mmCB_COLOR0_ATTRIB 0 0xa31d 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR1_ATTRIB 0 0xa32c 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR2_ATTRIB 0 0xa33b 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR3_ATTRIB 0 0xa34a 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR4_ATTRIB 0 0xa359 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR5_ATTRIB 0 0xa368 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR6_ATTRIB 0 0xa377 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR7_ATTRIB 0 0xa386 6 0 4294967295 TILE_MODE_INDEX 0 4 FMASK_TILE_MODE_INDEX 5 9 FMASK_BANK_HEIGHT 10 11 NUM_SAMPLES 12 14 NUM_FRAGMENTS 15 16 FORCE_DST_ALPHA_1 17 17 mmCB_COLOR0_CMASK 0 0xa31f 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR1_CMASK 0 0xa32e 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR2_CMASK 0 0xa33d 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR3_CMASK 0 0xa34c 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR4_CMASK 0 0xa35b 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR5_CMASK 0 0xa36a 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR6_CMASK 0 0xa379 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR7_CMASK 0 0xa388 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR0_CMASK_SLICE 0 0xa320 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR1_CMASK_SLICE 0 0xa32f 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR2_CMASK_SLICE 0 0xa33e 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR3_CMASK_SLICE 0 0xa34d 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR4_CMASK_SLICE 0 0xa35c 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR5_CMASK_SLICE 0 0xa36b 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR6_CMASK_SLICE 0 0xa37a 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR7_CMASK_SLICE 0 0xa389 1 0 4294967295 TILE_MAX 0 13 mmCB_COLOR0_FMASK 0 0xa321 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR1_FMASK 0 0xa330 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR2_FMASK 0 0xa33f 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR3_FMASK 0 0xa34e 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR4_FMASK 0 0xa35d 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR5_FMASK 0 0xa36c 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR6_FMASK 0 0xa37b 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR7_FMASK 0 0xa38a 1 0 4294967295 BASE_256B 0 31 mmCB_COLOR0_FMASK_SLICE 0 0xa322 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR1_FMASK_SLICE 0 0xa331 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR2_FMASK_SLICE 0 0xa340 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR3_FMASK_SLICE 0 0xa34f 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR4_FMASK_SLICE 0 0xa35e 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR5_FMASK_SLICE 0 0xa36d 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR6_FMASK_SLICE 0 0xa37c 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR7_FMASK_SLICE 0 0xa38b 1 0 4294967295 TILE_MAX 0 21 mmCB_COLOR0_CLEAR_WORD0 0 0xa323 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR1_CLEAR_WORD0 0 0xa332 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR2_CLEAR_WORD0 0 0xa341 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR3_CLEAR_WORD0 0 0xa350 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR4_CLEAR_WORD0 0 0xa35f 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR5_CLEAR_WORD0 0 0xa36e 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR6_CLEAR_WORD0 0 0xa37d 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR7_CLEAR_WORD0 0 0xa38c 1 0 4294967295 CLEAR_WORD0 0 31 mmCB_COLOR0_CLEAR_WORD1 0 0xa324 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR1_CLEAR_WORD1 0 0xa333 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR2_CLEAR_WORD1 0 0xa342 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR3_CLEAR_WORD1 0 0xa351 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR4_CLEAR_WORD1 0 0xa360 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR5_CLEAR_WORD1 0 0xa36f 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR6_CLEAR_WORD1 0 0xa37e 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_COLOR7_CLEAR_WORD1 0 0xa38d 1 0 4294967295 CLEAR_WORD1 0 31 mmCB_TARGET_MASK 0 0xa08e 8 0 4294967295 TARGET0_ENABLE 0 3 TARGET1_ENABLE 4 7 TARGET2_ENABLE 8 11 TARGET3_ENABLE 12 15 TARGET4_ENABLE 16 19 TARGET5_ENABLE 20 23 TARGET6_ENABLE 24 27 TARGET7_ENABLE 28 31 mmCB_SHADER_MASK 0 0xa08f 8 0 4294967295 OUTPUT0_ENABLE 0 3 OUTPUT1_ENABLE 4 7 OUTPUT2_ENABLE 8 11 OUTPUT3_ENABLE 12 15 OUTPUT4_ENABLE 16 19 OUTPUT5_ENABLE 20 23 OUTPUT6_ENABLE 24 27 OUTPUT7_ENABLE 28 31 mmCB_HW_CONTROL 0 0x2684 18 0 4294967295 CM_CACHE_EVICT_POINT 0 3 FC_CACHE_EVICT_POINT 6 9 CC_CACHE_EVICT_POINT 12 15 ALLOW_MRT_WITH_DUAL_SOURCE 16 16 DISABLE_INTNORM_LE11BPC_CLAMPING 18 18 FORCE_NEEDS_DST 19 19 FORCE_ALWAYS_TOGGLE 20 20 DISABLE_BLEND_OPT_RESULT_EQ_DEST 21 21 DISABLE_FULL_WRITE_MASK 22 22 DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG 23 23 DISABLE_BLEND_OPT_DONT_RD_DST 24 24 DISABLE_BLEND_OPT_BYPASS 25 25 DISABLE_BLEND_OPT_DISCARD_PIXEL 26 26 DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED 27 27 PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT 28 28 PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT 29 29 DISABLE_CC_IB_SERIALIZER_STATE_OPT 30 30 DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE 31 31 mmCB_HW_CONTROL_1 0 0x2685 5 0 4294967295 CM_CACHE_NUM_TAGS 0 4 FC_CACHE_NUM_TAGS 5 10 CC_CACHE_NUM_TAGS 11 16 CM_TILE_FIFO_DEPTH 17 25 CHICKEN_BITS 26 31 mmCB_HW_CONTROL_2 0 0x2686 4 0 4294967295 CC_EVEN_ODD_FIFO_DEPTH 0 7 FC_RDLAT_TILE_FIFO_DEPTH 8 14 FC_RDLAT_QUAD_FIFO_DEPTH 15 22 CHICKEN_BITS 24 31 mmCB_HW_CONTROL_3 0 0x2683 1 0 4294967295 DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL 0 0 mmCB_PERFCOUNTER_FILTER 0 0xdc00 12 0 4294967295 OP_FILTER_ENABLE 0 0 OP_FILTER_SEL 1 3 FORMAT_FILTER_ENABLE 4 4 FORMAT_FILTER_SEL 5 9 CLEAR_FILTER_ENABLE 10 10 CLEAR_FILTER_SEL 11 11 MRT_FILTER_ENABLE 12 12 MRT_FILTER_SEL 13 15 NUM_SAMPLES_FILTER_ENABLE 17 17 NUM_SAMPLES_FILTER_SEL 18 20 NUM_FRAGMENTS_FILTER_ENABLE 21 21 NUM_FRAGMENTS_FILTER_SEL 22 23 mmCB_PERFCOUNTER0_SELECT 0 0xdc01 5 0 4294967295 PERF_SEL 0 8 PERF_SEL1 10 18 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmCB_PERFCOUNTER0_SELECT1 0 0xdc02 4 0 4294967295 PERF_SEL2 0 8 PERF_SEL3 10 18 PERF_MODE3 24 27 PERF_MODE2 28 31 mmCB_PERFCOUNTER1_SELECT 0 0xdc03 2 0 4294967295 PERF_SEL 0 8 PERF_MODE 28 31 mmCB_PERFCOUNTER2_SELECT 0 0xdc04 2 0 4294967295 PERF_SEL 0 8 PERF_MODE 28 31 mmCB_PERFCOUNTER3_SELECT 0 0xdc05 2 0 4294967295 PERF_SEL 0 8 PERF_MODE 28 31 mmCB_PERFCOUNTER0_LO 0 0xd406 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER1_LO 0 0xd408 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER2_LO 0 0xd40a 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER3_LO 0 0xd40c 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCB_PERFCOUNTER0_HI 0 0xd407 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER1_HI 0 0xd409 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER2_HI 0 0xd40b 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCB_PERFCOUNTER3_HI 0 0xd40d 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCB_CGTT_SCLK_CTRL 0 0xf0a8 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCB_DEBUG_BUS_1 0 0x2699 0 0 4294967295 mmCB_DEBUG_BUS_2 0 0x269a 0 0 4294967295 mmCB_DEBUG_BUS_3 0 0x269b 0 0 4294967295 mmCB_DEBUG_BUS_4 0 0x269c 0 0 4294967295 mmCB_DEBUG_BUS_5 0 0x269d 0 0 4294967295 mmCB_DEBUG_BUS_6 0 0x269e 0 0 4294967295 mmCB_DEBUG_BUS_7 0 0x269f 0 0 4294967295 mmCB_DEBUG_BUS_8 0 0x26a0 0 0 4294967295 mmCB_DEBUG_BUS_9 0 0x26a1 0 0 4294967295 mmCB_DEBUG_BUS_10 0 0x26a2 0 0 4294967295 mmCB_DEBUG_BUS_11 0 0x26a3 0 0 4294967295 mmCB_DEBUG_BUS_12 0 0x26a4 0 0 4294967295 mmCB_DEBUG_BUS_13 0 0x26a5 12 0 4294967295 TILE_INTFC_BUSY 0 0 MU_BUSY 1 1 TQ_BUSY 2 2 AC_BUSY 3 3 CRW_BUSY 4 4 CACHE_CTRL_BUSY 5 5 MC_WR_PENDING 6 6 FC_WR_PENDING 7 7 FC_RD_PENDING 8 8 EVICT_PENDING 9 9 LAST_RD_ARB_WINNER 10 10 MU_STATE 11 18 mmCB_DEBUG_BUS_14 0 0x26a6 9 0 4294967295 TILE_RETIREMENT_BUSY 0 0 FOP_BUSY 1 1 LAT_BUSY 2 2 CACHE_CTL_BUSY 3 3 ADDR_BUSY 4 4 MERGE_BUSY 5 5 QUAD_BUSY 6 6 TILE_BUSY 7 7 CLEAR_BUSY 8 8 mmCB_DEBUG_BUS_15 0 0x26a7 8 0 4294967295 SURF_SYNC_STATE 0 1 SURF_SYNC_START 2 2 SF_BUSY 3 3 CS_BUSY 4 4 RB_BUSY 5 5 DS_BUSY 6 6 TB_BUSY 7 7 IB_BUSY 8 8 mmCB_DEBUG_BUS_16 0 0x26a8 7 0 4294967295 MC_RDREQ_CREDITS 0 5 LAST_RD_GRANT_VEC 6 9 MC_WRREQ_CREDITS 10 15 LAST_WR_GRANT_VEC 16 19 CC_WRREQ_FIFO_EMPTY 20 20 FC_WRREQ_FIFO_EMPTY 21 21 CM_WRREQ_FIFO_EMPTY 22 22 mmCB_DEBUG_BUS_17 0 0x26a9 8 0 4294967295 CM_BUSY 0 0 FC_BUSY 1 1 CC_BUSY 2 2 BB_BUSY 3 3 MA_BUSY 4 4 CORE_SCLK_VLD 5 5 REG_SCLK1_VLD 6 6 REG_SCLK0_VLD 7 7 mmCB_DEBUG_BUS_18 0 0x26aa 1 0 4294967295 NOT_USED 0 23 mmCP_DFY_CNTL 0 0x3020 3 0 4294967295 POLICY 8 9 VOL 10 10 ATC 11 11 mmCP_DFY_STAT 0 0x3021 3 0 4294967295 BURST_COUNT 0 15 TAGS_PENDING 16 23 BUSY 31 31 mmCP_DFY_ADDR_HI 0 0x3022 1 0 4294967295 ADDR_HI 0 31 mmCP_DFY_ADDR_LO 0 0x3023 1 0 4294967295 ADDR_LO 5 31 mmCP_DFY_DATA_0 0 0x3024 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_1 0 0x3025 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_2 0 0x3026 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_3 0 0x3027 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_4 0 0x3028 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_5 0 0x3029 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_6 0 0x302a 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_7 0 0x302b 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_8 0 0x302c 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_9 0 0x302d 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_10 0 0x302e 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_11 0 0x302f 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_12 0 0x3030 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_13 0 0x3031 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_14 0 0x3032 1 0 4294967295 DATA 0 31 mmCP_DFY_DATA_15 0 0x3033 1 0 4294967295 DATA 0 31 mmCP_RB0_BASE 0 0x3040 1 0 4294967295 RB_BASE 0 31 mmCP_RB0_BASE_HI 0 0x30b1 1 0 4294967295 RB_BASE_HI 0 7 mmCP_RB_BASE 0 0x3040 1 0 4294967295 RB_BASE 0 31 mmCP_RB1_BASE 0 0x3060 1 0 4294967295 RB_BASE 0 31 mmCP_RB1_BASE_HI 0 0x30b2 1 0 4294967295 RB_BASE_HI 0 7 mmCP_RB2_BASE 0 0x3065 1 0 4294967295 RB_BASE 0 31 mmCP_RB0_CNTL 0 0x3041 9 0 4294967295 RB_BUFSZ 0 5 RB_BLKSZ 8 13 BUF_SWAP 16 17 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 mmCP_RB_CNTL 0 0x3041 9 0 4294967295 RB_BUFSZ 0 5 RB_BLKSZ 8 13 BUF_SWAP 16 17 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 mmCP_RB1_CNTL 0 0x3061 8 0 4294967295 RB_BUFSZ 0 5 RB_BLKSZ 8 13 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 mmCP_RB2_CNTL 0 0x3066 8 0 4294967295 RB_BUFSZ 0 5 RB_BLKSZ 8 13 MIN_AVAILSZ 20 21 MIN_IB_AVAILSZ 22 23 CACHE_POLICY 24 25 RB_VOLATILE 26 26 RB_NO_UPDATE 27 27 RB_RPTR_WR_ENA 31 31 mmCP_RB_RPTR_WR 0 0x3042 1 0 4294967295 RB_RPTR_WR 0 19 mmCP_RB0_RPTR_ADDR 0 0x3043 2 0 4294967295 RB_RPTR_SWAP 0 1 RB_RPTR_ADDR 2 31 mmCP_RB_RPTR_ADDR 0 0x3043 2 0 4294967295 RB_RPTR_SWAP 0 1 RB_RPTR_ADDR 2 31 mmCP_RB1_RPTR_ADDR 0 0x3062 2 0 4294967295 RB_RPTR_SWAP 0 1 RB_RPTR_ADDR 2 31 mmCP_RB2_RPTR_ADDR 0 0x3067 2 0 4294967295 RB_RPTR_SWAP 0 1 RB_RPTR_ADDR 2 31 mmCP_RB0_RPTR_ADDR_HI 0 0x3044 1 0 4294967295 RB_RPTR_ADDR_HI 0 15 mmCP_RB_RPTR_ADDR_HI 0 0x3044 1 0 4294967295 RB_RPTR_ADDR_HI 0 15 mmCP_RB1_RPTR_ADDR_HI 0 0x3063 1 0 4294967295 RB_RPTR_ADDR_HI 0 15 mmCP_RB2_RPTR_ADDR_HI 0 0x3068 1 0 4294967295 RB_RPTR_ADDR_HI 0 15 mmCP_RB0_WPTR 0 0x3045 1 0 4294967295 RB_WPTR 0 19 mmCP_RB_WPTR 0 0x3045 1 0 4294967295 RB_WPTR 0 19 mmCP_RB1_WPTR 0 0x3064 1 0 4294967295 RB_WPTR 0 19 mmCP_RB2_WPTR 0 0x3069 1 0 4294967295 RB_WPTR 0 19 mmCP_RB_WPTR_POLL_ADDR_LO 0 0x3046 1 0 4294967295 OBSOLETE 2 31 mmCP_RB_WPTR_POLL_ADDR_HI 0 0x3047 1 0 4294967295 OBSOLETE 0 7 mmGC_PRIV_MODE 0 0x3048 0 0 4294967295 mmCP_INT_CNTL 0 0x3049 12 0 4294967295 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_CNTL_RING0 0 0x306a 12 0 4294967295 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_CNTL_RING1 0 0x306b 12 0 4294967295 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_CNTL_RING2 0 0x306c 12 0 4294967295 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 CNTX_BUSY_INT_ENABLE 19 19 CNTX_EMPTY_INT_ENABLE 20 20 PRIV_INSTR_INT_ENABLE 22 22 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_INT_STATUS 0 0x304a 12 0 4294967295 CP_ECC_ERROR_INT_STAT 14 14 WRM_POLL_TIMEOUT_INT_STAT 17 17 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_INT_STATUS_RING0 0 0x306d 12 0 4294967295 CP_ECC_ERROR_INT_STAT 14 14 WRM_POLL_TIMEOUT_INT_STAT 17 17 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_INT_STATUS_RING1 0 0x306e 12 0 4294967295 CP_ECC_ERROR_INT_STAT 14 14 WRM_POLL_TIMEOUT_INT_STAT 17 17 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_INT_STATUS_RING2 0 0x306f 12 0 4294967295 CP_ECC_ERROR_INT_STAT 14 14 WRM_POLL_TIMEOUT_INT_STAT 17 17 CNTX_BUSY_INT_STAT 19 19 CNTX_EMPTY_INT_STAT 20 20 PRIV_INSTR_INT_STAT 22 22 PRIV_REG_INT_STAT 23 23 OPCODE_ERROR_INT_STAT 24 24 TIME_STAMP_INT_STAT 26 26 RESERVED_BIT_ERROR_INT_STAT 27 27 GENERIC2_INT_STAT 29 29 GENERIC1_INT_STAT 30 30 GENERIC0_INT_STAT 31 31 mmCP_DEVICE_ID 0 0x304b 1 0 4294967295 DEVICE_ID 0 7 mmCP_RING_PRIORITY_CNTS 0 0x304c 4 0 4294967295 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME0_PIPE_PRIORITY_CNTS 0 0x304c 4 0 4294967295 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_RING0_PRIORITY 0 0x304d 1 0 4294967295 PRIORITY 0 1 mmCP_ME0_PIPE0_PRIORITY 0 0x304d 1 0 4294967295 PRIORITY 0 1 mmCP_RING1_PRIORITY 0 0x304e 1 0 4294967295 PRIORITY 0 1 mmCP_ME0_PIPE1_PRIORITY 0 0x304e 1 0 4294967295 PRIORITY 0 1 mmCP_RING2_PRIORITY 0 0x304f 1 0 4294967295 PRIORITY 0 1 mmCP_ME0_PIPE2_PRIORITY 0 0x304f 1 0 4294967295 PRIORITY 0 1 mmCP_ENDIAN_SWAP 0 0x3050 1 0 4294967295 ENDIAN_SWAP 0 1 mmCP_RB_VMID 0 0x3051 3 0 4294967295 RB0_VMID 0 3 RB1_VMID 8 11 RB2_VMID 16 19 mmCP_PFP_UCODE_ADDR 0 0x3054 1 0 4294967295 UCODE_ADDR 0 11 mmCP_PFP_UCODE_DATA 0 0x3055 1 0 4294967295 UCODE_DATA 0 31 mmCP_ME_RAM_RADDR 0 0x3056 1 0 4294967295 ME_RAM_RADDR 0 11 mmCP_ME_RAM_WADDR 0 0x3057 1 0 4294967295 ME_RAM_WADDR 0 11 mmCP_ME_RAM_DATA 0 0x3058 1 0 4294967295 ME_RAM_DATA 0 31 mmCGTT_CPC_CLK_CTRL 0 0xf0b2 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 mmCGTT_CPF_CLK_CTRL 0 0xf0b1 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 mmCGTT_CP_CLK_CTRL 0 0xf0b0 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 mmCP_CE_UCODE_ADDR 0 0x305a 1 0 4294967295 UCODE_ADDR 0 11 mmCP_CE_UCODE_DATA 0 0x305b 1 0 4294967295 UCODE_DATA 0 31 mmCP_MEC_ME1_UCODE_ADDR 0 0x305c 1 0 4294967295 UCODE_ADDR 0 12 mmCP_MEC_ME1_UCODE_DATA 0 0x305d 1 0 4294967295 UCODE_DATA 0 31 mmCP_MEC_ME2_UCODE_ADDR 0 0x305e 1 0 4294967295 UCODE_ADDR 0 12 mmCP_MEC_ME2_UCODE_DATA 0 0x305f 1 0 4294967295 UCODE_DATA 0 31 mmCP_PWR_CNTL 0 0x3078 1 0 4294967295 GFX_CLK_HALT 0 0 mmCP_MEM_SLP_CNTL 0 0x3079 6 0 4294967295 CP_MEM_LS_EN 0 0 CP_MEM_DS_EN 1 1 RESERVED 2 7 CP_MEM_LS_ON_DELAY 8 15 CP_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 mmCP_ECC_FIRSTOCCURRENCE 0 0x307a 4 0 4294967295 INTERFACE 0 1 REQUEST_CLIENT 4 7 RING_ID 10 13 VMID 16 19 mmCP_ECC_FIRSTOCCURRENCE_RING0 0 0x307b 4 0 4294967295 INTERFACE 0 1 REQUEST_CLIENT 4 7 RING_ID 10 13 VMID 16 19 mmCP_ECC_FIRSTOCCURRENCE_RING1 0 0x307c 4 0 4294967295 INTERFACE 0 1 REQUEST_CLIENT 4 7 RING_ID 10 13 VMID 16 19 mmCP_ECC_FIRSTOCCURRENCE_RING2 0 0x307d 4 0 4294967295 INTERFACE 0 1 REQUEST_CLIENT 4 7 RING_ID 10 13 VMID 16 19 mmCP_CPF_DEBUG 0 0x3080 0 0 4294967295 mmCP_FETCHER_SOURCE 0 0x3082 1 0 4294967295 ME_SRC 0 0 mmCP_PQ_WPTR_POLL_CNTL 0 0x3083 3 0 4294967295 PERIOD 0 7 POLL_ACTIVE 30 30 EN 31 31 mmCP_PQ_WPTR_POLL_CNTL1 0 0x3084 1 0 4294967295 QUEUE_MASK 0 31 mmCPC_INT_CNTL 0 0x30b4 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE0_INT_CNTL 0 0x3085 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE1_INT_CNTL 0 0x3086 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE2_INT_CNTL 0 0x3087 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME1_PIPE3_INT_CNTL 0 0x3088 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE0_INT_CNTL 0 0x3089 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE1_INT_CNTL 0 0x308a 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE2_INT_CNTL 0 0x308b 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCP_ME2_PIPE3_INT_CNTL 0 0x308c 10 0 4294967295 DEQUEUE_REQUEST_INT_ENABLE 13 13 CP_ECC_ERROR_INT_ENABLE 14 14 WRM_POLL_TIMEOUT_INT_ENABLE 17 17 PRIV_REG_INT_ENABLE 23 23 OPCODE_ERROR_INT_ENABLE 24 24 TIME_STAMP_INT_ENABLE 26 26 RESERVED_BIT_ERROR_INT_ENABLE 27 27 GENERIC2_INT_ENABLE 29 29 GENERIC1_INT_ENABLE 30 30 GENERIC0_INT_ENABLE 31 31 mmCPC_INT_STATUS 0 0x30b5 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE0_INT_STATUS 0 0x308d 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE1_INT_STATUS 0 0x308e 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE2_INT_STATUS 0 0x308f 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_PIPE3_INT_STATUS 0 0x3090 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE0_INT_STATUS 0 0x3091 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE1_INT_STATUS 0 0x3092 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE2_INT_STATUS 0 0x3093 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME2_PIPE3_INT_STATUS 0 0x3094 10 0 4294967295 DEQUEUE_REQUEST_INT_STATUS 13 13 CP_ECC_ERROR_INT_STATUS 14 14 WRM_POLL_TIMEOUT_INT_STATUS 17 17 PRIV_REG_INT_STATUS 23 23 OPCODE_ERROR_INT_STATUS 24 24 TIME_STAMP_INT_STATUS 26 26 RESERVED_BIT_ERROR_INT_STATUS 27 27 GENERIC2_INT_STATUS 29 29 GENERIC1_INT_STATUS 30 30 GENERIC0_INT_STATUS 31 31 mmCP_ME1_INT_STAT_DEBUG 0 0x3095 10 0 4294967295 DEQUEUE_REQUEST_INT_ASSERTED 13 13 CP_ECC_ERROR_INT_ASSERTED 14 14 WRM_POLL_TIMEOUT_INT_ASSERTED 17 17 PRIV_REG_INT_ASSERTED 23 23 OPCODE_ERROR_INT_ASSERTED 24 24 TIME_STAMP_INT_ASSERTED 26 26 RESERVED_BIT_ERROR_INT_ASSERTED 27 27 GENERIC2_INT_ASSERTED 29 29 GENERIC1_INT_ASSERTED 30 30 GENERIC0_INT_ASSERTED 31 31 mmCP_ME2_INT_STAT_DEBUG 0 0x3096 10 0 4294967295 DEQUEUE_REQUEST_INT_ASSERTED 13 13 CP_ECC_ERROR_INT_ASSERTED 14 14 WRM_POLL_TIMEOUT_INT_ASSERTED 17 17 PRIV_REG_INT_ASSERTED 23 23 OPCODE_ERROR_INT_ASSERTED 24 24 TIME_STAMP_INT_ASSERTED 26 26 RESERVED_BIT_ERROR_INT_ASSERTED 27 27 GENERIC2_INT_ASSERTED 29 29 GENERIC1_INT_ASSERTED 30 30 GENERIC0_INT_ASSERTED 31 31 mmCP_ME1_PIPE_PRIORITY_CNTS 0 0x3099 4 0 4294967295 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME1_PIPE0_PRIORITY 0 0x309a 1 0 4294967295 PRIORITY 0 1 mmCP_ME1_PIPE1_PRIORITY 0 0x309b 1 0 4294967295 PRIORITY 0 1 mmCP_ME1_PIPE2_PRIORITY 0 0x309c 1 0 4294967295 PRIORITY 0 1 mmCP_ME1_PIPE3_PRIORITY 0 0x309d 1 0 4294967295 PRIORITY 0 1 mmCP_ME2_PIPE_PRIORITY_CNTS 0 0x309e 4 0 4294967295 PRIORITY1_CNT 0 7 PRIORITY2A_CNT 8 15 PRIORITY2B_CNT 16 23 PRIORITY3_CNT 24 31 mmCP_ME2_PIPE0_PRIORITY 0 0x309f 1 0 4294967295 PRIORITY 0 1 mmCP_ME2_PIPE1_PRIORITY 0 0x30a0 1 0 4294967295 PRIORITY 0 1 mmCP_ME2_PIPE2_PRIORITY 0 0x30a1 1 0 4294967295 PRIORITY 0 1 mmCP_ME2_PIPE3_PRIORITY 0 0x30a2 1 0 4294967295 PRIORITY 0 1 mmCP_CE_PRGRM_CNTR_START 0 0x30a3 1 0 4294967295 IP_START 0 10 mmCP_PFP_PRGRM_CNTR_START 0 0x30a4 1 0 4294967295 IP_START 0 10 mmCP_ME_PRGRM_CNTR_START 0 0x30a5 1 0 4294967295 IP_START 0 10 mmCP_MEC1_PRGRM_CNTR_START 0 0x30a6 1 0 4294967295 IP_START 0 11 mmCP_MEC2_PRGRM_CNTR_START 0 0x30a7 1 0 4294967295 IP_START 0 11 mmCP_CE_INTR_ROUTINE_START 0 0x30a8 1 0 4294967295 IR_START 0 10 mmCP_PFP_INTR_ROUTINE_START 0 0x30a9 1 0 4294967295 IR_START 0 10 mmCP_ME_INTR_ROUTINE_START 0 0x30aa 1 0 4294967295 IR_START 0 10 mmCP_MEC1_INTR_ROUTINE_START 0 0x30ab 1 0 4294967295 IR_START 0 11 mmCP_MEC2_INTR_ROUTINE_START 0 0x30ac 1 0 4294967295 IR_START 0 11 mmCP_CONTEXT_CNTL 0 0x30ad 4 0 4294967295 ME0PIPE0_MAX_WD_CNTX 0 2 ME0PIPE0_MAX_PIPE_CNTX 4 6 ME0PIPE1_MAX_WD_CNTX 16 18 ME0PIPE1_MAX_PIPE_CNTX 20 22 mmCP_MAX_CONTEXT 0 0x30ae 1 0 4294967295 MAX_CONTEXT 0 2 mmCP_IQ_WAIT_TIME1 0 0x30af 4 0 4294967295 IB_OFFLOAD 0 7 ATOMIC_OFFLOAD 8 15 WRM_OFFLOAD 16 23 GWS 24 31 mmCP_IQ_WAIT_TIME2 0 0x30b0 4 0 4294967295 QUE_SLEEP 0 7 SCH_WAVE 8 15 SEM_REARM 16 23 DEQ_RETRY 24 31 mmCP_VMID_RESET 0 0x30b3 2 0 4294967295 RESET_REQUEST 0 15 RESET_STATUS 16 31 mmCP_VMID_PREEMPT 0 0x30b6 2 0 4294967295 PREEMPT_REQUEST 0 15 PREEMPT_STATUS 16 31 mmCP_PQ_STATUS 0 0x30b8 2 0 4294967295 DOORBELL_UPDATED 0 0 DOORBELL_ENABLE 1 1 mmCP_CPC_STATUS 0 0x2084 16 0 4294967295 MEC1_BUSY 0 0 MEC2_BUSY 1 1 DC0_BUSY 2 2 DC1_BUSY 3 3 RCIU1_BUSY 4 4 RCIU2_BUSY 5 5 ROQ1_BUSY 6 6 ROQ2_BUSY 7 7 MIU_RDREQ_BUSY 8 8 MIU_WRREQ_BUSY 9 9 TCIU_BUSY 10 10 SCRATCH_RAM_BUSY 11 11 QU_BUSY 12 12 CPG_CPC_BUSY 29 29 CPF_CPC_BUSY 30 30 CPC_BUSY 31 31 mmCP_CPC_BUSY_STAT 0 0x2085 28 0 4294967295 MEC1_LOAD_BUSY 0 0 MEC1_SEMAPOHRE_BUSY 1 1 MEC1_MUTEX_BUSY 2 2 MEC1_MESSAGE_BUSY 3 3 MEC1_EOP_QUEUE_BUSY 4 4 MEC1_IQ_QUEUE_BUSY 5 5 MEC1_IB_QUEUE_BUSY 6 6 MEC1_TC_BUSY 7 7 MEC1_DMA_BUSY 8 8 MEC1_PARTIAL_FLUSH_BUSY 9 9 MEC1_PIPE0_BUSY 10 10 MEC1_PIPE1_BUSY 11 11 MEC1_PIPE2_BUSY 12 12 MEC1_PIPE3_BUSY 13 13 MEC2_LOAD_BUSY 16 16 MEC2_SEMAPOHRE_BUSY 17 17 MEC2_MUTEX_BUSY 18 18 MEC2_MESSAGE_BUSY 19 19 MEC2_EOP_QUEUE_BUSY 20 20 MEC2_IQ_QUEUE_BUSY 21 21 MEC2_IB_QUEUE_BUSY 22 22 MEC2_TC_BUSY 23 23 MEC2_DMA_BUSY 24 24 MEC2_PARTIAL_FLUSH_BUSY 25 25 MEC2_PIPE0_BUSY 26 26 MEC2_PIPE1_BUSY 27 27 MEC2_PIPE2_BUSY 28 28 MEC2_PIPE3_BUSY 29 29 mmCP_CPC_STALLED_STAT1 0 0x2086 17 0 4294967295 MIU_RDREQ_FREE_STALL 0 0 MIU_WRREQ_FREE_STALL 1 1 RCIU_TX_FREE_STALL 3 3 RCIU_PRIV_VIOLATION 4 4 TCIU_TX_FREE_STALL 6 6 MEC1_DECODING_PACKET 8 8 MEC1_WAIT_ON_RCIU 9 9 MEC1_WAIT_ON_RCIU_READ 10 10 MEC1_WAIT_ON_MC_READ 11 11 MEC1_WAIT_ON_MC_WR_ACK 12 12 MEC1_WAIT_ON_ROQ_DATA 13 13 MEC2_DECODING_PACKET 16 16 MEC2_WAIT_ON_RCIU 17 17 MEC2_WAIT_ON_RCIU_READ 18 18 MEC2_WAIT_ON_MC_READ 19 19 MEC2_WAIT_ON_MC_WR_ACK 20 20 MEC2_WAIT_ON_ROQ_DATA 21 21 mmCP_CPF_STATUS 0 0x2087 18 0 4294967295 POST_WPTR_GFX_BUSY 0 0 CSF_BUSY 1 1 MIU_RDREQ_BUSY 2 2 MIU_WRREQ_BUSY 3 3 ROQ_ALIGN_BUSY 4 4 ROQ_RING_BUSY 5 5 ROQ_INDIRECT1_BUSY 6 6 ROQ_INDIRECT2_BUSY 7 7 ROQ_STATE_BUSY 8 8 ROQ_CE_RING_BUSY 9 9 ROQ_CE_INDIRECT1_BUSY 10 10 ROQ_CE_INDIRECT2_BUSY 11 11 SEMAPHORE_BUSY 12 12 INTERRUPT_BUSY 13 13 TCIU_BUSY 14 14 HQD_BUSY 15 15 CPC_CPF_BUSY 30 30 CPF_BUSY 31 31 mmCP_CPF_BUSY_STAT 0 0x2088 31 0 4294967295 REG_BUS_FIFO_BUSY 0 0 CSF_RING_BUSY 1 1 CSF_INDIRECT1_BUSY 2 2 CSF_INDIRECT2_BUSY 3 3 CSF_STATE_BUSY 4 4 CSF_CE_INDR1_BUSY 5 5 CSF_CE_INDR2_BUSY 6 6 CSF_ARBITER_BUSY 7 7 CSF_INPUT_BUSY 8 8 OUTSTANDING_READ_TAGS 9 9 HPD_PROCESSING_EOP_BUSY 11 11 HQD_DISPATCH_BUSY 12 12 HQD_IQ_TIMER_BUSY 13 13 HQD_DMA_OFFLOAD_BUSY 14 14 HQD_WAIT_SEMAPHORE_BUSY 15 15 HQD_SIGNAL_SEMAPHORE_BUSY 16 16 HQD_MESSAGE_BUSY 17 17 HQD_PQ_FETCHER_BUSY 18 18 HQD_IB_FETCHER_BUSY 19 19 HQD_IQ_FETCHER_BUSY 20 20 HQD_EOP_FETCHER_BUSY 21 21 HQD_CONSUMED_RPTR_BUSY 22 22 HQD_FETCHER_ARB_BUSY 23 23 HQD_ROQ_ALIGN_BUSY 24 24 HQD_ROQ_EOP_BUSY 25 25 HQD_ROQ_IQ_BUSY 26 26 HQD_ROQ_PQ_BUSY 27 27 HQD_ROQ_IB_BUSY 28 28 HQD_WPTR_POLL_BUSY 29 29 HQD_PQ_BUSY 30 30 HQD_IB_BUSY 31 31 mmCP_CPF_STALLED_STAT1 0 0x2089 7 0 4294967295 RING_FETCHING_DATA 0 0 INDR1_FETCHING_DATA 1 1 INDR2_FETCHING_DATA 2 2 STATE_FETCHING_DATA 3 3 MIU_WAITING_ON_RDREQ_FREE 4 4 TCIU_WAITING_ON_FREE 5 5 TCIU_WAITING_ON_TAGS 6 6 mmCP_CPC_MC_CNTL 0 0x208a 1 0 4294967295 PACK_DELAY_CNT 0 4 mmCP_CPC_GRBM_FREE_COUNT 0 0x208b 1 0 4294967295 FREE_COUNT 0 5 mmCP_MEC_CNTL 0 0x208d 5 0 4294967295 MEC_INVALIDATE_ICACHE 4 4 MEC_ME2_HALT 28 28 MEC_ME2_STEP 29 29 MEC_ME1_HALT 30 30 MEC_ME1_STEP 31 31 mmCP_MEC_ME1_HEADER_DUMP 0 0x208e 1 0 4294967295 HEADER_DUMP 0 31 mmCP_MEC_ME2_HEADER_DUMP 0 0x208f 1 0 4294967295 HEADER_DUMP 0 31 mmCP_CPC_SCRATCH_INDEX 0 0x2090 1 0 4294967295 SCRATCH_INDEX 0 7 mmCP_CPC_SCRATCH_DATA 0 0x2091 1 0 4294967295 SCRATCH_DATA 0 31 mmCPG_PERFCOUNTER1_SELECT 0 0xd800 1 0 4294967295 PERF_SEL 0 5 mmCPG_PERFCOUNTER1_LO 0 0xd000 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPG_PERFCOUNTER1_HI 0 0xd001 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCPG_PERFCOUNTER0_SELECT1 0 0xd801 2 0 4294967295 PERF_SEL2 0 5 PERF_SEL3 10 15 mmCPG_PERFCOUNTER0_SELECT 0 0xd802 3 0 4294967295 PERF_SEL 0 5 PERF_SEL1 10 15 CNTR_MODE 20 23 mmCPG_PERFCOUNTER0_LO 0 0xd002 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPG_PERFCOUNTER0_HI 0 0xd003 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCPC_PERFCOUNTER1_SELECT 0 0xd803 1 0 4294967295 PERF_SEL 0 5 mmCPC_PERFCOUNTER1_LO 0 0xd004 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPC_PERFCOUNTER1_HI 0 0xd005 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCPC_PERFCOUNTER0_SELECT1 0 0xd804 2 0 4294967295 PERF_SEL2 0 5 PERF_SEL3 10 15 mmCPC_PERFCOUNTER0_SELECT 0 0xd809 3 0 4294967295 PERF_SEL 0 5 PERF_SEL1 10 15 CNTR_MODE 20 23 mmCPC_PERFCOUNTER0_LO 0 0xd006 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPC_PERFCOUNTER0_HI 0 0xd007 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCPF_PERFCOUNTER1_SELECT 0 0xd805 1 0 4294967295 PERF_SEL 0 5 mmCPF_PERFCOUNTER1_LO 0 0xd008 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPF_PERFCOUNTER1_HI 0 0xd009 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCPF_PERFCOUNTER0_SELECT1 0 0xd806 2 0 4294967295 PERF_SEL2 0 5 PERF_SEL3 10 15 mmCPF_PERFCOUNTER0_SELECT 0 0xd807 3 0 4294967295 PERF_SEL 0 5 PERF_SEL1 10 15 CNTR_MODE 20 23 mmCPF_PERFCOUNTER0_LO 0 0xd00a 1 0 4294967295 PERFCOUNTER_LO 0 31 mmCPF_PERFCOUNTER0_HI 0 0xd00b 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCP_CPC_HALT_HYST_COUNT 0 0x20a7 1 0 4294967295 COUNT 0 3 mmCP_CE_COMPARE_COUNT 0 0x20c0 1 0 4294967295 COMPARE_COUNT 0 31 mmCP_CE_DE_COUNT 0 0x20c1 1 0 4294967295 DRAW_ENGINE_COUNT 0 31 mmCP_DE_CE_COUNT 0 0x20c2 1 0 4294967295 CONST_ENGINE_COUNT 0 31 mmCP_DE_LAST_INVAL_COUNT 0 0x20c3 1 0 4294967295 LAST_INVAL_COUNT 0 31 mmCP_DE_DE_COUNT 0 0x20c4 1 0 4294967295 DRAW_ENGINE_COUNT 0 31 mmCP_EOP_DONE_EVENT_CNTL 0 0xc0d5 4 0 4294967295 WBINV_TC_OP 0 6 WBINV_ACTION_ENA 12 17 CACHE_CONTROL 25 26 EOP_VOLATILE 27 27 mmCP_EOP_DONE_DATA_CNTL 0 0xc0d6 4 0 4294967295 CNTX_ID 0 15 DST_SEL 16 17 INT_SEL 24 26 DATA_SEL 29 31 mmCP_EOP_DONE_ADDR_LO 0 0xc000 2 0 4294967295 ADDR_SWAP 0 1 ADDR_LO 2 31 mmCP_EOP_DONE_ADDR_HI 0 0xc001 1 0 4294967295 ADDR_HI 0 15 mmCP_EOP_DONE_DATA_LO 0 0xc002 1 0 4294967295 DATA_LO 0 31 mmCP_EOP_DONE_DATA_HI 0 0xc003 1 0 4294967295 DATA_HI 0 31 mmCP_EOP_LAST_FENCE_LO 0 0xc004 1 0 4294967295 LAST_FENCE_LO 0 31 mmCP_EOP_LAST_FENCE_HI 0 0xc005 1 0 4294967295 LAST_FENCE_HI 0 31 mmCP_STREAM_OUT_ADDR_LO 0 0xc006 2 0 4294967295 STREAM_OUT_ADDR_SWAP 0 1 STREAM_OUT_ADDR_LO 2 31 mmCP_STREAM_OUT_ADDR_HI 0 0xc007 1 0 4294967295 STREAM_OUT_ADDR_HI 0 15 mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0 0xc008 1 0 4294967295 NUM_PRIM_WRITTEN_CNT0_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0 0xc009 1 0 4294967295 NUM_PRIM_WRITTEN_CNT0_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0 0xc00a 1 0 4294967295 NUM_PRIM_NEEDED_CNT0_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0 0xc00b 1 0 4294967295 NUM_PRIM_NEEDED_CNT0_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0 0xc00c 1 0 4294967295 NUM_PRIM_WRITTEN_CNT1_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0 0xc00d 1 0 4294967295 NUM_PRIM_WRITTEN_CNT1_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0 0xc00e 1 0 4294967295 NUM_PRIM_NEEDED_CNT1_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0 0xc00f 1 0 4294967295 NUM_PRIM_NEEDED_CNT1_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0 0xc010 1 0 4294967295 NUM_PRIM_WRITTEN_CNT2_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0 0xc011 1 0 4294967295 NUM_PRIM_WRITTEN_CNT2_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0 0xc012 1 0 4294967295 NUM_PRIM_NEEDED_CNT2_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0 0xc013 1 0 4294967295 NUM_PRIM_NEEDED_CNT2_HI 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0 0xc014 1 0 4294967295 NUM_PRIM_WRITTEN_CNT3_LO 0 31 mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0 0xc015 1 0 4294967295 NUM_PRIM_WRITTEN_CNT3_HI 0 31 mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0 0xc016 1 0 4294967295 NUM_PRIM_NEEDED_CNT3_LO 0 31 mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0 0xc017 1 0 4294967295 NUM_PRIM_NEEDED_CNT3_HI 0 31 mmCP_PIPE_STATS_ADDR_LO 0 0xc018 2 0 4294967295 PIPE_STATS_ADDR_SWAP 0 1 PIPE_STATS_ADDR_LO 2 31 mmCP_PIPE_STATS_ADDR_HI 0 0xc019 1 0 4294967295 PIPE_STATS_ADDR_HI 0 15 mmCP_VGT_IAVERT_COUNT_LO 0 0xc01a 1 0 4294967295 IAVERT_COUNT_LO 0 31 mmCP_VGT_IAVERT_COUNT_HI 0 0xc01b 1 0 4294967295 IAVERT_COUNT_HI 0 31 mmCP_VGT_IAPRIM_COUNT_LO 0 0xc01c 1 0 4294967295 IAPRIM_COUNT_LO 0 31 mmCP_VGT_IAPRIM_COUNT_HI 0 0xc01d 1 0 4294967295 IAPRIM_COUNT_HI 0 31 mmCP_VGT_GSPRIM_COUNT_LO 0 0xc01e 1 0 4294967295 GSPRIM_COUNT_LO 0 31 mmCP_VGT_GSPRIM_COUNT_HI 0 0xc01f 1 0 4294967295 GSPRIM_COUNT_HI 0 31 mmCP_VGT_VSINVOC_COUNT_LO 0 0xc020 1 0 4294967295 VSINVOC_COUNT_LO 0 31 mmCP_VGT_VSINVOC_COUNT_HI 0 0xc021 1 0 4294967295 VSINVOC_COUNT_HI 0 31 mmCP_VGT_GSINVOC_COUNT_LO 0 0xc022 1 0 4294967295 GSINVOC_COUNT_LO 0 31 mmCP_VGT_GSINVOC_COUNT_HI 0 0xc023 1 0 4294967295 GSINVOC_COUNT_HI 0 31 mmCP_VGT_HSINVOC_COUNT_LO 0 0xc024 1 0 4294967295 HSINVOC_COUNT_LO 0 31 mmCP_VGT_HSINVOC_COUNT_HI 0 0xc025 1 0 4294967295 HSINVOC_COUNT_HI 0 31 mmCP_VGT_DSINVOC_COUNT_LO 0 0xc026 1 0 4294967295 DSINVOC_COUNT_LO 0 31 mmCP_VGT_DSINVOC_COUNT_HI 0 0xc027 1 0 4294967295 DSINVOC_COUNT_HI 0 31 mmCP_PA_CINVOC_COUNT_LO 0 0xc028 1 0 4294967295 CINVOC_COUNT_LO 0 31 mmCP_PA_CINVOC_COUNT_HI 0 0xc029 1 0 4294967295 CINVOC_COUNT_HI 0 31 mmCP_PA_CPRIM_COUNT_LO 0 0xc02a 1 0 4294967295 CPRIM_COUNT_LO 0 31 mmCP_PA_CPRIM_COUNT_HI 0 0xc02b 1 0 4294967295 CPRIM_COUNT_HI 0 31 mmCP_SC_PSINVOC_COUNT0_LO 0 0xc02c 1 0 4294967295 PSINVOC_COUNT0_LO 0 31 mmCP_SC_PSINVOC_COUNT0_HI 0 0xc02d 1 0 4294967295 PSINVOC_COUNT0_HI 0 31 mmCP_SC_PSINVOC_COUNT1_LO 0 0xc02e 1 0 4294967295 OBSOLETE 0 31 mmCP_SC_PSINVOC_COUNT1_HI 0 0xc02f 1 0 4294967295 OBSOLETE 0 31 mmCP_VGT_CSINVOC_COUNT_LO 0 0xc030 1 0 4294967295 CSINVOC_COUNT_LO 0 31 mmCP_VGT_CSINVOC_COUNT_HI 0 0xc031 1 0 4294967295 CSINVOC_COUNT_HI 0 31 mmCP_STRMOUT_CNTL 0 0xc03f 1 0 4294967295 OFFSET_UPDATE_DONE 0 0 mmSCRATCH_REG0 0 0xc040 1 0 4294967295 SCRATCH_REG0 0 31 mmSCRATCH_REG1 0 0xc041 1 0 4294967295 SCRATCH_REG1 0 31 mmSCRATCH_REG2 0 0xc042 1 0 4294967295 SCRATCH_REG2 0 31 mmSCRATCH_REG3 0 0xc043 1 0 4294967295 SCRATCH_REG3 0 31 mmSCRATCH_REG4 0 0xc044 1 0 4294967295 SCRATCH_REG4 0 31 mmSCRATCH_REG5 0 0xc045 1 0 4294967295 SCRATCH_REG5 0 31 mmSCRATCH_REG6 0 0xc046 1 0 4294967295 SCRATCH_REG6 0 31 mmSCRATCH_REG7 0 0xc047 1 0 4294967295 SCRATCH_REG7 0 31 mmSCRATCH_UMSK 0 0xc050 2 0 4294967295 OBSOLETE_UMSK 0 7 OBSOLETE_SWAP 16 17 mmSCRATCH_ADDR 0 0xc051 1 0 4294967295 OBSOLETE_ADDR 0 31 mmCP_PFP_ATOMIC_PREOP_LO 0 0xc052 1 0 4294967295 ATOMIC_PREOP_LO 0 31 mmCP_PFP_ATOMIC_PREOP_HI 0 0xc053 1 0 4294967295 ATOMIC_PREOP_HI 0 31 mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0 0xc054 1 0 4294967295 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0 0xc055 1 0 4294967295 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0 0xc056 1 0 4294967295 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0 0xc057 1 0 4294967295 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_APPEND_ADDR_LO 0 0xc058 1 0 4294967295 MEM_ADDR_LO 2 31 mmCP_APPEND_ADDR_HI 0 0xc059 3 0 4294967295 MEM_ADDR_HI 0 15 CS_PS_SEL 16 16 COMMAND 29 31 mmCP_APPEND_DATA 0 0xc05a 1 0 4294967295 DATA 0 31 mmCP_APPEND_LAST_CS_FENCE 0 0xc05b 1 0 4294967295 LAST_FENCE 0 31 mmCP_APPEND_LAST_PS_FENCE 0 0xc05c 1 0 4294967295 LAST_FENCE 0 31 mmCP_ATOMIC_PREOP_LO 0 0xc05d 1 0 4294967295 ATOMIC_PREOP_LO 0 31 mmCP_ME_ATOMIC_PREOP_LO 0 0xc05d 1 0 4294967295 ATOMIC_PREOP_LO 0 31 mmCP_ATOMIC_PREOP_HI 0 0xc05e 1 0 4294967295 ATOMIC_PREOP_HI 0 31 mmCP_ME_ATOMIC_PREOP_HI 0 0xc05e 1 0 4294967295 ATOMIC_PREOP_HI 0 31 mmCP_GDS_ATOMIC0_PREOP_LO 0 0xc05f 1 0 4294967295 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_ME_GDS_ATOMIC0_PREOP_LO 0 0xc05f 1 0 4294967295 GDS_ATOMIC0_PREOP_LO 0 31 mmCP_GDS_ATOMIC0_PREOP_HI 0 0xc060 1 0 4294967295 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_ME_GDS_ATOMIC0_PREOP_HI 0 0xc060 1 0 4294967295 GDS_ATOMIC0_PREOP_HI 0 31 mmCP_GDS_ATOMIC1_PREOP_LO 0 0xc061 1 0 4294967295 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_ME_GDS_ATOMIC1_PREOP_LO 0 0xc061 1 0 4294967295 GDS_ATOMIC1_PREOP_LO 0 31 mmCP_GDS_ATOMIC1_PREOP_HI 0 0xc062 1 0 4294967295 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_ME_GDS_ATOMIC1_PREOP_HI 0 0xc062 1 0 4294967295 GDS_ATOMIC1_PREOP_HI 0 31 mmCP_ME_MC_WADDR_LO 0 0xc069 2 0 4294967295 ME_MC_WADDR_SWAP 0 1 ME_MC_WADDR_LO 2 31 mmCP_ME_MC_WADDR_HI 0 0xc06a 1 0 4294967295 ME_MC_WADDR_HI 0 15 mmCP_ME_MC_WDATA_LO 0 0xc06b 1 0 4294967295 ME_MC_WDATA_LO 0 31 mmCP_ME_MC_WDATA_HI 0 0xc06c 1 0 4294967295 ME_MC_WDATA_HI 0 31 mmCP_ME_MC_RADDR_LO 0 0xc06d 2 0 4294967295 ME_MC_RADDR_SWAP 0 1 ME_MC_RADDR_LO 2 31 mmCP_ME_MC_RADDR_HI 0 0xc06e 1 0 4294967295 ME_MC_RADDR_HI 0 15 mmCP_SEM_WAIT_TIMER 0 0xc06f 1 0 4294967295 SEM_WAIT_TIMER 0 31 mmCP_SIG_SEM_ADDR_LO 0 0xc070 2 0 4294967295 SEM_ADDR_SWAP 0 1 SEM_ADDR_LO 3 31 mmCP_SIG_SEM_ADDR_HI 0 0xc071 5 0 4294967295 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 mmCP_SEM_INCOMPLETE_TIMER_CNTL 0 0xc072 0 0 4294967295 mmCP_WAIT_SEM_STATUS 0 0xc073 0 0 4294967295 mmCP_WAIT_SEM_ADDR_LO 0 0xc075 2 0 4294967295 SEM_ADDR_SWAP 0 1 SEM_ADDR_LO 3 31 mmCP_WAIT_SEM_ADDR_HI 0 0xc076 5 0 4294967295 SEM_ADDR_HI 0 15 SEM_USE_MAILBOX 16 16 SEM_SIGNAL_TYPE 20 20 SEM_CLIENT_CODE 24 25 SEM_SELECT 29 31 mmCP_WAIT_REG_MEM_TIMEOUT 0 0xc074 1 0 4294967295 WAIT_REG_MEM_TIMEOUT 0 31 mmCP_COHER_START_DELAY 0 0xc07b 1 0 4294967295 START_DELAY_COUNT 0 5 mmCP_COHER_CNTL 0 0xc07c 23 0 4294967295 DEST_BASE_0_ENA 0 0 DEST_BASE_1_ENA 1 1 CB0_DEST_BASE_ENA 6 6 CB1_DEST_BASE_ENA 7 7 CB2_DEST_BASE_ENA 8 8 CB3_DEST_BASE_ENA 9 9 CB4_DEST_BASE_ENA 10 10 CB5_DEST_BASE_ENA 11 11 CB6_DEST_BASE_ENA 12 12 CB7_DEST_BASE_ENA 13 13 DB_DEST_BASE_ENA 14 14 TCL1_VOL_ACTION_ENA 15 15 TC_VOL_ACTION_ENA 16 16 TC_WB_ACTION_ENA 18 18 DEST_BASE_2_ENA 19 19 DEST_BASE_3_ENA 21 21 TCL1_ACTION_ENA 22 22 TC_ACTION_ENA 23 23 CB_ACTION_ENA 25 25 DB_ACTION_ENA 26 26 SH_KCACHE_ACTION_ENA 27 27 SH_KCACHE_VOL_ACTION_ENA 28 28 SH_ICACHE_ACTION_ENA 29 29 mmCP_COHER_SIZE 0 0xc07d 1 0 4294967295 COHER_SIZE_256B 0 31 mmCP_COHER_SIZE_HI 0 0xc08c 1 0 4294967295 COHER_SIZE_HI_256B 0 7 mmCP_COHER_BASE 0 0xc07e 1 0 4294967295 COHER_BASE_256B 0 31 mmCP_COHER_BASE_HI 0 0xc079 1 0 4294967295 COHER_BASE_HI_256B 0 7 mmCP_COHER_STATUS 0 0xc07f 4 0 4294967295 MATCHING_GFX_CNTX 0 7 MEID 24 25 PHASE1_STATUS 30 30 STATUS 31 31 mmCOHER_DEST_BASE_0 0 0xa092 1 0 4294967295 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_1 0 0xa093 1 0 4294967295 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_2 0 0xa07e 1 0 4294967295 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_3 0 0xa07f 1 0 4294967295 DEST_BASE_256B 0 31 mmCOHER_DEST_BASE_HI_0 0 0xa07a 1 0 4294967295 DEST_BASE_HI_256B 0 31 mmCOHER_DEST_BASE_HI_1 0 0xa07b 1 0 4294967295 DEST_BASE_HI_256B 0 31 mmCOHER_DEST_BASE_HI_2 0 0xa07c 1 0 4294967295 DEST_BASE_HI_256B 0 31 mmCOHER_DEST_BASE_HI_3 0 0xa07d 1 0 4294967295 DEST_BASE_HI_256B 0 31 mmCP_DMA_ME_SRC_ADDR 0 0xc080 1 0 4294967295 SRC_ADDR 0 31 mmCP_DMA_ME_SRC_ADDR_HI 0 0xc081 1 0 4294967295 SRC_ADDR_HI 0 15 mmCP_DMA_ME_DST_ADDR 0 0xc082 1 0 4294967295 DST_ADDR 0 31 mmCP_DMA_ME_DST_ADDR_HI 0 0xc083 1 0 4294967295 DST_ADDR_HI 0 15 mmCP_DMA_ME_CONTROL 0 0xc078 8 0 4294967295 SRC_ATC 12 12 SRC_CACHE_POLICY 13 14 SRC_VOLATILE 15 15 DST_SELECT 20 21 DST_ATC 24 24 DST_CACHE_POLICY 25 26 DST_VOLATILE 27 27 SRC_SELECT 29 30 mmCP_DMA_ME_COMMAND 0 0xc084 9 0 4294967295 BYTE_COUNT 0 20 DIS_WC 21 21 SRC_SWAP 22 23 DST_SWAP 24 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 mmCP_DMA_PFP_SRC_ADDR 0 0xc085 1 0 4294967295 SRC_ADDR 0 31 mmCP_DMA_PFP_SRC_ADDR_HI 0 0xc086 1 0 4294967295 SRC_ADDR_HI 0 15 mmCP_DMA_PFP_DST_ADDR 0 0xc087 1 0 4294967295 DST_ADDR 0 31 mmCP_DMA_PFP_DST_ADDR_HI 0 0xc088 1 0 4294967295 DST_ADDR_HI 0 15 mmCP_DMA_PFP_CONTROL 0 0xc077 8 0 4294967295 SRC_ATC 12 12 SRC_CACHE_POLICY 13 14 SRC_VOLATILE 15 15 DST_SELECT 20 21 DST_ATC 24 24 DST_CACHE_POLICY 25 26 DST_VOLATILE 27 27 SRC_SELECT 29 30 mmCP_DMA_PFP_COMMAND 0 0xc089 9 0 4294967295 BYTE_COUNT 0 20 DIS_WC 21 21 SRC_SWAP 22 23 DST_SWAP 24 25 SAS 26 26 DAS 27 27 SAIC 28 28 DAIC 29 29 RAW_WAIT 30 30 mmCP_DMA_CNTL 0 0xc08a 5 0 4294967295 MIN_AVAILSZ 4 5 BUFFER_DEPTH 16 19 PIO_FIFO_EMPTY 28 28 PIO_FIFO_FULL 29 29 PIO_COUNT 30 31 mmCP_DMA_READ_TAGS 0 0xc08b 2 0 4294967295 DMA_READ_TAG 0 25 DMA_READ_TAG_VALID 28 28 mmCP_PFP_IB_CONTROL 0 0xc08d 1 0 4294967295 IB_EN 0 7 mmCP_PFP_LOAD_CONTROL 0 0xc08e 5 0 4294967295 CONFIG_REG_EN 0 0 CNTX_REG_EN 1 1 UCONFIG_REG_EN 15 15 SH_GFX_REG_EN 16 16 SH_CS_REG_EN 24 24 mmCP_SCRATCH_INDEX 0 0xc08f 1 0 4294967295 SCRATCH_INDEX 0 7 mmCP_SCRATCH_DATA 0 0xc090 1 0 4294967295 SCRATCH_DATA 0 31 mmCP_RB_OFFSET 0 0xc091 1 0 4294967295 RB_OFFSET 0 19 mmCP_IB1_OFFSET 0 0xc092 1 0 4294967295 IB1_OFFSET 0 19 mmCP_IB2_OFFSET 0 0xc093 1 0 4294967295 IB2_OFFSET 0 19 mmCP_IB1_PREAMBLE_BEGIN 0 0xc094 1 0 4294967295 IB1_PREAMBLE_BEGIN 0 19 mmCP_IB1_PREAMBLE_END 0 0xc095 1 0 4294967295 IB1_PREAMBLE_END 0 19 mmCP_IB2_PREAMBLE_BEGIN 0 0xc096 1 0 4294967295 IB2_PREAMBLE_BEGIN 0 19 mmCP_IB2_PREAMBLE_END 0 0xc097 1 0 4294967295 IB2_PREAMBLE_END 0 19 mmCP_STALLED_STAT1 0 0x219d 18 0 4294967295 RBIU_TO_DMA_NOT_RDY_TO_RCV 0 0 RBIU_TO_SEM_NOT_RDY_TO_RCV 2 2 RBIU_TO_MEMWR_NOT_RDY_TO_RCV 4 4 ME_HAS_ACTIVE_CE_BUFFER_FLAG 10 10 ME_HAS_ACTIVE_DE_BUFFER_FLAG 11 11 ME_STALLED_ON_TC_WR_CONFIRM 12 12 ME_STALLED_ON_ATOMIC_RTN_DATA 13 13 ME_WAITING_ON_MC_READ_DATA 14 14 ME_WAITING_ON_REG_READ_DATA 15 15 MIU_WAITING_ON_RDREQ_FREE 16 16 MIU_WAITING_ON_WRREQ_FREE 17 17 RCIU_WAITING_ON_GDS_FREE 23 23 RCIU_WAITING_ON_GRBM_FREE 24 24 RCIU_WAITING_ON_VGT_FREE 25 25 RCIU_STALLED_ON_ME_READ 26 26 RCIU_STALLED_ON_DMA_READ 27 27 RCIU_STALLED_ON_APPEND_READ 28 28 RCIU_HALTED_BY_REG_VIOLATION 29 29 mmCP_STALLED_STAT2 0 0x219e 31 0 4294967295 PFP_TO_CSF_NOT_RDY_TO_RCV 0 0 PFP_TO_MEQ_NOT_RDY_TO_RCV 1 1 PFP_TO_RCIU_NOT_RDY_TO_RCV 2 2 PFP_TO_VGT_WRITES_PENDING 4 4 PFP_RCIU_READ_PENDING 5 5 PFP_MIU_READ_PENDING 6 6 PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV 7 7 PFP_WAITING_ON_BUFFER_DATA 8 8 ME_WAIT_ON_CE_COUNTER 9 9 ME_WAIT_ON_AVAIL_BUFFER 10 10 GFX_CNTX_NOT_AVAIL_TO_ME 11 11 ME_RCIU_NOT_RDY_TO_RCV 12 12 ME_TO_CONST_NOT_RDY_TO_RCV 13 13 ME_WAITING_DATA_FROM_PFP 14 14 ME_WAITING_ON_PARTIAL_FLUSH 15 15 MEQ_TO_ME_NOT_RDY_TO_RCV 16 16 STQ_TO_ME_NOT_RDY_TO_RCV 17 17 ME_WAITING_DATA_FROM_STQ 18 18 PFP_STALLED_ON_TC_WR_CONFIRM 19 19 PFP_STALLED_ON_ATOMIC_RTN_DATA 20 20 EOPD_FIFO_NEEDS_SC_EOP_DONE 21 21 EOPD_FIFO_NEEDS_WR_CONFIRM 22 22 STRMO_WR_OF_PRIM_DATA_PENDING 23 23 PIPE_STATS_WR_DATA_PENDING 24 24 APPEND_RDY_WAIT_ON_CS_DONE 25 25 APPEND_RDY_WAIT_ON_PS_DONE 26 26 APPEND_WAIT_ON_WR_CONFIRM 27 27 APPEND_ACTIVE_PARTITION 28 28 APPEND_WAITING_TO_SEND_MEMWRITE 29 29 SURF_SYNC_NEEDS_IDLE_CNTXS 30 30 SURF_SYNC_NEEDS_ALL_CLEAN 31 31 mmCP_STALLED_STAT3 0 0x219c 15 0 4294967295 CE_TO_CSF_NOT_RDY_TO_RCV 0 0 CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV 1 1 CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER 2 2 CE_TO_RAM_INIT_NOT_RDY 3 3 CE_TO_RAM_DUMP_NOT_RDY 4 4 CE_TO_RAM_WRITE_NOT_RDY 5 5 CE_TO_INC_FIFO_NOT_RDY_TO_RCV 6 6 CE_TO_WR_FIFO_NOT_RDY_TO_RCV 7 7 CE_TO_MIU_WRITE_NOT_RDY_TO_RCV 8 8 CE_WAITING_ON_BUFFER_DATA 10 10 CE_WAITING_ON_CE_BUFFER_FLAG 11 11 CE_WAITING_ON_DE_COUNTER 12 12 CE_WAITING_ON_DE_COUNTER_UNDERFLOW 13 13 TCIU_WAITING_ON_FREE 14 14 TCIU_WAITING_ON_TAGS 15 15 mmCP_BUSY_STAT 0 0x219f 16 0 4294967295 REG_BUS_FIFO_BUSY 0 0 COHER_CNT_NEQ_ZERO 6 6 PFP_PARSING_PACKETS 7 7 ME_PARSING_PACKETS 8 8 RCIU_PFP_BUSY 9 9 RCIU_ME_BUSY 10 10 SEM_CMDFIFO_NOT_EMPTY 12 12 SEM_FAILED_AND_HOLDING 13 13 SEM_POLLING_FOR_PASS 14 14 GFX_CONTEXT_BUSY 15 15 ME_PARSER_BUSY 17 17 EOP_DONE_BUSY 18 18 STRM_OUT_BUSY 19 19 PIPE_STATS_BUSY 20 20 RCIU_CE_BUSY 21 21 CE_PARSING_PACKETS 22 22 mmCP_STAT 0 0x21a0 24 0 4294967295 MIU_RDREQ_BUSY 7 7 MIU_WRREQ_BUSY 8 8 ROQ_RING_BUSY 9 9 ROQ_INDIRECT1_BUSY 10 10 ROQ_INDIRECT2_BUSY 11 11 ROQ_STATE_BUSY 12 12 DC_BUSY 13 13 PFP_BUSY 15 15 MEQ_BUSY 16 16 ME_BUSY 17 17 QUERY_BUSY 18 18 SEMAPHORE_BUSY 19 19 INTERRUPT_BUSY 20 20 SURFACE_SYNC_BUSY 21 21 DMA_BUSY 22 22 RCIU_BUSY 23 23 SCRATCH_RAM_BUSY 24 24 CPC_CPG_BUSY 25 25 CE_BUSY 26 26 TCIU_BUSY 27 27 ROQ_CE_RING_BUSY 28 28 ROQ_CE_INDIRECT1_BUSY 29 29 ROQ_CE_INDIRECT2_BUSY 30 30 CP_BUSY 31 31 mmCP_ME_HEADER_DUMP 0 0x21a1 1 0 4294967295 ME_HEADER_DUMP 0 31 mmCP_PFP_HEADER_DUMP 0 0x21a2 1 0 4294967295 PFP_HEADER_DUMP 0 31 mmCP_GRBM_FREE_COUNT 0 0x21a3 3 0 4294967295 FREE_COUNT 0 5 FREE_COUNT_GDS 8 13 FREE_COUNT_PFP 16 21 mmCP_CE_HEADER_DUMP 0 0x21a4 1 0 4294967295 CE_HEADER_DUMP 0 31 mmCP_MC_PACK_DELAY_CNT 0 0x21a7 1 0 4294967295 PACK_DELAY_CNT 0 4 mmCP_MC_TAG_CNTL 0 0x21a8 2 0 4294967295 TAG_RAM_INDEX 0 5 TAG_RAM_SEL 16 17 mmCP_MC_TAG_DATA 0 0x21a9 1 0 4294967295 TAG_RAM_DATA 0 31 mmCP_CSF_STAT 0 0x21b4 2 0 4294967295 BUFFER_SLOTS_ALLOCATED 0 3 BUFFER_REQUEST_COUNT 8 13 mmCP_CSF_CNTL 0 0x21b5 1 0 4294967295 FETCH_BUFFER_DEPTH 0 3 mmCP_ME_CNTL 0 0x21b6 9 0 4294967295 CE_INVALIDATE_ICACHE 4 4 PFP_INVALIDATE_ICACHE 6 6 ME_INVALIDATE_ICACHE 8 8 CE_HALT 24 24 CE_STEP 25 25 PFP_HALT 26 26 PFP_STEP 27 27 ME_HALT 28 28 ME_STEP 29 29 mmCP_CNTX_STAT 0 0x21b8 4 0 4294967295 ACTIVE_HP3D_CONTEXTS 0 7 CURRENT_HP3D_CONTEXT 8 10 ACTIVE_GFX_CONTEXTS 20 27 CURRENT_GFX_CONTEXT 28 30 mmCP_ME_PREEMPTION 0 0x21b9 1 0 4294967295 ME_CNTXSW_PREEMPTION 0 0 mmCP_RB0_RPTR 0 0x21c0 1 0 4294967295 RB_RPTR 0 19 mmCP_RB_RPTR 0 0x21c0 1 0 4294967295 RB_RPTR 0 19 mmCP_RB1_RPTR 0 0x21bf 1 0 4294967295 RB_RPTR 0 19 mmCP_RB2_RPTR 0 0x21be 1 0 4294967295 RB_RPTR 0 19 mmCP_RB_WPTR_DELAY 0 0x21c1 2 0 4294967295 PRE_WRITE_TIMER 0 27 PRE_WRITE_LIMIT 28 31 mmCP_RB_WPTR_POLL_CNTL 0 0x21c2 2 0 4294967295 POLL_FREQUENCY 0 15 IDLE_POLL_COUNT 16 31 mmCP_CE_INIT_BASE_LO 0 0xc0c3 1 0 4294967295 INIT_BASE_LO 5 31 mmCP_CE_INIT_BASE_HI 0 0xc0c4 1 0 4294967295 INIT_BASE_HI 0 15 mmCP_CE_INIT_BUFSZ 0 0xc0c5 1 0 4294967295 INIT_BUFSZ 0 11 mmCP_CE_IB1_BASE_LO 0 0xc0c6 1 0 4294967295 IB1_BASE_LO 2 31 mmCP_CE_IB1_BASE_HI 0 0xc0c7 1 0 4294967295 IB1_BASE_HI 0 15 mmCP_CE_IB1_BUFSZ 0 0xc0c8 1 0 4294967295 IB1_BUFSZ 0 19 mmCP_CE_IB2_BASE_LO 0 0xc0c9 1 0 4294967295 IB2_BASE_LO 2 31 mmCP_CE_IB2_BASE_HI 0 0xc0ca 1 0 4294967295 IB2_BASE_HI 0 15 mmCP_CE_IB2_BUFSZ 0 0xc0cb 1 0 4294967295 IB2_BUFSZ 0 19 mmCP_IB1_BASE_LO 0 0xc0cc 1 0 4294967295 IB1_BASE_LO 2 31 mmCP_IB1_BASE_HI 0 0xc0cd 1 0 4294967295 IB1_BASE_HI 0 15 mmCP_IB1_BUFSZ 0 0xc0ce 1 0 4294967295 IB1_BUFSZ 0 19 mmCP_IB2_BASE_LO 0 0xc0cf 1 0 4294967295 IB2_BASE_LO 2 31 mmCP_IB2_BASE_HI 0 0xc0d0 1 0 4294967295 IB2_BASE_HI 0 15 mmCP_IB2_BUFSZ 0 0xc0d1 1 0 4294967295 IB2_BUFSZ 0 19 mmCP_ST_BASE_LO 0 0xc0d2 1 0 4294967295 ST_BASE_LO 2 31 mmCP_ST_BASE_HI 0 0xc0d3 1 0 4294967295 ST_BASE_HI 0 15 mmCP_ST_BUFSZ 0 0xc0d4 1 0 4294967295 ST_BUFSZ 0 19 mmCP_ROQ_THRESHOLDS 0 0x21bc 2 0 4294967295 IB1_START 0 7 IB2_START 8 15 mmCP_MEQ_STQ_THRESHOLD 0 0x21bd 1 0 4294967295 STQ_START 0 7 mmCP_ROQ1_THRESHOLDS 0 0x21d5 4 0 4294967295 RB1_START 0 7 RB2_START 8 15 R0_IB1_START 16 23 R1_IB1_START 24 31 mmCP_ROQ2_THRESHOLDS 0 0x21d6 4 0 4294967295 R2_IB1_START 0 7 R0_IB2_START 8 15 R1_IB2_START 16 23 R2_IB2_START 24 31 mmCP_STQ_THRESHOLDS 0 0x21d7 3 0 4294967295 STQ0_START 0 7 STQ1_START 8 15 STQ2_START 16 23 mmCP_QUEUE_THRESHOLDS 0 0x21d8 2 0 4294967295 ROQ_IB1_START 0 5 ROQ_IB2_START 8 13 mmCP_MEQ_THRESHOLDS 0 0x21d9 2 0 4294967295 MEQ1_START 0 7 MEQ2_START 8 15 mmCP_ROQ_AVAIL 0 0x21da 2 0 4294967295 ROQ_CNT_RING 0 10 ROQ_CNT_IB1 16 26 mmCP_STQ_AVAIL 0 0x21db 1 0 4294967295 STQ_CNT 0 8 mmCP_ROQ2_AVAIL 0 0x21dc 1 0 4294967295 ROQ_CNT_IB2 0 10 mmCP_MEQ_AVAIL 0 0x21dd 1 0 4294967295 MEQ_CNT 0 9 mmCP_CMD_INDEX 0 0x21de 3 0 4294967295 CMD_INDEX 0 10 CMD_ME_SEL 12 13 CMD_QUEUE_SEL 16 17 mmCP_CMD_DATA 0 0x21df 1 0 4294967295 CMD_DATA 0 31 mmCP_ROQ_RB_STAT 0 0x21e0 2 0 4294967295 ROQ_RPTR_PRIMARY 0 9 ROQ_WPTR_PRIMARY 16 25 mmCP_ROQ_IB1_STAT 0 0x21e1 2 0 4294967295 ROQ_RPTR_INDIRECT1 0 9 ROQ_WPTR_INDIRECT1 16 25 mmCP_ROQ_IB2_STAT 0 0x21e2 2 0 4294967295 ROQ_RPTR_INDIRECT2 0 9 ROQ_WPTR_INDIRECT2 16 25 mmCP_STQ_STAT 0 0x21e3 1 0 4294967295 STQ_RPTR 0 9 mmCP_STQ_WR_STAT 0 0x21e4 1 0 4294967295 STQ_WPTR 0 9 mmCP_MEQ_STAT 0 0x21e5 2 0 4294967295 MEQ_RPTR 0 9 MEQ_WPTR 16 25 mmCP_CEQ1_AVAIL 0 0x21e6 2 0 4294967295 CEQ_CNT_RING 0 10 CEQ_CNT_IB1 16 26 mmCP_CEQ2_AVAIL 0 0x21e7 1 0 4294967295 CEQ_CNT_IB2 0 10 mmCP_CE_ROQ_RB_STAT 0 0x21e8 2 0 4294967295 CEQ_RPTR_PRIMARY 0 9 CEQ_WPTR_PRIMARY 16 25 mmCP_CE_ROQ_IB1_STAT 0 0x21e9 2 0 4294967295 CEQ_RPTR_INDIRECT1 0 9 CEQ_WPTR_INDIRECT1 16 25 mmCP_CE_ROQ_IB2_STAT 0 0x21ea 2 0 4294967295 CEQ_RPTR_INDIRECT2 0 9 CEQ_WPTR_INDIRECT2 16 25 mmCP_INT_STAT_DEBUG 0 0x21f7 12 0 4294967295 CP_ECC_ERROR_INT_ASSERTED 14 14 WRM_POLL_TIMEOUT_INT_ASSERTED 17 17 CNTX_BUSY_INT_ASSERTED 19 19 CNTX_EMPTY_INT_ASSERTED 20 20 PRIV_INSTR_INT_ASSERTED 22 22 PRIV_REG_INT_ASSERTED 23 23 OPCODE_ERROR_INT_ASSERTED 24 24 TIME_STAMP_INT_ASSERTED 26 26 RESERVED_BIT_ERROR_INT_ASSERTED 27 27 GENERIC2_INT_ASSERTED 29 29 GENERIC1_INT_ASSERTED 30 30 GENERIC0_INT_ASSERTED 31 31 mmCP_PERFMON_CNTL 0 0xd808 4 0 4294967295 PERFMON_STATE 0 3 SPM_PERFMON_STATE 4 7 PERFMON_ENABLE_MODE 8 9 PERFMON_SAMPLE_ENABLE 10 10 mmCP_PERFMON_CNTX_CNTL 0 0xa0d8 1 0 4294967295 PERFMON_ENABLE 31 31 mmCP_RINGID 0 0xa0d9 1 0 4294967295 RINGID 0 1 mmCP_PIPEID 0 0xa0d9 1 0 4294967295 PIPE_ID 0 1 mmCP_VMID 0 0xa0da 1 0 4294967295 VMID 0 3 mmCP_HPD_ROQ_OFFSETS 0 0x3240 3 0 4294967295 IQ_OFFSET 0 2 PQ_OFFSET 8 13 IB_OFFSET 16 21 mmCP_HPD_EOP_BASE_ADDR 0 0x3241 1 0 4294967295 BASE_ADDR 0 31 mmCP_HPD_EOP_BASE_ADDR_HI 0 0x3242 1 0 4294967295 BASE_ADDR_HI 0 7 mmCP_HPD_EOP_VMID 0 0x3243 1 0 4294967295 VMID 0 3 mmCP_HPD_EOP_CONTROL 0 0x3244 11 0 4294967295 EOP_SIZE 0 5 PROCESSING_EOP 8 8 PROCESSING_QID 9 11 PROCESS_EOP_EN 12 12 PROCESSING_EOPIB 13 13 PROCESS_EOPIB_EN 14 14 EOP_ATC 23 23 CACHE_POLICY 24 25 EOP_VOLATILE 26 26 PEND_Q_SEM 28 30 PEND_SIG_SEM 31 31 mmCP_MQD_BASE_ADDR 0 0x3245 1 0 4294967295 BASE_ADDR 2 31 mmCP_MQD_BASE_ADDR_HI 0 0x3246 1 0 4294967295 BASE_ADDR_HI 0 15 mmCP_HQD_ACTIVE 0 0x3247 1 0 4294967295 ACTIVE 0 0 mmCP_HQD_VMID 0 0x3248 3 0 4294967295 VMID 0 3 IB_VMID 8 11 VQID 16 25 mmCP_HQD_PERSISTENT_STATE 0 0x3249 3 0 4294967295 PRELOAD_REQ 0 0 PRELOAD_SIZE 8 17 DISP_ACTIVE 31 31 mmCP_HQD_PIPE_PRIORITY 0 0x324a 1 0 4294967295 PIPE_PRIORITY 0 1 mmCP_HQD_QUEUE_PRIORITY 0 0x324b 1 0 4294967295 PRIORITY_LEVEL 0 3 mmCP_HQD_QUANTUM 0 0x324c 3 0 4294967295 QUANTUM_EN 0 0 QUANTUM_SCALE 4 4 QUANTUM_DURATION 8 13 mmCP_HQD_PQ_BASE 0 0x324d 1 0 4294967295 ADDR 0 31 mmCP_HQD_PQ_BASE_HI 0 0x324e 1 0 4294967295 ADDR_HI 0 7 mmCP_HQD_PQ_RPTR 0 0x324f 1 0 4294967295 CONSUMED_OFFSET 0 31 mmCP_HQD_PQ_RPTR_REPORT_ADDR 0 0x3250 1 0 4294967295 RPTR_REPORT_ADDR 2 31 mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0 0x3251 1 0 4294967295 RPTR_REPORT_ADDR_HI 0 15 mmCP_HQD_PQ_WPTR_POLL_ADDR 0 0x3252 1 0 4294967295 WPTR_ADDR 2 31 mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0 0x3253 1 0 4294967295 WPTR_ADDR_HI 0 15 mmCP_HQD_PQ_DOORBELL_CONTROL 0 0x3254 5 0 4294967295 DOORBELL_OFFSET 2 22 DOORBELL_SOURCE 28 28 DOORBELL_SCHD_HIT 29 29 DOORBELL_EN 30 30 DOORBELL_HIT 31 31 mmCP_HQD_PQ_WPTR 0 0x3255 1 0 4294967295 OFFSET 0 31 mmCP_HQD_PQ_CONTROL 0 0x3256 12 0 4294967295 QUEUE_SIZE 0 5 RPTR_BLOCK_SIZE 8 13 ENDIAN_SWAP 16 17 MIN_AVAIL_SIZE 20 21 PQ_ATC 23 23 CACHE_POLICY 24 25 PQ_VOLATILE 26 26 NO_UPDATE_RPTR 27 27 UNORD_DISPATCH 28 28 ROQ_PQ_IB_FLIP 29 29 PRIV_STATE 30 30 KMD_QUEUE 31 31 mmCP_HQD_IB_BASE_ADDR 0 0x3257 1 0 4294967295 IB_BASE_ADDR 2 31 mmCP_HQD_IB_BASE_ADDR_HI 0 0x3258 1 0 4294967295 IB_BASE_ADDR_HI 0 15 mmCP_HQD_IB_RPTR 0 0x3259 1 0 4294967295 CONSUMED_OFFSET 0 19 mmCP_HQD_IB_CONTROL 0 0x325a 6 0 4294967295 IB_SIZE 0 19 MIN_IB_AVAIL_SIZE 20 21 IB_ATC 23 23 IB_CACHE_POLICY 24 25 IB_VOLATILE 26 26 PROCESSING_IB 31 31 mmCP_HQD_IQ_TIMER 0 0x325b 10 0 4294967295 WAIT_TIME 0 7 RETRY_TYPE 8 10 INTERRUPT_TYPE 12 13 INTERRUPT_SIZE 16 21 IQ_ATC 23 23 CACHE_POLICY 24 25 IQ_VOLATILE 26 26 PROCESS_IQ_EN 29 29 PROCESSING_IQ 30 30 ACTIVE 31 31 mmCP_HQD_IQ_RPTR 0 0x325c 1 0 4294967295 OFFSET 0 5 mmCP_HQD_DEQUEUE_REQUEST 0 0x325d 3 0 4294967295 DEQUEUE_REQ 0 1 IQ_REQ_PEND 4 4 DEQUEUE_INT 8 8 mmCP_HQD_DMA_OFFLOAD 0 0x325e 1 0 4294967295 DMA_OFFLOAD 0 0 mmCP_HQD_SEMA_CMD 0 0x325f 2 0 4294967295 RETRY 0 0 RESULT 1 2 mmCP_HQD_MSG_TYPE 0 0x3260 1 0 4294967295 ACTION 0 1 mmCP_HQD_ATOMIC0_PREOP_LO 0 0x3261 1 0 4294967295 ATOMIC0_PREOP_LO 0 31 mmCP_HQD_ATOMIC0_PREOP_HI 0 0x3262 1 0 4294967295 ATOMIC0_PREOP_HI 0 31 mmCP_HQD_ATOMIC1_PREOP_LO 0 0x3263 1 0 4294967295 ATOMIC1_PREOP_LO 0 31 mmCP_HQD_ATOMIC1_PREOP_HI 0 0x3264 1 0 4294967295 ATOMIC1_PREOP_HI 0 31 mmCP_HQD_HQ_SCHEDULER0 0 0x3265 9 0 4294967295 DEQUEUE_STATUS 0 1 DEQUEUE_RETRY_CNT 2 3 RSV_5_4 4 5 QUEUE_RUN_ONCE 6 6 SCRATCH_RAM_INIT 7 7 TCL2_DIRTY 8 8 PG_ACTIVATED 9 9 CG_ACTIVATED 10 10 RSVR_31_11 11 31 mmCP_HQD_HQ_SCHEDULER1 0 0x3266 1 0 4294967295 SCHEDULER 0 31 mmCP_MQD_CONTROL 0 0x3267 4 0 4294967295 VMID 0 3 MQD_ATC 23 23 CACHE_POLICY 24 25 MQD_VOLATILE 26 26 mmDB_Z_READ_BASE 0 0xa012 1 0 4294967295 BASE_256B 0 31 mmDB_STENCIL_READ_BASE 0 0xa013 1 0 4294967295 BASE_256B 0 31 mmDB_Z_WRITE_BASE 0 0xa014 1 0 4294967295 BASE_256B 0 31 mmDB_STENCIL_WRITE_BASE 0 0xa015 1 0 4294967295 BASE_256B 0 31 mmDB_DEPTH_INFO 0 0xa00f 7 0 4294967295 ADDR5_SWIZZLE_MASK 0 3 ARRAY_MODE 4 7 PIPE_CONFIG 8 12 BANK_WIDTH 13 14 BANK_HEIGHT 15 16 MACRO_TILE_ASPECT 17 18 NUM_BANKS 19 20 mmDB_Z_INFO 0 0xa010 8 0 4294967295 FORMAT 0 1 NUM_SAMPLES 2 3 TILE_SPLIT 13 15 TILE_MODE_INDEX 20 22 ALLOW_EXPCLEAR 27 27 READ_SIZE 28 28 TILE_SURFACE_ENABLE 29 29 ZRANGE_PRECISION 31 31 mmDB_STENCIL_INFO 0 0xa011 5 0 4294967295 FORMAT 0 0 TILE_SPLIT 13 15 TILE_MODE_INDEX 20 22 ALLOW_EXPCLEAR 27 27 TILE_STENCIL_DISABLE 29 29 mmDB_DEPTH_SIZE 0 0xa016 2 0 4294967295 PITCH_TILE_MAX 0 10 HEIGHT_TILE_MAX 11 21 mmDB_DEPTH_SLICE 0 0xa017 1 0 4294967295 SLICE_TILE_MAX 0 21 mmDB_DEPTH_VIEW 0 0xa002 4 0 4294967295 SLICE_START 0 10 SLICE_MAX 13 23 Z_READ_ONLY 24 24 STENCIL_READ_ONLY 25 25 mmDB_RENDER_CONTROL 0 0xa000 9 0 4294967295 DEPTH_CLEAR_ENABLE 0 0 STENCIL_CLEAR_ENABLE 1 1 DEPTH_COPY 2 2 STENCIL_COPY 3 3 RESUMMARIZE_ENABLE 4 4 STENCIL_COMPRESS_DISABLE 5 5 DEPTH_COMPRESS_DISABLE 6 6 COPY_CENTROID 7 7 COPY_SAMPLE 8 11 mmDB_COUNT_CONTROL 0 0xa001 9 0 4294967295 ZPASS_INCREMENT_DISABLE 0 0 PERFECT_ZPASS_COUNTS 1 1 SAMPLE_RATE 4 6 ZPASS_ENABLE 8 11 ZFAIL_ENABLE 12 15 SFAIL_ENABLE 16 19 DBFAIL_ENABLE 20 23 SLICE_EVEN_ENABLE 24 27 SLICE_ODD_ENABLE 28 31 mmDB_RENDER_OVERRIDE 0 0xa003 23 0 4294967295 FORCE_HIZ_ENABLE 0 1 FORCE_HIS_ENABLE0 2 3 FORCE_HIS_ENABLE1 4 5 FORCE_SHADER_Z_ORDER 6 6 FAST_Z_DISABLE 7 7 FAST_STENCIL_DISABLE 8 8 NOOP_CULL_DISABLE 9 9 FORCE_COLOR_KILL 10 10 FORCE_Z_READ 11 11 FORCE_STENCIL_READ 12 12 FORCE_FULL_Z_RANGE 13 14 FORCE_QC_SMASK_CONFLICT 15 15 DISABLE_VIEWPORT_CLAMP 16 16 IGNORE_SC_ZRANGE 17 17 DISABLE_FULLY_COVERED 18 18 FORCE_Z_LIMIT_SUMM 19 20 MAX_TILES_IN_DTT 21 25 DISABLE_TILE_RATE_TILES 26 26 FORCE_Z_DIRTY 27 27 FORCE_STENCIL_DIRTY 28 28 FORCE_Z_VALID 29 29 FORCE_STENCIL_VALID 30 30 PRESERVE_COMPRESSION 31 31 mmDB_RENDER_OVERRIDE2 0 0xa004 15 0 4294967295 PARTIAL_SQUAD_LAUNCH_CONTROL 0 1 PARTIAL_SQUAD_LAUNCH_COUNTDOWN 2 4 DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION 5 5 DISABLE_SMEM_EXPCLEAR_OPTIMIZATION 6 6 DISABLE_COLOR_ON_VALIDATION 7 7 DECOMPRESS_Z_ON_FLUSH 8 8 DISABLE_REG_SNOOP 9 9 DEPTH_BOUNDS_HIER_DEPTH_DISABLE 10 10 SEPARATE_HIZS_FUNC_ENABLE 11 11 HIZ_ZFUNC 12 14 HIS_SFUNC_FF 15 17 HIS_SFUNC_BF 18 20 PRESERVE_ZRANGE 21 21 PRESERVE_SRESULTS 22 22 DISABLE_FAST_PASS 23 23 mmDB_EQAA 0 0xa201 12 0 4294967295 MAX_ANCHOR_SAMPLES 0 2 PS_ITER_SAMPLES 4 6 MASK_EXPORT_NUM_SAMPLES 8 10 ALPHA_TO_MASK_NUM_SAMPLES 12 14 HIGH_QUALITY_INTERSECTIONS 16 16 INCOHERENT_EQAA_READS 17 17 INTERPOLATE_COMP_Z 18 18 INTERPOLATE_SRC_Z 19 19 STATIC_ANCHOR_ASSOCIATIONS 20 20 ALPHA_TO_MASK_EQAA_DISABLE 21 21 OVERRASTERIZATION_AMOUNT 24 26 ENABLE_POSTZ_OVERRASTERIZATION 27 27 mmDB_SHADER_CONTROL 0 0xa203 12 0 4294967295 Z_EXPORT_ENABLE 0 0 STENCIL_TEST_VAL_EXPORT_ENABLE 1 1 STENCIL_OP_VAL_EXPORT_ENABLE 2 2 Z_ORDER 4 5 KILL_ENABLE 6 6 COVERAGE_TO_MASK_ENABLE 7 7 MASK_EXPORT_ENABLE 8 8 EXEC_ON_HIER_FAIL 9 9 EXEC_ON_NOOP 10 10 ALPHA_TO_MASK_DISABLE 11 11 DEPTH_BEFORE_SHADER 12 12 CONSERVATIVE_Z_EXPORT 13 14 mmDB_DEPTH_BOUNDS_MIN 0 0xa008 1 0 4294967295 MIN 0 31 mmDB_DEPTH_BOUNDS_MAX 0 0xa009 1 0 4294967295 MAX 0 31 mmDB_STENCIL_CLEAR 0 0xa00a 1 0 4294967295 CLEAR 0 7 mmDB_DEPTH_CLEAR 0 0xa00b 1 0 4294967295 DEPTH_CLEAR 0 31 mmDB_HTILE_DATA_BASE 0 0xa005 1 0 4294967295 BASE_256B 0 31 mmDB_HTILE_SURFACE 0 0xa2af 7 0 4294967295 LINEAR 0 0 FULL_CACHE 1 1 HTILE_USES_PRELOAD_WIN 2 2 PRELOAD 3 3 PREFETCH_WIDTH 4 9 PREFETCH_HEIGHT 10 15 DST_OUTSIDE_ZERO_TO_ONE 16 16 mmDB_PRELOAD_CONTROL 0 0xa2b2 4 0 4294967295 START_X 0 7 START_Y 8 15 MAX_X 16 23 MAX_Y 24 31 mmDB_STENCILREFMASK 0 0xa10c 4 0 4294967295 STENCILTESTVAL 0 7 STENCILMASK 8 15 STENCILWRITEMASK 16 23 STENCILOPVAL 24 31 mmDB_STENCILREFMASK_BF 0 0xa10d 4 0 4294967295 STENCILTESTVAL_BF 0 7 STENCILMASK_BF 8 15 STENCILWRITEMASK_BF 16 23 STENCILOPVAL_BF 24 31 mmDB_SRESULTS_COMPARE_STATE0 0 0xa2b0 4 0 4294967295 COMPAREFUNC0 0 2 COMPAREVALUE0 4 11 COMPAREMASK0 12 19 ENABLE0 24 24 mmDB_SRESULTS_COMPARE_STATE1 0 0xa2b1 4 0 4294967295 COMPAREFUNC1 0 2 COMPAREVALUE1 4 11 COMPAREMASK1 12 19 ENABLE1 24 24 mmDB_DEPTH_CONTROL 0 0xa200 10 0 4294967295 STENCIL_ENABLE 0 0 Z_ENABLE 1 1 Z_WRITE_ENABLE 2 2 DEPTH_BOUNDS_ENABLE 3 3 ZFUNC 4 6 BACKFACE_ENABLE 7 7 STENCILFUNC 8 10 STENCILFUNC_BF 20 22 ENABLE_COLOR_WRITES_ON_DEPTH_FAIL 30 30 DISABLE_COLOR_WRITES_ON_DEPTH_PASS 31 31 mmDB_STENCIL_CONTROL 0 0xa10b 6 0 4294967295 STENCILFAIL 0 3 STENCILZPASS 4 7 STENCILZFAIL 8 11 STENCILFAIL_BF 12 15 STENCILZPASS_BF 16 19 STENCILZFAIL_BF 20 23 mmDB_ALPHA_TO_MASK 0 0xa2dc 6 0 4294967295 ALPHA_TO_MASK_ENABLE 0 0 ALPHA_TO_MASK_OFFSET0 8 9 ALPHA_TO_MASK_OFFSET1 10 11 ALPHA_TO_MASK_OFFSET2 12 13 ALPHA_TO_MASK_OFFSET3 14 15 OFFSET_ROUND 16 16 mmDB_PERFCOUNTER0_SELECT 0 0xdc40 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER1_SELECT 0 0xdc42 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER2_SELECT 0 0xdc44 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER3_SELECT 0 0xdc46 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmDB_PERFCOUNTER0_SELECT1 0 0xdc41 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmDB_PERFCOUNTER1_SELECT1 0 0xdc43 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmDB_PERFCOUNTER0_LO 0 0xd440 1 0 4294967295 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER1_LO 0 0xd442 1 0 4294967295 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER2_LO 0 0xd444 1 0 4294967295 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER3_LO 0 0xd446 1 0 4294967295 PERFCOUNTER_LO 0 31 mmDB_PERFCOUNTER0_HI 0 0xd441 1 0 4294967295 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER1_HI 0 0xd443 1 0 4294967295 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER2_HI 0 0xd445 1 0 4294967295 PERFCOUNTER_HI 0 31 mmDB_PERFCOUNTER3_HI 0 0xd447 1 0 4294967295 PERFCOUNTER_HI 0 31 mmDB_DEBUG 0 0x260c 24 0 4294967295 DEBUG_STENCIL_COMPRESS_DISABLE 0 0 DEBUG_DEPTH_COMPRESS_DISABLE 1 1 FETCH_FULL_Z_TILE 2 2 FETCH_FULL_STENCIL_TILE 3 3 FORCE_Z_MODE 4 5 DEBUG_FORCE_DEPTH_READ 6 6 DEBUG_FORCE_STENCIL_READ 7 7 DEBUG_FORCE_HIZ_ENABLE 8 9 DEBUG_FORCE_HIS_ENABLE0 10 11 DEBUG_FORCE_HIS_ENABLE1 12 13 DEBUG_FAST_Z_DISABLE 14 14 DEBUG_FAST_STENCIL_DISABLE 15 15 DEBUG_NOOP_CULL_DISABLE 16 16 DISABLE_SUMM_SQUADS 17 17 DEPTH_CACHE_FORCE_MISS 18 18 DEBUG_FORCE_FULL_Z_RANGE 19 20 NEVER_FREE_Z_ONLY 21 21 ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS 22 22 DISABLE_VPORT_ZPLANE_OPTIMIZATION 23 23 DECOMPRESS_AFTER_N_ZPLANES 24 27 ONE_FREE_IN_FLIGHT 28 28 FORCE_MISS_IF_NOT_INFLIGHT 29 29 DISABLE_DEPTH_SURFACE_SYNC 30 30 DISABLE_HTILE_SURFACE_SYNC 31 31 mmDB_DEBUG2 0 0x260d 20 0 4294967295 ALLOW_COMPZ_BYTE_MASKING 0 0 DISABLE_TC_ZRANGE_L0_CACHE 1 1 DISABLE_TC_MASK_L0_CACHE 2 2 DTR_ROUND_ROBIN_ARB 3 3 DTR_PREZ_STALLS_FOR_ETF_ROOM 4 4 DISABLE_PREZL_LPF_STALL 5 5 ENABLE_PREZL_CB_STALL 6 6 DISABLE_PREZL_LPF_STALL_REZ 7 7 DISABLE_PREZL_CB_STALL_REZ 8 8 CLK_OFF_DELAY 9 13 DISABLE_TILE_COVERED_FOR_PS_ITER 14 14 ENABLE_SUBTILE_GROUPING 15 15 DISABLE_HTILE_PAIRED_PIPES 16 16 DISABLE_NULL_EOT_FORWARDING 17 17 DISABLE_DTT_DATA_FORWARDING 18 18 DISABLE_QUAD_COHERENCY_STALL 19 19 ENABLE_PREZ_OF_REZ_SUMM 28 28 DISABLE_PREZL_VIEWPORT_STALL 29 29 DISABLE_SINGLE_STENCIL_QUAD_SUMM 30 30 DISABLE_WRITE_STALL_ON_RDWR_CONFLICT 31 31 mmDB_DEBUG3 0 0x260e 29 0 4294967295 FORCE_DB_IS_GOOD 2 2 DISABLE_TL_SSO_NULL_SUPPRESSION 3 3 DISABLE_HIZ_ON_VPORT_CLAMP 4 4 EQAA_INTERPOLATE_COMP_Z 5 5 EQAA_INTERPOLATE_SRC_Z 6 6 DISABLE_TCP_CAM_BYPASS 7 7 DISABLE_ZCMP_DIRTY_SUPPRESSION 8 8 DISABLE_REDUNDANT_PLANE_FLUSHES_OPT 9 9 DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP 10 10 ENABLE_INCOHERENT_EQAA_READS 11 11 DISABLE_OP_Z_DATA_FORWARDING 12 12 DISABLE_OP_DF_BYPASS 13 13 DISABLE_OP_DF_WRITE_COMBINE 14 14 DISABLE_OP_DF_DIRECT_FEEDBACK 15 15 ALLOW_RF2P_RW_COLLISION 16 16 SLOW_PREZ_TO_A2M_OMASK_RATE 17 17 DISABLE_OP_S_DATA_FORWARDING 18 18 DISABLE_TC_UPDATE_WRITE_COMBINE 19 19 DISABLE_HZ_TC_WRITE_COMBINE 20 20 ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT 21 21 ENABLE_TC_MA_ROUND_ROBIN_ARB 22 22 DISABLE_RAM_READ_SUPPRESION_ON_FWD 23 23 DISABLE_EQAA_A2M_PERF_OPT 24 24 DISABLE_DI_DT_STALL 25 25 ENABLE_DB_PROCESS_RESET 26 26 DISABLE_OVERRASTERIZATION_FIX 27 27 DONT_INSERT_CONTEXT_SUSPEND 28 28 DONT_DELETE_CONTEXT_SUSPEND 29 29 DB_EXTRA_DEBUG3 30 31 mmDB_DEBUG4 0 0x260f 5 0 4294967295 DISABLE_QC_Z_MASK_SUMMATION 0 0 DISABLE_QC_STENCIL_MASK_SUMMATION 1 1 DISABLE_RESUMM_TO_SINGLE_STENCIL 2 2 DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL 3 3 DB_EXTRA_DEBUG4 4 31 mmDB_CREDIT_LIMIT 0 0x2614 4 0 4294967295 DB_SC_TILE_CREDITS 0 4 DB_SC_QUAD_CREDITS 5 9 DB_CB_LQUAD_CREDITS 10 12 DB_CB_TILE_CREDITS 24 30 mmDB_WATERMARKS 0 0x2615 10 0 4294967295 DEPTH_FREE 0 4 DEPTH_FLUSH 5 10 FORCE_SUMMARIZE 11 14 DEPTH_PENDING_FREE 15 19 DEPTH_CACHELINE_FREE 20 26 EARLY_Z_PANIC_DISABLE 27 27 LATE_Z_PANIC_DISABLE 28 28 RE_Z_PANIC_DISABLE 29 29 AUTO_FLUSH_HTILE 30 30 AUTO_FLUSH_QUAD 31 31 mmDB_SUBTILE_CONTROL 0 0x2616 10 0 4294967295 MSAA1_X 0 1 MSAA1_Y 2 3 MSAA2_X 4 5 MSAA2_Y 6 7 MSAA4_X 8 9 MSAA4_Y 10 11 MSAA8_X 12 13 MSAA8_Y 14 15 MSAA16_X 16 17 MSAA16_Y 18 19 mmDB_FREE_CACHELINES 0 0x2617 5 0 4294967295 FREE_DTILE_DEPTH 0 6 FREE_PLANE_DEPTH 7 13 FREE_Z_DEPTH 14 20 FREE_HTILE_DEPTH 21 24 QUAD_READ_REQS 25 31 mmDB_FIFO_DEPTH1 0 0x2618 5 0 4294967295 MI_RDREQ_FIFO_DEPTH 0 4 MI_WRREQ_FIFO_DEPTH 5 9 MCC_DEPTH 10 15 QC_DEPTH 16 20 LTILE_PROBE_FIFO_DEPTH 21 28 mmDB_FIFO_DEPTH2 0 0x2619 4 0 4294967295 EQUAD_FIFO_DEPTH 0 7 ETILE_OP_FIFO_DEPTH 8 14 LQUAD_FIFO_DEPTH 15 24 LTILE_OP_FIFO_DEPTH 25 31 mmDB_CGTT_CLK_CTRL_0 0 0xf0a4 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmDB_ZPASS_COUNT_LOW 0 0xc3fe 1 0 4294967295 COUNT_LOW 0 31 mmDB_ZPASS_COUNT_HI 0 0xc3ff 1 0 4294967295 COUNT_HI 0 30 mmDB_RING_CONTROL 0 0x261b 1 0 4294967295 COUNTER_CONTROL 0 1 mmDB_READ_DEBUG_0 0 0x2620 1 0 4294967295 BUSY_DATA0 0 31 mmDB_READ_DEBUG_1 0 0x2621 1 0 4294967295 BUSY_DATA1 0 31 mmDB_READ_DEBUG_2 0 0x2622 1 0 4294967295 BUSY_DATA2 0 31 mmDB_READ_DEBUG_3 0 0x2623 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_4 0 0x2624 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_5 0 0x2625 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_6 0 0x2626 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_7 0 0x2627 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_8 0 0x2628 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_9 0 0x2629 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_A 0 0x262a 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_B 0 0x262b 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_C 0 0x262c 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_D 0 0x262d 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_E 0 0x262e 1 0 4294967295 DEBUG_DATA 0 31 mmDB_READ_DEBUG_F 0 0x262f 1 0 4294967295 DEBUG_DATA 0 31 mmDB_OCCLUSION_COUNT0_LOW 0 0xc3c0 1 0 4294967295 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT0_HI 0 0xc3c1 1 0 4294967295 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT1_LOW 0 0xc3c2 1 0 4294967295 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT1_HI 0 0xc3c3 1 0 4294967295 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT2_LOW 0 0xc3c4 1 0 4294967295 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT2_HI 0 0xc3c5 1 0 4294967295 COUNT_HI 0 30 mmDB_OCCLUSION_COUNT3_LOW 0 0xc3c6 1 0 4294967295 COUNT_LOW 0 31 mmDB_OCCLUSION_COUNT3_HI 0 0xc3c7 1 0 4294967295 COUNT_HI 0 30 mmCC_RB_REDUNDANCY 0 0x263c 4 0 4294967295 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 mmCC_RB_BACKEND_DISABLE 0 0x263d 1 0 4294967295 BACKEND_DISABLE 16 23 mmGC_USER_RB_REDUNDANCY 0 0x26de 4 0 4294967295 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 mmGC_USER_RB_BACKEND_DISABLE 0 0x26df 1 0 4294967295 BACKEND_DISABLE 16 23 mmGB_ADDR_CONFIG 0 0x263e 9 0 4294967295 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 4 6 BANK_INTERLEAVE_SIZE 8 10 NUM_SHADER_ENGINES 12 13 SHADER_ENGINE_TILE_SIZE 16 18 NUM_GPUS 20 22 MULTI_GPU_TILE_SIZE 24 25 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 mmGB_BACKEND_MAP 0 0x263f 1 0 4294967295 BACKEND_MAP 0 31 mmGB_GPU_ID 0 0x2640 1 0 4294967295 GPU_ID 0 3 mmCC_RB_DAISY_CHAIN 0 0x2641 8 0 4294967295 RB_0 0 3 RB_1 4 7 RB_2 8 11 RB_3 12 15 RB_4 16 19 RB_5 20 23 RB_6 24 27 RB_7 28 31 mmGB_TILE_MODE0 0 0x2644 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE1 0 0x2645 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE2 0 0x2646 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE3 0 0x2647 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE4 0 0x2648 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE5 0 0x2649 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE6 0 0x264a 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE7 0 0x264b 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE8 0 0x264c 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE9 0 0x264d 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE10 0 0x264e 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE11 0 0x264f 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE12 0 0x2650 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE13 0 0x2651 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE14 0 0x2652 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE15 0 0x2653 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE16 0 0x2654 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE17 0 0x2655 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE18 0 0x2656 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE19 0 0x2657 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE20 0 0x2658 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE21 0 0x2659 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE22 0 0x265a 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE23 0 0x265b 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE24 0 0x265c 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE25 0 0x265d 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE26 0 0x265e 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE27 0 0x265f 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE28 0 0x2660 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE29 0 0x2661 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE30 0 0x2662 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_TILE_MODE31 0 0x2663 5 0 4294967295 ARRAY_MODE 2 5 PIPE_CONFIG 6 10 TILE_SPLIT 11 13 MICRO_TILE_MODE_NEW 22 24 SAMPLE_SPLIT 25 26 mmGB_MACROTILE_MODE0 0 0x2664 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE1 0 0x2665 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE2 0 0x2666 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE3 0 0x2667 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE4 0 0x2668 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE5 0 0x2669 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE6 0 0x266a 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE7 0 0x266b 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE8 0 0x266c 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE9 0 0x266d 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE10 0 0x266e 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE11 0 0x266f 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE12 0 0x2670 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE13 0 0x2671 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE14 0 0x2672 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_MACROTILE_MODE15 0 0x2673 4 0 4294967295 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 mmGB_EDC_MODE 0 0x307e 4 0 4294967295 FORCE_SEC_ON_DED 16 16 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmCC_GC_EDC_CONFIG 0 0x3098 1 0 4294967295 DIS_EDC 1 1 mmRAS_SIGNATURE_CONTROL 0 0x3380 1 0 4294967295 ENABLE 0 0 mmRAS_SIGNATURE_MASK 0 0x3381 1 0 4294967295 INPUT_BUS_MASK 0 31 mmRAS_SX_SIGNATURE0 0 0x3382 1 0 4294967295 SIGNATURE 0 31 mmRAS_SX_SIGNATURE1 0 0x3383 1 0 4294967295 SIGNATURE 0 31 mmRAS_SX_SIGNATURE2 0 0x3384 1 0 4294967295 SIGNATURE 0 31 mmRAS_SX_SIGNATURE3 0 0x3385 1 0 4294967295 SIGNATURE 0 31 mmRAS_DB_SIGNATURE0 0 0x338b 1 0 4294967295 SIGNATURE 0 31 mmRAS_PA_SIGNATURE0 0 0x338c 1 0 4294967295 SIGNATURE 0 31 mmRAS_VGT_SIGNATURE0 0 0x338d 1 0 4294967295 SIGNATURE 0 31 mmRAS_SQ_SIGNATURE0 0 0x338e 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE0 0 0x338f 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE1 0 0x3390 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE2 0 0x3391 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE3 0 0x3392 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE4 0 0x3393 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE5 0 0x3394 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE6 0 0x3395 1 0 4294967295 SIGNATURE 0 31 mmRAS_SC_SIGNATURE7 0 0x3396 1 0 4294967295 SIGNATURE 0 31 mmRAS_IA_SIGNATURE0 0 0x3397 1 0 4294967295 SIGNATURE 0 31 mmRAS_IA_SIGNATURE1 0 0x3398 1 0 4294967295 SIGNATURE 0 31 mmRAS_SPI_SIGNATURE0 0 0x3399 1 0 4294967295 SIGNATURE 0 31 mmRAS_SPI_SIGNATURE1 0 0x339a 1 0 4294967295 SIGNATURE 0 31 mmRAS_TA_SIGNATURE0 0 0x339b 1 0 4294967295 SIGNATURE 0 31 mmRAS_TD_SIGNATURE0 0 0x339c 1 0 4294967295 SIGNATURE 0 31 mmRAS_CB_SIGNATURE0 0 0x339d 1 0 4294967295 SIGNATURE 0 31 mmRAS_BCI_SIGNATURE0 0 0x339e 1 0 4294967295 SIGNATURE 0 31 mmRAS_BCI_SIGNATURE1 0 0x339f 1 0 4294967295 SIGNATURE 0 31 mmGRBM_CAM_INDEX 0 0x3000 1 0 4294967295 CAM_INDEX 0 2 mmGRBM_CAM_DATA 0 0x3001 2 0 4294967295 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 mmGRBM_CNTL 0 0x2000 1 0 4294967295 READ_TIMEOUT 0 7 mmGRBM_SKEW_CNTL 0 0x2001 2 0 4294967295 SKEW_TOP_THRESHOLD 0 5 SKEW_COUNT 6 11 mmGRBM_PWR_CNTL 0 0x2003 2 0 4294967295 REQ_TYPE 0 3 RSP_TYPE 4 7 mmGRBM_STATUS 0 0x2004 24 0 4294967295 ME0PIPE0_CMDFIFO_AVAIL 0 3 SRBM_RQ_PENDING 5 5 ME0PIPE0_CF_RQ_PENDING 7 7 ME0PIPE0_PF_RQ_PENDING 8 8 GDS_DMA_RQ_PENDING 9 9 DB_CLEAN 12 12 CB_CLEAN 13 13 TA_BUSY 14 14 GDS_BUSY 15 15 WD_BUSY_NO_DMA 16 16 VGT_BUSY 17 17 IA_BUSY_NO_DMA 18 18 IA_BUSY 19 19 SX_BUSY 20 20 WD_BUSY 21 21 SPI_BUSY 22 22 BCI_BUSY 23 23 SC_BUSY 24 24 PA_BUSY 25 25 DB_BUSY 26 26 CP_COHERENCY_BUSY 28 28 CP_BUSY 29 29 CB_BUSY 30 30 GUI_ACTIVE 31 31 mmGRBM_STATUS2 0 0x2002 17 0 4294967295 ME0PIPE1_CMDFIFO_AVAIL 0 3 ME0PIPE1_CF_RQ_PENDING 4 4 ME0PIPE1_PF_RQ_PENDING 5 5 ME1PIPE0_RQ_PENDING 6 6 ME1PIPE1_RQ_PENDING 7 7 ME1PIPE2_RQ_PENDING 8 8 ME1PIPE3_RQ_PENDING 9 9 ME2PIPE0_RQ_PENDING 10 10 ME2PIPE1_RQ_PENDING 11 11 ME2PIPE2_RQ_PENDING 12 12 ME2PIPE3_RQ_PENDING 13 13 RLC_RQ_PENDING 14 14 RLC_BUSY 24 24 TC_BUSY 25 25 CPF_BUSY 28 28 CPC_BUSY 29 29 CPG_BUSY 30 30 mmGRBM_STATUS_SE0 0 0x2005 11 0 4294967295 DB_CLEAN 1 1 CB_CLEAN 2 2 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS_SE1 0 0x2006 11 0 4294967295 DB_CLEAN 1 1 CB_CLEAN 2 2 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS_SE2 0 0x200e 11 0 4294967295 DB_CLEAN 1 1 CB_CLEAN 2 2 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_STATUS_SE3 0 0x200f 11 0 4294967295 DB_CLEAN 1 1 CB_CLEAN 2 2 BCI_BUSY 22 22 VGT_BUSY 23 23 PA_BUSY 24 24 TA_BUSY 25 25 SX_BUSY 26 26 SPI_BUSY 27 27 SC_BUSY 29 29 DB_BUSY 30 30 CB_BUSY 31 31 mmGRBM_SOFT_RESET 0 0x2008 6 0 4294967295 SOFT_RESET_CP 0 0 SOFT_RESET_RLC 2 2 SOFT_RESET_GFX 16 16 SOFT_RESET_CPF 17 17 SOFT_RESET_CPC 18 18 SOFT_RESET_CPG 19 19 mmGRBM_DEBUG_CNTL 0 0x2009 1 0 4294967295 GRBM_DEBUG_INDEX 0 5 mmGRBM_DEBUG_DATA 0 0x200a 1 0 4294967295 DATA 0 31 mmGRBM_GFX_INDEX 0 0xc200 6 0 4294967295 INSTANCE_INDEX 0 7 SH_INDEX 8 15 SE_INDEX 16 23 SH_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 mmGRBM_GFX_CLKEN_CNTL 0 0x200c 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmGRBM_WAIT_IDLE_CLOCKS 0 0x200d 1 0 4294967295 WAIT_IDLE_CLOCKS 0 7 mmGRBM_DEBUG 0 0x2014 6 0 4294967295 IGNORE_RDY 1 1 IGNORE_FAO 5 5 DISABLE_READ_TIMEOUT 6 6 SNAPSHOT_FREE_CNTRS 7 7 HYSTERESIS_GUI_ACTIVE 8 11 GFX_CLOCK_DOMAIN_OVERRIDE 12 12 mmGRBM_DEBUG_SNAPSHOT 0 0x2015 22 0 4294967295 CPF_RDY 0 0 CPG_RDY 1 1 SRBM_RDY 2 2 WD_ME0PIPE0_RDY 3 3 WD_ME0PIPE1_RDY 4 4 GDS_RDY 5 5 SE0SPI_ME0PIPE0_RDY0 6 6 SE0SPI_ME0PIPE1_RDY0 7 7 SE1SPI_ME0PIPE0_RDY0 8 8 SE1SPI_ME0PIPE1_RDY0 9 9 SE2SPI_ME0PIPE0_RDY0 10 10 SE2SPI_ME0PIPE1_RDY0 11 11 SE3SPI_ME0PIPE0_RDY0 12 12 SE3SPI_ME0PIPE1_RDY0 13 13 SE0SPI_ME0PIPE0_RDY1 14 14 SE0SPI_ME0PIPE1_RDY1 15 15 SE1SPI_ME0PIPE0_RDY1 16 16 SE1SPI_ME0PIPE1_RDY1 17 17 SE2SPI_ME0PIPE0_RDY1 18 18 SE2SPI_ME0PIPE1_RDY1 19 19 SE3SPI_ME0PIPE0_RDY1 20 20 SE3SPI_ME0PIPE1_RDY1 21 21 mmGRBM_READ_ERROR 0 0x2016 4 0 4294967295 READ_ADDRESS 2 17 READ_PIPEID 20 21 READ_MEID 22 23 READ_ERROR 31 31 mmGRBM_READ_ERROR2 0 0x2017 15 0 4294967295 READ_REQUESTER_SRBM 17 17 READ_REQUESTER_RLC 18 18 READ_REQUESTER_GDS_DMA 19 19 READ_REQUESTER_ME0PIPE0_CF 20 20 READ_REQUESTER_ME0PIPE0_PF 21 21 READ_REQUESTER_ME0PIPE1_CF 22 22 READ_REQUESTER_ME0PIPE1_PF 23 23 READ_REQUESTER_ME1PIPE0 24 24 READ_REQUESTER_ME1PIPE1 25 25 READ_REQUESTER_ME1PIPE2 26 26 READ_REQUESTER_ME1PIPE3 27 27 READ_REQUESTER_ME2PIPE0 28 28 READ_REQUESTER_ME2PIPE1 29 29 READ_REQUESTER_ME2PIPE2 30 30 READ_REQUESTER_ME2PIPE3 31 31 mmGRBM_INT_CNTL 0 0x2018 2 0 4294967295 RDERR_INT_ENABLE 0 0 GUI_IDLE_INT_ENABLE 19 19 mmGRBM_PERFCOUNTER0_SELECT 0 0xd840 19 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 VGT_BUSY_USER_DEFINED_MASK 12 12 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 IA_BUSY_USER_DEFINED_MASK 23 23 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TC_BUSY_USER_DEFINED_MASK 27 27 WD_BUSY_USER_DEFINED_MASK 28 28 mmGRBM_PERFCOUNTER1_SELECT 0 0xd841 19 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 VGT_BUSY_USER_DEFINED_MASK 12 12 TA_BUSY_USER_DEFINED_MASK 13 13 SX_BUSY_USER_DEFINED_MASK 14 14 SPI_BUSY_USER_DEFINED_MASK 16 16 SC_BUSY_USER_DEFINED_MASK 17 17 PA_BUSY_USER_DEFINED_MASK 18 18 GRBM_BUSY_USER_DEFINED_MASK 19 19 DB_BUSY_USER_DEFINED_MASK 20 20 CB_BUSY_USER_DEFINED_MASK 21 21 CP_BUSY_USER_DEFINED_MASK 22 22 IA_BUSY_USER_DEFINED_MASK 23 23 GDS_BUSY_USER_DEFINED_MASK 24 24 BCI_BUSY_USER_DEFINED_MASK 25 25 RLC_BUSY_USER_DEFINED_MASK 26 26 TC_BUSY_USER_DEFINED_MASK 27 27 WD_BUSY_USER_DEFINED_MASK 28 28 mmGRBM_SE0_PERFCOUNTER_SELECT 0 0xd842 12 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 mmGRBM_SE1_PERFCOUNTER_SELECT 0 0xd843 12 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 mmGRBM_SE2_PERFCOUNTER_SELECT 0 0xd844 12 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 mmGRBM_SE3_PERFCOUNTER_SELECT 0 0xd845 12 0 4294967295 PERF_SEL 0 5 DB_CLEAN_USER_DEFINED_MASK 10 10 CB_CLEAN_USER_DEFINED_MASK 11 11 TA_BUSY_USER_DEFINED_MASK 12 12 SX_BUSY_USER_DEFINED_MASK 13 13 SPI_BUSY_USER_DEFINED_MASK 15 15 SC_BUSY_USER_DEFINED_MASK 16 16 DB_BUSY_USER_DEFINED_MASK 17 17 CB_BUSY_USER_DEFINED_MASK 18 18 VGT_BUSY_USER_DEFINED_MASK 19 19 PA_BUSY_USER_DEFINED_MASK 20 20 BCI_BUSY_USER_DEFINED_MASK 21 21 mmGRBM_PERFCOUNTER0_LO 0 0xd040 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_PERFCOUNTER0_HI 0 0xd041 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_PERFCOUNTER1_LO 0 0xd043 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_PERFCOUNTER1_HI 0 0xd044 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_SE0_PERFCOUNTER_LO 0 0xd045 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_SE0_PERFCOUNTER_HI 0 0xd046 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_SE1_PERFCOUNTER_LO 0 0xd047 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_SE1_PERFCOUNTER_HI 0 0xd048 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_SE2_PERFCOUNTER_LO 0 0xd049 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_SE2_PERFCOUNTER_HI 0 0xd04a 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_SE3_PERFCOUNTER_LO 0 0xd04b 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGRBM_SE3_PERFCOUNTER_HI 0 0xd04c 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGRBM_SCRATCH_REG0 0 0x2040 1 0 4294967295 SCRATCH_REG0 0 31 mmGRBM_SCRATCH_REG1 0 0x2041 1 0 4294967295 SCRATCH_REG1 0 31 mmGRBM_SCRATCH_REG2 0 0x2042 1 0 4294967295 SCRATCH_REG2 0 31 mmGRBM_SCRATCH_REG3 0 0x2043 1 0 4294967295 SCRATCH_REG3 0 31 mmGRBM_SCRATCH_REG4 0 0x2044 1 0 4294967295 SCRATCH_REG4 0 31 mmGRBM_SCRATCH_REG5 0 0x2045 1 0 4294967295 SCRATCH_REG5 0 31 mmGRBM_SCRATCH_REG6 0 0x2046 1 0 4294967295 SCRATCH_REG6 0 31 mmGRBM_SCRATCH_REG7 0 0x2047 1 0 4294967295 SCRATCH_REG7 0 31 mmDEBUG_INDEX 0 0x203c 1 0 4294967295 DEBUG_INDEX 0 17 mmDEBUG_DATA 0 0x203d 1 0 4294967295 DEBUG_DATA 0 31 mmGRBM_NOWHERE 0 0x203f 1 0 4294967295 DATA 0 31 mmPA_CL_VPORT_XSCALE 0 0xa10f 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET 0 0xa110 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE 0 0xa111 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET 0 0xa112 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE 0 0xa113 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET 0 0xa114 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_XSCALE_1 0 0xa115 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_2 0 0xa11b 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_3 0 0xa121 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_4 0 0xa127 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_5 0 0xa12d 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_6 0 0xa133 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_7 0 0xa139 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_8 0 0xa13f 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_9 0 0xa145 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_10 0 0xa14b 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_11 0 0xa151 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_12 0 0xa157 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_13 0 0xa15d 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_14 0 0xa163 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XSCALE_15 0 0xa169 1 0 4294967295 VPORT_XSCALE 0 31 mmPA_CL_VPORT_XOFFSET_1 0 0xa116 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_2 0 0xa11c 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_3 0 0xa122 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_4 0 0xa128 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_5 0 0xa12e 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_6 0 0xa134 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_7 0 0xa13a 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_8 0 0xa140 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_9 0 0xa146 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_10 0 0xa14c 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_11 0 0xa152 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_12 0 0xa158 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_13 0 0xa15e 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_14 0 0xa164 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_XOFFSET_15 0 0xa16a 1 0 4294967295 VPORT_XOFFSET 0 31 mmPA_CL_VPORT_YSCALE_1 0 0xa117 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_2 0 0xa11d 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_3 0 0xa123 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_4 0 0xa129 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_5 0 0xa12f 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_6 0 0xa135 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_7 0 0xa13b 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_8 0 0xa141 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_9 0 0xa147 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_10 0 0xa14d 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_11 0 0xa153 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_12 0 0xa159 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_13 0 0xa15f 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_14 0 0xa165 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YSCALE_15 0 0xa16b 1 0 4294967295 VPORT_YSCALE 0 31 mmPA_CL_VPORT_YOFFSET_1 0 0xa118 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_2 0 0xa11e 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_3 0 0xa124 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_4 0 0xa12a 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_5 0 0xa130 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_6 0 0xa136 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_7 0 0xa13c 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_8 0 0xa142 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_9 0 0xa148 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_10 0 0xa14e 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_11 0 0xa154 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_12 0 0xa15a 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_13 0 0xa160 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_14 0 0xa166 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_YOFFSET_15 0 0xa16c 1 0 4294967295 VPORT_YOFFSET 0 31 mmPA_CL_VPORT_ZSCALE_1 0 0xa119 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_2 0 0xa11f 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_3 0 0xa125 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_4 0 0xa12b 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_5 0 0xa131 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_6 0 0xa137 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_7 0 0xa13d 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_8 0 0xa143 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_9 0 0xa149 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_10 0 0xa14f 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_11 0 0xa155 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_12 0 0xa15b 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_13 0 0xa161 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_14 0 0xa167 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZSCALE_15 0 0xa16d 1 0 4294967295 VPORT_ZSCALE 0 31 mmPA_CL_VPORT_ZOFFSET_1 0 0xa11a 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_2 0 0xa120 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_3 0 0xa126 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_4 0 0xa12c 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_5 0 0xa132 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_6 0 0xa138 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_7 0 0xa13e 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_8 0 0xa144 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_9 0 0xa14a 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_10 0 0xa150 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_11 0 0xa156 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_12 0 0xa15c 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_13 0 0xa162 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_14 0 0xa168 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VPORT_ZOFFSET_15 0 0xa16e 1 0 4294967295 VPORT_ZOFFSET 0 31 mmPA_CL_VTE_CNTL 0 0xa206 10 0 4294967295 VPORT_X_SCALE_ENA 0 0 VPORT_X_OFFSET_ENA 1 1 VPORT_Y_SCALE_ENA 2 2 VPORT_Y_OFFSET_ENA 3 3 VPORT_Z_SCALE_ENA 4 4 VPORT_Z_OFFSET_ENA 5 5 VTX_XY_FMT 8 8 VTX_Z_FMT 9 9 VTX_W0_FMT 10 10 PERFCOUNTER_REF 11 11 mmPA_CL_VS_OUT_CNTL 0 0xa207 26 0 4294967295 CLIP_DIST_ENA_0 0 0 CLIP_DIST_ENA_1 1 1 CLIP_DIST_ENA_2 2 2 CLIP_DIST_ENA_3 3 3 CLIP_DIST_ENA_4 4 4 CLIP_DIST_ENA_5 5 5 CLIP_DIST_ENA_6 6 6 CLIP_DIST_ENA_7 7 7 CULL_DIST_ENA_0 8 8 CULL_DIST_ENA_1 9 9 CULL_DIST_ENA_2 10 10 CULL_DIST_ENA_3 11 11 CULL_DIST_ENA_4 12 12 CULL_DIST_ENA_5 13 13 CULL_DIST_ENA_6 14 14 CULL_DIST_ENA_7 15 15 USE_VTX_POINT_SIZE 16 16 USE_VTX_EDGE_FLAG 17 17 USE_VTX_RENDER_TARGET_INDX 18 18 USE_VTX_VIEWPORT_INDX 19 19 USE_VTX_KILL_FLAG 20 20 VS_OUT_MISC_VEC_ENA 21 21 VS_OUT_CCDIST0_VEC_ENA 22 22 VS_OUT_CCDIST1_VEC_ENA 23 23 VS_OUT_MISC_SIDE_BUS_ENA 24 24 USE_VTX_GS_CUT_FLAG 25 25 mmPA_CL_NANINF_CNTL 0 0xa208 16 0 4294967295 VTE_XY_INF_DISCARD 0 0 VTE_Z_INF_DISCARD 1 1 VTE_W_INF_DISCARD 2 2 VTE_0XNANINF_IS_0 3 3 VTE_XY_NAN_RETAIN 4 4 VTE_Z_NAN_RETAIN 5 5 VTE_W_NAN_RETAIN 6 6 VTE_W_RECIP_NAN_IS_0 7 7 VS_XY_NAN_TO_INF 8 8 VS_XY_INF_RETAIN 9 9 VS_Z_NAN_TO_INF 10 10 VS_Z_INF_RETAIN 11 11 VS_W_NAN_TO_INF 12 12 VS_W_INF_RETAIN 13 13 VS_CLIP_DIST_INF_DISCARD 14 14 VTE_NO_OUTPUT_NEG_0 20 20 mmPA_CL_CLIP_CNTL 0 0xa204 19 0 4294967295 UCP_ENA_0 0 0 UCP_ENA_1 1 1 UCP_ENA_2 2 2 UCP_ENA_3 3 3 UCP_ENA_4 4 4 UCP_ENA_5 5 5 PS_UCP_Y_SCALE_NEG 13 13 PS_UCP_MODE 14 15 CLIP_DISABLE 16 16 UCP_CULL_ONLY_ENA 17 17 BOUNDARY_EDGE_FLAG_ENA 18 18 DX_CLIP_SPACE_DEF 19 19 DIS_CLIP_ERR_DETECT 20 20 VTX_KILL_OR 21 21 DX_RASTERIZATION_KILL 22 22 DX_LINEAR_ATTR_CLIP_ENA 24 24 VTE_VPORT_PROVOKE_DISABLE 25 25 ZCLIP_NEAR_DISABLE 26 26 ZCLIP_FAR_DISABLE 27 27 mmPA_CL_GB_VERT_CLIP_ADJ 0 0xa2fa 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_GB_VERT_DISC_ADJ 0 0xa2fb 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_GB_HORZ_CLIP_ADJ 0 0xa2fc 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_GB_HORZ_DISC_ADJ 0 0xa2fd 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_0_X 0 0xa16f 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_0_Y 0 0xa170 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_0_Z 0 0xa171 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_0_W 0 0xa172 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_1_X 0 0xa173 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_1_Y 0 0xa174 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_1_Z 0 0xa175 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_1_W 0 0xa176 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_2_X 0 0xa177 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_2_Y 0 0xa178 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_2_Z 0 0xa179 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_2_W 0 0xa17a 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_3_X 0 0xa17b 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_3_Y 0 0xa17c 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_3_Z 0 0xa17d 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_3_W 0 0xa17e 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_4_X 0 0xa17f 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_4_Y 0 0xa180 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_4_Z 0 0xa181 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_4_W 0 0xa182 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_5_X 0 0xa183 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_5_Y 0 0xa184 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_5_Z 0 0xa185 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_UCP_5_W 0 0xa186 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_POINT_X_RAD 0 0xa1f5 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_POINT_Y_RAD 0 0xa1f6 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_POINT_SIZE 0 0xa1f7 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_POINT_CULL_RAD 0 0xa1f8 1 0 4294967295 DATA_REGISTER 0 31 mmPA_CL_ENHANCE 0 0x2285 9 0 4294967295 CLIP_VTX_REORDER_ENA 0 0 NUM_CLIP_SEQ 1 2 CLIPPED_PRIM_SEQ_STALL 3 3 VE_NAN_PROC_DISABLE 4 4 XTRA_DEBUG_REG_SEL 5 5 ECO_SPARE3 28 28 ECO_SPARE2 29 29 ECO_SPARE1 30 30 ECO_SPARE0 31 31 mmPA_CL_RESET_DEBUG 0 0x2286 1 0 4294967295 CL_TRIV_DISC_DISABLE 0 0 mmPA_SU_VTX_CNTL 0 0xa2f9 3 0 4294967295 PIX_CENTER 0 0 ROUND_MODE 1 2 QUANT_MODE 3 5 mmPA_SU_POINT_SIZE 0 0xa280 2 0 4294967295 HEIGHT 0 15 WIDTH 16 31 mmPA_SU_POINT_MINMAX 0 0xa281 2 0 4294967295 MIN_SIZE 0 15 MAX_SIZE 16 31 mmPA_SU_LINE_CNTL 0 0xa282 1 0 4294967295 WIDTH 0 15 mmPA_SU_LINE_STIPPLE_CNTL 0 0xa209 4 0 4294967295 LINE_STIPPLE_RESET 0 1 EXPAND_FULL_LENGTH 2 2 FRACTIONAL_ACCUM 3 3 DIAMOND_ADJUST 4 4 mmPA_SU_LINE_STIPPLE_SCALE 0 0xa20a 1 0 4294967295 LINE_STIPPLE_SCALE 0 31 mmPA_SU_PRIM_FILTER_CNTL 0 0xa20b 11 0 4294967295 TRIANGLE_FILTER_DISABLE 0 0 LINE_FILTER_DISABLE 1 1 POINT_FILTER_DISABLE 2 2 RECTANGLE_FILTER_DISABLE 3 3 TRIANGLE_EXPAND_ENA 4 4 LINE_EXPAND_ENA 5 5 POINT_EXPAND_ENA 6 6 RECTANGLE_EXPAND_ENA 7 7 PRIM_EXPAND_CONSTANT 8 15 XMAX_RIGHT_EXCLUSION 30 30 YMAX_BOTTOM_EXCLUSION 31 31 mmPA_SU_SC_MODE_CNTL 0 0xa205 13 0 4294967295 CULL_FRONT 0 0 CULL_BACK 1 1 FACE 2 2 POLY_MODE 3 4 POLYMODE_FRONT_PTYPE 5 7 POLYMODE_BACK_PTYPE 8 10 POLY_OFFSET_FRONT_ENABLE 11 11 POLY_OFFSET_BACK_ENABLE 12 12 POLY_OFFSET_PARA_ENABLE 13 13 VTX_WINDOW_OFFSET_ENABLE 16 16 PROVOKING_VTX_LAST 19 19 PERSP_CORR_DIS 20 20 MULTI_PRIM_IB_ENA 21 21 mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0 0xa2de 2 0 4294967295 POLY_OFFSET_NEG_NUM_DB_BITS 0 7 POLY_OFFSET_DB_IS_FLOAT_FMT 8 8 mmPA_SU_POLY_OFFSET_CLAMP 0 0xa2df 1 0 4294967295 CLAMP 0 31 mmPA_SU_POLY_OFFSET_FRONT_SCALE 0 0xa2e0 1 0 4294967295 SCALE 0 31 mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0 0xa2e1 1 0 4294967295 OFFSET 0 31 mmPA_SU_POLY_OFFSET_BACK_SCALE 0 0xa2e2 1 0 4294967295 SCALE 0 31 mmPA_SU_POLY_OFFSET_BACK_OFFSET 0 0xa2e3 1 0 4294967295 OFFSET 0 31 mmPA_SU_HARDWARE_SCREEN_OFFSET 0 0xa08d 2 0 4294967295 HW_SCREEN_OFFSET_X 0 8 HW_SCREEN_OFFSET_Y 16 24 mmPA_SU_LINE_STIPPLE_VALUE 0 0xc280 1 0 4294967295 LINE_STIPPLE_VALUE 0 23 mmPA_SU_PERFCOUNTER0_SELECT 0 0xd900 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmPA_SU_PERFCOUNTER0_SELECT1 0 0xd901 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmPA_SU_PERFCOUNTER1_SELECT 0 0xd902 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmPA_SU_PERFCOUNTER1_SELECT1 0 0xd903 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmPA_SU_PERFCOUNTER2_SELECT 0 0xd904 2 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 mmPA_SU_PERFCOUNTER3_SELECT 0 0xd905 2 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 mmPA_SU_PERFCOUNTER0_LO 0 0xd100 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER0_HI 0 0xd101 1 0 4294967295 PERFCOUNTER_HI 0 15 mmPA_SU_PERFCOUNTER1_LO 0 0xd102 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER1_HI 0 0xd103 1 0 4294967295 PERFCOUNTER_HI 0 15 mmPA_SU_PERFCOUNTER2_LO 0 0xd104 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER2_HI 0 0xd105 1 0 4294967295 PERFCOUNTER_HI 0 15 mmPA_SU_PERFCOUNTER3_LO 0 0xd106 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SU_PERFCOUNTER3_HI 0 0xd107 1 0 4294967295 PERFCOUNTER_HI 0 15 mmPA_SC_AA_CONFIG 0 0xa2f8 5 0 4294967295 MSAA_NUM_SAMPLES 0 2 AA_MASK_CENTROID_DTMN 4 4 MAX_SAMPLE_DIST 13 16 MSAA_EXPOSED_SAMPLES 20 22 DETAIL_TO_EXPOSED_MODE 24 25 mmPA_SC_AA_MASK_X0Y0_X1Y0 0 0xa30e 2 0 4294967295 AA_MASK_X0Y0 0 15 AA_MASK_X1Y0 16 31 mmPA_SC_AA_MASK_X0Y1_X1Y1 0 0xa30f 2 0 4294967295 AA_MASK_X0Y1 0 15 AA_MASK_X1Y1 16 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0 0xa2fe 8 0 4294967295 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0 0xa2ff 8 0 4294967295 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0 0xa300 8 0 4294967295 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0 0xa301 8 0 4294967295 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0 0xa302 8 0 4294967295 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0 0xa303 8 0 4294967295 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0 0xa304 8 0 4294967295 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0 0xa305 8 0 4294967295 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0 0xa306 8 0 4294967295 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0 0xa307 8 0 4294967295 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0 0xa308 8 0 4294967295 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0 0xa309 8 0 4294967295 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0 0xa30a 8 0 4294967295 S0_X 0 3 S0_Y 4 7 S1_X 8 11 S1_Y 12 15 S2_X 16 19 S2_Y 20 23 S3_X 24 27 S3_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0 0xa30b 8 0 4294967295 S4_X 0 3 S4_Y 4 7 S5_X 8 11 S5_Y 12 15 S6_X 16 19 S6_Y 20 23 S7_X 24 27 S7_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0 0xa30c 8 0 4294967295 S8_X 0 3 S8_Y 4 7 S9_X 8 11 S9_Y 12 15 S10_X 16 19 S10_Y 20 23 S11_X 24 27 S11_Y 28 31 mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0 0xa30d 8 0 4294967295 S12_X 0 3 S12_Y 4 7 S13_X 8 11 S13_Y 12 15 S14_X 16 19 S14_Y 20 23 S15_X 24 27 S15_Y 28 31 mmPA_SC_CENTROID_PRIORITY_0 0 0xa2f5 8 0 4294967295 DISTANCE_0 0 3 DISTANCE_1 4 7 DISTANCE_2 8 11 DISTANCE_3 12 15 DISTANCE_4 16 19 DISTANCE_5 20 23 DISTANCE_6 24 27 DISTANCE_7 28 31 mmPA_SC_CENTROID_PRIORITY_1 0 0xa2f6 8 0 4294967295 DISTANCE_8 0 3 DISTANCE_9 4 7 DISTANCE_10 8 11 DISTANCE_11 12 15 DISTANCE_12 16 19 DISTANCE_13 20 23 DISTANCE_14 24 27 DISTANCE_15 28 31 mmPA_SC_CLIPRECT_0_TL 0 0xa084 2 0 4294967295 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_0_BR 0 0xa085 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_1_TL 0 0xa086 2 0 4294967295 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_1_BR 0 0xa087 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_2_TL 0 0xa088 2 0 4294967295 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_2_BR 0 0xa089 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_3_TL 0 0xa08a 2 0 4294967295 TL_X 0 14 TL_Y 16 30 mmPA_SC_CLIPRECT_3_BR 0 0xa08b 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_CLIPRECT_RULE 0 0xa083 1 0 4294967295 CLIP_RULE 0 15 mmPA_SC_EDGERULE 0 0xa08c 7 0 4294967295 ER_TRI 0 3 ER_POINT 4 7 ER_RECT 8 11 ER_LINE_LR 12 17 ER_LINE_RL 18 23 ER_LINE_TB 24 27 ER_LINE_BT 28 31 mmPA_SC_LINE_CNTL 0 0xa2f7 4 0 4294967295 EXPAND_LINE_WIDTH 9 9 LAST_PIXEL 10 10 PERPENDICULAR_ENDCAP_ENA 11 11 DX10_DIAMOND_TEST_ENA 12 12 mmPA_SC_LINE_STIPPLE 0 0xa283 4 0 4294967295 LINE_PATTERN 0 15 REPEAT_COUNT 16 23 PATTERN_BIT_ORDER 28 28 AUTO_RESET_CNTL 29 30 mmPA_SC_MODE_CNTL_0 0 0xa292 4 0 4294967295 MSAA_ENABLE 0 0 VPORT_SCISSOR_ENABLE 1 1 LINE_STIPPLE_ENABLE 2 2 SEND_UNLIT_STILES_TO_PKR 3 3 mmPA_SC_MODE_CNTL_1 0 0xa293 24 0 4294967295 WALK_SIZE 0 0 WALK_ALIGNMENT 1 1 WALK_ALIGN8_PRIM_FITS_ST 2 2 WALK_FENCE_ENABLE 3 3 WALK_FENCE_SIZE 4 6 SUPERTILE_WALK_ORDER_ENABLE 7 7 TILE_WALK_ORDER_ENABLE 8 8 TILE_COVER_DISABLE 9 9 TILE_COVER_NO_SCISSOR 10 10 ZMM_LINE_EXTENT 11 11 ZMM_LINE_OFFSET 12 12 ZMM_RECT_EXTENT 13 13 KILL_PIX_POST_HI_Z 14 14 KILL_PIX_POST_DETAIL_MASK 15 15 PS_ITER_SAMPLE 16 16 MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE 17 17 MULTI_GPU_SUPERTILE_ENABLE 18 18 GPU_ID_OVERRIDE_ENABLE 19 19 GPU_ID_OVERRIDE 20 23 MULTI_GPU_PRIM_DISCARD_ENABLE 24 24 FORCE_EOV_CNTDWN_ENABLE 25 25 FORCE_EOV_REZ_ENABLE 26 26 OUT_OF_ORDER_PRIMITIVE_ENABLE 27 27 OUT_OF_ORDER_WATER_MARK 28 30 mmPA_SC_RASTER_CONFIG 0 0xa0d4 15 0 4294967295 RB_MAP_PKR0 0 1 RB_MAP_PKR1 2 3 RB_XSEL2 4 5 RB_XSEL 6 6 RB_YSEL 7 7 PKR_MAP 8 9 PKR_XSEL 10 11 PKR_YSEL 12 13 PKR_XSEL2 14 15 SC_MAP 16 17 SC_XSEL 18 19 SC_YSEL 20 21 SE_MAP 24 25 SE_XSEL 26 27 SE_YSEL 28 29 mmPA_SC_RASTER_CONFIG_1 0 0xa0d5 3 0 4294967295 SE_PAIR_MAP 0 1 SE_PAIR_XSEL 2 3 SE_PAIR_YSEL 4 5 mmPA_SC_SCREEN_EXTENT_CONTROL 0 0xa0d6 2 0 4294967295 SLICE_EVEN_ENABLE 0 1 SLICE_ODD_ENABLE 2 3 mmPA_SC_GENERIC_SCISSOR_TL 0 0xa090 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_GENERIC_SCISSOR_BR 0 0xa091 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_SCREEN_SCISSOR_TL 0 0xa00c 2 0 4294967295 TL_X 0 15 TL_Y 16 31 mmPA_SC_SCREEN_SCISSOR_BR 0 0xa00d 2 0 4294967295 BR_X 0 15 BR_Y 16 31 mmPA_SC_WINDOW_OFFSET 0 0xa080 2 0 4294967295 WINDOW_X_OFFSET 0 15 WINDOW_Y_OFFSET 16 31 mmPA_SC_WINDOW_SCISSOR_TL 0 0xa081 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_WINDOW_SCISSOR_BR 0 0xa082 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_0_TL 0 0xa094 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_1_TL 0 0xa096 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_2_TL 0 0xa098 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_3_TL 0 0xa09a 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_4_TL 0 0xa09c 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_5_TL 0 0xa09e 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_6_TL 0 0xa0a0 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_7_TL 0 0xa0a2 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_8_TL 0 0xa0a4 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_9_TL 0 0xa0a6 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_10_TL 0 0xa0a8 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_11_TL 0 0xa0aa 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_12_TL 0 0xa0ac 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_13_TL 0 0xa0ae 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_14_TL 0 0xa0b0 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_15_TL 0 0xa0b2 3 0 4294967295 TL_X 0 14 TL_Y 16 30 WINDOW_OFFSET_DISABLE 31 31 mmPA_SC_VPORT_SCISSOR_0_BR 0 0xa095 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_1_BR 0 0xa097 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_2_BR 0 0xa099 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_3_BR 0 0xa09b 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_4_BR 0 0xa09d 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_5_BR 0 0xa09f 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_6_BR 0 0xa0a1 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_7_BR 0 0xa0a3 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_8_BR 0 0xa0a5 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_9_BR 0 0xa0a7 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_10_BR 0 0xa0a9 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_11_BR 0 0xa0ab 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_12_BR 0 0xa0ad 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_13_BR 0 0xa0af 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_14_BR 0 0xa0b1 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_SCISSOR_15_BR 0 0xa0b3 2 0 4294967295 BR_X 0 14 BR_Y 16 30 mmPA_SC_VPORT_ZMIN_0 0 0xa0b4 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_1 0 0xa0b6 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_2 0 0xa0b8 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_3 0 0xa0ba 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_4 0 0xa0bc 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_5 0 0xa0be 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_6 0 0xa0c0 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_7 0 0xa0c2 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_8 0 0xa0c4 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_9 0 0xa0c6 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_10 0 0xa0c8 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_11 0 0xa0ca 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_12 0 0xa0cc 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_13 0 0xa0ce 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_14 0 0xa0d0 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMIN_15 0 0xa0d2 1 0 4294967295 VPORT_ZMIN 0 31 mmPA_SC_VPORT_ZMAX_0 0 0xa0b5 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_1 0 0xa0b7 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_2 0 0xa0b9 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_3 0 0xa0bb 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_4 0 0xa0bd 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_5 0 0xa0bf 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_6 0 0xa0c1 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_7 0 0xa0c3 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_8 0 0xa0c5 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_9 0 0xa0c7 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_10 0 0xa0c9 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_11 0 0xa0cb 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_12 0 0xa0cd 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_13 0 0xa0cf 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_14 0 0xa0d1 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_VPORT_ZMAX_15 0 0xa0d3 1 0 4294967295 VPORT_ZMAX 0 31 mmPA_SC_ENHANCE 0 0x22fc 31 0 4294967295 ENABLE_PA_SC_OUT_OF_ORDER 0 0 DISABLE_SC_DB_TILE_FIX 1 1 DISABLE_AA_MASK_FULL_FIX 2 2 ENABLE_1XMSAA_SAMPLE_LOCATIONS 3 3 ENABLE_1XMSAA_SAMPLE_LOC_CENTROID 4 4 DISABLE_SCISSOR_FIX 5 5 DISABLE_PW_BUBBLE_COLLAPSE 6 7 SEND_UNLIT_STILES_TO_PACKER 8 8 DISABLE_DUALGRAD_PERF_OPTIMIZATION 9 9 DISABLE_SC_PROCESS_RESET_PRIM 10 10 DISABLE_SC_PROCESS_RESET_SUPERTILE 11 11 DISABLE_SC_PROCESS_RESET_TILE 12 12 DISABLE_PA_SC_GUIDANCE 13 13 DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS 14 14 ENABLE_MULTICYCLE_BUBBLE_FREEZE 15 15 DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE 16 16 ENABLE_OUT_OF_ORDER_POLY_MODE 17 17 DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST 18 18 DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING 19 19 ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY 20 20 DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING 21 21 DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING 22 22 DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS 23 23 ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID 24 24 DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO 25 25 OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT 26 26 OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING 27 27 DISABLE_EOP_LINE_STIPPLE_RESET 28 28 DISABLE_VPZ_EOP_LINE_STIPPLE_RESET 29 29 ECO_SPARE1 30 30 ECO_SPARE0 31 31 mmPA_SC_FIFO_SIZE 0 0x22f3 4 0 4294967295 SC_FRONTEND_PRIM_FIFO_SIZE 0 5 SC_BACKEND_PRIM_FIFO_SIZE 6 14 SC_HIZ_TILE_FIFO_SIZE 15 20 SC_EARLYZ_TILE_FIFO_SIZE 23 31 mmPA_SC_IF_FIFO_SIZE 0 0x22f5 4 0 4294967295 SC_DB_TILE_IF_FIFO_SIZE 0 5 SC_DB_QUAD_IF_FIFO_SIZE 6 11 SC_SPI_IF_FIFO_SIZE 12 17 SC_BCI_IF_FIFO_SIZE 18 23 mmPA_SC_FORCE_EOV_MAX_CNTS 0 0x22c9 2 0 4294967295 FORCE_EOV_MAX_CLK_CNT 0 15 FORCE_EOV_MAX_REZ_CNT 16 31 mmPA_SC_LINE_STIPPLE_STATE 0 0xc281 2 0 4294967295 CURRENT_PTR 0 3 CURRENT_COUNT 8 15 mmPA_SC_SCREEN_EXTENT_MIN_0 0 0xc284 2 0 4294967295 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MAX_0 0 0xc285 2 0 4294967295 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MIN_1 0 0xc286 2 0 4294967295 X 0 15 Y 16 31 mmPA_SC_SCREEN_EXTENT_MAX_1 0 0xc28b 2 0 4294967295 X 0 15 Y 16 31 mmPA_SC_PERFCOUNTER0_SELECT 0 0xd940 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmPA_SC_PERFCOUNTER0_SELECT1 0 0xd941 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmPA_SC_PERFCOUNTER1_SELECT 0 0xd942 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER2_SELECT 0 0xd943 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER3_SELECT 0 0xd944 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER4_SELECT 0 0xd945 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER5_SELECT 0 0xd946 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER6_SELECT 0 0xd947 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER7_SELECT 0 0xd948 1 0 4294967295 PERF_SEL 0 9 mmPA_SC_PERFCOUNTER0_LO 0 0xd140 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER0_HI 0 0xd141 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER1_LO 0 0xd142 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER1_HI 0 0xd143 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER2_LO 0 0xd144 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER2_HI 0 0xd145 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER3_LO 0 0xd146 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER3_HI 0 0xd147 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER4_LO 0 0xd148 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER4_HI 0 0xd149 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER5_LO 0 0xd14a 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER5_HI 0 0xd14b 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER6_LO 0 0xd14c 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER6_HI 0 0xd14d 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_PERFCOUNTER7_LO 0 0xd14e 1 0 4294967295 PERFCOUNTER_LO 0 31 mmPA_SC_PERFCOUNTER7_HI 0 0xd14f 1 0 4294967295 PERFCOUNTER_HI 0 31 mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0 0xc2a0 2 0 4294967295 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_P3D_TRAP_SCREEN_H 0 0xc2a1 1 0 4294967295 X_COORD 0 13 mmPA_SC_P3D_TRAP_SCREEN_V 0 0xc2a2 1 0 4294967295 Y_COORD 0 13 mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0 0xc2a3 1 0 4294967295 COUNT 0 15 mmPA_SC_P3D_TRAP_SCREEN_COUNT 0 0xc2a4 1 0 4294967295 COUNT 0 15 mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0 0xc2a8 2 0 4294967295 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_HP3D_TRAP_SCREEN_H 0 0xc2a9 1 0 4294967295 X_COORD 0 13 mmPA_SC_HP3D_TRAP_SCREEN_V 0 0xc2aa 1 0 4294967295 Y_COORD 0 13 mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0 0xc2ab 1 0 4294967295 COUNT 0 15 mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0 0xc2ac 1 0 4294967295 COUNT 0 15 mmPA_SC_TRAP_SCREEN_HV_EN 0 0xc2b0 2 0 4294967295 ENABLE_HV_PRE_SHADER 0 0 FORCE_PRE_SHADER_ALL_PIXELS 1 1 mmPA_SC_TRAP_SCREEN_H 0 0xc2b1 1 0 4294967295 X_COORD 0 13 mmPA_SC_TRAP_SCREEN_V 0 0xc2b2 1 0 4294967295 Y_COORD 0 13 mmPA_SC_TRAP_SCREEN_OCCURRENCE 0 0xc2b3 1 0 4294967295 COUNT 0 15 mmPA_SC_TRAP_SCREEN_COUNT 0 0xc2b4 1 0 4294967295 COUNT 0 15 mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0 0x22c0 1 0 4294967295 DISABLE_NON_PRIV_WRITES 0 0 mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0 0x22c1 1 0 4294967295 DISABLE_NON_PRIV_WRITES 0 0 mmPA_SC_TRAP_SCREEN_HV_LOCK 0 0x22c2 1 0 4294967295 DISABLE_NON_PRIV_WRITES 0 0 mmPA_CL_CNTL_STATUS 0 0x2284 1 0 4294967295 CL_BUSY 31 31 mmPA_SU_CNTL_STATUS 0 0x2294 1 0 4294967295 SU_BUSY 31 31 mmPA_SC_FIFO_DEPTH_CNTL 0 0x2295 1 0 4294967295 DEPTH 0 9 mmCGTT_PA_CLK_CTRL 0 0xf088 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SU_CLK_OVERRIDE 29 29 CL_CLK_OVERRIDE 30 30 REG_CLK_OVERRIDE 31 31 mmCGTT_SC_CLK_CTRL 0 0xf089 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmPA_SU_DEBUG_CNTL 0 0x2280 1 0 4294967295 SU_DEBUG_INDX 0 4 mmPA_SU_DEBUG_DATA 0 0x2281 1 0 4294967295 DATA 0 31 mmPA_SC_DEBUG_CNTL 0 0x22f6 1 0 4294967295 SC_DEBUG_INDX 0 5 mmPA_SC_DEBUG_DATA 0 0x22f7 1 0 4294967295 DATA 0 31 ixCLIPPER_DEBUG_REG00 2 0x0 24 0 4294967295 ALWAYS_ZERO 0 7 clip_ga_bc_fifo_write 8 8 su_clip_baryc_free 9 10 clip_to_ga_fifo_write 11 11 clip_to_ga_fifo_full 12 12 primic_to_clprim_fifo_empty 13 13 primic_to_clprim_fifo_full 14 14 clip_to_outsm_fifo_empty 15 15 clip_to_outsm_fifo_full 16 16 vgt_to_clipp_fifo_empty 17 17 vgt_to_clipp_fifo_full 18 18 vgt_to_clips_fifo_empty 19 19 vgt_to_clips_fifo_full 20 20 clipcode_fifo_fifo_empty 21 21 clipcode_fifo_full 22 22 vte_out_clip_fifo_fifo_empty 23 23 vte_out_clip_fifo_fifo_full 24 24 vte_out_orig_fifo_fifo_empty 25 25 vte_out_orig_fifo_fifo_full 26 26 ccgen_to_clipcc_fifo_empty 27 27 ccgen_to_clipcc_fifo_full 28 28 clip_to_outsm_fifo_write 29 29 vte_out_orig_fifo_fifo_write 30 30 vgt_to_clipp_fifo_write 31 31 ixCLIPPER_DEBUG_REG01 2 0x1 16 0 4294967295 ALWAYS_ZERO 0 7 clip_extra_bc_valid 8 10 clip_vert_vte_valid 11 13 clip_to_outsm_vertex_deallocate 14 16 clip_to_outsm_deallocate_slot 17 19 clip_to_outsm_null_primitive 20 20 vte_positions_vte_clip_vte_naninf_kill_2 21 21 vte_positions_vte_clip_vte_naninf_kill_1 22 22 vte_positions_vte_clip_vte_naninf_kill_0 23 23 vte_out_clip_rd_extra_bc_valid 24 24 vte_out_clip_rd_vte_naninf_kill 25 25 vte_out_clip_rd_vertex_store_indx 26 27 clip_ga_bc_fifo_write 28 28 clip_to_ga_fifo_write 29 29 vte_out_clip_fifo_fifo_advanceread 30 30 vte_out_clip_fifo_fifo_empty 31 31 ixCLIPPER_DEBUG_REG02 2 0x2 18 0 4294967295 clip_extra_bc_valid 0 2 clip_vert_vte_valid 3 5 clip_to_outsm_clip_seq_indx 6 7 clip_to_outsm_vertex_store_indx_2 8 11 clip_to_outsm_vertex_store_indx_1 12 15 clip_to_outsm_vertex_store_indx_0 16 19 clip_to_clipga_extra_bc_coords 20 20 clip_to_clipga_vte_naninf_kill 21 21 clip_to_outsm_end_of_packet 22 22 clip_to_outsm_first_prim_of_slot 23 23 clip_to_outsm_clipped_prim 24 24 clip_to_outsm_null_primitive 25 25 clip_ga_bc_fifo_full 26 26 clip_to_ga_fifo_full 27 27 clip_ga_bc_fifo_write 28 28 clip_to_ga_fifo_write 29 29 clip_to_outsm_fifo_advanceread 30 30 clip_to_outsm_fifo_empty 31 31 ixCLIPPER_DEBUG_REG03 2 0x3 10 0 4294967295 clipsm0_clprim_to_clip_clip_code_or 0 13 clipsm0_clprim_to_clip_event_id 14 19 clipsm0_clprim_to_clip_state_var_indx 20 22 clipsm0_clprim_to_clip_clip_primitive 23 23 clipsm0_clprim_to_clip_deallocate_slot 24 26 clipsm0_clprim_to_clip_first_prim_of_slot 27 27 clipsm0_clprim_to_clip_end_of_packet 28 28 clipsm0_clprim_to_clip_event 29 29 clipsm0_clprim_to_clip_null_primitive 30 30 clipsm0_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG04 2 0x4 7 0 4294967295 clipsm0_clprim_to_clip_param_cache_indx_0 1 10 clipsm0_clprim_to_clip_vertex_store_indx_2 11 16 clipsm0_clprim_to_clip_vertex_store_indx_1 17 22 clipsm0_clprim_to_clip_vertex_store_indx_0 23 28 clipsm0_clprim_to_clip_event 29 29 clipsm0_clprim_to_clip_null_primitive 30 30 clipsm0_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG05 2 0x5 10 0 4294967295 clipsm1_clprim_to_clip_clip_code_or 0 13 clipsm1_clprim_to_clip_event_id 14 19 clipsm1_clprim_to_clip_state_var_indx 20 22 clipsm1_clprim_to_clip_clip_primitive 23 23 clipsm1_clprim_to_clip_deallocate_slot 24 26 clipsm1_clprim_to_clip_first_prim_of_slot 27 27 clipsm1_clprim_to_clip_end_of_packet 28 28 clipsm1_clprim_to_clip_event 29 29 clipsm1_clprim_to_clip_null_primitive 30 30 clipsm1_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG06 2 0x6 7 0 4294967295 clipsm1_clprim_to_clip_param_cache_indx_0 1 10 clipsm1_clprim_to_clip_vertex_store_indx_2 11 16 clipsm1_clprim_to_clip_vertex_store_indx_1 17 22 clipsm1_clprim_to_clip_vertex_store_indx_0 23 28 clipsm1_clprim_to_clip_event 29 29 clipsm1_clprim_to_clip_null_primitive 30 30 clipsm1_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG07 2 0x7 10 0 4294967295 clipsm2_clprim_to_clip_clip_code_or 0 13 clipsm2_clprim_to_clip_event_id 14 19 clipsm2_clprim_to_clip_state_var_indx 20 22 clipsm2_clprim_to_clip_clip_primitive 23 23 clipsm2_clprim_to_clip_deallocate_slot 24 26 clipsm2_clprim_to_clip_first_prim_of_slot 27 27 clipsm2_clprim_to_clip_end_of_packet 28 28 clipsm2_clprim_to_clip_event 29 29 clipsm2_clprim_to_clip_null_primitive 30 30 clipsm2_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG08 2 0x8 7 0 4294967295 clipsm2_clprim_to_clip_param_cache_indx_0 1 10 clipsm2_clprim_to_clip_vertex_store_indx_2 11 16 clipsm2_clprim_to_clip_vertex_store_indx_1 17 22 clipsm2_clprim_to_clip_vertex_store_indx_0 23 28 clipsm2_clprim_to_clip_event 29 29 clipsm2_clprim_to_clip_null_primitive 30 30 clipsm2_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG09 2 0x9 10 0 4294967295 clipsm3_clprim_to_clip_clip_code_or 0 13 clipsm3_clprim_to_clip_event_id 14 19 clipsm3_clprim_to_clip_state_var_indx 20 22 clipsm3_clprim_to_clip_clip_primitive 23 23 clipsm3_clprim_to_clip_deallocate_slot 24 26 clipsm3_clprim_to_clip_first_prim_of_slot 27 27 clipsm3_clprim_to_clip_end_of_packet 28 28 clipsm3_clprim_to_clip_event 29 29 clipsm3_clprim_to_clip_null_primitive 30 30 clipsm3_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG10 2 0xa 7 0 4294967295 clipsm3_clprim_to_clip_param_cache_indx_0 1 10 clipsm3_clprim_to_clip_vertex_store_indx_2 11 16 clipsm3_clprim_to_clip_vertex_store_indx_1 17 22 clipsm3_clprim_to_clip_vertex_store_indx_0 23 28 clipsm3_clprim_to_clip_event 29 29 clipsm3_clprim_to_clip_null_primitive 30 30 clipsm3_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG11 2 0xb 20 0 4294967295 clipsm3_clip_to_clipga_event 0 0 clipsm2_clip_to_clipga_event 1 1 clipsm1_clip_to_clipga_event 2 2 clipsm0_clip_to_clipga_event 3 3 clipsm3_clip_to_clipga_clip_primitive 4 4 clipsm2_clip_to_clipga_clip_primitive 5 5 clipsm1_clip_to_clipga_clip_primitive 6 6 clipsm0_clip_to_clipga_clip_primitive 7 7 clipsm3_clip_to_clipga_clip_to_outsm_cnt 8 11 clipsm2_clip_to_clipga_clip_to_outsm_cnt 12 15 clipsm1_clip_to_clipga_clip_to_outsm_cnt 16 19 clipsm0_clip_to_clipga_clip_to_outsm_cnt 20 23 clipsm3_clip_to_clipga_prim_valid 24 24 clipsm2_clip_to_clipga_prim_valid 25 25 clipsm1_clip_to_clipga_prim_valid 26 26 clipsm0_clip_to_clipga_prim_valid 27 27 clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt 28 28 clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt 29 29 clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt 30 30 clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt 31 31 ixCLIPPER_DEBUG_REG12 2 0xc 14 0 4294967295 ALWAYS_ZERO 0 7 clip_priority_available_vte_out_clip 8 12 clip_priority_available_clip_verts 13 17 clip_priority_seq_indx_out 18 19 clip_priority_seq_indx_vert 20 21 clip_priority_seq_indx_load 22 23 clipsm3_clprim_to_clip_clip_primitive 24 24 clipsm3_clprim_to_clip_prim_valid 25 25 clipsm2_clprim_to_clip_clip_primitive 26 26 clipsm2_clprim_to_clip_prim_valid 27 27 clipsm1_clprim_to_clip_clip_primitive 28 28 clipsm1_clprim_to_clip_prim_valid 29 29 clipsm0_clprim_to_clip_clip_primitive 30 30 clipsm0_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG13 2 0xd 18 0 4294967295 clprim_in_back_state_var_indx 0 2 point_clip_candidate 3 3 prim_nan_kill 4 4 clprim_clip_primitive 5 5 clprim_cull_primitive 6 6 prim_back_valid 7 7 vertval_bits_vertex_cc_next_valid 8 11 clipcc_vertex_store_indx 12 13 vte_out_orig_fifo_fifo_empty 14 14 clipcode_fifo_fifo_empty 15 15 ccgen_to_clipcc_fifo_empty 16 16 clip_priority_seq_indx_out_cnt 17 20 outsm_clr_rd_orig_vertices 21 22 outsm_clr_rd_clipsm_wait 23 23 outsm_clr_fifo_contents 24 28 outsm_clr_fifo_full 29 29 outsm_clr_fifo_advanceread 30 30 outsm_clr_fifo_write 31 31 ixCLIPPER_DEBUG_REG14 2 0xe 10 0 4294967295 clprim_in_back_vertex_store_indx_2 0 5 clprim_in_back_vertex_store_indx_1 6 11 clprim_in_back_vertex_store_indx_0 12 17 outputclprimtoclip_null_primitive 18 18 clprim_in_back_end_of_packet 19 19 clprim_in_back_first_prim_of_slot 20 20 clprim_in_back_deallocate_slot 21 23 clprim_in_back_event_id 24 29 clprim_in_back_event 30 30 prim_back_valid 31 31 ixCLIPPER_DEBUG_REG15 2 0xf 5 0 4294967295 vertval_bits_vertex_vertex_store_msb 0 15 primic_to_clprim_fifo_vertex_store_indx_2 16 20 primic_to_clprim_fifo_vertex_store_indx_1 21 25 primic_to_clprim_fifo_vertex_store_indx_0 26 30 primic_to_clprim_valid 31 31 ixCLIPPER_DEBUG_REG16 2 0x10 12 0 4294967295 sm0_prim_end_state 0 6 sm0_ps_expand 7 7 sm0_clip_vert_cnt 8 12 sm0_vertex_clip_cnt 13 17 sm0_inv_to_clip_data_valid_1 18 18 sm0_inv_to_clip_data_valid_0 19 19 sm0_current_state 20 26 sm0_clip_to_clipga_clip_to_outsm_cnt_eq0 27 27 sm0_clip_to_outsm_fifo_full 28 28 sm0_highest_priority_seq 29 29 sm0_outputcliptoclipga_0 30 30 sm0_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG17 2 0x11 12 0 4294967295 sm1_prim_end_state 0 6 sm1_ps_expand 7 7 sm1_clip_vert_cnt 8 12 sm1_vertex_clip_cnt 13 17 sm1_inv_to_clip_data_valid_1 18 18 sm1_inv_to_clip_data_valid_0 19 19 sm1_current_state 20 26 sm1_clip_to_clipga_clip_to_outsm_cnt_eq0 27 27 sm1_clip_to_outsm_fifo_full 28 28 sm1_highest_priority_seq 29 29 sm1_outputcliptoclipga_0 30 30 sm1_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG18 2 0x12 12 0 4294967295 sm2_prim_end_state 0 6 sm2_ps_expand 7 7 sm2_clip_vert_cnt 8 12 sm2_vertex_clip_cnt 13 17 sm2_inv_to_clip_data_valid_1 18 18 sm2_inv_to_clip_data_valid_0 19 19 sm2_current_state 20 26 sm2_clip_to_clipga_clip_to_outsm_cnt_eq0 27 27 sm2_clip_to_outsm_fifo_full 28 28 sm2_highest_priority_seq 29 29 sm2_outputcliptoclipga_0 30 30 sm2_clprim_to_clip_prim_valid 31 31 ixCLIPPER_DEBUG_REG19 2 0x13 12 0 4294967295 sm3_prim_end_state 0 6 sm3_ps_expand 7 7 sm3_clip_vert_cnt 8 12 sm3_vertex_clip_cnt 13 17 sm3_inv_to_clip_data_valid_1 18 18 sm3_inv_to_clip_data_valid_0 19 19 sm3_current_state 20 26 sm3_clip_to_clipga_clip_to_outsm_cnt_eq0 27 27 sm3_clip_to_outsm_fifo_full 28 28 sm3_highest_priority_seq 29 29 sm3_outputcliptoclipga_0 30 30 sm3_clprim_to_clip_prim_valid 31 31 ixSXIFCCG_DEBUG_REG0 2 0x14 9 0 4294967295 position_address 0 5 point_address 6 8 sx_pending_rd_state_var_indx 9 11 sx_pending_rd_req_mask 12 15 sx_pending_rd_pci 16 25 sx_pending_rd_aux_sel 26 27 sx_pending_rd_sp_id 28 29 sx_pending_rd_aux_inc 30 30 sx_pending_rd_advance 31 31 ixSXIFCCG_DEBUG_REG1 2 0x15 10 0 4294967295 available_positions 0 6 sx_receive_indx 7 9 sx_pending_fifo_contents 10 14 statevar_bits_vs_out_misc_vec_ena 15 15 statevar_bits_disable_sp 16 19 aux_sel 20 21 sx_to_pa_empty_1 22 22 sx_to_pa_empty_0 23 23 pasx_req_cnt_1 24 27 pasx_req_cnt_0 28 31 ixSXIFCCG_DEBUG_REG2 2 0x16 7 0 4294967295 param_cache_base 0 6 sx_aux 7 8 sx_request_indx 9 14 req_active_verts_loaded 15 15 req_active_verts 16 22 vgt_to_ccgen_state_var_indx 23 25 vgt_to_ccgen_active_verts 26 31 ixSXIFCCG_DEBUG_REG3 2 0x17 15 0 4294967295 ALWAYS_ZERO 0 7 vertex_fifo_entriesavailable 8 11 statevar_bits_vs_out_ccdist1_vec_ena 12 12 statevar_bits_vs_out_ccdist0_vec_ena 13 13 available_positions 14 20 current_state 21 22 vertex_fifo_empty 23 23 vertex_fifo_full 24 24 sx0_receive_fifo_empty 25 25 sx0_receive_fifo_full 26 26 vgt_to_ccgen_fifo_empty 27 27 vgt_to_ccgen_fifo_full 28 28 ccgen_to_clipcc_fifo_full 29 29 sx0_receive_fifo_write 30 30 ccgen_to_clipcc_write 31 31 ixSETUP_DEBUG_REG0 2 0x18 15 0 4294967295 su_baryc_cntl_state 0 1 su_cntl_state 2 5 pmode_state 8 13 ge_stallb 14 14 geom_enable 15 15 su_clip_baryc_free 16 17 su_clip_rtr 18 18 pfifo_busy 19 19 su_cntl_busy 20 20 geom_busy 21 21 event_id_gated 22 27 event_gated 28 28 pmode_prim_gated 29 29 su_dyn_sclk_vld 30 30 cl_dyn_sclk_vld 31 31 ixSETUP_DEBUG_REG1 2 0x19 2 0 4294967295 y_sort0_gated_23_8 0 15 x_sort0_gated_23_8 16 31 ixSETUP_DEBUG_REG2 2 0x1a 2 0 4294967295 y_sort1_gated_23_8 0 15 x_sort1_gated_23_8 16 31 ixSETUP_DEBUG_REG3 2 0x1b 2 0 4294967295 y_sort2_gated_23_8 0 15 x_sort2_gated_23_8 16 31 ixSETUP_DEBUG_REG4 2 0x1c 11 0 4294967295 attr_indx_sort0_gated 0 13 null_prim_gated 14 14 backfacing_gated 15 15 st_indx_gated 16 18 clipped_gated 19 19 dealloc_slot_gated 20 22 xmajor_gated 23 23 diamond_rule_gated 24 25 type_gated 26 28 fpov_gated 29 30 eop_gated 31 31 ixSETUP_DEBUG_REG5 2 0x1d 5 0 4294967295 attr_indx_sort2_gated 0 13 attr_indx_sort1_gated 14 27 provoking_vtx_gated 28 29 valid_prim_gated 30 30 pa_reg_sclk_vld 31 31 ixPA_SC_DEBUG_REG0 2 0x0 2 0 4294967295 REG0_FIELD0 0 1 REG0_FIELD1 2 3 ixPA_SC_DEBUG_REG1 2 0x1 2 0 4294967295 REG1_FIELD0 0 1 REG1_FIELD1 2 3 mmCOMPUTE_DISPATCH_INITIATOR 0 0x2e00 12 0 4294967295 COMPUTE_SHADER_EN 0 0 PARTIAL_TG_EN 1 1 FORCE_START_AT_000 2 2 ORDERED_APPEND_ENBL 3 3 ORDERED_APPEND_MODE 4 4 USE_THREAD_DIMENSIONS 5 5 ORDER_MODE 6 6 DISPATCH_CACHE_CNTL 7 9 SCALAR_L1_INV_VOL 10 10 VECTOR_L1_INV_VOL 11 11 DATA_ATC 12 12 RESTORE 14 14 mmCOMPUTE_DIM_X 0 0x2e01 1 0 4294967295 SIZE 0 31 mmCOMPUTE_DIM_Y 0 0x2e02 1 0 4294967295 SIZE 0 31 mmCOMPUTE_DIM_Z 0 0x2e03 1 0 4294967295 SIZE 0 31 mmCOMPUTE_START_X 0 0x2e04 1 0 4294967295 START 0 31 mmCOMPUTE_START_Y 0 0x2e05 1 0 4294967295 START 0 31 mmCOMPUTE_START_Z 0 0x2e06 1 0 4294967295 START 0 31 mmCOMPUTE_NUM_THREAD_X 0 0x2e07 2 0 4294967295 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_NUM_THREAD_Y 0 0x2e08 2 0 4294967295 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_NUM_THREAD_Z 0 0x2e09 2 0 4294967295 NUM_THREAD_FULL 0 15 NUM_THREAD_PARTIAL 16 31 mmCOMPUTE_PIPELINESTAT_ENABLE 0 0x2e0a 1 0 4294967295 PIPELINESTAT_ENABLE 0 0 mmCOMPUTE_PERFCOUNT_ENABLE 0 0x2e0b 1 0 4294967295 PERFCOUNT_ENABLE 0 0 mmCOMPUTE_PGM_LO 0 0x2e0c 1 0 4294967295 DATA 0 31 mmCOMPUTE_PGM_HI 0 0x2e0d 2 0 4294967295 DATA 0 7 INST_ATC 8 8 mmCOMPUTE_TBA_LO 0 0x2e0e 1 0 4294967295 DATA 0 31 mmCOMPUTE_TBA_HI 0 0x2e0f 1 0 4294967295 DATA 0 7 mmCOMPUTE_TMA_LO 0 0x2e10 1 0 4294967295 DATA 0 31 mmCOMPUTE_TMA_HI 0 0x2e11 1 0 4294967295 DATA 0 7 mmCOMPUTE_PGM_RSRC1 0 0x2e12 10 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 BULKY 24 24 CDBG_USER 25 25 mmCOMPUTE_PGM_RSRC2 0 0x2e13 11 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 TGID_X_EN 7 7 TGID_Y_EN 8 8 TGID_Z_EN 9 9 TG_SIZE_EN 10 10 TIDIG_COMP_CNT 11 12 EXCP_EN_MSB 13 14 LDS_SIZE 15 23 EXCP_EN 24 30 mmCOMPUTE_VMID 0 0x2e14 1 0 4294967295 DATA 0 3 mmCOMPUTE_RESOURCE_LIMITS 0 0x2e15 6 0 4294967295 WAVES_PER_SH 0 9 TG_PER_CU 12 15 LOCK_THRESHOLD 16 21 SIMD_DEST_CNTL 22 22 FORCE_SIMD_DIST 23 23 CU_GROUP_COUNT 24 26 mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0 0x2e16 2 0 4294967295 SH0_CU_EN 0 15 SH1_CU_EN 16 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0 0x2e17 2 0 4294967295 SH0_CU_EN 0 15 SH1_CU_EN 16 31 mmCOMPUTE_TMPRING_SIZE 0 0x2e18 2 0 4294967295 WAVES 0 11 WAVESIZE 12 24 mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0 0x2e19 2 0 4294967295 SH0_CU_EN 0 15 SH1_CU_EN 16 31 mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0 0x2e1a 2 0 4294967295 SH0_CU_EN 0 15 SH1_CU_EN 16 31 mmCOMPUTE_RESTART_X 0 0x2e1b 1 0 4294967295 RESTART 0 31 mmCOMPUTE_RESTART_Y 0 0x2e1c 1 0 4294967295 RESTART 0 31 mmCOMPUTE_RESTART_Z 0 0x2e1d 1 0 4294967295 RESTART 0 31 mmCOMPUTE_THREAD_TRACE_ENABLE 0 0x2e1e 1 0 4294967295 THREAD_TRACE_ENABLE 0 0 mmCOMPUTE_MISC_RESERVED 0 0x2e1f 4 0 4294967295 SEND_SEID 0 1 RESERVED2 2 2 RESERVED3 3 3 RESERVED4 4 4 mmCOMPUTE_USER_DATA_0 0 0x2e40 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_1 0 0x2e41 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_2 0 0x2e42 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_3 0 0x2e43 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_4 0 0x2e44 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_5 0 0x2e45 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_6 0 0x2e46 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_7 0 0x2e47 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_8 0 0x2e48 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_9 0 0x2e49 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_10 0 0x2e4a 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_11 0 0x2e4b 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_12 0 0x2e4c 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_13 0 0x2e4d 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_14 0 0x2e4e 1 0 4294967295 DATA 0 31 mmCOMPUTE_USER_DATA_15 0 0x2e4f 1 0 4294967295 DATA 0 31 mmCSPRIV_CONNECT 0 0x0 4 0 4294967295 DOORBELL_OFFSET 0 20 QUEUE_ID 21 23 VMID 26 29 UNORD_DISP 31 31 mmCSPRIV_THREAD_TRACE_TG0 0 0x1e 1 0 4294967295 TGID_X 0 31 mmCSPRIV_THREAD_TRACE_TG1 0 0x1e 1 0 4294967295 TGID_Y 0 31 mmCSPRIV_THREAD_TRACE_TG2 0 0x1e 1 0 4294967295 TGID_Z 0 31 mmCSPRIV_THREAD_TRACE_TG3 0 0x1e 7 0 4294967295 WAVE_ID_BASE 0 11 THREADS_IN_GROUP 12 23 PARTIAL_X_FLAG 24 24 PARTIAL_Y_FLAG 25 25 PARTIAL_Z_FLAG 26 26 LAST_TG 27 27 FIRST_TG 28 28 mmCSPRIV_THREAD_TRACE_EVENT 0 0x1f 1 0 4294967295 EVENT_ID 0 4 mmRLC_CNTL 0 0x30c0 6 0 4294967295 RLC_ENABLE_F32 0 0 FORCE_RETRY 1 1 READ_CACHE_DISABLE 2 2 RLC_STEP_F32 3 3 SOFT_RESET_DEBUG_MODE 4 4 RESERVED 8 31 mmRLC_DEBUG_SELECT 0 0x30c1 2 0 4294967295 SELECT 0 7 RESERVED 8 31 mmRLC_DEBUG 0 0x30c2 1 0 4294967295 DATA 0 31 mmRLC_MC_CNTL 0 0x30c3 13 0 4294967295 WRREQ_SWAP 0 1 WRREQ_TRAN 2 2 WRREQ_PRIV 3 3 WRNFO_STALL 4 4 WRNFO_URG 5 8 WRREQ_DW_IMASK 9 12 RESERVED_B 13 19 RDNFO_URG 20 23 RDREQ_SWAP 24 25 RDREQ_TRAN 26 26 RDREQ_PRIV 27 27 RDNFO_STALL 28 28 RESERVED 29 31 mmRLC_STAT 0 0x30c4 4 0 4294967295 RLC_BUSY 0 0 RLC_GPM_BUSY 1 1 RLC_SPM_BUSY 2 2 RESERVED 3 31 mmRLC_SAFE_MODE 0 0x313a 3 0 4294967295 REQ 0 0 MESSAGE 1 4 RESERVED 5 31 mmRLC_SOFT_RESET_GPU 0 0x30c5 2 0 4294967295 SOFT_RESET_GPU 0 0 RESERVED 1 31 mmRLC_MEM_SLP_CNTL 0 0x30c6 6 0 4294967295 RLC_MEM_LS_EN 0 0 RLC_MEM_DS_EN 1 1 RESERVED 2 7 RLC_MEM_LS_ON_DELAY 8 15 RLC_MEM_LS_OFF_DELAY 16 23 RESERVED1 24 31 mmRLC_PERFMON_CNTL 0 0xdcc0 2 0 4294967295 PERFMON_STATE 0 2 PERFMON_SAMPLE_ENABLE 10 10 mmRLC_PERFCOUNTER0_SELECT 0 0xdcc1 1 0 4294967295 PERFCOUNTER_SELECT 0 7 mmRLC_PERFCOUNTER1_SELECT 0 0xdcc2 1 0 4294967295 PERFCOUNTER_SELECT 0 7 mmRLC_PERFCOUNTER0_LO 0 0xd480 1 0 4294967295 PERFCOUNTER_LO 0 31 mmRLC_PERFCOUNTER1_LO 0 0xd482 1 0 4294967295 PERFCOUNTER_LO 0 31 mmRLC_PERFCOUNTER0_HI 0 0xd481 1 0 4294967295 PERFCOUNTER_HI 0 31 mmRLC_PERFCOUNTER1_HI 0 0xd483 1 0 4294967295 PERFCOUNTER_HI 0 31 mmCGTT_RLC_CLK_CTRL 0 0xf0b8 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_DYN 30 30 SOFT_OVERRIDE_REG 31 31 mmRLC_LB_CNTL 0 0x30d9 6 0 4294967295 LOAD_BALANCE_ENABLE 0 0 LB_CNT_CP_BUSY 1 1 LB_CNT_SPIM_ACTIVE 2 2 LB_CNT_REG_INC 3 3 CU_MASK_USED_OFF_HYST 4 11 RESERVED 12 31 mmRLC_LB_CNTR_MAX 0 0x30d2 1 0 4294967295 LB_CNTR_MAX 0 31 mmRLC_LB_CNTR_INIT 0 0x30db 1 0 4294967295 LB_CNTR_INIT 0 31 mmRLC_LOAD_BALANCE_CNTR 0 0x30dc 1 0 4294967295 RLC_LOAD_BALANCE_CNTR 0 31 mmRLC_SAVE_AND_RESTORE_BASE 0 0x30dd 1 0 4294967295 BASE 0 31 mmRLC_JUMP_TABLE_RESTORE 0 0x30de 1 0 4294967295 ADDR 0 31 mmRLC_DRIVER_CPDMA_STATUS 0 0x30de 4 0 4294967295 DRIVER_REQUEST 0 0 RESERVED1 1 3 DRIVER_ACK 4 4 RESERVED 5 31 mmRLC_PG_DELAY_2 0 0x30df 3 0 4294967295 SERDES_TIMEOUT_VALUE 0 7 SERDES_CMD_DELAY 8 15 PERCU_TIMEOUT_VALUE 16 31 mmRLC_GPM_DEBUG_SELECT 0 0x30e0 2 0 4294967295 SELECT 0 7 RESERVED 8 31 mmRLC_GPM_DEBUG 0 0x30e1 1 0 4294967295 DATA 0 31 mmRLC_GPM_UCODE_ADDR 0 0x30e2 2 0 4294967295 UCODE_ADDR 0 11 RESERVED 12 31 mmRLC_GPM_UCODE_DATA 0 0x30e3 1 0 4294967295 UCODE_DATA 0 31 mmRLC_GPU_CLOCK_COUNT_LSB 0 0x30e4 1 0 4294967295 GPU_CLOCKS_LSB 0 31 mmRLC_GPU_CLOCK_COUNT_MSB 0 0x30e5 1 0 4294967295 GPU_CLOCKS_MSB 0 31 mmRLC_CAPTURE_GPU_CLOCK_COUNT 0 0x30e6 2 0 4294967295 CAPTURE 0 0 RESERVED 1 31 mmRLC_UCODE_CNTL 0 0x30e7 1 0 4294967295 RLC_UCODE_FLAGS 0 31 mmRLC_GPM_STAT 0 0x3100 5 0 4294967295 RLC_BUSY 0 0 GFX_POWER_STATUS 1 1 GFX_CLOCK_STATUS 2 2 GFX_LS_STATUS 3 3 RESERVED 4 31 mmRLC_GPU_CLOCK_32_RES_SEL 0 0x3101 2 0 4294967295 RES_SEL 0 5 RESERVED 6 31 mmRLC_GPU_CLOCK_32 0 0x3102 1 0 4294967295 GPU_CLOCK_32 0 31 mmRLC_PG_CNTL 0 0x3103 10 0 4294967295 GFX_POWER_GATING_ENABLE 0 0 GFX_POWER_GATING_SRC 1 1 DYN_PER_CU_PG_ENABLE 2 2 STATIC_PER_CU_PG_ENABLE 3 3 RESERVED 4 15 CHUB_HANDSHAKE_ENABLE 16 16 SMU_CLK_SLOWDOWN_ON_PU_ENABLE 17 17 SMU_CLK_SLOWDOWN_ON_PD_ENABLE 18 18 RESERVED1 19 23 PG_ERROR_STATUS 24 31 mmRLC_GPM_THREAD_PRIORITY 0 0x3104 4 0 4294967295 THREAD0_PRIORITY 0 7 THREAD1_PRIORITY 8 15 THREAD2_PRIORITY 16 23 THREAD3_PRIORITY 24 31 mmRLC_GPM_THREAD_ENABLE 0 0x3105 5 0 4294967295 THREAD0_ENABLE 0 0 THREAD1_ENABLE 1 1 THREAD2_ENABLE 2 2 THREAD3_ENABLE 3 3 RESERVED 4 31 mmRLC_GPM_VMID_THREAD0 0 0x3106 2 0 4294967295 RLC_VMID 0 3 RESERVED 4 31 mmRLC_GPM_VMID_THREAD1 0 0x3107 2 0 4294967295 RLC_VMID 0 3 RESERVED 4 31 mmRLC_CGTT_MGCG_OVERRIDE 0 0x3108 1 0 4294967295 OVERRIDE 0 31 mmRLC_CGCG_CGLS_CTRL 0 0x3109 8 0 4294967295 CGCG_EN 0 0 CGLS_EN 1 1 CGLS_REP_COMPANSAT_DELAY 2 7 CGCG_GFX_IDLE_THRESHOLD 8 26 CGCG_CONTROLLER 27 27 CGCG_REG_CTRL 28 28 SLEEP_MODE 29 30 SPARE 31 31 mmRLC_CGCG_RAMP_CTRL 0 0x310a 6 0 4294967295 DOWN_DIV_START_UNIT 0 3 DOWN_DIV_STEP_UNIT 4 7 UP_DIV_START_UNIT 8 11 UP_DIV_STEP_UNIT 12 15 STEP_DELAY_CNT 16 27 STEP_DELAY_UNIT 28 31 mmRLC_DYN_PG_STATUS 0 0x310b 1 0 4294967295 PG_STATUS_CU_MASK 0 31 mmRLC_DYN_PG_REQUEST 0 0x310c 1 0 4294967295 PG_REQUEST_CU_MASK 0 31 mmRLC_PG_DELAY 0 0x310d 4 0 4294967295 POWER_UP_DELAY 0 7 POWER_DOWN_DELAY 8 15 CMD_PROPAGATE_DELAY 16 23 MEM_SLEEP_DELAY 24 31 mmRLC_CU_STATUS 0 0x310e 1 0 4294967295 WORK_PENDING 0 31 mmRLC_LB_INIT_CU_MASK 0 0x310f 1 0 4294967295 INIT_CU_MASK 0 31 mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0 0x3110 1 0 4294967295 ALWAYS_ACTIVE_CU_MASK 0 31 mmRLC_LB_PARAMS 0 0x3111 4 0 4294967295 SKIP_L2_CHECK 0 0 FIFO_SAMPLES 1 7 PG_IDLE_SAMPLES 8 15 PG_IDLE_SAMPLE_INTERVAL 16 31 mmRLC_THREAD1_DELAY 0 0x3112 4 0 4294967295 CU_IDEL_DELAY 0 7 LBPW_INNER_LOOP_DELAY 8 15 LBPW_OUTER_LOOP_DELAY 16 23 SPARE 24 31 mmRLC_PG_ALWAYS_ON_CU_MASK 0 0x3113 1 0 4294967295 AON_CU_MASK 0 31 mmRLC_MAX_PG_CU 0 0x3114 2 0 4294967295 MAX_POWERED_UP_CU 0 7 SPARE 8 31 mmRLC_AUTO_PG_CTRL 0 0x3115 5 0 4294967295 AUTO_PG_EN 0 0 AUTO_GRBM_REG_SAVE_ON_IDLE_EN 1 1 AUTO_WAKE_UP_EN 2 2 GRBM_REG_SAVE_GFX_IDLE_THRESHOLD 3 18 PG_AFTER_GRBM_REG_SAVE_THRESHOLD 19 31 mmRLC_SMU_GRBM_REG_SAVE_CTRL 0 0x3116 2 0 4294967295 START_GRBM_REG_SAVE 0 0 SPARE 1 31 mmRLC_SMU_PG_CTRL 0 0x3117 2 0 4294967295 START_PG 0 0 SPARE 1 31 mmRLC_SMU_PG_WAKE_UP_CTRL 0 0x3118 2 0 4294967295 START_PG_WAKE_UP 0 0 SPARE 1 31 mmRLC_SERDES_RD_MASTER_INDEX 0 0x3119 8 0 4294967295 CU_ID 0 3 SH_ID 4 5 SE_ID 6 8 SE_NONCU_ID 9 9 SE_NONCU 10 10 NON_SE 11 13 DATA_REG_ID 14 15 SPARE 16 31 mmRLC_SERDES_RD_DATA_0 0 0x311a 1 0 4294967295 DATA 0 31 mmRLC_SERDES_RD_DATA_1 0 0x311b 1 0 4294967295 DATA 0 31 mmRLC_SERDES_RD_DATA_2 0 0x311c 1 0 4294967295 DATA 0 31 mmRLC_SERDES_WR_CU_MASTER_MASK 0 0x311d 1 0 4294967295 MASTER_MASK 0 31 mmRLC_SERDES_WR_NONCU_MASTER_MASK 0 0x311e 9 0 4294967295 SE_MASTER_MASK 0 15 GC_MASTER_MASK 16 16 TC0_MASTER_MASK 17 17 TC1_MASTER_MASK 18 18 SPARE0_MASTER_MASK 19 19 SPARE1_MASTER_MASK 20 20 SPARE2_MASTER_MASK 21 21 SPARE3_MASTER_MASK 22 22 RESERVED 23 31 mmRLC_SERDES_WR_CTRL 0 0x311f 18 0 4294967295 BPM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE_COMMAND 12 12 READ_COMMAND 13 13 RESERVED_1 14 15 CGLS_ENABLE 16 16 CGLS_DISABLE 17 17 CGLS_ON 18 18 CGLS_OFF 19 19 CGCG_OVERRIDE_0 20 20 CGCG_OVERRIDE_1 21 21 MGCG_OVERRIDE_0 22 22 MGCG_OVERRIDE_1 23 23 RESERVED_2 24 27 REG_ADDR 28 31 mmRLC_SERDES_WR_DATA 0 0x3120 1 0 4294967295 DATA 0 31 mmRLC_SERDES_CU_MASTER_BUSY 0 0x3121 1 0 4294967295 BUSY_BUSY 0 31 mmRLC_SERDES_NONCU_MASTER_BUSY 0 0x3122 9 0 4294967295 SE_MASTER_BUSY 0 15 GC_MASTER_BUSY 16 16 TC0_MASTER_BUSY 17 17 TC1_MASTER_BUSY 18 18 SPARE0_MASTER_BUSY 19 19 SPARE1_MASTER_BUSY 20 20 SPARE2_MASTER_BUSY 21 21 SPARE3_MASTER_BUSY 22 22 RESERVED 23 31 mmRLC_GPM_GENERAL_0 0 0x3123 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_1 0 0x3124 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_2 0 0x3125 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_3 0 0x3126 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_4 0 0x3127 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_5 0 0x3128 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_6 0 0x3129 1 0 4294967295 DATA 0 31 mmRLC_GPM_GENERAL_7 0 0x312a 1 0 4294967295 DATA 0 31 mmRLC_GPM_CU_PD_TIMEOUT 0 0x312b 1 0 4294967295 TIMEOUT 0 31 mmRLC_GPM_SCRATCH_ADDR 0 0x312c 2 0 4294967295 ADDR 0 8 RESERVED 9 31 mmRLC_GPM_SCRATCH_DATA 0 0x312d 1 0 4294967295 DATA 0 31 mmRLC_STATIC_PG_STATUS 0 0x312e 1 0 4294967295 PG_STATUS_CU_MASK 0 31 mmRLC_GPM_PERF_COUNT_0 0 0x312f 8 0 4294967295 FEATURE_SEL 0 3 SE_INDEX 4 7 SH_INDEX 8 11 CU_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 mmRLC_GPM_PERF_COUNT_1 0 0x3130 8 0 4294967295 FEATURE_SEL 0 3 SE_INDEX 4 7 SH_INDEX 8 11 CU_INDEX 12 15 EVENT_SEL 16 17 UNUSED 18 19 ENABLE 20 20 RESERVED 21 31 mmRLC_GPR_REG1 0 0x3139 1 0 4294967295 DATA 0 31 mmRLC_GPR_REG2 0 0x313a 1 0 4294967295 DATA 0 31 mmRLC_SPM_VMID 0 0x3131 2 0 4294967295 RLC_SPM_VMID 0 3 RESERVED 4 31 mmRLC_SPM_INT_CNTL 0 0x3132 2 0 4294967295 RLC_SPM_INT_CNTL 0 0 RESERVED 1 31 mmRLC_SPM_INT_STATUS 0 0x3133 2 0 4294967295 RLC_SPM_INT_STATUS 0 0 RESERVED 1 31 mmRLC_SPM_DEBUG_SELECT 0 0x3134 4 0 4294967295 SELECT 0 7 RESERVED 8 14 RLC_SPM_DEBUG_MODE 15 15 RLC_SPM_NUM_SAMPLE 16 31 mmRLC_SPM_DEBUG 0 0x3135 1 0 4294967295 DATA 0 31 mmRLC_GPM_LOG_ADDR 0 0x3136 1 0 4294967295 ADDR 0 31 mmRLC_GPM_LOG_SIZE 0 0x3137 1 0 4294967295 SIZE 0 31 mmRLC_GPM_LOG_CONT 0 0x3138 1 0 4294967295 CONT 0 31 mmRLC_SPM_PERFMON_CNTL 0 0xdc80 4 0 4294967295 RESERVED1 0 11 PERFMON_RING_MODE 12 13 RESERVED 14 15 PERFMON_SAMPLE_INTERVAL 16 31 mmRLC_SPM_PERFMON_RING_BASE_LO 0 0xdc81 1 0 4294967295 RING_BASE_LO 0 31 mmRLC_SPM_PERFMON_RING_BASE_HI 0 0xdc82 2 0 4294967295 RING_BASE_HI 0 15 RESERVED 16 31 mmRLC_SPM_PERFMON_RING_SIZE 0 0xdc83 1 0 4294967295 RING_BASE_SIZE 0 31 mmRLC_SPM_PERFMON_SEGMENT_SIZE 0 0xdc84 7 0 4294967295 PERFMON_SEGMENT_SIZE 0 7 RESERVED1 8 10 GLOBAL_NUM_LINE 11 15 SE0_NUM_LINE 16 20 SE1_NUM_LINE 21 25 SE2_NUM_LINE 26 30 RESERVED 31 31 mmRLC_SPM_SE_MUXSEL_ADDR 0 0xdc85 1 0 4294967295 PERFMON_SEL_ADDR 0 31 mmRLC_SPM_SE_MUXSEL_DATA 0 0xdc86 1 0 4294967295 PERFMON_SEL_DATA 0 31 mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0 0xdc87 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0 0xdc88 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0 0xdc89 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0 0xdc8a 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0 0xdc8b 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0 0xdc8c 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0 0xdc8d 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0 0xdc8e 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0 0xdc90 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0 0xdc91 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0 0xdc92 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0 0xdc93 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0 0xdc94 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0 0xdc95 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0 0xdc96 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0 0xdc97 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0 0xdc98 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0 0xdc99 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0 0xdc9a 2 0 4294967295 PERFMON_SAMPLE_DELAY 0 7 RESERVED 8 31 mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0 0xdc9b 1 0 4294967295 PERFMON_SEL_ADDR 0 31 mmRLC_SPM_GLOBAL_MUXSEL_DATA 0 0xdc9c 1 0 4294967295 PERFMON_SEL_DATA 0 31 mmRLC_SPM_RING_RDPTR 0 0xdc9d 1 0 4294967295 PERFMON_RING_RDPTR 0 31 mmRLC_SPM_SEGMENT_THRESHOLD 0 0xdc9e 1 0 4294967295 NUM_SEGMENT_THRESHOLD 0 31 mmSPI_PS_INPUT_CNTL_0 0 0xa191 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_1 0 0xa192 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_2 0 0xa193 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_3 0 0xa194 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_4 0 0xa195 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_5 0 0xa196 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_6 0 0xa197 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_7 0 0xa198 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_8 0 0xa199 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_9 0 0xa19a 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_10 0 0xa19b 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_11 0 0xa19c 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_12 0 0xa19d 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_13 0 0xa19e 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_14 0 0xa19f 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_15 0 0xa1a0 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_16 0 0xa1a1 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_17 0 0xa1a2 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_18 0 0xa1a3 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_19 0 0xa1a4 6 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 CYL_WRAP 13 16 PT_SPRITE_TEX 17 17 DUP 18 18 mmSPI_PS_INPUT_CNTL_20 0 0xa1a5 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_21 0 0xa1a6 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_22 0 0xa1a7 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_23 0 0xa1a8 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_24 0 0xa1a9 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_25 0 0xa1aa 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_26 0 0xa1ab 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_27 0 0xa1ac 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_28 0 0xa1ad 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_29 0 0xa1ae 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_30 0 0xa1af 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_PS_INPUT_CNTL_31 0 0xa1b0 4 0 4294967295 OFFSET 0 5 DEFAULT_VAL 8 9 FLAT_SHADE 10 10 DUP 18 18 mmSPI_VS_OUT_CONFIG 0 0xa1b1 2 0 4294967295 VS_EXPORT_COUNT 1 5 VS_HALF_PACK 6 6 mmSPI_PS_INPUT_ENA 0 0xa1b3 16 0 4294967295 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 mmSPI_PS_INPUT_ADDR 0 0xa1b4 16 0 4294967295 PERSP_SAMPLE_ENA 0 0 PERSP_CENTER_ENA 1 1 PERSP_CENTROID_ENA 2 2 PERSP_PULL_MODEL_ENA 3 3 LINEAR_SAMPLE_ENA 4 4 LINEAR_CENTER_ENA 5 5 LINEAR_CENTROID_ENA 6 6 LINE_STIPPLE_TEX_ENA 7 7 POS_X_FLOAT_ENA 8 8 POS_Y_FLOAT_ENA 9 9 POS_Z_FLOAT_ENA 10 10 POS_W_FLOAT_ENA 11 11 FRONT_FACE_ENA 12 12 ANCILLARY_ENA 13 13 SAMPLE_COVERAGE_ENA 14 14 POS_FIXED_PT_ENA 15 15 mmSPI_INTERP_CONTROL_0 0 0xa1b5 7 0 4294967295 FLAT_SHADE_ENA 0 0 PNT_SPRITE_ENA 1 1 PNT_SPRITE_OVRD_X 2 4 PNT_SPRITE_OVRD_Y 5 7 PNT_SPRITE_OVRD_Z 8 10 PNT_SPRITE_OVRD_W 11 13 PNT_SPRITE_TOP_1 14 14 mmSPI_PS_IN_CONTROL 0 0xa1b6 3 0 4294967295 NUM_INTERP 0 5 PARAM_GEN 6 6 BC_OPTIMIZE_DISABLE 14 14 mmSPI_BARYC_CNTL 0 0xa1b8 7 0 4294967295 PERSP_CENTER_CNTL 0 0 PERSP_CENTROID_CNTL 4 4 LINEAR_CENTER_CNTL 8 8 LINEAR_CENTROID_CNTL 12 12 POS_FLOAT_LOCATION 16 17 POS_FLOAT_ULC 20 20 FRONT_FACE_ALL_BITS 24 24 mmSPI_TMPRING_SIZE 0 0xa1ba 2 0 4294967295 WAVES 0 11 WAVESIZE 12 24 mmSPI_SHADER_POS_FORMAT 0 0xa1c3 4 0 4294967295 POS0_EXPORT_FORMAT 0 3 POS1_EXPORT_FORMAT 4 7 POS2_EXPORT_FORMAT 8 11 POS3_EXPORT_FORMAT 12 15 mmSPI_SHADER_Z_FORMAT 0 0xa1c4 1 0 4294967295 Z_EXPORT_FORMAT 0 3 mmSPI_SHADER_COL_FORMAT 0 0xa1c5 8 0 4294967295 COL0_EXPORT_FORMAT 0 3 COL1_EXPORT_FORMAT 4 7 COL2_EXPORT_FORMAT 8 11 COL3_EXPORT_FORMAT 12 15 COL4_EXPORT_FORMAT 16 19 COL5_EXPORT_FORMAT 20 23 COL6_EXPORT_FORMAT 24 27 COL7_EXPORT_FORMAT 28 31 mmSPI_ARB_PRIORITY 0 0x31c0 8 0 4294967295 PIPE_ORDER_TS0 0 2 PIPE_ORDER_TS1 3 5 PIPE_ORDER_TS2 6 8 PIPE_ORDER_TS3 9 11 TS0_DUR_MULT 12 13 TS1_DUR_MULT 14 15 TS2_DUR_MULT 16 17 TS3_DUR_MULT 18 19 mmSPI_ARB_CYCLES_0 0 0x31c1 2 0 4294967295 TS0_DURATION 0 15 TS1_DURATION 16 31 mmSPI_ARB_CYCLES_1 0 0x31c2 2 0 4294967295 TS2_DURATION 0 15 TS3_DURATION 16 31 mmSPI_CDBG_SYS_GFX 0 0x31c3 7 0 4294967295 PS_EN 0 0 VS_EN 1 1 GS_EN 2 2 ES_EN 3 3 HS_EN 4 4 LS_EN 5 5 CS_EN 6 6 mmSPI_CDBG_SYS_HP3D 0 0x31c4 6 0 4294967295 PS_EN 0 0 VS_EN 1 1 GS_EN 2 2 ES_EN 3 3 HS_EN 4 4 LS_EN 5 5 mmSPI_CDBG_SYS_CS0 0 0x31c5 4 0 4294967295 PIPE0 0 7 PIPE1 8 15 PIPE2 16 23 PIPE3 24 31 mmSPI_CDBG_SYS_CS1 0 0x31c6 4 0 4294967295 PIPE0 0 7 PIPE1 8 15 PIPE2 16 23 PIPE3 24 31 mmSPI_WCL_PIPE_PERCENT_GFX 0 0x31c7 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_HP3D 0 0x31c8 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS0 0 0x31c9 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS1 0 0x31ca 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS2 0 0x31cb 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS3 0 0x31cc 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS4 0 0x31cd 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS5 0 0x31ce 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS6 0 0x31cf 1 0 4294967295 VALUE 0 4 mmSPI_WCL_PIPE_PERCENT_CS7 0 0x31d0 1 0 4294967295 VALUE 0 4 mmSPI_GDBG_WAVE_CNTL 0 0x31d1 1 0 4294967295 STALL_RA 0 0 mmSPI_GDBG_TRAP_CONFIG 0 0x31d2 8 0 4294967295 ME_SEL 0 1 PIPE_SEL 2 3 QUEUE_SEL 4 6 ME_MATCH 7 7 PIPE_MATCH 8 8 QUEUE_MATCH 9 9 TRAP_EN 15 15 VMID_SEL 16 31 mmSPI_GDBG_TRAP_MASK 0 0x31d3 2 0 4294967295 EXCP_EN 0 8 REPLACE 9 9 mmSPI_GDBG_TBA_LO 0 0x31d4 1 0 4294967295 MEM_BASE 0 31 mmSPI_GDBG_TBA_HI 0 0x31d5 1 0 4294967295 MEM_BASE 0 7 mmSPI_GDBG_TMA_LO 0 0x31d6 1 0 4294967295 MEM_BASE 0 31 mmSPI_GDBG_TMA_HI 0 0x31d7 1 0 4294967295 MEM_BASE 0 7 mmSPI_GDBG_TRAP_DATA0 0 0x31d8 1 0 4294967295 DATA 0 31 mmSPI_GDBG_TRAP_DATA1 0 0x31d9 1 0 4294967295 DATA 0 31 mmSPI_RESET_DEBUG 0 0x31da 5 0 4294967295 DISABLE_GFX_RESET 0 0 DISABLE_GFX_RESET_PER_VMID 1 1 DISABLE_GFX_RESET_ALL_VMID 2 2 DISABLE_GFX_RESET_RESOURCE 3 3 DISABLE_GFX_RESET_PRIORITY 4 4 mmSPI_COMPUTE_QUEUE_RESET 0 0x31db 1 0 4294967295 RESET 0 0 mmSPI_RESOURCE_RESERVE_CU_0 0 0x31dc 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_1 0 0x31dd 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_2 0 0x31de 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_3 0 0x31df 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_4 0 0x31e0 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_5 0 0x31e1 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_6 0 0x31e2 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_7 0 0x31e3 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_8 0 0x31e4 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_CU_9 0 0x31e5 5 0 4294967295 VGPR 0 3 SGPR 4 7 LDS 8 11 WAVES 12 14 BARRIERS 15 18 mmSPI_RESOURCE_RESERVE_EN_CU_0 0 0x31e6 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_1 0 0x31e7 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_2 0 0x31e8 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_3 0 0x31e9 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_4 0 0x31ea 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_5 0 0x31eb 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_6 0 0x31ec 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_7 0 0x31ed 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_8 0 0x31ee 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_RESOURCE_RESERVE_EN_CU_9 0 0x31ef 4 0 4294967295 EN 0 0 TYPE_MASK 1 15 QUEUE_MASK 16 23 RESERVE_SPACE_ONLY 24 24 mmSPI_PS_MAX_WAVE_ID 0 0x243a 1 0 4294967295 MAX_WAVE_ID 0 11 mmSPI_CONFIG_CNTL 0 0x2440 6 0 4294967295 GPR_WRITE_PRIORITY 0 20 EXP_PRIORITY_ORDER 21 23 ENABLE_SQG_TOP_EVENTS 24 24 ENABLE_SQG_BOP_EVENTS 25 25 RSRC_MGMT_RESET 26 26 TTRACE_STALL_ALL 27 27 mmSPI_DEBUG_CNTL 0 0x2441 15 0 4294967295 DEBUG_GRBM_OVERRIDE 0 0 DEBUG_THREAD_TYPE_SEL 1 3 DEBUG_GROUP_SEL 4 9 DEBUG_SIMD_SEL 10 15 DEBUG_SH_SEL 16 16 SPI_ECO_SPARE_0 17 17 SPI_ECO_SPARE_1 18 18 SPI_ECO_SPARE_2 19 19 SPI_ECO_SPARE_3 20 20 SPI_ECO_SPARE_4 21 21 SPI_ECO_SPARE_5 22 22 SPI_ECO_SPARE_6 23 23 SPI_ECO_SPARE_7 24 24 DEBUG_PIPE_SEL 25 27 DEBUG_REG_EN 31 31 mmSPI_DEBUG_READ 0 0x2442 1 0 4294967295 DATA 0 23 mmSPI_PERFCOUNTER0_SELECT 0 0xd980 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmSPI_PERFCOUNTER1_SELECT 0 0xd981 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmSPI_PERFCOUNTER2_SELECT 0 0xd982 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmSPI_PERFCOUNTER3_SELECT 0 0xd983 3 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 mmSPI_PERFCOUNTER0_SELECT1 0 0xd984 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmSPI_PERFCOUNTER1_SELECT1 0 0xd985 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmSPI_PERFCOUNTER2_SELECT1 0 0xd986 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmSPI_PERFCOUNTER3_SELECT1 0 0xd987 2 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 mmSPI_PERFCOUNTER4_SELECT 0 0xd988 1 0 4294967295 PERF_SEL 0 7 mmSPI_PERFCOUNTER5_SELECT 0 0xd989 1 0 4294967295 PERF_SEL 0 7 mmSPI_PERFCOUNTER_BINS 0 0xd98a 8 0 4294967295 BIN0_MIN 0 3 BIN0_MAX 4 7 BIN1_MIN 8 11 BIN1_MAX 12 15 BIN2_MIN 16 19 BIN2_MAX 20 23 BIN3_MIN 24 27 BIN3_MAX 28 31 mmSPI_PERFCOUNTER0_HI 0 0xd180 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER0_LO 0 0xd181 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER1_HI 0 0xd182 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER1_LO 0 0xd183 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER2_HI 0 0xd184 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER2_LO 0 0xd185 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER3_HI 0 0xd186 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER3_LO 0 0xd187 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER4_HI 0 0xd188 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER4_LO 0 0xd189 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_PERFCOUNTER5_HI 0 0xd18a 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSPI_PERFCOUNTER5_LO 0 0xd18b 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSPI_CONFIG_CNTL_1 0 0x244f 8 0 4294967295 VTX_DONE_DELAY 0 3 INTERP_ONE_PRIM_PER_ROW 4 4 PC_LIMIT_ENABLE 6 6 PC_LIMIT_STRICT 7 7 CRC_SIMD_ID_WADDR_DISABLE 8 8 LBPW_CU_CHK_MODE 9 9 LBPW_CU_CHK_CNT 10 13 PC_LIMIT_SIZE 16 31 mmSPI_DEBUG_BUSY 0 0x2450 24 0 4294967295 LS_BUSY 0 0 HS_BUSY 1 1 ES_BUSY 2 2 GS_BUSY 3 3 VS_BUSY 4 4 PS0_BUSY 5 5 PS1_BUSY 6 6 CSG_BUSY 7 7 CS0_BUSY 8 8 CS1_BUSY 9 9 CS2_BUSY 10 10 CS3_BUSY 11 11 CS4_BUSY 12 12 CS5_BUSY 13 13 CS6_BUSY 14 14 CS7_BUSY 15 15 LDS_WR_CTL0_BUSY 16 16 LDS_WR_CTL1_BUSY 17 17 RSRC_ALLOC0_BUSY 18 18 RSRC_ALLOC1_BUSY 19 19 PC_DEALLOC_BUSY 20 20 EVENT_CLCTR_BUSY 21 21 GRBM_BUSY 22 22 SPIS_BUSY 23 23 mmCGTS_SM_CTRL_REG 0 0xf000 10 0 4294967295 ON_SEQ_DELAY 0 3 OFF_SEQ_DELAY 4 11 MGCG_ENABLED 12 12 BASE_MODE 16 16 SM_MODE 17 19 SM_MODE_ENABLE 20 20 OVERRIDE 21 21 LS_OVERRIDE 22 22 ON_MONITOR_ADD_EN 23 23 ON_MONITOR_ADD 24 31 mmCGTS_RD_CTRL_REG 0 0xf001 2 0 4294967295 ROW_MUX_SEL 0 4 REG_MUX_SEL 8 12 mmCGTS_RD_REG 0 0xf002 1 0 4294967295 READ_DATA 0 13 mmCGTS_TCC_DISABLE 0 0xf003 1 0 4294967295 TCC_DISABLE 16 31 mmCGTS_USER_TCC_DISABLE 0 0xf004 1 0 4294967295 TCC_DISABLE 16 31 mmCGTS_CU0_SP0_CTRL_REG 0 0xf008 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU0_LDS_SQ_CTRL_REG 0 0xf009 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU0_TA_SQC_CTRL_REG 0 0xf00a 10 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU0_SP1_CTRL_REG 0 0xf00b 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU0_TD_TCP_CTRL_REG 0 0xf00c 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU1_SP0_CTRL_REG 0 0xf00d 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU1_LDS_SQ_CTRL_REG 0 0xf00e 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU1_TA_CTRL_REG 0 0xf00f 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU1_SP1_CTRL_REG 0 0xf010 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU1_TD_TCP_CTRL_REG 0 0xf011 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU2_SP0_CTRL_REG 0 0xf012 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU2_LDS_SQ_CTRL_REG 0 0xf013 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU2_TA_CTRL_REG 0 0xf014 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU2_SP1_CTRL_REG 0 0xf015 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU2_TD_TCP_CTRL_REG 0 0xf016 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU3_SP0_CTRL_REG 0 0xf017 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU3_LDS_SQ_CTRL_REG 0 0xf018 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU3_TA_CTRL_REG 0 0xf019 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU3_SP1_CTRL_REG 0 0xf01a 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU3_TD_TCP_CTRL_REG 0 0xf01b 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU4_SP0_CTRL_REG 0 0xf01c 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU4_LDS_SQ_CTRL_REG 0 0xf01d 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU4_TA_SQC_CTRL_REG 0 0xf01e 10 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU4_SP1_CTRL_REG 0 0xf01f 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU4_TD_TCP_CTRL_REG 0 0xf020 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU5_SP0_CTRL_REG 0 0xf021 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU5_LDS_SQ_CTRL_REG 0 0xf022 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU5_TA_CTRL_REG 0 0xf023 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU5_SP1_CTRL_REG 0 0xf024 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU5_TD_TCP_CTRL_REG 0 0xf025 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU6_SP0_CTRL_REG 0 0xf026 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU6_LDS_SQ_CTRL_REG 0 0xf027 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU6_TA_CTRL_REG 0 0xf028 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU6_SP1_CTRL_REG 0 0xf029 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU6_TD_TCP_CTRL_REG 0 0xf02a 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU7_SP0_CTRL_REG 0 0xf02b 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU7_LDS_SQ_CTRL_REG 0 0xf02c 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU7_TA_CTRL_REG 0 0xf02d 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU7_SP1_CTRL_REG 0 0xf02e 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU7_TD_TCP_CTRL_REG 0 0xf02f 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU8_SP0_CTRL_REG 0 0xf030 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU8_LDS_SQ_CTRL_REG 0 0xf031 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU8_TA_SQC_CTRL_REG 0 0xf032 10 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU8_SP1_CTRL_REG 0 0xf033 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU8_TD_TCP_CTRL_REG 0 0xf034 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU9_SP0_CTRL_REG 0 0xf035 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU9_LDS_SQ_CTRL_REG 0 0xf036 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU9_TA_CTRL_REG 0 0xf037 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU9_SP1_CTRL_REG 0 0xf038 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU9_TD_TCP_CTRL_REG 0 0xf039 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU10_SP0_CTRL_REG 0 0xf03a 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU10_LDS_SQ_CTRL_REG 0 0xf03b 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU10_TA_CTRL_REG 0 0xf03c 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU10_SP1_CTRL_REG 0 0xf03d 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU10_TD_TCP_CTRL_REG 0 0xf03e 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU11_SP0_CTRL_REG 0 0xf03f 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU11_LDS_SQ_CTRL_REG 0 0xf040 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU11_TA_CTRL_REG 0 0xf041 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU11_SP1_CTRL_REG 0 0xf042 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU11_TD_TCP_CTRL_REG 0 0xf043 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU12_SP0_CTRL_REG 0 0xf044 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU12_LDS_SQ_CTRL_REG 0 0xf045 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU12_TA_SQC_CTRL_REG 0 0xf046 10 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 SQC 16 22 SQC_OVERRIDE 23 23 SQC_BUSY_OVERRIDE 24 25 SQC_LS_OVERRIDE 26 26 SQC_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU12_SP1_CTRL_REG 0 0xf047 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU12_TD_TCP_CTRL_REG 0 0xf048 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU13_SP0_CTRL_REG 0 0xf049 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU13_LDS_SQ_CTRL_REG 0 0xf04a 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU13_TA_CTRL_REG 0 0xf04b 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU13_SP1_CTRL_REG 0 0xf04c 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU13_TD_TCP_CTRL_REG 0 0xf04d 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU14_SP0_CTRL_REG 0 0xf04e 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU14_LDS_SQ_CTRL_REG 0 0xf04f 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU14_TA_CTRL_REG 0 0xf050 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU14_SP1_CTRL_REG 0 0xf051 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU14_TD_TCP_CTRL_REG 0 0xf052 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU15_SP0_CTRL_REG 0 0xf053 10 0 4294967295 SP00 0 6 SP00_OVERRIDE 7 7 SP00_BUSY_OVERRIDE 8 9 SP00_LS_OVERRIDE 10 10 SP00_SIMDBUSY_OVERRIDE 11 11 SP01 16 22 SP01_OVERRIDE 23 23 SP01_BUSY_OVERRIDE 24 25 SP01_LS_OVERRIDE 26 26 SP01_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU15_LDS_SQ_CTRL_REG 0 0xf054 10 0 4294967295 LDS 0 6 LDS_OVERRIDE 7 7 LDS_BUSY_OVERRIDE 8 9 LDS_LS_OVERRIDE 10 10 LDS_SIMDBUSY_OVERRIDE 11 11 SQ 16 22 SQ_OVERRIDE 23 23 SQ_BUSY_OVERRIDE 24 25 SQ_LS_OVERRIDE 26 26 SQ_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU15_TA_CTRL_REG 0 0xf055 5 0 4294967295 TA 0 6 TA_OVERRIDE 7 7 TA_BUSY_OVERRIDE 8 9 TA_LS_OVERRIDE 10 10 TA_SIMDBUSY_OVERRIDE 11 11 mmCGTS_CU15_SP1_CTRL_REG 0 0xf056 10 0 4294967295 SP10 0 6 SP10_OVERRIDE 7 7 SP10_BUSY_OVERRIDE 8 9 SP10_LS_OVERRIDE 10 10 SP10_SIMDBUSY_OVERRIDE 11 11 SP11 16 22 SP11_OVERRIDE 23 23 SP11_BUSY_OVERRIDE 24 25 SP11_LS_OVERRIDE 26 26 SP11_SIMDBUSY_OVERRIDE 27 27 mmCGTS_CU15_TD_TCP_CTRL_REG 0 0xf057 10 0 4294967295 TD 0 6 TD_OVERRIDE 7 7 TD_BUSY_OVERRIDE 8 9 TD_LS_OVERRIDE 10 10 TD_SIMDBUSY_OVERRIDE 11 11 TCP 16 22 TCP_OVERRIDE 23 23 TCP_BUSY_OVERRIDE 24 25 TCP_LS_OVERRIDE 26 26 TCP_SIMDBUSY_OVERRIDE 27 27 mmCGTT_SPI_CLK_CTRL 0 0xf080 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 GRP5_CG_OFF_HYST 18 23 GRP5_CG_OVERRIDE 24 24 ALL_CLK_ON_OVERRIDE 26 26 GRP3_OVERRIDE 27 27 GRP2_OVERRIDE 28 28 GRP1_OVERRIDE 29 29 GRP0_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmCGTT_PC_CLK_CTRL 0 0xf081 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 GRP5_CG_OFF_HYST 18 23 GRP5_CG_OVERRIDE 24 24 BACK_CLK_ON_OVERRIDE 25 25 FRONT_CLK_ON_OVERRIDE 26 26 CORE3_OVERRIDE 27 27 CORE2_OVERRIDE 28 28 CORE1_OVERRIDE 29 29 CORE0_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmCGTT_BCI_CLK_CTRL 0 0xf082 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 CORE6_OVERRIDE 24 24 CORE5_OVERRIDE 25 25 CORE4_OVERRIDE 26 26 CORE3_OVERRIDE 27 27 CORE2_OVERRIDE 28 28 CORE1_OVERRIDE 29 29 CORE0_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmSPI_WF_LIFETIME_CNTL 0 0x24aa 2 0 4294967295 SAMPLE_PERIOD 0 3 EN 4 4 mmSPI_WF_LIFETIME_LIMIT_0 0 0x24ab 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_1 0 0x24ac 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_2 0 0x24ad 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_3 0 0x24ae 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_4 0 0x24af 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_5 0 0x24b0 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_6 0 0x24b1 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_7 0 0x24b2 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_8 0 0x24b3 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_LIMIT_9 0 0x24b4 2 0 4294967295 MAX_CNT 0 30 EN_WARN 31 31 mmSPI_WF_LIFETIME_STATUS_0 0 0x24b5 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_1 0 0x24b6 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_2 0 0x24b7 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_3 0 0x24b8 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_4 0 0x24b9 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_5 0 0x24ba 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_6 0 0x24bb 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_7 0 0x24bc 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_8 0 0x24bd 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_9 0 0x24be 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_10 0 0x24bf 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_11 0 0x24c0 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_12 0 0x24c1 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_13 0 0x24c2 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_14 0 0x24c3 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_15 0 0x24c4 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_16 0 0x24c5 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_17 0 0x24c6 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_18 0 0x24c7 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_19 0 0x24c8 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_STATUS_20 0 0x24c9 2 0 4294967295 MAX_CNT 0 30 INT_SENT 31 31 mmSPI_WF_LIFETIME_DEBUG 0 0x24ca 2 0 4294967295 START_VALUE 0 30 OVERRIDE_EN 31 31 mmSPI_SLAVE_DEBUG_BUSY 0 0x24d3 22 0 4294967295 LS_VTX_BUSY 0 0 HS_VTX_BUSY 1 1 ES_VTX_BUSY 2 2 GS_VTX_BUSY 3 3 VS_VTX_BUSY 4 4 VGPR_WC00_BUSY 5 5 VGPR_WC01_BUSY 6 6 VGPR_WC10_BUSY 7 7 VGPR_WC11_BUSY 8 8 SGPR_WC00_BUSY 9 9 SGPR_WC01_BUSY 10 10 SGPR_WC02_BUSY 11 11 SGPR_WC03_BUSY 12 12 SGPR_WC10_BUSY 13 13 SGPR_WC11_BUSY 14 14 SGPR_WC12_BUSY 15 15 SGPR_WC13_BUSY 16 16 WAVEBUFFER0_BUSY 17 17 WAVEBUFFER1_BUSY 18 18 WAVE_WC0_BUSY 19 19 WAVE_WC1_BUSY 20 20 EVENT_CNTL_BUSY 21 21 mmSPI_LB_CTR_CTRL 0 0x24d4 1 0 4294967295 LOAD 0 0 mmSPI_LB_CU_MASK 0 0x24d5 1 0 4294967295 CU_MASK 0 15 mmSPI_LB_DATA_REG 0 0x24d6 1 0 4294967295 CNT_DATA 0 31 mmSPI_PG_ENABLE_STATIC_CU_MASK 0 0x24d7 1 0 4294967295 CU_MASK 0 15 mmSPI_GDS_CREDITS 0 0x24d8 3 0 4294967295 DS_DATA_CREDITS 0 7 DS_CMD_CREDITS 8 15 UNUSED 16 31 mmSPI_SX_EXPORT_BUFFER_SIZES 0 0x24d9 2 0 4294967295 COLOR_BUFFER_SIZE 0 15 POSITION_BUFFER_SIZE 16 31 mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0 0x24da 2 0 4294967295 COLOR_SCOREBOARD_SIZE 0 15 POSITION_SCOREBOARD_SIZE 16 31 mmSPI_CSQ_WF_ACTIVE_STATUS 0 0x24db 1 0 4294967295 ACTIVE 0 31 mmSPI_CSQ_WF_ACTIVE_COUNT_0 0 0x24dc 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_1 0 0x24dd 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_2 0 0x24de 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_3 0 0x24df 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_4 0 0x24e0 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_5 0 0x24e1 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_6 0 0x24e2 1 0 4294967295 COUNT 0 10 mmSPI_CSQ_WF_ACTIVE_COUNT_7 0 0x24e3 1 0 4294967295 COUNT 0 10 mmBCI_DEBUG_READ 0 0x24eb 1 0 4294967295 DATA 0 23 mmSPI_P0_TRAP_SCREEN_PSBA_LO 0 0x24ec 1 0 4294967295 MEM_BASE 0 31 mmSPI_P0_TRAP_SCREEN_PSBA_HI 0 0x24ed 1 0 4294967295 MEM_BASE 0 7 mmSPI_P0_TRAP_SCREEN_PSMA_LO 0 0x24ee 1 0 4294967295 MEM_BASE 0 31 mmSPI_P0_TRAP_SCREEN_PSMA_HI 0 0x24ef 1 0 4294967295 MEM_BASE 0 7 mmSPI_P0_TRAP_SCREEN_GPR_MIN 0 0x24f0 2 0 4294967295 VGPR_MIN 0 5 SGPR_MIN 6 9 mmSPI_P1_TRAP_SCREEN_PSBA_LO 0 0x24f1 1 0 4294967295 MEM_BASE 0 31 mmSPI_P1_TRAP_SCREEN_PSBA_HI 0 0x24f2 1 0 4294967295 MEM_BASE 0 7 mmSPI_P1_TRAP_SCREEN_PSMA_LO 0 0x24f3 1 0 4294967295 MEM_BASE 0 31 mmSPI_P1_TRAP_SCREEN_PSMA_HI 0 0x24f4 1 0 4294967295 MEM_BASE 0 7 mmSPI_P1_TRAP_SCREEN_GPR_MIN 0 0x24f5 2 0 4294967295 VGPR_MIN 0 5 SGPR_MIN 6 9 mmSPI_SHADER_TBA_LO_PS 0 0x2c00 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_PS 0 0x2c01 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_PS 0 0x2c02 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_PS 0 0x2c03 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_PS 0 0x2c08 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_PS 0 0x2c09 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_PS 0 0x2c0a 11 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 CU_GROUP_DISABLE 24 24 CACHE_CTL 25 27 CDBG_USER 28 28 mmSPI_SHADER_PGM_RSRC2_PS 0 0x2c0b 6 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 WAVE_CNT_EN 7 7 EXTRA_LDS_SIZE 8 15 EXCP_EN 16 24 mmSPI_SHADER_PGM_RSRC3_PS 0 0x2c07 3 0 4294967295 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_USER_DATA_PS_0 0 0x2c0c 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_1 0 0x2c0d 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_2 0 0x2c0e 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_3 0 0x2c0f 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_4 0 0x2c10 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_5 0 0x2c11 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_6 0 0x2c12 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_7 0 0x2c13 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_8 0 0x2c14 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_9 0 0x2c15 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_10 0 0x2c16 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_11 0 0x2c17 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_12 0 0x2c18 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_13 0 0x2c19 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_14 0 0x2c1a 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_PS_15 0 0x2c1b 1 0 4294967295 DATA 0 31 mmSPI_SHADER_TBA_LO_VS 0 0x2c40 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_VS 0 0x2c41 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_VS 0 0x2c42 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_VS 0 0x2c43 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_VS 0 0x2c48 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_VS 0 0x2c49 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_VS 0 0x2c4a 12 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 VGPR_COMP_CNT 24 25 CU_GROUP_ENABLE 26 26 CACHE_CTL 27 29 CDBG_USER 30 30 mmSPI_SHADER_PGM_RSRC2_VS 0 0x2c4b 10 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 SO_BASE0_EN 8 8 SO_BASE1_EN 9 9 SO_BASE2_EN 10 10 SO_BASE3_EN 11 11 SO_EN 12 12 EXCP_EN 13 21 mmSPI_SHADER_PGM_RSRC3_VS 0 0x2c46 3 0 4294967295 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_LATE_ALLOC_VS 0 0x2c47 1 0 4294967295 LIMIT 0 5 mmSPI_SHADER_USER_DATA_VS_0 0 0x2c4c 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_1 0 0x2c4d 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_2 0 0x2c4e 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_3 0 0x2c4f 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_4 0 0x2c50 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_5 0 0x2c51 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_6 0 0x2c52 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_7 0 0x2c53 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_8 0 0x2c54 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_9 0 0x2c55 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_10 0 0x2c56 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_11 0 0x2c57 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_12 0 0x2c58 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_13 0 0x2c59 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_14 0 0x2c5a 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_VS_15 0 0x2c5b 1 0 4294967295 DATA 0 31 mmSPI_SHADER_PGM_RSRC2_ES_VS 0 0x2c7c 6 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 EXCP_EN 8 16 LDS_SIZE 20 28 mmSPI_SHADER_PGM_RSRC2_LS_VS 0 0x2c7d 5 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 LDS_SIZE 7 15 EXCP_EN 16 24 mmSPI_SHADER_TBA_LO_GS 0 0x2c80 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_GS 0 0x2c81 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_GS 0 0x2c82 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_GS 0 0x2c83 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_GS 0 0x2c88 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_GS 0 0x2c89 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_GS 0 0x2c8a 11 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 CU_GROUP_ENABLE 24 24 CACHE_CTL 25 27 CDBG_USER 28 28 mmSPI_SHADER_PGM_RSRC2_GS 0 0x2c8b 4 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 EXCP_EN 7 15 mmSPI_SHADER_PGM_RSRC3_GS 0 0x2c87 3 0 4294967295 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_USER_DATA_GS_0 0 0x2c8c 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_1 0 0x2c8d 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_2 0 0x2c8e 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_3 0 0x2c8f 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_4 0 0x2c90 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_5 0 0x2c91 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_6 0 0x2c92 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_7 0 0x2c93 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_8 0 0x2c94 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_9 0 0x2c95 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_10 0 0x2c96 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_11 0 0x2c97 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_12 0 0x2c98 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_13 0 0x2c99 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_14 0 0x2c9a 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_GS_15 0 0x2c9b 1 0 4294967295 DATA 0 31 mmSPI_SHADER_PGM_RSRC2_ES_GS 0 0x2cbc 6 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 EXCP_EN 8 16 LDS_SIZE 20 28 mmSPI_SHADER_TBA_LO_ES 0 0x2cc0 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_ES 0 0x2cc1 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_ES 0 0x2cc2 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_ES 0 0x2cc3 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_ES 0 0x2cc8 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_ES 0 0x2cc9 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_ES 0 0x2cca 12 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 VGPR_COMP_CNT 24 25 CU_GROUP_ENABLE 26 26 CACHE_CTL 27 29 CDBG_USER 30 30 mmSPI_SHADER_PGM_RSRC2_ES 0 0x2ccb 6 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 EXCP_EN 8 16 LDS_SIZE 20 28 mmSPI_SHADER_PGM_RSRC3_ES 0 0x2cc7 3 0 4294967295 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_USER_DATA_ES_0 0 0x2ccc 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_1 0 0x2ccd 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_2 0 0x2cce 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_3 0 0x2ccf 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_4 0 0x2cd0 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_5 0 0x2cd1 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_6 0 0x2cd2 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_7 0 0x2cd3 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_8 0 0x2cd4 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_9 0 0x2cd5 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_10 0 0x2cd6 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_11 0 0x2cd7 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_12 0 0x2cd8 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_13 0 0x2cd9 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_14 0 0x2cda 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_ES_15 0 0x2cdb 1 0 4294967295 DATA 0 31 mmSPI_SHADER_PGM_RSRC2_LS_ES 0 0x2cfd 5 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 LDS_SIZE 7 15 EXCP_EN 16 24 mmSPI_SHADER_TBA_LO_HS 0 0x2d00 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_HS 0 0x2d01 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_HS 0 0x2d02 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_HS 0 0x2d03 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_HS 0 0x2d08 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_HS 0 0x2d09 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_HS 0 0x2d0a 10 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 CACHE_CTL 24 26 CDBG_USER 27 27 mmSPI_SHADER_PGM_RSRC2_HS 0 0x2d0b 6 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 OC_LDS_EN 7 7 TG_SIZE_EN 8 8 EXCP_EN 9 17 mmSPI_SHADER_PGM_RSRC3_HS 0 0x2d07 2 0 4294967295 WAVE_LIMIT 0 5 LOCK_LOW_THRESHOLD 6 9 mmSPI_SHADER_USER_DATA_HS_0 0 0x2d0c 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_1 0 0x2d0d 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_2 0 0x2d0e 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_3 0 0x2d0f 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_4 0 0x2d10 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_5 0 0x2d11 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_6 0 0x2d12 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_7 0 0x2d13 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_8 0 0x2d14 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_9 0 0x2d15 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_10 0 0x2d16 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_11 0 0x2d17 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_12 0 0x2d18 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_13 0 0x2d19 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_14 0 0x2d1a 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_HS_15 0 0x2d1b 1 0 4294967295 DATA 0 31 mmSPI_SHADER_PGM_RSRC2_LS_HS 0 0x2d3d 5 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 LDS_SIZE 7 15 EXCP_EN 16 24 mmSPI_SHADER_TBA_LO_LS 0 0x2d40 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TBA_HI_LS 0 0x2d41 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_TMA_LO_LS 0 0x2d42 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_TMA_HI_LS 0 0x2d43 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_LO_LS 0 0x2d48 1 0 4294967295 MEM_BASE 0 31 mmSPI_SHADER_PGM_HI_LS 0 0x2d49 1 0 4294967295 MEM_BASE 0 7 mmSPI_SHADER_PGM_RSRC1_LS 0 0x2d4a 11 0 4294967295 VGPRS 0 5 SGPRS 6 9 PRIORITY 10 11 FLOAT_MODE 12 19 PRIV 20 20 DX10_CLAMP 21 21 DEBUG_MODE 22 22 IEEE_MODE 23 23 VGPR_COMP_CNT 24 25 CACHE_CTL 26 28 CDBG_USER 29 29 mmSPI_SHADER_PGM_RSRC2_LS 0 0x2d4b 5 0 4294967295 SCRATCH_EN 0 0 USER_SGPR 1 5 TRAP_PRESENT 6 6 LDS_SIZE 7 15 EXCP_EN 16 24 mmSPI_SHADER_PGM_RSRC3_LS 0 0x2d47 3 0 4294967295 CU_EN 0 15 WAVE_LIMIT 16 21 LOCK_LOW_THRESHOLD 22 25 mmSPI_SHADER_USER_DATA_LS_0 0 0x2d4c 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_1 0 0x2d4d 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_2 0 0x2d4e 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_3 0 0x2d4f 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_4 0 0x2d50 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_5 0 0x2d51 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_6 0 0x2d52 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_7 0 0x2d53 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_8 0 0x2d54 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_9 0 0x2d55 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_10 0 0x2d56 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_11 0 0x2d57 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_12 0 0x2d58 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_13 0 0x2d59 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_14 0 0x2d5a 1 0 4294967295 DATA 0 31 mmSPI_SHADER_USER_DATA_LS_15 0 0x2d5b 1 0 4294967295 DATA 0 31 mmSQ_CONFIG 0 0x2300 9 0 4294967295 UNUSED 0 7 DEBUG_EN 8 8 DISABLE_SCA_BYPASS 9 9 DISABLE_IB_DEP_CHECK 10 10 ENABLE_SOFT_CLAUSE 11 11 EARLY_TA_DONE_DISABLE 12 12 DUA_FLAT_LOCK_ENABLE 13 13 DUA_LDS_BYPASS_DISABLE 14 14 DUA_FLAT_LDS_PINGPONG_DISABLE 15 15 mmSQC_CONFIG 0 0x2301 9 0 4294967295 INST_CACHE_SIZE 0 1 DATA_CACHE_SIZE 2 3 MISS_FIFO_DEPTH 4 5 HIT_FIFO_DEPTH 6 6 FORCE_ALWAYS_MISS 7 7 FORCE_IN_ORDER 8 8 IDENTITY_HASH_BANK 9 9 IDENTITY_HASH_SET 10 10 PER_VMID_INV_DISABLE 11 11 mmSQC_CACHES 0 0xc348 3 0 4294967295 INST_INVALIDATE 0 0 DATA_INVALIDATE 1 1 INVALIDATE_VOLATILE 2 2 mmSQ_RANDOM_WAVE_PRI 0 0x2303 3 0 4294967295 RET 0 6 RUI 7 9 RNG 10 20 mmSQ_REG_CREDITS 0 0x2304 6 0 4294967295 SRBM_CREDITS 0 5 CMD_CREDITS 8 11 REG_BUSY 28 28 SRBM_OVERFLOW 29 29 IMMED_OVERFLOW 30 30 CMD_OVERFLOW 31 31 mmSQ_FIFO_SIZES 0 0x2305 4 0 4294967295 INTERRUPT_FIFO_SIZE 0 3 TTRACE_FIFO_SIZE 8 11 EXPORT_BUF_SIZE 16 17 VMEM_DATA_FIFO_SIZE 18 19 mmSQ_INTERRUPT_AUTO_MASK 0 0x2314 1 0 4294967295 MASK 0 23 mmSQ_INTERRUPT_MSG_CTRL 0 0x2315 1 0 4294967295 STALL 0 0 mmSQ_PERFCOUNTER_CTRL 0 0xd9e0 9 0 4294967295 PS_EN 0 0 VS_EN 1 1 GS_EN 2 2 ES_EN 3 3 HS_EN 4 4 LS_EN 5 5 CS_EN 6 6 CNTR_RATE 8 12 DISABLE_FLUSH 13 13 mmSQ_PERFCOUNTER_MASK 0 0xd9e1 2 0 4294967295 SH0_MASK 0 15 SH1_MASK 16 31 mmSQ_PERFCOUNTER_CTRL2 0 0xd9e2 1 0 4294967295 FORCE_EN 0 0 mmCC_SQC_BANK_DISABLE 0 0x2307 4 0 4294967295 SQC0_BANK_DISABLE 16 19 SQC1_BANK_DISABLE 20 23 SQC2_BANK_DISABLE 24 27 SQC3_BANK_DISABLE 28 31 mmUSER_SQC_BANK_DISABLE 0 0x2308 4 0 4294967295 SQC0_BANK_DISABLE 16 19 SQC1_BANK_DISABLE 20 23 SQC2_BANK_DISABLE 24 27 SQC3_BANK_DISABLE 28 31 mmSQ_PERFCOUNTER0_LO 0 0xd1c0 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER1_LO 0 0xd1c2 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER2_LO 0 0xd1c4 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER3_LO 0 0xd1c6 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER4_LO 0 0xd1c8 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER5_LO 0 0xd1ca 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER6_LO 0 0xd1cc 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER7_LO 0 0xd1ce 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER8_LO 0 0xd1d0 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER9_LO 0 0xd1d2 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER10_LO 0 0xd1d4 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER11_LO 0 0xd1d6 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER12_LO 0 0xd1d8 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER13_LO 0 0xd1da 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER14_LO 0 0xd1dc 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER15_LO 0 0xd1de 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSQ_PERFCOUNTER0_HI 0 0xd1c1 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER1_HI 0 0xd1c3 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER2_HI 0 0xd1c5 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER3_HI 0 0xd1c7 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER4_HI 0 0xd1c9 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER5_HI 0 0xd1cb 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER6_HI 0 0xd1cd 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER7_HI 0 0xd1cf 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER8_HI 0 0xd1d1 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER9_HI 0 0xd1d3 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER10_HI 0 0xd1d5 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER11_HI 0 0xd1d7 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER12_HI 0 0xd1d9 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER13_HI 0 0xd1db 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER14_HI 0 0xd1dd 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER15_HI 0 0xd1df 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSQ_PERFCOUNTER0_SELECT 0 0xd9c0 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER1_SELECT 0 0xd9c1 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER2_SELECT 0 0xd9c2 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER3_SELECT 0 0xd9c3 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER4_SELECT 0 0xd9c4 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER5_SELECT 0 0xd9c5 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER6_SELECT 0 0xd9c6 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER7_SELECT 0 0xd9c7 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER8_SELECT 0 0xd9c8 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER9_SELECT 0 0xd9c9 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER10_SELECT 0 0xd9ca 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER11_SELECT 0 0xd9cb 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER12_SELECT 0 0xd9cc 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER13_SELECT 0 0xd9cd 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER14_SELECT 0 0xd9ce 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmSQ_PERFCOUNTER15_SELECT 0 0xd9cf 6 0 4294967295 PERF_SEL 0 7 SQC_BANK_MASK 12 15 SQC_CLIENT_MASK 16 19 SPM_MODE 20 23 SIMD_MASK 24 27 PERF_MODE 28 31 mmCGTT_SQ_CLK_CTRL 0 0xf08c 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 CORE_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmCGTT_SQG_CLK_CTRL 0 0xf08d 4 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 CORE_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmSQ_ALU_CLK_CTRL 0 0xf08e 2 0 4294967295 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 mmSQ_TEX_CLK_CTRL 0 0xf08f 2 0 4294967295 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 mmSQ_LDS_CLK_CTRL 0 0xf090 2 0 4294967295 FORCE_CU_ON_SH0 0 15 FORCE_CU_ON_SH1 16 31 mmSQ_POWER_THROTTLE 0 0xf091 3 0 4294967295 MIN_POWER 0 13 MAX_POWER 16 29 PHASE_OFFSET 30 31 mmSQ_POWER_THROTTLE2 0 0xf092 4 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 USE_REF_CLOCK 31 31 mmSQ_TIME_HI 0 0x237c 1 0 4294967295 TIME 0 31 mmSQ_TIME_LO 0 0x237d 1 0 4294967295 TIME 0 31 mmSQ_THREAD_TRACE_BASE 0 0x2380 1 0 4294967295 ADDR 0 31 mmSQ_THREAD_TRACE_BASE2 0 0x2385 2 0 4294967295 ADDR_HI 0 3 ATC 4 4 mmSQ_THREAD_TRACE_SIZE 0 0x2381 1 0 4294967295 SIZE 0 21 mmSQ_THREAD_TRACE_MASK 0 0x2382 8 0 4294967295 CU_SEL 0 4 SH_SEL 5 5 REG_STALL_EN 7 7 SIMD_EN 8 11 VM_ID_MASK 12 13 SPI_STALL_EN 14 14 SQ_STALL_EN 15 15 RANDOM_SEED 16 31 mmSQ_THREAD_TRACE_USERDATA_0 0 0xc340 1 0 4294967295 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_1 0 0xc341 1 0 4294967295 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_2 0 0xc342 1 0 4294967295 DATA 0 31 mmSQ_THREAD_TRACE_USERDATA_3 0 0xc343 1 0 4294967295 DATA 0 31 mmSQ_THREAD_TRACE_MODE 0 0x238e 15 0 4294967295 MASK_PS 0 2 MASK_VS 3 5 MASK_GS 6 8 MASK_ES 9 11 MASK_HS 12 14 MASK_LS 15 17 MASK_CS 18 20 MODE 21 22 CAPTURE_MODE 23 24 AUTOFLUSH_EN 25 25 PRIV 26 26 ISSUE_MASK 27 28 TEST_MODE 29 29 INTERRUPT_EN 30 30 WRAP 31 31 mmSQ_THREAD_TRACE_CTRL 0 0x238f 1 0 4294967295 RESET_BUFFER 31 31 mmSQ_THREAD_TRACE_TOKEN_MASK 0 0x2383 3 0 4294967295 TOKEN_MASK 0 15 REG_MASK 16 23 REG_DROP_ON_STALL 24 24 mmSQ_THREAD_TRACE_TOKEN_MASK2 0 0x2386 1 0 4294967295 INST_MASK 0 15 mmSQ_THREAD_TRACE_PERF_MASK 0 0x2384 2 0 4294967295 SH0_MASK 0 15 SH1_MASK 16 31 mmSQ_THREAD_TRACE_WPTR 0 0x238c 2 0 4294967295 WPTR 0 29 READ_OFFSET 30 31 mmSQ_THREAD_TRACE_STATUS 0 0x238d 5 0 4294967295 FINISH_PENDING 0 9 FINISH_DONE 16 25 NEW_BUF 29 29 BUSY 30 30 FULL 31 31 mmSQ_THREAD_TRACE_CNTR 0 0x2390 1 0 4294967295 CNTR 0 31 mmSQ_THREAD_TRACE_HIWATER 0 0x2392 1 0 4294967295 HIWATER 0 2 mmSQ_LB_CTR_CTRL 0 0x2398 3 0 4294967295 START 0 0 LOAD 1 1 CLEAR 2 2 mmSQ_LB_DATA_ALU_CYCLES 0 0x2399 1 0 4294967295 DATA 0 31 mmSQ_LB_DATA_TEX_CYCLES 0 0x239a 1 0 4294967295 DATA 0 31 mmSQ_LB_DATA_ALU_STALLS 0 0x239b 1 0 4294967295 DATA 0 31 mmSQ_LB_DATA_TEX_STALLS 0 0x239c 1 0 4294967295 DATA 0 31 mmSQC_SECDED_CNT 0 0x23a0 4 0 4294967295 INST_SEC 0 7 INST_DED 8 15 DATA_SEC 16 23 DATA_DED 24 31 mmSQ_SEC_CNT 0 0x23a1 3 0 4294967295 LDS_SEC 0 5 SGPR_SEC 8 12 VGPR_SEC 16 24 mmSQ_DED_CNT 0 0x23a2 3 0 4294967295 LDS_DED 0 5 SGPR_DED 8 12 VGPR_DED 16 24 mmSQ_DED_INFO 0 0x23a3 4 0 4294967295 WAVE_ID 0 3 SIMD_ID 4 5 SOURCE 6 8 VM_ID 9 12 mmSQ_BUF_RSRC_WORD0 0 0x23c0 1 0 4294967295 BASE_ADDRESS 0 31 mmSQ_BUF_RSRC_WORD1 0 0x23c1 4 0 4294967295 BASE_ADDRESS_HI 0 15 STRIDE 16 29 CACHE_SWIZZLE 30 30 SWIZZLE_ENABLE 31 31 mmSQ_BUF_RSRC_WORD2 0 0x23c2 1 0 4294967295 NUM_RECORDS 0 31 mmSQ_BUF_RSRC_WORD3 0 0x23c3 14 0 4294967295 DST_SEL_X 0 2 DST_SEL_Y 3 5 DST_SEL_Z 6 8 DST_SEL_W 9 11 NUM_FORMAT 12 14 DATA_FORMAT 15 18 ELEMENT_SIZE 19 20 INDEX_STRIDE 21 22 ADD_TID_ENABLE 23 23 ATC 24 24 HASH_ENABLE 25 25 HEAP 26 26 MTYPE 27 29 TYPE 30 31 mmSQ_IMG_RSRC_WORD0 0 0x23c4 1 0 4294967295 BASE_ADDRESS 0 31 mmSQ_IMG_RSRC_WORD1 0 0x23c5 5 0 4294967295 BASE_ADDRESS_HI 0 7 MIN_LOD 8 19 DATA_FORMAT 20 25 NUM_FORMAT 26 29 MTYPE 30 31 mmSQ_IMG_RSRC_WORD2 0 0x23c6 4 0 4294967295 WIDTH 0 13 HEIGHT 14 27 PERF_MOD 28 30 INTERLACED 31 31 mmSQ_IMG_RSRC_WORD3 0 0x23c7 11 0 4294967295 DST_SEL_X 0 2 DST_SEL_Y 3 5 DST_SEL_Z 6 8 DST_SEL_W 9 11 BASE_LEVEL 12 15 LAST_LEVEL 16 19 TILING_INDEX 20 24 POW2_PAD 25 25 MTYPE 26 26 ATC 27 27 TYPE 28 31 mmSQ_IMG_RSRC_WORD4 0 0x23c8 2 0 4294967295 DEPTH 0 12 PITCH 13 26 mmSQ_IMG_RSRC_WORD5 0 0x23c9 2 0 4294967295 BASE_ARRAY 0 12 LAST_ARRAY 13 25 mmSQ_IMG_RSRC_WORD6 0 0x23ca 4 0 4294967295 MIN_LOD_WARN 0 11 COUNTER_BANK_ID 12 19 LOD_HDW_CNT_EN 20 20 UNUNSED 21 31 mmSQ_IMG_RSRC_WORD7 0 0x23cb 1 0 4294967295 UNUNSED 0 31 mmSQ_IMG_SAMP_WORD0 0 0x23cc 13 0 4294967295 CLAMP_X 0 2 CLAMP_Y 3 5 CLAMP_Z 6 8 MAX_ANISO_RATIO 9 11 DEPTH_COMPARE_FUNC 12 14 FORCE_UNNORMALIZED 15 15 ANISO_THRESHOLD 16 18 MC_COORD_TRUNC 19 19 FORCE_DEGAMMA 20 20 ANISO_BIAS 21 26 TRUNC_COORD 27 27 DISABLE_CUBE_WRAP 28 28 FILTER_MODE 29 30 mmSQ_IMG_SAMP_WORD1 0 0x23cd 4 0 4294967295 MIN_LOD 0 11 MAX_LOD 12 23 PERF_MIP 24 27 PERF_Z 28 31 mmSQ_IMG_SAMP_WORD2 0 0x23ce 9 0 4294967295 LOD_BIAS 0 13 LOD_BIAS_SEC 14 19 XY_MAG_FILTER 20 21 XY_MIN_FILTER 22 23 Z_FILTER 24 25 MIP_FILTER 26 27 MIP_POINT_PRECLAMP 28 28 DISABLE_LSB_CEIL 29 29 FILTER_PREC_FIX 30 30 mmSQ_IMG_SAMP_WORD3 0 0x23cf 2 0 4294967295 BORDER_COLOR_PTR 0 11 BORDER_COLOR_TYPE 30 31 mmSQ_FLAT_SCRATCH_WORD0 0 0x23d0 1 0 4294967295 SIZE 0 18 mmSQ_FLAT_SCRATCH_WORD1 0 0x23d1 1 0 4294967295 OFFSET 0 23 mmSQ_IND_INDEX 0 0x2378 8 0 4294967295 WAVE_ID 0 3 SIMD_ID 4 5 THREAD_ID 6 11 AUTO_INCR 12 12 FORCE_READ 13 13 READ_TIMEOUT 14 14 UNINDEXED 15 15 INDEX 16 31 mmSQ_IND_CMD 0 0x237a 0 0 4294967295 mmSQ_CMD 0 0x237b 8 0 4294967295 CMD 0 2 MODE 4 6 CHECK_VMID 7 7 TRAP_ID 8 10 WAVE_ID 16 19 SIMD_ID 20 21 QUEUE_ID 24 26 VM_ID 28 31 mmSQ_IND_DATA 0 0x2379 1 0 4294967295 DATA 0 31 mmSQ_REG_TIMESTAMP 0 0x2374 1 0 4294967295 TIMESTAMP 0 7 mmSQ_CMD_TIMESTAMP 0 0x2375 1 0 4294967295 TIMESTAMP 0 7 mmSQ_HV_VMID_CTRL 0 0xf840 2 0 4294967295 DEFAULT_VMID 0 3 ALLOWED_VMID_MASK 4 19 ixSQ_WAVE_INST_DW0 2 0x1a 1 0 4294967295 INST_DW0 0 31 ixSQ_WAVE_INST_DW1 2 0x1b 1 0 4294967295 INST_DW1 0 31 ixSQ_WAVE_PC_LO 2 0x18 1 0 4294967295 PC_LO 0 31 ixSQ_WAVE_PC_HI 2 0x19 1 0 4294967295 PC_HI 0 7 ixSQ_WAVE_IB_DBG0 2 0x1c 13 0 4294967295 IBUF_ST 0 2 PC_INVALID 3 3 NEED_NEXT_DW 4 4 NO_PREFETCH_CNT 5 7 IBUF_RPTR 8 9 IBUF_WPTR 10 11 INST_STR_ST 16 18 MISC_CNT 19 21 ECC_ST 22 23 IS_HYB 24 24 HYB_CNT 25 26 KILL 27 27 NEED_KILL_IFETCH 28 28 ixSQ_WAVE_EXEC_LO 2 0x27e 1 0 4294967295 EXEC_LO 0 31 ixSQ_WAVE_EXEC_HI 2 0x27f 1 0 4294967295 EXEC_HI 0 31 ixSQ_WAVE_STATUS 2 0x12 24 0 4294967295 SCC 0 0 SPI_PRIO 1 2 WAVE_PRIO 3 4 PRIV 5 5 TRAP_EN 6 6 TTRACE_EN 7 7 EXPORT_RDY 8 8 EXECZ 9 9 VCCZ 10 10 IN_TG 11 11 IN_BARRIER 12 12 HALT 13 13 TRAP 14 14 TTRACE_CU_EN 15 15 VALID 16 16 ECC_ERR 17 17 SKIP_EXPORT 18 18 PERF_EN 19 19 COND_DBG_USER 20 20 COND_DBG_SYS 21 21 DATA_ATC 22 22 INST_ATC 23 23 DISPATCH_CACHE_CTRL 24 26 MUST_EXPORT 27 27 ixSQ_WAVE_MODE 2 0x11 9 0 4294967295 FP_ROUND 0 3 FP_DENORM 4 7 DX10_CLAMP 8 8 IEEE 9 9 LOD_CLAMPED 10 10 DEBUG_EN 11 11 EXCP_EN 12 20 VSKIP 28 28 CSP 29 31 ixSQ_WAVE_TRAPSTS 2 0x13 3 0 4294967295 EXCP 0 8 EXCP_CYCLE 16 21 DP_RATE 29 31 ixSQ_WAVE_HW_ID 2 0x14 11 0 4294967295 WAVE_ID 0 3 SIMD_ID 4 5 PIPE_ID 6 7 CU_ID 8 11 SH_ID 12 12 SE_ID 13 14 TG_ID 16 19 VM_ID 20 23 QUEUE_ID 24 26 STATE_ID 27 29 ME_ID 30 31 ixSQ_WAVE_GPR_ALLOC 2 0x15 4 0 4294967295 VGPR_BASE 0 5 VGPR_SIZE 8 13 SGPR_BASE 16 21 SGPR_SIZE 24 27 ixSQ_WAVE_LDS_ALLOC 2 0x16 2 0 4294967295 LDS_BASE 0 7 LDS_SIZE 12 20 ixSQ_WAVE_IB_STS 2 0x17 4 0 4294967295 VM_CNT 0 3 EXP_CNT 4 6 LGKM_CNT 8 11 VALU_CNT 12 14 ixSQ_WAVE_M0 2 0x27c 1 0 4294967295 M0 0 31 ixSQ_WAVE_TBA_LO 2 0x26c 1 0 4294967295 ADDR_LO 0 31 ixSQ_WAVE_TBA_HI 2 0x26d 1 0 4294967295 ADDR_HI 0 7 ixSQ_WAVE_TMA_LO 2 0x26e 1 0 4294967295 ADDR_LO 0 31 ixSQ_WAVE_TMA_HI 2 0x26f 1 0 4294967295 ADDR_HI 0 7 ixSQ_WAVE_TTMP0 2 0x270 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP1 2 0x271 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP2 2 0x272 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP3 2 0x273 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP4 2 0x274 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP5 2 0x275 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP6 2 0x276 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP7 2 0x277 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP8 2 0x278 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP9 2 0x279 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP10 2 0x27a 1 0 4294967295 DATA 0 31 ixSQ_WAVE_TTMP11 2 0x27b 1 0 4294967295 DATA 0 31 mmSQ_DEBUG_STS_GLOBAL 0 0x2309 4 0 4294967295 BUSY 0 0 INTERRUPT_MSG_BUSY 1 1 WAVE_LEVEL_SH0 4 15 WAVE_LEVEL_SH1 16 27 mmSQ_DEBUG_STS_GLOBAL2 0 0x2310 4 0 4294967295 FIFO_LEVEL_GFX0 0 7 FIFO_LEVEL_GFX1 8 15 FIFO_LEVEL_IMMED 16 23 FIFO_LEVEL_HOST 24 31 mmSQ_DEBUG_STS_GLOBAL3 0 0x2311 2 0 4294967295 FIFO_LEVEL_HOST_CMD 0 3 FIFO_LEVEL_HOST_REG 4 7 ixSQ_DEBUG_STS_LOCAL 2 0x8 2 0 4294967295 BUSY 0 0 WAVE_LEVEL 4 9 ixSQ_DEBUG_CTRL_LOCAL 2 0x9 1 0 4294967295 UNUSED 0 7 mmSH_MEM_BASES 0 0x230a 2 0 4294967295 PRIVATE_BASE 0 15 SHARED_BASE 16 31 mmSH_MEM_APE1_BASE 0 0x230b 1 0 4294967295 BASE 0 31 mmSH_MEM_APE1_LIMIT 0 0x230c 1 0 4294967295 LIMIT 0 31 mmSH_MEM_CONFIG 0 0x230d 5 0 4294967295 PTR32 0 0 PRIVATE_ATC 1 1 ALIGNMENT_MODE 2 3 DEFAULT_MTYPE 4 6 APE1_MTYPE 7 9 mmSQC_POLICY 0 0x230e 17 0 4294967295 DATA_L1_POLICY_0 0 0 DATA_L1_POLICY_1 1 1 DATA_L1_POLICY_2 2 2 DATA_L1_POLICY_3 3 3 DATA_L1_POLICY_4 4 4 DATA_L1_POLICY_5 5 5 DATA_L1_POLICY_6 6 6 DATA_L1_POLICY_7 7 7 DATA_L2_POLICY_0 8 9 DATA_L2_POLICY_1 10 11 DATA_L2_POLICY_2 12 13 DATA_L2_POLICY_3 14 15 DATA_L2_POLICY_4 16 17 DATA_L2_POLICY_5 18 19 DATA_L2_POLICY_6 20 21 DATA_L2_POLICY_7 22 23 INST_L2_POLICY 24 25 mmSQC_VOLATILE 0 0x230f 3 0 4294967295 DATA_L1 0 3 DATA_L2 4 7 INST_L2 8 8 mmSQ_THREAD_TRACE_WORD_CMN 0 0x23b0 2 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 mmSQ_THREAD_TRACE_WORD_INST 0 0x23b0 6 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 WAVE_ID 5 8 SIMD_ID 9 10 SIZE 11 11 INST_TYPE 12 15 mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0 0x23b0 5 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 WAVE_ID 5 8 SIMD_ID 9 10 PC_LO 16 31 mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0 0x23b1 1 0 4294967295 PC_HI 0 23 mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0 0x23b0 7 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 DATA_LO 16 31 mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0 0x23b1 1 0 4294967295 DATA_HI 0 15 mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0 0x23b0 2 0 4294967295 TOKEN_TYPE 0 3 TIME_LO 16 31 mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0 0x23b1 1 0 4294967295 TIME_HI 0 31 mmSQ_THREAD_TRACE_WORD_WAVE 0 0x23b0 6 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 mmSQ_THREAD_TRACE_WORD_MISC 0 0x23b0 4 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 11 SH_ID 12 12 MISC_TOKEN_TYPE 13 15 mmSQ_THREAD_TRACE_WORD_WAVE_START 0 0x23b0 10 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 WAVE_ID 10 13 SIMD_ID 14 15 DISPATCHER 16 20 VS_NO_ALLOC_OR_GROUPED 21 21 COUNT 22 28 TG_ID 29 31 mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0 0x23b0 9 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 PIPE_ID 5 6 ME_ID 7 8 REG_DROPPED_PREV 9 9 REG_TYPE 10 12 REG_PRIV 14 14 REG_OP 15 15 REG_ADDR 16 31 mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0 0x23b0 1 0 4294967295 DATA 0 31 mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0 0x23b0 6 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 PIPE_ID 5 6 ME_ID 7 8 REG_ADDR 9 15 DATA_LO 16 31 mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0 0x23b0 1 0 4294967295 DATA_HI 0 15 mmSQ_THREAD_TRACE_WORD_EVENT 0 0x23b0 5 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 STAGE 6 8 EVENT_TYPE 10 15 mmSQ_THREAD_TRACE_WORD_ISSUE 0 0x23b0 13 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SIMD_ID 5 6 INST0 8 9 INST1 10 11 INST2 12 13 INST3 14 15 INST4 16 17 INST5 18 19 INST6 20 21 INST7 22 23 INST8 24 25 INST9 26 27 mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0 0x23b0 7 0 4294967295 TOKEN_TYPE 0 3 TIME_DELTA 4 4 SH_ID 5 5 CU_ID 6 9 CNTR_BANK 10 11 CNTR0 12 24 CNTR1_LO 25 31 mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0 0x23b1 3 0 4294967295 CNTR1_HI 0 5 CNTR2 6 18 CNTR3 19 31 ixSQ_INTERRUPT_WORD_CMN 2 0x20c0 2 0 4294967295 SE_ID 24 25 ENCODING 26 27 ixSQ_INTERRUPT_WORD_AUTO 2 0x20c0 10 0 4294967295 THREAD_TRACE 0 0 WLT 1 1 THREAD_TRACE_BUF_FULL 2 2 REG_TIMESTAMP 3 3 CMD_TIMESTAMP 4 4 HOST_CMD_OVERFLOW 5 5 HOST_REG_OVERFLOW 6 6 IMMED_OVERFLOW 7 7 SE_ID 24 25 ENCODING 26 27 ixSQ_INTERRUPT_WORD_WAVE 2 0x20c0 9 0 4294967295 DATA 0 7 SH_ID 8 8 PRIV 9 9 VM_ID 10 13 WAVE_ID 14 17 SIMD_ID 18 19 CU_ID 20 23 SE_ID 24 25 ENCODING 26 27 mmSQ_SOP2 0 0x237f 5 0 4294967295 SSRC0 0 7 SSRC1 8 15 SDST 16 22 OP 23 29 ENCODING 30 31 mmSQ_VOP1 0 0x237f 4 0 4294967295 SRC0 0 8 OP 9 16 VDST 17 24 ENCODING 25 31 mmSQ_MTBUF_1 0 0x237f 6 0 4294967295 VADDR 0 7 VDATA 8 15 SRSRC 16 20 SLC 22 22 TFE 23 23 SOFFSET 24 31 mmSQ_EXP_1 0 0x237f 4 0 4294967295 VSRC0 0 7 VSRC1 8 15 VSRC2 16 23 VSRC3 24 31 mmSQ_MUBUF_1 0 0x237f 6 0 4294967295 VADDR 0 7 VDATA 8 15 SRSRC 16 20 SLC 22 22 TFE 23 23 SOFFSET 24 31 mmSQ_INST 0 0x237f 1 0 4294967295 ENCODING 0 31 mmSQ_EXP_0 0 0x237f 6 0 4294967295 EN 0 3 TGT 4 9 COMPR 10 10 DONE 11 11 VM 12 12 ENCODING 26 31 mmSQ_MUBUF_0 0 0x237f 8 0 4294967295 OFFSET 0 11 OFFEN 12 12 IDXEN 13 13 GLC 14 14 ADDR64 15 15 LDS 16 16 OP 18 24 ENCODING 26 31 mmSQ_VOP3_0 0 0x237f 5 0 4294967295 VDST 0 7 ABS 8 10 CLAMP 11 11 OP 17 25 ENCODING 26 31 mmSQ_VOP2 0 0x237f 5 0 4294967295 SRC0 0 8 VSRC1 9 16 VDST 17 24 OP 25 30 ENCODING 31 31 mmSQ_MTBUF_0 0 0x237f 9 0 4294967295 OFFSET 0 11 OFFEN 12 12 IDXEN 13 13 GLC 14 14 ADDR64 15 15 OP 16 18 DFMT 19 22 NFMT 23 25 ENCODING 26 31 mmSQ_SOPP 0 0x237f 3 0 4294967295 SIMM16 0 15 OP 16 22 ENCODING 23 31 mmSQ_FLAT_0 0 0x237f 4 0 4294967295 GLC 16 16 SLC 17 17 OP 18 24 ENCODING 26 31 mmSQ_VOP3_0_SDST_ENC 0 0x237f 4 0 4294967295 VDST 0 7 SDST 8 14 OP 17 25 ENCODING 26 31 mmSQ_MIMG_1 0 0x237f 4 0 4294967295 VADDR 0 7 VDATA 8 15 SRSRC 16 20 SSAMP 21 25 mmSQ_SMRD 0 0x237f 6 0 4294967295 OFFSET 0 7 IMM 8 8 SBASE 9 14 SDST 15 21 OP 22 26 ENCODING 27 31 mmSQ_SOP1 0 0x237f 4 0 4294967295 SSRC0 0 7 OP 8 15 SDST 16 22 ENCODING 23 31 mmSQ_SOPC 0 0x237f 4 0 4294967295 SSRC0 0 7 SSRC1 8 15 OP 16 22 ENCODING 23 31 mmSQ_FLAT_1 0 0x237f 4 0 4294967295 ADDR 0 7 DATA 8 15 TFE 23 23 VDST 24 31 mmSQ_DS_1 0 0x237f 4 0 4294967295 ADDR 0 7 DATA0 8 15 DATA1 16 23 VDST 24 31 mmSQ_VOP3_1 0 0x237f 5 0 4294967295 SRC0 0 8 SRC1 9 17 SRC2 18 26 OMOD 27 28 NEG 29 31 mmSQ_MIMG_0 0 0x237f 10 0 4294967295 DMASK 8 11 UNORM 12 12 GLC 13 13 DA 14 14 R128 15 15 TFE 16 16 LWE 17 17 OP 18 24 SLC 25 25 ENCODING 26 31 mmSQ_SOPK 0 0x237f 4 0 4294967295 SIMM16 0 15 SDST 16 22 OP 23 27 ENCODING 28 31 mmSQ_DS_0 0 0x237f 5 0 4294967295 OFFSET0 0 7 OFFSET1 8 15 GDS 17 17 OP 18 25 ENCODING 26 31 mmSQ_VOPC 0 0x237f 4 0 4294967295 SRC0 0 8 VSRC1 9 16 OP 17 24 ENCODING 25 31 mmSQ_VINTRP 0 0x237f 6 0 4294967295 VSRC 0 7 ATTRCHAN 8 9 ATTR 10 15 OP 16 17 VDST 18 25 ENCODING 26 31 mmCGTT_SX_CLK_CTRL0 0 0xf094 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_SX_CLK_CTRL1 0 0xf095 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_SX_CLK_CTRL2 0 0xf096 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_SX_CLK_CTRL3 0 0xf097 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_SX_CLK_CTRL4 0 0xf098 11 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmSX_DEBUG_BUSY 0 0x2414 32 0 4294967295 POS_FREE_OR_VALIDS 0 0 POS_REQUESTER_BUSY 1 1 PA_SX_BUSY 2 2 POS_SCBD_BUSY 3 3 POS_BANK3VAL3_BUSY 4 4 POS_BANK3VAL2_BUSY 5 5 POS_BANK3VAL1_BUSY 6 6 POS_BANK3VAL0_BUSY 7 7 POS_BANK2VAL3_BUSY 8 8 POS_BANK2VAL2_BUSY 9 9 POS_BANK2VAL1_BUSY 10 10 POS_BANK2VAL0_BUSY 11 11 POS_BANK1VAL3_BUSY 12 12 POS_BANK1VAL2_BUSY 13 13 POS_BANK1VAL1_BUSY 14 14 POS_BANK1VAL0_BUSY 15 15 POS_BANK0VAL3_BUSY 16 16 POS_BANK0VAL2_BUSY 17 17 POS_BANK0VAL1_BUSY 18 18 POS_BANK0VAL0_BUSY 19 19 POS_INMUX_VALID 20 20 WRCTRL1_VALIDQ3 21 21 WRCTRL1_VALIDQ2 22 22 WRCTRL1_VALIDQ1 23 23 WRCTRL0_VALIDQ3 24 24 WRCTRL0_VALIDQ2 25 25 WRCTRL0_VALIDQ1 26 26 PCCMD_VALID 27 27 VDATA1_VALID 28 28 VDATA0_VALID 29 29 CMD_BUSYORVAL 30 30 ADDR_BUSYORVAL 31 31 mmSX_DEBUG_BUSY_2 0 0x2415 32 0 4294967295 COL_SCBD_BUSY 0 0 COL_REQ3_FREECNT_NE0 1 1 COL_REQ3_IDLE 2 2 COL_REQ3_BUSY 3 3 COL_REQ2_FREECNT_NE0 4 4 COL_REQ2_IDLE 5 5 COL_REQ2_BUSY 6 6 COL_REQ1_FREECNT_NE0 7 7 COL_REQ1_IDLE 8 8 COL_REQ1_BUSY 9 9 COL_REQ0_FREECNT_NE0 10 10 COL_REQ0_IDLE 11 11 COL_REQ0_BUSY 12 12 COL_DBIF3_SENDFREE_BUSY 13 13 COL_DBIF3_FIFO_BUSY 14 14 COL_DBIF3_READ_VALID 15 15 COL_DBIF2_SENDFREE_BUSY 16 16 COL_DBIF2_FIFO_BUSY 17 17 COL_DBIF2_READ_VALID 18 18 COL_DBIF1_SENDFREE_BUSY 19 19 COL_DBIF1_FIFO_BUSY 20 20 COL_DBIF1_READ_VALID 21 21 COL_DBIF0_SENDFREE_BUSY 22 22 COL_DBIF0_FIFO_BUSY 23 23 COL_DBIF0_READ_VALID 24 24 COL_BUFF3_BANK3_VAL3_BUSY 25 25 COL_BUFF3_BANK3_VAL2_BUSY 26 26 COL_BUFF3_BANK3_VAL1_BUSY 27 27 COL_BUFF3_BANK3_VAL0_BUSY 28 28 COL_BUFF3_BANK2_VAL3_BUSY 29 29 COL_BUFF3_BANK2_VAL2_BUSY 30 30 COL_BUFF3_BANK2_VAL1_BUSY 31 31 mmSX_DEBUG_BUSY_3 0 0x2416 32 0 4294967295 COL_BUFF3_BANK2_VAL0_BUSY 0 0 COL_BUFF3_BANK1_VAL3_BUSY 1 1 COL_BUFF3_BANK1_VAL2_BUSY 2 2 COL_BUFF3_BANK1_VAL1_BUSY 3 3 COL_BUFF3_BANK1_VAL0_BUSY 4 4 COL_BUFF3_BANK0_VAL3_BUSY 5 5 COL_BUFF3_BANK0_VAL2_BUSY 6 6 COL_BUFF3_BANK0_VAL1_BUSY 7 7 COL_BUFF3_BANK0_VAL0_BUSY 8 8 COL_BUFF2_BANK3_VAL3_BUSY 9 9 COL_BUFF2_BANK3_VAL2_BUSY 10 10 COL_BUFF2_BANK3_VAL1_BUSY 11 11 COL_BUFF2_BANK3_VAL0_BUSY 12 12 COL_BUFF2_BANK2_VAL3_BUSY 13 13 COL_BUFF2_BANK2_VAL2_BUSY 14 14 COL_BUFF2_BANK2_VAL1_BUSY 15 15 COL_BUFF2_BANK2_VAL0_BUSY 16 16 COL_BUFF2_BANK1_VAL3_BUSY 17 17 COL_BUFF2_BANK1_VAL2_BUSY 18 18 COL_BUFF2_BANK1_VAL1_BUSY 19 19 COL_BUFF2_BANK1_VAL0_BUSY 20 20 COL_BUFF2_BANK0_VAL3_BUSY 21 21 COL_BUFF2_BANK0_VAL2_BUSY 22 22 COL_BUFF2_BANK0_VAL1_BUSY 23 23 COL_BUFF2_BANK0_VAL0_BUSY 24 24 COL_BUFF1_BANK3_VAL3_BUSY 25 25 COL_BUFF1_BANK3_VAL2_BUSY 26 26 COL_BUFF1_BANK3_VAL1_BUSY 27 27 COL_BUFF1_BANK3_VAL0_BUSY 28 28 COL_BUFF1_BANK2_VAL3_BUSY 29 29 COL_BUFF1_BANK2_VAL2_BUSY 30 30 COL_BUFF1_BANK2_VAL1_BUSY 31 31 mmSX_DEBUG_BUSY_4 0 0x2417 26 0 4294967295 COL_BUFF1_BANK2_VAL0_BUSY 0 0 COL_BUFF1_BANK1_VAL3_BUSY 1 1 COL_BUFF1_BANK1_VAL2_BUSY 2 2 COL_BUFF1_BANK1_VAL1_BUSY 3 3 COL_BUFF1_BANK1_VAL0_BUSY 4 4 COL_BUFF1_BANK0_VAL3_BUSY 5 5 COL_BUFF1_BANK0_VAL2_BUSY 6 6 COL_BUFF1_BANK0_VAL1_BUSY 7 7 COL_BUFF1_BANK0_VAL0_BUSY 8 8 COL_BUFF0_BANK3_VAL3_BUSY 9 9 COL_BUFF0_BANK3_VAL2_BUSY 10 10 COL_BUFF0_BANK3_VAL1_BUSY 11 11 COL_BUFF0_BANK3_VAL0_BUSY 12 12 COL_BUFF0_BANK2_VAL3_BUSY 13 13 COL_BUFF0_BANK2_VAL2_BUSY 14 14 COL_BUFF0_BANK2_VAL1_BUSY 15 15 COL_BUFF0_BANK2_VAL0_BUSY 16 16 COL_BUFF0_BANK1_VAL3_BUSY 17 17 COL_BUFF0_BANK1_VAL2_BUSY 18 18 COL_BUFF0_BANK1_VAL1_BUSY 19 19 COL_BUFF0_BANK1_VAL0_BUSY 20 20 COL_BUFF0_BANK0_VAL3_BUSY 21 21 COL_BUFF0_BANK0_VAL2_BUSY 22 22 COL_BUFF0_BANK0_VAL1_BUSY 23 23 COL_BUFF0_BANK0_VAL0_BUSY 24 24 RESERVED 25 31 mmSX_DEBUG_1 0 0x2418 2 0 4294967295 SX_DB_QUAD_CREDIT 0 6 DEBUG_DATA 7 31 mmSX_PERFCOUNTER0_SELECT 0 0xda40 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmSX_PERFCOUNTER1_SELECT 0 0xda41 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmSX_PERFCOUNTER2_SELECT 0 0xda42 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmSX_PERFCOUNTER3_SELECT 0 0xda43 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmSX_PERFCOUNTER0_SELECT1 0 0xda44 2 0 4294967295 PERFCOUNTER_SELECT2 0 9 PERFCOUNTER_SELECT3 10 19 mmSX_PERFCOUNTER1_SELECT1 0 0xda45 2 0 4294967295 PERFCOUNTER_SELECT2 0 9 PERFCOUNTER_SELECT3 10 19 mmSX_PERFCOUNTER0_LO 0 0xd240 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER0_HI 0 0xd241 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER1_LO 0 0xd242 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER1_HI 0 0xd243 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER2_LO 0 0xd244 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER2_HI 0 0xd245 1 0 4294967295 PERFCOUNTER_HI 0 31 mmSX_PERFCOUNTER3_LO 0 0xd246 1 0 4294967295 PERFCOUNTER_LO 0 31 mmSX_PERFCOUNTER3_HI 0 0xd247 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCC_CTRL 0 0x2b80 6 0 4294967295 CACHE_SIZE 0 1 RATE 2 3 WRITEBACK_MARGIN 4 7 SRC_FIFO_SIZE 12 15 LATENCY_FIFO_SIZE 16 19 WB_OR_INV_ALL_VMIDS 20 20 mmTCC_EDC_COUNTER 0 0x2b82 2 0 4294967295 SEC_COUNT 0 3 DED_COUNT 16 19 mmTCC_REDUNDANCY 0 0x2b83 2 0 4294967295 MC_SEL0 0 0 MC_SEL1 1 1 mmTCC_CGTT_SCLK_CTRL 0 0xf0ac 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmTCA_CGTT_SCLK_CTRL 0 0xf0ad 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmTCS_CGTT_SCLK_CTRL 0 0xf0ae 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmTCC_PERFCOUNTER0_SELECT 0 0xdb80 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCC_PERFCOUNTER1_SELECT 0 0xdb82 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCC_PERFCOUNTER0_SELECT1 0 0xdb81 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmTCC_PERFCOUNTER1_SELECT1 0 0xdb83 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmTCC_PERFCOUNTER2_SELECT 0 0xdb84 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCC_PERFCOUNTER3_SELECT 0 0xdb85 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCC_PERFCOUNTER0_LO 0 0xd380 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCC_PERFCOUNTER1_LO 0 0xd382 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCC_PERFCOUNTER2_LO 0 0xd384 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCC_PERFCOUNTER3_LO 0 0xd386 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCC_PERFCOUNTER0_HI 0 0xd381 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCC_PERFCOUNTER1_HI 0 0xd383 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCC_PERFCOUNTER2_HI 0 0xd385 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCC_PERFCOUNTER3_HI 0 0xd387 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCA_CTRL 0 0x2bc0 1 0 4294967295 HOLE_TIMEOUT 0 3 mmTCA_PERFCOUNTER0_SELECT 0 0xdb90 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCA_PERFCOUNTER1_SELECT 0 0xdb92 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCA_PERFCOUNTER0_SELECT1 0 0xdb91 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmTCA_PERFCOUNTER1_SELECT1 0 0xdb93 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmTCA_PERFCOUNTER2_SELECT 0 0xdb94 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCA_PERFCOUNTER3_SELECT 0 0xdb95 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCA_PERFCOUNTER0_LO 0 0xd390 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCA_PERFCOUNTER1_LO 0 0xd392 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCA_PERFCOUNTER2_LO 0 0xd394 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCA_PERFCOUNTER3_LO 0 0xd396 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCA_PERFCOUNTER0_HI 0 0xd391 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCA_PERFCOUNTER1_HI 0 0xd393 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCA_PERFCOUNTER2_HI 0 0xd395 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCA_PERFCOUNTER3_HI 0 0xd397 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCS_CTRL 0 0x2be0 1 0 4294967295 RATE 0 1 mmTCS_PERFCOUNTER0_SELECT 0 0xdba0 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCS_PERFCOUNTER0_SELECT1 0 0xdba1 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE2 24 27 PERF_MODE3 28 31 mmTCS_PERFCOUNTER1_SELECT 0 0xdba2 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCS_PERFCOUNTER2_SELECT 0 0xdba3 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCS_PERFCOUNTER3_SELECT 0 0xdba4 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCS_PERFCOUNTER0_LO 0 0xd3a0 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCS_PERFCOUNTER1_LO 0 0xd3a2 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCS_PERFCOUNTER2_LO 0 0xd3a4 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCS_PERFCOUNTER3_LO 0 0xd3a6 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCS_PERFCOUNTER0_HI 0 0xd3a1 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCS_PERFCOUNTER1_HI 0 0xd3a3 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCS_PERFCOUNTER2_HI 0 0xd3a5 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCS_PERFCOUNTER3_HI 0 0xd3a7 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTA_BC_BASE_ADDR 0 0xa020 1 0 4294967295 ADDRESS 0 31 mmTA_BC_BASE_ADDR_HI 0 0xa021 1 0 4294967295 ADDRESS 0 7 mmTD_CNTL 0 0x2525 10 0 4294967295 SYNC_PHASE_SH 0 1 SYNC_PHASE_VC_SMX 4 5 PAD_STALL_EN 8 8 EXTEND_LDS_STALL 9 10 LDS_STALL_PHASE_ADJUST 11 12 PRECISION_COMPATIBILITY 15 15 GATHER4_FLOAT_MODE 16 16 LD_FLOAT_MODE 18 18 GATHER4_DX9_MODE 19 19 DISABLE_POWER_THROTTLE 20 20 mmTD_STATUS 0 0x2526 1 0 4294967295 BUSY 31 31 mmTD_DEBUG_INDEX 0 0x2528 1 0 4294967295 INDEX 0 4 mmTD_DEBUG_DATA 0 0x2529 1 0 4294967295 DATA 0 31 mmTD_PERFCOUNTER0_SELECT 0 0xdb00 5 0 4294967295 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTD_PERFCOUNTER1_SELECT 0 0xdb02 5 0 4294967295 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTD_PERFCOUNTER0_SELECT1 0 0xdb01 4 0 4294967295 PERF_SEL2 0 7 PERF_SEL3 10 17 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTD_PERFCOUNTER0_LO 0 0xd300 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTD_PERFCOUNTER1_LO 0 0xd302 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTD_PERFCOUNTER0_HI 0 0xd301 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTD_PERFCOUNTER1_HI 0 0xd303 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTD_SCRATCH 0 0x2533 1 0 4294967295 SCRATCH 0 31 mmTA_CNTL 0 0x2541 3 0 4294967295 TC_DATA_CREDIT 13 15 ALIGNER_CREDIT 16 20 TD_FIFO_CREDIT 22 31 mmTA_CNTL_AUX 0 0x2542 3 0 4294967295 SCOAL_DSWIZZLE_N 0 0 RESERVED 1 3 ANISO_WEIGHT_MODE 16 16 mmTA_RESERVED_010C 0 0x2543 1 0 4294967295 Unused 0 31 mmTA_CS_BC_BASE_ADDR 0 0xc380 1 0 4294967295 ADDRESS 0 31 mmTA_CS_BC_BASE_ADDR_HI 0 0xc381 1 0 4294967295 ADDRESS 0 7 mmTA_STATUS 0 0x2548 17 0 4294967295 FG_PFIFO_EMPTYB 12 12 FG_LFIFO_EMPTYB 13 13 FG_SFIFO_EMPTYB 14 14 FL_PFIFO_EMPTYB 16 16 FL_LFIFO_EMPTYB 17 17 FL_SFIFO_EMPTYB 18 18 FA_PFIFO_EMPTYB 20 20 FA_LFIFO_EMPTYB 21 21 FA_SFIFO_EMPTYB 22 22 IN_BUSY 24 24 FG_BUSY 25 25 LA_BUSY 26 26 FL_BUSY 27 27 TA_BUSY 28 28 FA_BUSY 29 29 AL_BUSY 30 30 BUSY 31 31 mmTA_DEBUG_INDEX 0 0x254c 1 0 4294967295 INDEX 0 4 mmTA_DEBUG_DATA 0 0x254d 1 0 4294967295 DATA 0 31 mmTA_PERFCOUNTER0_SELECT 0 0xdac0 5 0 4294967295 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTA_PERFCOUNTER1_SELECT 0 0xdac2 5 0 4294967295 PERF_SEL 0 7 PERF_SEL1 10 17 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTA_PERFCOUNTER0_SELECT1 0 0xdac1 4 0 4294967295 PERF_SEL2 0 7 PERF_SEL3 10 17 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTA_PERFCOUNTER0_LO 0 0xd2c0 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTA_PERFCOUNTER1_LO 0 0xd2c2 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTA_PERFCOUNTER0_HI 0 0xd2c1 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTA_PERFCOUNTER1_HI 0 0xd2c3 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTA_SCRATCH 0 0x2564 1 0 4294967295 SCRATCH 0 31 mmSH_HIDDEN_PRIVATE_BASE_VMID 0 0x2580 1 0 4294967295 ADDRESS 0 31 mmSH_STATIC_MEM_CONFIG 0 0x2581 5 0 4294967295 SWIZZLE_ENABLE 0 0 ELEMENT_SIZE 1 2 INDEX_STRIDE 3 4 PRIVATE_MTYPE 5 7 READ_ONLY_CNTL 8 15 mmTCP_INVALIDATE 0 0x2b00 1 0 4294967295 START 0 0 mmTCP_STATUS 0 0x2b01 1 0 4294967295 TCP_BUSY 0 0 mmTCP_CNTL 0 0x2b02 9 0 4294967295 FORCE_HIT 0 0 FORCE_MISS 1 1 L1_SIZE 2 3 FLAT_BUF_HASH_ENABLE 4 4 FLAT_BUF_CACHE_SWIZZLE 5 5 FORCE_EOW_TOTAL_CNT 15 20 FORCE_EOW_TAGRAM_CNT 22 27 DISABLE_Z_MAP 28 28 INV_ALL_VMIDS 29 29 mmTCP_CHAN_STEER_LO 0 0x2b03 8 0 4294967295 CHAN0 0 3 CHAN1 4 7 CHAN2 8 11 CHAN3 12 15 CHAN4 16 19 CHAN5 20 23 CHAN6 24 27 CHAN7 28 31 mmTCP_CHAN_STEER_HI 0 0x2b04 8 0 4294967295 CHAN8 0 3 CHAN9 4 7 CHANA 8 11 CHANB 12 15 CHANC 16 19 CHAND 20 23 CHANE 24 27 CHANF 28 31 mmTCP_ADDR_CONFIG 0 0x2b05 4 0 4294967295 NUM_TCC_BANKS 0 3 NUM_BANKS 4 5 COLHI_WIDTH 6 8 RB_SPLIT_COLHI 9 9 mmTCP_CREDIT 0 0x2b06 3 0 4294967295 LFIFO_CREDIT 0 9 REQ_FIFO_CREDIT 16 22 TD_CREDIT 29 31 mmTCP_PERFCOUNTER0_SELECT 0 0xdb40 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCP_PERFCOUNTER1_SELECT 0 0xdb42 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmTCP_PERFCOUNTER0_SELECT1 0 0xdb41 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTCP_PERFCOUNTER1_SELECT1 0 0xdb43 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmTCP_PERFCOUNTER2_SELECT 0 0xdb44 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCP_PERFCOUNTER3_SELECT 0 0xdb45 3 0 4294967295 PERF_SEL 0 9 CNTR_MODE 20 23 PERF_MODE 28 31 mmTCP_PERFCOUNTER0_LO 0 0xd340 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER1_LO 0 0xd342 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER2_LO 0 0xd344 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER3_LO 0 0xd346 1 0 4294967295 PERFCOUNTER_LO 0 31 mmTCP_PERFCOUNTER0_HI 0 0xd341 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER1_HI 0 0xd343 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER2_HI 0 0xd345 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCP_PERFCOUNTER3_HI 0 0xd347 1 0 4294967295 PERFCOUNTER_HI 0 31 mmTCP_BUFFER_ADDR_HASH_CNTL 0 0x2b16 4 0 4294967295 CHANNEL_BITS 0 2 BANK_BITS 8 10 CHANNEL_XOR_COUNT 16 18 BANK_XOR_COUNT 24 26 mmTCP_EDC_COUNTER 0 0x2b17 2 0 4294967295 SEC_COUNT 0 3 DED_COUNT 16 19 mmTC_CFG_L1_LOAD_POLICY0 0 0x2b1a 16 0 4294967295 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 mmTC_CFG_L1_LOAD_POLICY1 0 0x2b1b 16 0 4294967295 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 mmTC_CFG_L1_STORE_POLICY 0 0x2b1c 32 0 4294967295 POLICY_0 0 0 POLICY_1 1 1 POLICY_2 2 2 POLICY_3 3 3 POLICY_4 4 4 POLICY_5 5 5 POLICY_6 6 6 POLICY_7 7 7 POLICY_8 8 8 POLICY_9 9 9 POLICY_10 10 10 POLICY_11 11 11 POLICY_12 12 12 POLICY_13 13 13 POLICY_14 14 14 POLICY_15 15 15 POLICY_16 16 16 POLICY_17 17 17 POLICY_18 18 18 POLICY_19 19 19 POLICY_20 20 20 POLICY_21 21 21 POLICY_22 22 22 POLICY_23 23 23 POLICY_24 24 24 POLICY_25 25 25 POLICY_26 26 26 POLICY_27 27 27 POLICY_28 28 28 POLICY_29 29 29 POLICY_30 30 30 POLICY_31 31 31 mmTC_CFG_L2_LOAD_POLICY0 0 0x2b1d 16 0 4294967295 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 mmTC_CFG_L2_LOAD_POLICY1 0 0x2b1e 16 0 4294967295 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 mmTC_CFG_L2_STORE_POLICY0 0 0x2b1f 16 0 4294967295 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 mmTC_CFG_L2_STORE_POLICY1 0 0x2b20 16 0 4294967295 POLICY_16 0 1 POLICY_17 2 3 POLICY_18 4 5 POLICY_19 6 7 POLICY_20 8 9 POLICY_21 10 11 POLICY_22 12 13 POLICY_23 14 15 POLICY_24 16 17 POLICY_25 18 19 POLICY_26 20 21 POLICY_27 22 23 POLICY_28 24 25 POLICY_29 26 27 POLICY_30 28 29 POLICY_31 30 31 mmTC_CFG_L2_ATOMIC_POLICY 0 0x2b21 16 0 4294967295 POLICY_0 0 1 POLICY_1 2 3 POLICY_2 4 5 POLICY_3 6 7 POLICY_4 8 9 POLICY_5 10 11 POLICY_6 12 13 POLICY_7 14 15 POLICY_8 16 17 POLICY_9 18 19 POLICY_10 20 21 POLICY_11 22 23 POLICY_12 24 25 POLICY_13 26 27 POLICY_14 28 29 POLICY_15 30 31 mmTC_CFG_L1_VOLATILE 0 0x2b22 1 0 4294967295 VOL 0 3 mmTC_CFG_L2_VOLATILE 0 0x2b23 1 0 4294967295 VOL 0 3 mmTCP_WATCH0_ADDR_H 0 0x32a0 1 0 4294967295 ADDR 0 15 mmTCP_WATCH1_ADDR_H 0 0x32a3 1 0 4294967295 ADDR 0 15 mmTCP_WATCH2_ADDR_H 0 0x32a6 1 0 4294967295 ADDR 0 15 mmTCP_WATCH3_ADDR_H 0 0x32a9 1 0 4294967295 ADDR 0 15 mmTCP_WATCH0_ADDR_L 0 0x32a1 1 0 4294967295 ADDR 6 31 mmTCP_WATCH1_ADDR_L 0 0x32a4 1 0 4294967295 ADDR 6 31 mmTCP_WATCH2_ADDR_L 0 0x32a7 1 0 4294967295 ADDR 6 31 mmTCP_WATCH3_ADDR_L 0 0x32aa 1 0 4294967295 ADDR 6 31 mmTCP_WATCH0_CNTL 0 0x32a2 4 0 4294967295 MASK 0 23 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH1_CNTL 0 0x32a5 4 0 4294967295 MASK 0 23 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH2_CNTL 0 0x32a8 4 0 4294967295 MASK 0 23 VMID 24 27 MODE 29 30 VALID 31 31 mmTCP_WATCH3_CNTL 0 0x32ab 4 0 4294967295 MASK 0 23 VMID 24 27 MODE 29 30 VALID 31 31 mmTD_CGTT_CTRL 0 0xf09c 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmTA_CGTT_CTRL 0 0xf09d 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_TCP_CLK_CTRL 0 0xf09e 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmCGTT_TCI_CLK_CTRL 0 0xf09f 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmTCI_STATUS 0 0x2b61 1 0 4294967295 TCI_BUSY 0 0 mmTCI_CNTL_1 0 0x2b62 3 0 4294967295 WBINVL1_NUM_CYCLES 0 15 REQ_FIFO_DEPTH 16 23 WDATA_RAM_DEPTH 24 31 mmTCI_CNTL_2 0 0x2b63 2 0 4294967295 L1_INVAL_ON_WBINVL2 0 0 TCA_MAX_CREDIT 1 8 mmGDS_CONFIG 0 0x25c0 4 0 4294967295 SH0_GPR_PHASE_SEL 1 2 SH1_GPR_PHASE_SEL 3 4 SH2_GPR_PHASE_SEL 5 6 SH3_GPR_PHASE_SEL 7 8 mmGDS_CNTL_STATUS 0 0x25c1 7 0 4294967295 GDS_BUSY 0 0 GRBM_WBUF_BUSY 1 1 ORD_APP_BUSY 2 2 DS_BANK_CONFLICT 3 3 DS_ADDR_CONFLICT 4 4 DS_WR_CLAMP 5 5 DS_RD_CLAMP 6 6 mmGDS_ENHANCE 0 0x25c2 4 0 4294967295 MISC 0 15 AUTO_INC_INDEX 16 16 CGPG_RESTORE 17 17 UNUSED 18 31 mmGDS_PROTECTION_FAULT 0 0x25c3 8 0 4294967295 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GRBM 2 2 SH_ID 3 5 CU_ID 6 9 SIMD_ID 10 11 WAVE_ID 12 15 ADDRESS 16 31 mmGDS_VM_PROTECTION_FAULT 0 0x25c4 7 0 4294967295 WRITE_DIS 0 0 FAULT_DETECTED 1 1 GWS 2 2 OA 3 3 GRBM 4 4 VMID 8 11 ADDRESS 16 31 mmGDS_SECDED_CNT 0 0x25c5 2 0 4294967295 DED 0 15 SEC 16 31 mmGDS_GRBM_SECDED_CNT 0 0x25c6 2 0 4294967295 DED 0 15 SEC 16 31 mmGDS_OA_DED 0 0x25c7 13 0 4294967295 ME0_GFXHP3D_PIX_DED 0 0 ME0_GFXHP3D_VTX_DED 1 1 ME0_CS_DED 2 2 UNUSED0 3 3 ME1_PIPE0_DED 4 4 ME1_PIPE1_DED 5 5 ME1_PIPE2_DED 6 6 ME1_PIPE3_DED 7 7 ME2_PIPE0_DED 8 8 ME2_PIPE1_DED 9 9 ME2_PIPE2_DED 10 10 ME2_PIPE3_DED 11 11 UNUSED1 12 31 mmGDS_DEBUG_CNTL 0 0x25c8 2 0 4294967295 GDS_DEBUG_INDX 0 4 UNUSED 5 31 mmGDS_DEBUG_DATA 0 0x25c9 1 0 4294967295 DATA 0 31 mmCGTT_GDS_CLK_CTRL 0 0xf0a0 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmGDS_RD_ADDR 0 0xc400 1 0 4294967295 READ_ADDR 0 31 mmGDS_RD_DATA 0 0xc401 1 0 4294967295 READ_DATA 0 31 mmGDS_RD_BURST_ADDR 0 0xc402 1 0 4294967295 BURST_ADDR 0 31 mmGDS_RD_BURST_COUNT 0 0xc403 1 0 4294967295 BURST_COUNT 0 31 mmGDS_RD_BURST_DATA 0 0xc404 1 0 4294967295 BURST_DATA 0 31 mmGDS_WR_ADDR 0 0xc405 1 0 4294967295 WRITE_ADDR 0 31 mmGDS_WR_DATA 0 0xc406 1 0 4294967295 WRITE_DATA 0 31 mmGDS_WR_BURST_ADDR 0 0xc407 1 0 4294967295 WRITE_ADDR 0 31 mmGDS_WR_BURST_DATA 0 0xc408 1 0 4294967295 WRITE_DATA 0 31 mmGDS_WRITE_COMPLETE 0 0xc409 1 0 4294967295 WRITE_COMPLETE 0 31 mmGDS_ATOM_CNTL 0 0xc40a 4 0 4294967295 AINC 0 5 UNUSED1 6 7 DMODE 8 8 UNUSED2 9 31 mmGDS_ATOM_COMPLETE 0 0xc40b 2 0 4294967295 COMPLETE 0 0 UNUSED 1 31 mmGDS_ATOM_BASE 0 0xc40c 2 0 4294967295 BASE 0 15 UNUSED 16 31 mmGDS_ATOM_SIZE 0 0xc40d 2 0 4294967295 SIZE 0 15 UNUSED 16 31 mmGDS_ATOM_OFFSET0 0 0xc40e 2 0 4294967295 OFFSET0 0 7 UNUSED 8 31 mmGDS_ATOM_OFFSET1 0 0xc40f 2 0 4294967295 OFFSET1 0 7 UNUSED 8 31 mmGDS_ATOM_DST 0 0xc410 1 0 4294967295 DST 0 31 mmGDS_ATOM_OP 0 0xc411 2 0 4294967295 OP 0 7 UNUSED 8 31 mmGDS_ATOM_SRC0 0 0xc412 1 0 4294967295 DATA 0 31 mmGDS_ATOM_SRC0_U 0 0xc413 1 0 4294967295 DATA 0 31 mmGDS_ATOM_SRC1 0 0xc414 1 0 4294967295 DATA 0 31 mmGDS_ATOM_SRC1_U 0 0xc415 1 0 4294967295 DATA 0 31 mmGDS_ATOM_READ0 0 0xc416 1 0 4294967295 DATA 0 31 mmGDS_ATOM_READ0_U 0 0xc417 1 0 4294967295 DATA 0 31 mmGDS_ATOM_READ1 0 0xc418 1 0 4294967295 DATA 0 31 mmGDS_ATOM_READ1_U 0 0xc419 1 0 4294967295 DATA 0 31 mmGDS_GWS_RESOURCE_CNTL 0 0xc41a 2 0 4294967295 INDEX 0 5 UNUSED 6 31 mmGDS_GWS_RESOURCE 0 0xc41b 9 0 4294967295 FLAG 0 0 COUNTER 1 12 TYPE 13 13 DED 14 14 RELEASE_ALL 15 15 HEAD_QUEUE 16 26 HEAD_VALID 27 27 HEAD_FLAG 28 28 UNUSED1 29 31 mmGDS_GWS_RESOURCE_CNT 0 0xc41c 2 0 4294967295 RESOURCE_CNT 0 15 UNUSED 16 31 mmGDS_OA_CNTL 0 0xc41d 2 0 4294967295 INDEX 0 3 UNUSED 4 31 mmGDS_OA_COUNTER 0 0xc41e 1 0 4294967295 SPACE_AVAILABLE 0 31 mmGDS_OA_ADDRESS 0 0xc41f 6 0 4294967295 DS_ADDRESS 0 15 CRAWLER_TYPE 16 19 CRAWLER 20 23 UNUSED 24 29 NO_ALLOC 30 30 ENABLE 31 31 mmGDS_OA_INCDEC 0 0xc420 2 0 4294967295 VALUE 0 30 INCDEC 31 31 ixGDS_DEBUG_REG0 2 0x0 11 0 4294967295 spare1 0 5 write_buff_valid 6 6 wr_pixel_nxt_ptr 7 11 last_pixel_ptr 12 12 cstate 13 16 buff_write 17 17 flush_request 18 18 wr_buffer_wr_complete 19 19 wbuf_fifo_empty 20 20 wbuf_fifo_full 21 21 spare 22 31 ixGDS_DEBUG_REG1 2 0x1 11 0 4294967295 tag_hit 0 0 tag_miss 1 1 pixel_addr 2 16 pixel_vld 17 17 data_ready 18 18 awaiting_data 19 19 addr_fifo_full 20 20 addr_fifo_empty 21 21 buffer_loaded 22 22 buffer_invalid 23 23 spare 24 31 ixGDS_DEBUG_REG2 2 0x2 7 0 4294967295 ds_full 0 0 ds_credit_avail 1 1 ord_idx_free 2 2 cmd_write 3 3 app_sel 4 7 req 8 22 spare 23 31 ixGDS_DEBUG_REG3 2 0x3 3 0 4294967295 pipe_num_busy 0 10 pipe0_busy_num 11 14 spare 15 31 ixGDS_DEBUG_REG4 2 0x4 20 0 4294967295 gws_busy 0 0 gws_req 1 1 gws_out_stall 2 2 cur_reso 3 8 cur_reso_head_valid 9 9 cur_reso_head_dirty 10 10 cur_reso_head_flag 11 11 cur_reso_fed 12 12 cur_reso_barrier 13 13 cur_reso_flag 14 14 cur_reso_cnt_gt0 15 15 credit_cnt_gt0 16 16 cmd_write 17 17 grbm_gws_reso_wr 18 18 grbm_gws_reso_rd 19 19 ram_read_busy 20 20 gws_bulkfree 21 21 ram_gws_re 22 22 ram_gws_we 23 23 spare 24 31 ixGDS_DEBUG_REG5 2 0x5 8 0 4294967295 write_dis 0 0 dec_error 1 1 alloc_opco_error 2 2 dealloc_opco_error 3 3 wrap_opco_error 4 4 spare 5 7 error_ds_address 8 21 spare1 22 31 ixGDS_DEBUG_REG6 2 0x6 4 0 4294967295 oa_busy 0 0 counters_enabled 1 4 counters_busy 5 20 spare 21 31 mmGDS_PERFCOUNTER0_SELECT 0 0xda80 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmGDS_PERFCOUNTER1_SELECT 0 0xda81 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmGDS_PERFCOUNTER2_SELECT 0 0xda82 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmGDS_PERFCOUNTER3_SELECT 0 0xda83 3 0 4294967295 PERFCOUNTER_SELECT 0 9 PERFCOUNTER_SELECT1 10 19 CNTR_MODE 20 23 mmGDS_PERFCOUNTER0_LO 0 0xd280 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER1_LO 0 0xd282 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER2_LO 0 0xd284 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER3_LO 0 0xd286 1 0 4294967295 PERFCOUNTER_LO 0 31 mmGDS_PERFCOUNTER0_HI 0 0xd281 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER1_HI 0 0xd283 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER2_HI 0 0xd285 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER3_HI 0 0xd287 1 0 4294967295 PERFCOUNTER_HI 0 31 mmGDS_PERFCOUNTER0_SELECT1 0 0xda84 2 0 4294967295 PERFCOUNTER_SELECT2 0 9 PERFCOUNTER_SELECT3 10 19 mmGDS_VMID0_BASE 0 0x3300 1 0 4294967295 BASE 0 15 mmGDS_VMID1_BASE 0 0x3302 1 0 4294967295 BASE 0 15 mmGDS_VMID2_BASE 0 0x3304 1 0 4294967295 BASE 0 15 mmGDS_VMID3_BASE 0 0x3306 1 0 4294967295 BASE 0 15 mmGDS_VMID4_BASE 0 0x3308 1 0 4294967295 BASE 0 15 mmGDS_VMID5_BASE 0 0x330a 1 0 4294967295 BASE 0 15 mmGDS_VMID6_BASE 0 0x330c 1 0 4294967295 BASE 0 15 mmGDS_VMID7_BASE 0 0x330e 1 0 4294967295 BASE 0 15 mmGDS_VMID8_BASE 0 0x3310 1 0 4294967295 BASE 0 15 mmGDS_VMID9_BASE 0 0x3312 1 0 4294967295 BASE 0 15 mmGDS_VMID10_BASE 0 0x3314 1 0 4294967295 BASE 0 15 mmGDS_VMID11_BASE 0 0x3316 1 0 4294967295 BASE 0 15 mmGDS_VMID12_BASE 0 0x3318 1 0 4294967295 BASE 0 15 mmGDS_VMID13_BASE 0 0x331a 1 0 4294967295 BASE 0 15 mmGDS_VMID14_BASE 0 0x331c 1 0 4294967295 BASE 0 15 mmGDS_VMID15_BASE 0 0x331e 1 0 4294967295 BASE 0 15 mmGDS_VMID0_SIZE 0 0x3301 1 0 4294967295 SIZE 0 16 mmGDS_VMID1_SIZE 0 0x3303 1 0 4294967295 SIZE 0 16 mmGDS_VMID2_SIZE 0 0x3305 1 0 4294967295 SIZE 0 16 mmGDS_VMID3_SIZE 0 0x3307 1 0 4294967295 SIZE 0 16 mmGDS_VMID4_SIZE 0 0x3309 1 0 4294967295 SIZE 0 16 mmGDS_VMID5_SIZE 0 0x330b 1 0 4294967295 SIZE 0 16 mmGDS_VMID6_SIZE 0 0x330d 1 0 4294967295 SIZE 0 16 mmGDS_VMID7_SIZE 0 0x330f 1 0 4294967295 SIZE 0 16 mmGDS_VMID8_SIZE 0 0x3311 1 0 4294967295 SIZE 0 16 mmGDS_VMID9_SIZE 0 0x3313 1 0 4294967295 SIZE 0 16 mmGDS_VMID10_SIZE 0 0x3315 1 0 4294967295 SIZE 0 16 mmGDS_VMID11_SIZE 0 0x3317 1 0 4294967295 SIZE 0 16 mmGDS_VMID12_SIZE 0 0x3319 1 0 4294967295 SIZE 0 16 mmGDS_VMID13_SIZE 0 0x331b 1 0 4294967295 SIZE 0 16 mmGDS_VMID14_SIZE 0 0x331d 1 0 4294967295 SIZE 0 16 mmGDS_VMID15_SIZE 0 0x331f 1 0 4294967295 SIZE 0 16 mmGDS_GWS_VMID0 0 0x3320 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID1 0 0x3321 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID2 0 0x3322 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID3 0 0x3323 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID4 0 0x3324 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID5 0 0x3325 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID6 0 0x3326 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID7 0 0x3327 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID8 0 0x3328 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID9 0 0x3329 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID10 0 0x332a 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID11 0 0x332b 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID12 0 0x332c 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID13 0 0x332d 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID14 0 0x332e 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_GWS_VMID15 0 0x332f 2 0 4294967295 BASE 0 5 SIZE 16 22 mmGDS_OA_VMID0 0 0x3330 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID1 0 0x3331 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID2 0 0x3332 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID3 0 0x3333 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID4 0 0x3334 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID5 0 0x3335 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID6 0 0x3336 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID7 0 0x3337 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID8 0 0x3338 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID9 0 0x3339 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID10 0 0x333a 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID11 0 0x333b 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID12 0 0x333c 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID13 0 0x333d 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID14 0 0x333e 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_OA_VMID15 0 0x333f 2 0 4294967295 MASK 0 15 UNUSED 16 31 mmGDS_GWS_RESET0 0 0x3344 32 0 4294967295 RESOURCE0_RESET 0 0 RESOURCE1_RESET 1 1 RESOURCE2_RESET 2 2 RESOURCE3_RESET 3 3 RESOURCE4_RESET 4 4 RESOURCE5_RESET 5 5 RESOURCE6_RESET 6 6 RESOURCE7_RESET 7 7 RESOURCE8_RESET 8 8 RESOURCE9_RESET 9 9 RESOURCE10_RESET 10 10 RESOURCE11_RESET 11 11 RESOURCE12_RESET 12 12 RESOURCE13_RESET 13 13 RESOURCE14_RESET 14 14 RESOURCE15_RESET 15 15 RESOURCE16_RESET 16 16 RESOURCE17_RESET 17 17 RESOURCE18_RESET 18 18 RESOURCE19_RESET 19 19 RESOURCE20_RESET 20 20 RESOURCE21_RESET 21 21 RESOURCE22_RESET 22 22 RESOURCE23_RESET 23 23 RESOURCE24_RESET 24 24 RESOURCE25_RESET 25 25 RESOURCE26_RESET 26 26 RESOURCE27_RESET 27 27 RESOURCE28_RESET 28 28 RESOURCE29_RESET 29 29 RESOURCE30_RESET 30 30 RESOURCE31_RESET 31 31 mmGDS_GWS_RESET1 0 0x3345 32 0 4294967295 RESOURCE32_RESET 0 0 RESOURCE33_RESET 1 1 RESOURCE34_RESET 2 2 RESOURCE35_RESET 3 3 RESOURCE36_RESET 4 4 RESOURCE37_RESET 5 5 RESOURCE38_RESET 6 6 RESOURCE39_RESET 7 7 RESOURCE40_RESET 8 8 RESOURCE41_RESET 9 9 RESOURCE42_RESET 10 10 RESOURCE43_RESET 11 11 RESOURCE44_RESET 12 12 RESOURCE45_RESET 13 13 RESOURCE46_RESET 14 14 RESOURCE47_RESET 15 15 RESOURCE48_RESET 16 16 RESOURCE49_RESET 17 17 RESOURCE50_RESET 18 18 RESOURCE51_RESET 19 19 RESOURCE52_RESET 20 20 RESOURCE53_RESET 21 21 RESOURCE54_RESET 22 22 RESOURCE55_RESET 23 23 RESOURCE56_RESET 24 24 RESOURCE57_RESET 25 25 RESOURCE58_RESET 26 26 RESOURCE59_RESET 27 27 RESOURCE60_RESET 28 28 RESOURCE61_RESET 29 29 RESOURCE62_RESET 30 30 RESOURCE63_RESET 31 31 mmGDS_GWS_RESOURCE_RESET 0 0x3346 2 0 4294967295 RESET 0 0 RESOURCE_ID 8 15 mmGDS_COMPUTE_MAX_WAVE_ID 0 0x3348 1 0 4294967295 MAX_WAVE_ID 0 11 mmGDS_OA_RESET_MASK 0 0x3349 13 0 4294967295 ME0_GFXHP3D_PIX_RESET 0 0 ME0_GFXHP3D_VTX_RESET 1 1 ME0_CS_RESET 2 2 UNUSED0 3 3 ME1_PIPE0_RESET 4 4 ME1_PIPE1_RESET 5 5 ME1_PIPE2_RESET 6 6 ME1_PIPE3_RESET 7 7 ME2_PIPE0_RESET 8 8 ME2_PIPE1_RESET 9 9 ME2_PIPE2_RESET 10 10 ME2_PIPE3_RESET 11 11 UNUSED1 12 31 mmGDS_OA_RESET 0 0x334a 2 0 4294967295 RESET 0 0 PIPE_ID 8 15 mmCS_COPY_STATE 0 0xa1f3 1 0 4294967295 SRC_STATE_ID 0 2 mmGFX_COPY_STATE 0 0xa1f4 1 0 4294967295 SRC_STATE_ID 0 2 mmVGT_DRAW_INITIATOR 0 0xa1fc 5 0 4294967295 SOURCE_SELECT 0 1 MAJOR_MODE 2 3 SPRITE_EN_R6XX 4 4 NOT_EOP 5 5 USE_OPAQUE 6 6 mmVGT_EVENT_INITIATOR 0 0xa2a4 3 0 4294967295 EVENT_TYPE 0 5 ADDRESS_HI 18 26 EXTENDED_EVENT 27 27 mmVGT_EVENT_ADDRESS_REG 0 0xa1fe 1 0 4294967295 ADDRESS_LOW 0 27 mmVGT_DMA_BASE_HI 0 0xa1f9 1 0 4294967295 BASE_ADDR 0 7 mmVGT_DMA_BASE 0 0xa1fa 1 0 4294967295 BASE_ADDR 0 31 mmVGT_DMA_INDEX_TYPE 0 0xa29f 7 0 4294967295 INDEX_TYPE 0 1 SWAP_MODE 2 3 BUF_TYPE 4 5 RDREQ_POLICY 6 7 ATC 8 8 NOT_EOP 9 9 REQ_PATH 10 10 mmVGT_DMA_NUM_INSTANCES 0 0xa2a2 1 0 4294967295 NUM_INSTANCES 0 31 mmIA_ENHANCE 0 0xa29c 1 0 4294967295 MISC 0 31 mmVGT_DMA_SIZE 0 0xa29d 1 0 4294967295 NUM_INDICES 0 31 mmVGT_DMA_MAX_SIZE 0 0xa29e 1 0 4294967295 MAX_SIZE 0 31 mmVGT_DMA_PRIMITIVE_TYPE 0 0x2271 1 0 4294967295 PRIM_TYPE 0 5 mmVGT_DMA_CONTROL 0 0x2272 3 0 4294967295 PRIMGROUP_SIZE 0 15 IA_SWITCH_ON_EOP 17 17 WD_SWITCH_ON_EOP 20 20 mmVGT_IMMED_DATA 0 0xa1fd 1 0 4294967295 DATA 0 31 mmVGT_INDEX_TYPE 0 0xc243 1 0 4294967295 INDEX_TYPE 0 1 mmVGT_NUM_INDICES 0 0xc24c 1 0 4294967295 NUM_INDICES 0 31 mmVGT_NUM_INSTANCES 0 0xc24d 1 0 4294967295 NUM_INSTANCES 0 31 mmVGT_PRIMITIVE_TYPE 0 0xc242 1 0 4294967295 PRIM_TYPE 0 5 mmVGT_PRIMITIVEID_EN 0 0xa2a1 2 0 4294967295 PRIMITIVEID_EN 0 0 DISABLE_RESET_ON_EOI 1 1 mmVGT_PRIMITIVEID_RESET 0 0xa2a3 1 0 4294967295 VALUE 0 31 mmVGT_VTX_CNT_EN 0 0xa2ae 1 0 4294967295 VTX_CNT_EN 0 0 mmVGT_REUSE_OFF 0 0xa2ad 1 0 4294967295 REUSE_OFF 0 0 mmVGT_INSTANCE_STEP_RATE_0 0 0xa2a8 1 0 4294967295 STEP_RATE 0 31 mmVGT_INSTANCE_STEP_RATE_1 0 0xa2a9 1 0 4294967295 STEP_RATE 0 31 mmVGT_MAX_VTX_INDX 0 0xa100 1 0 4294967295 MAX_INDX 0 31 mmVGT_MIN_VTX_INDX 0 0xa101 1 0 4294967295 MIN_INDX 0 31 mmVGT_INDX_OFFSET 0 0xa102 1 0 4294967295 INDX_OFFSET 0 31 mmVGT_VERTEX_REUSE_BLOCK_CNTL 0 0xa316 1 0 4294967295 VTX_REUSE_DEPTH 0 7 mmVGT_OUT_DEALLOC_CNTL 0 0xa317 1 0 4294967295 DEALLOC_DIST 0 6 mmVGT_MULTI_PRIM_IB_RESET_INDX 0 0xa103 1 0 4294967295 RESET_INDX 0 31 mmVGT_MULTI_PRIM_IB_RESET_EN 0 0xa2a5 1 0 4294967295 RESET_EN 0 0 mmVGT_ENHANCE 0 0xa294 1 0 4294967295 MISC 0 31 mmVGT_OUTPUT_PATH_CNTL 0 0xa284 1 0 4294967295 PATH_SELECT 0 2 mmVGT_HOS_CNTL 0 0xa285 1 0 4294967295 TESS_MODE 0 1 mmVGT_HOS_MAX_TESS_LEVEL 0 0xa286 1 0 4294967295 MAX_TESS 0 31 mmVGT_HOS_MIN_TESS_LEVEL 0 0xa287 1 0 4294967295 MIN_TESS 0 31 mmVGT_HOS_REUSE_DEPTH 0 0xa288 1 0 4294967295 REUSE_DEPTH 0 7 mmVGT_GROUP_PRIM_TYPE 0 0xa289 4 0 4294967295 PRIM_TYPE 0 4 RETAIN_ORDER 14 14 RETAIN_QUADS 15 15 PRIM_ORDER 16 18 mmVGT_GROUP_FIRST_DECR 0 0xa28a 1 0 4294967295 FIRST_DECR 0 3 mmVGT_GROUP_DECR 0 0xa28b 1 0 4294967295 DECR 0 3 mmVGT_GROUP_VECT_0_CNTL 0 0xa28c 6 0 4294967295 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 mmVGT_GROUP_VECT_1_CNTL 0 0xa28d 6 0 4294967295 COMP_X_EN 0 0 COMP_Y_EN 1 1 COMP_Z_EN 2 2 COMP_W_EN 3 3 STRIDE 8 15 SHIFT 16 23 mmVGT_GROUP_VECT_0_FMT_CNTL 0 0xa28e 8 0 4294967295 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 mmVGT_GROUP_VECT_1_FMT_CNTL 0 0xa28f 8 0 4294967295 X_CONV 0 3 X_OFFSET 4 7 Y_CONV 8 11 Y_OFFSET 12 15 Z_CONV 16 19 Z_OFFSET 20 23 W_CONV 24 27 W_OFFSET 28 31 mmVGT_VTX_VECT_EJECT_REG 0 0x222c 1 0 4294967295 PRIM_COUNT 0 9 mmVGT_DMA_DATA_FIFO_DEPTH 0 0x222d 1 0 4294967295 DMA_DATA_FIFO_DEPTH 0 8 mmVGT_DMA_REQ_FIFO_DEPTH 0 0x222e 1 0 4294967295 DMA_REQ_FIFO_DEPTH 0 5 mmVGT_DRAW_INIT_FIFO_DEPTH 0 0x222f 1 0 4294967295 DRAW_INIT_FIFO_DEPTH 0 5 mmVGT_LAST_COPY_STATE 0 0x2230 2 0 4294967295 SRC_STATE_ID 0 2 DST_STATE_ID 16 18 mmCC_GC_SHADER_ARRAY_CONFIG 0 0x226f 4 0 4294967295 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 HALF_LDS 4 4 INACTIVE_CUS 16 31 mmGC_USER_SHADER_ARRAY_CONFIG 0 0x2270 4 0 4294967295 DPFP_RATE 1 2 SQC_BALANCE_DISABLE 3 3 HALF_LDS 4 4 INACTIVE_CUS 16 31 mmVGT_GS_MODE 0 0xa290 15 0 4294967295 MODE 0 2 RESERVED_0 3 3 CUT_MODE 4 5 RESERVED_1 6 10 GS_C_PACK_EN 11 11 RESERVED_2 12 12 ES_PASSTHRU 13 13 COMPUTE_MODE 14 14 FAST_COMPUTE_MODE 15 15 ELEMENT_INFO_EN 16 16 PARTIAL_THD_AT_EOI 17 17 SUPPRESS_CUTS 18 18 ES_WRITE_OPTIMIZE 19 19 GS_WRITE_OPTIMIZE 20 20 ONCHIP 21 22 mmVGT_GS_ONCHIP_CNTL 0 0xa291 2 0 4294967295 ES_VERTS_PER_SUBGRP 0 10 GS_PRIMS_PER_SUBGRP 11 21 mmVGT_GS_OUT_PRIM_TYPE 0 0xa29b 5 0 4294967295 OUTPRIM_TYPE 0 5 OUTPRIM_TYPE_1 8 13 OUTPRIM_TYPE_2 16 21 OUTPRIM_TYPE_3 22 27 UNIQUE_TYPE_PER_STREAM 31 31 mmVGT_CACHE_INVALIDATION 0 0x2231 8 0 4294967295 CACHE_INVALIDATION 0 1 VS_NO_EXTRA_BUFFER 5 5 AUTO_INVLD_EN 6 7 USE_GS_DONE 9 9 DIS_RANGE_FULL_INVLD 11 11 GS_LATE_ALLOC_EN 12 12 STREAMOUT_FULL_FLUSH 13 13 ES_LIMIT 16 20 mmVGT_RESET_DEBUG 0 0x2232 3 0 4294967295 GS_DISABLE 0 0 TESS_DISABLE 1 1 WD_DISABLE 2 2 mmVGT_STRMOUT_DELAY 0 0x2233 5 0 4294967295 SKIP_DELAY 0 7 SE0_WD_DELAY 8 10 SE1_WD_DELAY 11 13 SE2_WD_DELAY 14 16 SE3_WD_DELAY 17 19 mmVGT_FIFO_DEPTHS 0 0x2234 4 0 4294967295 VS_DEALLOC_TBL_DEPTH 0 6 RESERVED_0 7 7 CLIPP_FIFO_DEPTH 8 21 RESERVED_1 22 22 mmVGT_GS_PER_ES 0 0xa295 1 0 4294967295 GS_PER_ES 0 10 mmVGT_ES_PER_GS 0 0xa296 1 0 4294967295 ES_PER_GS 0 10 mmVGT_GS_PER_VS 0 0xa297 1 0 4294967295 GS_PER_VS 0 3 mmVGT_GS_VERTEX_REUSE 0 0x2235 1 0 4294967295 VERT_REUSE 0 4 mmVGT_MC_LAT_CNTL 0 0x2236 1 0 4294967295 MC_TIME_STAMP_RES 0 1 mmIA_CNTL_STATUS 0 0x2237 5 0 4294967295 IA_BUSY 0 0 IA_DMA_BUSY 1 1 IA_DMA_REQ_BUSY 2 2 IA_GRP_BUSY 3 3 IA_ADC_BUSY 4 4 mmVGT_STRMOUT_CONFIG 0 0xa2e5 7 0 4294967295 STREAMOUT_0_EN 0 0 STREAMOUT_1_EN 1 1 STREAMOUT_2_EN 2 2 STREAMOUT_3_EN 3 3 RAST_STREAM 4 6 RAST_STREAM_MASK 8 11 USE_RAST_STREAM_MASK 31 31 mmVGT_STRMOUT_BUFFER_SIZE_0 0 0xa2b4 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_SIZE_1 0 0xa2b8 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_SIZE_2 0 0xa2bc 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_SIZE_3 0 0xa2c0 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_OFFSET_0 0 0xa2b7 1 0 4294967295 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_OFFSET_1 0 0xa2bb 1 0 4294967295 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_OFFSET_2 0 0xa2bf 1 0 4294967295 OFFSET 0 31 mmVGT_STRMOUT_BUFFER_OFFSET_3 0 0xa2c3 1 0 4294967295 OFFSET 0 31 mmVGT_STRMOUT_VTX_STRIDE_0 0 0xa2b5 1 0 4294967295 STRIDE 0 9 mmVGT_STRMOUT_VTX_STRIDE_1 0 0xa2b9 1 0 4294967295 STRIDE 0 9 mmVGT_STRMOUT_VTX_STRIDE_2 0 0xa2bd 1 0 4294967295 STRIDE 0 9 mmVGT_STRMOUT_VTX_STRIDE_3 0 0xa2c1 1 0 4294967295 STRIDE 0 9 mmVGT_STRMOUT_BUFFER_CONFIG 0 0xa2e6 4 0 4294967295 STREAM_0_BUFFER_EN 0 3 STREAM_1_BUFFER_EN 4 7 STREAM_2_BUFFER_EN 8 11 STREAM_3_BUFFER_EN 12 15 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0 0xc244 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0 0xc245 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0 0xc246 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0 0xc247 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0 0xa2ca 1 0 4294967295 OFFSET 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0 0xa2cb 1 0 4294967295 SIZE 0 31 mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0 0xa2cc 1 0 4294967295 VERTEX_STRIDE 0 8 mmVGT_GS_MAX_VERT_OUT 0 0xa2ce 1 0 4294967295 MAX_VERT_OUT 0 10 mmIA_VMID_OVERRIDE 0 0x2260 2 0 4294967295 ENABLE 0 0 VMID 1 4 mmVGT_SHADER_STAGES_EN 0 0xa2d5 6 0 4294967295 LS_EN 0 1 HS_EN 2 2 ES_EN 3 4 GS_EN 5 5 VS_EN 6 7 DYNAMIC_HS 8 8 mmVGT_LS_HS_CONFIG 0 0xa2d6 3 0 4294967295 NUM_PATCHES 0 7 HS_NUM_INPUT_CP 8 13 HS_NUM_OUTPUT_CP 14 19 mmVGT_DMA_LS_HS_CONFIG 0 0x2273 1 0 4294967295 HS_NUM_INPUT_CP 8 13 mmVGT_TF_PARAM 0 0xa2db 8 0 4294967295 TYPE 0 1 PARTITIONING 2 4 TOPOLOGY 5 7 RESERVED_REDUC_AXIS 8 8 DEPRECATED 9 9 NUM_DS_WAVES_PER_SIMD 10 13 DISABLE_DONUTS 14 14 RDREQ_POLICY 15 16 mmVGT_TF_RING_SIZE 0 0xc24e 1 0 4294967295 SIZE 0 15 mmVGT_SYS_CONFIG 0 0x2263 3 0 4294967295 DUAL_CORE_EN 0 0 MAX_LS_HS_THDGRP 1 6 ADC_EVENT_FILTER_DISABLE 7 7 mmVGT_HS_OFFCHIP_PARAM 0 0xc24f 2 0 4294967295 OFFCHIP_BUFFERING 0 8 OFFCHIP_GRANULARITY 9 10 mmVGT_TF_MEMORY_BASE 0 0xc250 1 0 4294967295 BASE 0 31 mmVGT_GS_INSTANCE_CNT 0 0xa2e4 2 0 4294967295 ENABLE 0 0 CNT 2 8 mmIA_MULTI_VGT_PARAM 0 0xa2aa 6 0 4294967295 PRIMGROUP_SIZE 0 15 PARTIAL_VS_WAVE_ON 16 16 SWITCH_ON_EOP 17 17 PARTIAL_ES_WAVE_ON 18 18 SWITCH_ON_EOI 19 19 WD_SWITCH_ON_EOP 20 20 mmVGT_VS_MAX_WAVE_ID 0 0x2268 1 0 4294967295 MAX_WAVE_ID 0 11 mmVGT_ESGS_RING_SIZE 0 0xc240 1 0 4294967295 MEM_SIZE 0 31 mmVGT_GSVS_RING_SIZE 0 0xc241 1 0 4294967295 MEM_SIZE 0 31 mmVGT_GSVS_RING_OFFSET_1 0 0xa298 1 0 4294967295 OFFSET 0 14 mmVGT_GSVS_RING_OFFSET_2 0 0xa299 1 0 4294967295 OFFSET 0 14 mmVGT_GSVS_RING_OFFSET_3 0 0xa29a 1 0 4294967295 OFFSET 0 14 mmVGT_ESGS_RING_ITEMSIZE 0 0xa2ab 1 0 4294967295 ITEMSIZE 0 14 mmVGT_GSVS_RING_ITEMSIZE 0 0xa2ac 1 0 4294967295 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE 0 0xa2d7 1 0 4294967295 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_1 0 0xa2d8 1 0 4294967295 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_2 0 0xa2d9 1 0 4294967295 ITEMSIZE 0 14 mmVGT_GS_VERT_ITEMSIZE_3 0 0xa2da 1 0 4294967295 ITEMSIZE 0 14 mmWD_CNTL_STATUS 0 0x223f 4 0 4294967295 WD_BUSY 0 0 WD_SPL_DMA_BUSY 1 1 WD_SPL_DI_BUSY 2 2 WD_ADC_BUSY 3 3 mmWD_ENHANCE 0 0xa2a0 1 0 4294967295 MISC 0 31 mmGFX_PIPE_CONTROL 0 0x226d 3 0 4294967295 HYSTERESIS_CNT 0 12 RESERVED 13 15 CONTEXT_SUSPEND_EN 16 16 mmGFX_PIPE_PRIORITY 0 0xf87f 1 0 4294967295 HP_PIPE_SELECT 0 0 mmCGTT_VGT_CLK_CTRL 0 0xf084 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 PERF_ENABLE 25 25 DBG_ENABLE 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 GS_OVERRIDE 29 29 CORE_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmCGTT_IA_CLK_CTRL 0 0xf085 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 PERF_ENABLE 25 25 DBG_ENABLE 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 CORE_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmCGTT_WD_CLK_CTRL 0 0xf086 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 PERF_ENABLE 25 25 DBG_ENABLE 26 26 SOFT_OVERRIDE4 27 27 ADC_OVERRIDE 28 28 CORE_OVERRIDE 29 29 RBIU_INPUT_OVERRIDE 30 30 REG_OVERRIDE 31 31 mmVGT_DEBUG_CNTL 0 0x2238 2 0 4294967295 VGT_DEBUG_INDX 0 5 VGT_DEBUG_SEL_BUS_B 6 6 mmVGT_DEBUG_DATA 0 0x2239 1 0 4294967295 DATA 0 31 mmIA_DEBUG_CNTL 0 0x223a 2 0 4294967295 IA_DEBUG_INDX 0 5 IA_DEBUG_SEL_BUS_B 6 6 mmIA_DEBUG_DATA 0 0x223b 1 0 4294967295 DATA 0 31 mmVGT_CNTL_STATUS 0 0x223c 10 0 4294967295 VGT_BUSY 0 0 VGT_OUT_INDX_BUSY 1 1 VGT_OUT_BUSY 2 2 VGT_PT_BUSY 3 3 VGT_TE_BUSY 4 4 VGT_VR_BUSY 5 5 VGT_PI_BUSY 6 6 VGT_GS_BUSY 7 7 VGT_HS_BUSY 8 8 VGT_TE11_BUSY 9 9 mmWD_DEBUG_CNTL 0 0x223d 2 0 4294967295 WD_DEBUG_INDX 0 5 WD_DEBUG_SEL_BUS_B 6 6 mmWD_DEBUG_DATA 0 0x223e 1 0 4294967295 DATA 0 31 mmCC_GC_PRIM_CONFIG 0 0x2240 2 0 4294967295 INACTIVE_IA 16 17 INACTIVE_VGT_PA 24 27 mmGC_USER_PRIM_CONFIG 0 0x2241 2 0 4294967295 INACTIVE_IA 16 17 INACTIVE_VGT_PA 24 27 ixWD_DEBUG_REG0 2 0x0 32 0 4294967295 wd_busy_extended 0 0 wd_nodma_busy_extended 1 1 wd_busy 2 2 wd_nodma_busy 3 3 rbiu_busy 4 4 spl_dma_busy 5 5 spl_di_busy 6 6 vgt0_active_q 7 7 vgt1_active_q 8 8 spl_dma_p1_busy 9 9 rbiu_dr_p1_fifo_busy 10 10 rbiu_di_p1_fifo_busy 11 11 SPARE2 12 12 rbiu_dr_fifo_busy 13 13 rbiu_spl_dr_valid 14 14 spl_rbiu_dr_read 15 15 SPARE3 16 16 rbiu_di_fifo_busy 17 17 rbiu_spl_di_valid 18 18 spl_rbiu_di_read 19 19 se0_synced_q 20 20 se1_synced_q 21 21 se2_synced_q 22 22 se3_synced_q 23 23 reg_clk_busy 24 24 input_clk_busy 25 25 core_clk_busy 26 26 vgt2_active_q 27 27 sclk_reg_vld 28 28 sclk_input_vld 29 29 sclk_core_vld 30 30 vgt3_active_q 31 31 ixWD_DEBUG_REG1 2 0x1 21 0 4294967295 grbm_fifo_empty 0 0 grbm_fifo_full 1 1 grbm_fifo_we 2 2 grbm_fifo_re 3 3 draw_initiator_valid_q 4 4 event_initiator_valid_q 5 5 event_addr_valid_q 6 6 dma_request_valid_q 7 7 SPARE0 8 8 min_indx_valid_q 9 9 max_indx_valid_q 10 10 indx_offset_valid_q 11 11 grbm_fifo_rdata_reg_id 12 16 grbm_fifo_rdata_state 17 19 free_cnt_q 20 25 rbiu_di_fifo_we 26 26 rbiu_dr_fifo_we 27 27 rbiu_di_fifo_empty 28 28 rbiu_di_fifo_full 29 29 rbiu_dr_fifo_empty 30 30 rbiu_dr_fifo_full 31 31 ixWD_DEBUG_REG2 2 0x2 21 0 4294967295 p1_grbm_fifo_empty 0 0 p1_grbm_fifo_full 1 1 p1_grbm_fifo_we 2 2 p1_grbm_fifo_re 3 3 p1_draw_initiator_valid_q 4 4 p1_event_initiator_valid_q 5 5 p1_event_addr_valid_q 6 6 p1_dma_request_valid_q 7 7 SPARE0 8 8 p1_min_indx_valid_q 9 9 p1_max_indx_valid_q 10 10 p1_indx_offset_valid_q 11 11 p1_grbm_fifo_rdata_reg_id 12 16 p1_grbm_fifo_rdata_state 17 19 p1_free_cnt_q 20 25 p1_rbiu_di_fifo_we 26 26 p1_rbiu_dr_fifo_we 27 27 p1_rbiu_di_fifo_empty 28 28 p1_rbiu_di_fifo_full 29 29 p1_rbiu_dr_fifo_empty 30 30 p1_rbiu_dr_fifo_full 31 31 ixWD_DEBUG_REG3 2 0x3 31 0 4294967295 rbiu_spl_dr_valid 0 0 SPARE0 1 1 pipe0_dr 2 2 pipe0_rtr 3 3 pipe1_dr 4 4 pipe1_rtr 5 5 wd_subdma_fifo_empty 6 6 wd_subdma_fifo_full 7 7 dma_buf_type_p0_q 8 9 dma_zero_indices_p0_q 10 10 dma_req_path_p3_q 11 11 dma_not_eop_p1_q 12 12 out_of_range_p4 13 13 last_sub_dma_p3_q 14 14 last_rdreq_of_sub_dma_p4 15 15 WD_IA_dma_send_d 16 16 WD_IA_dma_rtr 17 17 WD_IA1_dma_send_d 18 18 WD_IA1_dma_rtr 19 19 last_inst_of_dma_p2 20 20 last_sd_of_inst_p2 21 21 last_sd_of_dma_p2 22 22 SPARE1 23 23 WD_IA_dma_busy 24 24 WD_IA1_dma_busy 25 25 send_to_ia1_p3_q 26 26 dma_wd_switch_on_eop_p3_q 27 27 pipe3_dr 28 28 pipe3_rtr 29 29 wd_dma2draw_fifo_empty 30 30 wd_dma2draw_fifo_full 31 31 ixWD_DEBUG_REG4 2 0x4 29 0 4294967295 rbiu_spl_di_valid 0 0 spl_rbiu_di_read 1 1 rbiu_spl_p1_di_valid 2 2 spl_rbiu_p1_di_read 3 3 pipe0_dr 4 4 pipe0_rtr 5 5 pipe1_dr 6 6 pipe1_rtr 7 7 pipe2_dr 8 8 pipe2_rtr 9 9 pipe3_ld 10 10 pipe3_rtr 11 11 WD_IA_draw_send_d 12 12 WD_IA_draw_rtr 13 13 di_type_p0 14 15 di_state_sel_p1_q 16 18 di_wd_switch_on_eop_p1_q 19 19 rbiu_spl_pipe0_lockout 20 20 last_inst_of_di_p2 21 21 last_sd_of_inst_p2 22 22 last_sd_of_di_p2 23 23 not_eop_wait_p1_q 24 24 not_eop_wait_q 25 25 ext_event_wait_p1_q 26 26 ext_event_wait_q 27 27 WD_IA1_draw_send_d 28 28 WD_IA1_draw_rtr 29 29 send_to_ia1_q 30 30 dual_ia_mode 31 31 ixWD_DEBUG_REG5 2 0x5 31 0 4294967295 p1_rbiu_spl_dr_valid 0 0 SPARE0 1 1 p1_pipe0_dr 2 2 p1_pipe0_rtr 3 3 p1_pipe1_dr 4 4 p1_pipe1_rtr 5 5 p1_wd_subdma_fifo_empty 6 6 p1_wd_subdma_fifo_full 7 7 p1_dma_buf_type_p0_q 8 9 p1_dma_zero_indices_p0_q 10 10 p1_dma_req_path_p3_q 11 11 p1_dma_not_eop_p1_q 12 12 p1_out_of_range_p4 13 13 p1_last_sub_dma_p3_q 14 14 p1_last_rdreq_of_sub_dma_p4 15 15 p1_WD_IA_dma_send_d 16 16 p1_WD_IA_dma_rtr 17 17 p1_WD_IA1_dma_send_d 18 18 p1_WD_IA1_dma_rtr 19 19 p1_last_inst_of_dma_p2 20 20 p1_last_sd_of_inst_p2 21 21 p1_last_sd_of_dma_p2 22 22 SPARE1 23 23 p1_WD_IA_dma_busy 24 24 p1_WD_IA1_dma_busy 25 25 p1_send_to_ia1_p3_q 26 26 p1_dma_wd_switch_on_eop_p3_q 27 27 p1_pipe3_dr 28 28 p1_pipe3_rtr 29 29 p1_wd_dma2draw_fifo_empty 30 30 p1_wd_dma2draw_fifo_full 31 31 ixIA_DEBUG_REG0 2 0x0 23 0 4294967295 ia_busy_extended 0 0 ia_nodma_busy_extended 1 1 ia_busy 2 2 ia_nodma_busy 3 3 SPARE0 4 4 dma_req_busy 5 5 dma_busy 6 6 mc_xl8r_busy 7 7 grp_busy 8 8 SPARE1 9 9 dma_grp_valid 10 10 grp_dma_read 11 11 dma_grp_hp_valid 12 12 grp_dma_hp_read 13 13 SPARE2 14 23 reg_clk_busy 24 24 core_clk_busy 25 25 SPARE3 26 26 SPARE4 27 27 sclk_reg_vld 28 28 sclk_core_vld 29 29 SPARE5 30 30 SPARE6 31 31 ixIA_DEBUG_REG1 2 0x1 31 0 4294967295 dma_input_fifo_empty 0 0 dma_input_fifo_full 1 1 start_new_packet 2 2 dma_rdreq_dr_q 3 3 dma_zero_indices_q 4 4 dma_buf_type_q 5 6 dma_req_path_q 7 7 discard_1st_chunk 8 8 discard_2nd_chunk 9 9 second_tc_ret_data_q 10 10 dma_tc_ret_sel_q 11 11 last_rdreq_in_dma_op 12 12 dma_mask_fifo_empty 13 13 dma_data_fifo_empty_q 14 14 dma_data_fifo_full 15 15 dma_req_fifo_empty 16 16 dma_req_fifo_full 17 17 stage2_dr 18 18 stage2_rtr 19 19 stage3_dr 20 20 stage3_rtr 21 21 stage4_dr 22 22 stage4_rtr 23 23 dma_skid_fifo_empty 24 24 dma_skid_fifo_full 25 25 dma_grp_valid 26 26 grp_dma_read 27 27 current_data_valid 28 28 out_of_range_r2_q 29 29 dma_mask_fifo_we 30 30 dma_ret_data_we_q 31 31 ixIA_DEBUG_REG2 2 0x2 31 0 4294967295 hp_dma_input_fifo_empty 0 0 hp_dma_input_fifo_full 1 1 hp_start_new_packet 2 2 hp_dma_rdreq_dr_q 3 3 hp_dma_zero_indices_q 4 4 hp_dma_buf_type_q 5 6 hp_dma_req_path_q 7 7 hp_discard_1st_chunk 8 8 hp_discard_2nd_chunk 9 9 hp_second_tc_ret_data_q 10 10 hp_dma_tc_ret_sel_q 11 11 hp_last_rdreq_in_dma_op 12 12 hp_dma_mask_fifo_empty 13 13 hp_dma_data_fifo_empty_q 14 14 hp_dma_data_fifo_full 15 15 hp_dma_req_fifo_empty 16 16 hp_dma_req_fifo_full 17 17 hp_stage2_dr 18 18 hp_stage2_rtr 19 19 hp_stage3_dr 20 20 hp_stage3_rtr 21 21 hp_stage4_dr 22 22 hp_stage4_rtr 23 23 hp_dma_skid_fifo_empty 24 24 hp_dma_skid_fifo_full 25 25 hp_dma_grp_valid 26 26 hp_grp_dma_read 27 27 hp_current_data_valid 28 28 hp_out_of_range_r2_q 29 29 hp_dma_mask_fifo_we 30 30 hp_dma_ret_data_we_q 31 31 ixIA_DEBUG_REG3 2 0x3 31 0 4294967295 dma_pipe0_rdreq_valid 0 0 dma_pipe0_rdreq_read 1 1 dma_pipe0_rdreq_null_out 2 2 dma_pipe0_rdreq_eop_out 3 3 dma_pipe0_rdreq_use_tc_out 4 4 grp_dma_draw_is_pipe0 5 5 must_service_pipe0_req 6 6 send_pipe1_req 7 7 dma_pipe1_rdreq_valid 8 8 dma_pipe1_rdreq_read 9 9 dma_pipe1_rdreq_null_out 10 10 dma_pipe1_rdreq_eop_out 11 11 dma_pipe1_rdreq_use_tc_out 12 12 ia_mc_rdreq_rtr_q 13 13 mc_out_rtr 14 14 dma_rdreq_send_out 15 15 pipe0_dr 16 16 pipe0_rtr 17 17 ia_tc_rdreq_rtr_q 18 18 tc_out_rtr 19 19 pair0_valid_p1 20 20 pair1_valid_p1 21 21 pair2_valid_p1 22 22 pair3_valid_p1 23 23 tc_req_count_q 24 25 discard_1st_chunk 26 26 discard_2nd_chunk 27 27 last_tc_req_p1 28 28 IA_TC_rdreq_send_out 29 29 TC_IA_rdret_valid_in 30 30 TAP_IA_rdret_vld_in 31 31 ixIA_DEBUG_REG4 2 0x4 27 0 4294967295 pipe0_dr 0 0 pipe1_dr 1 1 pipe2_dr 2 2 pipe3_dr 3 3 pipe4_dr 4 4 pipe5_dr 5 5 grp_se0_fifo_empty 6 6 grp_se0_fifo_full 7 7 pipe0_rtr 8 8 pipe1_rtr 9 9 pipe2_rtr 10 10 pipe3_rtr 11 11 pipe4_rtr 12 12 pipe5_rtr 13 13 ia_vgt_prim_rtr_q 14 14 ia_se1vgt_prim_rtr_q 15 15 di_major_mode_p1_q 16 16 gs_mode_p1_q 17 19 di_event_flag_p1_q 20 20 di_state_sel_p1_q 21 23 draw_opaq_en_p1_q 24 24 draw_opaq_active_q 25 25 di_source_select_p1_q 26 27 ready_to_read_di 28 28 di_first_group_of_draw_q 29 29 last_shift_of_draw 30 30 current_shift_is_vect1_q 31 31 ixIA_DEBUG_REG5 2 0x5 4 0 4294967295 di_index_counter_q_15_0 0 15 instanceid_13_0 16 29 draw_input_fifo_full 30 30 draw_input_fifo_empty 31 31 ixIA_DEBUG_REG6 2 0x6 11 0 4294967295 current_shift_q 0 3 current_stride_pre 4 7 current_stride_q 8 12 first_group_partial 13 13 second_group_partial 14 14 curr_prim_partial 15 15 next_stride_q 16 20 next_group_partial 21 21 after_group_partial 22 22 extract_group 23 23 grp_shift_debug_data 24 31 ixIA_DEBUG_REG7 2 0x7 15 0 4294967295 reset_indx_state_q 0 3 shift_vect_valid_p2_q 4 7 shift_vect1_valid_p2_q 8 11 shift_vect0_reset_match_p2_q 12 15 shift_vect1_reset_match_p2_q 16 19 num_indx_in_group_p2_q 20 22 last_group_of_draw_p2_q 23 23 shift_event_flag_p2_q 24 24 indx_shift_is_one_p2_q 25 25 indx_shift_is_two_p2_q 26 26 indx_stride_is_four_p2_q 27 27 shift_prim1_reset_p3_q 28 28 shift_prim1_partial_p3_q 29 29 shift_prim0_reset_p3_q 30 30 shift_prim0_partial_p3_q 31 31 ixIA_DEBUG_REG8 2 0x8 16 0 4294967295 di_prim_type_p1_q 0 4 two_cycle_xfer_p1_q 5 5 two_prim_input_p1_q 6 6 shift_vect_end_of_packet_p5_q 7 7 last_group_of_inst_p5_q 8 8 shift_prim1_null_flag_p5_q 9 9 shift_prim0_null_flag_p5_q 10 10 grp_continued 11 11 grp_state_sel 12 14 grp_sub_prim_type 15 20 grp_output_path 21 23 grp_null_primitive 24 24 grp_eop 25 25 grp_eopg 26 26 grp_event_flag 27 27 grp_components_valid 28 31 ixIA_DEBUG_REG9 2 0x9 21 0 4294967295 send_to_se1_p6 0 0 gfx_se_switch_p6 1 1 null_eoi_xfer_prim1_p6 2 2 null_eoi_xfer_prim0_p6 3 3 prim1_eoi_p6 4 4 prim0_eoi_p6 5 5 prim1_valid_eopg_p6 6 6 prim0_valid_eopg_p6 7 7 prim1_to_other_se_p6 8 8 eopg_on_last_prim_p6 9 9 eopg_between_prims_p6 10 10 prim_count_eq_group_size_p6 11 11 prim_count_gt_group_size_p6 12 12 two_prim_output_p5_q 13 13 SPARE0 14 14 SPARE1 15 15 shift_vect_end_of_packet_p5_q 16 16 prim1_xfer_p6 17 17 grp_se1_fifo_empty 18 18 grp_se1_fifo_full 19 19 prim_counter_q 20 31 ixVGT_DEBUG_REG0 2 0x0 32 0 4294967295 vgt_busy_extended 0 0 SPARE9 1 1 vgt_busy 2 2 SPARE8 3 3 SPARE7 4 4 SPARE6 5 5 SPARE5 6 6 SPARE4 7 7 pi_busy 8 8 vr_pi_busy 9 9 pt_pi_busy 10 10 te_pi_busy 11 11 gs_busy 12 12 rcm_busy 13 13 tm_busy 14 14 cm_busy 15 15 gog_busy 16 16 frmt_busy 17 17 SPARE10 18 18 te11_pi_busy 19 19 SPARE3 20 20 combined_out_busy 21 21 spi_vs_interfaces_busy 22 22 pa_interfaces_busy 23 23 reg_clk_busy 24 24 SPARE2 25 25 core_clk_busy 26 26 gs_clk_busy 27 27 SPARE1 28 28 sclk_core_vld 29 29 sclk_gs_vld 30 30 SPARE0 31 31 ixVGT_DEBUG_REG1 2 0x1 32 0 4294967295 SPARE9 0 0 SPARE8 1 1 SPARE7 2 2 SPARE6 3 3 SPARE5 4 4 SPARE4 5 5 SPARE3 6 6 SPARE2 7 7 SPARE1 8 8 SPARE0 9 9 pi_vr_valid 10 10 vr_pi_read 11 11 pi_pt_valid 12 12 pt_pi_read 13 13 pi_te_valid 14 14 te_grp_read 15 15 vr_out_indx_valid 16 16 SPARE12 17 17 vr_out_prim_valid 18 18 SPARE11 19 19 pt_out_indx_valid 20 20 SPARE10 21 21 pt_out_prim_valid 22 22 SPARE23 23 23 te_out_data_valid 24 24 SPARE25 25 25 pi_gs_valid 26 26 gs_pi_read 27 27 gog_out_indx_valid 28 28 out_indx_read 29 29 gog_out_prim_valid 30 30 out_prim_read 31 31 ixVGT_DEBUG_REG2 2 0x1e 30 0 4294967295 hs_grp_busy 0 0 hs_noif_busy 1 1 tfmmIsBusy 2 2 lsVertIfBusy_0 3 3 te11_hs_tess_input_rtr 4 4 lsWaveIfBusy_0 5 5 hs_te11_tess_input_rts 6 6 grpModBusy 7 7 lsVertFifoEmpty 8 8 lsWaveFifoEmpty 9 9 hsVertFifoEmpty 10 10 hsWaveFifoEmpty 11 11 hsInputFifoEmpty 12 12 hsTifFifoEmpty 13 13 lsVertFifoFull 14 14 lsWaveFifoFull 15 15 hsVertFifoFull 16 16 hsWaveFifoFull 17 17 hsInputFifoFull 18 18 hsTifFifoFull 19 19 p0_rtr 20 20 p1_rtr 21 21 p0_dr 22 22 p1_dr 23 23 p0_rts 24 24 p1_rts 25 25 ls_sh_id 26 26 lsFwaveFlag 27 27 lsWaveSendFlush 28 28 SPARE 29 31 ixVGT_DEBUG_REG3 2 0x1f 4 0 4294967295 lsTgRelInd 0 11 lsWaveRelInd 12 17 lsPatchCnt 18 25 hsWaveRelInd 26 31 ixVGT_DEBUG_REG4 2 0x20 6 0 4294967295 hsPatchCnt 0 7 hsPrimId_15_0 8 23 hsCpCnt 24 28 hsWaveSendFlush 29 29 hsFwaveFlag 30 30 SPARE 31 31 ixVGT_DEBUG_REG5 2 0x21 8 0 4294967295 SPARE4 0 2 hsWaveCreditCnt_0 3 7 SPARE3 8 10 hsVertCreditCnt_0 11 15 SPARE2 16 18 lsWaveCreditCnt_0 19 23 SPARE1 24 26 lsVertCreditCnt_0 27 31 ixVGT_DEBUG_REG6 2 0x22 2 0 4294967295 debug_BASE 0 15 debug_SIZE 16 31 ixVGT_DEBUG_REG7 2 0x23 7 0 4294967295 debug_tfmmFifoEmpty 0 0 debug_tfmmFifoFull 1 1 hs_pipe0_dr 2 2 hs_pipe0_rtr 3 3 hs_pipe1_rtr 4 4 SPARE 5 15 TF_addr 16 31 ixVGT_DEBUG_REG8 2 0x8 32 0 4294967295 rcm_busy_q 0 0 rcm_noif_busy_q 1 1 r1_inst_rtr 2 2 spi_gsprim_fifo_busy_q 3 3 spi_esvert_fifo_busy_q 4 4 gs_tbl_valid_r3_q 5 5 valid_r0_q 6 6 valid_r1_q 7 7 valid_r2 8 8 valid_r2_q 9 9 r0_rtr 10 10 r1_rtr 11 11 r2_indx_rtr 12 12 r2_rtr 13 13 es_gs_rtr 14 14 gs_event_fifo_rtr 15 15 tm_rcm_gs_event_rtr 16 16 gs_tbl_r3_rtr 17 17 prim_skid_fifo_empty 18 18 VGT_SPI_gsprim_rtr_q 19 19 tm_rcm_gs_tbl_rtr 20 20 tm_rcm_es_tbl_rtr 21 21 VGT_SPI_esvert_rtr_q 22 22 r2_no_bp_rtr 23 23 hold_for_es_flush 24 24 gs_event_fifo_empty 25 25 gsprim_buff_empty_q 26 26 gsprim_buff_full_q 27 27 te_prim_fifo_empty 28 28 te_prim_fifo_full 29 29 te_vert_fifo_empty 30 30 te_vert_fifo_full 31 31 ixVGT_DEBUG_REG9 2 0x9 23 0 4294967295 indices_to_send_r2_q 0 1 valid_indices_r3 2 2 gs_eov_r3 3 3 eop_indx_r3 4 4 eop_prim_r3 5 5 es_eov_r3 6 6 es_tbl_state_r3_q_0 7 7 pending_es_send_r3_q 8 8 pending_es_flush_r3 9 9 gs_tbl_num_es_per_gs_r3_q_not_0 10 10 gs_tbl_prim_cnt_r3_q 11 17 gs_tbl_eop_r3_q 18 18 gs_tbl_state_r3_q 19 21 gs_pending_state_r3_q 22 22 invalidate_rb_roll_over_q 23 23 gs_instancing_state_q 24 24 es_per_gs_vert_cnt_r3_q_not_0 25 25 gs_prim_per_es_ctr_r3_q_not_0 26 26 pre_r0_rtr 27 27 valid_r3_q 28 28 valid_pre_r0_q 29 29 SPARE0 30 30 off_chip_hs_r2_q 31 31 ixVGT_DEBUG_REG10 2 0xa 9 0 4294967295 index_buffer_depth_r1_q 0 4 eopg_r2_q 5 5 eotg_r2_q 6 6 onchip_gs_en_r0_q 7 8 SPARE2 9 10 rcm_mem_gsprim_re_qq 11 11 rcm_mem_gsprim_re_q 12 12 gs_rb_space_avail_r3_q_9_0 13 22 es_rb_space_avail_r2_q_8_0 23 31 ixVGT_DEBUG_REG11 2 0xb 32 0 4294967295 tm_busy_q 0 0 tm_noif_busy_q 1 1 tm_out_busy_q 2 2 es_rb_dealloc_fifo_busy 3 3 vs_dealloc_tbl_busy 4 4 SPARE1 5 5 spi_gsthread_fifo_busy 6 6 spi_esthread_fifo_busy 7 7 hold_eswave 8 8 es_rb_roll_over_r3 9 9 counters_busy_r0 10 10 counters_avail_r0 11 11 counters_available_r0 12 12 vs_event_fifo_rtr 13 13 VGT_SPI_gsthread_rtr_q 14 14 VGT_SPI_esthread_rtr_q 15 15 gs_issue_rtr 16 16 tm_pt_event_rtr 17 17 SPARE0 18 18 gs_r0_rtr 19 19 es_r0_rtr 20 20 gog_tm_vs_event_rtr 21 21 tm_rcm_gs_event_rtr 22 22 tm_rcm_gs_tbl_rtr 23 23 tm_rcm_es_tbl_rtr 24 24 vs_event_fifo_empty 25 25 vs_event_fifo_full 26 26 es_rb_dealloc_fifo_full 27 27 vs_dealloc_tbl_full 28 28 send_event_q 29 29 es_tbl_empty 30 30 no_active_states_r0 31 31 ixVGT_DEBUG_REG12 2 0xc 12 0 4294967295 gs_state0_r0_q 0 2 gs_state1_r0_q 3 5 gs_state2_r0_q 6 8 gs_state3_r0_q 9 11 gs_state4_r0_q 12 14 gs_state5_r0_q 15 17 gs_state6_r0_q 18 20 gs_state7_r0_q 21 23 gs_state8_r0_q 24 26 gs_state9_r0_q 27 29 hold_eswave_eop 30 30 SPARE0 31 31 ixVGT_DEBUG_REG13 2 0xd 13 0 4294967295 gs_state10_r0_q 0 2 gs_state11_r0_q 3 5 gs_state12_r0_q 6 8 gs_state13_r0_q 9 11 gs_state14_r0_q 12 14 gs_state15_r0_q 15 17 gs_tbl_wrptr_r0_q_3_0 18 21 gsfetch_done_fifo_cnt_q_not_0 22 22 gsfetch_done_cnt_q_not_0 23 23 es_tbl_full 24 24 SPARE1 25 25 SPARE0 26 26 active_cm_sm_r0_q 27 31 ixVGT_DEBUG_REG14 2 0xe 18 0 4294967295 SPARE3 0 3 gsfetch_done_fifo_full 4 4 gs_rb_space_avail_r0 5 5 smx_es_done_cnt_r0_q_not_0 6 6 SPARE8 7 8 vs_done_cnt_q_not_0 9 9 es_flush_cnt_busy_q 10 10 gs_tbl_full_r0 11 11 SPARE2 12 20 se1spi_gsthread_fifo_busy 21 21 SPARE 22 24 VGT_SE1SPI_gsthread_rtr_q 25 25 smx1_es_done_cnt_r0_q_not_0 26 26 se1spi_esthread_fifo_busy 27 27 SPARE1 28 28 gsfetch_done_se1_cnt_q_not_0 29 29 SPARE0 30 30 VGT_SE1SPI_esthread_rtr_q 31 31 ixVGT_DEBUG_REG15 2 0xf 12 0 4294967295 cm_busy_q 0 0 counters_busy_q 1 1 output_fifo_empty 2 2 output_fifo_full 3 3 counters_full 4 4 active_sm_q 5 9 entry_rdptr_q 10 14 cntr_tbl_wrptr_q 15 19 SPARE25 20 25 st_cut_mode_q 26 27 gs_done_array_q_not_0 28 28 SPARE31 29 31 ixVGT_DEBUG_REG16 2 0x10 28 0 4294967295 gog_busy 0 0 gog_state_q 1 3 r0_rtr 4 4 r1_rtr 5 5 r1_upstream_rtr 6 6 r2_vs_tbl_rtr 7 7 r2_prim_rtr 8 8 r2_indx_rtr 9 9 r2_rtr 10 10 gog_tm_vs_event_rtr 11 11 r3_force_vs_tbl_we_rtr 12 12 indx_valid_r2_q 13 13 prim_valid_r2_q 14 14 valid_r2_q 15 15 prim_valid_r1_q 16 16 indx_valid_r1_q 17 17 valid_r1_q 18 18 indx_valid_r0_q 19 19 prim_valid_r0_q 20 20 valid_r0_q 21 21 send_event_q 22 22 SPARE24 23 23 vert_seen_since_sopg_r2_q 24 24 gog_out_prim_state_sel 25 27 multiple_streams_en_r1_q 28 28 vs_vert_count_r2_q_not_0 29 29 num_gs_r2_q_not_0 30 30 new_vs_thread_r2 31 31 ixVGT_DEBUG_REG17 2 0x11 4 0 4294967295 gog_out_prim_rel_indx2_5_0 0 5 gog_out_prim_rel_indx1_5_0 6 11 gog_out_prim_rel_indx0_5_0 12 17 gog_out_indx_13_0 18 31 ixVGT_DEBUG_REG18 2 0x7 26 0 4294967295 grp_vr_valid 0 0 pipe0_dr 1 1 pipe1_dr 2 2 vr_grp_read 3 3 pipe0_rtr 4 4 pipe1_rtr 5 5 out_vr_indx_read 6 6 out_vr_prim_read 7 7 indices_to_send_q 8 10 valid_indices 11 11 last_indx_of_prim 12 12 indx0_new_d 13 13 indx1_new_d 14 14 indx2_new_d 15 15 indx2_hit_d 16 16 indx1_hit_d 17 17 indx0_hit_d 18 18 st_vertex_reuse_off_r0_q 19 19 last_group_of_instance_r0_q 20 20 null_primitive_r0_q 21 21 eop_r0_q 22 22 eject_vtx_vect_r1_d 23 23 sub_prim_type_r0_q 24 26 gs_scenario_a_r0_q 27 27 gs_scenario_b_r0_q 28 28 components_valid_r0_q 29 31 ixVGT_DEBUG_REG19 2 0x13 26 0 4294967295 separate_out_busy_q 0 0 separate_out_indx_busy_q 1 1 prim_buffer_empty 2 2 prim_buffer_full 3 3 pa_clips_fifo_busy_q 4 4 pa_clipp_fifo_busy_q 5 5 VGT_PA_clips_rtr_q 6 6 VGT_PA_clipp_rtr_q 7 7 spi_vsthread_fifo_busy_q 8 8 spi_vsvert_fifo_busy_q 9 9 pa_clipv_fifo_busy_q 10 10 hold_prim 11 11 VGT_SPI_vsthread_rtr_q 12 12 VGT_SPI_vsvert_rtr_q 13 13 VGT_PA_clipv_rtr_q 14 14 new_packet_q 15 15 buffered_prim_event 16 16 buffered_prim_null_primitive 17 17 buffered_prim_eop 18 18 buffered_prim_eject_vtx_vect 19 19 buffered_prim_type_event 20 25 VGT_SE1SPI_vswave_rtr_q 26 26 VGT_SE1SPI_vsvert_rtr_q 27 27 num_new_unique_rel_indx 28 29 null_terminate_vtx_vector 30 30 filter_event 31 31 ixVGT_DEBUG_REG20 2 0x14 8 0 4294967295 dbg_VGT_SPI_vsthread_sovertexindex 0 15 dbg_VGT_SPI_vsthread_sovertexcount_not_0 16 16 SPARE17 17 17 alloc_counter_q 18 21 curr_dealloc_distance_q 22 28 new_allocate_q 29 29 curr_slot_in_vtx_vect_q_not_0 30 30 int_vtx_counter_q_not_0 31 31 ixVGT_DEBUG_REG21 2 0x15 30 0 4294967295 out_indx_fifo_empty 0 0 indx_side_fifo_empty 1 1 pipe0_dr 2 2 pipe1_dr 3 3 pipe2_dr 4 4 vsthread_buff_empty 5 5 out_indx_fifo_full 6 6 indx_side_fifo_full 7 7 pipe0_rtr 8 8 pipe1_rtr 9 9 pipe2_rtr 10 10 vsthread_buff_full 11 11 interfaces_rtr 12 12 indx_count_q_not_0 13 13 wait_for_external_eopg_q 14 14 full_state_p1_q 15 15 indx_side_indx_valid 16 16 stateid_p0_q 17 19 is_event_p0_q 20 20 lshs_dealloc_p1 21 21 stream_id_r2_q 22 22 vtx_vect_counter_q_not_0 23 23 buff_full_p1 24 24 strmout_valid_p1 25 25 eotg_r2_q 26 26 null_r2_q 27 27 p0_dr 28 28 p0_rtr 29 29 eopg_p0_q 30 30 p0_nobp 31 31 ixVGT_DEBUG_REG22 2 0x16 16 0 4294967295 cm_state16 0 1 cm_state17 2 3 cm_state18 4 5 cm_state19 6 7 cm_state20 8 9 cm_state21 10 11 cm_state22 12 13 cm_state23 14 15 cm_state24 16 17 cm_state25 18 19 cm_state26 20 21 cm_state27 22 23 cm_state28 24 25 cm_state29 26 27 cm_state30 28 29 cm_state31 30 31 ixVGT_DEBUG_REG23 2 0x17 19 0 4294967295 frmt_busy 0 0 rcm_frmt_vert_rtr 1 1 rcm_frmt_prim_rtr 2 2 prim_r3_rtr 3 3 prim_r2_rtr 4 4 vert_r3_rtr 5 5 vert_r2_rtr 6 6 vert_r1_rtr 7 7 vert_r0_rtr 8 8 prim_fifo_empty 9 9 prim_fifo_full 10 10 vert_dr_r2_q 11 11 prim_dr_r2_q 12 12 vert_dr_r1_q 13 13 vert_dr_r0_q 14 14 new_verts_r2_q 15 16 verts_sent_r2_q 17 20 prim_state_sel_r2_q 21 23 SPARE 24 31 ixVGT_DEBUG_REG24 2 0x18 3 0 4294967295 avail_es_rb_space_r0_q_23_0 0 23 dependent_st_cut_mode_q 24 25 SPARE31 26 31 ixVGT_DEBUG_REG25 2 0x19 4 0 4294967295 avail_gs_rb_space_r0_q_25_0 0 25 active_sm_r0_q 26 29 add_gs_rb_space_r1_q 30 30 add_gs_rb_space_r0_q 31 31 ixVGT_DEBUG_REG26 2 0x24 16 0 4294967295 cm_state0 0 1 cm_state1 2 3 cm_state2 4 5 cm_state3 6 7 cm_state4 8 9 cm_state5 10 11 cm_state6 12 13 cm_state7 14 15 cm_state8 16 17 cm_state9 18 19 cm_state10 20 21 cm_state11 22 23 cm_state12 24 25 cm_state13 26 27 cm_state14 28 29 cm_state15 30 31 ixVGT_DEBUG_REG27 2 0x1b 20 0 4294967295 pipe0_dr 0 0 gsc0_dr 1 1 pipe1_dr 2 2 tm_pt_event_rtr 3 3 pipe0_rtr 4 4 gsc0_rtr 5 5 pipe1_rtr 6 6 last_indx_of_prim_p1_q 7 7 indices_to_send_p0_q 8 9 event_flag_p1_q 10 10 eop_p1_q 11 11 gs_out_prim_type_p0_q 12 13 gsc_null_primitive_p0_q 14 14 gsc_eop_p0_q 15 15 gsc_2cycle_output 16 16 gsc_2nd_cycle_p0_q 17 17 last_indx_of_vsprim 18 18 first_vsprim_of_gsprim_p0_q 19 19 gsc_indx_count_p0_q 20 30 last_vsprim_of_gsprim 31 31 ixVGT_DEBUG_REG28 2 0x1c 29 0 4294967295 con_state_q 0 3 second_cycle_q 4 4 process_tri_middle_p0_q 5 5 process_tri_1st_2nd_half_p0_q 6 6 process_tri_center_poly_p0_q 7 7 pipe0_patch_dr 8 8 pipe0_edge_dr 9 9 pipe1_dr 10 10 pipe0_patch_rtr 11 11 pipe0_edge_rtr 12 12 pipe1_rtr 13 13 outer_parity_p0_q 14 14 parallel_parity_p0_q 15 15 first_ring_of_patch_p0_q 16 16 last_ring_of_patch_p0_q 17 17 last_edge_of_outer_ring_p0_q 18 18 last_point_of_outer_ring_p1 19 19 last_point_of_inner_ring_p1 20 20 outer_edge_tf_eq_one_p0_q 21 21 advance_outer_point_p1 22 22 advance_inner_point_p1 23 23 next_ring_is_rect_p0_q 24 24 pipe1_outer1_rtr 25 25 pipe1_outer2_rtr 26 26 pipe1_inner1_rtr 27 27 pipe1_inner2_rtr 28 28 pipe1_patch_rtr 29 29 pipe1_edge_rtr 30 30 use_stored_inner_q_ring2 31 31 ixVGT_DEBUG_REG29 2 0x1d 29 0 4294967295 con_state_q 0 3 second_cycle_q 4 4 process_tri_middle_p0_q 5 5 process_tri_1st_2nd_half_p0_q 6 6 process_tri_center_poly_p0_q 7 7 pipe0_patch_dr 8 8 pipe0_edge_dr 9 9 pipe1_dr 10 10 pipe0_patch_rtr 11 11 pipe0_edge_rtr 12 12 pipe1_rtr 13 13 outer_parity_p0_q 14 14 parallel_parity_p0_q 15 15 first_ring_of_patch_p0_q 16 16 last_ring_of_patch_p0_q 17 17 last_edge_of_outer_ring_p0_q 18 18 last_point_of_outer_ring_p1 19 19 last_point_of_inner_ring_p1 20 20 outer_edge_tf_eq_one_p0_q 21 21 advance_outer_point_p1 22 22 advance_inner_point_p1 23 23 next_ring_is_rect_p0_q 24 24 pipe1_outer1_rtr 25 25 pipe1_outer2_rtr 26 26 pipe1_inner1_rtr 27 27 pipe1_inner2_rtr 28 28 pipe1_patch_rtr 29 29 pipe1_edge_rtr 30 30 use_stored_inner_q_ring3 31 31 ixVGT_DEBUG_REG30 2 0x25 26 0 4294967295 pipe0_dr 0 0 pipe0_tf_dr 1 1 pipe2_dr 2 2 event_or_null_p0_q 3 3 pipe0_rtr 4 4 pipe1_rtr 5 5 pipe1_tf_rtr 6 6 pipe2_rtr 7 7 ttp_patch_fifo_full 8 8 ttp_patch_fifo_empty 9 9 ttp_tf0_fifo_empty 10 10 ttp_tf1_fifo_empty 11 11 ttp_tf2_fifo_empty 12 12 ttp_tf3_fifo_empty 13 13 ttp_tf4_fifo_empty 14 14 ttp_tf5_fifo_empty 15 15 tf_fetch_state_q 16 18 last_tf_of_tg 19 19 tf_pointer_p0_q 20 23 dynamic_hs_p0_q 24 24 first_fetch_of_tg_p0_q 25 25 first_data_ret_of_req_p0_q 26 26 first_data_chunk_invalid_p0_q 27 27 tf_xfer_count_p2_q 28 29 pipe4_dr 30 30 pipe4_rtr 31 31 ixVGT_DEBUG_REG31 2 0x26 32 0 4294967295 pipe0_dr 0 0 pipe0_rtr 1 1 pipe1_outer_dr 2 2 pipe1_inner_dr 3 3 pipe2_outer_dr 4 4 pipe2_inner_dr 5 5 pipe3_outer_dr 6 6 pipe3_inner_dr 7 7 pipe4_outer_dr 8 8 pipe4_inner_dr 9 9 pipe5_outer_dr 10 10 pipe5_inner_dr 11 11 pipe2_outer_rtr 12 12 pipe2_inner_rtr 13 13 pipe3_outer_rtr 14 14 pipe3_inner_rtr 15 15 pipe4_outer_rtr 16 16 pipe4_inner_rtr 17 17 pipe5_outer_rtr 18 18 pipe5_inner_rtr 19 19 pg_con_outer_point1_rts 20 20 pg_con_outer_point2_rts 21 21 pg_con_inner_point1_rts 22 22 pg_con_inner_point2_rts 23 23 pg_patch_fifo_empty 24 24 pg_edge_fifo_empty 25 25 pg_inner3_perp_fifo_empty 26 26 pg_patch_fifo_full 27 27 pg_edge_fifo_full 28 28 pg_inner_perp_fifo_full 29 29 outer_ring_done_q 30 30 inner_ring_done_q 31 31 ixVGT_DEBUG_REG32 2 0x27 28 0 4294967295 first_ring_of_patch 0 0 last_ring_of_patch 1 1 last_edge_of_outer_ring 2 2 last_point_of_outer_edge 3 3 last_edge_of_inner_ring 4 4 last_point_of_inner_edge 5 5 last_patch_of_tg_p0_q 6 6 event_null_special_p0_q 7 7 event_flag_p5_q 8 8 first_point_of_patch_p5_q 9 9 first_point_of_edge_p5_q 10 10 last_patch_of_tg_p5_q 11 11 tess_topology_p5_q 12 13 pipe5_inner3_rtr 14 14 pipe5_inner2_rtr 15 15 pg_edge_fifo3_full 16 16 pg_edge_fifo2_full 17 17 pg_inner3_point_fifo_full 18 18 pg_outer3_point_fifo_full 19 19 pg_inner2_point_fifo_full 20 20 pg_outer2_point_fifo_full 21 21 pg_inner_point_fifo_full 22 22 pg_outer_point_fifo_full 23 23 inner2_fifos_rtr 24 24 inner_fifos_rtr 25 25 outer_fifos_rtr 26 26 fifos_rtr 27 27 SPARE 28 31 ixVGT_DEBUG_REG33 2 0x28 30 0 4294967295 pipe0_patch_dr 0 0 ring3_pipe1_dr 1 1 pipe1_dr 2 2 pipe2_dr 3 3 pipe0_patch_rtr 4 4 ring2_pipe1_dr 5 5 ring1_pipe1_dr 6 6 pipe2_rtr 7 7 pipe3_dr 8 8 pipe3_rtr 9 9 ring2_in_sync_q 10 10 ring1_in_sync_q 11 11 pipe1_patch_rtr 12 12 ring3_in_sync_q 13 13 tm_te11_event_rtr 14 14 first_prim_of_patch_q 15 15 con_prim_fifo_full 16 16 con_vert_fifo_full 17 17 con_prim_fifo_empty 18 18 con_vert_fifo_empty 19 19 last_patch_of_tg_p0_q 20 20 ring3_valid_p2 21 21 ring2_valid_p2 22 22 ring1_valid_p2 23 23 tess_type_p0_q 24 25 tess_topology_p0_q 26 27 te11_out_vert_gs_en 28 28 con_ring3_busy 29 29 con_ring2_busy 30 30 con_ring1_busy 31 31 ixVGT_DEBUG_REG34 2 0x29 29 0 4294967295 con_state_q 0 3 second_cycle_q 4 4 process_tri_middle_p0_q 5 5 process_tri_1st_2nd_half_p0_q 6 6 process_tri_center_poly_p0_q 7 7 pipe0_patch_dr 8 8 pipe0_edge_dr 9 9 pipe1_dr 10 10 pipe0_patch_rtr 11 11 pipe0_edge_rtr 12 12 pipe1_rtr 13 13 outer_parity_p0_q 14 14 parallel_parity_p0_q 15 15 first_ring_of_patch_p0_q 16 16 last_ring_of_patch_p0_q 17 17 last_edge_of_outer_ring_p0_q 18 18 last_point_of_outer_ring_p1 19 19 last_point_of_inner_ring_p1 20 20 outer_edge_tf_eq_one_p0_q 21 21 advance_outer_point_p1 22 22 advance_inner_point_p1 23 23 next_ring_is_rect_p0_q 24 24 pipe1_outer1_rtr 25 25 pipe1_outer2_rtr 26 26 pipe1_inner1_rtr 27 27 pipe1_inner2_rtr 28 28 pipe1_patch_rtr 29 29 pipe1_edge_rtr 30 30 use_stored_inner_q_ring1 31 31 ixVGT_DEBUG_REG35 2 0x2a 21 0 4294967295 pipe0_dr 0 0 pipe1_dr 1 1 pipe0_rtr 2 2 pipe1_rtr 3 3 tfreq_tg_fifo_empty 4 4 tfreq_tg_fifo_full 5 5 tf_data_fifo_busy_q 6 6 tf_data_fifo_rtr_q 7 7 tf_skid_fifo_empty 8 8 tf_skid_fifo_full 9 9 vgt_tc_rdreq_rtr_q 10 10 last_req_of_tg_p2 11 11 spi_vgt_hs_done_cnt_q 12 17 event_flag_p1_q 18 18 null_flag_p1_q 19 19 tf_data_fifo_cnt_q 20 26 second_tf_ret_data_q 27 27 first_req_of_tg_p1_q 28 28 VGT_TC_rdreq_send_out 29 29 VGT_TC_rdnfo_stall_out 30 30 TC_VGT_rdret_data_in 31 31 mmVGT_PERFCOUNTER_SEID_MASK 0 0xd894 1 0 4294967295 PERF_SEID_IGNORE_MASK 0 7 mmVGT_PERFCOUNTER0_SELECT 0 0xd88c 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmVGT_PERFCOUNTER1_SELECT 0 0xd88d 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmVGT_PERFCOUNTER2_SELECT 0 0xd88e 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmVGT_PERFCOUNTER3_SELECT 0 0xd88f 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmVGT_PERFCOUNTER0_SELECT1 0 0xd890 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmVGT_PERFCOUNTER1_SELECT1 0 0xd891 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmVGT_PERFCOUNTER0_LO 0 0xd090 1 0 4294967295 PERFCOUNTER_LO 0 31 mmVGT_PERFCOUNTER1_LO 0 0xd092 1 0 4294967295 PERFCOUNTER_LO 0 31 mmVGT_PERFCOUNTER2_LO 0 0xd094 1 0 4294967295 PERFCOUNTER_LO 0 31 mmVGT_PERFCOUNTER3_LO 0 0xd096 1 0 4294967295 PERFCOUNTER_LO 0 31 mmVGT_PERFCOUNTER0_HI 0 0xd091 1 0 4294967295 PERFCOUNTER_HI 0 31 mmVGT_PERFCOUNTER1_HI 0 0xd093 1 0 4294967295 PERFCOUNTER_HI 0 31 mmVGT_PERFCOUNTER2_HI 0 0xd095 1 0 4294967295 PERFCOUNTER_HI 0 31 mmVGT_PERFCOUNTER3_HI 0 0xd097 1 0 4294967295 PERFCOUNTER_HI 0 31 mmIA_PERFCOUNTER0_SELECT 0 0xd884 5 0 4294967295 PERF_SEL 0 9 PERF_SEL1 10 19 CNTR_MODE 20 23 PERF_MODE1 24 27 PERF_MODE 28 31 mmIA_PERFCOUNTER1_SELECT 0 0xd885 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmIA_PERFCOUNTER2_SELECT 0 0xd886 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmIA_PERFCOUNTER3_SELECT 0 0xd887 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmIA_PERFCOUNTER0_SELECT1 0 0xd888 4 0 4294967295 PERF_SEL2 0 9 PERF_SEL3 10 19 PERF_MODE3 24 27 PERF_MODE2 28 31 mmIA_PERFCOUNTER0_LO 0 0xd088 1 0 4294967295 PERFCOUNTER_LO 0 31 mmIA_PERFCOUNTER1_LO 0 0xd08a 1 0 4294967295 PERFCOUNTER_LO 0 31 mmIA_PERFCOUNTER2_LO 0 0xd08c 1 0 4294967295 PERFCOUNTER_LO 0 31 mmIA_PERFCOUNTER3_LO 0 0xd08e 1 0 4294967295 PERFCOUNTER_LO 0 31 mmIA_PERFCOUNTER0_HI 0 0xd089 1 0 4294967295 PERFCOUNTER_HI 0 31 mmIA_PERFCOUNTER1_HI 0 0xd08b 1 0 4294967295 PERFCOUNTER_HI 0 31 mmIA_PERFCOUNTER2_HI 0 0xd08d 1 0 4294967295 PERFCOUNTER_HI 0 31 mmIA_PERFCOUNTER3_HI 0 0xd08f 1 0 4294967295 PERFCOUNTER_HI 0 31 mmWD_PERFCOUNTER0_SELECT 0 0xd880 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmWD_PERFCOUNTER1_SELECT 0 0xd881 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmWD_PERFCOUNTER2_SELECT 0 0xd882 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmWD_PERFCOUNTER3_SELECT 0 0xd883 2 0 4294967295 PERF_SEL 0 7 PERF_MODE 28 31 mmWD_PERFCOUNTER0_LO 0 0xd080 1 0 4294967295 PERFCOUNTER_LO 0 31 mmWD_PERFCOUNTER1_LO 0 0xd082 1 0 4294967295 PERFCOUNTER_LO 0 31 mmWD_PERFCOUNTER2_LO 0 0xd084 1 0 4294967295 PERFCOUNTER_LO 0 31 mmWD_PERFCOUNTER3_LO 0 0xd086 1 0 4294967295 PERFCOUNTER_LO 0 31 mmWD_PERFCOUNTER0_HI 0 0xd081 1 0 4294967295 PERFCOUNTER_HI 0 31 mmWD_PERFCOUNTER1_HI 0 0xd083 1 0 4294967295 PERFCOUNTER_HI 0 31 mmWD_PERFCOUNTER2_HI 0 0xd085 1 0 4294967295 PERFCOUNTER_HI 0 31 mmWD_PERFCOUNTER3_HI 0 0xd087 1 0 4294967295 PERFCOUNTER_HI 0 31 mmDIDT_IND_INDEX 0 0x3280 1 0 4294967295 DIDT_IND_INDEX 0 31 mmDIDT_IND_DATA 0 0x3281 1 0 4294967295 DIDT_IND_DATA 0 31 ixDIDT_SQ_CTRL0 2 0x0 5 0 4294967295 DIDT_CTRL_EN 0 0 USE_REF_CLOCK 1 1 PHASE_OFFSET 2 3 DIDT_CTRL_RST 4 4 DIDT_CLK_EN_OVERRIDE 5 5 ixDIDT_SQ_CTRL1 2 0x1 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_SQ_CTRL2 2 0x2 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_SQ_WEIGHT0_3 2 0x10 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_SQ_WEIGHT4_7 2 0x11 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_SQ_WEIGHT8_11 2 0x12 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_DB_CTRL0 2 0x20 5 0 4294967295 DIDT_CTRL_EN 0 0 USE_REF_CLOCK 1 1 PHASE_OFFSET 2 3 DIDT_CTRL_RST 4 4 DIDT_CLK_EN_OVERRIDE 5 5 ixDIDT_DB_CTRL1 2 0x21 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_DB_CTRL2 2 0x22 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_DB_WEIGHT0_3 2 0x30 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_DB_WEIGHT4_7 2 0x31 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_DB_WEIGHT8_11 2 0x32 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TD_CTRL0 2 0x40 5 0 4294967295 DIDT_CTRL_EN 0 0 USE_REF_CLOCK 1 1 PHASE_OFFSET 2 3 DIDT_CTRL_RST 4 4 DIDT_CLK_EN_OVERRIDE 5 5 ixDIDT_TD_CTRL1 2 0x41 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TD_CTRL2 2 0x42 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TD_WEIGHT0_3 2 0x50 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TD_WEIGHT4_7 2 0x51 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TD_WEIGHT8_11 2 0x52 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31 ixDIDT_TCP_CTRL0 2 0x60 5 0 4294967295 DIDT_CTRL_EN 0 0 USE_REF_CLOCK 1 1 PHASE_OFFSET 2 3 DIDT_CTRL_RST 4 4 DIDT_CLK_EN_OVERRIDE 5 5 ixDIDT_TCP_CTRL1 2 0x61 2 0 4294967295 MIN_POWER 0 15 MAX_POWER 16 31 ixDIDT_TCP_CTRL2 2 0x62 3 0 4294967295 MAX_POWER_DELTA 0 13 SHORT_TERM_INTERVAL_SIZE 16 25 LONG_TERM_INTERVAL_RATIO 27 30 ixDIDT_TCP_WEIGHT0_3 2 0x70 4 0 4294967295 WEIGHT0 0 7 WEIGHT1 8 15 WEIGHT2 16 23 WEIGHT3 24 31 ixDIDT_TCP_WEIGHT4_7 2 0x71 4 0 4294967295 WEIGHT4 0 7 WEIGHT5 8 15 WEIGHT6 16 23 WEIGHT7 24 31 ixDIDT_TCP_WEIGHT8_11 2 0x72 4 0 4294967295 WEIGHT8 0 7 WEIGHT9 8 15 WEIGHT10 16 23 WEIGHT11 24 31