629 mmMC_CONFIG 0 0x800 6 0 4294967295 MCDW_WR_ENABLE 0 0 MCDX_WR_ENABLE 1 1 MCDY_WR_ENABLE 2 2 MCDZ_WR_ENABLE 3 3 MC_RD_ENABLE 4 5 MCC_INDEX_MODE_ENABLE 31 31 mmMC_ARB_AGE_CNTL 0 0x9bf 18 0 4294967295 RESET_RD_GROUP0 0 0 RESET_RD_GROUP1 1 1 RESET_RD_GROUP2 2 2 RESET_RD_GROUP3 3 3 RESET_RD_GROUP4 4 4 RESET_RD_GROUP5 5 5 RESET_RD_GROUP6 6 6 RESET_RD_GROUP7 7 7 RESET_WR_GROUP0 8 8 RESET_WR_GROUP1 9 9 RESET_WR_GROUP2 10 10 RESET_WR_GROUP3 11 11 RESET_WR_GROUP4 12 12 RESET_WR_GROUP5 13 13 RESET_WR_GROUP6 14 14 RESET_WR_GROUP7 15 15 AGE_LOW_RATE_RD 16 18 AGE_LOW_RATE_WR 19 21 mmMC_ARB_RET_CREDITS2 0 0x9c0 1 0 4294967295 ACP_WR 0 7 mmMC_ARB_FED_CNTL 0 0x9c1 6 0 4294967295 MODE 0 1 WR_ERR 2 3 KEEP_POISON_IN_PAGE 4 4 RDRET_PARITY_NACK 5 5 USE_LEGACY_NACK 6 6 DEBUG_RSV 7 31 mmMC_ARB_GECC2_STATUS 0 0x9c2 27 0 4294967295 CORR_STS0 0 0 UNCORR_STS0 1 1 FED_STS0 2 2 RSVD0 3 3 CORR_STS1 4 4 UNCORR_STS1 5 5 FED_STS1 6 6 RSVD1 7 7 CORR_CLEAR0 8 8 UNCORR_CLEAR0 9 9 FED_CLEAR0 10 10 RSVD2 11 11 CORR_CLEAR1 12 12 UNCORR_CLEAR1 13 13 FED_CLEAR1 14 14 RSVD3 15 15 RMWRD_CORR_STS0 16 16 RMWRD_UNCORR_STS0 17 17 RSVD4 18 19 RMWRD_CORR_STS1 20 20 RMWRD_UNCORR_STS1 21 21 RSVD5 22 23 RMWRD_CORR_CLEAR0 24 24 RMWRD_UNCORR_CLEAR0 25 25 RSVD6 26 27 RMWRD_CORR_CLEAR1 28 28 RMWRD_UNCORR_CLEAR1 29 29 mmMC_ARB_GECC2_MISC 0 0x9c3 5 0 4294967295 STREAK_BREAK 0 3 COL10_HACK 4 4 CWRD_IN_REPLAY 5 5 NO_EOB_ALL_WR_IN_REPLAY 6 6 DEBUG_RSV 7 31 mmMC_ARB_GECC2_DEBUG 0 0x9c4 4 0 4294967295 NUM_ERR_BITS 0 1 DIRECTION 2 2 DATA_FIELD 3 4 SW_INJECTION 5 5 mmMC_ARB_GECC2_DEBUG2 0 0x9c5 4 0 4294967295 PERIOD 0 7 ERR0_START 8 15 ERR1_START 16 23 ERR2_START 24 31 mmMC_ARB_GECC2 0 0x9c9 10 0 4294967295 ENABLE 0 0 ECC_MODE 1 2 PAGE_BIT0 3 4 EXOR_BANK_SEL 5 6 NO_GECC_CLI 7 10 READ_ERR 11 13 CLOSE_BANK_RMW 14 14 COLFIFO_WATER 15 20 WRADDR_CONV 21 21 RMWRD_UNCOR_POISON 22 22 mmMC_ARB_GECC2_CLI 0 0x9ca 4 0 4294967295 NO_GECC_CLI0 0 7 NO_GECC_CLI1 8 15 NO_GECC_CLI2 16 23 NO_GECC_CLI3 24 31 mmMC_ARB_ADDR_SWIZ0 0 0x9cb 8 0 4294967295 A8 0 3 A9 4 7 A10 8 11 A11 12 15 A12 16 19 A13 20 23 A14 24 27 A15 28 31 mmMC_ARB_ADDR_SWIZ1 0 0x9cc 4 0 4294967295 A16 0 3 A17 4 7 A18 8 11 A19 12 15 mmMC_ARB_MISC3 0 0x9cd 2 0 4294967295 NO_GECC_EXT_EOB 0 0 TBD_FIELD 1 31 mmMC_ARB_WCDR_2 0 0x9ce 8 0 4294967295 WPRE_INC_STEP 0 3 WPRE_MIN_THRESHOLD 4 8 DEBUG_0 9 9 DEBUG_1 10 10 DEBUG_2 11 11 DEBUG_3 12 12 DEBUG_4 13 13 DEBUG_5 14 14 mmMC_ARB_RTT_DATA 0 0x9cf 1 0 4294967295 PATTERN 0 7 mmMC_ARB_RTT_CNTL0 0 0x9d0 23 0 4294967295 ENABLE 0 0 START_IDLE 1 1 START_R2W 2 3 FLUSH_ON_ENTER 4 4 HARSH_START 5 5 TPS_HARSH_PRIORITY 6 6 TWRT_HARSH_PRIORITY 7 7 BREAK_ON_HARSH 8 8 BREAK_ON_URGENTRD 9 9 BREAK_ON_URGENTWR 10 10 TRAIN_PERIOD 11 13 START_R2W_RFSH 14 14 DEBUG_RSV_0 15 15 DEBUG_RSV_1 16 16 DEBUG_RSV_2 17 17 DEBUG_RSV_3 18 18 DEBUG_RSV_4 19 19 DEBUG_RSV_5 20 20 DEBUG_RSV_6 21 21 DEBUG_RSV_7 22 22 DEBUG_RSV_8 23 23 DATA_CNTL 24 24 NEIGHBOR_BIT 25 25 mmMC_ARB_RTT_CNTL1 0 0x9d1 7 0 4294967295 WINDOW_SIZE 0 4 WINDOW_UPDATE 5 5 WINDOW_INC_THRESHOLD 6 12 WINDOW_DEC_THRESHOLD 13 19 WINDOW_SIZE_MAX 20 24 WINDOW_SIZE_MIN 25 29 WINDOW_UPDATE_COUNT 30 31 mmMC_ARB_RTT_CNTL2 0 0x9d2 4 0 4294967295 SAMPLE_CNT 0 5 PHASE_ADJUST_THRESHOLD 6 11 PHASE_ADJUST_SIZE 12 12 FILTER_CNTL 13 13 mmMC_ARB_RTT_DEBUG 0 0x9d3 6 0 4294967295 DEBUG_BYTE_CH0 0 1 DEBUG_BYTE_CH1 2 3 SHIFTED_PHASE_CH0 4 11 WINDOW_SIZE_CH0 12 16 SHIFTED_PHASE_CH1 17 24 WINDOW_SIZE_CH1 25 29 mmMC_ARB_CAC_CNTL 0 0x9d4 4 0 4294967295 ENABLE 0 0 READ_WEIGHT 1 6 WRITE_WEIGHT 7 12 ALLOW_OVERFLOW 13 13 mmMC_ARB_MISC2 0 0x9d5 19 0 4294967295 TCCDL4_BANKBIT3_XOR_ENABLE 5 5 TCCDL4_BANKBIT3_XOR_COLBIT4 6 6 TCCDL4_BANKBIT3_XOR_COLBIT5 7 7 TCCDL4_BANKBIT3_XOR_COLBIT6 8 8 TCCDL4_BANKBIT3_XOR_COLBIT7 9 9 TCCDL4_BANKBIT3_XOR_COLBIT8 10 10 POP_IDLE_REPLAY 11 11 RDRET_NO_REORDERING 12 12 RDRET_NO_BP 13 13 RDRET_SEQ_SKID 14 17 GECC 18 18 GECC_RST 19 19 GECC_STATUS 20 20 TAGFIFO_THRESHOLD 21 24 WCDR_REPLAY_MASKCNT 25 27 REPLAY_DEBUG 28 28 ARB_DEBUG29 29 29 SEQ_RDY_POP_IDLE 30 30 TCCDL4_REPLAY_EOB 31 31 mmMC_ARB_MISC 0 0x9d6 14 0 4294967295 STICKY_RFSH 0 0 IDLE_RFSH 1 1 STUTTER_RFSH 2 2 CHAN_COUPLE 3 10 HARSHNESS 11 18 SMART_RDWR_SW 19 19 CALI_ENABLE 20 20 CALI_RATES 21 22 DISPURGVLD_NOWRT 23 23 DISPURG_NOSW2WR 24 24 DISPURG_STALL 25 25 DISPURG_THROTTLE 26 29 EXTEND_WEIGHT 30 30 ACPURG_STALL 31 31 mmMC_ARB_BANKMAP 0 0x9d7 5 0 4294967295 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 RANK 16 19 mmMC_ARB_RAMCFG 0 0x9d8 10 0 4294967295 NOOFBANK 0 1 NOOFRANKS 2 2 NOOFROWS 3 5 NOOFCOLS 6 7 CHANSIZE 8 8 RSV_1 9 9 RSV_2 10 10 RSV_3 11 11 NOOFGROUPS 12 12 RSV_4 13 17 mmMC_ARB_POP 0 0x9d9 9 0 4294967295 ENABLE_ARB 0 0 SPEC_OPEN 1 1 POP_DEPTH 2 5 WRDATAINDEX_DEPTH 6 11 SKID_DEPTH 12 14 WAIT_AFTER_RFSH 15 16 QUICK_STOP 17 17 ENABLE_TWO_PAGE 18 18 ALLOW_EOB_BY_WRRET_STALL 19 19 mmMC_ARB_MINCLKS 0 0x9da 4 0 4294967295 READ_CLKS 0 7 WRITE_CLKS 8 15 ARB_RW_SWITCH 16 16 RW_SWITCH_HARSH 17 18 mmMC_ARB_SQM_CNTL 0 0x9db 6 0 4294967295 MIN_PENAL 0 7 DYN_SQM_ENABLE 8 8 SQM_RDY16 9 9 SQM_RESERVE 10 15 RATIO 16 23 RATIO_DEBUG 24 31 mmMC_ARB_ADDR_HASH 0 0x9dc 3 0 4294967295 BANK_XOR_ENABLE 0 3 COL_XOR 4 11 ROW_XOR 12 27 mmMC_ARB_DRAM_TIMING 0 0x9dd 4 0 4294967295 ACTRD 0 7 ACTWR 8 15 RASMACTRD 16 23 RASMACTWR 24 31 mmMC_ARB_DRAM_TIMING2 0 0x9de 4 0 4294967295 RAS2RAS 0 7 RP 8 15 WRPLUSRP 16 23 BUS_TURN 24 28 mmMC_ARB_WTM_CNTL_RD 0 0x9df 13 0 4294967295 WTMODE 0 1 HARSH_PRI 2 2 ALLOW_STUTTER_GRP0 3 3 ALLOW_STUTTER_GRP1 4 4 ALLOW_STUTTER_GRP2 5 5 ALLOW_STUTTER_GRP3 6 6 ALLOW_STUTTER_GRP4 7 7 ALLOW_STUTTER_GRP5 8 8 ALLOW_STUTTER_GRP6 9 9 ALLOW_STUTTER_GRP7 10 10 ACP_HARSH_PRI 11 11 ACP_OVER_DISP 12 12 FORCE_ACP_URG 13 13 mmMC_ARB_WTM_CNTL_WR 0 0x9e0 13 0 4294967295 WTMODE 0 1 HARSH_PRI 2 2 ALLOW_STUTTER_GRP0 3 3 ALLOW_STUTTER_GRP1 4 4 ALLOW_STUTTER_GRP2 5 5 ALLOW_STUTTER_GRP3 6 6 ALLOW_STUTTER_GRP4 7 7 ALLOW_STUTTER_GRP5 8 8 ALLOW_STUTTER_GRP6 9 9 ALLOW_STUTTER_GRP7 10 10 ACP_HARSH_PRI 11 11 ACP_OVER_DISP 12 12 FORCE_ACP_URG 13 13 mmMC_ARB_WTM_GRPWT_RD 0 0x9e1 9 0 4294967295 GRP0 0 1 GRP1 2 3 GRP2 4 5 GRP3 6 7 GRP4 8 9 GRP5 10 11 GRP6 12 13 GRP7 14 15 GRP_EXT 16 23 mmMC_ARB_WTM_GRPWT_WR 0 0x9e2 9 0 4294967295 GRP0 0 1 GRP1 2 3 GRP2 4 5 GRP3 6 7 GRP4 8 9 GRP5 10 11 GRP6 12 13 GRP7 14 15 GRP_EXT 16 23 mmMC_ARB_TM_CNTL_RD 0 0x9e3 4 0 4294967295 GROUPBY_RANK 0 0 BANK_SELECT 1 2 MATCH_RANK 3 3 MATCH_BANK 4 4 mmMC_ARB_TM_CNTL_WR 0 0x9e4 4 0 4294967295 GROUPBY_RANK 0 0 BANK_SELECT 1 2 MATCH_RANK 3 3 MATCH_BANK 4 4 mmMC_ARB_LAZY0_RD 0 0x9e5 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_LAZY0_WR 0 0x9e6 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_LAZY1_RD 0 0x9e7 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_LAZY1_WR 0 0x9e8 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_AGE_RD 0 0x9e9 24 0 4294967295 RATE_GROUP0 0 1 RATE_GROUP1 2 3 RATE_GROUP2 4 5 RATE_GROUP3 6 7 RATE_GROUP4 8 9 RATE_GROUP5 10 11 RATE_GROUP6 12 13 RATE_GROUP7 14 15 ENABLE_GROUP0 16 16 ENABLE_GROUP1 17 17 ENABLE_GROUP2 18 18 ENABLE_GROUP3 19 19 ENABLE_GROUP4 20 20 ENABLE_GROUP5 21 21 ENABLE_GROUP6 22 22 ENABLE_GROUP7 23 23 DIVIDE_GROUP0 24 24 DIVIDE_GROUP1 25 25 DIVIDE_GROUP2 26 26 DIVIDE_GROUP3 27 27 DIVIDE_GROUP4 28 28 DIVIDE_GROUP5 29 29 DIVIDE_GROUP6 30 30 DIVIDE_GROUP7 31 31 mmMC_ARB_AGE_WR 0 0x9ea 24 0 4294967295 RATE_GROUP0 0 1 RATE_GROUP1 2 3 RATE_GROUP2 4 5 RATE_GROUP3 6 7 RATE_GROUP4 8 9 RATE_GROUP5 10 11 RATE_GROUP6 12 13 RATE_GROUP7 14 15 ENABLE_GROUP0 16 16 ENABLE_GROUP1 17 17 ENABLE_GROUP2 18 18 ENABLE_GROUP3 19 19 ENABLE_GROUP4 20 20 ENABLE_GROUP5 21 21 ENABLE_GROUP6 22 22 ENABLE_GROUP7 23 23 DIVIDE_GROUP0 24 24 DIVIDE_GROUP1 25 25 DIVIDE_GROUP2 26 26 DIVIDE_GROUP3 27 27 DIVIDE_GROUP4 28 28 DIVIDE_GROUP5 29 29 DIVIDE_GROUP6 30 30 DIVIDE_GROUP7 31 31 mmMC_ARB_RFSH_CNTL 0 0x9eb 4 0 4294967295 ENABLE 0 0 URG0 1 5 URG1 6 10 ACCUM 11 11 mmMC_ARB_RFSH_RATE 0 0x9ec 1 0 4294967295 POWERMODE0 0 7 mmMC_ARB_PM_CNTL 0 0x9ed 20 0 4294967295 OVERRIDE_CGSTATE 0 1 OVRR_CGRFSH 2 2 OVRR_CGSQM 3 3 SRFSH_ON_D1 4 4 BLKOUT_ON_D1 5 5 IDLE_ON_D1 6 6 OVRR_PM 7 7 OVRR_PM_STATE 8 9 OVRR_RD 10 10 OVRR_RD_STATE 11 11 OVRR_WR 12 12 OVRR_WR_STATE 13 13 OVRR_RFSH 14 14 OVRR_RFSH_STATE 15 15 RSV_0 16 17 IDLE_ON_D2 18 18 IDLE_ON_D3 19 19 IDLE_CNT 20 23 RSV_1 24 24 RSV_2 25 25 mmMC_ARB_GDEC_RD_CNTL 0 0x9ee 5 0 4294967295 PAGEBIT0 0 3 PAGEBIT1 4 7 USE_RANK 8 8 USE_RSNO 9 9 REM_DEFAULT_GRP 10 13 mmMC_ARB_GDEC_WR_CNTL 0 0x9ef 5 0 4294967295 PAGEBIT0 0 3 PAGEBIT1 4 7 USE_RANK 8 8 USE_RSNO 9 9 REM_DEFAULT_GRP 10 13 mmMC_ARB_LM_RD 0 0x9f0 8 0 4294967295 STREAK_LIMIT 0 7 STREAK_LIMIT_UBER 8 15 STREAK_BREAK 16 16 STREAK_UBER 17 17 ENABLE_TWO_LIST 18 18 POPIDLE_RST_TWOLIST 19 19 SKID1_RST_TWOLIST 20 20 BANKGROUP_CONFIG 21 23 mmMC_ARB_LM_WR 0 0x9f1 8 0 4294967295 STREAK_LIMIT 0 7 STREAK_LIMIT_UBER 8 15 STREAK_BREAK 16 16 STREAK_UBER 17 17 ENABLE_TWO_LIST 18 18 POPIDLE_RST_TWOLIST 19 19 SKID1_RST_TWOLIST 20 20 BANKGROUP_CONFIG 21 23 mmMC_ARB_REMREQ 0 0x9f2 5 0 4294967295 RD_WATER 0 7 WR_WATER 8 15 WR_MAXBURST_SIZE 16 19 WR_LAZY_TIMER 20 23 ENABLE_REMOTE_NACK_REQ 24 24 mmMC_ARB_REPLAY 0 0x9f3 10 0 4294967295 ENABLE_RD 0 0 ENABLE_WR 1 1 WRACK_MODE 2 2 WAW_ENABLE 3 3 RAW_ENABLE 4 4 IGNORE_WR_CDC 5 5 BREAK_ON_STALL 6 6 BOS_ENABLE_WAIT_CYC 7 7 BOS_WAIT_CYC 8 14 NO_PCH_AT_REPLAY_START 15 15 mmMC_ARB_RET_CREDITS_RD 0 0x9f4 4 0 4294967295 LCL 0 7 HUB 8 15 DISP 16 23 RETURN_CREDIT 24 31 mmMC_ARB_RET_CREDITS_WR 0 0x9f5 4 0 4294967295 LCL 0 7 HUB 8 15 RETURN_CREDIT 16 23 WRRET_SEQ_SKID 24 27 mmMC_ARB_MAX_LAT_CID 0 0x9f6 6 0 4294967295 CID_CH0 0 7 CID_CH1 8 15 WRITE_CH0 16 16 WRITE_CH1 17 17 REALTIME_CH0 18 18 REALTIME_CH1 19 19 mmMC_ARB_MAX_LAT_RSLT0 0 0x9f7 1 0 4294967295 MAX_LATENCY 0 31 mmMC_ARB_MAX_LAT_RSLT1 0 0x9f8 1 0 4294967295 MAX_LATENCY 0 31 mmMC_ARB_SSM 0 0x9f9 1 0 4294967295 FORMAT 0 4 mmMC_ARB_CG 0 0x9fa 4 0 4294967295 CG_ARB_REQ 0 7 CG_ARB_RESP 8 15 RSV_0 16 23 RSV_1 24 31 mmMC_ARB_WCDR 0 0x9fb 14 0 4294967295 IDLE_ENABLE 0 0 SEQ_IDLE 1 1 IDLE_PERIOD 2 6 IDLE_BURST 7 12 IDLE_BURST_MODE 13 13 IDLE_WAKEUP 14 15 IDLE_DEGLITCH_ENABLE 16 16 WPRE_ENABLE 17 17 WPRE_THRESHOLD 18 21 WPRE_MAX_BURST 22 24 WPRE_INC_READ 25 25 WPRE_INC_SKIDIDLE 26 26 WPRE_INC_SEQIDLE 27 27 WPRE_TWOPAGE 28 28 mmMC_ARB_DRAM_TIMING_1 0 0x9fc 4 0 4294967295 ACTRD 0 7 ACTWR 8 15 RASMACTRD 16 23 RASMACTWR 24 31 mmMC_ARB_BUSY_STATUS 0 0x9fd 32 0 4294967295 LM_RD0 0 0 LM_RD1 1 1 LM_WR0 2 2 LM_WR1 3 3 HM_RD0 4 4 HM_RD1 5 5 HM_WR0 6 6 HM_WR1 7 7 WDE_RD0 8 8 WDE_RD1 9 9 WDE_WR0 10 10 WDE_WR1 11 11 POP0 12 12 POP1 13 13 TAGFIFO0 14 14 TAGFIFO1 15 15 REPLAY0 16 16 REPLAY1 17 17 RDRET0 18 18 RDRET1 19 19 GECC2_RD0 20 20 GECC2_RD1 21 21 GECC2_WR0 22 22 GECC2_WR1 23 23 WCDR0 24 24 WCDR1 25 25 RTT0 26 26 RTT1 27 27 REM_RD0 28 28 REM_RD1 29 29 REM_WR0 30 30 REM_WR1 31 31 mmMC_ARB_DRAM_TIMING2_1 0 0x9ff 4 0 4294967295 RAS2RAS 0 7 RP 8 15 WRPLUSRP 16 23 BUS_TURN 24 28 mmMC_ARB_BURST_TIME 0 0xa02 4 0 4294967295 STATE0 0 4 STATE1 5 9 STATE2 10 14 STATE3 15 19 mmMC_CITF_XTRA_ENABLE 0 0x96d 18 0 4294967295 CB1_RD 0 0 CB1_WR 1 1 DB1_RD 2 2 DB1_WR 3 3 TC2_RD 4 4 ARB_DBG 8 11 TC2_WR 12 12 CB0_CONNECT_CNTL 13 14 DB0_CONNECT_CNTL 15 16 CB1_CONNECT_CNTL 17 18 DB1_CONNECT_CNTL 19 20 TC0_CONNECT_CNTL 21 22 TC1_CONNECT_CNTL 23 24 CB0_CID_CNTL_ENABLE 25 25 DB0_CID_CNTL_ENABLE 26 26 CB1_CID_CNTL_ENABLE 27 27 DB1_CID_CNTL_ENABLE 28 28 TC2_REPAIR_ENABLE 29 30 mmCC_MC_MAX_CHANNEL 0 0x96e 1 0 4294967295 NOOFCHAN 1 4 mmMC_CG_CONFIG 0 0x96f 6 0 4294967295 MCDW_WR_ENABLE 0 0 MCDX_WR_ENABLE 1 1 MCDY_WR_ENABLE 2 2 MCDZ_WR_ENABLE 3 3 MC_RD_ENABLE 4 5 INDEX 6 21 mmMC_CITF_CNTL 0 0x970 6 0 4294967295 IGNOREPM 2 2 EXEMPTPM 3 3 GFX_IDLE_OVERRIDE 4 5 MCD_SRBM_MASK_ENABLE 6 6 CNTR_CHMAP_MODE 7 7 REMOTE_RB_CONNECT_ENABLE 8 8 mmMC_CITF_CREDITS_VM 0 0x971 2 0 4294967295 READ_ALL 0 5 WRITE_ALL 6 11 mmMC_CITF_CREDITS_ARB_RD 0 0x972 5 0 4294967295 READ_LCL 0 7 READ_HUB 8 15 READ_PRI 16 23 LCL_PRI 24 24 HUB_PRI 25 25 mmMC_CITF_CREDITS_ARB_WR 0 0x973 4 0 4294967295 WRITE_LCL 0 7 WRITE_HUB 8 15 HUB_PRI 16 16 LCL_PRI 17 17 mmMC_CITF_DAGB_CNTL 0 0x974 4 0 4294967295 JUMP_AHEAD 0 0 CENTER_RD_MAX_BURST 1 4 DISABLE_SELF_INIT 5 5 CENTER_WR_MAX_BURST 6 9 mmMC_CITF_INT_CREDITS 0 0x975 4 0 4294967295 REMRDRET 0 5 CNTR_RD_HUB_LP 12 17 CNTR_RD_HUB_HP 18 23 CNTR_RD_LCL 24 29 mmMC_CITF_RET_MODE 0 0x976 6 0 4294967295 INORDER_RD 0 0 INORDER_WR 1 1 REMPRI_RD 2 2 REMPRI_WR 3 3 LCLPRI_RD 4 4 LCLPRI_WR 5 5 mmMC_CITF_DAGB_DLY 0 0x977 3 0 4294967295 DLY 0 4 CLI 16 20 POS 24 28 mmMC_RD_GRP_EXT 0 0x978 2 0 4294967295 DBSTEN0 0 3 TC0 4 7 mmMC_WR_GRP_EXT 0 0x979 2 0 4294967295 DBSTEN0 0 3 TC0 4 7 mmMC_CITF_REMREQ 0 0x97a 3 0 4294967295 READ_CREDITS 0 6 WRITE_CREDITS 7 13 CREDITS_ENABLE 14 14 mmMC_WR_TC0 0 0x97b 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_TC1 0 0x97c 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_CITF_INT_CREDITS_WR 0 0x97d 2 0 4294967295 CNTR_WR_HUB 0 5 CNTR_WR_LCL 6 11 mmMC_CITF_WTM_RD_CNTL 0 0x97f 10 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 DISABLE_REMOTE 24 24 DISABLE_LOCAL 25 25 mmMC_CITF_WTM_WR_CNTL 0 0x980 10 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 DISABLE_REMOTE 24 24 DISABLE_LOCAL 25 25 mmMC_RD_CB 0 0x981 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_DB 0 0x982 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_TC0 0 0x983 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_TC1 0 0x984 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_HUB 0 0x985 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_CB 0 0x986 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_DB 0 0x987 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_HUB 0 0x988 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_CITF_CREDITS_XBAR 0 0x989 2 0 4294967295 READ_LCL 0 7 WRITE_LCL 8 15 mmMC_RD_GRP_LCL 0 0x98a 5 0 4294967295 CB0 12 15 CBCMASK0 16 19 CBFMASK0 20 23 DB0 24 27 DBHTILE0 28 31 mmMC_WR_GRP_LCL 0 0x98b 7 0 4294967295 CB0 0 3 CBCMASK0 4 7 CBFMASK0 8 11 DB0 12 15 DBHTILE0 16 19 SX0 20 23 CBIMMED0 28 31 mmMC_CITF_PERF_MON_CNTL2 0 0x98e 1 0 4294967295 CID 0 7 mmMC_CITF_PERF_MON_RSLT2 0 0x991 13 0 4294967295 CB_RD_BUSY 6 6 DB_RD_BUSY 7 7 TC0_RD_BUSY 8 8 VC0_RD_BUSY 9 9 TC1_RD_BUSY 10 10 VC1_RD_BUSY 11 11 CB_WR_BUSY 12 12 DB_WR_BUSY 13 13 SX_WR_BUSY 14 14 TC2_RD_BUSY 15 15 TC0_WR_BUSY 16 16 TC1_WR_BUSY 17 17 TC2_WR_BUSY 18 18 mmMC_CITF_MISC_RD_CG 0 0x992 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_CITF_MISC_WR_CG 0 0x993 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_CITF_MISC_VM_CG 0 0x994 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_POWER 0 0x82d 2 0 4294967295 SRBM_GATE_OVERRIDE 2 2 PM_BLACKOUT_CNTL 3 4 mmMC_HUB_MISC_HUB_CG 0 0x82e 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_VM_CG 0 0x82f 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_SIP_CG 0 0x830 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_DBG 0 0x831 4 0 4294967295 SELECT0 0 3 SELECT1 4 7 CTRL0 8 12 CTRL1 13 17 mmMC_HUB_MISC_STATUS 0 0x832 14 0 4294967295 OUTSTANDING_READ 0 0 OUTSTANDING_WRITE 1 1 OUTSTANDING_HUB_RDREQ 2 2 OUTSTANDING_HUB_RDRET 3 3 OUTSTANDING_HUB_WRREQ 4 4 OUTSTANDING_HUB_WRRET 5 5 OUTSTANDING_RPB_READ 6 6 OUTSTANDING_RPB_WRITE 7 7 OUTSTANDING_MCD_READ 8 8 OUTSTANDING_MCD_WRITE 9 9 RPB_BUSY 10 10 WRITE_DEADLOCK_WARNING 11 11 READ_DEADLOCK_WARNING 12 12 GFX_BUSY 13 13 mmMC_HUB_MISC_OVERRIDE 0 0x833 1 0 4294967295 IDLE 0 1 mmMC_HUB_MISC_FRAMING 0 0x834 1 0 4294967295 BITS 0 31 mmMC_HUB_WDP_CNTL 0 0x835 13 0 4294967295 JUMPAHEAD_GBL0 1 1 JUMPAHEAD_GBL1 2 2 JUMPAHEAD_INTERNAL 3 3 OVERRIDE_STALL_ENABLE 4 4 DEBUG_REG 5 12 DISABLE_SELF_INIT_GBL0 13 13 DISABLE_SELF_INIT_GBL1 14 14 DISABLE_SELF_INIT_INTERNAL 15 15 FAIR_CH_SW 16 16 LCLWRREQ_BYPASS 17 17 DISP_WAIT_EOP 18 18 MCD_WAIT_EOP 19 19 SIP_WAIT_EOP 20 20 mmMC_HUB_WDP_ERR 0 0x836 2 0 4294967295 MGPU1_TARG_SYS 0 0 MGPU2_TARG_SYS 1 1 mmMC_HUB_WDP_BP 0 0x837 3 0 4294967295 ENABLE 0 0 RDRET 1 17 WRREQ 18 29 mmMC_HUB_WDP_STATUS 0 0x838 11 0 4294967295 SIP_AVAIL 0 0 MCDW_RD_AVAIL 1 1 MCDX_RD_AVAIL 2 2 MCDY_RD_AVAIL 3 3 MCDZ_RD_AVAIL 4 4 GBL0_VM_FULL 5 5 GBL0_STOR_FULL 6 6 GBL0_BYPASS_STOR_FULL 7 7 GBL1_VM_FULL 8 8 GBL1_STOR_FULL 9 9 GBL1_BYPASS_STOR_FULL 10 10 mmMC_HUB_RDREQ_STATUS 0 0x839 12 0 4294967295 SIP_AVAIL 0 0 MCDW_RD_AVAIL 1 1 MCDX_RD_AVAIL 2 2 MCDY_RD_AVAIL 3 3 MCDZ_RD_AVAIL 4 4 GBL0_VM_FULL 5 5 GBL0_STOR_FULL 6 6 GBL0_BYPASS_STOR_FULL 7 7 GBL1_VM_FULL 8 8 GBL1_STOR_FULL 9 9 GBL1_BYPASS_STOR_FULL 10 10 PWRXPRESS_ERR 11 11 mmMC_HUB_WRRET_STATUS 0 0x83a 4 0 4294967295 MCDW_AVAIL 0 0 MCDX_AVAIL 1 1 MCDY_AVAIL 2 2 MCDZ_AVAIL 3 3 mmMC_HUB_RDREQ_CNTL 0 0x83b 14 0 4294967295 REMOTE_BLACKOUT 0 0 JUMPAHEAD_GBL0 2 2 JUMPAHEAD_GBL1 3 3 OVERRIDE_STALL_ENABLE 4 4 MCDW_STALL_MODE 5 5 MCDX_STALL_MODE 6 6 MCDY_STALL_MODE 7 7 MCDZ_STALL_MODE 8 8 BREAK_HDP_DEADLOCK 9 9 DEBUG_REG 10 16 DISABLE_SELF_INIT_GBL0 17 17 DISABLE_SELF_INIT_GBL1 18 18 PWRXPRESS_MODE 19 19 ACPG_HP_TO_MCD_OVERRIDE 20 20 mmMC_HUB_WRRET_CNTL 0 0x83c 6 0 4294967295 JUMPAHEAD 0 0 BP 1 20 BP_ENABLE 21 21 DEBUG_REG 22 29 DISABLE_SELF_INIT 30 30 FAIR_CH_SW 31 31 mmMC_HUB_RDREQ_WTM_CNTL 0 0x83d 8 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 mmMC_HUB_WDP_WTM_CNTL 0 0x83e 8 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 mmMC_HUB_WDP_CREDITS 0 0x83f 4 0 4294967295 VM0 0 7 VM1 8 15 STOR0 16 23 STOR1 24 31 mmMC_HUB_WDP_MGPU2 0 0x840 1 0 4294967295 CID2 0 7 mmMC_HUB_WDP_GBL0 0 0x841 4 0 4294967295 MAXBURST 0 3 LAZY_TIMER 4 7 STALL_THRESHOLD 8 15 STALL_MODE 16 16 mmMC_HUB_WDP_GBL1 0 0x842 4 0 4294967295 MAXBURST 0 3 LAZY_TIMER 4 7 STALL_THRESHOLD 8 15 STALL_MODE 16 16 mmMC_HUB_WDP_MGPU 0 0x843 5 0 4294967295 STOR 0 7 CID 8 15 MGPU_PRIORITY_TIME 16 22 ENABLE 23 23 OTH_PRIORITY_TIME 24 30 mmMC_HUB_RDREQ_CREDITS 0 0x844 4 0 4294967295 VM0 0 7 VM1 8 15 STOR0 16 23 STOR1 24 31 mmMC_HUB_RDREQ_CREDITS2 0 0x845 1 0 4294967295 STOR1_PRI 0 7 mmMC_HUB_SHARED_DAGB_DLY 0 0x846 3 0 4294967295 DLY 0 5 CLI 16 20 POS 24 28 mmMC_HUB_MISC_IDLE_STATUS 0 0x847 30 0 4294967295 OUTSTANDING_GFX_READ 0 0 OUTSTANDING_GFX_WRITE 1 1 OUTSTANDING_RLC_READ 2 2 OUTSTANDING_RLC_WRITE 3 3 OUTSTANDING_SDMA0_READ 4 4 OUTSTANDING_SDMA0_WRITE 5 5 OUTSTANDING_SDMA1_READ 6 6 OUTSTANDING_SDMA1_WRITE 7 7 OUTSTANDING_DISP_READ 8 8 OUTSTANDING_DISP_WRITE 9 9 OUTSTANDING_UVD_READ 10 10 OUTSTANDING_UVD_WRITE 11 11 OUTSTANDING_SMU_READ 12 12 OUTSTANDING_SMU_WRITE 13 13 OUTSTANDING_HDP_READ 14 14 OUTSTANDING_HDP_WRITE 15 15 OUTSTANDING_OTH_READ 16 16 OUTSTANDING_OTH_WRITE 17 17 OUTSTANDING_VMC_READ 18 18 OUTSTANDING_VMC_WRITE 19 19 OUTSTANDING_IA_READ 20 20 OUTSTANDING_IA_WRITE 21 21 OUTSTANDING_VCE_READ 22 22 OUTSTANDING_VCE_WRITE 23 23 OUTSTANDING_ACP_READ 24 24 OUTSTANDING_ACP_WRITE 25 25 OUTSTANDING_CP_READ 26 26 OUTSTANDING_CP_WRITE 27 27 OUTSTANDING_XDMA_READ 28 28 OUTSTANDING_XDMA_WRITE 29 29 mmMC_HUB_RDREQ_DMIF_LIMIT 0 0x848 2 0 4294967295 ENABLE 0 1 LIMIT_COUNT 2 6 mmMC_HUB_RDREQ_ACPG_LIMIT 0 0x849 2 0 4294967295 ENABLE 0 1 LIMIT_COUNT 2 6 mmMC_HUB_WDP_SH2 0 0x84d 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SH3 0 0x84e 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_IA0 0 0x84f 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_IA1 0 0x850 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_MCDW 0 0x851 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDX 0 0x852 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDY 0 0x853 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDZ 0 0x854 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_SIP 0 0x855 3 0 4294967295 ASK_CREDITS 0 6 DUMMY 7 7 DISPLAY_CREDITS 8 14 mmMC_HUB_RDREQ_GBL0 0 0x856 1 0 4294967295 STALL_THRESHOLD 0 7 mmMC_HUB_RDREQ_GBL1 0 0x857 1 0 4294967295 STALL_THRESHOLD 0 7 mmMC_HUB_RDREQ_SMU 0 0x858 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_CPG 0 0x859 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_SDMA0 0 0x85a 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_HDP 0 0x85b 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_SDMA1 0 0x85c 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_RLC 0 0x85d 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_SEM 0 0x85e 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_VCE 0 0x85f 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_UMC 0 0x860 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_UVD 0 0x861 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 mmMC_HUB_RDREQ_IA 0 0x862 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_DMIF 0 0x863 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_MCIF 0 0x864 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_VMC 0 0x865 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_VCEU 0 0x866 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_MCDW 0 0x867 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDX 0 0x868 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDY 0 0x869 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDZ 0 0x86a 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_SIP 0 0x86b 2 0 4294967295 STALL_MODE 0 1 ASK_CREDITS 2 8 mmMC_HUB_WDP_CPG 0 0x86c 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SDMA1 0 0x86d 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SH0 0 0x86e 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_MCIF 0 0x86f 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_VCE 0 0x870 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_XDP 0 0x871 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_IH 0 0x872 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_RLC 0 0x873 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SEM 0 0x874 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SMU 0 0x875 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SH1 0 0x876 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_UMC 0 0x877 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_UVD 0 0x878 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 mmMC_HUB_WDP_HDP 0 0x879 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_SDMA0 0 0x87a 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WRRET_MCDW 0 0x87b 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDX 0 0x87c 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDY 0 0x87d 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDZ 0 0x87e 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WDP_VCEU 0 0x87f 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_XDMAM 0 0x880 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_XDMA 0 0x881 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_XDMAM 0 0x882 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_ACPG 0 0x883 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_ACPO 0 0x884 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_SAM 0 0x885 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_ACPG 0 0x886 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ACPO 0 0x887 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_SAM 0 0x888 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_CPC 0 0x889 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_RDREQ_CPF 0 0x88a 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_CPC 0 0x88b 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_HUB_WDP_CPF 0 0x88c 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RPB_CONF 0 0x94d 3 0 4294967295 XPB_PCIE_ORDER 15 15 RPB_RD_PCIE_ORDER 16 16 RPB_WR_PCIE_ORDER 17 17 mmMC_RPB_IF_CONF 0 0x94e 2 0 4294967295 RPB_BIF_CREDITS 0 7 OUTSTANDING_WRRET_ASK 8 15 mmMC_RPB_DBG1 0 0x94f 3 0 4294967295 RPB_BIF_OUTSTANDING_RD 0 7 RPB_BIF_OUTSTANDING_RD_32B 8 19 DEBUG_BITS 20 31 mmMC_RPB_EFF_CNTL 0 0x950 2 0 4294967295 WR_LAZY_TIMER 0 7 RD_LAZY_TIMER 8 15 mmMC_RPB_ARB_CNTL 0 0x951 3 0 4294967295 WR_SWITCH_NUM 0 7 RD_SWITCH_NUM 8 15 ATC_SWITCH_NUM 16 23 mmMC_RPB_BIF_CNTL 0 0x952 2 0 4294967295 ARB_SWITCH_NUM 0 7 XPB_SWITCH_NUM 8 15 mmMC_RPB_WR_SWITCH_CNTL 0 0x953 4 0 4294967295 QUEUE0_SWITCH_NUM 0 7 QUEUE1_SWITCH_NUM 8 15 QUEUE2_SWITCH_NUM 16 23 QUEUE3_SWITCH_NUM 24 31 mmMC_RPB_WR_COMBINE_CNTL 0 0x954 4 0 4294967295 WC_ENABLE 0 0 WC_MAX_PACKET_SIZE 1 2 WC_FLUSH_TIMER 3 6 WC_ALIGN 7 7 mmMC_RPB_RD_SWITCH_CNTL 0 0x955 4 0 4294967295 QUEUE0_SWITCH_NUM 0 7 QUEUE1_SWITCH_NUM 8 15 QUEUE2_SWITCH_NUM 16 23 QUEUE3_SWITCH_NUM 24 31 mmMC_RPB_CID_QUEUE_WR 0 0x956 5 0 4294967295 CLIENT_ID 0 7 UPDATE_MODE 8 8 WRITE_QUEUE 9 10 READ_QUEUE 11 12 UPDATE 13 13 mmMC_RPB_CID_QUEUE_RD 0 0x957 3 0 4294967295 CLIENT_ID 0 7 WRITE_QUEUE 8 9 READ_QUEUE 10 11 mmMC_RPB_PERF_COUNTER_CNTL 0 0x958 9 0 4294967295 PERF_COUNTER_SELECT 0 1 CLEAR_SELECTED_PERF_COUNTER 2 2 CLEAR_ALL_PERF_COUNTERS 3 3 STOP_ON_COUNTER_SATURATION 4 4 ENABLE_PERF_COUNTERS 5 8 PERF_COUNTER_ASSIGN_0 9 13 PERF_COUNTER_ASSIGN_1 14 18 PERF_COUNTER_ASSIGN_2 19 23 PERF_COUNTER_ASSIGN_3 24 28 mmMC_RPB_PERF_COUNTER_STATUS 0 0x959 1 0 4294967295 PERFORMANCE_COUNTER_VALUE 0 31 mmMC_RPB_CID_QUEUE_EX 0 0x95a 2 0 4294967295 START 0 0 OFFSET 1 5 mmMC_RPB_CID_QUEUE_EX_DATA 0 0x95b 2 0 4294967295 WRITE_ENTRIES 0 15 READ_ENTRIES 16 31 mmMC_SHARED_CHMAP 0 0x801 4 0 4294967295 CHAN0 0 3 CHAN1 4 7 CHAN2 8 11 NOOFCHAN 12 15 mmMC_SHARED_CHREMAP 0 0x802 8 0 4294967295 CHAN0 0 2 CHAN1 3 5 CHAN2 6 8 CHAN3 9 11 CHAN4 12 14 CHAN5 15 17 CHAN6 18 20 CHAN7 21 23 mmMC_RD_GRP_GFX 0 0x803 6 0 4294967295 CP 0 3 SH 4 7 IA 8 11 ACPG 12 15 ACPO 16 19 XDMAM 20 23 mmMC_WR_GRP_GFX 0 0x804 6 0 4294967295 CP 0 3 SH 4 7 ACPG 8 11 ACPO 12 15 XDMA 16 19 XDMAM 20 23 mmMC_RD_GRP_SYS 0 0x805 8 0 4294967295 RLC 0 3 VMC 4 7 SDMA1 8 11 DMIF 12 15 MCIF 16 19 SMU 20 23 VCE 24 27 VCEU 28 31 mmMC_WR_GRP_SYS 0 0x806 8 0 4294967295 IH 0 3 MCIF 4 7 RLC 8 11 SAM 12 15 SMU 16 19 SDMA1 20 23 VCE 24 27 VCEU 28 31 mmMC_RD_GRP_OTH 0 0x807 8 0 4294967295 UVD_EXT0 0 3 SDMA0 4 7 HDP 8 11 SEM 12 15 UMC 16 19 UVD 20 23 UVD_EXT1 24 27 SAM 28 31 mmMC_WR_GRP_OTH 0 0x808 8 0 4294967295 UVD_EXT0 0 3 SDMA0 4 7 HDP 8 11 SEM 12 15 UMC 16 19 UVD 20 23 XDP 24 27 UVD_EXT1 28 31 mmMC_VM_FB_LOCATION 0 0x809 2 0 4294967295 FB_BASE 0 15 FB_TOP 16 31 mmMC_VM_AGP_TOP 0 0x80a 1 0 4294967295 AGP_TOP 0 17 mmMC_VM_AGP_BOT 0 0x80b 1 0 4294967295 AGP_BOT 0 17 mmMC_VM_AGP_BASE 0 0x80c 1 0 4294967295 AGP_BASE 0 17 mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x80d 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x80e 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0 0x80f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmMC_VM_DC_WRITE_CNTL 0 0x810 6 0 4294967295 DC_WRITE_HIT_REGION_0_MODE 0 1 DC_WRITE_HIT_REGION_1_MODE 2 3 DC_WRITE_HIT_REGION_2_MODE 4 5 DC_WRITE_HIT_REGION_3_MODE 6 7 DC_MEMORY_WRITE_LOCAL 8 8 DC_MEMORY_WRITE_SYSTEM 9 9 mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0 0x811 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0 0x812 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0 0x813 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0 0x814 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0 0x815 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0 0x816 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0 0x817 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0 0x818 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_MX_L1_TLB_CNTL 0 0x819 6 0 4294967295 ENABLE_L1_TLB 0 0 ENABLE_L1_FRAGMENT_PROCESSING 1 1 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 mmMC_VM_FB_OFFSET 0 0x81a 1 0 4294967295 FB_OFFSET 0 17 mmMC_VM_STEERING 0 0x81b 1 0 4294967295 DEFAULT_STEERING 0 1 mmMC_CONFIG_MCD 0 0x828 8 0 4294967295 MCD0_WR_ENABLE 0 0 MCD1_WR_ENABLE 1 1 MCD2_WR_ENABLE 2 2 MCD3_WR_ENABLE 3 3 MCD4_WR_ENABLE 4 4 MCD5_WR_ENABLE 5 5 MC_RD_ENABLE 8 10 MCD_INDEX_MODE_ENABLE 31 31 mmMC_CG_CONFIG_MCD 0 0x829 8 0 4294967295 MCD0_WR_ENABLE 0 0 MCD1_WR_ENABLE 1 1 MCD2_WR_ENABLE 2 2 MCD3_WR_ENABLE 3 3 MCD4_WR_ENABLE 4 4 MCD5_WR_ENABLE 5 5 MC_RD_ENABLE 8 10 INDEX 13 28 mmMC_MEM_POWER_LS 0 0x82a 2 0 4294967295 LS_SETUP 0 5 LS_HOLD 6 11 mmMC_SHARED_BLACKOUT_CNTL 0 0x82b 1 0 4294967295 BLACKOUT_MODE 0 2 mmMC_VM_MB_L1_TLB0_DEBUG 0 0x891 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB2_DEBUG 0 0x893 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB0_STATUS 0 0x895 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L1_TLB1_STATUS 0 0x896 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L1_TLB2_STATUS 0 0x897 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L2ARBITER_L2_CREDITS 0 0x8a1 1 0 4294967295 L2_IF_CREDITS 0 5 mmMC_VM_MB_L1_TLB3_DEBUG 0 0x8a5 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB3_STATUS 0 0x8a6 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB0_DEBUG 0 0x998 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB1_DEBUG 0 0x999 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB2_DEBUG 0 0x99a 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB0_STATUS 0 0x99b 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB1_STATUS 0 0x99c 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB2_STATUS 0 0x99d 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L2ARBITER_L2_CREDITS 0 0x9a4 1 0 4294967295 L2_IF_CREDITS 0 5 mmMC_VM_MD_L1_TLB3_DEBUG 0 0x9a7 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB3_STATUS 0 0x9a8 1 0 4294967295 BUSY 0 0 mmMC_XPB_RTR_SRC_APRTR0 0 0x8cd 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR1 0 0x8ce 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR2 0 0x8cf 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR3 0 0x8d0 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR4 0 0x8d1 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR5 0 0x8d2 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR6 0 0x8d3 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR7 0 0x8d4 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR8 0 0x8d5 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR9 0 0x8d6 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR0 0 0x8d7 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR1 0 0x8d8 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR2 0 0x8d9 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR3 0 0x8da 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_DEST_MAP0 0 0x8db 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP1 0 0x8dc 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP2 0 0x8dd 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP3 0 0x8de 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP4 0 0x8df 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP5 0 0x8e0 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP6 0 0x8e1 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP7 0 0x8e2 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP8 0 0x8e3 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP9 0 0x8e4 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP0 0 0x8e5 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP1 0 0x8e6 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP2 0 0x8e7 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP3 0 0x8e8 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_CLG_CFG0 0 0x8e9 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG1 0 0x8ea 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG2 0 0x8eb 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG3 0 0x8ec 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG4 0 0x8ed 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG5 0 0x8ee 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG6 0 0x8ef 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG7 0 0x8f0 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG8 0 0x8f1 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG9 0 0x8f2 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG10 0 0x8f3 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG11 0 0x8f4 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG12 0 0x8f5 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG13 0 0x8f6 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG14 0 0x8f7 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG15 0 0x8f8 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG16 0 0x8f9 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG17 0 0x8fa 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG18 0 0x8fb 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG19 0 0x8fc 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_EXTRA 0 0x8fd 5 0 4294967295 CMP0 0 7 MSK0 8 15 VLD0 16 16 CMP1 17 24 VLD1 25 25 mmMC_XPB_LB_ADDR 0 0x8fe 4 0 4294967295 CMP0 0 9 MASK0 10 19 CMP1 20 25 MASK1 26 31 mmMC_XPB_UNC_THRESH_HST 0 0x8ff 3 0 4294967295 CHANGE_PREF 0 5 STRONG_PREF 6 11 USE_UNFULL 12 17 mmMC_XPB_UNC_THRESH_SID 0 0x900 3 0 4294967295 CHANGE_PREF 0 5 STRONG_PREF 6 11 USE_UNFULL 12 17 mmMC_XPB_WCB_STS 0 0x901 3 0 4294967295 PBUF_VLD 0 15 WCB_HST_DATA_BUF_CNT 16 22 WCB_SID_DATA_BUF_CNT 23 29 mmMC_XPB_WCB_CFG 0 0x902 3 0 4294967295 TIMEOUT 0 15 HST_MAX 16 17 SID_MAX 18 19 mmMC_XPB_P2P_BAR_CFG 0 0x903 9 0 4294967295 ADDR_SIZE 0 3 SEND_BAR 4 5 SNOOP 6 6 SEND_DIS 7 7 COMPRESS_DIS 8 8 UPDATE_DIS 9 9 REGBAR_FROM_SYSBAR 10 10 RD_EN 11 11 ATC_TRANSLATED 12 12 mmMC_XPB_P2P_BAR0 0 0x904 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR1 0 0x905 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR2 0 0x906 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR3 0 0x907 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR4 0 0x908 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR5 0 0x909 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR6 0 0x90a 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR7 0 0x90b 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR_SETUP 0 0x90c 7 0 4294967295 SEL 0 7 REG_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR_DEBUG 0 0x90d 3 0 4294967295 SEL 0 7 HOST_FLUSH 8 11 MEM_SYS_BAR 12 15 mmMC_XPB_P2P_BAR_DELTA_ABOVE 0 0x90e 2 0 4294967295 EN 0 7 DELTA 8 27 mmMC_XPB_P2P_BAR_DELTA_BELOW 0 0x90f 2 0 4294967295 EN 0 7 DELTA 8 27 mmMC_XPB_PEER_SYS_BAR0 0 0x910 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR1 0 0x911 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR2 0 0x912 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR3 0 0x913 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR4 0 0x914 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR5 0 0x915 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR6 0 0x916 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR7 0 0x917 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR8 0 0x918 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR9 0 0x919 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR0 0 0x91a 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR1 0 0x91b 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR2 0 0x91c 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR3 0 0x91d 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_CLK_GAT 0 0x91e 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_XPB_INTF_CFG 0 0x91f 11 0 4294967295 RPB_WRREQ_CRD 0 7 MC_WRRET_ASK 8 15 XSP_REQ_CRD 16 22 BIF_REG_SNOOP_SEL 23 23 BIF_REG_SNOOP_VAL 24 24 BIF_MEM_SNOOP_SEL 25 25 BIF_MEM_SNOOP_VAL 26 26 XSP_SNOOP_SEL 27 28 XSP_SNOOP_VAL 29 29 XSP_ORDERING_SEL 30 30 XSP_ORDERING_VAL 31 31 mmMC_XPB_INTF_STS 0 0x920 7 0 4294967295 RPB_WRREQ_CRD 0 7 XSP_REQ_CRD 8 14 HOP_DATA_BUF_FULL 15 15 HOP_ATTR_BUF_FULL 16 16 CNS_BUF_FULL 17 17 CNS_BUF_BUSY 18 18 RPB_RDREQ_CRD 19 26 mmMC_XPB_PIPE_STS 0 0x921 13 0 4294967295 WCB_ANY_PBUF 0 0 WCB_HST_DATA_BUF_CNT 1 7 WCB_SID_DATA_BUF_CNT 8 14 WCB_HST_RD_PTR_BUF_FULL 15 15 WCB_SID_RD_PTR_BUF_FULL 16 16 WCB_HST_REQ_FIFO_FULL 17 17 WCB_SID_REQ_FIFO_FULL 18 18 WCB_HST_REQ_OBUF_FULL 19 19 WCB_SID_REQ_OBUF_FULL 20 20 WCB_HST_DATA_OBUF_FULL 21 21 WCB_SID_DATA_OBUF_FULL 22 22 RET_BUF_FULL 23 23 XPB_CLK_BUSY_BITS 24 31 mmMC_XPB_SUB_CTRL 0 0x922 20 0 4294967295 WRREQ_BYPASS_XPB 0 0 STALL_CNS_RTR_REQ 1 1 STALL_RTR_RPB_WRREQ 2 2 STALL_RTR_MAP_REQ 3 3 STALL_MAP_WCB_REQ 4 4 STALL_WCB_SID_REQ 5 5 STALL_MC_XSP_REQ_SEND 6 6 STALL_WCB_HST_REQ 7 7 STALL_HST_HOP_REQ 8 8 STALL_XPB_RPB_REQ_ATTR 9 9 RESET_CNS 10 10 RESET_RTR 11 11 RESET_RET 12 12 RESET_MAP 13 13 RESET_WCB 14 14 RESET_HST 15 15 RESET_HOP 16 16 RESET_SID 17 17 RESET_SRB 18 18 RESET_CGR 19 19 mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0 0x923 1 0 4294967295 ALTER_FLUSH_NUM 0 15 mmMC_XPB_PERF_KNOBS 0 0x924 3 0 4294967295 CNS_FIFO_DEPTH 0 5 WCB_HST_FIFO_DEPTH 6 11 WCB_SID_FIFO_DEPTH 12 17 mmMC_XPB_STICKY 0 0x925 1 0 4294967295 BITS 0 31 mmMC_XPB_STICKY_W1C 0 0x926 1 0 4294967295 BITS 0 31 mmMC_XPB_MISC_CFG 0 0x927 5 0 4294967295 FIELDNAME0 0 7 FIELDNAME1 8 15 FIELDNAME2 16 23 FIELDNAME3 24 30 TRIGGERNAME 31 31 mmMC_XPB_CLG_CFG20 0 0x928 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG21 0 0x929 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG22 0 0x92a 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG23 0 0x92b 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG24 0 0x92c 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG25 0 0x92d 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG26 0 0x92e 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG27 0 0x92f 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG28 0 0x930 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG29 0 0x931 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG30 0 0x932 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG31 0 0x933 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_INTF_CFG2 0 0x934 1 0 4294967295 RPB_RDREQ_CRD 0 7 mmMC_XPB_CLG_EXTRA_RD 0 0x935 5 0 4294967295 CMP0 0 7 MSK0 8 15 VLD0 16 16 CMP1 17 24 VLD1 25 25 mmMC_XPB_CLG_CFG32 0 0x936 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG33 0 0x937 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG34 0 0x938 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG35 0 0x939 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG36 0 0x93a 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XBAR_ADDR_DEC 0 0xc80 4 0 4294967295 NO_DIV_BY_3 0 0 GECC 1 1 RB_SPLIT 2 2 RB_SPLIT_COLHI 3 3 mmMC_XBAR_REMOTE 0 0xc81 2 0 4294967295 WRREQ_EN_GOQ 0 0 RDREQ_EN_GOQ 1 1 mmMC_XBAR_WRREQ_CREDIT 0 0xc82 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDREQ_CREDIT 0 0xc83 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDREQ_PRI_CREDIT 0 0xc84 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_WRRET_CREDIT1 0 0xc85 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_WRRET_CREDIT2 0 0xc86 2 0 4294967295 OUT4 0 7 OUT5 8 15 mmMC_XBAR_RDRET_CREDIT1 0 0xc87 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDRET_CREDIT2 0 0xc88 3 0 4294967295 OUT4 0 7 OUT5 8 15 HUB_LP_RDRET_SKID 16 23 mmMC_XBAR_RDRET_PRI_CREDIT1 0 0xc89 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDRET_PRI_CREDIT2 0 0xc8a 2 0 4294967295 OUT4 0 7 OUT5 8 15 mmMC_XBAR_CHTRIREMAP 0 0xc8b 3 0 4294967295 CH0 0 1 CH1 2 3 CH2 4 5 mmMC_XBAR_TWOCHAN 0 0xc8c 3 0 4294967295 DISABLE_ONEPORT 0 0 CH0 1 2 CH1 3 4 mmMC_XBAR_ARB 0 0xc8d 3 0 4294967295 HUBRD_HIGHEST 0 0 DISABLE_HUB_STALL_HIGHEST 1 1 BREAK_BURST_CID_CHANGE 2 2 mmMC_XBAR_ARB_MAX_BURST 0 0xc8e 8 0 4294967295 RD_PORT0 0 3 RD_PORT1 4 7 RD_PORT2 8 11 RD_PORT3 12 15 WR_PORT0 16 19 WR_PORT1 20 23 WR_PORT2 24 27 WR_PORT3 28 31 mmMC_XBAR_PERF_MON_CNTL0 0 0xc8f 5 0 4294967295 START_THRESH 0 11 STOP_THRESH 12 23 START_MODE 24 25 STOP_MODE 26 27 ALLOW_WRAP 28 28 mmMC_XBAR_PERF_MON_CNTL1 0 0xc90 3 0 4294967295 THRESH_CNTR_ID 0 7 START_TRIG_ID 8 15 STOP_TRIG_ID 16 23 mmMC_XBAR_PERF_MON_CNTL2 0 0xc91 4 0 4294967295 MON0_ID 0 7 MON1_ID 8 15 MON2_ID 16 23 MON3_ID 24 31 mmMC_XBAR_PERF_MON_RSLT0 0 0xc92 1 0 4294967295 COUNT 0 31 mmMC_XBAR_PERF_MON_RSLT1 0 0xc93 1 0 4294967295 COUNT 0 31 mmMC_XBAR_PERF_MON_RSLT2 0 0xc94 1 0 4294967295 COUNT 0 31 mmMC_XBAR_PERF_MON_RSLT3 0 0xc95 1 0 4294967295 COUNT 0 31 mmMC_XBAR_PERF_MON_MAX_THSH 0 0xc96 4 0 4294967295 MON0 0 7 MON1 8 15 MON2 16 23 MON3 24 31 mmMC_XBAR_SPARE0 0 0xc97 1 0 4294967295 BIT 0 31 mmMC_XBAR_SPARE1 0 0xc98 1 0 4294967295 BIT 0 31 mmMC_CITF_PERFCOUNTER_LO 0 0x7a0 1 0 4294967295 COUNTER_LO 0 31 mmMC_HUB_PERFCOUNTER_LO 0 0x7a1 1 0 4294967295 COUNTER_LO 0 31 mmMC_RPB_PERFCOUNTER_LO 0 0x7a2 1 0 4294967295 COUNTER_LO 0 31 mmMC_MCBVM_PERFCOUNTER_LO 0 0x7a3 1 0 4294967295 COUNTER_LO 0 31 mmMC_MCDVM_PERFCOUNTER_LO 0 0x7a4 1 0 4294967295 COUNTER_LO 0 31 mmMC_VM_L2_PERFCOUNTER_LO 0 0x7a5 1 0 4294967295 COUNTER_LO 0 31 mmMC_ARB_PERFCOUNTER_LO 0 0x7a6 1 0 4294967295 COUNTER_LO 0 31 mmATC_PERFCOUNTER_LO 0 0x7a7 1 0 4294967295 COUNTER_LO 0 31 mmMC_CITF_PERFCOUNTER_HI 0 0x7a8 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_HUB_PERFCOUNTER_HI 0 0x7a9 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_MCBVM_PERFCOUNTER_HI 0 0x7aa 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_MCDVM_PERFCOUNTER_HI 0 0x7ab 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_RPB_PERFCOUNTER_HI 0 0x7ac 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_VM_L2_PERFCOUNTER_HI 0 0x7ad 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_ARB_PERFCOUNTER_HI 0 0x7ae 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATC_PERFCOUNTER_HI 0 0x7af 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_CITF_PERFCOUNTER0_CFG 0 0x7b0 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER1_CFG 0 0x7b1 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER2_CFG 0 0x7b2 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER3_CFG 0 0x7b3 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER0_CFG 0 0x7b4 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER1_CFG 0 0x7b5 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER2_CFG 0 0x7b6 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER3_CFG 0 0x7b7 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER0_CFG 0 0x7b8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER1_CFG 0 0x7b9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER2_CFG 0 0x7ba 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER3_CFG 0 0x7bb 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER0_CFG 0 0x7bc 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER1_CFG 0 0x7bd 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER2_CFG 0 0x7be 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER3_CFG 0 0x7bf 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER0_CFG 0 0x7c0 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER1_CFG 0 0x7c1 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER2_CFG 0 0x7c2 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER3_CFG 0 0x7c3 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER0_CFG 0 0x7c4 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER1_CFG 0 0x7c5 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER2_CFG 0 0x7c6 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER3_CFG 0 0x7c7 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER0_CFG 0 0x7c8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER1_CFG 0 0x7c9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER2_CFG 0 0x7ca 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER3_CFG 0 0x7cb 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER0_CFG 0 0x7cc 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER1_CFG 0 0x7cd 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0 0x7ce 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0 0x7cf 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0 0x7d0 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0 0x7d1 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0 0x7d2 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x7d3 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0 0x7d4 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmATC_PERFCOUNTER_RSLT_CNTL 0 0x7d5 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmCHUB_ATC_PERFCOUNTER_LO 0 0x7d6 1 0 4294967295 COUNTER_LO 0 31 mmCHUB_ATC_PERFCOUNTER_HI 0 0x7d7 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmCHUB_ATC_PERFCOUNTER0_CFG 0 0x7d8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmCHUB_ATC_PERFCOUNTER1_CFG 0 0x7d9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0 0x7da 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_ARB_PERF_MON_CNTL0_ECC 0 0x7db 1 0 4294967295 ALLOW_WRAP 0 0 mmATC_VM_APERTURE0_LOW_ADDR 0 0xcc0 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE1_LOW_ADDR 0 0xcc1 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE0_HIGH_ADDR 0 0xcc2 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE1_HIGH_ADDR 0 0xcc3 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE0_CNTL 0 0xcc4 1 0 4294967295 ATS_ACCESS_MODE 0 1 mmATC_VM_APERTURE1_CNTL 0 0xcc5 1 0 4294967295 ATS_ACCESS_MODE 0 1 mmATC_VM_APERTURE0_CNTL2 0 0xcc6 1 0 4294967295 VMIDS_USING_RANGE 0 15 mmATC_VM_APERTURE1_CNTL2 0 0xcc7 1 0 4294967295 VMIDS_USING_RANGE 0 15 mmATC_ATS_CNTL 0 0xcc9 5 0 4294967295 DISABLE_ATC 0 0 DISABLE_PRI 1 1 DISABLE_PASID 2 2 CREDITS_ATS_RPB 8 13 DEBUG_ECO 16 19 mmATC_ATS_DEBUG 0 0xcca 13 0 4294967295 INVALIDATE_ALL 0 0 IDENT_RETURN 1 1 ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS 2 2 PAGE_REQUESTS_USE_RELAXED_ORDERING 5 5 PRIV_BIT 6 6 EXE_BIT 7 7 PAGE_REQUEST_PERMS 8 8 UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE 9 9 NUM_REQUESTS_AT_ERR 10 13 DISALLOW_ERR_TO_DONE 14 14 IGNORE_FED 15 15 INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED 16 16 DEBUG_BUS_SELECT 17 17 mmATC_ATS_FAULT_DEBUG 0 0xccb 3 0 4294967295 CREDITS_ATS_IH 0 4 ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES 8 8 CLEAR_FAULT_STATUS_ADDR 16 16 mmATC_ATS_STATUS 0 0xccc 3 0 4294967295 BUSY 0 0 CRASHED 1 1 DEADLOCK_DETECTION 2 2 mmATC_ATS_FAULT_CNTL 0 0xccd 3 0 4294967295 FAULT_REGISTER_LOG 0 5 FAULT_INTERRUPT_TABLE 10 15 FAULT_CRASH_TABLE 20 25 mmATC_ATS_FAULT_STATUS_INFO 0 0xcce 8 0 4294967295 FAULT_TYPE 0 5 VMID 10 14 EXTRA_INFO 15 15 EXTRA_INFO2 16 16 INVALIDATION 17 17 PAGE_REQUEST 18 18 STATUS 19 23 PAGE_ADDR_HIGH 24 27 mmATC_ATS_FAULT_STATUS_ADDR 0 0xccf 1 0 4294967295 PAGE_ADDR 0 31 mmATC_ATS_DEFAULT_PAGE_LOW 0 0xcd0 1 0 4294967295 DEFAULT_PAGE 0 31 mmATC_ATS_DEFAULT_PAGE_CNTL 0 0xcd1 2 0 4294967295 SEND_DEFAULT_PAGE 0 0 DEFAULT_PAGE_HIGH 2 5 mmATC_MISC_CG 0 0xcd4 3 0 4294967295 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmATC_L2_CNTL 0 0xcd5 4 0 4294967295 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 4 5 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 8 8 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 9 9 mmATC_L2_CNTL2 0 0xcd6 6 0 4294967295 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 mmATC_L2_DEBUG 0 0xcd7 1 0 4294967295 CREDITS_L2_ATS 0 5 mmATC_L2_DEBUG2 0 0xcd8 10 0 4294967295 EFFECTIVE_CACHE_SIZE 0 4 EFFECTIVE_WORK_QUEUE_SIZE 5 7 FORCE_CACHE_MISS 8 8 INVALIDATE_ALL 9 9 DISABLE_INVALIDATE_PER_DOMAIN 10 10 DISABLE_CACHING_SPECULATIVE_READ_RETURNS 11 11 DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS 12 12 DISABLE_CACHING_FAULT_RETURNS 14 14 DEBUG_BUS_SELECT 15 16 DEBUG_ECO 17 18 mmATC_L1_CNTL 0 0xcdc 3 0 4294967295 DONT_NEED_ATS_BEHAVIOR 0 1 NEED_ATS_BEHAVIOR 2 2 NEED_ATS_SNOOP_DEFAULT 4 4 mmATC_L1_ADDRESS_OFFSET 0 0xcdd 1 0 4294967295 LOGICAL_ADDRESS 0 31 mmATC_L1RD_DEBUG_TLB 0 0xcde 9 0 4294967295 DISABLE_FRAGMENTS 0 0 DISABLE_INVALIDATE_BY_ADDRESS_RANGE 1 1 EFFECTIVE_CAM_SIZE 4 7 EFFECTIVE_WORK_QUEUE_SIZE 8 10 CREDITS_L1_L2 12 17 CREDITS_L1_RPB 20 27 DEBUG_ECO 28 29 INVALIDATE_ALL 30 30 DISABLE_CACHING_FAULT_RETURNS 31 31 mmATC_L1WR_DEBUG_TLB 0 0xcdf 9 0 4294967295 DISABLE_FRAGMENTS 0 0 DISABLE_INVALIDATE_BY_ADDRESS_RANGE 1 1 EFFECTIVE_CAM_SIZE 4 7 EFFECTIVE_WORK_QUEUE_SIZE 8 10 CREDITS_L1_L2 12 17 CREDITS_L1_RPB 20 27 DEBUG_ECO 28 29 INVALIDATE_ALL 30 30 DISABLE_CACHING_FAULT_RETURNS 31 31 mmATC_L1RD_STATUS 0 0xce0 3 0 4294967295 BUSY 0 0 DEADLOCK_DETECTION 1 1 BAD_NEED_ATS 8 8 mmATC_L1WR_STATUS 0 0xce1 3 0 4294967295 BUSY 0 0 DEADLOCK_DETECTION 1 1 BAD_NEED_ATS 8 8 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0 0xce6 16 0 4294967295 VMID0_REMAPPING_FINISHED 0 0 VMID1_REMAPPING_FINISHED 1 1 VMID2_REMAPPING_FINISHED 2 2 VMID3_REMAPPING_FINISHED 3 3 VMID4_REMAPPING_FINISHED 4 4 VMID5_REMAPPING_FINISHED 5 5 VMID6_REMAPPING_FINISHED 6 6 VMID7_REMAPPING_FINISHED 7 7 VMID8_REMAPPING_FINISHED 8 8 VMID9_REMAPPING_FINISHED 9 9 VMID10_REMAPPING_FINISHED 10 10 VMID11_REMAPPING_FINISHED 11 11 VMID12_REMAPPING_FINISHED 12 12 VMID13_REMAPPING_FINISHED 13 13 VMID14_REMAPPING_FINISHED 14 14 VMID15_REMAPPING_FINISHED 15 15 mmATC_VMID0_PASID_MAPPING 0 0xce7 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID1_PASID_MAPPING 0 0xce8 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID2_PASID_MAPPING 0 0xce9 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID3_PASID_MAPPING 0 0xcea 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID4_PASID_MAPPING 0 0xceb 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID5_PASID_MAPPING 0 0xcec 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID6_PASID_MAPPING 0 0xced 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID7_PASID_MAPPING 0 0xcee 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID8_PASID_MAPPING 0 0xcef 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID9_PASID_MAPPING 0 0xcf0 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID10_PASID_MAPPING 0 0xcf1 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID11_PASID_MAPPING 0 0xcf2 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID12_PASID_MAPPING 0 0xcf3 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID13_PASID_MAPPING 0 0xcf4 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID14_PASID_MAPPING 0 0xcf5 2 0 4294967295 PASID 0 15 VALID 31 31 mmATC_VMID15_PASID_MAPPING 0 0xcf6 2 0 4294967295 PASID 0 15 VALID 31 31 mmGMCON_RENG_RAM_INDEX 0 0xd40 1 0 4294967295 RENG_RAM_INDEX 0 9 mmGMCON_RENG_RAM_DATA 0 0xd41 1 0 4294967295 RENG_RAM_DATA 0 31 mmGMCON_RENG_EXECUTE 0 0xd42 5 0 4294967295 RENG_EXECUTE_ON_PWR_UP 0 0 RENG_EXECUTE_NOW 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_DSP_END_PTR 12 21 RENG_EXECUTE_END_PTR 22 31 mmGMCON_MISC 0 0xd43 15 0 4294967295 RENG_EXECUTE_NOW_MODE 10 10 RENG_EXECUTE_ON_REG_UPDATE 11 11 RENG_SRBM_CREDITS_MCD 12 15 STCTRL_STUTTER_EN 16 16 STCTRL_GMC_IDLE_THRESHOLD 17 18 STCTRL_SRBM_IDLE_THRESHOLD 19 20 STCTRL_IGNORE_PRE_SR 21 21 STCTRL_IGNORE_ALLOW_STOP 22 22 STCTRL_IGNORE_SR_COMMIT 23 23 STCTRL_IGNORE_PROTECTION_FAULT 24 24 STCTRL_DISABLE_ALLOW_SR 25 25 STCTRL_DISABLE_GMC_OFFLINE 26 26 CRITICAL_REGS_LOCK 27 27 ALLOW_DEEP_SLEEP_MODE 28 30 STCTRL_FORCE_ALLOW_SR 31 31 mmGMCON_MISC2 0 0xd44 8 0 4294967295 RENG_MEM_POWER_CTRL_OVERRIDE0 0 2 RENG_MEM_POWER_CTRL_OVERRIDE1 3 5 STCTRL_NONDISP_IDLE_THRESHOLD 6 10 RENG_SR_HOLD_THRESHOLD 11 16 STCTRL_LPT_TARGET 17 28 STCTRL_IGNORE_ARB_BUSY 29 29 STCTRL_EXTEND_GMC_OFFLINE 30 30 STCTRL_TIMER_PULSE_OVERRIDE 31 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0 0xd45 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE0 0 15 STCTRL_REGISTER_SAVE_LIMIT0 16 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0 0xd46 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE1 0 15 STCTRL_REGISTER_SAVE_LIMIT1 16 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0 0xd47 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE2 0 15 STCTRL_REGISTER_SAVE_LIMIT2 16 31 mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0xd48 2 0 4294967295 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0xd49 2 0 4294967295 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmGMCON_PERF_MON_CNTL0 0 0xd4a 5 0 4294967295 START_THRESH 0 11 STOP_THRESH 12 23 START_MODE 24 25 STOP_MODE 26 27 ALLOW_WRAP 28 28 mmGMCON_PERF_MON_CNTL1 0 0xd4b 5 0 4294967295 THRESH_CNTR_ID 0 5 START_TRIG_ID 6 11 STOP_TRIG_ID 12 17 MON0_ID 18 23 MON1_ID 24 29 mmGMCON_PERF_MON_RSLT0 0 0xd4c 1 0 4294967295 COUNT 0 31 mmGMCON_PERF_MON_RSLT1 0 0xd4d 1 0 4294967295 COUNT 0 31 mmGMCON_PGFSM_CONFIG 0 0xd4e 10 0 4294967295 FSM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE 12 12 READ 13 13 RSRVD 14 26 SRBM_OVERRIDE 27 27 REG_ADDR 28 31 mmGMCON_PGFSM_WRITE 0 0xd4f 1 0 4294967295 WRITE_VALUE 0 31 mmGMCON_PGFSM_READ 0 0xd50 3 0 4294967295 READ_VALUE 0 23 PGFSM_SELECT 24 27 SERDES_MASTER_BUSY 28 28 mmGMCON_MISC3 0 0xd51 6 0 4294967295 RENG_DISABLE_MCC 0 5 RENG_DISABLE_MCD 6 11 STCTRL_FORCE_PGFSM_CMD_DONE 12 23 STCTRL_IGNORE_ALLOW_STUTTER 24 24 RENG_MEM_LS_ENABLE 25 25 STCTRL_EXCLUDE_NONMEM_CLIENTS 26 26 mmGMCON_MASK 0 0xd52 5 0 4294967295 STCTRL_BUSY_MASK_ACP_RD 0 0 STCTRL_BUSY_MASK_ACP_WR 1 1 STCTRL_BUSY_MASK_VCE_RD 2 2 STCTRL_BUSY_MASK_VCE_WR 3 3 STCTRL_SR_HANDSHAKE_MASK 4 9 mmGMCON_DEBUG 0 0xd5f 3 0 4294967295 GFX_STALL 0 0 GFX_CLEAR 1 1 MISC_FLAGS 2 29 mmVM_L2_CNTL 0 0x500 15 0 4294967295 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_CACHE_4K_SWAP_TAG_INDEX_LSBS 26 27 L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS 28 30 mmVM_L2_CNTL2 0 0x501 7 0 4294967295 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_CACHE_BIGK_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmVM_L2_CNTL3 0 0x502 10 0 4294967295 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 mmVM_L2_STATUS 0 0x503 2 0 4294967295 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 mmVM_CONTEXT0_CNTL 0 0x504 22 0 4294967295 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 6 6 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 PDE0_PROTECTION_FAULT_ENABLE_SAVE 11 11 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 VALID_PROTECTION_FAULT_ENABLE_SAVE 14 14 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_SAVE 17 17 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 18 18 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 19 19 WRITE_PROTECTION_FAULT_ENABLE_SAVE 20 20 PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE 23 23 PAGE_TABLE_BLOCK_SIZE 24 27 mmVM_CONTEXT1_CNTL 0 0x505 22 0 4294967295 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 6 6 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 PDE0_PROTECTION_FAULT_ENABLE_SAVE 11 11 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 VALID_PROTECTION_FAULT_ENABLE_SAVE 14 14 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_SAVE 17 17 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 18 18 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 19 19 WRITE_PROTECTION_FAULT_ENABLE_SAVE 20 20 PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE 23 23 PAGE_TABLE_BLOCK_SIZE 24 27 mmVM_DUMMY_PAGE_FAULT_CNTL 0 0x506 3 0 4294967295 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MASK 2 3 mmVM_DUMMY_PAGE_FAULT_ADDR 0 0x507 1 0 4294967295 DUMMY_PAGE_ADDR 0 27 mmVM_CONTEXT0_CNTL2 0 0x50c 5 0 4294967295 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT 1 1 ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT 2 2 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 3 3 WAIT_FOR_IDLE_WHEN_INVALIDATE 4 4 mmVM_CONTEXT1_CNTL2 0 0x50d 5 0 4294967295 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT 1 1 ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT 2 2 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 3 3 WAIT_FOR_IDLE_WHEN_INVALIDATE 4 4 mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0 0x50e 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0 0x50f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0 0x510 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0 0x511 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0 0x512 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0 0x513 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0 0x514 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0 0x515 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_INVALIDATE_REQUEST 0 0x51e 16 0 4294967295 INVALIDATE_DOMAIN_0 0 0 INVALIDATE_DOMAIN_1 1 1 INVALIDATE_DOMAIN_2 2 2 INVALIDATE_DOMAIN_3 3 3 INVALIDATE_DOMAIN_4 4 4 INVALIDATE_DOMAIN_5 5 5 INVALIDATE_DOMAIN_6 6 6 INVALIDATE_DOMAIN_7 7 7 INVALIDATE_DOMAIN_8 8 8 INVALIDATE_DOMAIN_9 9 9 INVALIDATE_DOMAIN_10 10 10 INVALIDATE_DOMAIN_11 11 11 INVALIDATE_DOMAIN_12 12 12 INVALIDATE_DOMAIN_13 13 13 INVALIDATE_DOMAIN_14 14 14 INVALIDATE_DOMAIN_15 15 15 mmVM_INVALIDATE_RESPONSE 0 0x51f 16 0 4294967295 DOMAIN_INVALIDATED_0 0 0 DOMAIN_INVALIDATED_1 1 1 DOMAIN_INVALIDATED_2 2 2 DOMAIN_INVALIDATED_3 3 3 DOMAIN_INVALIDATED_4 4 4 DOMAIN_INVALIDATED_5 5 5 DOMAIN_INVALIDATED_6 6 6 DOMAIN_INVALIDATED_7 7 7 DOMAIN_INVALIDATED_8 8 8 DOMAIN_INVALIDATED_9 9 9 DOMAIN_INVALIDATED_10 10 10 DOMAIN_INVALIDATED_11 11 11 DOMAIN_INVALIDATED_12 12 12 DOMAIN_INVALIDATED_13 13 13 DOMAIN_INVALIDATED_14 14 14 DOMAIN_INVALIDATED_15 15 15 mmVM_PRT_APERTURE0_LOW_ADDR 0 0x52c 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE1_LOW_ADDR 0 0x52d 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE2_LOW_ADDR 0 0x52e 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE3_LOW_ADDR 0 0x52f 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE0_HIGH_ADDR 0 0x530 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE1_HIGH_ADDR 0 0x531 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE2_HIGH_ADDR 0 0x532 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE3_HIGH_ADDR 0 0x533 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_CNTL 0 0x534 7 0 4294967295 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS 0 0 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS 1 1 L2_CACHE_STORE_INVALID_ENTRIES 2 2 L1_TLB_STORE_INVALID_ENTRIES 3 3 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS 4 4 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS 5 5 MASK_PDE0_FAULT 6 6 mmVM_CONTEXTS_DISABLE 0 0x535 16 0 4294967295 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0 0x536 4 0 4294967295 PROTECTIONS 0 7 MEMORY_CLIENT_ID 12 19 MEMORY_CLIENT_RW 24 24 VMID 25 28 mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0 0x537 4 0 4294967295 PROTECTIONS 0 7 MEMORY_CLIENT_ID 12 19 MEMORY_CLIENT_RW 24 24 VMID 25 28 mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0 0x538 1 0 4294967295 NAME 0 31 mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0 0x539 1 0 4294967295 NAME 0 31 mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0 0x53e 1 0 4294967295 LOGICAL_PAGE_ADDR 0 27 mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0 0x53f 1 0 4294967295 LOGICAL_PAGE_ADDR 0 27 mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0 0x546 1 0 4294967295 PHYSICAL_PAGE_ADDR 0 27 mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0 0x547 1 0 4294967295 PHYSICAL_PAGE_ADDR 0 27 mmVM_FAULT_CLIENT_ID 0 0x54e 2 0 4294967295 MEMORY_CLIENT 0 8 MEMORY_CLIENT_MASK 9 17 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0 0x54f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0 0x550 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0 0x551 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0 0x552 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0 0x553 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0 0x554 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0 0x555 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0 0x556 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0 0x557 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0 0x558 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0 0x55f 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0 0x560 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_DEBUG 0 0x56f 1 0 4294967295 FLAGS 0 31 mmVM_L2_CG 0 0x570 3 0 4294967295 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmVM_L2_BANK_SELECT_MASKA 0 0x572 1 0 4294967295 BANK_SELECT_MASK 0 27 mmVM_L2_BANK_SELECT_MASKB 0 0x573 1 0 4294967295 BANK_SELECT_MASK 0 7 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0 0x575 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0 0x576 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0 0x577 1 0 4294967295 PHYSICAL_PAGE_OFFSET 0 27 mmMC_ARB_HARSH_EN_RD 0 0xdc0 4 0 4294967295 TX_PRI 0 7 BW_PRI 8 15 FIX_PRI 16 23 ST_PRI 24 31 mmMC_ARB_HARSH_EN_WR 0 0xdc1 4 0 4294967295 TX_PRI 0 7 BW_PRI 8 15 FIX_PRI 16 23 ST_PRI 24 31 mmMC_ARB_HARSH_TX_HI0_RD 0 0xdc2 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_HI0_WR 0 0xdc3 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_HI1_RD 0 0xdc4 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_HI1_WR 0 0xdc5 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_LO0_RD 0 0xdc6 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_LO0_WR 0 0xdc7 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_LO1_RD 0 0xdc8 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_LO1_WR 0 0xdc9 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWPERIOD0_RD 0 0xdca 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWPERIOD0_WR 0 0xdcb 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWPERIOD1_RD 0 0xdcc 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWPERIOD1_WR 0 0xdcd 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWCNT0_RD 0 0xdce 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWCNT0_WR 0 0xdcf 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWCNT1_RD 0 0xdd0 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWCNT1_WR 0 0xdd1 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_SAT0_RD 0 0xdd2 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_SAT0_WR 0 0xdd3 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_SAT1_RD 0 0xdd4 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_SAT1_WR 0 0xdd5 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_CTL_RD 0 0xdd6 8 0 4294967295 FORCE_HIGHEST 0 7 HARSH_RR 8 8 BANK_AGE_ONLY 9 9 USE_LEGACY_HARSH 10 10 BWCNT_CATCHUP 11 11 ST_MODE 12 13 FORCE_STALL 14 21 PERF_MON_SEL 22 24 mmMC_ARB_HARSH_CTL_WR 0 0xdd7 8 0 4294967295 FORCE_HIGHEST 0 7 HARSH_RR 8 8 BANK_AGE_ONLY 9 9 USE_LEGACY_HARSH 10 10 BWCNT_CATCHUP 11 11 ST_MODE 12 13 FORCE_STALL 14 21 PERF_MON_SEL 22 24 mmMC_FUS_DRAM0_CS0_BASE 0 0xa05 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS0_BASE 0 0xa06 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS1_BASE 0 0xa07 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS1_BASE 0 0xa08 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS2_BASE 0 0xa09 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS2_BASE 0 0xa0a 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS3_BASE 0 0xa0b 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS3_BASE 0 0xa0c 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS01_MASK 0 0xa0d 0 0 4294967295 mmMC_FUS_DRAM1_CS01_MASK 0 0xa0e 0 0 4294967295 mmMC_FUS_DRAM0_CS23_MASK 0 0xa0f 0 0 4294967295 mmMC_FUS_DRAM1_CS23_MASK 0 0xa10 0 0 4294967295 mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0 0xa11 4 0 4294967295 DIMM0ADDRMAP 0 3 DIMM1ADDRMAP 4 7 BANKSWIZZLEMODE 8 8 BANKSWAP 9 9 mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0 0xa12 4 0 4294967295 DIMM0ADDRMAP 0 3 DIMM1ADDRMAP 4 7 BANKSWIZZLEMODE 8 8 BANKSWAP 9 9 mmMC_FUS_DRAM0_CTL_BASE 0 0xa13 4 0 4294967295 DCTSEL 0 2 DCTINTLVEN 3 6 DCTBASEADDR 7 27 DCTOFFSETEN 28 28 mmMC_FUS_DRAM1_CTL_BASE 0 0xa14 4 0 4294967295 DCTSEL 0 2 DCTINTLVEN 3 6 DCTBASEADDR 7 27 DCTOFFSETEN 28 28 mmMC_FUS_DRAM0_CTL_LIMIT 0 0xa15 2 0 4294967295 DCTLIMITADDR 0 20 DRAMHOLEVALID 21 21 mmMC_FUS_DRAM1_CTL_LIMIT 0 0xa16 2 0 4294967295 DCTLIMITADDR 0 20 DRAMHOLEVALID 21 21 mmMC_FUS_DRAM_CTL_HIGH_01 0 0xa17 2 0 4294967295 DCTHIGHADDROFF0 0 11 DCTHIGHADDROFF1 12 23 mmMC_FUS_DRAM_CTL_HIGH_23 0 0xa18 2 0 4294967295 DCTHIGHADDROFF2 0 11 DCTHIGHADDROFF3 12 23 mmMC_FUS_DRAM_MODE 0 0xa19 3 0 4294967295 DCTSELINTLVADDR 0 2 GDDR5EN 3 3 DRAMHOLEOFFSET 4 12 mmMC_FUS_DRAM_APER_BASE 0 0xa1a 1 0 4294967295 BASE 0 19 mmMC_FUS_DRAM_APER_TOP 0 0xa1b 1 0 4294967295 TOP 0 19 mmMC_FUS_DRAM_C6SAVE_APER_BASE 0 0xa1c 1 0 4294967295 BASE 0 19 mmMC_FUS_DRAM_C6SAVE_APER_TOP 0 0xa1d 1 0 4294967295 TOP 0 19 mmMC_FUS_DRAM_APER_DEF 0 0xa1e 2 0 4294967295 DEF 0 27 LOCK_MC_FUS_DRAM_REGS 28 28 mmMC_FUS_ARB_GARLIC_ISOC_PRI 0 0xa1f 25 0 4294967295 DMIF_RD_TOKURG_EN 0 0 UVD_RD_TOKURG_EN 1 1 VCE_RD_TOKURG_EN 2 2 ACP_RD_TOKURG_EN 3 3 DMIF_RD_PRIURG_EN 4 4 UVD_RD_PRIURG_EN 5 5 VCE_RD_PRIURG_EN 6 6 ACP_RD_PRIURG_EN 7 7 DMIF_RD_ISOC_EN 8 8 UVD_RD_ISOC_EN 9 9 VCE_RD_ISOC_EN 10 10 MCIF_RD_ISOC_EN 11 11 UMC_RD_ISOC_EN 12 12 VCEU_RD_ISOC_EN 13 13 ACP_RD_ISOC_EN 14 14 REQPRI_OVERRIDE_EN 15 15 REQPRI_OVERRIDE_VAL 16 17 PRIPRMTE_OVERRIDE_EN 18 18 TOKURG_OVERRIDE_EN 19 19 PRIURG_OVERRIDE_EN 20 20 PRIPRMTE_OVERRIDE_VAL 21 21 TOKURG_OVERRIDE_VAL 22 22 PRIURG_OVERRIDE_VAL 23 23 GARLIC_REQ_CREDITS 24 28 MM_REL_LATE 29 29 mmMC_FUS_ARB_GARLIC_CNTL 0 0xa20 6 0 4294967295 RX_RDRESP_FIFO_PTR_INIT_VALUE 0 7 RX_WRRESP_FIFO_PTR_INIT_VALUE 8 14 EN_64_BYTE_WRITE 15 15 EDC_RESPONSE_ENABLE 16 16 OUTSTANDING_RDRESP_LIMIT 17 25 OUTSTANDING_WRRESP_LIMIT 26 31 mmMC_FUS_ARB_GARLIC_WR_PRI 0 0xa21 16 0 4294967295 CB_WR_PRI 0 1 DB_WR_PRI 2 3 TC_WR_PRI 4 5 CP_WR_PRI 6 7 HDP_WR_PRI 8 9 XDP_WR_PRI 10 11 UMC_WR_PRI 12 13 UVD_WR_PRI 14 15 RLC_WR_PRI 16 17 IH_WR_PRI 18 19 SDMA_WR_PRI 20 21 SEM_WR_PRI 22 23 SH_WR_PRI 24 25 MCIF_WR_PRI 26 27 VCE_WR_PRI 28 29 VCEU_WR_PRI 30 31 mmMC_FUS_ARB_GARLIC_WR_PRI2 0 0xa22 3 0 4294967295 SMU_WR_PRI 0 1 SAM_WR_PRI 2 3 ACP_WR_PRI 4 5 mmMC_CG_DATAPORT 0 0xa32 1 0 4294967295 DATA_FIELD 0 31 mmCHUB_ATC_L1_DEBUG_TLB 0 0x8c00 9 0 4294967295 DISABLE_FRAGMENTS 0 0 DISABLE_INVALIDATE_BY_ADDRESS_RANGE 1 1 EFFECTIVE_CAM_SIZE 4 7 EFFECTIVE_WORK_QUEUE_SIZE 8 10 CREDITS_L1_L2 12 17 CREDITS_L1_RPB 20 27 DEBUG_ECO 28 29 INVALIDATE_ALL 30 30 DISABLE_CACHING_UNTRANSLATED_RETURNS 31 31 mmCHUB_ATC_L1_STATUS 0 0x8c01 3 0 4294967295 BUSY 0 0 DEADLOCK_DETECTION 1 1 BAD_NEED_ATS 8 8