882 mmMC_CONFIG 0 0x800 10 0 4294967295 MCDW_WR_ENABLE 0 0 MCDX_WR_ENABLE 1 1 MCDY_WR_ENABLE 2 2 MCDZ_WR_ENABLE 3 3 MCDS_WR_ENABLE 4 4 MCDT_WR_ENABLE 5 5 MCDU_WR_ENABLE 6 6 MCDV_WR_ENABLE 7 7 MC_RD_ENABLE 8 10 MCC_INDEX_MODE_ENABLE 31 31 mmMC_ARB_ATOMIC 0 0x9be 6 0 4294967295 TC_GRP 0 2 TC_GRP_EN 3 3 SDMA_GRP 4 6 SDMA_GRP_EN 7 7 OUTSTANDING 8 15 ATOMIC_RTN_GRP 16 23 mmMC_ARB_AGE_CNTL 0 0x9bf 22 0 4294967295 RESET_RD_GROUP0 0 0 RESET_RD_GROUP1 1 1 RESET_RD_GROUP2 2 2 RESET_RD_GROUP3 3 3 RESET_RD_GROUP4 4 4 RESET_RD_GROUP5 5 5 RESET_RD_GROUP6 6 6 RESET_RD_GROUP7 7 7 RESET_WR_GROUP0 8 8 RESET_WR_GROUP1 9 9 RESET_WR_GROUP2 10 10 RESET_WR_GROUP3 11 11 RESET_WR_GROUP4 12 12 RESET_WR_GROUP5 13 13 RESET_WR_GROUP6 14 14 RESET_WR_GROUP7 15 15 AGE_LOW_RATE_RD 16 18 AGE_LOW_RATE_WR 19 21 TIMER_STALL_RD 22 22 TIMER_STALL_WR 23 23 EXTEND_WEIGHT_RD 24 24 EXTEND_WEIGHT_WR 25 25 mmMC_ARB_RET_CREDITS2 0 0x9c0 10 0 4294967295 ACP_WR 0 7 NECKDOWN_CNTR_EN_RD 8 8 NECKDOWN_CNTR_EN_WR 9 9 ACP_RDRET_URG 10 10 HDP_RDRET_URG 11 11 NECKDOWN_CNTR_MONITOR_RD 12 12 NECKDOWN_CNTR_MONITOR_WR 13 13 DISABLE_DISP_RDY_RD 14 14 DISABLE_ACP_RDY_WR 15 15 RDRET_CREDIT_MED 16 23 mmMC_ARB_FED_CNTL 0 0x9c1 6 0 4294967295 MODE 0 1 WR_ERR 2 3 KEEP_POISON_IN_PAGE 4 4 RDRET_PARITY_NACK 5 5 USE_LEGACY_NACK 6 6 DEBUG_RSV 7 31 mmMC_ARB_GECC2_STATUS 0 0x9c2 27 0 4294967295 CORR_STS0 0 0 UNCORR_STS0 1 1 FED_STS0 2 2 RSVD0 3 3 CORR_STS1 4 4 UNCORR_STS1 5 5 FED_STS1 6 6 RSVD1 7 7 CORR_CLEAR0 8 8 UNCORR_CLEAR0 9 9 FED_CLEAR0 10 10 RSVD2 11 11 CORR_CLEAR1 12 12 UNCORR_CLEAR1 13 13 FED_CLEAR1 14 14 RSVD3 15 15 RMWRD_CORR_STS0 16 16 RMWRD_UNCORR_STS0 17 17 RSVD4 18 19 RMWRD_CORR_STS1 20 20 RMWRD_UNCORR_STS1 21 21 RSVD5 22 23 RMWRD_CORR_CLEAR0 24 24 RMWRD_UNCORR_CLEAR0 25 25 RSVD6 26 27 RMWRD_CORR_CLEAR1 28 28 RMWRD_UNCORR_CLEAR1 29 29 mmMC_ARB_GECC2_MISC 0 0x9c3 11 0 4294967295 STREAK_BREAK 0 3 COL10_HACK 4 4 CWRD_IN_REPLAY 5 5 NO_EOB_ALL_WR_IN_REPLAY 6 6 RMW_LM_WR_STALL 7 7 RMW_STALL_RELEASE 8 8 WR_EDC_MASK_REPLAY 9 9 CWRD_REPLAY_AGAIN 10 10 WRRDWR_REPLAY_AGAIN 11 11 ALLOW_RMW_ERR_AFTER_REPLAY 12 12 DEBUG_RSV 13 31 mmMC_ARB_GECC2_DEBUG 0 0x9c4 4 0 4294967295 NUM_ERR_BITS 0 1 DIRECTION 2 2 DATA_FIELD 3 4 SW_INJECTION 5 5 mmMC_ARB_GECC2_DEBUG2 0 0x9c5 4 0 4294967295 PERIOD 0 7 ERR0_START 8 15 ERR1_START 16 23 ERR2_START 24 31 mmMC_ARB_PERF_CID 0 0x9c6 4 0 4294967295 CH0 0 7 CH1 8 15 CH0_EN 16 16 CH1_EN 17 17 mmMC_ARB_SNOOP 0 0x9c7 10 0 4294967295 TC_GRP_RD 0 2 TC_GRP_RD_EN 3 3 TC_GRP_WR 4 6 TC_GRP_WR_EN 7 7 SDMA_GRP_RD 8 10 SDMA_GRP_RD_EN 11 11 SDMA_GRP_WR 12 14 SDMA_GRP_WR_EN 15 15 OUTSTANDING_RD 16 23 OUTSTANDING_WR 24 31 mmMC_ARB_GRUB 0 0x9c8 5 0 4294967295 GRUB_WATERMARK 0 7 GRUB_WATERMARK_PRI 8 15 GRUB_WATERMARK_MED 16 23 REG_WR_EN 24 25 REG_RD_SEL 26 26 mmMC_ARB_GECC2 0 0x9c9 10 0 4294967295 ENABLE 0 0 ECC_MODE 1 2 PAGE_BIT0 3 4 EXOR_BANK_SEL 5 6 NO_GECC_CLI 7 10 READ_ERR 11 13 CLOSE_BANK_RMW 14 14 COLFIFO_WATER 15 20 WRADDR_CONV 21 21 RMWRD_UNCOR_POISON 22 22 mmMC_ARB_GECC2_CLI 0 0x9ca 4 0 4294967295 NO_GECC_CLI0 0 7 NO_GECC_CLI1 8 15 NO_GECC_CLI2 16 23 NO_GECC_CLI3 24 31 mmMC_ARB_ADDR_SWIZ0 0 0x9cb 8 0 4294967295 A8 0 3 A9 4 7 A10 8 11 A11 12 15 A12 16 19 A13 20 23 A14 24 27 A15 28 31 mmMC_ARB_ADDR_SWIZ1 0 0x9cc 4 0 4294967295 A16 0 3 A17 4 7 A18 8 11 A19 12 15 mmMC_ARB_MISC3 0 0x9cd 6 0 4294967295 NO_GECC_EXT_EOB 0 0 CHAN4_EN 1 1 CHAN4_ARB_SEL 2 2 UVD_URG_MODE 3 3 UVD_DMIF_HARSH_WT_EN 4 4 TBD_FIELD 5 31 mmMC_ARB_GRUB_PROMOTE 0 0x9ce 4 0 4294967295 URGENT_RD 0 7 URGENT_WR 8 15 PROMOTE_RD 16 23 PROMOTE_WR 24 31 mmMC_ARB_RTT_DATA 0 0x9cf 1 0 4294967295 PATTERN 0 7 mmMC_ARB_RTT_CNTL0 0 0x9d0 23 0 4294967295 ENABLE 0 0 START_IDLE 1 1 START_R2W 2 3 FLUSH_ON_ENTER 4 4 HARSH_START 5 5 TPS_HARSH_PRIORITY 6 6 TWRT_HARSH_PRIORITY 7 7 BREAK_ON_HARSH 8 8 BREAK_ON_URGENTRD 9 9 BREAK_ON_URGENTWR 10 10 TRAIN_PERIOD 11 13 START_R2W_RFSH 14 14 DEBUG_RSV_0 15 15 DEBUG_RSV_1 16 16 DEBUG_RSV_2 17 17 DEBUG_RSV_3 18 18 DEBUG_RSV_4 19 19 DEBUG_RSV_5 20 20 DEBUG_RSV_6 21 21 DEBUG_RSV_7 22 22 DEBUG_RSV_8 23 23 DATA_CNTL 24 24 NEIGHBOR_BIT 25 25 mmMC_ARB_RTT_CNTL1 0 0x9d1 7 0 4294967295 WINDOW_SIZE 0 4 WINDOW_UPDATE 5 5 WINDOW_INC_THRESHOLD 6 12 WINDOW_DEC_THRESHOLD 13 19 WINDOW_SIZE_MAX 20 24 WINDOW_SIZE_MIN 25 29 WINDOW_UPDATE_COUNT 30 31 mmMC_ARB_RTT_CNTL2 0 0x9d2 4 0 4294967295 SAMPLE_CNT 0 5 PHASE_ADJUST_THRESHOLD 6 11 PHASE_ADJUST_SIZE 12 12 FILTER_CNTL 13 13 mmMC_ARB_RTT_DEBUG 0 0x9d3 6 0 4294967295 DEBUG_BYTE_CH0 0 1 DEBUG_BYTE_CH1 2 3 SHIFTED_PHASE_CH0 4 11 WINDOW_SIZE_CH0 12 16 SHIFTED_PHASE_CH1 17 24 WINDOW_SIZE_CH1 25 29 mmMC_ARB_CAC_CNTL 0 0x9d4 4 0 4294967295 ENABLE 0 0 READ_WEIGHT 1 6 WRITE_WEIGHT 7 12 ALLOW_OVERFLOW 13 13 mmMC_ARB_MISC2 0 0x9d5 19 0 4294967295 TCCDL4_BANKBIT3_XOR_ENABLE 5 5 TCCDL4_BANKBIT3_XOR_COLBIT4 6 6 TCCDL4_BANKBIT3_XOR_COLBIT5 7 7 TCCDL4_BANKBIT3_XOR_COLBIT6 8 8 TCCDL4_BANKBIT3_XOR_COLBIT7 9 9 TCCDL4_BANKBIT3_XOR_COLBIT8 10 10 POP_IDLE_REPLAY 11 11 RDRET_NO_REORDERING 12 12 RDRET_NO_BP 13 13 RDRET_SEQ_SKID 14 17 GECC 18 18 GECC_RST 19 19 GECC_STATUS 20 20 TAGFIFO_THRESHOLD 21 24 WCDR_REPLAY_MASKCNT 25 27 REPLAY_DEBUG 28 28 ARB_DEBUG29 29 29 SEQ_RDY_POP_IDLE 30 30 TCCDL4_REPLAY_EOB 31 31 mmMC_ARB_MISC 0 0x9d6 14 0 4294967295 STICKY_RFSH 0 0 IDLE_RFSH 1 1 STUTTER_RFSH 2 2 CHAN_COUPLE 3 10 HARSHNESS 11 18 SMART_RDWR_SW 19 19 CALI_ENABLE 20 20 CALI_RATES 21 22 DISPURGVLD_NOWRT 23 23 DISPURG_NOSW2WR 24 24 DISPURG_STALL 25 25 DISPURG_THROTTLE 26 29 EXTEND_WEIGHT 30 30 ACPURG_STALL 31 31 mmMC_ARB_BANKMAP 0 0x9d7 5 0 4294967295 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 RANK 16 19 mmMC_ARB_RAMCFG 0 0x9d8 10 0 4294967295 NOOFBANK 0 1 NOOFRANKS 2 2 NOOFROWS 3 5 NOOFCOLS 6 7 CHANSIZE 8 8 RSV_1 9 9 RSV_2 10 10 RSV_3 11 11 NOOFGROUPS 12 12 RSV_4 13 17 mmMC_ARB_POP 0 0x9d9 9 0 4294967295 ENABLE_ARB 0 0 SPEC_OPEN 1 1 POP_DEPTH 2 5 WRDATAINDEX_DEPTH 6 11 SKID_DEPTH 12 14 WAIT_AFTER_RFSH 15 16 QUICK_STOP 17 17 ENABLE_TWO_PAGE 18 18 ALLOW_EOB_BY_WRRET_STALL 19 19 mmMC_ARB_MINCLKS 0 0x9da 4 0 4294967295 READ_CLKS 0 7 WRITE_CLKS 8 15 ARB_RW_SWITCH 16 16 RW_SWITCH_HARSH 17 18 mmMC_ARB_SQM_CNTL 0 0x9db 6 0 4294967295 MIN_PENAL 0 7 DYN_SQM_ENABLE 8 8 SQM_RDY16 9 9 SQM_RESERVE 10 15 RATIO 16 23 RATIO_DEBUG 24 31 mmMC_ARB_ADDR_HASH 0 0x9dc 3 0 4294967295 BANK_XOR_ENABLE 0 3 COL_XOR 4 11 ROW_XOR 12 27 mmMC_ARB_DRAM_TIMING 0 0x9dd 4 0 4294967295 ACTRD 0 7 ACTWR 8 15 RASMACTRD 16 23 RASMACTWR 24 31 mmMC_ARB_DRAM_TIMING2 0 0x9de 4 0 4294967295 RAS2RAS 0 7 RP 8 15 WRPLUSRP 16 23 BUS_TURN 24 28 mmMC_ARB_WTM_CNTL_RD 0 0x9df 13 0 4294967295 WTMODE 0 1 HARSH_PRI 2 2 ALLOW_STUTTER_GRP0 3 3 ALLOW_STUTTER_GRP1 4 4 ALLOW_STUTTER_GRP2 5 5 ALLOW_STUTTER_GRP3 6 6 ALLOW_STUTTER_GRP4 7 7 ALLOW_STUTTER_GRP5 8 8 ALLOW_STUTTER_GRP6 9 9 ALLOW_STUTTER_GRP7 10 10 ACP_HARSH_PRI 11 11 ACP_OVER_DISP 12 12 FORCE_ACP_URG 13 13 mmMC_ARB_WTM_CNTL_WR 0 0x9e0 13 0 4294967295 WTMODE 0 1 HARSH_PRI 2 2 ALLOW_STUTTER_GRP0 3 3 ALLOW_STUTTER_GRP1 4 4 ALLOW_STUTTER_GRP2 5 5 ALLOW_STUTTER_GRP3 6 6 ALLOW_STUTTER_GRP4 7 7 ALLOW_STUTTER_GRP5 8 8 ALLOW_STUTTER_GRP6 9 9 ALLOW_STUTTER_GRP7 10 10 ACP_HARSH_PRI 11 11 ACP_OVER_DISP 12 12 FORCE_ACP_URG 13 13 mmMC_ARB_WTM_GRPWT_RD 0 0x9e1 9 0 4294967295 GRP0 0 1 GRP1 2 3 GRP2 4 5 GRP3 6 7 GRP4 8 9 GRP5 10 11 GRP6 12 13 GRP7 14 15 GRP_EXT 16 23 mmMC_ARB_WTM_GRPWT_WR 0 0x9e2 9 0 4294967295 GRP0 0 1 GRP1 2 3 GRP2 4 5 GRP3 6 7 GRP4 8 9 GRP5 10 11 GRP6 12 13 GRP7 14 15 GRP_EXT 16 23 mmMC_ARB_TM_CNTL_RD 0 0x9e3 4 0 4294967295 GROUPBY_RANK 0 0 BANK_SELECT 1 2 MATCH_RANK 3 3 MATCH_BANK 4 4 mmMC_ARB_TM_CNTL_WR 0 0x9e4 4 0 4294967295 GROUPBY_RANK 0 0 BANK_SELECT 1 2 MATCH_RANK 3 3 MATCH_BANK 4 4 mmMC_ARB_LAZY0_RD 0 0x9e5 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_LAZY0_WR 0 0x9e6 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_LAZY1_RD 0 0x9e7 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_LAZY1_WR 0 0x9e8 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_AGE_RD 0 0x9e9 24 0 4294967295 RATE_GROUP0 0 1 RATE_GROUP1 2 3 RATE_GROUP2 4 5 RATE_GROUP3 6 7 RATE_GROUP4 8 9 RATE_GROUP5 10 11 RATE_GROUP6 12 13 RATE_GROUP7 14 15 ENABLE_GROUP0 16 16 ENABLE_GROUP1 17 17 ENABLE_GROUP2 18 18 ENABLE_GROUP3 19 19 ENABLE_GROUP4 20 20 ENABLE_GROUP5 21 21 ENABLE_GROUP6 22 22 ENABLE_GROUP7 23 23 DIVIDE_GROUP0 24 24 DIVIDE_GROUP1 25 25 DIVIDE_GROUP2 26 26 DIVIDE_GROUP3 27 27 DIVIDE_GROUP4 28 28 DIVIDE_GROUP5 29 29 DIVIDE_GROUP6 30 30 DIVIDE_GROUP7 31 31 mmMC_ARB_AGE_WR 0 0x9ea 24 0 4294967295 RATE_GROUP0 0 1 RATE_GROUP1 2 3 RATE_GROUP2 4 5 RATE_GROUP3 6 7 RATE_GROUP4 8 9 RATE_GROUP5 10 11 RATE_GROUP6 12 13 RATE_GROUP7 14 15 ENABLE_GROUP0 16 16 ENABLE_GROUP1 17 17 ENABLE_GROUP2 18 18 ENABLE_GROUP3 19 19 ENABLE_GROUP4 20 20 ENABLE_GROUP5 21 21 ENABLE_GROUP6 22 22 ENABLE_GROUP7 23 23 DIVIDE_GROUP0 24 24 DIVIDE_GROUP1 25 25 DIVIDE_GROUP2 26 26 DIVIDE_GROUP3 27 27 DIVIDE_GROUP4 28 28 DIVIDE_GROUP5 29 29 DIVIDE_GROUP6 30 30 DIVIDE_GROUP7 31 31 mmMC_ARB_RFSH_CNTL 0 0x9eb 7 0 4294967295 ENABLE 0 0 URG0 1 5 URG1 6 10 ACCUM 11 11 SINGLE_BANK 12 12 PUSH_SINGLE_BANK_REFRESH 13 13 PENDING_RATE_SEL 14 16 mmMC_ARB_RFSH_RATE 0 0x9ec 1 0 4294967295 POWERMODE0 0 7 mmMC_ARB_PM_CNTL 0 0x9ed 21 0 4294967295 OVERRIDE_CGSTATE 0 1 OVRR_CGRFSH 2 2 OVRR_CGSQM 3 3 SRFSH_ON_D1 4 4 BLKOUT_ON_D1 5 5 IDLE_ON_D1 6 6 OVRR_PM 7 7 OVRR_PM_STATE 8 9 OVRR_RD 10 10 OVRR_RD_STATE 11 11 OVRR_WR 12 12 OVRR_WR_STATE 13 13 OVRR_RFSH 14 14 OVRR_RFSH_STATE 15 15 OVRR_RD0_BUSY 16 16 OVRR_RD1_BUSY 17 17 IDLE_ON_D2 18 18 IDLE_ON_D3 19 19 IDLE_CNT 20 23 OVRR_WR0_BUSY 24 24 OVRR_WR1_BUSY 25 25 mmMC_ARB_GDEC_RD_CNTL 0 0x9ee 5 0 4294967295 PAGEBIT0 0 3 PAGEBIT1 4 7 USE_RANK 8 8 USE_RSNO 9 9 REM_DEFAULT_GRP 10 13 mmMC_ARB_GDEC_WR_CNTL 0 0x9ef 5 0 4294967295 PAGEBIT0 0 3 PAGEBIT1 4 7 USE_RANK 8 8 USE_RSNO 9 9 REM_DEFAULT_GRP 10 13 mmMC_ARB_LM_RD 0 0x9f0 8 0 4294967295 STREAK_LIMIT 0 7 STREAK_LIMIT_UBER 8 15 STREAK_BREAK 16 16 STREAK_UBER 17 17 ENABLE_TWO_LIST 18 18 POPIDLE_RST_TWOLIST 19 19 SKID1_RST_TWOLIST 20 20 BANKGROUP_CONFIG 21 23 mmMC_ARB_LM_WR 0 0x9f1 11 0 4294967295 STREAK_LIMIT 0 7 STREAK_LIMIT_UBER 8 15 STREAK_BREAK 16 16 STREAK_UBER 17 17 ENABLE_TWO_LIST 18 18 POPIDLE_RST_TWOLIST 19 19 SKID1_RST_TWOLIST 20 20 BANKGROUP_CONFIG 21 23 MASKWR_LM_EOB 24 24 ATOMIC_LM_EOB 25 25 ATOMIC_RTN_LM_EOB 26 26 mmMC_ARB_REMREQ 0 0x9f2 5 0 4294967295 RD_WATER 0 7 WR_WATER 8 15 WR_MAXBURST_SIZE 16 19 WR_LAZY_TIMER 20 23 ENABLE_REMOTE_NACK_REQ 24 24 mmMC_ARB_REPLAY 0 0x9f3 10 0 4294967295 ENABLE_RD 0 0 ENABLE_WR 1 1 WRACK_MODE 2 2 WAW_ENABLE 3 3 RAW_ENABLE 4 4 IGNORE_WR_CDC 5 5 BREAK_ON_STALL 6 6 BOS_ENABLE_WAIT_CYC 7 7 BOS_WAIT_CYC 8 14 NO_PCH_AT_REPLAY_START 15 15 mmMC_ARB_RET_CREDITS_RD 0 0x9f4 4 0 4294967295 LCL 0 7 HUB 8 15 DISP 16 23 RETURN_CREDIT 24 31 mmMC_ARB_RET_CREDITS_WR 0 0x9f5 5 0 4294967295 LCL 0 7 HUB 8 15 RETURN_CREDIT 16 23 WRRET_SEQ_SKID 24 27 WRRET_BP 28 28 mmMC_ARB_MAX_LAT_CID 0 0x9f6 6 0 4294967295 CID_CH0 0 7 CID_CH1 8 15 WRITE_CH0 16 16 WRITE_CH1 17 17 REALTIME_CH0 18 18 REALTIME_CH1 19 19 mmMC_ARB_MAX_LAT_RSLT0 0 0x9f7 1 0 4294967295 MAX_LATENCY 0 31 mmMC_ARB_MAX_LAT_RSLT1 0 0x9f8 1 0 4294967295 MAX_LATENCY 0 31 mmMC_ARB_GRUB_REALTIME_RD 0 0x9f9 32 0 4294967295 CB0 0 0 CBCMASK0 1 1 CBFMASK0 2 2 DB0 3 3 DBHTILE0 4 4 DBSTEN0 5 5 TC0 6 6 IA 7 7 ACPG 8 8 ACPO 9 9 DMIF 10 10 DMIF_EXT0 11 11 DMIF_EXT1 12 12 DMIF_TW 13 13 MCIF 14 14 RLC 15 15 VMC 16 16 SDMA1 17 17 SMU 18 18 VCE0 19 19 VCE1 20 20 XDMAM 21 21 SDMA0 22 22 HDP 23 23 UMC 24 24 UVD 25 25 UVD_EXT0 26 26 UVD_EXT1 27 27 SEM 28 28 SAMMSP 29 29 VP8 30 30 ISP 31 31 mmMC_ARB_CG 0 0x9fa 4 0 4294967295 CG_ARB_REQ 0 7 CG_ARB_RESP 8 15 RSV_0 16 23 RSV_1 24 31 mmMC_ARB_GRUB_REALTIME_WR 0 0x9fb 32 0 4294967295 CB0 0 0 CBCMASK0 1 1 CBFMASK0 2 2 CBIMMED0 3 3 DB0 4 4 DBHTILE0 5 5 DBSTEN0 6 6 TC0 7 7 SH 8 8 ACPG 9 9 ACPO 10 10 MCIF 11 11 RLC 12 12 SDMA1 13 13 SMU 14 14 VCE0 15 15 VCE1 16 16 SAMMSP 17 17 XDMA 18 18 XDMAM 19 19 SDMA0 20 20 HDP 21 21 UMC 22 22 UVD 23 23 UVD_EXT0 24 24 UVD_EXT1 25 25 XDP 26 26 SEM 27 27 IH 28 28 VP8 29 29 ISP 30 30 VIN0 31 31 mmMC_ARB_DRAM_TIMING_1 0 0x9fc 4 0 4294967295 ACTRD 0 7 ACTWR 8 15 RASMACTRD 16 23 RASMACTWR 24 31 mmMC_ARB_BUSY_STATUS 0 0x9fd 32 0 4294967295 LM_RD0 0 0 LM_RD1 1 1 LM_WR0 2 2 LM_WR1 3 3 HM_RD0 4 4 HM_RD1 5 5 HM_WR0 6 6 HM_WR1 7 7 WDE_RD0 8 8 WDE_RD1 9 9 WDE_WR0 10 10 WDE_WR1 11 11 POP0 12 12 POP1 13 13 TAGFIFO0 14 14 TAGFIFO1 15 15 REPLAY0 16 16 REPLAY1 17 17 RDRET0 18 18 RDRET1 19 19 GECC2_RD0 20 20 GECC2_RD1 21 21 GECC2_WR0 22 22 GECC2_WR1 23 23 WRRET0 24 24 WRRET1 25 25 RTT0 26 26 RTT1 27 27 REM_RD0 28 28 REM_RD1 29 29 REM_WR0 30 30 REM_WR1 31 31 mmMC_ARB_DRAM_TIMING2_1 0 0x9ff 4 0 4294967295 RAS2RAS 0 7 RP 8 15 WRPLUSRP 16 23 BUS_TURN 24 28 mmMC_ARB_GRUB2 0 0xa01 15 0 4294967295 REALTIME_GRP_RD 0 7 REALTIME_GRP_WR 8 15 DISP_RD_STALL_EN 16 16 ACP_RD_STALL_EN 17 17 UVD_RD_STALL_EN 18 18 VCE0_RD_STALL_EN 19 19 VCE1_RD_STALL_EN 20 20 REALTIME_RD_WTS 21 21 REALTIME_WR_WTS 22 22 URGENT_BY_DISP_STALL 23 23 PROMOTE_BY_DMIF_URG 24 24 PRIORITY_URGENT_OUTSTANDING_ONLY_RD 25 25 PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD 26 26 PRIORITY_URGENT_OUTSTANDING_ONLY_WR 27 27 PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR 28 28 mmMC_ARB_BURST_TIME 0 0xa02 4 0 4294967295 STATE0 0 4 STATE1 5 9 STATE2 10 14 STATE3 15 19 mmMC_CITF_XTRA_ENABLE 0 0x96d 18 0 4294967295 CB1_RD 0 0 CB1_WR 1 1 DB1_RD 2 2 DB1_WR 3 3 TC2_RD 4 4 ARB_DBG 8 11 TC2_WR 12 12 CB0_CONNECT_CNTL 13 14 DB0_CONNECT_CNTL 15 16 CB1_CONNECT_CNTL 17 18 DB1_CONNECT_CNTL 19 20 TC0_CONNECT_CNTL 21 22 TC1_CONNECT_CNTL 23 24 CB0_CID_CNTL_ENABLE 25 25 DB0_CID_CNTL_ENABLE 26 26 CB1_CID_CNTL_ENABLE 27 27 DB1_CID_CNTL_ENABLE 28 28 TC2_REPAIR_ENABLE 29 30 mmCC_MC_MAX_CHANNEL 0 0x96e 1 0 4294967295 NOOFCHAN 1 4 mmMC_CG_CONFIG 0 0x96f 6 0 4294967295 MCDW_WR_ENABLE 0 0 MCDX_WR_ENABLE 1 1 MCDY_WR_ENABLE 2 2 MCDZ_WR_ENABLE 3 3 MC_RD_ENABLE 4 5 INDEX 6 21 mmMC_CITF_CNTL 0 0x970 6 0 4294967295 IGNOREPM 2 2 EXEMPTPM 3 3 GFX_IDLE_OVERRIDE 4 5 MCD_SRBM_MASK_ENABLE 6 6 CNTR_CHMAP_MODE 7 8 REMOTE_RB_CONNECT_ENABLE 9 9 mmMC_CITF_CREDITS_VM 0 0x971 2 0 4294967295 READ_ALL 0 5 WRITE_ALL 6 11 mmMC_CITF_CREDITS_ARB_RD 0 0x972 5 0 4294967295 READ_LCL 0 7 READ_HUB 8 15 READ_PRI 16 23 LCL_PRI 24 24 HUB_PRI 25 25 mmMC_CITF_CREDITS_ARB_WR 0 0x973 5 0 4294967295 WRITE_LCL 0 7 WRITE_HUB 8 15 WRITE_PRI 16 23 HUB_PRI 24 24 LCL_PRI 25 25 mmMC_CITF_DAGB_CNTL 0 0x974 4 0 4294967295 JUMP_AHEAD 0 0 CENTER_RD_MAX_BURST 1 4 DISABLE_SELF_INIT 5 5 CENTER_WR_MAX_BURST 6 9 mmMC_CITF_INT_CREDITS 0 0x975 4 0 4294967295 REMRDRET 0 5 CNTR_RD_HUB_LP 12 17 CNTR_RD_HUB_HP 18 23 CNTR_RD_LCL 24 29 mmMC_CITF_RET_MODE 0 0x976 8 0 4294967295 INORDER_RD 0 0 INORDER_WR 1 1 REMPRI_RD 2 2 REMPRI_WR 3 3 LCLPRI_RD 4 4 LCLPRI_WR 5 5 RDRET_STALL_EN 6 6 RDRET_STALL_THRESHOLD 7 14 mmMC_CITF_DAGB_DLY 0 0x977 3 0 4294967295 DLY 0 4 CLI 16 21 POS 24 29 mmMC_RD_GRP_EXT 0 0x978 2 0 4294967295 DBSTEN0 0 3 TC0 4 7 mmMC_WR_GRP_EXT 0 0x979 2 0 4294967295 DBSTEN0 0 3 TC0 4 7 mmMC_CITF_REMREQ 0 0x97a 3 0 4294967295 READ_CREDITS 0 6 WRITE_CREDITS 7 13 CREDITS_ENABLE 14 14 mmMC_WR_TC0 0 0x97b 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_TC1 0 0x97c 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_CITF_INT_CREDITS_WR 0 0x97d 2 0 4294967295 CNTR_WR_HUB 0 5 CNTR_WR_LCL 6 11 mmMC_CITF_CREDITS_ARB_RD2 0 0x97e 1 0 4294967295 READ_MED 0 7 mmMC_CITF_WTM_RD_CNTL 0 0x97f 10 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 DISABLE_REMOTE 24 24 DISABLE_LOCAL 25 25 mmMC_CITF_WTM_WR_CNTL 0 0x980 10 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 DISABLE_REMOTE 24 24 DISABLE_LOCAL 25 25 mmMC_RD_CB 0 0x981 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_DB 0 0x982 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_TC0 0 0x983 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_TC1 0 0x984 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_RD_HUB 0 0x985 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_CB 0 0x986 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_DB 0 0x987 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_WR_HUB 0 0x988 8 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAX_BURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 mmMC_CITF_CREDITS_XBAR 0 0x989 2 0 4294967295 READ_LCL 0 7 WRITE_LCL 8 15 mmMC_RD_GRP_LCL 0 0x98a 5 0 4294967295 CB0 12 15 CBCMASK0 16 19 CBFMASK0 20 23 DB0 24 27 DBHTILE0 28 31 mmMC_WR_GRP_LCL 0 0x98b 7 0 4294967295 CB0 0 3 CBCMASK0 4 7 CBFMASK0 8 11 DB0 12 15 DBHTILE0 16 19 SX0 20 23 CBIMMED0 28 31 mmMC_CITF_PERF_MON_CNTL2 0 0x98e 1 0 4294967295 CID 0 7 mmMC_CITF_PERF_MON_RSLT2 0 0x991 18 0 4294967295 CB_RD_BUSY 1 1 DB_RD_BUSY 2 2 TC0_RD_BUSY 3 3 VC0_RD_BUSY 4 4 TC1_RD_BUSY 5 5 VC1_RD_BUSY 6 6 CB_WR_BUSY 7 7 DB_WR_BUSY 8 8 SX_WR_BUSY 9 9 TC2_RD_BUSY 10 10 TC0_WR_BUSY 11 11 TC1_WR_BUSY 12 12 TC2_WR_BUSY 13 13 TC0_ATOM_BUSY 14 14 TC1_ATOM_BUSY 15 15 TC2_ATOM_BUSY 16 16 CB_ATOM_BUSY 17 17 DB_ATOM_BUSY 18 18 mmMC_CITF_MISC_RD_CG 0 0x992 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_CITF_MISC_WR_CG 0 0x993 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_CITF_MISC_VM_CG 0 0x994 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_POWER 0 0x82d 2 0 4294967295 SRBM_GATE_OVERRIDE 2 2 PM_BLACKOUT_CNTL 3 4 mmMC_HUB_MISC_HUB_CG 0 0x82e 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_VM_CG 0 0x82f 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_SIP_CG 0 0x830 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_HUB_MISC_STATUS 0 0x832 20 0 4294967295 OUTSTANDING_READ 0 0 OUTSTANDING_WRITE 1 1 OUTSTANDING_ATOMIC 2 2 OUTSTANDING_HUB_RDREQ 3 3 OUTSTANDING_HUB_RDRET 4 4 OUTSTANDING_HUB_WRREQ 5 5 OUTSTANDING_HUB_WRRET 6 6 OUTSTANDING_HUB_ATOMIC_REQ 7 7 OUTSTANDING_HUB_ATOMIC_RET 8 8 OUTSTANDING_RPB_READ 9 9 OUTSTANDING_RPB_WRITE 10 10 OUTSTANDING_RPB_ATOMIC 11 11 OUTSTANDING_MCD_READ 12 12 OUTSTANDING_MCD_WRITE 13 13 OUTSTANDING_MCD_ATOMIC 14 14 RPB_BUSY 15 15 WRITE_DEADLOCK_WARNING 16 16 READ_DEADLOCK_WARNING 17 17 ATOMIC_DEADLOCK_WARNING 18 18 GFX_BUSY 19 19 mmMC_HUB_MISC_OVERRIDE 0 0x833 1 0 4294967295 IDLE 0 1 mmMC_HUB_MISC_FRAMING 0 0x834 1 0 4294967295 BITS 0 31 mmMC_HUB_WDP_CNTL 0 0x835 16 0 4294967295 JUMPAHEAD_GBL0 1 1 JUMPAHEAD_GBL1 2 2 JUMPAHEAD_INTERNAL 3 3 OVERRIDE_STALL_ENABLE 4 4 DEBUG_REG 5 12 DISABLE_SELF_INIT_GBL0 13 13 DISABLE_SELF_INIT_GBL1 14 14 DISABLE_SELF_INIT_INTERNAL 15 15 FAIR_CH_SW 16 16 LCLWRREQ_BYPASS 17 17 DISP_WAIT_EOP 18 18 MCD_WAIT_EOP 19 19 SIP_WAIT_EOP 20 20 UVD_VCE_WRITE_PRI_EN 21 21 WRITE_PRI_EN 22 22 IH_PHYSADDR_ENABLE 23 23 mmMC_HUB_WDP_ERR 0 0x836 2 0 4294967295 MGPU1_TARG_SYS 0 0 MGPU2_TARG_SYS 1 1 mmMC_HUB_WDP_BP 0 0x837 3 0 4294967295 ENABLE 0 0 RDRET 1 17 WRREQ 18 29 mmMC_HUB_WDP_STATUS 0 0x838 23 0 4294967295 SIP_AVAIL 0 0 MCDW_RD_AVAIL 1 1 MCDX_RD_AVAIL 2 2 MCDY_RD_AVAIL 3 3 MCDZ_RD_AVAIL 4 4 MCDS_RD_AVAIL 5 5 MCDT_RD_AVAIL 6 6 MCDU_RD_AVAIL 7 7 MCDV_RD_AVAIL 8 8 MCDW_WR_AVAIL 9 9 MCDX_WR_AVAIL 10 10 MCDY_WR_AVAIL 11 11 MCDZ_WR_AVAIL 12 12 MCDS_WR_AVAIL 13 13 MCDT_WR_AVAIL 14 14 MCDU_WR_AVAIL 15 15 MCDV_WR_AVAIL 16 16 GBL0_VM_FULL 17 17 GBL0_STOR_FULL 18 18 GBL0_BYPASS_STOR_FULL 19 19 GBL1_VM_FULL 20 20 GBL1_STOR_FULL 21 21 GBL1_BYPASS_STOR_FULL 22 22 mmMC_HUB_RDREQ_STATUS 0 0x839 16 0 4294967295 SIP_AVAIL 0 0 MCDW_RD_AVAIL 1 1 MCDX_RD_AVAIL 2 2 MCDY_RD_AVAIL 3 3 MCDZ_RD_AVAIL 4 4 MCDS_RD_AVAIL 5 5 MCDT_RD_AVAIL 6 6 MCDU_RD_AVAIL 7 7 MCDV_RD_AVAIL 8 8 GBL0_VM_FULL 9 9 GBL0_STOR_FULL 10 10 GBL0_BYPASS_STOR_FULL 11 11 GBL1_VM_FULL 12 12 GBL1_STOR_FULL 13 13 GBL1_BYPASS_STOR_FULL 14 14 PWRXPRESS_ERR 15 15 mmMC_HUB_WRRET_STATUS 0 0x83a 8 0 4294967295 MCDW_AVAIL 0 0 MCDX_AVAIL 1 1 MCDY_AVAIL 2 2 MCDZ_AVAIL 3 3 MCDS_AVAIL 4 4 MCDT_AVAIL 5 5 MCDU_AVAIL 6 6 MCDV_AVAIL 7 7 mmMC_HUB_RDREQ_CNTL 0 0x83b 21 0 4294967295 REMOTE_BLACKOUT 0 0 JUMPAHEAD_GBL0 2 2 JUMPAHEAD_GBL1 3 3 OVERRIDE_STALL_ENABLE 4 4 MCDW_STALL_MODE 5 5 MCDX_STALL_MODE 6 6 MCDY_STALL_MODE 7 7 MCDZ_STALL_MODE 8 8 MCDS_STALL_MODE 9 9 MCDT_STALL_MODE 10 10 MCDU_STALL_MODE 11 11 MCDV_STALL_MODE 12 12 BREAK_HDP_DEADLOCK 13 13 DEBUG_REG 14 20 DISABLE_SELF_INIT_GBL0 21 21 DISABLE_SELF_INIT_GBL1 22 22 PWRXPRESS_MODE 23 23 ACPG_HP_TO_MCD_OVERRIDE 24 24 GBL0_PRI_ENABLE 25 25 UVD_TRANSCODE_ENABLE 26 26 DMIF_URG_THRESHOLD 27 30 mmMC_HUB_WRRET_CNTL 0 0x83c 6 0 4294967295 JUMPAHEAD 0 0 BP 1 20 BP_ENABLE 21 21 DEBUG_REG 22 29 DISABLE_SELF_INIT 30 30 FAIR_CH_SW 31 31 mmMC_HUB_RDREQ_WTM_CNTL 0 0x83d 8 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 mmMC_HUB_WDP_WTM_CNTL 0 0x83e 8 0 4294967295 GROUP0_DECREMENT 0 2 GROUP1_DECREMENT 3 5 GROUP2_DECREMENT 6 8 GROUP3_DECREMENT 9 11 GROUP4_DECREMENT 12 14 GROUP5_DECREMENT 15 17 GROUP6_DECREMENT 18 20 GROUP7_DECREMENT 21 23 mmMC_HUB_WDP_CREDITS 0 0x83f 4 0 4294967295 VM0 0 7 VM1 8 15 STOR0 16 23 STOR1 24 31 mmMC_HUB_WDP_CREDITS2 0 0x840 3 0 4294967295 STOR0_PRI 0 7 STOR1_PRI 8 15 VM2 16 23 mmMC_HUB_WDP_GBL0 0 0x841 5 0 4294967295 MAXBURST 0 3 LAZY_TIMER 4 7 STALL_THRESHOLD 8 15 STALL_MODE 16 16 STALL_THRESHOLD_PRI 17 24 mmMC_HUB_WDP_GBL1 0 0x842 5 0 4294967295 MAXBURST 0 3 LAZY_TIMER 4 7 STALL_THRESHOLD 8 15 STALL_MODE 16 16 STALL_THRESHOLD_PRI 17 24 mmMC_HUB_RDREQ_CREDITS 0 0x844 4 0 4294967295 VM0 0 7 VM1 8 15 STOR0 16 23 STOR1 24 31 mmMC_HUB_RDREQ_CREDITS2 0 0x845 2 0 4294967295 STOR0_PRI 0 7 STOR1_PRI 8 15 mmMC_HUB_SHARED_DAGB_DLY 0 0x846 3 0 4294967295 DLY 0 5 CLI 16 21 POS 24 28 mmMC_HUB_MISC_IDLE_STATUS 0 0x847 32 0 4294967295 OUTSTANDING_GFX_READ 0 0 OUTSTANDING_GFX_WRITE 1 1 OUTSTANDING_RLC_READ 2 2 OUTSTANDING_RLC_WRITE 3 3 OUTSTANDING_SDMA0_READ 4 4 OUTSTANDING_SDMA0_WRITE 5 5 OUTSTANDING_SDMA1_READ 6 6 OUTSTANDING_SDMA1_WRITE 7 7 OUTSTANDING_DISP_READ 8 8 OUTSTANDING_DISP_WRITE 9 9 OUTSTANDING_UVD_READ 10 10 OUTSTANDING_UVD_WRITE 11 11 OUTSTANDING_SMU_READ 12 12 OUTSTANDING_SMU_WRITE 13 13 OUTSTANDING_HDP_READ 14 14 OUTSTANDING_HDP_WRITE 15 15 OUTSTANDING_OTH_READ 16 16 OUTSTANDING_OTH_WRITE 17 17 OUTSTANDING_VMC_READ 18 18 OUTSTANDING_VMC_WRITE 19 19 OUTSTANDING_VCE_READ 20 20 OUTSTANDING_VCE_WRITE 21 21 OUTSTANDING_ACP_READ 22 22 OUTSTANDING_ACP_WRITE 23 23 OUTSTANDING_SAMMSP_READ 24 24 OUTSTANDING_SAMMSP_WRITE 25 25 OUTSTANDING_XDMA_READ 26 26 OUTSTANDING_XDMA_WRITE 27 27 OUTSTANDING_ISP_READ 28 28 OUTSTANDING_ISP_WRITE 29 29 OUTSTANDING_VP8_READ 30 30 OUTSTANDING_VP8_WRITE 31 31 mmMC_HUB_RDREQ_DMIF_LIMIT 0 0x848 2 0 4294967295 ENABLE 0 1 LIMIT_COUNT 2 6 mmMC_HUB_RDREQ_ACPG_LIMIT 0 0x849 2 0 4294967295 ENABLE 0 1 LIMIT_COUNT 2 6 mmMC_HUB_WDP_BYPASS_GBL0 0 0x84a 5 0 4294967295 ENABLE 0 0 CID1 1 8 CID2 9 16 HDP_PRIORITY_TIME 17 23 OTH_PRIORITY_TIME 24 30 mmMC_HUB_WDP_BYPASS_GBL1 0 0x84b 5 0 4294967295 ENABLE 0 0 CID1 1 8 CID2 9 16 HDP_PRIORITY_TIME 17 23 OTH_PRIORITY_TIME 24 30 mmMC_HUB_RDREQ_BYPASS_GBL0 0 0x84c 3 0 4294967295 ENABLE 0 0 CID1 1 8 CID2 9 16 mmMC_HUB_WDP_SH2 0 0x84d 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SH3 0 0x84e 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_MISC_ATOMIC_IDLE_STATUS 0 0x84f 16 0 4294967295 OUTSTANDING_GFX_ATOMIC 0 0 OUTSTANDING_RLC_ATOMIC 1 1 OUTSTANDING_SDMA0_ATOMIC 2 2 OUTSTANDING_SDMA1_ATOMIC 3 3 OUTSTANDING_DISP_ATOMIC 4 4 OUTSTANDING_UVD_ATOMIC 5 5 OUTSTANDING_SMU_ATOMIC 6 6 OUTSTANDING_HDP_ATOMIC 7 7 OUTSTANDING_OTH_ATOMIC 8 8 OUTSTANDING_VMC_ATOMIC 9 9 OUTSTANDING_VCE_ATOMIC 10 10 OUTSTANDING_ACP_ATOMIC 11 11 OUTSTANDING_SAMMSP_ATOMIC 12 12 OUTSTANDING_XDMA_ATOMIC 13 13 OUTSTANDING_ISP_ATOMIC 14 14 OUTSTANDING_VP8_ATOMIC 15 15 mmMC_HUB_RDREQ_MCDW 0 0x851 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 MED_CREDITS 25 31 mmMC_HUB_RDREQ_MCDX 0 0x852 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 MED_CREDITS 25 31 mmMC_HUB_RDREQ_MCDY 0 0x853 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 MED_CREDITS 25 31 mmMC_HUB_RDREQ_MCDZ 0 0x854 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 MED_CREDITS 25 31 mmMC_HUB_RDREQ_SIP 0 0x855 3 0 4294967295 ASK_CREDITS 0 6 MED_CREDIT_SEL 7 7 DISPLAY_CREDITS 8 14 mmMC_HUB_RDREQ_GBL0 0 0x856 2 0 4294967295 STALL_THRESHOLD 0 7 STALL_THRESHOLD_PRI 8 15 mmMC_HUB_RDREQ_GBL1 0 0x857 2 0 4294967295 STALL_THRESHOLD 0 7 STALL_THRESHOLD_PRI 8 15 mmMC_HUB_RDREQ_SMU 0 0x858 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_SDMA0 0 0x859 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_HDP 0 0x85a 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_SDMA1 0 0x85b 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_RLC 0 0x85c 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_SEM 0 0x85d 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_VCE0 0 0x85e 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_RDREQ_UMC 0 0x85f 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_RDREQ_UVD 0 0x860 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_RDREQ_DMIF 0 0x862 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_MCIF 0 0x863 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_VMC 0 0x864 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_VCEU0 0 0x865 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_MCDW 0 0x866 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDX 0 0x867 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDY 0 0x868 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDZ 0 0x869 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_SIP 0 0x86a 2 0 4294967295 STALL_MODE 0 1 ASK_CREDITS 2 8 mmMC_HUB_WDP_SDMA1 0 0x86b 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SH0 0 0x86c 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_MCIF 0 0x86d 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_VCE0 0 0x86e 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_WDP_XDP 0 0x86f 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_IH 0 0x870 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_RLC 0 0x871 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SEM 0 0x872 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SMU 0 0x873 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SH1 0 0x874 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_UMC 0 0x875 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_UVD 0 0x876 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_WDP_HDP 0 0x877 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_SDMA0 0 0x878 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WRRET_MCDW 0 0x879 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDX 0 0x87a 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDY 0 0x87b 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDZ 0 0x87c 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WDP_VCEU0 0 0x87d 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_XDMAM 0 0x87e 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_XDMA 0 0x87f 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_XDMAM 0 0x880 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_ACPG 0 0x881 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_ACPO 0 0x882 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_SAMMSP 0 0x883 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_VP8 0 0x884 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_VP8U 0 0x885 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_ACPG 0 0x886 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ACPO 0 0x887 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_SAMMSP 0 0x888 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_VP8 0 0x889 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_VP8U 0 0x88a 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_RDREQ_ISP_SPM 0 0xde0 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_ISP_MPM 0 0xde1 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_ISP_CCPU 0 0xde2 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ISP_SPM 0 0xde3 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ISP_MPS 0 0xde4 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ISP_MPM 0 0xde5 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_WDP_ISP_CCPU 0 0xde6 12 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 PRIORITY_DISABLE 17 17 STALL_FILTER_ENABLE 18 18 STALL_THRESHOLD 19 24 mmMC_HUB_RDREQ_MCDS 0 0xde7 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDT 0 0xde8 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDU 0 0xde9 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_RDREQ_MCDV 0 0xdea 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 BUS 2 2 MAXBURST 3 6 LAZY_TIMER 7 10 ASK_CREDITS 11 17 DISPLAY_CREDITS 18 24 STALL_THRESHOLD 25 31 mmMC_HUB_WDP_MCDS 0 0xdeb 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDT 0 0xdec 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDU 0 0xded 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WDP_MCDV 0 0xdee 8 0 4294967295 ENABLE 0 0 BLACKOUT_EXEMPT 1 1 STALL_MODE 2 2 MAXBURST 3 6 ASK_CREDITS 7 12 LAZY_TIMER 13 16 STALL_THRESHOLD 17 23 ASK_CREDITS_W 24 30 mmMC_HUB_WRRET_MCDS 0 0xdef 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDT 0 0xdf0 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDU 0 0xdf1 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WRRET_MCDV 0 0xdf2 2 0 4294967295 STALL_MODE 0 0 CREDIT_COUNT 1 7 mmMC_HUB_WDP_CREDITS_MCDW 0 0xdf3 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDX 0 0xdf4 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDY 0 0xdf5 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDZ 0 0xdf6 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDS 0 0xdf7 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDT 0 0xdf8 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDU 0 0xdf9 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_CREDITS_MCDV 0 0xdfa 2 0 4294967295 WR_PRI 0 6 WR_PRI_STALL_THRESHOLD 7 13 mmMC_HUB_WDP_BP2 0 0xdfb 1 0 4294967295 RDRET 0 15 mmMC_HUB_RDREQ_VCE1 0 0xdfc 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_RDREQ_VCEU1 0 0xdfd 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_HUB_WDP_VCE1 0 0xdfe 10 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 VM_BYPASS 16 16 BYPASS_AVAIL_OVERRIDE 17 17 mmMC_HUB_WDP_VCEU1 0 0xdff 9 0 4294967295 ENABLE 0 0 PRESCALE 1 2 BLACKOUT_EXEMPT 3 3 STALL_MODE 4 5 STALL_OVERRIDE 6 6 MAXBURST 7 10 LAZY_TIMER 11 14 STALL_OVERRIDE_WTM 15 15 BYPASS_AVAIL_OVERRIDE 16 16 mmMC_RPB_CONF 0 0x94d 3 0 4294967295 XPB_PCIE_ORDER 15 15 RPB_RD_PCIE_ORDER 16 16 RPB_WR_PCIE_ORDER 17 17 mmMC_RPB_IF_CONF 0 0x94e 2 0 4294967295 RPB_BIF_CREDITS 0 7 OUTSTANDING_WRRET_ASK 8 15 mmMC_RPB_DBG1 0 0x94f 3 0 4294967295 RPB_BIF_OUTSTANDING_RD 0 7 RPB_BIF_OUTSTANDING_RD_32B 8 19 DEBUG_BITS 20 31 mmMC_RPB_EFF_CNTL 0 0x950 2 0 4294967295 WR_LAZY_TIMER 0 7 RD_LAZY_TIMER 8 15 mmMC_RPB_ARB_CNTL 0 0x951 3 0 4294967295 WR_SWITCH_NUM 0 7 RD_SWITCH_NUM 8 15 ATC_SWITCH_NUM 16 23 mmMC_RPB_BIF_CNTL 0 0x952 2 0 4294967295 ARB_SWITCH_NUM 0 7 XPB_SWITCH_NUM 8 15 mmMC_RPB_WR_SWITCH_CNTL 0 0x953 4 0 4294967295 QUEUE0_SWITCH_NUM 0 7 QUEUE1_SWITCH_NUM 8 15 QUEUE2_SWITCH_NUM 16 23 QUEUE3_SWITCH_NUM 24 31 mmMC_RPB_WR_COMBINE_CNTL 0 0x954 4 0 4294967295 WC_ENABLE 0 0 WC_MAX_PACKET_SIZE 1 2 WC_FLUSH_TIMER 3 6 WC_ALIGN 7 7 mmMC_RPB_RD_SWITCH_CNTL 0 0x955 4 0 4294967295 QUEUE0_SWITCH_NUM 0 7 QUEUE1_SWITCH_NUM 8 15 QUEUE2_SWITCH_NUM 16 23 QUEUE3_SWITCH_NUM 24 31 mmMC_RPB_CID_QUEUE_WR 0 0x956 5 0 4294967295 CLIENT_ID 0 7 UPDATE_MODE 8 8 WRITE_QUEUE 9 10 READ_QUEUE 11 12 UPDATE 13 13 mmMC_RPB_CID_QUEUE_RD 0 0x957 3 0 4294967295 CLIENT_ID 0 7 WRITE_QUEUE 8 9 READ_QUEUE 10 11 mmMC_RPB_PERF_COUNTER_CNTL 0 0x958 9 0 4294967295 PERF_COUNTER_SELECT 0 1 CLEAR_SELECTED_PERF_COUNTER 2 2 CLEAR_ALL_PERF_COUNTERS 3 3 STOP_ON_COUNTER_SATURATION 4 4 ENABLE_PERF_COUNTERS 5 8 PERF_COUNTER_ASSIGN_0 9 13 PERF_COUNTER_ASSIGN_1 14 18 PERF_COUNTER_ASSIGN_2 19 23 PERF_COUNTER_ASSIGN_3 24 28 mmMC_RPB_PERF_COUNTER_STATUS 0 0x959 1 0 4294967295 PERFORMANCE_COUNTER_VALUE 0 31 mmMC_RPB_CID_QUEUE_EX 0 0x95a 2 0 4294967295 START 0 0 OFFSET 1 5 mmMC_RPB_CID_QUEUE_EX_DATA 0 0x95b 2 0 4294967295 WRITE_ENTRIES 0 15 READ_ENTRIES 16 31 mmMC_RPB_TCI_CNTL 0 0x95c 7 0 4294967295 TCI_ENABLE 0 0 TCI_POLICY 1 2 TCI_VOL 3 3 TCI_VMID 4 7 TCI_REQ_CREDITS 8 15 TCI_MAX_WRITES 16 23 TCI_MAX_READS 24 31 mmMC_RPB_TCI_CNTL2 0 0x95d 6 0 4294967295 TCI_POLICY 0 0 TCI_MTYPE 1 2 TCI_SNOOP 3 3 TCI_PHYSICAL 4 4 TCI_PERF_CNTR_EN 5 5 TCI_EXE 6 6 mmMC_SHARED_CHMAP 0 0x801 6 0 4294967295 CHAN0 0 3 CHAN1 4 7 CHAN2 8 11 NOOFCHAN 12 15 CHAN3 16 19 CHAN4 20 23 mmMC_SHARED_CHREMAP 0 0x802 8 0 4294967295 CHAN0 0 3 CHAN1 4 7 CHAN2 8 11 CHAN3 12 15 CHAN4 16 19 CHAN5 20 23 CHAN6 24 27 CHAN7 28 31 mmMC_RD_GRP_GFX 0 0x803 8 0 4294967295 CP 0 3 SH 4 7 IA 8 11 ACPG 12 15 ACPO 16 19 XDMAM 20 23 ISP 24 27 VP8 28 31 mmMC_WR_GRP_GFX 0 0x804 8 0 4294967295 CP 0 3 SH 4 7 ACPG 8 11 ACPO 12 15 ISP 16 19 VP8 20 23 XDMA 24 27 XDMAM 28 31 mmMC_RD_GRP_SYS 0 0x805 8 0 4294967295 RLC 0 3 VMC 4 7 SDMA1 8 11 DMIF 12 15 MCIF 16 19 SMU 20 23 VCE0 24 27 VCE1 28 31 mmMC_WR_GRP_SYS 0 0x806 8 0 4294967295 IH 0 3 MCIF 4 7 RLC 8 11 SAMMSP 12 15 SMU 16 19 SDMA1 20 23 VCE0 24 27 VCE1 28 31 mmMC_RD_GRP_OTH 0 0x807 8 0 4294967295 UVD_EXT0 0 3 SDMA0 4 7 HDP 8 11 SEM 12 15 UMC 16 19 UVD 20 23 UVD_EXT1 24 27 SAMMSP 28 31 mmMC_WR_GRP_OTH 0 0x808 8 0 4294967295 UVD_EXT0 0 3 SDMA0 4 7 HDP 8 11 SEM 12 15 UMC 16 19 UVD 20 23 XDP 24 27 UVD_EXT1 28 31 mmMC_VM_FB_LOCATION 0 0x809 2 0 4294967295 FB_BASE 0 15 FB_TOP 16 31 mmMC_VM_AGP_TOP 0 0x80a 1 0 4294967295 AGP_TOP 0 17 mmMC_VM_AGP_BOT 0 0x80b 1 0 4294967295 AGP_BOT 0 17 mmMC_VM_AGP_BASE 0 0x80c 1 0 4294967295 AGP_BASE 0 17 mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x80d 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x80e 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0 0x80f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmMC_VM_DC_WRITE_CNTL 0 0x810 6 0 4294967295 DC_WRITE_HIT_REGION_0_MODE 0 1 DC_WRITE_HIT_REGION_1_MODE 2 3 DC_WRITE_HIT_REGION_2_MODE 4 5 DC_WRITE_HIT_REGION_3_MODE 6 7 DC_MEMORY_WRITE_LOCAL 8 8 DC_MEMORY_WRITE_SYSTEM 9 9 mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0 0x811 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0 0x812 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0 0x813 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0 0x814 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0 0x815 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0 0x816 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0 0x817 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0 0x818 1 0 4294967295 PHYSICAL_ADDRESS 0 27 mmMC_VM_MX_L1_TLB_CNTL 0 0x819 6 0 4294967295 ENABLE_L1_TLB 0 0 ENABLE_L1_FRAGMENT_PROCESSING 1 1 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 mmMC_VM_FB_OFFSET 0 0x81a 1 0 4294967295 FB_OFFSET 0 17 mmMC_VM_STEERING 0 0x81b 1 0 4294967295 DEFAULT_STEERING 0 1 mmMC_SHARED_CHREMAP2 0 0x81c 8 0 4294967295 CHAN8 0 3 CHAN9 4 7 CHAN10 8 11 CHAN11 12 15 CHAN12 16 19 CHAN13 20 23 CHAN14 24 27 CHAN15 28 31 mmMC_SHARED_VF_ENABLE 0 0x81d 1 0 4294967295 VF_ENABLE 0 0 mmMC_SHARED_VIRT_RESET_REQ 0 0x81e 2 0 4294967295 VF 0 15 PF 31 31 mmMC_SHARED_ACTIVE_FCN_ID 0 0x81f 2 0 4294967295 VFID 0 3 VF 31 31 mmMC_CONFIG_MCD 0 0x828 13 0 4294967295 MCD0_WR_ENABLE 0 0 MCD1_WR_ENABLE 1 1 MCD2_WR_ENABLE 2 2 MCD3_WR_ENABLE 3 3 MCD4_WR_ENABLE 4 4 MCD5_WR_ENABLE 5 5 MCD6_WR_ENABLE 6 6 MCD7_WR_ENABLE 7 7 MC_RD_ENABLE 8 10 MC_RD_ENABLE_SUB 11 11 ARB0_WR_ENABLE 12 12 ARB1_WR_ENABLE 13 13 MCD_INDEX_MODE_ENABLE 31 31 mmMC_CG_CONFIG_MCD 0 0x829 11 0 4294967295 MCD0_WR_ENABLE 0 0 MCD1_WR_ENABLE 1 1 MCD2_WR_ENABLE 2 2 MCD3_WR_ENABLE 3 3 MCD4_WR_ENABLE 4 4 MCD5_WR_ENABLE 5 5 MCD6_WR_ENABLE 6 6 MCD7_WR_ENABLE 7 7 MC_RD_ENABLE 8 10 MC_RD_ENABLE_SUB 11 11 INDEX 13 28 mmMC_MEM_POWER_LS 0 0x82a 2 0 4294967295 LS_SETUP 0 5 LS_HOLD 6 11 mmMC_SHARED_BLACKOUT_CNTL 0 0x82b 5 0 4294967295 BLACKOUT_MODE 0 2 BLACKOUT_SEQ_FREE 3 3 BLACKOUT_MCD_NUM 4 11 FREE_TIE_HIGH 12 12 SRBM_DUMMY_READ_RETURN 13 13 mmMC_VM_MB_L1_TLB0_DEBUG 0 0x891 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB1_DEBUG 0 0x892 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB2_DEBUG 0 0x893 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB0_STATUS 0 0x895 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L1_TLB1_STATUS 0 0x896 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L1_TLB2_STATUS 0 0x897 1 0 4294967295 BUSY 0 0 mmMC_VM_MB_L2ARBITER_L2_CREDITS 0 0x8a1 1 0 4294967295 L2_IF_CREDITS 0 5 mmMC_VM_MB_L1_TLB3_DEBUG 0 0x8a5 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MB_L1_TLB3_STATUS 0 0x8a6 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB0_DEBUG 0 0x998 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB1_DEBUG 0 0x999 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB2_DEBUG 0 0x99a 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB0_STATUS 0 0x99b 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB1_STATUS 0 0x99c 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L1_TLB2_STATUS 0 0x99d 1 0 4294967295 BUSY 0 0 mmMC_VM_MD_L2ARBITER_L2_CREDITS 0 0x9a4 1 0 4294967295 L2_IF_CREDITS 0 5 mmMC_VM_MD_L1_TLB3_DEBUG 0 0x9a7 6 0 4294967295 INVALIDATE_L1_TLB 0 0 SEND_FREE_AT_RTN 8 8 EFFECTIVE_L1_TLB_SIZE 9 11 EFFECTIVE_L1_QUEUE_SIZE 12 14 L1_TLB_DEBUG 15 18 L1_TLB_FORCE_MISS 19 19 mmMC_VM_MD_L1_TLB3_STATUS 0 0x9a8 1 0 4294967295 BUSY 0 0 mmMC_XPB_RTR_SRC_APRTR0 0 0x8cd 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR1 0 0x8ce 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR2 0 0x8cf 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR3 0 0x8d0 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR4 0 0x8d1 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR5 0 0x8d2 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR6 0 0x8d3 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR7 0 0x8d4 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR8 0 0x8d5 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_SRC_APRTR9 0 0x8d6 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR0 0 0x8d7 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR1 0 0x8d8 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR2 0 0x8d9 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_XDMA_RTR_SRC_APRTR3 0 0x8da 1 0 4294967295 BASE_ADDR 0 24 mmMC_XPB_RTR_DEST_MAP0 0 0x8db 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP1 0 0x8dc 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP2 0 0x8dd 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP3 0 0x8de 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP4 0 0x8df 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP5 0 0x8e0 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP6 0 0x8e1 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP7 0 0x8e2 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP8 0 0x8e3 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_RTR_DEST_MAP9 0 0x8e4 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP0 0 0x8e5 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP1 0 0x8e6 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP2 0 0x8e7 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_XDMA_RTR_DEST_MAP3 0 0x8e8 6 0 4294967295 NMR 0 0 DEST_OFFSET 1 19 DEST_SEL 20 23 DEST_SEL_RPB 24 24 SIDE_OK 25 25 APRTR_SIZE 26 30 mmMC_XPB_CLG_CFG0 0 0x8e9 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG1 0 0x8ea 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG2 0 0x8eb 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG3 0 0x8ec 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG4 0 0x8ed 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG5 0 0x8ee 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG6 0 0x8ef 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG7 0 0x8f0 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG8 0 0x8f1 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG9 0 0x8f2 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG10 0 0x8f3 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG11 0 0x8f4 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG12 0 0x8f5 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG13 0 0x8f6 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG14 0 0x8f7 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG15 0 0x8f8 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG16 0 0x8f9 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG17 0 0x8fa 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG18 0 0x8fb 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG19 0 0x8fc 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_EXTRA 0 0x8fd 5 0 4294967295 CMP0 0 7 MSK0 8 15 VLD0 16 16 CMP1 17 24 VLD1 25 25 mmMC_XPB_LB_ADDR 0 0x8fe 4 0 4294967295 CMP0 0 9 MASK0 10 19 CMP1 20 25 MASK1 26 31 mmMC_XPB_UNC_THRESH_HST 0 0x8ff 3 0 4294967295 CHANGE_PREF 0 5 STRONG_PREF 6 11 USE_UNFULL 12 17 mmMC_XPB_UNC_THRESH_SID 0 0x900 3 0 4294967295 CHANGE_PREF 0 5 STRONG_PREF 6 11 USE_UNFULL 12 17 mmMC_XPB_WCB_STS 0 0x901 3 0 4294967295 PBUF_VLD 0 15 WCB_HST_DATA_BUF_CNT 16 22 WCB_SID_DATA_BUF_CNT 23 29 mmMC_XPB_WCB_CFG 0 0x902 3 0 4294967295 TIMEOUT 0 15 HST_MAX 16 17 SID_MAX 18 19 mmMC_XPB_P2P_BAR_CFG 0 0x903 9 0 4294967295 ADDR_SIZE 0 3 SEND_BAR 4 5 SNOOP 6 6 SEND_DIS 7 7 COMPRESS_DIS 8 8 UPDATE_DIS 9 9 REGBAR_FROM_SYSBAR 10 10 RD_EN 11 11 ATC_TRANSLATED 12 12 mmMC_XPB_P2P_BAR0 0 0x904 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR1 0 0x905 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR2 0 0x906 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR3 0 0x907 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR4 0 0x908 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR5 0 0x909 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR6 0 0x90a 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR7 0 0x90b 8 0 4294967295 HOST_FLUSH 0 3 REG_SYS_BAR 4 7 MEM_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR_SETUP 0 0x90c 7 0 4294967295 SEL 0 7 REG_SYS_BAR 8 11 VALID 12 12 SEND_DIS 13 13 COMPRESS_DIS 14 14 RESERVED 15 15 ADDRESS 16 31 mmMC_XPB_P2P_BAR_DEBUG 0 0x90d 3 0 4294967295 SEL 0 7 HOST_FLUSH 8 11 MEM_SYS_BAR 12 15 mmMC_XPB_P2P_BAR_DELTA_ABOVE 0 0x90e 2 0 4294967295 EN 0 7 DELTA 8 27 mmMC_XPB_P2P_BAR_DELTA_BELOW 0 0x90f 2 0 4294967295 EN 0 7 DELTA 8 27 mmMC_XPB_PEER_SYS_BAR0 0 0x910 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR1 0 0x911 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR2 0 0x912 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR3 0 0x913 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR4 0 0x914 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR5 0 0x915 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR6 0 0x916 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR7 0 0x917 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR8 0 0x918 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_PEER_SYS_BAR9 0 0x919 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR0 0 0x91a 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR1 0 0x91b 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR2 0 0x91c 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_XDMA_PEER_SYS_BAR3 0 0x91d 3 0 4294967295 VALID 0 0 SIDE_OK 1 1 ADDR 2 26 mmMC_XPB_CLK_GAT 0 0x91e 5 0 4294967295 ONDLY 0 5 OFFDLY 6 11 RDYDLY 12 17 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMC_XPB_INTF_CFG 0 0x91f 11 0 4294967295 RPB_WRREQ_CRD 0 7 MC_WRRET_ASK 8 15 XSP_REQ_CRD 16 22 BIF_REG_SNOOP_SEL 23 23 BIF_REG_SNOOP_VAL 24 24 BIF_MEM_SNOOP_SEL 25 25 BIF_MEM_SNOOP_VAL 26 26 XSP_SNOOP_SEL 27 28 XSP_SNOOP_VAL 29 29 XSP_ORDERING_SEL 30 30 XSP_ORDERING_VAL 31 31 mmMC_XPB_INTF_STS 0 0x920 7 0 4294967295 RPB_WRREQ_CRD 0 7 XSP_REQ_CRD 8 14 HOP_DATA_BUF_FULL 15 15 HOP_ATTR_BUF_FULL 16 16 CNS_BUF_FULL 17 17 CNS_BUF_BUSY 18 18 RPB_RDREQ_CRD 19 26 mmMC_XPB_PIPE_STS 0 0x921 13 0 4294967295 WCB_ANY_PBUF 0 0 WCB_HST_DATA_BUF_CNT 1 7 WCB_SID_DATA_BUF_CNT 8 14 WCB_HST_RD_PTR_BUF_FULL 15 15 WCB_SID_RD_PTR_BUF_FULL 16 16 WCB_HST_REQ_FIFO_FULL 17 17 WCB_SID_REQ_FIFO_FULL 18 18 WCB_HST_REQ_OBUF_FULL 19 19 WCB_SID_REQ_OBUF_FULL 20 20 WCB_HST_DATA_OBUF_FULL 21 21 WCB_SID_DATA_OBUF_FULL 22 22 RET_BUF_FULL 23 23 XPB_CLK_BUSY_BITS 24 31 mmMC_XPB_SUB_CTRL 0 0x922 20 0 4294967295 WRREQ_BYPASS_XPB 0 0 STALL_CNS_RTR_REQ 1 1 STALL_RTR_RPB_WRREQ 2 2 STALL_RTR_MAP_REQ 3 3 STALL_MAP_WCB_REQ 4 4 STALL_WCB_SID_REQ 5 5 STALL_MC_XSP_REQ_SEND 6 6 STALL_WCB_HST_REQ 7 7 STALL_HST_HOP_REQ 8 8 STALL_XPB_RPB_REQ_ATTR 9 9 RESET_CNS 10 10 RESET_RTR 11 11 RESET_RET 12 12 RESET_MAP 13 13 RESET_WCB 14 14 RESET_HST 15 15 RESET_HOP 16 16 RESET_SID 17 17 RESET_SRB 18 18 RESET_CGR 19 19 mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0 0x923 1 0 4294967295 ALTER_FLUSH_NUM 0 15 mmMC_XPB_PERF_KNOBS 0 0x924 3 0 4294967295 CNS_FIFO_DEPTH 0 5 WCB_HST_FIFO_DEPTH 6 11 WCB_SID_FIFO_DEPTH 12 17 mmMC_XPB_STICKY 0 0x925 1 0 4294967295 BITS 0 31 mmMC_XPB_STICKY_W1C 0 0x926 1 0 4294967295 BITS 0 31 mmMC_XPB_MISC_CFG 0 0x927 5 0 4294967295 FIELDNAME0 0 7 FIELDNAME1 8 15 FIELDNAME2 16 23 FIELDNAME3 24 30 TRIGGERNAME 31 31 mmMC_XPB_CLG_CFG20 0 0x928 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG21 0 0x929 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG22 0 0x92a 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG23 0 0x92b 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG24 0 0x92c 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG25 0 0x92d 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG26 0 0x92e 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG27 0 0x92f 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG28 0 0x930 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG29 0 0x931 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG30 0 0x932 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG31 0 0x933 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_INTF_CFG2 0 0x934 1 0 4294967295 RPB_RDREQ_CRD 0 7 mmMC_XPB_CLG_EXTRA_RD 0 0x935 5 0 4294967295 CMP0 0 7 MSK0 8 15 VLD0 16 16 CMP1 17 24 VLD1 25 25 mmMC_XPB_CLG_CFG32 0 0x936 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG33 0 0x937 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG34 0 0x938 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG35 0 0x939 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XPB_CLG_CFG36 0 0x93a 5 0 4294967295 WCB_NUM 0 3 LB_TYPE 4 6 P2P_BAR 7 9 HOST_FLUSH 10 13 SIDE_FLUSH 14 17 mmMC_XBAR_ADDR_DEC 0 0xc80 4 0 4294967295 NO_DIV_BY_3 0 0 GECC 1 1 RB_SPLIT 2 2 RB_SPLIT_COLHI 3 3 mmMC_XBAR_REMOTE 0 0xc81 2 0 4294967295 WRREQ_EN_GOQ 0 0 RDREQ_EN_GOQ 1 1 mmMC_XBAR_WRREQ_CREDIT 0 0xc82 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDREQ_CREDIT 0 0xc83 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDREQ_PRI_CREDIT 0 0xc84 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_WRRET_CREDIT1 0 0xc85 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_WRRET_CREDIT2 0 0xc86 2 0 4294967295 OUT4 0 7 OUT5 8 15 mmMC_XBAR_RDRET_CREDIT1 0 0xc87 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDRET_CREDIT2 0 0xc88 3 0 4294967295 OUT4 0 7 OUT5 8 15 HUB_LP_RDRET_SKID 16 23 mmMC_XBAR_RDRET_PRI_CREDIT1 0 0xc89 4 0 4294967295 OUT0 0 7 OUT1 8 15 OUT2 16 23 OUT3 24 31 mmMC_XBAR_RDRET_PRI_CREDIT2 0 0xc8a 2 0 4294967295 OUT4 0 7 OUT5 8 15 mmMC_XBAR_CHTRIREMAP 0 0xc8b 3 0 4294967295 CH0 0 1 CH1 2 3 CH2 4 5 mmMC_XBAR_TWOCHAN 0 0xc8c 3 0 4294967295 DISABLE_ONEPORT 0 0 CH0 1 2 CH1 3 4 mmMC_XBAR_ARB 0 0xc8d 5 0 4294967295 HUBRD_HIGHEST 0 0 DISABLE_HUB_STALL_HIGHEST 1 1 BREAK_BURST_CID_CHANGE 2 2 ACP_RDRET_URG 3 3 HDP_RDRET_URG 4 4 mmMC_XBAR_ARB_MAX_BURST 0 0xc8e 8 0 4294967295 RD_PORT0 0 3 RD_PORT1 4 7 RD_PORT2 8 11 RD_PORT3 12 15 WR_PORT0 16 19 WR_PORT1 20 23 WR_PORT2 24 27 WR_PORT3 28 31 mmMC_XBAR_FIFO_MON_CNTL0 0 0xc8f 5 0 4294967295 START_THRESH 0 11 STOP_THRESH 12 23 START_MODE 24 25 STOP_MODE 26 27 ALLOW_WRAP 28 28 mmMC_XBAR_FIFO_MON_CNTL1 0 0xc90 3 0 4294967295 THRESH_CNTR_ID 0 7 START_TRIG_ID 8 15 STOP_TRIG_ID 16 23 mmMC_XBAR_FIFO_MON_CNTL2 0 0xc91 4 0 4294967295 MON0_ID 0 7 MON1_ID 8 15 MON2_ID 16 23 MON3_ID 24 31 mmMC_XBAR_FIFO_MON_RSLT0 0 0xc92 1 0 4294967295 COUNT 0 31 mmMC_XBAR_FIFO_MON_RSLT1 0 0xc93 1 0 4294967295 COUNT 0 31 mmMC_XBAR_FIFO_MON_RSLT2 0 0xc94 1 0 4294967295 COUNT 0 31 mmMC_XBAR_FIFO_MON_RSLT3 0 0xc95 1 0 4294967295 COUNT 0 31 mmMC_XBAR_FIFO_MON_MAX_THSH 0 0xc96 4 0 4294967295 MON0 0 7 MON1 8 15 MON2 16 23 MON3 24 31 mmMC_XBAR_SPARE0 0 0xc97 1 0 4294967295 BIT 0 31 mmMC_XBAR_SPARE1 0 0xc98 1 0 4294967295 BIT 0 31 mmMC_CITF_PERFCOUNTER_LO 0 0x7a0 1 0 4294967295 COUNTER_LO 0 31 mmMC_HUB_PERFCOUNTER_LO 0 0x7a1 1 0 4294967295 COUNTER_LO 0 31 mmMC_RPB_PERFCOUNTER_LO 0 0x7a2 1 0 4294967295 COUNTER_LO 0 31 mmMC_MCBVM_PERFCOUNTER_LO 0 0x7a3 1 0 4294967295 COUNTER_LO 0 31 mmMC_MCDVM_PERFCOUNTER_LO 0 0x7a4 1 0 4294967295 COUNTER_LO 0 31 mmMC_VM_L2_PERFCOUNTER_LO 0 0x7a5 1 0 4294967295 COUNTER_LO 0 31 mmMC_ARB_PERFCOUNTER_LO 0 0x7a6 1 0 4294967295 COUNTER_LO 0 31 mmATC_PERFCOUNTER_LO 0 0x7a7 1 0 4294967295 COUNTER_LO 0 31 mmMC_CITF_PERFCOUNTER_HI 0 0x7a8 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_HUB_PERFCOUNTER_HI 0 0x7a9 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_MCBVM_PERFCOUNTER_HI 0 0x7aa 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_MCDVM_PERFCOUNTER_HI 0 0x7ab 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_RPB_PERFCOUNTER_HI 0 0x7ac 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_VM_L2_PERFCOUNTER_HI 0 0x7ad 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_ARB_PERFCOUNTER_HI 0 0x7ae 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATC_PERFCOUNTER_HI 0 0x7af 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_CITF_PERFCOUNTER0_CFG 0 0x7b0 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER1_CFG 0 0x7b1 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER2_CFG 0 0x7b2 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER3_CFG 0 0x7b3 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER0_CFG 0 0x7b4 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER1_CFG 0 0x7b5 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER2_CFG 0 0x7b6 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_HUB_PERFCOUNTER3_CFG 0 0x7b7 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER0_CFG 0 0x7b8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER1_CFG 0 0x7b9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER2_CFG 0 0x7ba 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_RPB_PERFCOUNTER3_CFG 0 0x7bb 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER0_CFG 0 0x7bc 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER1_CFG 0 0x7bd 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER2_CFG 0 0x7be 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_ARB_PERFCOUNTER3_CFG 0 0x7bf 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER0_CFG 0 0x7c0 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER1_CFG 0 0x7c1 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER2_CFG 0 0x7c2 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCBVM_PERFCOUNTER3_CFG 0 0x7c3 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER0_CFG 0 0x7c4 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER1_CFG 0 0x7c5 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER2_CFG 0 0x7c6 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_MCDVM_PERFCOUNTER3_CFG 0 0x7c7 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER0_CFG 0 0x7c8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER1_CFG 0 0x7c9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER2_CFG 0 0x7ca 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_PERFCOUNTER3_CFG 0 0x7cb 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER0_CFG 0 0x7cc 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER1_CFG 0 0x7cd 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0 0x7ce 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0 0x7cf 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0 0x7d0 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0 0x7d1 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0 0x7d2 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x7d3 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0 0x7d4 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmATC_PERFCOUNTER_RSLT_CNTL 0 0x7d5 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmCHUB_ATC_PERFCOUNTER_LO 0 0x7d6 1 0 4294967295 COUNTER_LO 0 31 mmCHUB_ATC_PERFCOUNTER_HI 0 0x7d7 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmCHUB_ATC_PERFCOUNTER0_CFG 0 0x7d8 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmCHUB_ATC_PERFCOUNTER1_CFG 0 0x7d9 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0 0x7da 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_GRUB_PERFCOUNTER_LO 0 0x7e4 1 0 4294967295 COUNTER_LO 0 31 mmMC_GRUB_PERFCOUNTER_HI 0 0x7e5 2 0 4294967295 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_GRUB_PERFCOUNTER0_CFG 0 0x7e6 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_GRUB_PERFCOUNTER1_CFG 0 0x7e7 5 0 4294967295 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_GRUB_PERFCOUNTER_RSLT_CNTL 0 0x7e8 6 0 4294967295 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmATC_VM_APERTURE0_LOW_ADDR 0 0xcc0 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE1_LOW_ADDR 0 0xcc1 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE0_HIGH_ADDR 0 0xcc2 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE1_HIGH_ADDR 0 0xcc3 1 0 4294967295 VIRTUAL_PAGE_NUMBER 0 27 mmATC_VM_APERTURE0_CNTL 0 0xcc4 1 0 4294967295 ATS_ACCESS_MODE 0 1 mmATC_VM_APERTURE1_CNTL 0 0xcc5 1 0 4294967295 ATS_ACCESS_MODE 0 1 mmATC_VM_APERTURE0_CNTL2 0 0xcc6 1 0 4294967295 VMIDS_USING_RANGE 0 15 mmATC_VM_APERTURE1_CNTL2 0 0xcc7 1 0 4294967295 VMIDS_USING_RANGE 0 15 mmATC_ATS_CNTL 0 0xcc9 5 0 4294967295 DISABLE_ATC 0 0 DISABLE_PRI 1 1 DISABLE_PASID 2 2 CREDITS_ATS_RPB 8 13 DEBUG_ECO 16 19 mmATC_ATS_DEBUG 0 0xcca 17 0 4294967295 INVALIDATE_ALL 0 0 IDENT_RETURN 1 1 ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS 2 2 PAGE_REQUESTS_USE_RELAXED_ORDERING 5 5 PRIV_BIT 6 6 EXE_BIT 7 7 PAGE_REQUEST_PERMS 8 8 UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE 9 9 NUM_REQUESTS_AT_ERR 10 13 DISALLOW_ERR_TO_DONE 14 14 IGNORE_FED 15 15 INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED 16 16 DEBUG_BUS_SELECT 17 17 DISABLE_INVALIDATE_PER_DOMAIN 18 18 DISABLE_VMID0_PASID_MAPPING 19 19 DISABLE_INVALIDATION_ON_WORLD_SWITCH 20 20 ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT 21 21 mmATC_ATS_FAULT_DEBUG 0 0xccb 3 0 4294967295 CREDITS_ATS_IH 0 4 ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES 8 8 CLEAR_FAULT_STATUS_ADDR 16 16 mmATC_ATS_STATUS 0 0xccc 3 0 4294967295 BUSY 0 0 CRASHED 1 1 DEADLOCK_DETECTION 2 2 mmATC_ATS_FAULT_CNTL 0 0xccd 3 0 4294967295 FAULT_REGISTER_LOG 0 8 FAULT_INTERRUPT_TABLE 10 18 FAULT_CRASH_TABLE 20 28 mmATC_ATS_FAULT_STATUS_INFO 0 0xcce 8 0 4294967295 FAULT_TYPE 0 8 VMID 10 14 EXTRA_INFO 15 15 EXTRA_INFO2 16 16 INVALIDATION 17 17 PAGE_REQUEST 18 18 STATUS 19 23 PAGE_ADDR_HIGH 24 27 mmATC_ATS_FAULT_STATUS_ADDR 0 0xccf 1 0 4294967295 PAGE_ADDR 0 31 mmATC_ATS_DEFAULT_PAGE_LOW 0 0xcd0 1 0 4294967295 DEFAULT_PAGE 0 27 mmATC_ATS_DEFAULT_PAGE_CNTL 0 0xcd1 1 0 4294967295 SEND_DEFAULT_PAGE 0 0 mmATC_ATS_FAULT_STATUS_INFO2 0 0xcd2 3 0 4294967295 VF 0 0 VFID 1 5 L1_ID 9 16 mmATC_MISC_CG 0 0xcd4 3 0 4294967295 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmATC_L2_CNTL 0 0xcd5 4 0 4294967295 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 4 5 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 8 8 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 9 9 mmATC_L2_CNTL2 0 0xcd6 6 0 4294967295 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 mmATC_L2_DEBUG 0 0xcd7 9 0 4294967295 CREDITS_L2_ATS 0 5 L2_MEM_SELECT 7 7 CACHE_INDEX 8 19 CACHE_SELECT 24 24 CACHE_BANK_SELECT 25 25 CACHE_WAY_SELECT 27 27 CACHE_READ 29 29 CACHE_INJECT_SOFT_PARITY_ERROR 30 30 CACHE_INJECT_HARD_PARITY_ERROR 31 31 mmATC_L2_DEBUG2 0 0xcd8 12 0 4294967295 EFFECTIVE_CACHE_SIZE 0 4 EFFECTIVE_WORK_QUEUE_SIZE 5 7 FORCE_CACHE_MISS 8 8 INVALIDATE_ALL 9 9 DISABLE_2M_CACHE 10 10 DISABLE_CACHING_SPECULATIVE_RETURNS 11 11 DISABLE_CACHING_FAULT_RETURNS 14 14 DEBUG_BUS_SELECT 15 16 DEBUG_ECO 17 18 EFFECTIVE_2M_CACHE_SIZE 19 22 CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD 23 30 CLEAR_PARITY_ERROR_INFO 31 31 mmATC_L2_CACHE_DATA0 0 0xcd9 4 0 4294967295 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 24 VIRTUAL_PAGE_ADDRESS_HIGH 25 28 mmATC_L2_CACHE_DATA1 0 0xcda 1 0 4294967295 VIRTUAL_PAGE_ADDRESS_LOW 0 31 mmATC_L2_CACHE_DATA2 0 0xcdb 1 0 4294967295 PHYSICAL_PAGE_ADDRESS_LOW 0 27 mmATC_L1_CNTL 0 0xcdc 3 0 4294967295 DONT_NEED_ATS_BEHAVIOR 0 1 NEED_ATS_BEHAVIOR 2 2 NEED_ATS_SNOOP_DEFAULT 4 4 mmATC_L1_ADDRESS_OFFSET 0 0xcdd 1 0 4294967295 LOGICAL_ADDRESS 0 31 mmATC_L1RD_DEBUG_TLB 0 0xcde 9 0 4294967295 DISABLE_FRAGMENTS 0 0 DISABLE_INVALIDATE_BY_ADDRESS_RANGE 1 1 EFFECTIVE_CAM_SIZE 4 7 EFFECTIVE_WORK_QUEUE_SIZE 8 10 CREDITS_L1_L2 12 17 CREDITS_L1_RPB 20 27 DEBUG_ECO 28 29 INVALIDATE_ALL 30 30 DISABLE_CACHING_FAULT_RETURNS 31 31 mmATC_L1WR_DEBUG_TLB 0 0xcdf 9 0 4294967295 DISABLE_FRAGMENTS 0 0 DISABLE_INVALIDATE_BY_ADDRESS_RANGE 1 1 EFFECTIVE_CAM_SIZE 4 7 EFFECTIVE_WORK_QUEUE_SIZE 8 10 CREDITS_L1_L2 12 17 CREDITS_L1_RPB 20 27 DEBUG_ECO 28 29 INVALIDATE_ALL 30 30 DISABLE_CACHING_FAULT_RETURNS 31 31 mmATC_L1RD_STATUS 0 0xce0 5 0 4294967295 BUSY 0 0 DEADLOCK_DETECTION 1 1 BAD_NEED_ATS 8 8 CAM_PARITY_ERRORS 12 16 CAM_INDEX 17 21 mmATC_L1WR_STATUS 0 0xce1 5 0 4294967295 BUSY 0 0 DEADLOCK_DETECTION 1 1 BAD_NEED_ATS 8 8 CAM_PARITY_ERRORS 12 16 CAM_INDEX 17 21 mmATC_L1RD_DEBUG2_TLB 0 0xce2 6 0 4294967295 XNACK_RETRY_PERIOD 0 11 XNACK_RETRY_MODE 14 15 INJECT_SOFT_PARITY_ERROR 16 16 INJECT_HARD_PARITY_ERROR 17 17 CLEAR_CAM_PARITY_ERROR 18 18 CAM_INDEX 19 23 mmATC_L1WR_DEBUG2_TLB 0 0xce3 6 0 4294967295 XNACK_RETRY_PERIOD 0 11 XNACK_RETRY_MODE 14 15 INJECT_SOFT_PARITY_ERROR 16 16 INJECT_HARD_PARITY_ERROR 17 17 CLEAR_CAM_PARITY_ERROR 18 18 CAM_INDEX 19 23 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0 0xce6 16 0 4294967295 VMID0_REMAPPING_FINISHED 0 0 VMID1_REMAPPING_FINISHED 1 1 VMID2_REMAPPING_FINISHED 2 2 VMID3_REMAPPING_FINISHED 3 3 VMID4_REMAPPING_FINISHED 4 4 VMID5_REMAPPING_FINISHED 5 5 VMID6_REMAPPING_FINISHED 6 6 VMID7_REMAPPING_FINISHED 7 7 VMID8_REMAPPING_FINISHED 8 8 VMID9_REMAPPING_FINISHED 9 9 VMID10_REMAPPING_FINISHED 10 10 VMID11_REMAPPING_FINISHED 11 11 VMID12_REMAPPING_FINISHED 12 12 VMID13_REMAPPING_FINISHED 13 13 VMID14_REMAPPING_FINISHED 14 14 VMID15_REMAPPING_FINISHED 15 15 mmATC_VMID0_PASID_MAPPING 0 0xce7 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID1_PASID_MAPPING 0 0xce8 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID2_PASID_MAPPING 0 0xce9 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID3_PASID_MAPPING 0 0xcea 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID4_PASID_MAPPING 0 0xceb 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID5_PASID_MAPPING 0 0xcec 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID6_PASID_MAPPING 0 0xced 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID7_PASID_MAPPING 0 0xcee 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID8_PASID_MAPPING 0 0xcef 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID9_PASID_MAPPING 0 0xcf0 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID10_PASID_MAPPING 0 0xcf1 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID11_PASID_MAPPING 0 0xcf2 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID12_PASID_MAPPING 0 0xcf3 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID13_PASID_MAPPING 0 0xcf4 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID14_PASID_MAPPING 0 0xcf5 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_VMID15_PASID_MAPPING 0 0xcf6 3 0 4294967295 PASID 0 15 NO_INVALIDATION 30 30 VALID 31 31 mmATC_ATS_VMID_STATUS 0 0xd07 16 0 4294967295 VMID0_OUTSTANDING 0 0 VMID1_OUTSTANDING 1 1 VMID2_OUTSTANDING 2 2 VMID3_OUTSTANDING 3 3 VMID4_OUTSTANDING 4 4 VMID5_OUTSTANDING 5 5 VMID6_OUTSTANDING 6 6 VMID7_OUTSTANDING 7 7 VMID8_OUTSTANDING 8 8 VMID9_OUTSTANDING 9 9 VMID10_OUTSTANDING 10 10 VMID11_OUTSTANDING 11 11 VMID12_OUTSTANDING 12 12 VMID13_OUTSTANDING 13 13 VMID14_OUTSTANDING 14 14 VMID15_OUTSTANDING 15 15 mmATC_ATS_SMU_STATUS 0 0xd08 1 0 4294967295 VDDGFX_POWERED_DOWN 0 0 mmATC_L2_CNTL3 0 0xd09 5 0 4294967295 ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING 0 6 ENABLE_FREE_COUNTER 7 7 L2_CACHE_EVICTION_THRESHOLD 8 12 DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION 13 13 L2_DELAY_SEND_INVALIDATION_REQUEST 14 16 mmATC_L2_STATUS 0 0xd0a 2 0 4294967295 BUSY 0 0 PARITY_ERROR_INFO 1 29 mmATC_L2_STATUS2 0 0xd0b 2 0 4294967295 CACHE_ADDRESS_MODE 0 2 PARITY_ERROR_INFO 3 10 mmGMCON_RENG_RAM_INDEX 0 0xd40 1 0 4294967295 RENG_RAM_INDEX 0 9 mmGMCON_RENG_RAM_DATA 0 0xd41 1 0 4294967295 RENG_RAM_DATA 0 31 mmGMCON_RENG_EXECUTE 0 0xd42 5 0 4294967295 RENG_EXECUTE_ON_PWR_UP 0 0 RENG_EXECUTE_NOW 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_DSP_END_PTR 12 21 RENG_EXECUTE_END_PTR 22 31 mmGMCON_MISC 0 0xd43 15 0 4294967295 RENG_EXECUTE_NOW_MODE 10 10 RENG_EXECUTE_ON_REG_UPDATE 11 11 RENG_SRBM_CREDITS_MCD 12 15 STCTRL_STUTTER_EN 16 16 STCTRL_GMC_IDLE_THRESHOLD 17 18 STCTRL_SRBM_IDLE_THRESHOLD 19 20 STCTRL_IGNORE_PRE_SR 21 21 STCTRL_IGNORE_ALLOW_STOP 22 22 STCTRL_IGNORE_SR_COMMIT 23 23 STCTRL_IGNORE_PROTECTION_FAULT 24 24 STCTRL_DISABLE_ALLOW_SR 25 25 STCTRL_DISABLE_GMC_OFFLINE 26 26 CRITICAL_REGS_LOCK 27 27 ALLOW_DEEP_SLEEP_MODE 28 30 STCTRL_FORCE_ALLOW_SR 31 31 mmGMCON_MISC2 0 0xd44 7 0 4294967295 GMCON_MISC2_RESERVED0 0 5 STCTRL_NONDISP_IDLE_THRESHOLD 6 10 RENG_SR_HOLD_THRESHOLD 11 16 GMCON_MISC2_RESERVED1 17 28 STCTRL_IGNORE_ARB_BUSY 29 29 STCTRL_EXTEND_GMC_OFFLINE 30 30 STCTRL_TIMER_PULSE_OVERRIDE 31 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0 0xd45 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE0 0 15 STCTRL_REGISTER_SAVE_LIMIT0 16 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0 0xd46 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE1 0 15 STCTRL_REGISTER_SAVE_LIMIT1 16 31 mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0 0xd47 2 0 4294967295 STCTRL_REGISTER_SAVE_BASE2 0 15 STCTRL_REGISTER_SAVE_LIMIT2 16 31 mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0xd48 2 0 4294967295 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0xd49 2 0 4294967295 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmGMCON_PERF_MON_CNTL0 0 0xd4a 8 0 4294967295 START_THRESH 0 11 STOP_THRESH 12 23 START_MODE 24 25 STOP_MODE 26 27 ALLOW_WRAP 28 28 THRESH_CNTR_ID_EXT 29 29 START_TRIG_ID_EXT 30 30 STOP_TRIG_ID_EXT 31 31 mmGMCON_PERF_MON_CNTL1 0 0xd4b 5 0 4294967295 THRESH_CNTR_ID 0 5 START_TRIG_ID 6 11 STOP_TRIG_ID 12 17 MON0_ID 18 24 MON1_ID 25 31 mmGMCON_PERF_MON_RSLT0 0 0xd4c 1 0 4294967295 COUNT 0 31 mmGMCON_PERF_MON_RSLT1 0 0xd4d 1 0 4294967295 COUNT 0 31 mmGMCON_PGFSM_CONFIG 0 0xd4e 10 0 4294967295 FSM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE 12 12 READ 13 13 RSRVD 14 26 SRBM_OVERRIDE 27 27 REG_ADDR 28 31 mmGMCON_PGFSM_WRITE 0 0xd4f 1 0 4294967295 WRITE_VALUE 0 31 mmGMCON_PGFSM_READ 0 0xd50 3 0 4294967295 READ_VALUE 0 23 PGFSM_SELECT 24 27 SERDES_MASTER_BUSY 28 28 mmGMCON_MISC3 0 0xd51 6 0 4294967295 RENG_DISABLE_MCC 0 7 RENG_DISABLE_MCD 8 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 27 STCTRL_IGNORE_ALLOW_STUTTER 28 28 RENG_MEM_LS_ENABLE 29 29 STCTRL_EXCLUDE_NONMEM_CLIENTS 30 30 mmGMCON_MASK 0 0xd52 5 0 4294967295 STCTRL_BUSY_MASK_ACP_RD 0 0 STCTRL_BUSY_MASK_ACP_WR 1 1 STCTRL_BUSY_MASK_VCE_RD 2 2 STCTRL_BUSY_MASK_VCE_WR 3 3 STCTRL_SR_HANDSHAKE_MASK 4 11 mmGMCON_LPT_TARGET 0 0xd53 1 0 4294967295 STCTRL_LPT_TARGET 0 31 mmGMCON_DEBUG 0 0xd5f 6 0 4294967295 GFX_STALL 0 0 GFX_CLEAR 1 1 GMCON_DEBUG_RESERVED0 2 2 SR_COMMIT_STATE 3 3 STCTRL_ST 4 7 MISC_FLAGS 8 31 mmVM_L2_CNTL 0 0x500 15 0 4294967295 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_CACHE_4K_SWAP_TAG_INDEX_LSBS 26 27 L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS 28 30 mmVM_L2_CNTL2 0 0x501 7 0 4294967295 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_CACHE_BIGK_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmVM_L2_CNTL3 0 0x502 10 0 4294967295 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 mmVM_L2_STATUS 0 0x503 2 0 4294967295 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 mmVM_CONTEXT0_CNTL 0 0x504 22 0 4294967295 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 6 6 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 PDE0_PROTECTION_FAULT_ENABLE_SAVE 11 11 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 VALID_PROTECTION_FAULT_ENABLE_SAVE 14 14 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_SAVE 17 17 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 18 18 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 19 19 WRITE_PROTECTION_FAULT_ENABLE_SAVE 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 EXECUTE_PROTECTION_FAULT_ENABLE_SAVE 23 23 PAGE_TABLE_BLOCK_SIZE 24 27 mmVM_CONTEXT1_CNTL 0 0x505 22 0 4294967295 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 6 6 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 PDE0_PROTECTION_FAULT_ENABLE_SAVE 11 11 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 VALID_PROTECTION_FAULT_ENABLE_SAVE 14 14 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_SAVE 17 17 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 18 18 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 19 19 WRITE_PROTECTION_FAULT_ENABLE_SAVE 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 EXECUTE_PROTECTION_FAULT_ENABLE_SAVE 23 23 PAGE_TABLE_BLOCK_SIZE 24 27 mmVM_DUMMY_PAGE_FAULT_CNTL 0 0x506 3 0 4294967295 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MASK 2 3 mmVM_DUMMY_PAGE_FAULT_ADDR 0 0x507 1 0 4294967295 DUMMY_PAGE_ADDR 0 27 mmVM_CONTEXT0_CNTL2 0 0x50c 5 0 4294967295 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT 1 1 ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT 2 2 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 3 3 WAIT_FOR_IDLE_WHEN_INVALIDATE 4 4 mmVM_CONTEXT1_CNTL2 0 0x50d 5 0 4294967295 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT 1 1 ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT 2 2 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 3 3 WAIT_FOR_IDLE_WHEN_INVALIDATE 4 4 mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0 0x50e 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0 0x50f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0 0x510 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0 0x511 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0 0x512 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0 0x513 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0 0x514 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0 0x515 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_INVALIDATE_REQUEST 0 0x51e 16 0 4294967295 INVALIDATE_DOMAIN_0 0 0 INVALIDATE_DOMAIN_1 1 1 INVALIDATE_DOMAIN_2 2 2 INVALIDATE_DOMAIN_3 3 3 INVALIDATE_DOMAIN_4 4 4 INVALIDATE_DOMAIN_5 5 5 INVALIDATE_DOMAIN_6 6 6 INVALIDATE_DOMAIN_7 7 7 INVALIDATE_DOMAIN_8 8 8 INVALIDATE_DOMAIN_9 9 9 INVALIDATE_DOMAIN_10 10 10 INVALIDATE_DOMAIN_11 11 11 INVALIDATE_DOMAIN_12 12 12 INVALIDATE_DOMAIN_13 13 13 INVALIDATE_DOMAIN_14 14 14 INVALIDATE_DOMAIN_15 15 15 mmVM_INVALIDATE_RESPONSE 0 0x51f 16 0 4294967295 DOMAIN_INVALIDATED_0 0 0 DOMAIN_INVALIDATED_1 1 1 DOMAIN_INVALIDATED_2 2 2 DOMAIN_INVALIDATED_3 3 3 DOMAIN_INVALIDATED_4 4 4 DOMAIN_INVALIDATED_5 5 5 DOMAIN_INVALIDATED_6 6 6 DOMAIN_INVALIDATED_7 7 7 DOMAIN_INVALIDATED_8 8 8 DOMAIN_INVALIDATED_9 9 9 DOMAIN_INVALIDATED_10 10 10 DOMAIN_INVALIDATED_11 11 11 DOMAIN_INVALIDATED_12 12 12 DOMAIN_INVALIDATED_13 13 13 DOMAIN_INVALIDATED_14 14 14 DOMAIN_INVALIDATED_15 15 15 mmVM_PRT_APERTURE0_LOW_ADDR 0 0x52c 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE1_LOW_ADDR 0 0x52d 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE2_LOW_ADDR 0 0x52e 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE3_LOW_ADDR 0 0x52f 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE0_HIGH_ADDR 0 0x530 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE1_HIGH_ADDR 0 0x531 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE2_HIGH_ADDR 0 0x532 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_APERTURE3_HIGH_ADDR 0 0x533 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_PRT_CNTL 0 0x534 7 0 4294967295 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS 0 0 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS 1 1 L2_CACHE_STORE_INVALID_ENTRIES 2 2 L1_TLB_STORE_INVALID_ENTRIES 3 3 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS 4 4 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS 5 5 MASK_PDE0_FAULT 6 6 mmVM_CONTEXTS_DISABLE 0 0x535 16 0 4294967295 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0 0x536 5 0 4294967295 PROTECTIONS 0 7 MEMORY_CLIENT_ID 12 20 MEMORY_CLIENT_RW 24 24 VMID 25 28 ATOMIC 29 29 mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0 0x537 5 0 4294967295 PROTECTIONS 0 7 MEMORY_CLIENT_ID 12 20 MEMORY_CLIENT_RW 24 24 VMID 25 28 ATOMIC 29 29 mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0 0x538 1 0 4294967295 NAME 0 31 mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0 0x539 1 0 4294967295 NAME 0 31 mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0 0x53e 1 0 4294967295 LOGICAL_PAGE_ADDR 0 27 mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0 0x53f 1 0 4294967295 LOGICAL_PAGE_ADDR 0 27 mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0 0x546 1 0 4294967295 PHYSICAL_PAGE_ADDR 0 27 mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0 0x547 1 0 4294967295 PHYSICAL_PAGE_ADDR 0 27 mmVM_FAULT_CLIENT_ID 0 0x54e 4 0 4294967295 MEMORY_CLIENT 0 8 MEMORY_CLIENT_MASK 9 17 MEMORY_CLIENT_ID_MSB 18 18 MEMORY_CLIENT_ID_MASK_MSB 19 19 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0 0x54f 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0 0x550 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0 0x551 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0 0x552 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0 0x553 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0 0x554 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0 0x555 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0 0x556 1 0 4294967295 PHYSICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0 0x557 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0 0x558 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0 0x55f 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0 0x560 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_DEBUG 0 0x56f 1 0 4294967295 FLAGS 0 31 mmVM_L2_CG 0 0x570 4 0 4294967295 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 OVERRIDE 20 20 mmVM_L2_BANK_SELECT_MASKA 0 0x572 1 0 4294967295 BANK_SELECT_MASK 0 27 mmVM_L2_BANK_SELECT_MASKB 0 0x573 1 0 4294967295 BANK_SELECT_MASK 0 6 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0 0x575 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0 0x576 1 0 4294967295 LOGICAL_PAGE_NUMBER 0 27 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0 0x577 1 0 4294967295 PHYSICAL_PAGE_OFFSET 0 27 mmVM_L2_CNTL4 0 0x578 13 0 4294967295 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED 7 7 VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP 8 8 VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL 9 9 VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED 10 10 VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP 11 11 VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL 12 12 VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED 13 13 VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP 14 14 VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL 15 15 VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED 16 16 VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP 17 17 mmVM_L2_BANK_SELECT_RESERVED_CID 0 0x579 5 0 4294967295 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmMC_VM_FB_SIZE_OFFSET_VF0 0 0xf980 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF1 0 0xf981 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF2 0 0xf982 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF3 0 0xf983 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF4 0 0xf984 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF5 0 0xf985 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF6 0 0xf986 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF7 0 0xf987 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF8 0 0xf988 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF9 0 0xf989 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF10 0 0xf98a 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF11 0 0xf98b 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF12 0 0xf98c 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF13 0 0xf98d 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF14 0 0xf98e 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF15 0 0xf98f 2 0 4294967295 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_NB_MMIOBASE 0 0xf990 1 0 4294967295 MMIOBASE 0 31 mmMC_VM_NB_MMIOLIMIT 0 0xf991 1 0 4294967295 MMIOLIMIT 0 31 mmMC_VM_NB_PCI_CTRL 0 0xf992 1 0 4294967295 MMIOENABLE 23 23 mmMC_VM_NB_PCI_ARB 0 0xf993 1 0 4294967295 VGA_HOLE 3 3 mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0 0xf994 1 0 4294967295 TOP_OF_DRAM 23 31 mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0 0xf995 2 0 4294967295 ENABLE 0 0 LOWER_TOM2 23 31 mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0 0xf996 1 0 4294967295 UPPER_TOM2 0 7 mmMC_VM_NB_TOP_OF_DRAM3 0 0xf997 2 0 4294967295 TOM3_LIMIT 0 29 TOM3_ENABLE 31 31 mmMC_VM_MARC_BASE_LO_0 0 0xf998 1 0 4294967295 MARC_BASE_LO_0 12 31 mmMC_VM_MARC_BASE_LO_1 0 0xf99e 1 0 4294967295 MARC_BASE_LO_1 12 31 mmMC_VM_MARC_BASE_LO_2 0 0xf9a4 1 0 4294967295 MARC_BASE_LO_2 12 31 mmMC_VM_MARC_BASE_LO_3 0 0xf9aa 1 0 4294967295 MARC_BASE_LO_3 12 31 mmMC_VM_MARC_BASE_HI_0 0 0xf999 1 0 4294967295 MARC_BASE_HI_0 0 19 mmMC_VM_MARC_BASE_HI_1 0 0xf99f 1 0 4294967295 MARC_BASE_HI_1 0 19 mmMC_VM_MARC_BASE_HI_2 0 0xf9a5 1 0 4294967295 MARC_BASE_HI_2 0 19 mmMC_VM_MARC_BASE_HI_3 0 0xf9ab 1 0 4294967295 MARC_BASE_HI_3 0 19 mmMC_VM_MARC_RELOC_LO_0 0 0xf99a 3 0 4294967295 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmMC_VM_MARC_RELOC_LO_1 0 0xf9a0 3 0 4294967295 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmMC_VM_MARC_RELOC_LO_2 0 0xf9a6 3 0 4294967295 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmMC_VM_MARC_RELOC_LO_3 0 0xf9ac 3 0 4294967295 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmMC_VM_MARC_RELOC_HI_0 0 0xf99b 1 0 4294967295 MARC_RELOC_HI_0 0 19 mmMC_VM_MARC_RELOC_HI_1 0 0xf9a1 1 0 4294967295 MARC_RELOC_HI_1 0 19 mmMC_VM_MARC_RELOC_HI_2 0 0xf9a7 1 0 4294967295 MARC_RELOC_HI_2 0 19 mmMC_VM_MARC_RELOC_HI_3 0 0xf9ad 1 0 4294967295 MARC_RELOC_HI_3 0 19 mmMC_VM_MARC_LEN_LO_0 0 0xf99c 1 0 4294967295 MARC_LEN_LO_0 12 31 mmMC_VM_MARC_LEN_LO_1 0 0xf9a2 1 0 4294967295 MARC_LEN_LO_1 12 31 mmMC_VM_MARC_LEN_LO_2 0 0xf9a8 1 0 4294967295 MARC_LEN_LO_2 12 31 mmMC_VM_MARC_LEN_LO_3 0 0xf9ae 1 0 4294967295 MARC_LEN_LO_3 12 31 mmMC_VM_MARC_LEN_HI_0 0 0xf99d 1 0 4294967295 MARC_LEN_HI_0 0 19 mmMC_VM_MARC_LEN_HI_1 0 0xf9a3 1 0 4294967295 MARC_LEN_HI_1 0 19 mmMC_VM_MARC_LEN_HI_2 0 0xf9a9 1 0 4294967295 MARC_LEN_HI_2 0 19 mmMC_VM_MARC_LEN_HI_3 0 0xf9af 1 0 4294967295 MARC_LEN_HI_3 0 19 mmMC_VM_MARC_CNTL 0 0xf9b0 1 0 4294967295 ENABLE_ALL_CLIENTS 0 0 mmMC_ARB_HARSH_EN_RD 0 0xdc0 4 0 4294967295 TX_PRI 0 7 BW_PRI 8 15 FIX_PRI 16 23 ST_PRI 24 31 mmMC_ARB_HARSH_EN_WR 0 0xdc1 4 0 4294967295 TX_PRI 0 7 BW_PRI 8 15 FIX_PRI 16 23 ST_PRI 24 31 mmMC_ARB_HARSH_TX_HI0_RD 0 0xdc2 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_HI0_WR 0 0xdc3 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_HI1_RD 0 0xdc4 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_HI1_WR 0 0xdc5 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_LO0_RD 0 0xdc6 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_LO0_WR 0 0xdc7 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_TX_LO1_RD 0 0xdc8 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_TX_LO1_WR 0 0xdc9 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWPERIOD0_RD 0 0xdca 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWPERIOD0_WR 0 0xdcb 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWPERIOD1_RD 0 0xdcc 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWPERIOD1_WR 0 0xdcd 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWCNT0_RD 0 0xdce 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWCNT0_WR 0 0xdcf 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_BWCNT1_RD 0 0xdd0 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_BWCNT1_WR 0 0xdd1 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_SAT0_RD 0 0xdd2 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_SAT0_WR 0 0xdd3 4 0 4294967295 GROUP0 0 7 GROUP1 8 15 GROUP2 16 23 GROUP3 24 31 mmMC_ARB_HARSH_SAT1_RD 0 0xdd4 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_SAT1_WR 0 0xdd5 4 0 4294967295 GROUP4 0 7 GROUP5 8 15 GROUP6 16 23 GROUP7 24 31 mmMC_ARB_HARSH_CTL_RD 0 0xdd6 8 0 4294967295 FORCE_HIGHEST 0 7 HARSH_RR 8 8 BANK_AGE_ONLY 9 9 USE_LEGACY_HARSH 10 10 BWCNT_CATCHUP 11 11 ST_MODE 12 13 FORCE_STALL 14 21 PERF_MON_SEL 22 24 mmMC_ARB_HARSH_CTL_WR 0 0xdd7 8 0 4294967295 FORCE_HIGHEST 0 7 HARSH_RR 8 8 BANK_AGE_ONLY 9 9 USE_LEGACY_HARSH 10 10 BWCNT_CATCHUP 11 11 ST_MODE 12 13 FORCE_STALL 14 21 PERF_MON_SEL 22 24 mmMC_ARB_GRUB_PRIORITY1_RD 0 0xdd8 16 0 4294967295 CB0 0 1 CBCMASK0 2 3 CBFMASK0 4 5 DB0 6 7 DBHTILE0 8 9 DBSTEN0 10 11 TC0 12 13 ACPG 14 15 ACPO 16 17 DMIF 18 19 DMIF_EXT0 20 21 DMIF_EXT1 22 23 DMIF_TW 24 25 MCIF 26 27 RLC 28 29 VMC 30 31 mmMC_ARB_GRUB_PRIORITY1_WR 0 0xdd9 16 0 4294967295 CB0 0 1 CBCMASK0 2 3 CBFMASK0 4 5 CBIMMED0 6 7 DB0 8 9 DBHTILE0 10 11 DBSTEN0 12 13 TC0 14 15 SH 16 17 ACPG 18 19 ACPO 20 21 MCIF 22 23 RLC 24 25 SDMA1 26 27 SMU 28 29 VCE0 30 31 mmMC_ARB_GRUB_PRIORITY2_RD 0 0xdda 16 0 4294967295 SDMA1 0 1 SMU 2 3 VCE0 4 5 VCE1 6 7 XDMAM 8 9 SDMA0 10 11 HDP 12 13 UMC 14 15 UVD 16 17 UVD_EXT0 18 19 UVD_EXT1 20 21 SEM 22 23 SAMMSP 24 25 VP8 26 27 ISP 28 29 RSV2 30 31 mmMC_ARB_GRUB_PRIORITY2_WR 0 0xddb 16 0 4294967295 VCE1 0 1 SAMMSP 2 3 XDMA 4 5 XDMAM 6 7 SDMA0 8 9 HDP 10 11 UMC 12 13 UVD 14 15 UVD_EXT0 16 17 UVD_EXT1 18 19 XDP 20 21 SEM 22 23 IH 24 25 VP8 26 27 ISP 28 29 VIN0 30 31 mmMC_FUS_DRAM0_CS0_BASE 0 0xa05 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS0_BASE 0 0xa06 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS1_BASE 0 0xa07 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS1_BASE 0 0xa08 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS2_BASE 0 0xa09 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS2_BASE 0 0xa0a 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS3_BASE 0 0xa0b 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM1_CS3_BASE 0 0xa0c 3 0 4294967295 CSENABLE 0 0 BASEADDR21_11 5 15 BASEADDR38_27 19 30 mmMC_FUS_DRAM0_CS01_MASK 0 0xa0d 0 0 4294967295 mmMC_FUS_DRAM1_CS01_MASK 0 0xa0e 0 0 4294967295 mmMC_FUS_DRAM0_CS23_MASK 0 0xa0f 0 0 4294967295 mmMC_FUS_DRAM1_CS23_MASK 0 0xa10 0 0 4294967295 mmMC_FUS_DRAM0_BANK_ADDR_MAPPING 0 0xa11 4 0 4294967295 DIMM0ADDRMAP 0 3 DIMM1ADDRMAP 4 7 BANKSWIZZLEMODE 8 8 BANKSWAP 9 9 mmMC_FUS_DRAM1_BANK_ADDR_MAPPING 0 0xa12 4 0 4294967295 DIMM0ADDRMAP 0 3 DIMM1ADDRMAP 4 7 BANKSWIZZLEMODE 8 8 BANKSWAP 9 9 mmMC_FUS_DRAM0_CTL_BASE 0 0xa13 4 0 4294967295 DCTSEL 0 2 DCTINTLVEN 3 6 DCTBASEADDR 7 27 DCTOFFSETEN 28 28 mmMC_FUS_DRAM1_CTL_BASE 0 0xa14 4 0 4294967295 DCTSEL 0 2 DCTINTLVEN 3 6 DCTBASEADDR 7 27 DCTOFFSETEN 28 28 mmMC_FUS_DRAM0_CTL_LIMIT 0 0xa15 2 0 4294967295 DCTLIMITADDR 0 20 DRAMHOLEVALID 21 21 mmMC_FUS_DRAM1_CTL_LIMIT 0 0xa16 2 0 4294967295 DCTLIMITADDR 0 20 DRAMHOLEVALID 21 21 mmMC_FUS_DRAM_CTL_HIGH_01 0 0xa17 2 0 4294967295 DCTHIGHADDROFF0 0 11 DCTHIGHADDROFF1 12 23 mmMC_FUS_DRAM_CTL_HIGH_23 0 0xa18 2 0 4294967295 DCTHIGHADDROFF2 0 11 DCTHIGHADDROFF3 12 23 mmMC_FUS_DRAM_MODE 0 0xa19 5 0 4294967295 DCTSELINTLVADDR 0 2 DRAMTYPE 3 5 DRAMHOLEOFFSET 6 14 DDR3LPX32 15 15 BANKGROUPSWAP 16 16 mmMC_FUS_DRAM_APER_BASE 0 0xa1a 1 0 4294967295 BASE 0 19 mmMC_FUS_DRAM_APER_TOP 0 0xa1b 1 0 4294967295 TOP 0 19 mmMC_FUS_DRAM_APER_DEF 0 0xa1e 2 0 4294967295 DEF 0 27 LOCK_MC_FUS_DRAM_REGS 28 28 mmMC_FUS_ARB_GARLIC_ISOC_PRI 0 0xa1f 25 0 4294967295 DMIF_RD_TOKURG_EN 0 0 UVD_RD_TOKURG_EN 1 1 VCE_RD_TOKURG_EN 2 2 ACP_RD_TOKURG_EN 3 3 DMIF_RD_PRIURG_EN 4 4 UVD_RD_PRIURG_EN 5 5 VCE_RD_PRIURG_EN 6 6 ACP_RD_PRIURG_EN 7 7 DMIF_RD_ISOC_EN 8 8 UVD_RD_ISOC_EN 9 9 VCE_RD_ISOC_EN 10 10 MCIF_RD_ISOC_EN 11 11 UMC_RD_ISOC_EN 12 12 VCEU_RD_ISOC_EN 13 13 ACP_RD_ISOC_EN 14 14 REQPRI_OVERRIDE_EN 15 15 REQPRI_OVERRIDE_VAL 16 17 PRIPRMTE_OVERRIDE_EN 18 18 TOKURG_OVERRIDE_EN 19 19 PRIURG_OVERRIDE_EN 20 20 PRIPRMTE_OVERRIDE_VAL 21 21 TOKURG_OVERRIDE_VAL 22 22 PRIURG_OVERRIDE_VAL 23 23 GARLIC_REQ_CREDITS 24 28 MM_REL_LATE 29 29 mmMC_FUS_ARB_GARLIC_CNTL 0 0xa20 6 0 4294967295 RX_RDRESP_FIFO_PTR_INIT_VALUE 0 7 RX_WRRESP_FIFO_PTR_INIT_VALUE 8 14 EN_64_BYTE_WRITE 15 15 EDC_RESPONSE_ENABLE 16 16 OUTSTANDING_RDRESP_LIMIT 17 25 OUTSTANDING_WRRESP_LIMIT 26 31 mmMC_FUS_ARB_GARLIC_WR_PRI 0 0xa21 16 0 4294967295 CB_WR_PRI 0 1 DB_WR_PRI 2 3 TC_WR_PRI 4 5 CP_WR_PRI 6 7 HDP_WR_PRI 8 9 XDP_WR_PRI 10 11 UMC_WR_PRI 12 13 UVD_WR_PRI 14 15 RLC_WR_PRI 16 17 IH_WR_PRI 18 19 SDMA_WR_PRI 20 21 SEM_WR_PRI 22 23 SH_WR_PRI 24 25 MCIF_WR_PRI 26 27 VCE_WR_PRI 28 29 VCEU_WR_PRI 30 31 mmMC_FUS_ARB_GARLIC_WR_PRI2 0 0xa22 3 0 4294967295 SMU_WR_PRI 0 1 SAM_WR_PRI 2 3 ACP_WR_PRI 4 5 mmMC_CG_DATAPORT 0 0xa32 1 0 4294967295 DATA_FIELD 0 31 mmMC_GRUB_PROBE_MAP 0 0xa33 8 0 4294967295 ADDR0_TO_TC_MAP 0 1 ADDR1_TO_TC_MAP 2 3 ADDR2_TO_TC_MAP 4 5 ADDR3_TO_TC_MAP 6 7 ADDR0_TO_GRUB_MAP 8 8 ADDR1_TO_GRUB_MAP 9 9 ADDR2_TO_GRUB_MAP 10 10 ADDR3_TO_GRUB_MAP 11 11 mmMC_GRUB_POST_PROBE_DELAY 0 0xa34 3 0 4294967295 REQ_TO_RSP_DELAY 0 4 REQLCL_TO_RET_DELAY 8 12 REQREM_TO_RET_DELAY 16 20 mmMC_GRUB_PROBE_CREDITS 0 0xa35 5 0 4294967295 CREDITS_LIMIT_LO 0 5 CREDITS_LIMIT_HI 8 13 INTPRB_FIFO_LEVEL 15 15 INTPRB_TIMEOUT_THRESH 16 18 MEM_TIMEOUT_THRESH 20 22 mmMC_GRUB_FEATURES 0 0xa36 16 0 4294967295 WR_COMBINE_OFF 0 0 SCLK_CG_DISABLE 1 1 PRB_FILTER_DISABLE 2 2 ARB_NRT_STACK_DISABLE 3 3 ARB_FIXED_PRIORITY 4 4 PRIORITY_UPDATE_DISABLE 5 5 RT_BYPASS_OFF 6 6 SYNC_ON_ERROR_DISABLE 7 7 SYNC_REFLECT_DISABLE 8 8 ARB_STALL_EN 10 10 CREDIT_STALL_EN 11 11 ARB_STALL_SET_SEL 12 13 ARB_STALL_CLR_SEL 14 15 CREDIT_STALL_SET_SEL 16 17 CREDIT_STALL_CLR_SEL 18 19 WR_REORDER_OFF 20 20 mmMC_GRUB_TX_CREDITS 0 0xa37 5 0 4294967295 SRCTAG_LIMIT 0 5 SRCTAG_RT_RESERVE 8 11 NPC_RT_RESERVE 12 15 NPD_RT_RESERVE 16 19 TX_FIFO_DEPTH 20 24 mmMC_GRUB_TCB_INDEX 0 0xa38 5 0 4294967295 INDEX 0 6 TCB0_WR_EN 8 8 TCB1_WR_EN 9 9 RD_EN 10 10 TCB_SEL 11 11 mmMC_GRUB_TCB_DATA_LO 0 0xa39 1 0 4294967295 DATA 0 31 mmMC_GRUB_TCB_DATA_HI 0 0xa3a 1 0 4294967295 DATA 0 31 mmMCIF_WB_BUFMGR_SW_CONTROL 0 0x5e78 7 0 4294967295 MCIF_WB_BUFMGR_ENABLE 0 0 MCIF_WB_BUF_DUALSIZE_REQ 1 1 MCIF_WB_BUFMGR_SW_INT_EN 4 4 MCIF_WB_BUFMGR_SW_INT_ACK 5 5 MCIF_WB_BUFMGR_SW_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_SW_LOCK 8 11 MCIF_WB_P_VMID 16 19 mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0 0x5e78 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0 0x5eb8 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0 0x5ef8 0 0 4294967295 mmMCIF_WB_BUFMGR_CUR_LINE_R 0 0x5e79 1 0 4294967295 MCIF_WB_BUFMGR_CUR_LINE_R 0 12 mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x5e79 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x5eb9 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0 0x5ef9 0 0 4294967295 mmMCIF_WB_BUFMGR_STATUS 0 0x5e7a 7 0 4294967295 MCIF_WB_BUFMGR_VCE_INT_STATUS 0 0 MCIF_WB_BUFMGR_SW_INT_STATUS 1 1 MCIF_WB_BUFMGR_CUR_BUF 4 6 MCIF_WB_BUF_DUALSIZE_STATUS 7 7 MCIF_WB_BUFMGR_BUFTAG 8 11 MCIF_WB_BUFMGR_CUR_LINE_L 12 24 MCIF_WB_BUFMGR_NEXT_BUF 28 30 mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0 0x5e7a 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0 0x5eba 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0 0x5efa 0 0 4294967295 mmMCIF_WB_BUF_PITCH 0 0x5e7b 2 0 4294967295 MCIF_WB_BUF_LUMA_PITCH 8 15 MCIF_WB_BUF_CHROMA_PITCH 24 31 mmMCIF_WB0_MCIF_WB_BUF_PITCH 0 0x5e7b 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_PITCH 0 0x5ebb 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_PITCH 0 0x5efb 0 0 4294967295 mmMCIF_WB_BUF_1_STATUS 0 0x5e7c 13 0 4294967295 MCIF_WB_BUF_1_ACTIVE 0 0 MCIF_WB_BUF_1_SW_LOCKED 1 1 MCIF_WB_BUF_1_VCE_LOCKED 2 2 MCIF_WB_BUF_1_OVERFLOW 3 3 MCIF_WB_BUF_1_DISABLE 4 4 MCIF_WB_BUF_1_MODE 5 7 MCIF_WB_BUF_1_BUFTAG 8 11 MCIF_WB_BUF_1_NXT_BUF 12 14 MCIF_WB_BUF_1_FIELD 15 15 MCIF_WB_BUF_1_CUR_LINE_L 16 28 MCIF_WB_BUF_1_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_1_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_1_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0 0x5e7c 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0 0x5ebc 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0 0x5efc 0 0 4294967295 mmMCIF_WB_BUF_1_STATUS2 0 0x5e7d 3 0 4294967295 MCIF_WB_BUF_1_CUR_LINE_R 0 12 MCIF_WB_BUF_1_NEW_CONTENT 13 13 MCIF_WB_BUF_1_COLOR_DEPTH 14 14 mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0 0x5e7d 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0 0x5ebd 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0 0x5efd 0 0 4294967295 mmMCIF_WB_BUF_2_STATUS 0 0x5e7e 13 0 4294967295 MCIF_WB_BUF_2_ACTIVE 0 0 MCIF_WB_BUF_2_SW_LOCKED 1 1 MCIF_WB_BUF_2_VCE_LOCKED 2 2 MCIF_WB_BUF_2_OVERFLOW 3 3 MCIF_WB_BUF_2_DISABLE 4 4 MCIF_WB_BUF_2_MODE 5 7 MCIF_WB_BUF_2_BUFTAG 8 11 MCIF_WB_BUF_2_NXT_BUF 12 14 MCIF_WB_BUF_2_FIELD 15 15 MCIF_WB_BUF_2_CUR_LINE_L 16 28 MCIF_WB_BUF_2_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_2_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_2_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0 0x5e7e 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0 0x5ebe 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0 0x5efe 0 0 4294967295 mmMCIF_WB_BUF_2_STATUS2 0 0x5e7f 3 0 4294967295 MCIF_WB_BUF_2_CUR_LINE_R 0 12 MCIF_WB_BUF_2_NEW_CONTENT 13 13 MCIF_WB_BUF_2_COLOR_DEPTH 14 14 mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0 0x5e7f 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0 0x5ebf 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0 0x5eff 0 0 4294967295 mmMCIF_WB_BUF_3_STATUS 0 0x5e80 13 0 4294967295 MCIF_WB_BUF_3_ACTIVE 0 0 MCIF_WB_BUF_3_SW_LOCKED 1 1 MCIF_WB_BUF_3_VCE_LOCKED 2 2 MCIF_WB_BUF_3_OVERFLOW 3 3 MCIF_WB_BUF_3_DISABLE 4 4 MCIF_WB_BUF_3_MODE 5 7 MCIF_WB_BUF_3_BUFTAG 8 11 MCIF_WB_BUF_3_NXT_BUF 12 14 MCIF_WB_BUF_3_FIELD 15 15 MCIF_WB_BUF_3_CUR_LINE_L 16 28 MCIF_WB_BUF_3_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_3_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_3_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0 0x5e80 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0 0x5ec0 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0 0x5f00 0 0 4294967295 mmMCIF_WB_BUF_3_STATUS2 0 0x5e81 3 0 4294967295 MCIF_WB_BUF_3_CUR_LINE_R 0 12 MCIF_WB_BUF_3_NEW_CONTENT 13 13 MCIF_WB_BUF_3_COLOR_DEPTH 14 14 mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0 0x5e81 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0 0x5ec1 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0 0x5f01 0 0 4294967295 mmMCIF_WB_BUF_4_STATUS 0 0x5e82 13 0 4294967295 MCIF_WB_BUF_4_ACTIVE 0 0 MCIF_WB_BUF_4_SW_LOCKED 1 1 MCIF_WB_BUF_4_VCE_LOCKED 2 2 MCIF_WB_BUF_4_OVERFLOW 3 3 MCIF_WB_BUF_4_DISABLE 4 4 MCIF_WB_BUF_4_MODE 5 7 MCIF_WB_BUF_4_BUFTAG 8 11 MCIF_WB_BUF_4_NXT_BUF 12 14 MCIF_WB_BUF_4_FIELD 15 15 MCIF_WB_BUF_4_CUR_LINE_L 16 28 MCIF_WB_BUF_4_LONG_LINE_ERROR 29 29 MCIF_WB_BUF_4_SHORT_LINE_ERROR 30 30 MCIF_WB_BUF_4_FRAME_LENGTH_ERROR 31 31 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0 0x5e82 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0 0x5ec2 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0 0x5f02 0 0 4294967295 mmMCIF_WB_BUF_4_STATUS2 0 0x5e83 3 0 4294967295 MCIF_WB_BUF_4_CUR_LINE_R 0 12 MCIF_WB_BUF_4_NEW_CONTENT 13 13 MCIF_WB_BUF_4_COLOR_DEPTH 14 14 mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0 0x5e83 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0 0x5ec3 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0 0x5f03 0 0 4294967295 mmMCIF_WB_ARBITRATION_CONTROL 0 0x5e84 2 0 4294967295 MCIF_WB_CLIENT_ARBITRATION_SLICE 0 1 MCIF_WB_TIME_PER_PIXEL 26 31 mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0 0x5e84 0 0 4294967295 mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0 0x5ec4 0 0 4294967295 mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0 0x5f04 0 0 4294967295 mmMCIF_WB_URGENCY_WATERMARK 0 0x5e85 2 0 4294967295 MCIF_WB_CLIENT0_URGENCY_WATERMARK 0 15 MCIF_WB_CLIENT1_URGENCY_WATERMARK 16 31 mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK 0 0x5e85 0 0 4294967295 mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK 0 0x5ec5 0 0 4294967295 mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK 0 0x5f05 0 0 4294967295 mmMCIF_WB_TEST_DEBUG_INDEX 0 0x5e86 2 0 4294967295 MCIF_WB_TEST_DEBUG_INDEX 0 7 MCIF_WB_TEST_DEBUG_WRITE_EN 8 8 mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0 0x5e86 0 0 4294967295 mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0 0x5ec6 0 0 4294967295 mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0 0x5f06 0 0 4294967295 mmMCIF_WB_TEST_DEBUG_DATA 0 0x5e87 1 0 4294967295 MCIF_WB_TEST_DEBUG_DATA 0 31 mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0 0x5e87 0 0 4294967295 mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0 0x5ec7 0 0 4294967295 mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0 0x5f07 0 0 4294967295 mmMCIF_WB_BUF_1_ADDR_Y 0 0x5e88 1 0 4294967295 MCIF_WB_BUF_1_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0 0x5e88 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0 0x5ec8 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0 0x5f08 0 0 4294967295 mmMCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x5e89 1 0 4294967295 MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x5e89 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x5ec9 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0 0x5f09 0 0 4294967295 mmMCIF_WB_BUF_1_ADDR_C 0 0x5e8a 1 0 4294967295 MCIF_WB_BUF_1_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0 0x5e8a 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0 0x5eca 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0 0x5f0a 0 0 4294967295 mmMCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x5e8b 1 0 4294967295 MCIF_WB_BUF_1_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x5e8b 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x5ecb 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0 0x5f0b 0 0 4294967295 mmMCIF_WB_BUF_2_ADDR_Y 0 0x5e8c 1 0 4294967295 MCIF_WB_BUF_2_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0 0x5e8c 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0 0x5ecc 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0 0x5f0c 0 0 4294967295 mmMCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x5e8d 1 0 4294967295 MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x5e8d 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x5ecd 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0 0x5f0d 0 0 4294967295 mmMCIF_WB_BUF_2_ADDR_C 0 0x5e8e 1 0 4294967295 MCIF_WB_BUF_2_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0 0x5e8e 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0 0x5ece 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0 0x5f0e 0 0 4294967295 mmMCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x5e8f 1 0 4294967295 MCIF_WB_BUF_2_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x5e8f 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x5ecf 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0 0x5f0f 0 0 4294967295 mmMCIF_WB_BUF_3_ADDR_Y 0 0x5e90 1 0 4294967295 MCIF_WB_BUF_3_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0 0x5e90 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0 0x5ed0 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0 0x5f10 0 0 4294967295 mmMCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x5e91 1 0 4294967295 MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x5e91 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x5ed1 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0 0x5f11 0 0 4294967295 mmMCIF_WB_BUF_3_ADDR_C 0 0x5e92 1 0 4294967295 MCIF_WB_BUF_3_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0 0x5e92 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0 0x5ed2 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0 0x5f12 0 0 4294967295 mmMCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x5e93 1 0 4294967295 MCIF_WB_BUF_3_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x5e93 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x5ed3 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0 0x5f13 0 0 4294967295 mmMCIF_WB_BUF_4_ADDR_Y 0 0x5e94 1 0 4294967295 MCIF_WB_BUF_4_ADDR_Y 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0 0x5e94 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0 0x5ed4 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0 0x5f14 0 0 4294967295 mmMCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x5e95 1 0 4294967295 MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x5e95 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x5ed5 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0 0x5f15 0 0 4294967295 mmMCIF_WB_BUF_4_ADDR_C 0 0x5e96 1 0 4294967295 MCIF_WB_BUF_4_ADDR_C 0 31 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0 0x5e96 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0 0x5ed6 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0 0x5f16 0 0 4294967295 mmMCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x5e97 1 0 4294967295 MCIF_WB_BUF_4_ADDR_C_OFFSET 0 17 mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x5e97 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x5ed7 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0 0x5f17 0 0 4294967295 mmMCIF_WB_BUFMGR_VCE_CONTROL 0 0x5e98 6 0 4294967295 MCIF_WB_BUFMGR_VCE_LOCK_IGNORE 0 0 MCIF_WB_BUFMGR_VCE_INT_EN 4 4 MCIF_WB_BUFMGR_VCE_INT_ACK 5 5 MCIF_WB_BUFMGR_VCE_SLICE_INT_EN 6 6 MCIF_WB_BUFMGR_VCE_LOCK 8 11 MCIF_WB_BUFMGR_SLICE_SIZE 16 28 mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x5e98 0 0 4294967295 mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x5ed8 0 0 4294967295 mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0 0x5f18 0 0 4294967295 mmMCIF_WB_HVVMID_CONTROL 0 0x5e99 2 0 4294967295 MCIF_WB_DEFAULT_VMID 8 11 MCIF_WB_ALLOWED_VMID_MASK 16 31 mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL 0 0x5e99 0 0 4294967295 mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL 0 0x5ed9 0 0 4294967295 mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL 0 0x5f19 0 0 4294967295