2491 regDAGB0_RDCLI0 0 0x0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI1 0 0x1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI2 0 0x2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI3 0 0x3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI4 0 0x4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI5 0 0x5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI6 0 0x6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI7 0 0x7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI8 0 0x8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI9 0 0x9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI10 0 0xa 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI11 0 0xb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI12 0 0xc 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI13 0 0xd 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI14 0 0xe 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RDCLI15 0 0xf 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_RD_CNTL 0 0x10 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB0_RD_GMI_CNTL 0 0x11 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB0_RD_ADDR_DAGB 0 0x12 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0 0x13 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x14 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB0_RD_CGTT_CLK_CTRL 0 0x15 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0 0x16 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0 0x17 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0 0x18 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0 0x19 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0 0x1a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0 0x1b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_RD_VC0_CNTL 0 0x1c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC1_CNTL 0 0x1d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC2_CNTL 0 0x1e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC3_CNTL 0 0x1f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC4_CNTL 0 0x20 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC5_CNTL 0 0x21 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC6_CNTL 0 0x22 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_VC7_CNTL 0 0x23 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_RD_CNTL_MISC 0 0x24 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB0_RD_TLB_CREDIT 0 0x25 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB0_RD_RDRET_CREDIT_CNTL 0 0x26 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB0_RD_RDRET_CREDIT_CNTL2 0 0x27 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB0_RDCLI_ASK_PENDING 0 0x28 1 0 0 BUSY 0 31 regDAGB0_RDCLI_GO_PENDING 0 0x29 1 0 0 BUSY 0 31 regDAGB0_RDCLI_GBLSEND_PENDING 0 0x2a 1 0 0 BUSY 0 31 regDAGB0_RDCLI_TLB_PENDING 0 0x2b 1 0 0 BUSY 0 31 regDAGB0_RDCLI_OARB_PENDING 0 0x2c 1 0 0 BUSY 0 31 regDAGB0_RDCLI_OSD_PENDING 0 0x2d 1 0 0 BUSY 0 31 regDAGB0_WRCLI0 0 0x2e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI1 0 0x2f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI2 0 0x30 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI3 0 0x31 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI4 0 0x32 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI5 0 0x33 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI6 0 0x34 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI7 0 0x35 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI8 0 0x36 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI9 0 0x37 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI10 0 0x38 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI11 0 0x39 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI12 0 0x3a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI13 0 0x3b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI14 0 0x3c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WRCLI15 0 0x3d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB0_WR_CNTL 0 0x3e 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB0_WR_GMI_CNTL 0 0x3f 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB0_WR_ADDR_DAGB 0 0x40 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0 0x41 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x42 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB0_WR_CGTT_CLK_CTRL 0 0x43 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0 0x44 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0 0x45 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0 0x46 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0 0x47 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0 0x48 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0 0x49 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_WR_DATA_DAGB 0 0x4a 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB0_WR_DATA_DAGB_MAX_BURST0 0 0x4b 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0 0x4c 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB0_WR_DATA_DAGB_MAX_BURST1 0 0x4d 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0 0x4e 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB0_WR_VC0_CNTL 0 0x4f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC1_CNTL 0 0x50 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC2_CNTL 0 0x51 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC3_CNTL 0 0x52 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC4_CNTL 0 0x53 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC5_CNTL 0 0x54 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC6_CNTL 0 0x55 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_VC7_CNTL 0 0x56 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB0_WR_CNTL_MISC 0 0x57 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB0_WR_TLB_CREDIT 0 0x58 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB0_WR_DATA_CREDIT 0 0x59 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB0_WR_MISC_CREDIT 0 0x5a 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB0_WR_OSD_CREDIT_CNTL1 0 0x5b 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB0_WR_OSD_CREDIT_CNTL2 0 0x5c 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x5d 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0 0x5e 1 0 0 ENABLE 0 31 regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x5f 1 0 0 ENABLE 0 31 regDAGB0_WRCLI_ASK_PENDING 0 0x60 1 0 0 BUSY 0 31 regDAGB0_WRCLI_GO_PENDING 0 0x61 1 0 0 BUSY 0 31 regDAGB0_WRCLI_GBLSEND_PENDING 0 0x62 1 0 0 BUSY 0 31 regDAGB0_WRCLI_TLB_PENDING 0 0x63 1 0 0 BUSY 0 31 regDAGB0_WRCLI_OARB_PENDING 0 0x64 1 0 0 BUSY 0 31 regDAGB0_WRCLI_OSD_PENDING 0 0x65 1 0 0 BUSY 0 31 regDAGB0_WRCLI_DBUS_ASK_PENDING 0 0x66 1 0 0 BUSY 0 31 regDAGB0_WRCLI_DBUS_GO_PENDING 0 0x67 1 0 0 BUSY 0 31 regDAGB0_DAGB_DLY 0 0x68 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB0_CNTL_MISC 0 0x69 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB0_CNTL_MISC2 0 0x6a 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB0_FATAL_ERROR_CNTL 0 0x6b 1 0 0 FILTER_NUM 0 9 regDAGB0_FATAL_ERROR_CLEAR 0 0x6c 1 0 0 CLEAR 0 0 regDAGB0_FATAL_ERROR_STATUS0 0 0x6d 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB0_FATAL_ERROR_STATUS1 0 0x6e 1 0 0 ADDR_HI 0 16 regDAGB0_FATAL_ERROR_STATUS2 0 0x6f 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB0_FATAL_ERROR_STATUS3 0 0x70 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB0_FIFO_EMPTY 0 0x71 1 0 0 EMPTY 0 23 regDAGB0_FIFO_FULL 0 0x72 1 0 0 FULL 0 22 regDAGB0_WR_CREDITS_FULL 0 0x73 1 0 0 FULL 0 28 regDAGB0_RD_CREDITS_FULL 0 0x74 1 0 0 FULL 0 17 regDAGB0_PERFCOUNTER_LO 0 0x75 1 0 0 COUNTER_LO 0 31 regDAGB0_PERFCOUNTER_HI 0 0x76 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB0_PERFCOUNTER0_CFG 0 0x77 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB0_PERFCOUNTER1_CFG 0 0x78 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB0_PERFCOUNTER2_CFG 0 0x79 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB0_PERFCOUNTER_RSLT_CNTL 0 0x7a 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB0_L1TLB_REG_RW 0 0x7b 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB0_RESERVE1 0 0x7c 1 0 0 RESERVE 0 31 regDAGB0_RESERVE2 0 0x7d 1 0 0 RESERVE 0 31 regDAGB0_RESERVE3 0 0x7e 1 0 0 RESERVE 0 31 regDAGB0_RESERVE4 0 0x7f 1 0 0 RESERVE 0 31 regDAGB1_RDCLI0 0 0x80 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI1 0 0x81 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI2 0 0x82 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI3 0 0x83 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI4 0 0x84 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI5 0 0x85 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI6 0 0x86 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI7 0 0x87 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI8 0 0x88 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI9 0 0x89 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI10 0 0x8a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI11 0 0x8b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI12 0 0x8c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI13 0 0x8d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI14 0 0x8e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RDCLI15 0 0x8f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_RD_CNTL 0 0x90 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB1_RD_GMI_CNTL 0 0x91 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB1_RD_ADDR_DAGB 0 0x92 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0 0x93 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x94 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB1_RD_CGTT_CLK_CTRL 0 0x95 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0 0x96 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0 0x97 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0 0x98 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0 0x99 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0 0x9a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0 0x9b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_RD_VC0_CNTL 0 0x9c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC1_CNTL 0 0x9d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC2_CNTL 0 0x9e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC3_CNTL 0 0x9f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC4_CNTL 0 0xa0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC5_CNTL 0 0xa1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC6_CNTL 0 0xa2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_VC7_CNTL 0 0xa3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_RD_CNTL_MISC 0 0xa4 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB1_RD_TLB_CREDIT 0 0xa5 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB1_RD_RDRET_CREDIT_CNTL 0 0xa6 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB1_RD_RDRET_CREDIT_CNTL2 0 0xa7 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB1_RDCLI_ASK_PENDING 0 0xa8 1 0 0 BUSY 0 31 regDAGB1_RDCLI_GO_PENDING 0 0xa9 1 0 0 BUSY 0 31 regDAGB1_RDCLI_GBLSEND_PENDING 0 0xaa 1 0 0 BUSY 0 31 regDAGB1_RDCLI_TLB_PENDING 0 0xab 1 0 0 BUSY 0 31 regDAGB1_RDCLI_OARB_PENDING 0 0xac 1 0 0 BUSY 0 31 regDAGB1_RDCLI_OSD_PENDING 0 0xad 1 0 0 BUSY 0 31 regDAGB1_WRCLI0 0 0xae 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI1 0 0xaf 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI2 0 0xb0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI3 0 0xb1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI4 0 0xb2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI5 0 0xb3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI6 0 0xb4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI7 0 0xb5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI8 0 0xb6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI9 0 0xb7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI10 0 0xb8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI11 0 0xb9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI12 0 0xba 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI13 0 0xbb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI14 0 0xbc 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WRCLI15 0 0xbd 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB1_WR_CNTL 0 0xbe 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB1_WR_GMI_CNTL 0 0xbf 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB1_WR_ADDR_DAGB 0 0xc0 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0 0xc1 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0 0xc2 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB1_WR_CGTT_CLK_CTRL 0 0xc3 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0 0xc4 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0 0xc5 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0 0xc6 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0 0xc7 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0 0xc8 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0 0xc9 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_WR_DATA_DAGB 0 0xca 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB1_WR_DATA_DAGB_MAX_BURST0 0 0xcb 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0 0xcc 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB1_WR_DATA_DAGB_MAX_BURST1 0 0xcd 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0 0xce 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB1_WR_VC0_CNTL 0 0xcf 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC1_CNTL 0 0xd0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC2_CNTL 0 0xd1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC3_CNTL 0 0xd2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC4_CNTL 0 0xd3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC5_CNTL 0 0xd4 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC6_CNTL 0 0xd5 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_VC7_CNTL 0 0xd6 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB1_WR_CNTL_MISC 0 0xd7 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB1_WR_TLB_CREDIT 0 0xd8 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB1_WR_DATA_CREDIT 0 0xd9 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB1_WR_MISC_CREDIT 0 0xda 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB1_WR_OSD_CREDIT_CNTL1 0 0xdb 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB1_WR_OSD_CREDIT_CNTL2 0 0xdc 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0xdd 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE 0 0xde 1 0 0 ENABLE 0 31 regDAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0xdf 1 0 0 ENABLE 0 31 regDAGB1_WRCLI_ASK_PENDING 0 0xe0 1 0 0 BUSY 0 31 regDAGB1_WRCLI_GO_PENDING 0 0xe1 1 0 0 BUSY 0 31 regDAGB1_WRCLI_GBLSEND_PENDING 0 0xe2 1 0 0 BUSY 0 31 regDAGB1_WRCLI_TLB_PENDING 0 0xe3 1 0 0 BUSY 0 31 regDAGB1_WRCLI_OARB_PENDING 0 0xe4 1 0 0 BUSY 0 31 regDAGB1_WRCLI_OSD_PENDING 0 0xe5 1 0 0 BUSY 0 31 regDAGB1_WRCLI_DBUS_ASK_PENDING 0 0xe6 1 0 0 BUSY 0 31 regDAGB1_WRCLI_DBUS_GO_PENDING 0 0xe7 1 0 0 BUSY 0 31 regDAGB1_DAGB_DLY 0 0xe8 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB1_CNTL_MISC 0 0xe9 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB1_CNTL_MISC2 0 0xea 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB1_FATAL_ERROR_CNTL 0 0xeb 1 0 0 FILTER_NUM 0 9 regDAGB1_FATAL_ERROR_CLEAR 0 0xec 1 0 0 CLEAR 0 0 regDAGB1_FATAL_ERROR_STATUS0 0 0xed 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB1_FATAL_ERROR_STATUS1 0 0xee 1 0 0 ADDR_HI 0 16 regDAGB1_FATAL_ERROR_STATUS2 0 0xef 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB1_FATAL_ERROR_STATUS3 0 0xf0 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB1_FIFO_EMPTY 0 0xf1 1 0 0 EMPTY 0 23 regDAGB1_FIFO_FULL 0 0xf2 1 0 0 FULL 0 22 regDAGB1_WR_CREDITS_FULL 0 0xf3 1 0 0 FULL 0 28 regDAGB1_RD_CREDITS_FULL 0 0xf4 1 0 0 FULL 0 17 regDAGB1_PERFCOUNTER_LO 0 0xf5 1 0 0 COUNTER_LO 0 31 regDAGB1_PERFCOUNTER_HI 0 0xf6 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB1_PERFCOUNTER0_CFG 0 0xf7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB1_PERFCOUNTER1_CFG 0 0xf8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB1_PERFCOUNTER2_CFG 0 0xf9 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB1_PERFCOUNTER_RSLT_CNTL 0 0xfa 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB1_L1TLB_REG_RW 0 0xfb 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB1_RESERVE1 0 0xfc 1 0 0 RESERVE 0 31 regDAGB1_RESERVE2 0 0xfd 1 0 0 RESERVE 0 31 regDAGB1_RESERVE3 0 0xfe 1 0 0 RESERVE 0 31 regDAGB1_RESERVE4 0 0xff 1 0 0 RESERVE 0 31 regDAGB2_RDCLI0 0 0x100 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI1 0 0x101 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI2 0 0x102 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI3 0 0x103 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI4 0 0x104 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI5 0 0x105 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI6 0 0x106 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI7 0 0x107 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI8 0 0x108 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI9 0 0x109 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI10 0 0x10a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI11 0 0x10b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI12 0 0x10c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI13 0 0x10d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI14 0 0x10e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RDCLI15 0 0x10f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_RD_CNTL 0 0x110 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB2_RD_GMI_CNTL 0 0x111 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB2_RD_ADDR_DAGB 0 0x112 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0 0x113 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x114 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB2_RD_CGTT_CLK_CTRL 0 0x115 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0 0x116 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0 0x117 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_RD_ADDR_DAGB_MAX_BURST0 0 0x118 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0 0x119 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_RD_ADDR_DAGB_MAX_BURST1 0 0x11a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0 0x11b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_RD_VC0_CNTL 0 0x11c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC1_CNTL 0 0x11d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC2_CNTL 0 0x11e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC3_CNTL 0 0x11f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC4_CNTL 0 0x120 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC5_CNTL 0 0x121 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC6_CNTL 0 0x122 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_VC7_CNTL 0 0x123 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_RD_CNTL_MISC 0 0x124 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB2_RD_TLB_CREDIT 0 0x125 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB2_RD_RDRET_CREDIT_CNTL 0 0x126 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB2_RD_RDRET_CREDIT_CNTL2 0 0x127 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB2_RDCLI_ASK_PENDING 0 0x128 1 0 0 BUSY 0 31 regDAGB2_RDCLI_GO_PENDING 0 0x129 1 0 0 BUSY 0 31 regDAGB2_RDCLI_GBLSEND_PENDING 0 0x12a 1 0 0 BUSY 0 31 regDAGB2_RDCLI_TLB_PENDING 0 0x12b 1 0 0 BUSY 0 31 regDAGB2_RDCLI_OARB_PENDING 0 0x12c 1 0 0 BUSY 0 31 regDAGB2_RDCLI_OSD_PENDING 0 0x12d 1 0 0 BUSY 0 31 regDAGB2_WRCLI0 0 0x12e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI1 0 0x12f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI2 0 0x130 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI3 0 0x131 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI4 0 0x132 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI5 0 0x133 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI6 0 0x134 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI7 0 0x135 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI8 0 0x136 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI9 0 0x137 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI10 0 0x138 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI11 0 0x139 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI12 0 0x13a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI13 0 0x13b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI14 0 0x13c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WRCLI15 0 0x13d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB2_WR_CNTL 0 0x13e 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB2_WR_GMI_CNTL 0 0x13f 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB2_WR_ADDR_DAGB 0 0x140 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0 0x141 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x142 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB2_WR_CGTT_CLK_CTRL 0 0x143 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0 0x144 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0 0x145 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB2_WR_ADDR_DAGB_MAX_BURST0 0 0x146 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0 0x147 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_WR_ADDR_DAGB_MAX_BURST1 0 0x148 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0 0x149 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_WR_DATA_DAGB 0 0x14a 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB2_WR_DATA_DAGB_MAX_BURST0 0 0x14b 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0 0x14c 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB2_WR_DATA_DAGB_MAX_BURST1 0 0x14d 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0 0x14e 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB2_WR_VC0_CNTL 0 0x14f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC1_CNTL 0 0x150 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC2_CNTL 0 0x151 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC3_CNTL 0 0x152 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC4_CNTL 0 0x153 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC5_CNTL 0 0x154 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC6_CNTL 0 0x155 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_VC7_CNTL 0 0x156 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB2_WR_CNTL_MISC 0 0x157 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB2_WR_TLB_CREDIT 0 0x158 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB2_WR_DATA_CREDIT 0 0x159 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB2_WR_MISC_CREDIT 0 0x15a 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB2_WR_OSD_CREDIT_CNTL1 0 0x15b 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB2_WR_OSD_CREDIT_CNTL2 0 0x15c 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x15d 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE 0 0x15e 1 0 0 ENABLE 0 31 regDAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x15f 1 0 0 ENABLE 0 31 regDAGB2_WRCLI_ASK_PENDING 0 0x160 1 0 0 BUSY 0 31 regDAGB2_WRCLI_GO_PENDING 0 0x161 1 0 0 BUSY 0 31 regDAGB2_WRCLI_GBLSEND_PENDING 0 0x162 1 0 0 BUSY 0 31 regDAGB2_WRCLI_TLB_PENDING 0 0x163 1 0 0 BUSY 0 31 regDAGB2_WRCLI_OARB_PENDING 0 0x164 1 0 0 BUSY 0 31 regDAGB2_WRCLI_OSD_PENDING 0 0x165 1 0 0 BUSY 0 31 regDAGB2_WRCLI_DBUS_ASK_PENDING 0 0x166 1 0 0 BUSY 0 31 regDAGB2_WRCLI_DBUS_GO_PENDING 0 0x167 1 0 0 BUSY 0 31 regDAGB2_DAGB_DLY 0 0x168 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB2_CNTL_MISC 0 0x169 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB2_CNTL_MISC2 0 0x16a 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB2_FATAL_ERROR_CNTL 0 0x16b 1 0 0 FILTER_NUM 0 9 regDAGB2_FATAL_ERROR_CLEAR 0 0x16c 1 0 0 CLEAR 0 0 regDAGB2_FATAL_ERROR_STATUS0 0 0x16d 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB2_FATAL_ERROR_STATUS1 0 0x16e 1 0 0 ADDR_HI 0 16 regDAGB2_FATAL_ERROR_STATUS2 0 0x16f 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB2_FATAL_ERROR_STATUS3 0 0x170 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB2_FIFO_EMPTY 0 0x171 1 0 0 EMPTY 0 23 regDAGB2_FIFO_FULL 0 0x172 1 0 0 FULL 0 22 regDAGB2_WR_CREDITS_FULL 0 0x173 1 0 0 FULL 0 28 regDAGB2_RD_CREDITS_FULL 0 0x174 1 0 0 FULL 0 17 regDAGB2_PERFCOUNTER_LO 0 0x175 1 0 0 COUNTER_LO 0 31 regDAGB2_PERFCOUNTER_HI 0 0x176 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB2_PERFCOUNTER0_CFG 0 0x177 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB2_PERFCOUNTER1_CFG 0 0x178 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB2_PERFCOUNTER2_CFG 0 0x179 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB2_PERFCOUNTER_RSLT_CNTL 0 0x17a 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB2_L1TLB_REG_RW 0 0x17b 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB2_RESERVE1 0 0x17c 1 0 0 RESERVE 0 31 regDAGB2_RESERVE2 0 0x17d 1 0 0 RESERVE 0 31 regDAGB2_RESERVE3 0 0x17e 1 0 0 RESERVE 0 31 regDAGB2_RESERVE4 0 0x17f 1 0 0 RESERVE 0 31 regDAGB3_RDCLI0 0 0x180 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI1 0 0x181 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI2 0 0x182 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI3 0 0x183 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI4 0 0x184 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI5 0 0x185 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI6 0 0x186 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI7 0 0x187 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI8 0 0x188 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI9 0 0x189 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI10 0 0x18a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI11 0 0x18b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI12 0 0x18c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI13 0 0x18d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI14 0 0x18e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RDCLI15 0 0x18f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_RD_CNTL 0 0x190 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB3_RD_GMI_CNTL 0 0x191 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB3_RD_ADDR_DAGB 0 0x192 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0 0x193 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x194 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB3_RD_CGTT_CLK_CTRL 0 0x195 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0 0x196 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0 0x197 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_RD_ADDR_DAGB_MAX_BURST0 0 0x198 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0 0x199 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_RD_ADDR_DAGB_MAX_BURST1 0 0x19a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0 0x19b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_RD_VC0_CNTL 0 0x19c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC1_CNTL 0 0x19d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC2_CNTL 0 0x19e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC3_CNTL 0 0x19f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC4_CNTL 0 0x1a0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC5_CNTL 0 0x1a1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC6_CNTL 0 0x1a2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_VC7_CNTL 0 0x1a3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_RD_CNTL_MISC 0 0x1a4 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB3_RD_TLB_CREDIT 0 0x1a5 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB3_RD_RDRET_CREDIT_CNTL 0 0x1a6 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB3_RD_RDRET_CREDIT_CNTL2 0 0x1a7 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB3_RDCLI_ASK_PENDING 0 0x1a8 1 0 0 BUSY 0 31 regDAGB3_RDCLI_GO_PENDING 0 0x1a9 1 0 0 BUSY 0 31 regDAGB3_RDCLI_GBLSEND_PENDING 0 0x1aa 1 0 0 BUSY 0 31 regDAGB3_RDCLI_TLB_PENDING 0 0x1ab 1 0 0 BUSY 0 31 regDAGB3_RDCLI_OARB_PENDING 0 0x1ac 1 0 0 BUSY 0 31 regDAGB3_RDCLI_OSD_PENDING 0 0x1ad 1 0 0 BUSY 0 31 regDAGB3_WRCLI0 0 0x1ae 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI1 0 0x1af 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI2 0 0x1b0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI3 0 0x1b1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI4 0 0x1b2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI5 0 0x1b3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI6 0 0x1b4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI7 0 0x1b5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI8 0 0x1b6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI9 0 0x1b7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI10 0 0x1b8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI11 0 0x1b9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI12 0 0x1ba 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI13 0 0x1bb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI14 0 0x1bc 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WRCLI15 0 0x1bd 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB3_WR_CNTL 0 0x1be 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB3_WR_GMI_CNTL 0 0x1bf 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB3_WR_ADDR_DAGB 0 0x1c0 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0 0x1c1 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x1c2 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB3_WR_CGTT_CLK_CTRL 0 0x1c3 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0 0x1c4 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0 0x1c5 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB3_WR_ADDR_DAGB_MAX_BURST0 0 0x1c6 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0 0x1c7 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_WR_ADDR_DAGB_MAX_BURST1 0 0x1c8 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0 0x1c9 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_WR_DATA_DAGB 0 0x1ca 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB3_WR_DATA_DAGB_MAX_BURST0 0 0x1cb 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0 0x1cc 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB3_WR_DATA_DAGB_MAX_BURST1 0 0x1cd 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0 0x1ce 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB3_WR_VC0_CNTL 0 0x1cf 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC1_CNTL 0 0x1d0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC2_CNTL 0 0x1d1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC3_CNTL 0 0x1d2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC4_CNTL 0 0x1d3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC5_CNTL 0 0x1d4 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC6_CNTL 0 0x1d5 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_VC7_CNTL 0 0x1d6 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB3_WR_CNTL_MISC 0 0x1d7 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB3_WR_TLB_CREDIT 0 0x1d8 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB3_WR_DATA_CREDIT 0 0x1d9 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB3_WR_MISC_CREDIT 0 0x1da 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB3_WR_OSD_CREDIT_CNTL1 0 0x1db 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB3_WR_OSD_CREDIT_CNTL2 0 0x1dc 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x1dd 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE 0 0x1de 1 0 0 ENABLE 0 31 regDAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x1df 1 0 0 ENABLE 0 31 regDAGB3_WRCLI_ASK_PENDING 0 0x1e0 1 0 0 BUSY 0 31 regDAGB3_WRCLI_GO_PENDING 0 0x1e1 1 0 0 BUSY 0 31 regDAGB3_WRCLI_GBLSEND_PENDING 0 0x1e2 1 0 0 BUSY 0 31 regDAGB3_WRCLI_TLB_PENDING 0 0x1e3 1 0 0 BUSY 0 31 regDAGB3_WRCLI_OARB_PENDING 0 0x1e4 1 0 0 BUSY 0 31 regDAGB3_WRCLI_OSD_PENDING 0 0x1e5 1 0 0 BUSY 0 31 regDAGB3_WRCLI_DBUS_ASK_PENDING 0 0x1e6 1 0 0 BUSY 0 31 regDAGB3_WRCLI_DBUS_GO_PENDING 0 0x1e7 1 0 0 BUSY 0 31 regDAGB3_DAGB_DLY 0 0x1e8 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB3_CNTL_MISC 0 0x1e9 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB3_CNTL_MISC2 0 0x1ea 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB3_FATAL_ERROR_CNTL 0 0x1eb 1 0 0 FILTER_NUM 0 9 regDAGB3_FATAL_ERROR_CLEAR 0 0x1ec 1 0 0 CLEAR 0 0 regDAGB3_FATAL_ERROR_STATUS0 0 0x1ed 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB3_FATAL_ERROR_STATUS1 0 0x1ee 1 0 0 ADDR_HI 0 16 regDAGB3_FATAL_ERROR_STATUS2 0 0x1ef 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB3_FATAL_ERROR_STATUS3 0 0x1f0 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB3_FIFO_EMPTY 0 0x1f1 1 0 0 EMPTY 0 23 regDAGB3_FIFO_FULL 0 0x1f2 1 0 0 FULL 0 22 regDAGB3_WR_CREDITS_FULL 0 0x1f3 1 0 0 FULL 0 28 regDAGB3_RD_CREDITS_FULL 0 0x1f4 1 0 0 FULL 0 17 regDAGB3_PERFCOUNTER_LO 0 0x1f5 1 0 0 COUNTER_LO 0 31 regDAGB3_PERFCOUNTER_HI 0 0x1f6 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB3_PERFCOUNTER0_CFG 0 0x1f7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB3_PERFCOUNTER1_CFG 0 0x1f8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB3_PERFCOUNTER2_CFG 0 0x1f9 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB3_PERFCOUNTER_RSLT_CNTL 0 0x1fa 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB3_L1TLB_REG_RW 0 0x1fb 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB3_RESERVE1 0 0x1fc 1 0 0 RESERVE 0 31 regDAGB3_RESERVE2 0 0x1fd 1 0 0 RESERVE 0 31 regDAGB3_RESERVE3 0 0x1fe 1 0 0 RESERVE 0 31 regDAGB3_RESERVE4 0 0x1ff 1 0 0 RESERVE 0 31 regDAGB4_RDCLI0 0 0x200 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI1 0 0x201 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI2 0 0x202 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI3 0 0x203 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI4 0 0x204 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI5 0 0x205 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI6 0 0x206 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI7 0 0x207 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI8 0 0x208 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI9 0 0x209 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI10 0 0x20a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI11 0 0x20b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI12 0 0x20c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI13 0 0x20d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI14 0 0x20e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RDCLI15 0 0x20f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_RD_CNTL 0 0x210 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB4_RD_GMI_CNTL 0 0x211 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB4_RD_ADDR_DAGB 0 0x212 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0 0x213 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x214 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB4_RD_CGTT_CLK_CTRL 0 0x215 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0 0x216 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0 0x217 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_RD_ADDR_DAGB_MAX_BURST0 0 0x218 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0 0x219 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_RD_ADDR_DAGB_MAX_BURST1 0 0x21a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0 0x21b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_RD_VC0_CNTL 0 0x21c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC1_CNTL 0 0x21d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC2_CNTL 0 0x21e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC3_CNTL 0 0x21f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC4_CNTL 0 0x220 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC5_CNTL 0 0x221 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC6_CNTL 0 0x222 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_VC7_CNTL 0 0x223 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_RD_CNTL_MISC 0 0x224 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB4_RD_TLB_CREDIT 0 0x225 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB4_RD_RDRET_CREDIT_CNTL 0 0x226 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB4_RD_RDRET_CREDIT_CNTL2 0 0x227 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB4_RDCLI_ASK_PENDING 0 0x228 1 0 0 BUSY 0 31 regDAGB4_RDCLI_GO_PENDING 0 0x229 1 0 0 BUSY 0 31 regDAGB4_RDCLI_GBLSEND_PENDING 0 0x22a 1 0 0 BUSY 0 31 regDAGB4_RDCLI_TLB_PENDING 0 0x22b 1 0 0 BUSY 0 31 regDAGB4_RDCLI_OARB_PENDING 0 0x22c 1 0 0 BUSY 0 31 regDAGB4_RDCLI_OSD_PENDING 0 0x22d 1 0 0 BUSY 0 31 regDAGB4_WRCLI0 0 0x22e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI1 0 0x22f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI2 0 0x230 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI3 0 0x231 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI4 0 0x232 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI5 0 0x233 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI6 0 0x234 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI7 0 0x235 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI8 0 0x236 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI9 0 0x237 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI10 0 0x238 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI11 0 0x239 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI12 0 0x23a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI13 0 0x23b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI14 0 0x23c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WRCLI15 0 0x23d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB4_WR_CNTL 0 0x23e 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB4_WR_GMI_CNTL 0 0x23f 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB4_WR_ADDR_DAGB 0 0x240 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0 0x241 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x242 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB4_WR_CGTT_CLK_CTRL 0 0x243 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0 0x244 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0 0x245 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB4_WR_ADDR_DAGB_MAX_BURST0 0 0x246 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0 0x247 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_WR_ADDR_DAGB_MAX_BURST1 0 0x248 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0 0x249 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_WR_DATA_DAGB 0 0x24a 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB4_WR_DATA_DAGB_MAX_BURST0 0 0x24b 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0 0x24c 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB4_WR_DATA_DAGB_MAX_BURST1 0 0x24d 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0 0x24e 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB4_WR_VC0_CNTL 0 0x24f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC1_CNTL 0 0x250 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC2_CNTL 0 0x251 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC3_CNTL 0 0x252 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC4_CNTL 0 0x253 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC5_CNTL 0 0x254 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC6_CNTL 0 0x255 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_VC7_CNTL 0 0x256 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB4_WR_CNTL_MISC 0 0x257 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB4_WR_TLB_CREDIT 0 0x258 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB4_WR_DATA_CREDIT 0 0x259 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB4_WR_MISC_CREDIT 0 0x25a 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB4_WR_OSD_CREDIT_CNTL1 0 0x25b 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB4_WR_OSD_CREDIT_CNTL2 0 0x25c 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x25d 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE 0 0x25e 1 0 0 ENABLE 0 31 regDAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x25f 1 0 0 ENABLE 0 31 regDAGB4_WRCLI_ASK_PENDING 0 0x260 1 0 0 BUSY 0 31 regDAGB4_WRCLI_GO_PENDING 0 0x261 1 0 0 BUSY 0 31 regDAGB4_WRCLI_GBLSEND_PENDING 0 0x262 1 0 0 BUSY 0 31 regDAGB4_WRCLI_TLB_PENDING 0 0x263 1 0 0 BUSY 0 31 regDAGB4_WRCLI_OARB_PENDING 0 0x264 1 0 0 BUSY 0 31 regDAGB4_WRCLI_OSD_PENDING 0 0x265 1 0 0 BUSY 0 31 regDAGB4_WRCLI_DBUS_ASK_PENDING 0 0x266 1 0 0 BUSY 0 31 regDAGB4_WRCLI_DBUS_GO_PENDING 0 0x267 1 0 0 BUSY 0 31 regDAGB4_DAGB_DLY 0 0x268 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB4_CNTL_MISC 0 0x269 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB4_CNTL_MISC2 0 0x26a 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB4_FATAL_ERROR_CNTL 0 0x26b 1 0 0 FILTER_NUM 0 9 regDAGB4_FATAL_ERROR_CLEAR 0 0x26c 1 0 0 CLEAR 0 0 regDAGB4_FATAL_ERROR_STATUS0 0 0x26d 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB4_FATAL_ERROR_STATUS1 0 0x26e 1 0 0 ADDR_HI 0 16 regDAGB4_FATAL_ERROR_STATUS2 0 0x26f 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB4_FATAL_ERROR_STATUS3 0 0x270 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB4_FIFO_EMPTY 0 0x271 1 0 0 EMPTY 0 23 regDAGB4_FIFO_FULL 0 0x272 1 0 0 FULL 0 22 regDAGB4_WR_CREDITS_FULL 0 0x273 1 0 0 FULL 0 28 regDAGB4_RD_CREDITS_FULL 0 0x274 1 0 0 FULL 0 17 regDAGB4_PERFCOUNTER_LO 0 0x275 1 0 0 COUNTER_LO 0 31 regDAGB4_PERFCOUNTER_HI 0 0x276 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB4_PERFCOUNTER0_CFG 0 0x277 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB4_PERFCOUNTER1_CFG 0 0x278 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB4_PERFCOUNTER2_CFG 0 0x279 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB4_PERFCOUNTER_RSLT_CNTL 0 0x27a 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB4_L1TLB_REG_RW 0 0x27b 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB4_RESERVE1 0 0x27c 1 0 0 RESERVE 0 31 regDAGB4_RESERVE2 0 0x27d 1 0 0 RESERVE 0 31 regDAGB4_RESERVE3 0 0x27e 1 0 0 RESERVE 0 31 regDAGB4_RESERVE4 0 0x27f 1 0 0 RESERVE 0 31 regDAGB5_RDCLI0 0 0x280 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI1 0 0x281 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI2 0 0x282 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI3 0 0x283 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI4 0 0x284 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI5 0 0x285 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI6 0 0x286 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI7 0 0x287 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI8 0 0x288 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI9 0 0x289 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI10 0 0x28a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI11 0 0x28b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI12 0 0x28c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI13 0 0x28d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI14 0 0x28e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RDCLI15 0 0x28f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_RD_CNTL 0 0x290 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB5_RD_GMI_CNTL 0 0x291 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB5_RD_ADDR_DAGB 0 0x292 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0 0x293 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x294 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB5_RD_CGTT_CLK_CTRL 0 0x295 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0 0x296 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0 0x297 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_RD_ADDR_DAGB_MAX_BURST0 0 0x298 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0 0x299 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_RD_ADDR_DAGB_MAX_BURST1 0 0x29a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0 0x29b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_RD_VC0_CNTL 0 0x29c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC1_CNTL 0 0x29d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC2_CNTL 0 0x29e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC3_CNTL 0 0x29f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC4_CNTL 0 0x2a0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC5_CNTL 0 0x2a1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC6_CNTL 0 0x2a2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_VC7_CNTL 0 0x2a3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_RD_CNTL_MISC 0 0x2a4 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB5_RD_TLB_CREDIT 0 0x2a5 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB5_RD_RDRET_CREDIT_CNTL 0 0x2a6 7 0 0 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 regDAGB5_RD_RDRET_CREDIT_CNTL2 0 0x2a7 3 0 0 IO_CREDIT 0 5 GMI_CREDIT 6 11 POOL_CREDIT 12 18 regDAGB5_RDCLI_ASK_PENDING 0 0x2a8 1 0 0 BUSY 0 31 regDAGB5_RDCLI_GO_PENDING 0 0x2a9 1 0 0 BUSY 0 31 regDAGB5_RDCLI_GBLSEND_PENDING 0 0x2aa 1 0 0 BUSY 0 31 regDAGB5_RDCLI_TLB_PENDING 0 0x2ab 1 0 0 BUSY 0 31 regDAGB5_RDCLI_OARB_PENDING 0 0x2ac 1 0 0 BUSY 0 31 regDAGB5_RDCLI_OSD_PENDING 0 0x2ad 1 0 0 BUSY 0 31 regDAGB5_WRCLI0 0 0x2ae 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI1 0 0x2af 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI2 0 0x2b0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI3 0 0x2b1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI4 0 0x2b2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI5 0 0x2b3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI6 0 0x2b4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI7 0 0x2b5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI8 0 0x2b6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI9 0 0x2b7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI10 0 0x2b8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI11 0 0x2b9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI12 0 0x2ba 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI13 0 0x2bb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI14 0 0x2bc 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WRCLI15 0 0x2bd 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 regDAGB5_WR_CNTL 0 0x2be 8 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 FIX_JUMP 26 26 regDAGB5_WR_GMI_CNTL 0 0x2bf 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 regDAGB5_WR_ADDR_DAGB 0 0x2c0 5 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 regDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0 0x2c1 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x2c2 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 regDAGB5_WR_CGTT_CLK_CTRL 0 0x2c3 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0 0x2c4 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0 0x2c5 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 regDAGB5_WR_ADDR_DAGB_MAX_BURST0 0 0x2c6 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0 0x2c7 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_WR_ADDR_DAGB_MAX_BURST1 0 0x2c8 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0 0x2c9 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_WR_DATA_DAGB 0 0x2ca 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 regDAGB5_WR_DATA_DAGB_MAX_BURST0 0 0x2cb 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0 0x2cc 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 regDAGB5_WR_DATA_DAGB_MAX_BURST1 0 0x2cd 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0 0x2ce 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 regDAGB5_WR_VC0_CNTL 0 0x2cf 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC1_CNTL 0 0x2d0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC2_CNTL 0 0x2d1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC3_CNTL 0 0x2d2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC4_CNTL 0 0x2d3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC5_CNTL 0 0x2d4 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC6_CNTL 0 0x2d5 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_VC7_CNTL 0 0x2d6 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 regDAGB5_WR_CNTL_MISC 0 0x2d7 7 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 regDAGB5_WR_TLB_CREDIT 0 0x2d8 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 regDAGB5_WR_DATA_CREDIT 0 0x2d9 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 regDAGB5_WR_MISC_CREDIT 0 0x2da 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 regDAGB5_WR_OSD_CREDIT_CNTL1 0 0x2db 7 0 0 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 regDAGB5_WR_OSD_CREDIT_CNTL2 0 0x2dc 2 0 0 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 regDAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x2dd 10 0 0 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE 0 0x2de 1 0 0 ENABLE 0 31 regDAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x2df 1 0 0 ENABLE 0 31 regDAGB5_WRCLI_ASK_PENDING 0 0x2e0 1 0 0 BUSY 0 31 regDAGB5_WRCLI_GO_PENDING 0 0x2e1 1 0 0 BUSY 0 31 regDAGB5_WRCLI_GBLSEND_PENDING 0 0x2e2 1 0 0 BUSY 0 31 regDAGB5_WRCLI_TLB_PENDING 0 0x2e3 1 0 0 BUSY 0 31 regDAGB5_WRCLI_OARB_PENDING 0 0x2e4 1 0 0 BUSY 0 31 regDAGB5_WRCLI_OSD_PENDING 0 0x2e5 1 0 0 BUSY 0 31 regDAGB5_WRCLI_DBUS_ASK_PENDING 0 0x2e6 1 0 0 BUSY 0 31 regDAGB5_WRCLI_DBUS_GO_PENDING 0 0x2e7 1 0 0 BUSY 0 31 regDAGB5_DAGB_DLY 0 0x2e8 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 regDAGB5_CNTL_MISC 0 0x2e9 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 regDAGB5_CNTL_MISC2 0 0x2ea 14 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 HDP_CID 12 16 RDRET_FIFO_DLOCK_CREDITS 17 22 regDAGB5_FATAL_ERROR_CNTL 0 0x2eb 1 0 0 FILTER_NUM 0 9 regDAGB5_FATAL_ERROR_CLEAR 0 0x2ec 1 0 0 CLEAR 0 0 regDAGB5_FATAL_ERROR_STATUS0 0 0x2ed 3 0 0 VALID 0 0 CID 1 5 ADDR_LO 6 31 regDAGB5_FATAL_ERROR_STATUS1 0 0x2ee 1 0 0 ADDR_HI 0 16 regDAGB5_FATAL_ERROR_STATUS2 0 0x2ef 7 0 0 TAG 0 15 VFID 16 19 VF 20 20 SPACE 21 21 IO 22 22 SIZE 23 23 FED 25 25 regDAGB5_FATAL_ERROR_STATUS3 0 0x2f0 9 0 0 OP 6 12 WRTMZ 16 16 RDTMZ 17 17 SNOOP 18 18 INVAL 19 19 NACK 20 21 RO 22 22 MEMLOG 23 23 EOP 24 24 regDAGB5_FIFO_EMPTY 0 0x2f1 1 0 0 EMPTY 0 23 regDAGB5_FIFO_FULL 0 0x2f2 1 0 0 FULL 0 22 regDAGB5_WR_CREDITS_FULL 0 0x2f3 1 0 0 FULL 0 28 regDAGB5_RD_CREDITS_FULL 0 0x2f4 1 0 0 FULL 0 17 regDAGB5_PERFCOUNTER_LO 0 0x2f5 1 0 0 COUNTER_LO 0 31 regDAGB5_PERFCOUNTER_HI 0 0x2f6 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regDAGB5_PERFCOUNTER0_CFG 0 0x2f7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB5_PERFCOUNTER1_CFG 0 0x2f8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB5_PERFCOUNTER2_CFG 0 0x2f9 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regDAGB5_PERFCOUNTER_RSLT_CNTL 0 0x2fa 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regDAGB5_L1TLB_REG_RW 0 0x2fb 6 0 0 REG_WRITE_L1TLB_CTRL 0 0 REG_READ_L1TLB_CTRL 1 1 VMID_EXCEP_INT_CTRL 2 2 WDAT_PARITY_CHECK 4 4 DISABLE_RDRET_CHECK 5 5 RESERVE 6 31 regDAGB5_RESERVE1 0 0x2fc 1 0 0 RESERVE 0 31 regDAGB5_RESERVE2 0 0x2fd 1 0 0 RESERVE 0 31 regDAGB5_RESERVE3 0 0x2fe 1 0 0 RESERVE 0 31 regDAGB5_RESERVE4 0 0x2ff 1 0 0 RESERVE 0 31 regMMEA0_DRAM_RD_CLI2GRP_MAP0 0 0x300 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_DRAM_RD_CLI2GRP_MAP1 0 0x301 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_DRAM_WR_CLI2GRP_MAP0 0 0x302 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_DRAM_WR_CLI2GRP_MAP1 0 0x303 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_DRAM_RD_GRP2VC_MAP 0 0x304 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA0_DRAM_WR_GRP2VC_MAP 0 0x305 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA0_DRAM_RD_LAZY 0 0x306 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA0_DRAM_WR_LAZY 0 0x307 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA0_DRAM_RD_CAM_CNTL 0 0x308 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA0_DRAM_WR_CAM_CNTL 0 0x309 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA0_DRAM_PAGE_BURST 0 0x30a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA0_DRAM_RD_PRI_AGE 0 0x30b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_DRAM_WR_PRI_AGE 0 0x30c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_DRAM_RD_PRI_QUEUING 0 0x30d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_DRAM_WR_PRI_QUEUING 0 0x30e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_DRAM_RD_PRI_FIXED 0 0x30f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_DRAM_WR_PRI_FIXED 0 0x310 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_DRAM_RD_PRI_URGENCY 0 0x311 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_DRAM_WR_PRI_URGENCY 0 0x312 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_DRAM_RD_PRI_QUANT_PRI1 0 0x313 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_DRAM_RD_PRI_QUANT_PRI2 0 0x314 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_DRAM_RD_PRI_QUANT_PRI3 0 0x315 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_DRAM_WR_PRI_QUANT_PRI1 0 0x316 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_DRAM_WR_PRI_QUANT_PRI2 0 0x317 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_DRAM_WR_PRI_QUANT_PRI3 0 0x318 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_RD_CLI2GRP_MAP0 0 0x319 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_GMI_RD_CLI2GRP_MAP1 0 0x31a 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_GMI_WR_CLI2GRP_MAP0 0 0x31b 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_GMI_WR_CLI2GRP_MAP1 0 0x31c 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_GMI_RD_GRP2VC_MAP 0 0x31d 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA0_GMI_WR_GRP2VC_MAP 0 0x31e 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA0_GMI_RD_LAZY 0 0x31f 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA0_GMI_WR_LAZY 0 0x320 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA0_GMI_RD_CAM_CNTL 0 0x321 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA0_GMI_WR_CAM_CNTL 0 0x322 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA0_GMI_PAGE_BURST 0 0x323 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA0_GMI_RD_PRI_AGE 0 0x324 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_GMI_WR_PRI_AGE 0 0x325 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_GMI_RD_PRI_QUEUING 0 0x326 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_GMI_WR_PRI_QUEUING 0 0x327 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_GMI_RD_PRI_FIXED 0 0x328 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_GMI_WR_PRI_FIXED 0 0x329 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_GMI_RD_PRI_URGENCY 0 0x32a 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_GMI_WR_PRI_URGENCY 0 0x32b 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_GMI_RD_PRI_URGENCY_MASKING 0 0x32c 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA0_GMI_WR_PRI_URGENCY_MASKING 0 0x32d 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA0_GMI_RD_PRI_QUANT_PRI1 0 0x32e 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_RD_PRI_QUANT_PRI2 0 0x32f 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_RD_PRI_QUANT_PRI3 0 0x330 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_WR_PRI_QUANT_PRI1 0 0x331 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_WR_PRI_QUANT_PRI2 0 0x332 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_GMI_WR_PRI_QUANT_PRI3 0 0x333 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_ADDRNORM_BASE_ADDR0 0 0x334 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_LIMIT_ADDR0 0 0x335 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORM_BASE_ADDR1 0 0x336 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_LIMIT_ADDR1 0 0x337 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORM_OFFSET_ADDR1 0 0x338 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA0_ADDRNORM_BASE_ADDR2 0 0x339 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_LIMIT_ADDR2 0 0x33a 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORM_BASE_ADDR3 0 0x33b 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_LIMIT_ADDR3 0 0x33c 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORM_OFFSET_ADDR3 0 0x33d 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA0_ADDRNORM_MEGABASE_ADDR0 0 0x33e 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_MEGALIMIT_ADDR0 0 0x33f 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORM_MEGABASE_ADDR1 0 0x340 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA0_ADDRNORM_MEGALIMIT_ADDR1 0 0x341 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA0_ADDRNORMDRAM_HOLE_CNTL 0 0x343 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA0_ADDRNORMGMI_HOLE_CNTL 0 0x344 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x345 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x346 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA0_ADDRDEC_BANK_CFG 0 0x347 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA0_ADDRDEC_MISC_CFG 0 0x348 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0 0x353 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA0_ADDRDECGMI_HARVEST_ENABLE 0 0x35e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA0_ADDRDEC0_BASE_ADDR_CS0 0 0x35f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_CS1 0 0x360 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_CS2 0 0x361 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_CS3 0 0x362 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0 0x363 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0 0x364 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0 0x365 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0 0x366 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC0_ADDR_MASK_CS01 0 0x367 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC0_ADDR_MASK_CS23 0 0x368 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0 0x369 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0 0x36a 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC0_ADDR_CFG_CS01 0 0x36b 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC0_ADDR_CFG_CS23 0 0x36c 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC0_ADDR_SEL_CS01 0 0x36d 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC0_ADDR_SEL_CS23 0 0x36e 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0 0x36f 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0 0x370 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0 0x371 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0 0x372 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0 0x373 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0 0x374 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC0_RM_SEL_CS01 0 0x375 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC0_RM_SEL_CS23 0 0x376 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC0_RM_SEL_SECCS01 0 0x377 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC0_RM_SEL_SECCS23 0 0x378 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC1_BASE_ADDR_CS0 0 0x379 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_CS1 0 0x37a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_CS2 0 0x37b 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_CS3 0 0x37c 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0 0x37d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0 0x37e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0 0x37f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0 0x380 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC1_ADDR_MASK_CS01 0 0x381 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC1_ADDR_MASK_CS23 0 0x382 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0 0x383 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0 0x384 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC1_ADDR_CFG_CS01 0 0x385 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC1_ADDR_CFG_CS23 0 0x386 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC1_ADDR_SEL_CS01 0 0x387 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC1_ADDR_SEL_CS23 0 0x388 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0 0x389 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0 0x38a 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0 0x38b 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0 0x38c 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0 0x38d 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0 0x38e 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC1_RM_SEL_CS01 0 0x38f 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC1_RM_SEL_CS23 0 0x390 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC1_RM_SEL_SECCS01 0 0x391 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC1_RM_SEL_SECCS23 0 0x392 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC2_BASE_ADDR_CS0 0 0x393 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_CS1 0 0x394 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_CS2 0 0x395 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_CS3 0 0x396 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0 0x397 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0 0x398 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0 0x399 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0 0x39a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA0_ADDRDEC2_ADDR_MASK_CS01 0 0x39b 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC2_ADDR_MASK_CS23 0 0x39c 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0 0x39d 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0 0x39e 1 0 0 ADDR_MASK 1 31 regMMEA0_ADDRDEC2_ADDR_CFG_CS01 0 0x39f 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC2_ADDR_CFG_CS23 0 0x3a0 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA0_ADDRDEC2_ADDR_SEL_CS01 0 0x3a1 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC2_ADDR_SEL_CS23 0 0x3a2 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0 0x3a3 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0 0x3a4 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0 0x3a5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0 0x3a6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0 0x3a7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0 0x3a8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA0_ADDRDEC2_RM_SEL_CS01 0 0x3a9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC2_RM_SEL_CS23 0 0x3aa 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC2_RM_SEL_SECCS01 0 0x3ab 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRDEC2_RM_SEL_SECCS23 0 0x3ac 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0 0x3ad 0 0 0 regMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0 0x3ae 0 0 0 regMMEA0_ADDRNORM_MEGACONTROL_ADDR0 0 0x3d1 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA0_ADDRNORM_MEGACONTROL_ADDR1 0 0x3d2 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA0_ADDRNORMDRAM_MASKING 0 0x3d3 1 0 0 ADDRHI_MASK 0 11 regMMEA0_ADDRNORMGMI_MASKING 0 0x3d4 1 0 0 ADDRHI_MASK 0 11 regMMEA0_IO_RD_CLI2GRP_MAP0 0 0x3d5 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_IO_RD_CLI2GRP_MAP1 0 0x3d6 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_IO_WR_CLI2GRP_MAP0 0 0x3d7 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA0_IO_WR_CLI2GRP_MAP1 0 0x3d8 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA0_IO_RD_COMBINE_FLUSH 0 0x3d9 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA0_IO_WR_COMBINE_FLUSH 0 0x3da 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA0_IO_GROUP_BURST 0 0x3db 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA0_IO_RD_PRI_AGE 0 0x3dc 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_IO_WR_PRI_AGE 0 0x3dd 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA0_IO_RD_PRI_QUEUING 0 0x3de 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_IO_WR_PRI_QUEUING 0 0x3df 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA0_IO_RD_PRI_FIXED 0 0x3e0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_IO_WR_PRI_FIXED 0 0x3e1 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA0_IO_RD_PRI_URGENCY 0 0x3e2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_IO_WR_PRI_URGENCY 0 0x3e3 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA0_IO_RD_PRI_URGENCY_MASKING 0 0x3e4 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA0_IO_WR_PRI_URGENCY_MASKING 0 0x3e5 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA0_IO_RD_PRI_QUANT_PRI1 0 0x3e6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_IO_RD_PRI_QUANT_PRI2 0 0x3e7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_IO_RD_PRI_QUANT_PRI3 0 0x3e8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_IO_WR_PRI_QUANT_PRI1 0 0x3e9 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_IO_WR_PRI_QUANT_PRI2 0 0x3ea 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_IO_WR_PRI_QUANT_PRI3 0 0x3eb 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA0_SDP_ARB_DRAM 0 0x3ec 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA0_SDP_ARB_GMI 0 0x3ed 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA0_SDP_ARB_FINAL 0 0x3ee 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA0_SDP_DRAM_PRIORITY 0 0x3ef 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA0_SDP_GMI_PRIORITY 0 0x3f0 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA0_SDP_IO_PRIORITY 0 0x3f1 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA0_SDP_CREDITS 0 0x3f2 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA0_SDP_TAG_RESERVE0 0 0x3f3 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA0_SDP_TAG_RESERVE1 0 0x3f4 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA0_SDP_VCC_RESERVE0 0 0x3f5 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA0_SDP_VCC_RESERVE1 0 0x3f6 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA0_SDP_VCD_RESERVE0 0 0x3f7 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA0_SDP_VCD_RESERVE1 0 0x3f8 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA0_SDP_REQ_CNTL 0 0x3f9 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA0_MISC 0 0x3fa 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA0_LATENCY_SAMPLING 0 0x3fb 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA0_PERFCOUNTER_LO 0 0x3fc 1 0 0 COUNTER_LO 0 31 regMMEA0_PERFCOUNTER_HI 0 0x3fd 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA0_PERFCOUNTER0_CFG 0 0x3fe 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA0_PERFCOUNTER1_CFG 0 0x3ff 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA0_PERFCOUNTER_RSLT_CNTL 0 0x400 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA0_EDC_CNT 0 0x406 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA0_EDC_CNT2 0 0x407 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA0_DSM_CNTL 0 0x408 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA0_DSM_CNTLA 0 0x409 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA0_DSM_CNTLB 0 0x40a 0 0 0 regMMEA0_DSM_CNTL2 0 0x40b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA0_DSM_CNTL2A 0 0x40c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA0_DSM_CNTL2B 0 0x40d 0 0 0 regMMEA0_CGTT_CLK_CTRL 0 0x40f 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA0_EDC_MODE 0 0x410 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA0_ERR_STATUS 0 0x411 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA0_MISC2 0 0x412 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA0_ADDRDEC_SELECT 0 0x413 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA0_EDC_CNT3 0 0x414 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA0_MISC_AON 0 0x415 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMMEA1_DRAM_RD_CLI2GRP_MAP0 0 0x440 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_DRAM_RD_CLI2GRP_MAP1 0 0x441 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_DRAM_WR_CLI2GRP_MAP0 0 0x442 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_DRAM_WR_CLI2GRP_MAP1 0 0x443 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_DRAM_RD_GRP2VC_MAP 0 0x444 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA1_DRAM_WR_GRP2VC_MAP 0 0x445 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA1_DRAM_RD_LAZY 0 0x446 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA1_DRAM_WR_LAZY 0 0x447 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA1_DRAM_RD_CAM_CNTL 0 0x448 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA1_DRAM_WR_CAM_CNTL 0 0x449 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA1_DRAM_PAGE_BURST 0 0x44a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA1_DRAM_RD_PRI_AGE 0 0x44b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_DRAM_WR_PRI_AGE 0 0x44c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_DRAM_RD_PRI_QUEUING 0 0x44d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_DRAM_WR_PRI_QUEUING 0 0x44e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_DRAM_RD_PRI_FIXED 0 0x44f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_DRAM_WR_PRI_FIXED 0 0x450 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_DRAM_RD_PRI_URGENCY 0 0x451 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_DRAM_WR_PRI_URGENCY 0 0x452 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_DRAM_RD_PRI_QUANT_PRI1 0 0x453 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_DRAM_RD_PRI_QUANT_PRI2 0 0x454 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_DRAM_RD_PRI_QUANT_PRI3 0 0x455 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_DRAM_WR_PRI_QUANT_PRI1 0 0x456 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_DRAM_WR_PRI_QUANT_PRI2 0 0x457 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_DRAM_WR_PRI_QUANT_PRI3 0 0x458 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_RD_CLI2GRP_MAP0 0 0x459 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_GMI_RD_CLI2GRP_MAP1 0 0x45a 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_GMI_WR_CLI2GRP_MAP0 0 0x45b 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_GMI_WR_CLI2GRP_MAP1 0 0x45c 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_GMI_RD_GRP2VC_MAP 0 0x45d 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA1_GMI_WR_GRP2VC_MAP 0 0x45e 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA1_GMI_RD_LAZY 0 0x45f 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA1_GMI_WR_LAZY 0 0x460 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA1_GMI_RD_CAM_CNTL 0 0x461 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA1_GMI_WR_CAM_CNTL 0 0x462 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA1_GMI_PAGE_BURST 0 0x463 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA1_GMI_RD_PRI_AGE 0 0x464 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_GMI_WR_PRI_AGE 0 0x465 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_GMI_RD_PRI_QUEUING 0 0x466 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_GMI_WR_PRI_QUEUING 0 0x467 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_GMI_RD_PRI_FIXED 0 0x468 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_GMI_WR_PRI_FIXED 0 0x469 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_GMI_RD_PRI_URGENCY 0 0x46a 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_GMI_WR_PRI_URGENCY 0 0x46b 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_GMI_RD_PRI_URGENCY_MASKING 0 0x46c 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA1_GMI_WR_PRI_URGENCY_MASKING 0 0x46d 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA1_GMI_RD_PRI_QUANT_PRI1 0 0x46e 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_RD_PRI_QUANT_PRI2 0 0x46f 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_RD_PRI_QUANT_PRI3 0 0x470 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_WR_PRI_QUANT_PRI1 0 0x471 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_WR_PRI_QUANT_PRI2 0 0x472 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_GMI_WR_PRI_QUANT_PRI3 0 0x473 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_ADDRNORM_BASE_ADDR0 0 0x474 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_LIMIT_ADDR0 0 0x475 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORM_BASE_ADDR1 0 0x476 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_LIMIT_ADDR1 0 0x477 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORM_OFFSET_ADDR1 0 0x478 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA1_ADDRNORM_BASE_ADDR2 0 0x479 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_LIMIT_ADDR2 0 0x47a 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORM_BASE_ADDR3 0 0x47b 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_LIMIT_ADDR3 0 0x47c 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORM_OFFSET_ADDR3 0 0x47d 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA1_ADDRNORM_MEGABASE_ADDR0 0 0x47e 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_MEGALIMIT_ADDR0 0 0x47f 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORM_MEGABASE_ADDR1 0 0x480 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA1_ADDRNORM_MEGALIMIT_ADDR1 0 0x481 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA1_ADDRNORMDRAM_HOLE_CNTL 0 0x483 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA1_ADDRNORMGMI_HOLE_CNTL 0 0x484 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x485 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x486 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA1_ADDRDEC_BANK_CFG 0 0x487 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA1_ADDRDEC_MISC_CFG 0 0x488 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0 0x493 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA1_ADDRDECGMI_HARVEST_ENABLE 0 0x49e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA1_ADDRDEC0_BASE_ADDR_CS0 0 0x49f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_CS1 0 0x4a0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_CS2 0 0x4a1 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_CS3 0 0x4a2 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0 0x4a3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0 0x4a4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0 0x4a5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0 0x4a6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC0_ADDR_MASK_CS01 0 0x4a7 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC0_ADDR_MASK_CS23 0 0x4a8 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0 0x4a9 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0 0x4aa 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC0_ADDR_CFG_CS01 0 0x4ab 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC0_ADDR_CFG_CS23 0 0x4ac 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC0_ADDR_SEL_CS01 0 0x4ad 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC0_ADDR_SEL_CS23 0 0x4ae 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0 0x4af 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0 0x4b0 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0 0x4b1 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0 0x4b2 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0 0x4b3 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0 0x4b4 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC0_RM_SEL_CS01 0 0x4b5 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC0_RM_SEL_CS23 0 0x4b6 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC0_RM_SEL_SECCS01 0 0x4b7 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC0_RM_SEL_SECCS23 0 0x4b8 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC1_BASE_ADDR_CS0 0 0x4b9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_CS1 0 0x4ba 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_CS2 0 0x4bb 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_CS3 0 0x4bc 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0 0x4bd 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0 0x4be 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0 0x4bf 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0 0x4c0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC1_ADDR_MASK_CS01 0 0x4c1 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC1_ADDR_MASK_CS23 0 0x4c2 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0 0x4c3 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0 0x4c4 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC1_ADDR_CFG_CS01 0 0x4c5 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC1_ADDR_CFG_CS23 0 0x4c6 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC1_ADDR_SEL_CS01 0 0x4c7 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC1_ADDR_SEL_CS23 0 0x4c8 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0 0x4c9 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0 0x4ca 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0 0x4cb 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0 0x4cc 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0 0x4cd 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0 0x4ce 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC1_RM_SEL_CS01 0 0x4cf 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC1_RM_SEL_CS23 0 0x4d0 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC1_RM_SEL_SECCS01 0 0x4d1 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC1_RM_SEL_SECCS23 0 0x4d2 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC2_BASE_ADDR_CS0 0 0x4d3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_CS1 0 0x4d4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_CS2 0 0x4d5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_CS3 0 0x4d6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0 0x4d7 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0 0x4d8 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0 0x4d9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0 0x4da 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA1_ADDRDEC2_ADDR_MASK_CS01 0 0x4db 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC2_ADDR_MASK_CS23 0 0x4dc 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0 0x4dd 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0 0x4de 1 0 0 ADDR_MASK 1 31 regMMEA1_ADDRDEC2_ADDR_CFG_CS01 0 0x4df 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC2_ADDR_CFG_CS23 0 0x4e0 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA1_ADDRDEC2_ADDR_SEL_CS01 0 0x4e1 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC2_ADDR_SEL_CS23 0 0x4e2 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0 0x4e3 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0 0x4e4 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0 0x4e5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0 0x4e6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0 0x4e7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0 0x4e8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA1_ADDRDEC2_RM_SEL_CS01 0 0x4e9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC2_RM_SEL_CS23 0 0x4ea 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC2_RM_SEL_SECCS01 0 0x4eb 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRDEC2_RM_SEL_SECCS23 0 0x4ec 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0 0x4ed 0 0 0 regMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0 0x4ee 0 0 0 regMMEA1_ADDRNORM_MEGACONTROL_ADDR0 0 0x511 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA1_ADDRNORM_MEGACONTROL_ADDR1 0 0x512 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA1_ADDRNORMDRAM_MASKING 0 0x513 1 0 0 ADDRHI_MASK 0 11 regMMEA1_ADDRNORMGMI_MASKING 0 0x514 1 0 0 ADDRHI_MASK 0 11 regMMEA1_IO_RD_CLI2GRP_MAP0 0 0x515 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_IO_RD_CLI2GRP_MAP1 0 0x516 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_IO_WR_CLI2GRP_MAP0 0 0x517 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA1_IO_WR_CLI2GRP_MAP1 0 0x518 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA1_IO_RD_COMBINE_FLUSH 0 0x519 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA1_IO_WR_COMBINE_FLUSH 0 0x51a 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA1_IO_GROUP_BURST 0 0x51b 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA1_IO_RD_PRI_AGE 0 0x51c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_IO_WR_PRI_AGE 0 0x51d 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA1_IO_RD_PRI_QUEUING 0 0x51e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_IO_WR_PRI_QUEUING 0 0x51f 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA1_IO_RD_PRI_FIXED 0 0x520 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_IO_WR_PRI_FIXED 0 0x521 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA1_IO_RD_PRI_URGENCY 0 0x522 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_IO_WR_PRI_URGENCY 0 0x523 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA1_IO_RD_PRI_URGENCY_MASKING 0 0x524 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA1_IO_WR_PRI_URGENCY_MASKING 0 0x525 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA1_IO_RD_PRI_QUANT_PRI1 0 0x526 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_IO_RD_PRI_QUANT_PRI2 0 0x527 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_IO_RD_PRI_QUANT_PRI3 0 0x528 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_IO_WR_PRI_QUANT_PRI1 0 0x529 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_IO_WR_PRI_QUANT_PRI2 0 0x52a 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_IO_WR_PRI_QUANT_PRI3 0 0x52b 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA1_SDP_ARB_DRAM 0 0x52c 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA1_SDP_ARB_GMI 0 0x52d 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA1_SDP_ARB_FINAL 0 0x52e 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA1_SDP_DRAM_PRIORITY 0 0x52f 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA1_SDP_GMI_PRIORITY 0 0x530 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA1_SDP_IO_PRIORITY 0 0x531 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA1_SDP_CREDITS 0 0x532 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA1_SDP_TAG_RESERVE0 0 0x533 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA1_SDP_TAG_RESERVE1 0 0x534 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA1_SDP_VCC_RESERVE0 0 0x535 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA1_SDP_VCC_RESERVE1 0 0x536 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA1_SDP_VCD_RESERVE0 0 0x537 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA1_SDP_VCD_RESERVE1 0 0x538 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA1_SDP_REQ_CNTL 0 0x539 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA1_MISC 0 0x53a 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA1_LATENCY_SAMPLING 0 0x53b 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA1_PERFCOUNTER_LO 0 0x53c 1 0 0 COUNTER_LO 0 31 regMMEA1_PERFCOUNTER_HI 0 0x53d 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA1_PERFCOUNTER0_CFG 0 0x53e 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA1_PERFCOUNTER1_CFG 0 0x53f 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA1_PERFCOUNTER_RSLT_CNTL 0 0x540 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA1_EDC_CNT 0 0x546 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA1_EDC_CNT2 0 0x547 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA1_DSM_CNTL 0 0x548 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA1_DSM_CNTLA 0 0x549 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA1_DSM_CNTLB 0 0x54a 0 0 0 regMMEA1_DSM_CNTL2 0 0x54b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA1_DSM_CNTL2A 0 0x54c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA1_DSM_CNTL2B 0 0x54d 0 0 0 regMMEA1_CGTT_CLK_CTRL 0 0x54f 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA1_EDC_MODE 0 0x550 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA1_ERR_STATUS 0 0x551 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA1_MISC2 0 0x552 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA1_ADDRDEC_SELECT 0 0x553 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA1_EDC_CNT3 0 0x554 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA1_MISC_AON 0 0x555 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMMEA2_DRAM_RD_CLI2GRP_MAP0 0 0x580 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_DRAM_RD_CLI2GRP_MAP1 0 0x581 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_DRAM_WR_CLI2GRP_MAP0 0 0x582 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_DRAM_WR_CLI2GRP_MAP1 0 0x583 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_DRAM_RD_GRP2VC_MAP 0 0x584 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA2_DRAM_WR_GRP2VC_MAP 0 0x585 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA2_DRAM_RD_LAZY 0 0x586 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA2_DRAM_WR_LAZY 0 0x587 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA2_DRAM_RD_CAM_CNTL 0 0x588 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA2_DRAM_WR_CAM_CNTL 0 0x589 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA2_DRAM_PAGE_BURST 0 0x58a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA2_DRAM_RD_PRI_AGE 0 0x58b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_DRAM_WR_PRI_AGE 0 0x58c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_DRAM_RD_PRI_QUEUING 0 0x58d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_DRAM_WR_PRI_QUEUING 0 0x58e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_DRAM_RD_PRI_FIXED 0 0x58f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_DRAM_WR_PRI_FIXED 0 0x590 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_DRAM_RD_PRI_URGENCY 0 0x591 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_DRAM_WR_PRI_URGENCY 0 0x592 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_DRAM_RD_PRI_QUANT_PRI1 0 0x593 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_DRAM_RD_PRI_QUANT_PRI2 0 0x594 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_DRAM_RD_PRI_QUANT_PRI3 0 0x595 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_DRAM_WR_PRI_QUANT_PRI1 0 0x596 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_DRAM_WR_PRI_QUANT_PRI2 0 0x597 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_DRAM_WR_PRI_QUANT_PRI3 0 0x598 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_RD_CLI2GRP_MAP0 0 0x599 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_GMI_RD_CLI2GRP_MAP1 0 0x59a 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_GMI_WR_CLI2GRP_MAP0 0 0x59b 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_GMI_WR_CLI2GRP_MAP1 0 0x59c 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_GMI_RD_GRP2VC_MAP 0 0x59d 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA2_GMI_WR_GRP2VC_MAP 0 0x59e 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA2_GMI_RD_LAZY 0 0x59f 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA2_GMI_WR_LAZY 0 0x5a0 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA2_GMI_RD_CAM_CNTL 0 0x5a1 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA2_GMI_WR_CAM_CNTL 0 0x5a2 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA2_GMI_PAGE_BURST 0 0x5a3 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA2_GMI_RD_PRI_AGE 0 0x5a4 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_GMI_WR_PRI_AGE 0 0x5a5 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_GMI_RD_PRI_QUEUING 0 0x5a6 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_GMI_WR_PRI_QUEUING 0 0x5a7 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_GMI_RD_PRI_FIXED 0 0x5a8 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_GMI_WR_PRI_FIXED 0 0x5a9 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_GMI_RD_PRI_URGENCY 0 0x5aa 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_GMI_WR_PRI_URGENCY 0 0x5ab 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_GMI_RD_PRI_URGENCY_MASKING 0 0x5ac 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA2_GMI_WR_PRI_URGENCY_MASKING 0 0x5ad 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA2_GMI_RD_PRI_QUANT_PRI1 0 0x5ae 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_RD_PRI_QUANT_PRI2 0 0x5af 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_RD_PRI_QUANT_PRI3 0 0x5b0 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_WR_PRI_QUANT_PRI1 0 0x5b1 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_WR_PRI_QUANT_PRI2 0 0x5b2 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_GMI_WR_PRI_QUANT_PRI3 0 0x5b3 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_ADDRNORM_BASE_ADDR0 0 0x5b4 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_LIMIT_ADDR0 0 0x5b5 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORM_BASE_ADDR1 0 0x5b6 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_LIMIT_ADDR1 0 0x5b7 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORM_OFFSET_ADDR1 0 0x5b8 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA2_ADDRNORM_BASE_ADDR2 0 0x5b9 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_LIMIT_ADDR2 0 0x5ba 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORM_BASE_ADDR3 0 0x5bb 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_LIMIT_ADDR3 0 0x5bc 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORM_OFFSET_ADDR3 0 0x5bd 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA2_ADDRNORM_MEGABASE_ADDR0 0 0x5be 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_MEGALIMIT_ADDR0 0 0x5bf 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORM_MEGABASE_ADDR1 0 0x5c0 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA2_ADDRNORM_MEGALIMIT_ADDR1 0 0x5c1 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA2_ADDRNORMDRAM_HOLE_CNTL 0 0x5c3 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA2_ADDRNORMGMI_HOLE_CNTL 0 0x5c4 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x5c5 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x5c6 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA2_ADDRDEC_BANK_CFG 0 0x5c7 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA2_ADDRDEC_MISC_CFG 0 0x5c8 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0 0x5d3 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA2_ADDRDECGMI_HARVEST_ENABLE 0 0x5de 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA2_ADDRDEC0_BASE_ADDR_CS0 0 0x5df 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_CS1 0 0x5e0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_CS2 0 0x5e1 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_CS3 0 0x5e2 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0 0x5e3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0 0x5e4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0 0x5e5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0 0x5e6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC0_ADDR_MASK_CS01 0 0x5e7 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC0_ADDR_MASK_CS23 0 0x5e8 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0 0x5e9 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0 0x5ea 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC0_ADDR_CFG_CS01 0 0x5eb 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC0_ADDR_CFG_CS23 0 0x5ec 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC0_ADDR_SEL_CS01 0 0x5ed 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC0_ADDR_SEL_CS23 0 0x5ee 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0 0x5ef 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0 0x5f0 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0 0x5f1 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0 0x5f2 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0 0x5f3 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0 0x5f4 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC0_RM_SEL_CS01 0 0x5f5 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC0_RM_SEL_CS23 0 0x5f6 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC0_RM_SEL_SECCS01 0 0x5f7 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC0_RM_SEL_SECCS23 0 0x5f8 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC1_BASE_ADDR_CS0 0 0x5f9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_CS1 0 0x5fa 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_CS2 0 0x5fb 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_CS3 0 0x5fc 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0 0x5fd 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0 0x5fe 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0 0x5ff 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0 0x600 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC1_ADDR_MASK_CS01 0 0x601 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC1_ADDR_MASK_CS23 0 0x602 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0 0x603 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0 0x604 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC1_ADDR_CFG_CS01 0 0x605 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC1_ADDR_CFG_CS23 0 0x606 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC1_ADDR_SEL_CS01 0 0x607 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC1_ADDR_SEL_CS23 0 0x608 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0 0x609 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0 0x60a 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0 0x60b 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0 0x60c 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0 0x60d 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0 0x60e 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC1_RM_SEL_CS01 0 0x60f 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC1_RM_SEL_CS23 0 0x610 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC1_RM_SEL_SECCS01 0 0x611 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC1_RM_SEL_SECCS23 0 0x612 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC2_BASE_ADDR_CS0 0 0x613 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_CS1 0 0x614 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_CS2 0 0x615 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_CS3 0 0x616 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0 0x617 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0 0x618 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0 0x619 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0 0x61a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA2_ADDRDEC2_ADDR_MASK_CS01 0 0x61b 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC2_ADDR_MASK_CS23 0 0x61c 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0 0x61d 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0 0x61e 1 0 0 ADDR_MASK 1 31 regMMEA2_ADDRDEC2_ADDR_CFG_CS01 0 0x61f 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC2_ADDR_CFG_CS23 0 0x620 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA2_ADDRDEC2_ADDR_SEL_CS01 0 0x621 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC2_ADDR_SEL_CS23 0 0x622 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0 0x623 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0 0x624 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0 0x625 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0 0x626 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0 0x627 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0 0x628 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA2_ADDRDEC2_RM_SEL_CS01 0 0x629 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC2_RM_SEL_CS23 0 0x62a 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC2_RM_SEL_SECCS01 0 0x62b 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRDEC2_RM_SEL_SECCS23 0 0x62c 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0 0x62d 0 0 0 regMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0 0x62e 0 0 0 regMMEA2_ADDRNORM_MEGACONTROL_ADDR0 0 0x651 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA2_ADDRNORM_MEGACONTROL_ADDR1 0 0x652 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA2_ADDRNORMDRAM_MASKING 0 0x653 1 0 0 ADDRHI_MASK 0 11 regMMEA2_ADDRNORMGMI_MASKING 0 0x654 1 0 0 ADDRHI_MASK 0 11 regMMEA2_IO_RD_CLI2GRP_MAP0 0 0x655 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_IO_RD_CLI2GRP_MAP1 0 0x656 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_IO_WR_CLI2GRP_MAP0 0 0x657 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA2_IO_WR_CLI2GRP_MAP1 0 0x658 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA2_IO_RD_COMBINE_FLUSH 0 0x659 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA2_IO_WR_COMBINE_FLUSH 0 0x65a 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA2_IO_GROUP_BURST 0 0x65b 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA2_IO_RD_PRI_AGE 0 0x65c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_IO_WR_PRI_AGE 0 0x65d 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA2_IO_RD_PRI_QUEUING 0 0x65e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_IO_WR_PRI_QUEUING 0 0x65f 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA2_IO_RD_PRI_FIXED 0 0x660 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_IO_WR_PRI_FIXED 0 0x661 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA2_IO_RD_PRI_URGENCY 0 0x662 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_IO_WR_PRI_URGENCY 0 0x663 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA2_IO_RD_PRI_URGENCY_MASKING 0 0x664 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA2_IO_WR_PRI_URGENCY_MASKING 0 0x665 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA2_IO_RD_PRI_QUANT_PRI1 0 0x666 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_IO_RD_PRI_QUANT_PRI2 0 0x667 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_IO_RD_PRI_QUANT_PRI3 0 0x668 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_IO_WR_PRI_QUANT_PRI1 0 0x669 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_IO_WR_PRI_QUANT_PRI2 0 0x66a 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_IO_WR_PRI_QUANT_PRI3 0 0x66b 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA2_SDP_ARB_DRAM 0 0x66c 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA2_SDP_ARB_GMI 0 0x66d 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA2_SDP_ARB_FINAL 0 0x66e 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA2_SDP_DRAM_PRIORITY 0 0x66f 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA2_SDP_GMI_PRIORITY 0 0x670 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA2_SDP_IO_PRIORITY 0 0x671 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA2_SDP_CREDITS 0 0x672 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA2_SDP_TAG_RESERVE0 0 0x673 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA2_SDP_TAG_RESERVE1 0 0x674 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA2_SDP_VCC_RESERVE0 0 0x675 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA2_SDP_VCC_RESERVE1 0 0x676 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA2_SDP_VCD_RESERVE0 0 0x677 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA2_SDP_VCD_RESERVE1 0 0x678 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA2_SDP_REQ_CNTL 0 0x679 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA2_MISC 0 0x67a 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA2_LATENCY_SAMPLING 0 0x67b 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA2_PERFCOUNTER_LO 0 0x67c 1 0 0 COUNTER_LO 0 31 regMMEA2_PERFCOUNTER_HI 0 0x67d 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA2_PERFCOUNTER0_CFG 0 0x67e 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA2_PERFCOUNTER1_CFG 0 0x67f 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA2_PERFCOUNTER_RSLT_CNTL 0 0x680 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA2_EDC_CNT 0 0x686 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA2_EDC_CNT2 0 0x687 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA2_DSM_CNTL 0 0x688 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA2_DSM_CNTLA 0 0x689 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA2_DSM_CNTLB 0 0x68a 0 0 0 regMMEA2_DSM_CNTL2 0 0x68b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA2_DSM_CNTL2A 0 0x68c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA2_DSM_CNTL2B 0 0x68d 0 0 0 regMMEA2_CGTT_CLK_CTRL 0 0x68f 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA2_EDC_MODE 0 0x690 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA2_ERR_STATUS 0 0x691 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA2_MISC2 0 0x692 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA2_ADDRDEC_SELECT 0 0x693 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA2_EDC_CNT3 0 0x694 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA2_MISC_AON 0 0x695 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMMEA3_DRAM_RD_CLI2GRP_MAP0 0 0x6c0 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_DRAM_RD_CLI2GRP_MAP1 0 0x6c1 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_DRAM_WR_CLI2GRP_MAP0 0 0x6c2 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_DRAM_WR_CLI2GRP_MAP1 0 0x6c3 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_DRAM_RD_GRP2VC_MAP 0 0x6c4 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA3_DRAM_WR_GRP2VC_MAP 0 0x6c5 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA3_DRAM_RD_LAZY 0 0x6c6 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA3_DRAM_WR_LAZY 0 0x6c7 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA3_DRAM_RD_CAM_CNTL 0 0x6c8 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA3_DRAM_WR_CAM_CNTL 0 0x6c9 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA3_DRAM_PAGE_BURST 0 0x6ca 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA3_DRAM_RD_PRI_AGE 0 0x6cb 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_DRAM_WR_PRI_AGE 0 0x6cc 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_DRAM_RD_PRI_QUEUING 0 0x6cd 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_DRAM_WR_PRI_QUEUING 0 0x6ce 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_DRAM_RD_PRI_FIXED 0 0x6cf 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_DRAM_WR_PRI_FIXED 0 0x6d0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_DRAM_RD_PRI_URGENCY 0 0x6d1 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_DRAM_WR_PRI_URGENCY 0 0x6d2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_DRAM_RD_PRI_QUANT_PRI1 0 0x6d3 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_DRAM_RD_PRI_QUANT_PRI2 0 0x6d4 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_DRAM_RD_PRI_QUANT_PRI3 0 0x6d5 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_DRAM_WR_PRI_QUANT_PRI1 0 0x6d6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_DRAM_WR_PRI_QUANT_PRI2 0 0x6d7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_DRAM_WR_PRI_QUANT_PRI3 0 0x6d8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_RD_CLI2GRP_MAP0 0 0x6d9 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_GMI_RD_CLI2GRP_MAP1 0 0x6da 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_GMI_WR_CLI2GRP_MAP0 0 0x6db 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_GMI_WR_CLI2GRP_MAP1 0 0x6dc 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_GMI_RD_GRP2VC_MAP 0 0x6dd 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA3_GMI_WR_GRP2VC_MAP 0 0x6de 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA3_GMI_RD_LAZY 0 0x6df 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA3_GMI_WR_LAZY 0 0x6e0 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA3_GMI_RD_CAM_CNTL 0 0x6e1 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA3_GMI_WR_CAM_CNTL 0 0x6e2 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA3_GMI_PAGE_BURST 0 0x6e3 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA3_GMI_RD_PRI_AGE 0 0x6e4 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_GMI_WR_PRI_AGE 0 0x6e5 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_GMI_RD_PRI_QUEUING 0 0x6e6 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_GMI_WR_PRI_QUEUING 0 0x6e7 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_GMI_RD_PRI_FIXED 0 0x6e8 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_GMI_WR_PRI_FIXED 0 0x6e9 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_GMI_RD_PRI_URGENCY 0 0x6ea 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_GMI_WR_PRI_URGENCY 0 0x6eb 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_GMI_RD_PRI_URGENCY_MASKING 0 0x6ec 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA3_GMI_WR_PRI_URGENCY_MASKING 0 0x6ed 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA3_GMI_RD_PRI_QUANT_PRI1 0 0x6ee 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_RD_PRI_QUANT_PRI2 0 0x6ef 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_RD_PRI_QUANT_PRI3 0 0x6f0 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_WR_PRI_QUANT_PRI1 0 0x6f1 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_WR_PRI_QUANT_PRI2 0 0x6f2 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_GMI_WR_PRI_QUANT_PRI3 0 0x6f3 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_ADDRNORM_BASE_ADDR0 0 0x6f4 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_LIMIT_ADDR0 0 0x6f5 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORM_BASE_ADDR1 0 0x6f6 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_LIMIT_ADDR1 0 0x6f7 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORM_OFFSET_ADDR1 0 0x6f8 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA3_ADDRNORM_BASE_ADDR2 0 0x6f9 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_LIMIT_ADDR2 0 0x6fa 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORM_BASE_ADDR3 0 0x6fb 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_LIMIT_ADDR3 0 0x6fc 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORM_OFFSET_ADDR3 0 0x6fd 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA3_ADDRNORM_MEGABASE_ADDR0 0 0x6fe 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_MEGALIMIT_ADDR0 0 0x6ff 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORM_MEGABASE_ADDR1 0 0x700 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA3_ADDRNORM_MEGALIMIT_ADDR1 0 0x701 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA3_ADDRNORMDRAM_HOLE_CNTL 0 0x703 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA3_ADDRNORMGMI_HOLE_CNTL 0 0x704 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x705 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x706 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA3_ADDRDEC_BANK_CFG 0 0x707 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA3_ADDRDEC_MISC_CFG 0 0x708 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0 0x713 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA3_ADDRDECGMI_HARVEST_ENABLE 0 0x71e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA3_ADDRDEC0_BASE_ADDR_CS0 0 0x71f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_CS1 0 0x720 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_CS2 0 0x721 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_CS3 0 0x722 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0 0x723 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0 0x724 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0 0x725 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0 0x726 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC0_ADDR_MASK_CS01 0 0x727 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC0_ADDR_MASK_CS23 0 0x728 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0 0x729 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0 0x72a 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC0_ADDR_CFG_CS01 0 0x72b 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC0_ADDR_CFG_CS23 0 0x72c 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC0_ADDR_SEL_CS01 0 0x72d 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC0_ADDR_SEL_CS23 0 0x72e 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0 0x72f 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0 0x730 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0 0x731 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0 0x732 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0 0x733 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0 0x734 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC0_RM_SEL_CS01 0 0x735 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC0_RM_SEL_CS23 0 0x736 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC0_RM_SEL_SECCS01 0 0x737 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC0_RM_SEL_SECCS23 0 0x738 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC1_BASE_ADDR_CS0 0 0x739 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_CS1 0 0x73a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_CS2 0 0x73b 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_CS3 0 0x73c 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0 0x73d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0 0x73e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0 0x73f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0 0x740 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC1_ADDR_MASK_CS01 0 0x741 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC1_ADDR_MASK_CS23 0 0x742 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0 0x743 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0 0x744 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC1_ADDR_CFG_CS01 0 0x745 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC1_ADDR_CFG_CS23 0 0x746 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC1_ADDR_SEL_CS01 0 0x747 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC1_ADDR_SEL_CS23 0 0x748 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0 0x749 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0 0x74a 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0 0x74b 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0 0x74c 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0 0x74d 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0 0x74e 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC1_RM_SEL_CS01 0 0x74f 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC1_RM_SEL_CS23 0 0x750 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC1_RM_SEL_SECCS01 0 0x751 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC1_RM_SEL_SECCS23 0 0x752 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC2_BASE_ADDR_CS0 0 0x753 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_CS1 0 0x754 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_CS2 0 0x755 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_CS3 0 0x756 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0 0x757 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0 0x758 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0 0x759 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0 0x75a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA3_ADDRDEC2_ADDR_MASK_CS01 0 0x75b 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC2_ADDR_MASK_CS23 0 0x75c 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0 0x75d 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0 0x75e 1 0 0 ADDR_MASK 1 31 regMMEA3_ADDRDEC2_ADDR_CFG_CS01 0 0x75f 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC2_ADDR_CFG_CS23 0 0x760 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA3_ADDRDEC2_ADDR_SEL_CS01 0 0x761 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC2_ADDR_SEL_CS23 0 0x762 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0 0x763 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0 0x764 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0 0x765 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0 0x766 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0 0x767 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0 0x768 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA3_ADDRDEC2_RM_SEL_CS01 0 0x769 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC2_RM_SEL_CS23 0 0x76a 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC2_RM_SEL_SECCS01 0 0x76b 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRDEC2_RM_SEL_SECCS23 0 0x76c 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0 0x76d 0 0 0 regMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0 0x76e 0 0 0 regMMEA3_ADDRNORM_MEGACONTROL_ADDR0 0 0x791 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA3_ADDRNORM_MEGACONTROL_ADDR1 0 0x792 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA3_ADDRNORMDRAM_MASKING 0 0x793 1 0 0 ADDRHI_MASK 0 11 regMMEA3_ADDRNORMGMI_MASKING 0 0x794 1 0 0 ADDRHI_MASK 0 11 regMMEA3_IO_RD_CLI2GRP_MAP0 0 0x795 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_IO_RD_CLI2GRP_MAP1 0 0x796 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_IO_WR_CLI2GRP_MAP0 0 0x797 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA3_IO_WR_CLI2GRP_MAP1 0 0x798 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA3_IO_RD_COMBINE_FLUSH 0 0x799 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA3_IO_WR_COMBINE_FLUSH 0 0x79a 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA3_IO_GROUP_BURST 0 0x79b 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA3_IO_RD_PRI_AGE 0 0x79c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_IO_WR_PRI_AGE 0 0x79d 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA3_IO_RD_PRI_QUEUING 0 0x79e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_IO_WR_PRI_QUEUING 0 0x79f 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA3_IO_RD_PRI_FIXED 0 0x7a0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_IO_WR_PRI_FIXED 0 0x7a1 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA3_IO_RD_PRI_URGENCY 0 0x7a2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_IO_WR_PRI_URGENCY 0 0x7a3 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA3_IO_RD_PRI_URGENCY_MASKING 0 0x7a4 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA3_IO_WR_PRI_URGENCY_MASKING 0 0x7a5 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA3_IO_RD_PRI_QUANT_PRI1 0 0x7a6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_IO_RD_PRI_QUANT_PRI2 0 0x7a7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_IO_RD_PRI_QUANT_PRI3 0 0x7a8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_IO_WR_PRI_QUANT_PRI1 0 0x7a9 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_IO_WR_PRI_QUANT_PRI2 0 0x7aa 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_IO_WR_PRI_QUANT_PRI3 0 0x7ab 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA3_SDP_ARB_DRAM 0 0x7ac 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA3_SDP_ARB_GMI 0 0x7ad 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA3_SDP_ARB_FINAL 0 0x7ae 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA3_SDP_DRAM_PRIORITY 0 0x7af 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA3_SDP_GMI_PRIORITY 0 0x7b0 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA3_SDP_IO_PRIORITY 0 0x7b1 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA3_SDP_CREDITS 0 0x7b2 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA3_SDP_TAG_RESERVE0 0 0x7b3 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA3_SDP_TAG_RESERVE1 0 0x7b4 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA3_SDP_VCC_RESERVE0 0 0x7b5 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA3_SDP_VCC_RESERVE1 0 0x7b6 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA3_SDP_VCD_RESERVE0 0 0x7b7 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA3_SDP_VCD_RESERVE1 0 0x7b8 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA3_SDP_REQ_CNTL 0 0x7b9 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA3_MISC 0 0x7ba 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA3_LATENCY_SAMPLING 0 0x7bb 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA3_PERFCOUNTER_LO 0 0x7bc 1 0 0 COUNTER_LO 0 31 regMMEA3_PERFCOUNTER_HI 0 0x7bd 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA3_PERFCOUNTER0_CFG 0 0x7be 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA3_PERFCOUNTER1_CFG 0 0x7bf 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA3_PERFCOUNTER_RSLT_CNTL 0 0x7c0 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA3_EDC_CNT 0 0x7c6 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA3_EDC_CNT2 0 0x7c7 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA3_DSM_CNTL 0 0x7c8 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA3_DSM_CNTLA 0 0x7c9 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA3_DSM_CNTLB 0 0x7ca 0 0 0 regMMEA3_DSM_CNTL2 0 0x7cb 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA3_DSM_CNTL2A 0 0x7cc 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA3_DSM_CNTL2B 0 0x7cd 0 0 0 regMMEA3_CGTT_CLK_CTRL 0 0x7cf 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA3_EDC_MODE 0 0x7d0 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA3_ERR_STATUS 0 0x7d1 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA3_MISC2 0 0x7d2 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA3_ADDRDEC_SELECT 0 0x7d3 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA3_EDC_CNT3 0 0x7d4 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA3_MISC_AON 0 0x7d5 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMMEA4_DRAM_RD_CLI2GRP_MAP0 0 0x800 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_DRAM_RD_CLI2GRP_MAP1 0 0x801 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_DRAM_WR_CLI2GRP_MAP0 0 0x802 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_DRAM_WR_CLI2GRP_MAP1 0 0x803 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_DRAM_RD_GRP2VC_MAP 0 0x804 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA4_DRAM_WR_GRP2VC_MAP 0 0x805 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA4_DRAM_RD_LAZY 0 0x806 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA4_DRAM_WR_LAZY 0 0x807 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA4_DRAM_RD_CAM_CNTL 0 0x808 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA4_DRAM_WR_CAM_CNTL 0 0x809 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA4_DRAM_PAGE_BURST 0 0x80a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA4_DRAM_RD_PRI_AGE 0 0x80b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_DRAM_WR_PRI_AGE 0 0x80c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_DRAM_RD_PRI_QUEUING 0 0x80d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_DRAM_WR_PRI_QUEUING 0 0x80e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_DRAM_RD_PRI_FIXED 0 0x80f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_DRAM_WR_PRI_FIXED 0 0x810 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_DRAM_RD_PRI_URGENCY 0 0x811 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_DRAM_WR_PRI_URGENCY 0 0x812 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_DRAM_RD_PRI_QUANT_PRI1 0 0x813 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_DRAM_RD_PRI_QUANT_PRI2 0 0x814 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_DRAM_RD_PRI_QUANT_PRI3 0 0x815 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_DRAM_WR_PRI_QUANT_PRI1 0 0x816 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_DRAM_WR_PRI_QUANT_PRI2 0 0x817 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_DRAM_WR_PRI_QUANT_PRI3 0 0x818 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_RD_CLI2GRP_MAP0 0 0x819 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_GMI_RD_CLI2GRP_MAP1 0 0x81a 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_GMI_WR_CLI2GRP_MAP0 0 0x81b 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_GMI_WR_CLI2GRP_MAP1 0 0x81c 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_GMI_RD_GRP2VC_MAP 0 0x81d 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA4_GMI_WR_GRP2VC_MAP 0 0x81e 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA4_GMI_RD_LAZY 0 0x81f 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA4_GMI_WR_LAZY 0 0x820 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA4_GMI_RD_CAM_CNTL 0 0x821 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA4_GMI_WR_CAM_CNTL 0 0x822 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA4_GMI_PAGE_BURST 0 0x823 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA4_GMI_RD_PRI_AGE 0 0x824 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_GMI_WR_PRI_AGE 0 0x825 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_GMI_RD_PRI_QUEUING 0 0x826 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_GMI_WR_PRI_QUEUING 0 0x827 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_GMI_RD_PRI_FIXED 0 0x828 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_GMI_WR_PRI_FIXED 0 0x829 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_GMI_RD_PRI_URGENCY 0 0x82a 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_GMI_WR_PRI_URGENCY 0 0x82b 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_GMI_RD_PRI_URGENCY_MASKING 0 0x82c 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA4_GMI_WR_PRI_URGENCY_MASKING 0 0x82d 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA4_GMI_RD_PRI_QUANT_PRI1 0 0x82e 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_RD_PRI_QUANT_PRI2 0 0x82f 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_RD_PRI_QUANT_PRI3 0 0x830 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_WR_PRI_QUANT_PRI1 0 0x831 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_WR_PRI_QUANT_PRI2 0 0x832 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_GMI_WR_PRI_QUANT_PRI3 0 0x833 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_ADDRNORM_BASE_ADDR0 0 0x834 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_LIMIT_ADDR0 0 0x835 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORM_BASE_ADDR1 0 0x836 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_LIMIT_ADDR1 0 0x837 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORM_OFFSET_ADDR1 0 0x838 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA4_ADDRNORM_BASE_ADDR2 0 0x839 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_LIMIT_ADDR2 0 0x83a 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORM_BASE_ADDR3 0 0x83b 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_LIMIT_ADDR3 0 0x83c 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORM_OFFSET_ADDR3 0 0x83d 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA4_ADDRNORM_MEGABASE_ADDR0 0 0x83e 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_MEGALIMIT_ADDR0 0 0x83f 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORM_MEGABASE_ADDR1 0 0x840 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA4_ADDRNORM_MEGALIMIT_ADDR1 0 0x841 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA4_ADDRNORMDRAM_HOLE_CNTL 0 0x843 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA4_ADDRNORMGMI_HOLE_CNTL 0 0x844 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x845 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x846 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA4_ADDRDEC_BANK_CFG 0 0x847 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA4_ADDRDEC_MISC_CFG 0 0x848 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0 0x853 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA4_ADDRDECGMI_HARVEST_ENABLE 0 0x85e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA4_ADDRDEC0_BASE_ADDR_CS0 0 0x85f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_CS1 0 0x860 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_CS2 0 0x861 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_CS3 0 0x862 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0 0x863 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0 0x864 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0 0x865 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0 0x866 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC0_ADDR_MASK_CS01 0 0x867 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC0_ADDR_MASK_CS23 0 0x868 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0 0x869 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0 0x86a 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC0_ADDR_CFG_CS01 0 0x86b 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC0_ADDR_CFG_CS23 0 0x86c 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC0_ADDR_SEL_CS01 0 0x86d 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC0_ADDR_SEL_CS23 0 0x86e 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0 0x86f 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0 0x870 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0 0x871 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0 0x872 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0 0x873 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0 0x874 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC0_RM_SEL_CS01 0 0x875 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC0_RM_SEL_CS23 0 0x876 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC0_RM_SEL_SECCS01 0 0x877 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC0_RM_SEL_SECCS23 0 0x878 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC1_BASE_ADDR_CS0 0 0x879 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_CS1 0 0x87a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_CS2 0 0x87b 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_CS3 0 0x87c 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0 0x87d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0 0x87e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0 0x87f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0 0x880 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC1_ADDR_MASK_CS01 0 0x881 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC1_ADDR_MASK_CS23 0 0x882 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0 0x883 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0 0x884 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC1_ADDR_CFG_CS01 0 0x885 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC1_ADDR_CFG_CS23 0 0x886 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC1_ADDR_SEL_CS01 0 0x887 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC1_ADDR_SEL_CS23 0 0x888 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0 0x889 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0 0x88a 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0 0x88b 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0 0x88c 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0 0x88d 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0 0x88e 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC1_RM_SEL_CS01 0 0x88f 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC1_RM_SEL_CS23 0 0x890 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC1_RM_SEL_SECCS01 0 0x891 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC1_RM_SEL_SECCS23 0 0x892 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC2_BASE_ADDR_CS0 0 0x893 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_CS1 0 0x894 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_CS2 0 0x895 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_CS3 0 0x896 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0 0x897 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0 0x898 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0 0x899 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0 0x89a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA4_ADDRDEC2_ADDR_MASK_CS01 0 0x89b 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC2_ADDR_MASK_CS23 0 0x89c 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0 0x89d 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0 0x89e 1 0 0 ADDR_MASK 1 31 regMMEA4_ADDRDEC2_ADDR_CFG_CS01 0 0x89f 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC2_ADDR_CFG_CS23 0 0x8a0 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA4_ADDRDEC2_ADDR_SEL_CS01 0 0x8a1 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC2_ADDR_SEL_CS23 0 0x8a2 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0 0x8a3 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0 0x8a4 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0 0x8a5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0 0x8a6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0 0x8a7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0 0x8a8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA4_ADDRDEC2_RM_SEL_CS01 0 0x8a9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC2_RM_SEL_CS23 0 0x8aa 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC2_RM_SEL_SECCS01 0 0x8ab 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRDEC2_RM_SEL_SECCS23 0 0x8ac 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0 0x8ad 0 0 0 regMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0 0x8ae 0 0 0 regMMEA4_ADDRNORM_MEGACONTROL_ADDR0 0 0x8d1 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA4_ADDRNORM_MEGACONTROL_ADDR1 0 0x8d2 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA4_ADDRNORMDRAM_MASKING 0 0x8d3 1 0 0 ADDRHI_MASK 0 11 regMMEA4_ADDRNORMGMI_MASKING 0 0x8d4 1 0 0 ADDRHI_MASK 0 11 regMMEA4_IO_RD_CLI2GRP_MAP0 0 0x8d5 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_IO_RD_CLI2GRP_MAP1 0 0x8d6 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_IO_WR_CLI2GRP_MAP0 0 0x8d7 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA4_IO_WR_CLI2GRP_MAP1 0 0x8d8 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA4_IO_RD_COMBINE_FLUSH 0 0x8d9 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA4_IO_WR_COMBINE_FLUSH 0 0x8da 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA4_IO_GROUP_BURST 0 0x8db 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA4_IO_RD_PRI_AGE 0 0x8dc 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_IO_WR_PRI_AGE 0 0x8dd 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA4_IO_RD_PRI_QUEUING 0 0x8de 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_IO_WR_PRI_QUEUING 0 0x8df 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA4_IO_RD_PRI_FIXED 0 0x8e0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_IO_WR_PRI_FIXED 0 0x8e1 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA4_IO_RD_PRI_URGENCY 0 0x8e2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_IO_WR_PRI_URGENCY 0 0x8e3 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA4_IO_RD_PRI_URGENCY_MASKING 0 0x8e4 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA4_IO_WR_PRI_URGENCY_MASKING 0 0x8e5 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA4_IO_RD_PRI_QUANT_PRI1 0 0x8e6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_IO_RD_PRI_QUANT_PRI2 0 0x8e7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_IO_RD_PRI_QUANT_PRI3 0 0x8e8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_IO_WR_PRI_QUANT_PRI1 0 0x8e9 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_IO_WR_PRI_QUANT_PRI2 0 0x8ea 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_IO_WR_PRI_QUANT_PRI3 0 0x8eb 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA4_SDP_ARB_DRAM 0 0x8ec 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA4_SDP_ARB_GMI 0 0x8ed 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA4_SDP_ARB_FINAL 0 0x8ee 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA4_SDP_DRAM_PRIORITY 0 0x8ef 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA4_SDP_GMI_PRIORITY 0 0x8f0 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA4_SDP_IO_PRIORITY 0 0x8f1 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA4_SDP_CREDITS 0 0x8f2 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA4_SDP_TAG_RESERVE0 0 0x8f3 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA4_SDP_TAG_RESERVE1 0 0x8f4 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA4_SDP_VCC_RESERVE0 0 0x8f5 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA4_SDP_VCC_RESERVE1 0 0x8f6 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA4_SDP_VCD_RESERVE0 0 0x8f7 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA4_SDP_VCD_RESERVE1 0 0x8f8 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA4_SDP_REQ_CNTL 0 0x8f9 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA4_MISC 0 0x8fa 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA4_LATENCY_SAMPLING 0 0x8fb 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA4_PERFCOUNTER_LO 0 0x8fc 1 0 0 COUNTER_LO 0 31 regMMEA4_PERFCOUNTER_HI 0 0x8fd 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA4_PERFCOUNTER0_CFG 0 0x8fe 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA4_PERFCOUNTER1_CFG 0 0x8ff 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA4_PERFCOUNTER_RSLT_CNTL 0 0x900 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA4_EDC_CNT 0 0x906 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA4_EDC_CNT2 0 0x907 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA4_DSM_CNTL 0 0x908 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA4_DSM_CNTLA 0 0x909 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA4_DSM_CNTLB 0 0x90a 0 0 0 regMMEA4_DSM_CNTL2 0 0x90b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA4_DSM_CNTL2A 0 0x90c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA4_DSM_CNTL2B 0 0x90d 0 0 0 regMMEA4_CGTT_CLK_CTRL 0 0x90f 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA4_EDC_MODE 0 0x910 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA4_ERR_STATUS 0 0x911 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA4_MISC2 0 0x912 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA4_ADDRDEC_SELECT 0 0x913 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA4_EDC_CNT3 0 0x914 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA4_MISC_AON 0 0x915 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMMEA5_DRAM_RD_CLI2GRP_MAP0 0 0x940 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_DRAM_RD_CLI2GRP_MAP1 0 0x941 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_DRAM_WR_CLI2GRP_MAP0 0 0x942 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_DRAM_WR_CLI2GRP_MAP1 0 0x943 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_DRAM_RD_GRP2VC_MAP 0 0x944 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA5_DRAM_WR_GRP2VC_MAP 0 0x945 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA5_DRAM_RD_LAZY 0 0x946 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA5_DRAM_WR_LAZY 0 0x947 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA5_DRAM_RD_CAM_CNTL 0 0x948 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA5_DRAM_WR_CAM_CNTL 0 0x949 9 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 regMMEA5_DRAM_PAGE_BURST 0 0x94a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA5_DRAM_RD_PRI_AGE 0 0x94b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_DRAM_WR_PRI_AGE 0 0x94c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_DRAM_RD_PRI_QUEUING 0 0x94d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_DRAM_WR_PRI_QUEUING 0 0x94e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_DRAM_RD_PRI_FIXED 0 0x94f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_DRAM_WR_PRI_FIXED 0 0x950 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_DRAM_RD_PRI_URGENCY 0 0x951 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_DRAM_WR_PRI_URGENCY 0 0x952 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_DRAM_RD_PRI_QUANT_PRI1 0 0x953 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_DRAM_RD_PRI_QUANT_PRI2 0 0x954 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_DRAM_RD_PRI_QUANT_PRI3 0 0x955 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_DRAM_WR_PRI_QUANT_PRI1 0 0x956 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_DRAM_WR_PRI_QUANT_PRI2 0 0x957 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_DRAM_WR_PRI_QUANT_PRI3 0 0x958 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_RD_CLI2GRP_MAP0 0 0x959 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_GMI_RD_CLI2GRP_MAP1 0 0x95a 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_GMI_WR_CLI2GRP_MAP0 0 0x95b 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_GMI_WR_CLI2GRP_MAP1 0 0x95c 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_GMI_RD_GRP2VC_MAP 0 0x95d 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA5_GMI_WR_GRP2VC_MAP 0 0x95e 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 regMMEA5_GMI_RD_LAZY 0 0x95f 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA5_GMI_WR_LAZY 0 0x960 7 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 regMMEA5_GMI_RD_CAM_CNTL 0 0x961 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA5_GMI_WR_CAM_CNTL 0 0x962 10 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 regMMEA5_GMI_PAGE_BURST 0 0x963 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA5_GMI_RD_PRI_AGE 0 0x964 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_GMI_WR_PRI_AGE 0 0x965 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_GMI_RD_PRI_QUEUING 0 0x966 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_GMI_WR_PRI_QUEUING 0 0x967 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_GMI_RD_PRI_FIXED 0 0x968 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_GMI_WR_PRI_FIXED 0 0x969 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_GMI_RD_PRI_URGENCY 0 0x96a 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_GMI_WR_PRI_URGENCY 0 0x96b 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_GMI_RD_PRI_URGENCY_MASKING 0 0x96c 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA5_GMI_WR_PRI_URGENCY_MASKING 0 0x96d 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA5_GMI_RD_PRI_QUANT_PRI1 0 0x96e 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_RD_PRI_QUANT_PRI2 0 0x96f 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_RD_PRI_QUANT_PRI3 0 0x970 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_WR_PRI_QUANT_PRI1 0 0x971 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_WR_PRI_QUANT_PRI2 0 0x972 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_GMI_WR_PRI_QUANT_PRI3 0 0x973 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_ADDRNORM_BASE_ADDR0 0 0x974 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_LIMIT_ADDR0 0 0x975 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORM_BASE_ADDR1 0 0x976 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_LIMIT_ADDR1 0 0x977 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORM_OFFSET_ADDR1 0 0x978 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA5_ADDRNORM_BASE_ADDR2 0 0x979 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_LIMIT_ADDR2 0 0x97a 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORM_BASE_ADDR3 0 0x97b 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_LIMIT_ADDR3 0 0x97c 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORM_OFFSET_ADDR3 0 0x97d 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 12 23 regMMEA5_ADDRNORM_MEGABASE_ADDR0 0 0x97e 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_MEGALIMIT_ADDR0 0 0x97f 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORM_MEGABASE_ADDR1 0 0x980 7 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 6 INTLV_NUM_DIES 7 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 regMMEA5_ADDRNORM_MEGALIMIT_ADDR1 0 0x981 2 0 0 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 regMMEA5_ADDRNORMDRAM_HOLE_CNTL 0 0x983 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA5_ADDRNORMGMI_HOLE_CNTL 0 0x984 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 regMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x985 2 0 0 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 regMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x986 2 0 0 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 regMMEA5_ADDRDEC_BANK_CFG 0 0x987 6 0 0 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 regMMEA5_ADDRDEC_MISC_CFG 0 0x988 11 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 regMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0 0x993 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA5_ADDRDECGMI_HARVEST_ENABLE 0 0x99e 6 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 regMMEA5_ADDRDEC0_BASE_ADDR_CS0 0 0x99f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_CS1 0 0x9a0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_CS2 0 0x9a1 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_CS3 0 0x9a2 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0 0x9a3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0 0x9a4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0 0x9a5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0 0x9a6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC0_ADDR_MASK_CS01 0 0x9a7 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC0_ADDR_MASK_CS23 0 0x9a8 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0 0x9a9 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0 0x9aa 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC0_ADDR_CFG_CS01 0 0x9ab 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC0_ADDR_CFG_CS23 0 0x9ac 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC0_ADDR_SEL_CS01 0 0x9ad 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC0_ADDR_SEL_CS23 0 0x9ae 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0 0x9af 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0 0x9b0 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0 0x9b1 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0 0x9b2 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0 0x9b3 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0 0x9b4 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC0_RM_SEL_CS01 0 0x9b5 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC0_RM_SEL_CS23 0 0x9b6 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC0_RM_SEL_SECCS01 0 0x9b7 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC0_RM_SEL_SECCS23 0 0x9b8 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC1_BASE_ADDR_CS0 0 0x9b9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_CS1 0 0x9ba 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_CS2 0 0x9bb 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_CS3 0 0x9bc 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0 0x9bd 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0 0x9be 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0 0x9bf 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0 0x9c0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC1_ADDR_MASK_CS01 0 0x9c1 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC1_ADDR_MASK_CS23 0 0x9c2 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0 0x9c3 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0 0x9c4 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC1_ADDR_CFG_CS01 0 0x9c5 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC1_ADDR_CFG_CS23 0 0x9c6 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC1_ADDR_SEL_CS01 0 0x9c7 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC1_ADDR_SEL_CS23 0 0x9c8 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0 0x9c9 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0 0x9ca 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0 0x9cb 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0 0x9cc 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0 0x9cd 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0 0x9ce 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC1_RM_SEL_CS01 0 0x9cf 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC1_RM_SEL_CS23 0 0x9d0 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC1_RM_SEL_SECCS01 0 0x9d1 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC1_RM_SEL_SECCS23 0 0x9d2 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC2_BASE_ADDR_CS0 0 0x9d3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_CS1 0 0x9d4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_CS2 0 0x9d5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_CS3 0 0x9d6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0 0x9d7 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0 0x9d8 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0 0x9d9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0 0x9da 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 regMMEA5_ADDRDEC2_ADDR_MASK_CS01 0 0x9db 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC2_ADDR_MASK_CS23 0 0x9dc 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0 0x9dd 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0 0x9de 1 0 0 ADDR_MASK 1 31 regMMEA5_ADDRDEC2_ADDR_CFG_CS01 0 0x9df 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC2_ADDR_CFG_CS23 0 0x9e0 7 0 0 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 regMMEA5_ADDRDEC2_ADDR_SEL_CS01 0 0x9e1 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC2_ADDR_SEL_CS23 0 0x9e2 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 regMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0 0x9e3 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0 0x9e4 2 0 0 BANK5 0 4 CHAN_BIT 12 15 regMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0 0x9e5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0 0x9e6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 regMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0 0x9e7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0 0x9e8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 regMMEA5_ADDRDEC2_RM_SEL_CS01 0 0x9e9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC2_RM_SEL_CS23 0 0x9ea 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC2_RM_SEL_SECCS01 0 0x9eb 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRDEC2_RM_SEL_SECCS23 0 0x9ec 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 regMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0 0x9ed 0 0 0 regMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0 0x9ee 0 0 0 regMMEA5_ADDRNORM_MEGACONTROL_ADDR0 0 0xa11 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA5_ADDRNORM_MEGACONTROL_ADDR1 0 0xa12 1 0 0 LOG2_DIE_ADDR64K_SPACE 0 5 regMMEA5_ADDRNORMDRAM_MASKING 0 0xa13 1 0 0 ADDRHI_MASK 0 11 regMMEA5_ADDRNORMGMI_MASKING 0 0xa14 1 0 0 ADDRHI_MASK 0 11 regMMEA5_IO_RD_CLI2GRP_MAP0 0 0xa15 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_IO_RD_CLI2GRP_MAP1 0 0xa16 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_IO_WR_CLI2GRP_MAP0 0 0xa17 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 regMMEA5_IO_WR_CLI2GRP_MAP1 0 0xa18 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 regMMEA5_IO_RD_COMBINE_FLUSH 0 0xa19 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA5_IO_WR_COMBINE_FLUSH 0 0xa1a 5 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 regMMEA5_IO_GROUP_BURST 0 0xa1b 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 regMMEA5_IO_RD_PRI_AGE 0 0xa1c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_IO_WR_PRI_AGE 0 0xa1d 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 regMMEA5_IO_RD_PRI_QUEUING 0 0xa1e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_IO_WR_PRI_QUEUING 0 0xa1f 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 regMMEA5_IO_RD_PRI_FIXED 0 0xa20 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_IO_WR_PRI_FIXED 0 0xa21 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 regMMEA5_IO_RD_PRI_URGENCY 0 0xa22 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_IO_WR_PRI_URGENCY 0 0xa23 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 regMMEA5_IO_RD_PRI_URGENCY_MASKING 0 0xa24 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA5_IO_WR_PRI_URGENCY_MASKING 0 0xa25 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 regMMEA5_IO_RD_PRI_QUANT_PRI1 0 0xa26 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_IO_RD_PRI_QUANT_PRI2 0 0xa27 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_IO_RD_PRI_QUANT_PRI3 0 0xa28 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_IO_WR_PRI_QUANT_PRI1 0 0xa29 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_IO_WR_PRI_QUANT_PRI2 0 0xa2a 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_IO_WR_PRI_QUANT_PRI3 0 0xa2b 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 regMMEA5_SDP_ARB_DRAM 0 0xa2c 8 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 regMMEA5_SDP_ARB_GMI 0 0xa2d 9 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 regMMEA5_SDP_ARB_FINAL 0 0xa2e 19 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 regMMEA5_SDP_DRAM_PRIORITY 0 0xa2f 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA5_SDP_GMI_PRIORITY 0 0xa30 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA5_SDP_IO_PRIORITY 0 0xa31 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 regMMEA5_SDP_CREDITS 0 0xa32 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 regMMEA5_SDP_TAG_RESERVE0 0 0xa33 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 regMMEA5_SDP_TAG_RESERVE1 0 0xa34 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 regMMEA5_SDP_VCC_RESERVE0 0 0xa35 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA5_SDP_VCC_RESERVE1 0 0xa36 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA5_SDP_VCD_RESERVE0 0 0xa37 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 regMMEA5_SDP_VCD_RESERVE1 0 0xa38 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 regMMEA5_SDP_REQ_CNTL 0 0xa39 9 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 regMMEA5_MISC 0 0xa3a 25 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 regMMEA5_LATENCY_SAMPLING 0 0xa3b 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 regMMEA5_PERFCOUNTER_LO 0 0xa3c 1 0 0 COUNTER_LO 0 31 regMMEA5_PERFCOUNTER_HI 0 0xa3d 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regMMEA5_PERFCOUNTER0_CFG 0 0xa3e 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA5_PERFCOUNTER1_CFG 0 0xa3f 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMMEA5_PERFCOUNTER_RSLT_CNTL 0 0xa40 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMMEA5_EDC_CNT 0 0xa46 16 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 regMMEA5_EDC_CNT2 0 0xa47 16 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 regMMEA5_DSM_CNTL 0 0xa48 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 regMMEA5_DSM_CNTLA 0 0xa49 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 regMMEA5_DSM_CNTLB 0 0xa4a 0 0 0 regMMEA5_DSM_CNTL2 0 0xa4b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 regMMEA5_DSM_CNTL2A 0 0xa4c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 regMMEA5_DSM_CNTL2B 0 0xa4d 0 0 0 regMMEA5_CGTT_CLK_CTRL 0 0xa4f 12 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 regMMEA5_EDC_MODE 0 0xa50 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regMMEA5_ERR_STATUS 0 0xa51 12 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 BUSY_ON_CMPL_FATAL_ERROR 18 18 regMMEA5_MISC2 0 0xa52 8 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 regMMEA5_ADDRDEC_SELECT 0 0xa53 4 0 0 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 regMMEA5_EDC_CNT3 0 0xa54 6 0 0 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 regMMEA5_MISC_AON 0 0xa55 2 0 0 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 regMC_VM_MX_L1_TLB0_STATUS 0 0xb08 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB1_STATUS 0 0xb09 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB2_STATUS 0 0xb0a 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB3_STATUS 0 0xb0b 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB4_STATUS 0 0xb0c 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB5_STATUS 0 0xb0d 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB6_STATUS 0 0xb0e 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_TLB7_STATUS 0 0xb0f 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regMC_VM_MX_L1_PERFCOUNTER0_CFG 0 0xb20 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_MX_L1_PERFCOUNTER1_CFG 0 0xb21 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_MX_L1_PERFCOUNTER2_CFG 0 0xb22 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_MX_L1_PERFCOUNTER3_CFG 0 0xb23 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0 0xb24 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMC_VM_MX_L1_PERFCOUNTER_LO 0 0xb30 1 0 0 COUNTER_LO 0 31 regMC_VM_MX_L1_PERFCOUNTER_HI 0 0xb31 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regPCTL0_CTRL 0 0xa80 16 0 0 PG_ENABLE 0 0 ALLOW_DEEP_SLEEP_MODE 1 3 STCTRL_DAGB_IDLE_THRESHOLD 11 15 STCTRL_IGNORE_PROTECTION_FAULT 16 16 OVR_EA0_SDP_PARTACK 17 17 OVR_EA1_SDP_PARTACK 18 18 OVR_EA2_SDP_PARTACK 19 19 OVR_EA3_SDP_PARTACK 20 20 OVR_EA4_SDP_PARTACK 21 21 OVR_EA5_SDP_PARTACK 22 22 OVR_EA0_SDP_FULLACK 23 23 OVR_EA1_SDP_FULLACK 24 24 OVR_EA2_SDP_FULLACK 25 25 OVR_EA3_SDP_FULLACK 26 26 OVR_EA4_SDP_FULLACK 27 27 OVR_EA5_SDP_FULLACK 28 28 regPCTL0_MMHUB_DEEPSLEEP_IB 0 0xa81 18 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 SETCLEAR 31 31 regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0 0xa82 18 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 regPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0 0xa83 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_PG_IGNORE_DEEPSLEEP 0 0xa84 19 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 ALLIPS 18 18 regPCTL0_PG_IGNORE_DEEPSLEEP_IB 0 0xa85 18 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 ALLIPS 17 17 regPCTL0_SLICE0_CFG_DAGB_BUSY 0 0xa86 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE0_CFG_DS_ALLOW 0 0xa87 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE0_CFG_DS_ALLOW_IB 0 0xa88 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE1_CFG_DAGB_BUSY 0 0xa89 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE1_CFG_DS_ALLOW 0 0xa8a 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE1_CFG_DS_ALLOW_IB 0 0xa8b 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE2_CFG_DAGB_BUSY 0 0xa8c 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE2_CFG_DS_ALLOW 0 0xa8d 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE2_CFG_DS_ALLOW_IB 0 0xa8e 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE3_CFG_DAGB_BUSY 0 0xa8f 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE3_CFG_DS_ALLOW 0 0xa90 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE3_CFG_DS_ALLOW_IB 0 0xa91 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE4_CFG_DAGB_BUSY 0 0xa92 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE4_CFG_DS_ALLOW 0 0xa93 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE4_CFG_DS_ALLOW_IB 0 0xa94 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE5_CFG_DAGB_BUSY 0 0xa95 1 0 0 DB_LNCFG 0 31 regPCTL0_SLICE5_CFG_DS_ALLOW 0 0xa96 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_SLICE5_CFG_DS_ALLOW_IB 0 0xa97 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 regPCTL0_UTCL2_MISC 0 0xa98 6 0 0 CRITICAL_REGS_LOCK 11 11 TILE_IDLE_THRESHOLD 12 14 RENG_MEM_LS_ENABLE 15 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE0_MISC 0 0xa99 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE1_MISC 0 0xa9a 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE2_MISC 0 0xa9b 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE3_MISC 0 0xa9c 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE4_MISC 0 0xa9d 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regPCTL0_SLICE5_MISC 0 0xa9e 7 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 regATC_L2_CNTL 0 0xb40 12 0 0 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS 8 9 NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS 11 12 NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 14 14 NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 15 15 CACHE_INVALIDATE_MODE 16 18 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 19 19 FRAG_APT_INTXN_MODE 20 21 CLI_GPA_REQ_FRAG_SIZE 22 27 regATC_L2_CNTL2 0 0xb41 7 0 0 BANK_SELECT 0 5 NUM_BANKS_LOG2 6 8 L2_CACHE_UPDATE_MODE 9 10 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 11 11 L2_CACHE_SWAP_TAG_INDEX_LSBS 12 14 L2_CACHE_VMID_MODE 15 17 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 18 23 regATC_L2_CACHE_DATA0 0 0xb44 4 0 0 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 22 VIRTUAL_PAGE_ADDRESS_HIGH 23 26 regATC_L2_CACHE_DATA1 0 0xb45 1 0 0 VIRTUAL_PAGE_ADDRESS_LOW 0 31 regATC_L2_CACHE_DATA2 0 0xb46 1 0 0 PHYSICAL_PAGE_ADDRESS 0 31 regATC_L2_CACHE_DATA3 0 0xb47 1 0 0 PHYSICAL_PAGE_ADDRESS 0 31 regATC_L2_CNTL3 0 0xb48 7 0 0 L2_SMALLK_FRAGMENT_SIZE 0 5 L2_MIDK_FRAGMENT_SIZE 6 11 L2_BIGK_FRAGMENT_SIZE 12 17 DELAY_SEND_INVALIDATION_REQUEST 18 20 ATS_REQUEST_CREDIT_MINUS1 21 26 COMPCLKREQ_OFF_HYSTERESIS 27 29 REPEATER_FGCG_OFF 30 30 regATC_L2_STATUS 0 0xb49 1 0 0 BUSY 0 0 regATC_L2_STATUS2 0 0xb4a 4 0 0 UCE_MEM_ADDR 0 11 UCE_MEM_INST 12 17 UCE_SRT_CACHE 18 18 UCE 19 19 regATC_L2_MISC_CG 0 0xb4b 3 0 0 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 regATC_L2_MEM_POWER_LS 0 0xb4c 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 regATC_L2_CGTT_CLK_CTRL 0 0xb4d 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regATC_L2_CACHE_4K_DSM_INDEX 0 0xb4e 1 0 0 INDEX 0 7 regATC_L2_CACHE_32K_DSM_INDEX 0 0xb4f 1 0 0 INDEX 0 7 regATC_L2_CACHE_2M_DSM_INDEX 0 0xb50 1 0 0 INDEX 0 7 regATC_L2_CACHE_4K_DSM_CNTL 0 0xb51 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CACHE_32K_DSM_CNTL 0 0xb52 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CACHE_2M_DSM_CNTL 0 0xb53 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 regATC_L2_CNTL4 0 0xb54 2 0 0 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 0 9 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 10 19 regATC_L2_MM_GROUP_RT_CLASSES 0 0xb55 1 0 0 GROUP_RT_CLASS 0 31 regATC_L2_PERFCOUNTER0_CFG 0 0xd34 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regATC_L2_PERFCOUNTER1_CFG 0 0xd35 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regATC_L2_PERFCOUNTER_RSLT_CNTL 0 0xd36 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regATC_L2_PERFCOUNTER_LO 0 0xd30 1 0 0 COUNTER_LO 0 31 regATC_L2_PERFCOUNTER_HI 0 0xd31 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regL2TLB_TLB0_STATUS 0 0xd61 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0 0xd63 1 0 0 ADDR 0 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0 0xd64 10 0 0 ADDR 0 3 VMID 4 7 VFID 9 12 VF 13 13 GPA 14 15 RD_PERM 16 16 WR_PERM 17 17 EX_PERM 18 18 CLIENT_ID 19 27 REQ 31 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0 0xd65 1 0 0 ADDR 0 31 regUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0 0xd66 12 0 0 ADDR 0 3 PERMS 4 6 FRAGMENT_SIZE 7 12 SNOOP 13 13 SPA 14 14 IO 15 15 PTE_TMZ 16 16 NO_PTE 17 17 MTYPE 18 19 MEMLOG 20 20 NACK 21 22 ACK 30 30 regL2TLB_PERFCOUNTER0_CFG 0 0xd68 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER1_CFG 0 0xd69 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER2_CFG 0 0xd6a 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER3_CFG 0 0xd6b 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regL2TLB_PERFCOUNTER_RSLT_CNTL 0 0xd6c 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regL2TLB_PERFCOUNTER_LO 0 0xd70 1 0 0 COUNTER_LO 0 31 regL2TLB_PERFCOUNTER_HI 0 0xd71 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regVM_L2_CNTL 0 0xb80 14 0 0 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 regVM_L2_CNTL2 0 0xb81 7 0 0 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 regVM_L2_CNTL3 0 0xb82 11 0 0 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 regVM_L2_STATUS 0 0xb83 7 0 0 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 regVM_DUMMY_PAGE_FAULT_CNTL 0 0xb84 3 0 0 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 regVM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0xb85 1 0 0 DUMMY_PAGE_ADDR_LO32 0 31 regVM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0xb86 1 0 0 DUMMY_PAGE_ADDR_HI4 0 3 regVM_L2_PROTECTION_FAULT_CNTL 0 0xb87 17 0 0 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 regVM_L2_PROTECTION_FAULT_CNTL2 0 0xb88 5 0 0 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 regVM_L2_PROTECTION_FAULT_MM_CNTL3 0 0xb89 1 0 0 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 regVM_L2_PROTECTION_FAULT_MM_CNTL4 0 0xb8a 1 0 0 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 regVM_L2_PROTECTION_FAULT_STATUS 0 0xb8b 12 0 0 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 28 UCE 29 29 FED 30 30 regVM_L2_PROTECTION_FAULT_ADDR_LO32 0 0xb8c 1 0 0 LOGICAL_PAGE_ADDR_LO32 0 31 regVM_L2_PROTECTION_FAULT_ADDR_HI32 0 0xb8d 1 0 0 LOGICAL_PAGE_ADDR_HI4 0 3 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0xb8e 1 0 0 PHYSICAL_PAGE_ADDR_LO32 0 31 regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0xb8f 1 0 0 PHYSICAL_PAGE_ADDR_HI4 0 3 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0xb91 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0xb92 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0xb93 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0xb94 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0xb95 1 0 0 PHYSICAL_PAGE_OFFSET_LO32 0 31 regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0xb96 1 0 0 PHYSICAL_PAGE_OFFSET_HI4 0 3 regVM_L2_CNTL4 0 0xb97 8 0 0 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 GC_CH_FGCG_OFF 29 29 VFIFO_HEAD_OF_QUEUE 30 30 regVM_L2_MM_GROUP_RT_CLASSES 0 0xb98 32 0 0 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 regVM_L2_BANK_SELECT_RESERVED_CID 0 0xb99 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 regVM_L2_BANK_SELECT_RESERVED_CID2 0 0xb9a 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 regVM_L2_CACHE_PARITY_CNTL 0 0xb9b 9 0 0 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 regVM_L2_CGTT_CLK_CTRL 0 0xb9e 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regVM_L2_CGTT_BUSY_CTRL 0 0xb9f 2 0 0 READ_DELAY 0 3 ALWAYS_BUSY 4 4 regVML2_MEM_ECC_INDEX 0 0xba1 1 0 0 INDEX 0 7 regVML2_WALKER_MEM_ECC_INDEX 0 0xba2 1 0 0 INDEX 0 7 regUTCL2_MEM_ECC_INDEX 0 0xba3 1 0 0 INDEX 0 7 regVML2_MEM_ECC_CNTL 0 0xba4 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regVML2_WALKER_MEM_ECC_CNTL 0 0xba5 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regUTCL2_MEM_ECC_CNTL 0 0xba6 9 0 0 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 SEC_COUNT 12 13 DED_COUNT 14 15 WRITE_COUNTERS 16 16 TEST_FUE 17 17 regVML2_MEM_ECC_STATUS 0 0xba7 2 0 0 UCE 0 0 FED 1 1 regVML2_WALKER_MEM_ECC_STATUS 0 0xba8 2 0 0 UCE 0 0 FED 1 1 regUTCL2_MEM_ECC_STATUS 0 0xba9 2 0 0 UCE 0 0 FED 1 1 regUTCL2_EDC_MODE 0 0xbaa 6 0 0 FORCE_SEC_ON_DED 15 15 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 regUTCL2_EDC_CONFIG 0 0xbab 1 0 0 DIS_EDC 1 1 regMC_VM_L2_PERFCOUNTER0_CFG 0 0xd40 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER1_CFG 0 0xd41 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER2_CFG 0 0xd42 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER3_CFG 0 0xd43 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER4_CFG 0 0xd44 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER5_CFG 0 0xd45 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER6_CFG 0 0xd46 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER7_CFG 0 0xd47 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0xd48 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regMC_VM_L2_PERFCOUNTER_LO 0 0xd50 1 0 0 COUNTER_LO 0 31 regMC_VM_L2_PERFCOUNTER_HI 0 0xd51 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regVM_CONTEXT0_CNTL 0 0xbc0 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT1_CNTL 0 0xbc1 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT2_CNTL 0 0xbc2 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT3_CNTL 0 0xbc3 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT4_CNTL 0 0xbc4 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT5_CNTL 0 0xbc5 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT6_CNTL 0 0xbc6 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT7_CNTL 0 0xbc7 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT8_CNTL 0 0xbc8 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT9_CNTL 0 0xbc9 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT10_CNTL 0 0xbca 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT11_CNTL 0 0xbcb 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT12_CNTL 0 0xbcc 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT13_CNTL 0 0xbcd 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT14_CNTL 0 0xbce 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXT15_CNTL 0 0xbcf 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 regVM_CONTEXTS_DISABLE 0 0xbd0 16 0 0 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 regVM_INVALIDATE_ENG0_SEM 0 0xbd1 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG1_SEM 0 0xbd2 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG2_SEM 0 0xbd3 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG3_SEM 0 0xbd4 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG4_SEM 0 0xbd5 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG5_SEM 0 0xbd6 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG6_SEM 0 0xbd7 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG7_SEM 0 0xbd8 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG8_SEM 0 0xbd9 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG9_SEM 0 0xbda 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG10_SEM 0 0xbdb 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG11_SEM 0 0xbdc 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG12_SEM 0 0xbdd 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG13_SEM 0 0xbde 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG14_SEM 0 0xbdf 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG15_SEM 0 0xbe0 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG16_SEM 0 0xbe1 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG17_SEM 0 0xbe2 1 0 0 SEMAPHORE 0 0 regVM_INVALIDATE_ENG0_REQ 0 0xbe3 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG1_REQ 0 0xbe4 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG2_REQ 0 0xbe5 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG3_REQ 0 0xbe6 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG4_REQ 0 0xbe7 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG5_REQ 0 0xbe8 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG6_REQ 0 0xbe9 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG7_REQ 0 0xbea 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG8_REQ 0 0xbeb 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG9_REQ 0 0xbec 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG10_REQ 0 0xbed 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG11_REQ 0 0xbee 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG12_REQ 0 0xbef 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG13_REQ 0 0xbf0 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG14_REQ 0 0xbf1 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG15_REQ 0 0xbf2 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG16_REQ 0 0xbf3 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG17_REQ 0 0xbf4 9 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 LOG_REQUEST 24 24 regVM_INVALIDATE_ENG0_ACK 0 0xbf5 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG1_ACK 0 0xbf6 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG2_ACK 0 0xbf7 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG3_ACK 0 0xbf8 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG4_ACK 0 0xbf9 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG5_ACK 0 0xbfa 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG6_ACK 0 0xbfb 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG7_ACK 0 0xbfc 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG8_ACK 0 0xbfd 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG9_ACK 0 0xbfe 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG10_ACK 0 0xbff 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG11_ACK 0 0xc00 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG12_ACK 0 0xc01 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG13_ACK 0 0xc02 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG14_ACK 0 0xc03 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG15_ACK 0 0xc04 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG16_ACK 0 0xc05 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG17_ACK 0 0xc06 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0xc07 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0xc08 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0xc09 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0xc0a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0xc0b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0xc0c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0xc0d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0xc0e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0xc0f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0xc10 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0xc11 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0xc12 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0xc13 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0xc14 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0xc15 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0xc16 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0xc17 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0xc18 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0xc19 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0xc1a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0xc1b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0xc1c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0xc1d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0xc1e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0xc1f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0xc20 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0xc21 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0xc22 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0xc23 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0xc24 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0xc25 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0xc26 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0xc27 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0xc28 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0xc29 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 regVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0xc2a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0xc2b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0xc2c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0xc2d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0xc2e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0xc2f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0xc30 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0xc31 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0xc32 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0xc33 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0xc34 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0xc35 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0xc36 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0xc37 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0xc38 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0xc39 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0xc3a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0xc3b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0xc3c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0xc3d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0xc3e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0xc3f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0xc40 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0xc41 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0xc42 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0xc43 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0xc44 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0xc45 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0xc46 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0xc47 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0xc48 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0xc49 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0xc4a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0xc4b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0xc4c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0xc4d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0xc4e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0xc4f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0xc50 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0xc51 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0xc52 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0xc53 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0xc54 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0xc55 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0xc56 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0xc57 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0xc58 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0xc59 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0xc5a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0xc5b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0xc5c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0xc5d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0xc5e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0xc5f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0xc60 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0xc61 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0xc62 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0xc63 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0xc64 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0xc65 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0xc66 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0xc67 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0xc68 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0xc69 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0xc6a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0xc6b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0xc6c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0xc6d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0xc6e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0xc6f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0xc70 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0xc71 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0xc72 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0xc73 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0xc74 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0xc75 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0xc76 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0xc77 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0xc78 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0xc79 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0xc7a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0xc7b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0xc7c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0xc7d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0xc7e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0xc7f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0xc80 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0xc81 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0xc82 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0xc83 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0xc84 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0xc85 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0xc86 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0xc87 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0xc88 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0xc89 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 regVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0xc8a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 regMC_VM_FB_SIZE_OFFSET_VF0 0 0xce0 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF1 0 0xce1 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF2 0 0xce2 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF3 0 0xce3 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF4 0 0xce4 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF5 0 0xce5 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF6 0 0xce6 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF7 0 0xce7 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF8 0 0xce8 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF9 0 0xce9 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF10 0 0xcea 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF11 0 0xceb 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF12 0 0xcec 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF13 0 0xced 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF14 0 0xcee 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_FB_SIZE_OFFSET_VF15 0 0xcef 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 regMC_VM_MARC_BASE_LO_0 0 0xcf1 1 0 0 MARC_BASE_LO_0 12 31 regMC_VM_MARC_BASE_LO_1 0 0xcf2 1 0 0 MARC_BASE_LO_1 12 31 regMC_VM_MARC_BASE_LO_2 0 0xcf3 1 0 0 MARC_BASE_LO_2 12 31 regMC_VM_MARC_BASE_LO_3 0 0xcf4 1 0 0 MARC_BASE_LO_3 12 31 regMC_VM_MARC_BASE_HI_0 0 0xcf5 1 0 0 MARC_BASE_HI_0 0 19 regMC_VM_MARC_BASE_HI_1 0 0xcf6 1 0 0 MARC_BASE_HI_1 0 19 regMC_VM_MARC_BASE_HI_2 0 0xcf7 1 0 0 MARC_BASE_HI_2 0 19 regMC_VM_MARC_BASE_HI_3 0 0xcf8 1 0 0 MARC_BASE_HI_3 0 19 regMC_VM_MARC_RELOC_LO_0 0 0xcf9 3 0 0 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 regMC_VM_MARC_RELOC_LO_1 0 0xcfa 3 0 0 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 regMC_VM_MARC_RELOC_LO_2 0 0xcfb 3 0 0 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 regMC_VM_MARC_RELOC_LO_3 0 0xcfc 3 0 0 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 regMC_VM_MARC_RELOC_HI_0 0 0xcfd 1 0 0 MARC_RELOC_HI_0 0 19 regMC_VM_MARC_RELOC_HI_1 0 0xcfe 1 0 0 MARC_RELOC_HI_1 0 19 regMC_VM_MARC_RELOC_HI_2 0 0xcff 1 0 0 MARC_RELOC_HI_2 0 19 regMC_VM_MARC_RELOC_HI_3 0 0xd00 1 0 0 MARC_RELOC_HI_3 0 19 regMC_VM_MARC_LEN_LO_0 0 0xd01 1 0 0 MARC_LEN_LO_0 12 31 regMC_VM_MARC_LEN_LO_1 0 0xd02 1 0 0 MARC_LEN_LO_1 12 31 regMC_VM_MARC_LEN_LO_2 0 0xd03 1 0 0 MARC_LEN_LO_2 12 31 regMC_VM_MARC_LEN_LO_3 0 0xd04 1 0 0 MARC_LEN_LO_3 12 31 regMC_VM_MARC_LEN_HI_0 0 0xd05 1 0 0 MARC_LEN_HI_0 0 19 regMC_VM_MARC_LEN_HI_1 0 0xd06 1 0 0 MARC_LEN_HI_1 0 19 regMC_VM_MARC_LEN_HI_2 0 0xd07 1 0 0 MARC_LEN_HI_2 0 19 regMC_VM_MARC_LEN_HI_3 0 0xd08 1 0 0 MARC_LEN_HI_3 0 19 regVM_PCIE_ATS_CNTL 0 0xd0b 2 0 0 STU 16 20 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_0 0 0xd0c 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_1 0 0xd0d 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_2 0 0xd0e 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_3 0 0xd0f 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_4 0 0xd10 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_5 0 0xd11 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_6 0 0xd12 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_7 0 0xd13 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_8 0 0xd14 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_9 0 0xd15 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_10 0 0xd16 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_11 0 0xd17 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_12 0 0xd18 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_13 0 0xd19 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_14 0 0xd1a 1 0 0 ATC_ENABLE 31 31 regVM_PCIE_ATS_CNTL_VF_15 0 0xd1b 1 0 0 ATC_ENABLE 31 31 regMC_SHARED_ACTIVE_FCN_ID 0 0xd1c 2 0 0 VFID 0 3 VF 31 31 regMC_VM_XGMI_GPUIOV_ENABLE 0 0xd1d 17 0 0 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_PF 31 31 regMC_VM_FB_OFFSET 0 0xcab 1 0 0 FB_OFFSET 0 23 regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0xcac 1 0 0 PHYSICAL_PAGE_NUMBER_LSB 0 31 regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0xcad 1 0 0 PHYSICAL_PAGE_NUMBER_MSB 0 3 regMC_VM_STEERING 0 0xcae 1 0 0 DEFAULT_STEERING 0 1 regMC_SHARED_VIRT_RESET_REQ 0 0xcaf 2 0 0 VF 0 15 PF 31 31 regMC_MEM_POWER_LS 0 0xcb0 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 regMC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0xcb1 1 0 0 ADDRESS 0 23 regMC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0xcb2 1 0 0 ADDRESS 0 23 regMC_VM_APT_CNTL 0 0xcb3 4 0 0 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 CHECK_IS_LOCAL 2 2 PERMS_GRANTED 3 3 regMC_VM_LOCAL_HBM_ADDRESS_START 0 0xcb4 1 0 0 ADDRESS 0 23 regMC_VM_LOCAL_HBM_ADDRESS_END 0 0xcb5 1 0 0 ADDRESS 0 23 regMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0xcb6 1 0 0 LOCK 0 0 regUTCL2_CGTT_CLK_CTRL 0 0xcb7 6 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 regMC_VM_XGMI_LFB_CNTL 0 0xcb8 2 0 0 PF_LFB_REGION 0 3 PF_MAX_REGION 4 7 regMC_VM_XGMI_LFB_SIZE 0 0xcb9 1 0 0 PF_LFB_SIZE 0 16 regMC_VM_CACHEABLE_DRAM_CNTL 0 0xcba 1 0 0 ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE 0 0 regMC_VM_HOST_MAPPING 0 0xcbb 1 0 0 MODE 0 0 regMC_VM_FB_LOCATION_BASE 0 0xcc0 1 0 0 FB_BASE 0 23 regMC_VM_FB_LOCATION_TOP 0 0xcc1 1 0 0 FB_TOP 0 23 regMC_VM_AGP_TOP 0 0xcc2 1 0 0 AGP_TOP 0 23 regMC_VM_AGP_BOT 0 0xcc3 1 0 0 AGP_BOT 0 23 regMC_VM_AGP_BASE 0 0xcc4 1 0 0 AGP_BASE 0 23 regMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0xcc5 1 0 0 LOGICAL_ADDR 0 29 regMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0xcc6 1 0 0 LOGICAL_ADDR 0 29 regMC_VM_MX_L1_TLB_CNTL 0 0xcc7 7 0 0 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 12 ATC_EN 13 13