1163 mmDAGB0_RDCLI0 0 0x0 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI1 0 0x1 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI2 0 0x2 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI3 0 0x3 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI4 0 0x4 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI5 0 0x5 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI6 0 0x6 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI7 0 0x7 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI8 0 0x8 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI9 0 0x9 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI10 0 0xa 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI11 0 0xb 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI12 0 0xc 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI13 0 0xd 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI14 0 0xe 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI15 0 0xf 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI16 0 0x10 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI17 0 0x11 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI18 0 0x12 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI19 0 0x13 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI20 0 0x14 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI21 0 0x15 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI22 0 0x16 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI23 0 0x17 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI24 0 0x18 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI25 0 0x19 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI26 0 0x1a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI27 0 0x1b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI28 0 0x1c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI29 0 0x1d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI30 0 0x1e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RD_CNTL 0 0x1f 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_RD_GMI_CNTL 0 0x20 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_RD_ADDR_DAGB 0 0x21 5 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0 0x22 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x23 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_CGTT_CLK_CTRL 0 0x24 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0 0x25 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0 0x26 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0 0x27 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0 0x28 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0 0x29 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0 0x2a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0 0x2b 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0 0x2c 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST3 0 0x2d 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0 0x2e 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_RD_VC0_CNTL 0 0x2f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC1_CNTL 0 0x30 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC2_CNTL 0 0x31 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC3_CNTL 0 0x32 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC4_CNTL 0 0x33 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC5_CNTL 0 0x34 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC6_CNTL 0 0x35 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC7_CNTL 0 0x36 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_CNTL_MISC 0 0x37 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 HDP_CID 26 30 mmDAGB0_RD_TLB_CREDIT 0 0x38 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_RD_RDRET_CREDIT_CNTL 0 0x39 7 0 1 VC0_CREDIT 0 5 VC1_CREDIT 6 11 VC2_CREDIT 12 17 VC3_CREDIT 18 23 VC4_CREDIT 24 29 VC_MODE 30 30 FIX_EQ 31 31 mmDAGB0_RD_RDRET_CREDIT_CNTL2 0 0x3a 1 0 1 POOL_CREDIT 0 6 mmDAGB0_RDCLI_ASK_PENDING 0 0x3b 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_GO_PENDING 0 0x3c 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_GBLSEND_PENDING 0 0x3d 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_TLB_PENDING 0 0x3e 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_OARB_PENDING 0 0x3f 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_OSD_PENDING 0 0x40 1 0 1 BUSY 0 31 mmDAGB0_WRCLI0 0 0x41 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI1 0 0x42 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI2 0 0x43 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI3 0 0x44 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI4 0 0x45 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI5 0 0x46 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI6 0 0x47 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI7 0 0x48 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI8 0 0x49 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI9 0 0x4a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI10 0 0x4b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI11 0 0x4c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI12 0 0x4d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI13 0 0x4e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI14 0 0x4f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI15 0 0x50 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI16 0 0x51 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI17 0 0x52 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI18 0 0x53 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI19 0 0x54 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI20 0 0x55 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI21 0 0x56 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI22 0 0x57 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI23 0 0x58 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI24 0 0x59 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI25 0 0x5a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI26 0 0x5b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI27 0 0x5c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI28 0 0x5d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI29 0 0x5e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI30 0 0x5f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WR_CNTL 0 0x60 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_WR_GMI_CNTL 0 0x61 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_WR_ADDR_DAGB 0 0x62 5 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 JUMP_MODE 13 13 mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0 0x63 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x64 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_CGTT_CLK_CTRL 0 0x65 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0 0x66 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0 0x67 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0 0x68 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0 0x69 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0 0x6a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0 0x6b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0 0x6c 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0 0x6d 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST3 0 0x6e 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0 0x6f 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_WR_DATA_DAGB 0 0x70 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0 0x71 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0 0x72 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0 0x73 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0 0x74 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0 0x75 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0 0x76 8 0 1 CLIENT16 0 3 CLIENT17 4 7 CLIENT18 8 11 CLIENT19 12 15 CLIENT20 16 19 CLIENT21 20 23 CLIENT22 24 27 CLIENT23 28 31 mmDAGB0_WR_DATA_DAGB_MAX_BURST3 0 0x77 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0 0x78 8 0 1 CLIENT24 0 3 CLIENT25 4 7 CLIENT26 8 11 CLIENT27 12 15 CLIENT28 16 19 CLIENT29 20 23 CLIENT30 24 27 CLIENT31 28 31 mmDAGB0_WR_VC0_CNTL 0 0x79 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC1_CNTL 0 0x7a 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC2_CNTL 0 0x7b 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC3_CNTL 0 0x7c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC4_CNTL 0 0x7d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC5_CNTL 0 0x7e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC6_CNTL 0 0x7f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC7_CNTL 0 0x80 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_CNTL_MISC 0 0x81 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 HDP_CID 26 30 mmDAGB0_WR_TLB_CREDIT 0 0x82 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_WR_DATA_CREDIT 0 0x83 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB0_WR_MISC_CREDIT 0 0x84 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB0_WR_OSD_CREDIT_CNTL1 0 0x85 7 0 1 VC0_CREDIT 0 3 VC1_CREDIT 4 7 VC2_CREDIT 8 11 VC3_CREDIT 12 15 IO_CREDIT 16 19 GMI_CREDIT 20 23 POOL_CREDIT 24 29 mmDAGB0_WR_OSD_CREDIT_CNTL2 0 0x86 2 0 1 CREDIT_MARGIN 0 3 ENABLE_LEGACY 4 4 mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0 0x87 10 0 1 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 mmDAGB0_WR_DATA_FIFO_CREDIT_CNTL2 0 0x88 5 0 1 VC0_MAX_LENGTH 0 3 VC1_MAX_LENGTH 4 7 VC2_MAX_LENGTH 8 11 VC3_MAX_LENGTH 12 15 VC4_MAX_LENGTH 16 19 mmDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0 0x89 10 0 1 VC0_CREDIT 0 4 VC1_CREDIT 5 9 VC2_CREDIT 10 14 VC3_CREDIT 15 19 POOL_CREDIT 20 24 VC_MODE 25 25 FIX_EQ 26 26 FIX0 27 27 FIX1 28 28 FIX2 29 29 mmDAGB0_WRCLI_ASK_PENDING 0 0x8a 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_GO_PENDING 0 0x8b 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_GBLSEND_PENDING 0 0x8c 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_TLB_PENDING 0 0x8d 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_OARB_PENDING 0 0x8e 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_OSD_PENDING 0 0x8f 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_DBUS_ASK_PENDING 0 0x90 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_DBUS_GO_PENDING 0 0x91 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0 0x92 1 0 1 ENABLE 0 31 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0 0x93 1 0 1 ENABLE 0 31 mmDAGB0_DAGB_DLY 0 0x94 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB0_CNTL_MISC 0 0x95 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB0_CNTL_MISC2 0 0x96 15 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 ENABLE_PARITY_CHECK 11 11 RDRET_FIFO_PERF 12 12 RDRET_FIFO_CREDITS 13 18 RDRET_FIFO_DLOCK_CREDITS 19 24 mmDAGB0_FIFO_EMPTY 0 0x97 1 0 1 EMPTY 0 23 mmDAGB0_FIFO_FULL 0 0x98 1 0 1 FULL 0 22 mmDAGB0_WR_CREDITS_FULL 0 0x99 1 0 1 FULL 0 28 mmDAGB0_RD_CREDITS_FULL 0 0x9a 1 0 1 FULL 0 17 mmDAGB0_PERFCOUNTER_LO 0 0x9b 1 0 1 COUNTER_LO 0 31 mmDAGB0_PERFCOUNTER_HI 0 0x9c 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB0_PERFCOUNTER0_CFG 0 0x9d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER1_CFG 0 0x9e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER2_CFG 0 0x9f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER_RSLT_CNTL 0 0xa0 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB0_RESERVE0 0 0xa1 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE1 0 0xa2 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE2 0 0xa3 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE3 0 0xa4 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE4 0 0xa5 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE5 0 0xa6 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE6 0 0xa7 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE7 0 0xa8 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE8 0 0xa9 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE9 0 0xaa 1 0 1 RESERVE 0 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0 0x100 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0 0x101 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0 0x102 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0 0x103 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_RD_GRP2VC_MAP 0 0x104 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_WR_GRP2VC_MAP 0 0x105 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_RD_LAZY 0 0x106 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_DRAM_WR_LAZY 0 0x107 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_DRAM_RD_CAM_CNTL 0 0x108 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA0_DRAM_WR_CAM_CNTL 0 0x109 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA0_DRAM_PAGE_BURST 0 0x10a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_DRAM_RD_PRI_AGE 0 0x10b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_WR_PRI_AGE 0 0x10c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_RD_PRI_QUEUING 0 0x10d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_QUEUING 0 0x10e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_FIXED 0 0x10f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_FIXED 0 0x110 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_URGENCY 0 0x111 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_WR_PRI_URGENCY 0 0x112 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0 0x113 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0 0x114 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0 0x115 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0 0x116 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0 0x117 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0 0x118 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_ADDRNORM_BASE_ADDR0 0 0x134 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR0 0 0x135 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_BASE_ADDR1 0 0x136 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR1 0 0x137 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_OFFSET_ADDR1 0 0x138 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0 0x143 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x145 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA0_ADDRDEC_BANK_CFG 0 0x147 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA0_ADDRDEC_MISC_CFG 0 0x148 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x149 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x14a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x14b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x14c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x14d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x14e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0 0x14f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0 0x150 1 0 1 BANK_XOR 0 5 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0 0x151 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0 0x152 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0 0x153 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0 0x154 2 0 1 START 0 19 BANK_XOR 28 31 mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0 0x155 1 0 1 END 0 19 mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0 0x156 2 0 1 START 0 19 BANK_XOR 28 31 mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0 0x157 1 0 1 END 0 19 mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0 0x167 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0 0x168 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0 0x169 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0 0x16a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0 0x16b 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0 0x16c 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0 0x16d 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0 0x16e 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0 0x16f 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0 0x170 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0 0x171 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0 0x172 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0 0x173 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0 0x174 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0 0x175 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0 0x176 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0 0x177 2 0 1 BANK5 0 4 CHAN_BIT 12 15 mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0 0x178 2 0 1 BANK5 0 4 CHAN_BIT 12 15 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0 0x179 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0 0x17a 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0 0x17b 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0 0x17c 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_RM_SEL_CS01 0 0x17d 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC0_RM_SEL_CS23 0 0x17e 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC0_RM_SEL_CS1 0 0x17f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC0_RM_SEL_CS3 0 0x180 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0 0x181 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0 0x182 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0 0x183 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0 0x184 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0 0x185 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0 0x186 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0 0x187 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0 0x188 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0 0x189 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0 0x18a 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0 0x18b 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0 0x18c 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0 0x18d 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0 0x18e 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0 0x18f 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0 0x190 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0 0x191 2 0 1 BANK5 0 4 CHAN_BIT 12 15 mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0 0x192 2 0 1 BANK5 0 4 CHAN_BIT 12 15 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0 0x193 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0 0x194 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0 0x195 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0 0x196 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_RM_SEL_CS01 0 0x197 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC1_RM_SEL_CS23 0 0x198 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC1_RM_SEL_CS1 0 0x199 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRDEC1_RM_SEL_CS3 0 0x19a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 16 19 INVERT_ROW_MSBS 28 29 INVERT_ROW_MSBS_SEC 30 31 mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0 0x1b5 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ0 0 0x1b7 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ1 0 0x1b8 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ2 0 0x1b9 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ3 0 0x1ba 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ4 0 0x1bb 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDECDRAM_GECC_HARV_ADJ5 0 0x1bc 3 0 1 START 0 9 END 10 19 SUB 20 29 mmMMEA0_ADDRDEC0_ADDR_MASK_CS1 0 0x1c3 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS3 0 0x1c4 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS1 0 0x1c5 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS3 0 0x1c6 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS1 0 0x1c7 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS3 0 0x1c8 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS1 0 0x1c9 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS3 0 0x1ca 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS1 0 0x1cb 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS3 0 0x1cc 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS1 0 0x1cd 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS3 0 0x1ce 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS1 0 0x1cf 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS3 0 0x1d0 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS1 0 0x1d1 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS3 0 0x1d2 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS1 0 0x1d3 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS3 0 0x1d4 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS1 0 0x1d5 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS3 0 0x1d6 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS1 0 0x1d7 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS3 0 0x1d8 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS1 0 0x1d9 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS3 0 0x1da 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRNORMDRAM_MASKING 0 0x1db 1 0 1 ADDRHI_MASK 0 11 mmMMEA0_IO_RD_CLI2GRP_MAP0 0 0x1dd 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_RD_CLI2GRP_MAP1 0 0x1de 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP0 0 0x1df 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP1 0 0x1e0 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_RD_COMBINE_FLUSH 0 0x1e1 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 mmMMEA0_IO_WR_COMBINE_FLUSH 0 0x1e2 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 COMB_MODE 16 17 mmMMEA0_IO_GROUP_BURST 0 0x1e3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_IO_RD_PRI_AGE 0 0x1e4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_WR_PRI_AGE 0 0x1e5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_RD_PRI_QUEUING 0 0x1e6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_QUEUING 0 0x1e7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_FIXED 0 0x1e8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_FIXED 0 0x1e9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_URGENCY 0 0x1ea 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_WR_PRI_URGENCY 0 0x1eb 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0 0x1ec 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0 0x1ed 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_RD_PRI_QUANT_PRI1 0 0x1ee 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI2 0 0x1ef 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI3 0 0x1f0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI1 0 0x1f1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI2 0 0x1f2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI3 0 0x1f3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_SDP_ARB_DRAM 0 0x1f4 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA0_SDP_ARB_FINAL 0 0x1f6 19 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 DRAM_RD_THROTTLE 28 28 DRAM_WR_THROTTLE 29 29 GMI_RD_THROTTLE 30 30 GMI_WR_THROTTLE 31 31 mmMMEA0_SDP_DRAM_PRIORITY 0 0x1f7 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_IO_PRIORITY 0 0x1f9 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_CREDITS 0 0x1fa 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA0_SDP_TAG_RESERVE0 0 0x1fb 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA0_SDP_TAG_RESERVE1 0 0x1fc 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA0_SDP_VCC_RESERVE0 0 0x1fd 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCC_RESERVE1 0 0x1fe 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_VCD_RESERVE0 0 0x1ff 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCD_RESERVE1 0 0x200 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_REQ_CNTL 0 0x201 9 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 REQ_BLOCK_LEVEL_READ 6 7 REQ_BLOCK_LEVEL_WRITE 8 9 REQ_BLOCK_LEVEL_ATOMIC 10 11 mmMMEA0_MISC 0 0x202 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA0_LATENCY_SAMPLING 0 0x203 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA0_PERFCOUNTER_LO 0 0x204 1 0 1 COUNTER_LO 0 31 mmMMEA0_PERFCOUNTER_HI 0 0x205 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA0_PERFCOUNTER0_CFG 0 0x206 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER1_CFG 0 0x207 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER_RSLT_CNTL 0 0x208 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA0_EDC_CNT 0 0x20f 16 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 IOWR_DATAMEM_SEC_COUNT 20 21 IOWR_DATAMEM_DED_COUNT 22 23 DRAMRD_PAGEMEM_SED_COUNT 24 25 DRAMWR_PAGEMEM_SED_COUNT 26 27 IORD_CMDMEM_SED_COUNT 28 29 IOWR_CMDMEM_SED_COUNT 30 31 mmMMEA0_EDC_CNT2 0 0x210 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA0_DSM_CNTL 0 0x211 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA0_DSM_CNTLA 0 0x212 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA0_DSM_CNTLB 0 0x213 8 0 1 MAM_D0MEM_DSM_IRRITATOR_DATA 0 1 MAM_D0MEM_ENABLE_SINGLE_WRITE 2 2 MAM_D1MEM_DSM_IRRITATOR_DATA 3 4 MAM_D1MEM_ENABLE_SINGLE_WRITE 5 5 MAM_D2MEM_DSM_IRRITATOR_DATA 6 7 MAM_D2MEM_ENABLE_SINGLE_WRITE 8 8 MAM_D3MEM_DSM_IRRITATOR_DATA 9 10 MAM_D3MEM_ENABLE_SINGLE_WRITE 11 11 mmMMEA0_DSM_CNTL2 0 0x214 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA0_DSM_CNTL2A 0 0x215 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA0_DSM_CNTL2B 0 0x216 8 0 1 MAM_D0MEM_ENABLE_ERROR_INJECT 0 1 MAM_D0MEM_SELECT_INJECT_DELAY 2 2 MAM_D1MEM_ENABLE_ERROR_INJECT 3 4 MAM_D1MEM_SELECT_INJECT_DELAY 5 5 MAM_D2MEM_ENABLE_ERROR_INJECT 6 7 MAM_D2MEM_SELECT_INJECT_DELAY 8 8 MAM_D3MEM_ENABLE_ERROR_INJECT 9 10 MAM_D3MEM_SELECT_INJECT_DELAY 11 11 mmMMEA0_CGTT_CLK_CTRL 0 0x218 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA0_EDC_MODE 0 0x219 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA0_ERR_STATUS 0 0x21a 11 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 IGNORE_RDRSP_FED 14 14 INTERRUPT_ON_FATAL 15 15 INTERRUPT_IGNORE_CLI_FATAL 16 16 LEVEL_INTERRUPT 17 17 mmMMEA0_MISC2 0 0x21b 8 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 BLOCK_REQUESTS 14 14 REQUESTS_BLOCKED 15 15 mmMMEA0_ADDRDEC_SELECT 0 0x21c 8 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 DRAM_GECC_ENABLE 20 20 GMI_GECC_ENABLE 21 21 DRAM_SKIP_MSB 22 22 GMI_SKIP_MSB 23 23 mmMMEA0_EDC_CNT3 0 0x21d 6 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 GMIRD_PAGEMEM_DED_COUNT 8 9 GMIWR_PAGEMEM_DED_COUNT 10 11 mmMMEA0_SDP_PRIORITY_OVERRIDE 0 0x21e 16 0 1 OVERRIDE0_PRIORITY 0 3 OVERRIDE0_CLIENT_ID 4 8 OVERRIDE0_ENABLE_DRAM_RD 9 9 OVERRIDE0_ENABLE_DRAM_WR 10 10 OVERRIDE0_ENABLE_GMI_RD 11 11 OVERRIDE0_ENABLE_GMI_WR 12 12 OVERRIDE0_ENABLE_IO_RD 13 13 OVERRIDE0_ENABLE_IO_WR 14 14 OVERRIDE1_PRIORITY 16 19 OVERRIDE1_CLIENT_ID 20 24 OVERRIDE1_ENABLE_DRAM_RD 25 25 OVERRIDE1_ENABLE_DRAM_WR 26 26 OVERRIDE1_ENABLE_GMI_RD 27 27 OVERRIDE1_ENABLE_GMI_WR 28 28 OVERRIDE1_ENABLE_IO_RD 29 29 OVERRIDE1_ENABLE_IO_WR 30 30 mmMMEA0_MISC_AON 0 0x21f 2 0 1 LINKMGR_PARTACK_HYSTERESIS 0 1 LINKMGR_PARTACK_DEASSERT_MODE 2 2 mmPCTL_CTRL 0 0x380 6 0 1 PG_ENABLE 0 0 ALLOW_DEEP_SLEEP_MODE 1 3 STCTRL_DAGB_IDLE_THRESHOLD 14 18 STCTRL_IGNORE_PROTECTION_FAULT 19 19 UTCL2_LEGACY_MODE 20 20 SDP_DISCONNECT_MODE 21 21 mmPCTL_MMHUB_DEEPSLEEP_IB 0 0x381 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 SETCLEAR 31 31 mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0 0x382 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0 0x383 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_PG_IGNORE_DEEPSLEEP 0 0x384 19 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 ALLIPS 18 18 mmPCTL_PG_IGNORE_DEEPSLEEP_IB 0 0x385 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 ALLIPS 17 17 mmPCTL_SLICE0_CFG_DAGB_WRBUSY 0 0x386 1 0 1 DB_LNCFG 0 31 mmPCTL_SLICE0_CFG_DAGB_RDBUSY 0 0x387 1 0 1 DB_LNCFG 0 31 mmPCTL_SLICE0_CFG_DS_ALLOW 0 0x388 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_SLICE0_CFG_DS_ALLOW_IB 0 0x389 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_SLICE1_CFG_DAGB_WRBUSY 0 0x38a 1 0 1 DB_LNCFG 0 31 mmPCTL_SLICE1_CFG_DAGB_RDBUSY 0 0x38b 1 0 1 DB_LNCFG 0 31 mmPCTL_SLICE1_CFG_DS_ALLOW 0 0x38c 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_SLICE1_CFG_DS_ALLOW_IB 0 0x38d 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_UTCL2_MISC 0 0x38e 6 0 1 CRITICAL_REGS_LOCK 11 11 TILE_IDLE_THRESHOLD 12 14 RENG_MEM_LS_ENABLE 15 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL_SLICE0_MISC 0 0x38f 9 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 OVR_EA_SDP0_PARTACK 19 19 OVR_EA_SDP0_FULLACK 20 20 mmPCTL_SLICE1_MISC 0 0x390 9 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 OVR_EA_SDP1_PARTACK 19 19 OVR_EA_SDP1_FULLACK 20 20 mmPCTL_RENG_CTRL 0 0x391 2 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 mmPCTL_UTCL2_RENG_EXECUTE 0 0x392 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 12 RENG_EXECUTE_END_PTR 13 23 mmPCTL_SLICE0_RENG_EXECUTE 0 0x393 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL_SLICE1_RENG_EXECUTE 0 0x394 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL_UTCL2_RENG_RAM_INDEX 0 0x395 1 0 1 RENG_RAM_INDEX 0 10 mmPCTL_UTCL2_RENG_RAM_DATA 0 0x396 1 0 1 RENG_RAM_DATA 0 31 mmPCTL_SLICE0_RENG_RAM_INDEX 0 0x397 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL_SLICE0_RENG_RAM_DATA 0 0x398 1 0 1 RENG_RAM_DATA 0 31 mmPCTL_SLICE1_RENG_RAM_INDEX 0 0x399 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL_SLICE1_RENG_RAM_DATA 0 0x39a 1 0 1 RENG_RAM_DATA 0 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0 0x39b 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0 0x39c 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0 0x39d 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0 0x39e 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0 0x39f 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3a0 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3a1 2 0 1 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0 0x3a2 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0 0x3a3 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0 0x3a4 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0 0x3a5 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0 0x3a6 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3a7 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3a8 2 0 1 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0 0x3a9 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0 0x3aa 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0 0x3ab 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0 0x3ac 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0 0x3ad 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3ae 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3af 2 0 1 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmPCTL_STATUS 0 0x3b0 5 0 1 PGFSM_CMD_STATUS 0 1 MMHUB_POWER 11 11 UTCL2_RENG_RAM_STALE 12 12 SLICE0_RENG_RAM_STALE 13 13 SLICE1_RENG_RAM_STALE 14 14 mmPCTL_PERFCOUNTER_LO 0 0x3b1 1 0 1 COUNTER_LO 0 31 mmPCTL_PERFCOUNTER_HI 0 0x3b2 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmPCTL_PERFCOUNTER0_CFG 0 0x3b3 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmPCTL_PERFCOUNTER1_CFG 0 0x3b4 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmPCTL_PERFCOUNTER_RSLT_CNTL 0 0x3b5 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmPCTL_RESERVED_0 0 0x3b6 10 0 1 WORD 0 15 BYTE 16 23 BIT7 24 24 BIT6 25 25 BIT5 26 26 BIT4 27 27 BIT3 28 28 BIT2 29 29 BIT1 30 30 BIT0 31 31 mmPCTL_RESERVED_1 0 0x3b7 10 0 1 WORD 0 15 BYTE 16 23 BIT7 24 24 BIT6 25 25 BIT5 26 26 BIT4 27 27 BIT3 28 28 BIT2 29 29 BIT1 30 30 BIT0 31 31 mmPCTL_RESERVED_2 0 0x3b8 10 0 1 WORD 0 15 BYTE 16 23 BIT7 24 24 BIT6 25 25 BIT5 26 26 BIT4 27 27 BIT3 28 28 BIT2 29 29 BIT1 30 30 BIT0 31 31 mmPCTL_RESERVED_3 0 0x3b9 10 0 1 WORD 0 15 BYTE 16 23 BIT7 24 24 BIT6 25 25 BIT5 26 26 BIT4 27 27 BIT3 28 28 BIT2 29 29 BIT1 30 30 BIT0 31 31 mmMMMC_VM_MX_L1_TLB0_STATUS 0 0x588 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB1_STATUS 0 0x589 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB2_STATUS 0 0x58a 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB3_STATUS 0 0x58b 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB4_STATUS 0 0x58c 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB5_STATUS 0 0x58d 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB6_STATUS 0 0x58e 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_TLB7_STATUS 0 0x58f 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0 0x59c 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0 0x59d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0 0x59e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0 0x59f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0 0x5a0 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0 0x5a4 1 0 1 COUNTER_LO 0 31 mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0 0x5a5 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMMC_VM_MX_L1_TLS0_CNTL 0 0x5b0 6 0 1 PREFETCH_COUNT 0 3 CLEAR_PROTECTION_FAULT_STATUS_ADDR 4 4 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 5 5 IOMGR_SNOOP_SELECT 6 7 IOMGR_DEFAULT_SYSTEM 8 8 IOMGR_DEFAULT_SNOOP 9 9 mmMMMC_VM_MX_L1_TLS0_CNTL0 0 0x5b1 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL1 0 0x5b2 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL2 0 0x5b3 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL3 0 0x5b4 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL4 0 0x5b5 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL5 0 0x5b6 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL6 0 0x5b7 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL7 0 0x5b8 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL8 0 0x5b9 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL9 0 0x5ba 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL10 0 0x5bb 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL11 0 0x5bc 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL12 0 0x5bd 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL13 0 0x5be 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL14 0 0x5bf 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL15 0 0x5c0 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL16 0 0x5c1 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL17 0 0x5c2 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL18 0 0x5c3 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL19 0 0x5c4 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL20 0 0x5c5 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL21 0 0x5c6 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL22 0 0x5c7 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL23 0 0x5c8 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL24 0 0x5c9 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL25 0 0x5ca 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL26 0 0x5cb 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL27 0 0x5cc 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL28 0 0x5cd 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL29 0 0x5ce 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL30 0 0x5cf 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL31 0 0x5d0 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL32 0 0x5d1 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL33 0 0x5d2 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL34 0 0x5d3 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL35 0 0x5d4 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL36 0 0x5d5 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_CNTL37 0 0x5d6 3 0 1 REQ_STREAM_ID 0 8 EN 12 12 PREFETCH_DONE 13 13 mmMMMC_VM_MX_L1_TLS0_START_ADDR0_LO32 0 0x5d7 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR0_HI32 0 0x5d8 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR1_LO32 0 0x5d9 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR1_HI32 0 0x5da 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR2_LO32 0 0x5db 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR2_HI32 0 0x5dc 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR3_LO32 0 0x5dd 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR3_HI32 0 0x5de 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR4_LO32 0 0x5df 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR4_HI32 0 0x5e0 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR5_LO32 0 0x5e1 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR5_HI32 0 0x5e2 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR6_LO32 0 0x5e3 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR6_HI32 0 0x5e4 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR7_LO32 0 0x5e5 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR7_HI32 0 0x5e6 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR8_LO32 0 0x5e7 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR8_HI32 0 0x5e8 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR9_LO32 0 0x5e9 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR9_HI32 0 0x5ea 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR10_LO32 0 0x5eb 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR10_HI32 0 0x5ec 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR11_LO32 0 0x5ed 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR11_HI32 0 0x5ee 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR12_LO32 0 0x5ef 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR12_HI32 0 0x5f0 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR13_LO32 0 0x5f1 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR13_HI32 0 0x5f2 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR14_LO32 0 0x5f3 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR14_HI32 0 0x5f4 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR15_LO32 0 0x5f5 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR15_HI32 0 0x5f6 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR16_LO32 0 0x5f7 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR16_HI32 0 0x5f8 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR17_LO32 0 0x5f9 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR17_HI32 0 0x5fa 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR18_LO32 0 0x5fb 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR18_HI32 0 0x5fc 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR19_LO32 0 0x5fd 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR19_HI32 0 0x5fe 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR20_LO32 0 0x5ff 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR20_HI32 0 0x600 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR21_LO32 0 0x601 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR21_HI32 0 0x602 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR22_LO32 0 0x603 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR22_HI32 0 0x604 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR23_LO32 0 0x605 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR23_HI32 0 0x606 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR24_LO32 0 0x607 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR24_HI32 0 0x608 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR25_LO32 0 0x609 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR25_HI32 0 0x60a 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR26_LO32 0 0x60b 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR26_HI32 0 0x60c 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR27_LO32 0 0x60d 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR27_HI32 0 0x60e 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR28_LO32 0 0x60f 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR28_HI32 0 0x610 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR29_LO32 0 0x611 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR29_HI32 0 0x612 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR30_LO32 0 0x613 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR30_HI32 0 0x614 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR31_LO32 0 0x615 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR31_HI32 0 0x616 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR32_LO32 0 0x617 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR32_HI32 0 0x618 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR33_LO32 0 0x619 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR33_HI32 0 0x61a 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR34_LO32 0 0x61b 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR34_HI32 0 0x61c 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR35_LO32 0 0x61d 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR35_HI32 0 0x61e 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR36_LO32 0 0x61f 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR36_HI32 0 0x620 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_START_ADDR37_LO32 0 0x621 1 0 1 START_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_START_ADDR37_HI32 0 0x622 1 0 1 START_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR0_LO32 0 0x623 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR0_HI32 0 0x624 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR1_LO32 0 0x625 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR1_HI32 0 0x626 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR2_LO32 0 0x627 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR2_HI32 0 0x628 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR3_LO32 0 0x629 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR3_HI32 0 0x62a 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR4_LO32 0 0x62b 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR4_HI32 0 0x62c 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR5_LO32 0 0x62d 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR5_HI32 0 0x62e 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR6_LO32 0 0x62f 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR6_HI32 0 0x630 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR7_LO32 0 0x631 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR7_HI32 0 0x632 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR8_LO32 0 0x633 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR8_HI32 0 0x634 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR9_LO32 0 0x635 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR9_HI32 0 0x636 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR10_LO32 0 0x637 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR10_HI32 0 0x638 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR11_LO32 0 0x639 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR11_HI32 0 0x63a 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR12_LO32 0 0x63b 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR12_HI32 0 0x63c 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR13_LO32 0 0x63d 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR13_HI32 0 0x63e 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR14_LO32 0 0x63f 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR14_HI32 0 0x640 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR15_LO32 0 0x641 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR15_HI32 0 0x642 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR16_LO32 0 0x643 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR16_HI32 0 0x644 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR17_LO32 0 0x645 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR17_HI32 0 0x646 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR18_LO32 0 0x647 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR18_HI32 0 0x648 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR19_LO32 0 0x649 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR19_HI32 0 0x64a 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR20_LO32 0 0x64b 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR20_HI32 0 0x64c 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR21_LO32 0 0x64d 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR21_HI32 0 0x64e 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR22_LO32 0 0x64f 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR22_HI32 0 0x650 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR23_LO32 0 0x651 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR23_HI32 0 0x652 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR24_LO32 0 0x653 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR24_HI32 0 0x654 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR25_LO32 0 0x655 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR25_HI32 0 0x656 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR26_LO32 0 0x657 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR26_HI32 0 0x658 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR27_LO32 0 0x659 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR27_HI32 0 0x65a 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR28_LO32 0 0x65b 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR28_HI32 0 0x65c 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR29_LO32 0 0x65d 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR29_HI32 0 0x65e 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR30_LO32 0 0x65f 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR30_HI32 0 0x660 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR31_LO32 0 0x661 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR31_HI32 0 0x662 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR32_LO32 0 0x663 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR32_HI32 0 0x664 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR33_LO32 0 0x665 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR33_HI32 0 0x666 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR34_LO32 0 0x667 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR34_HI32 0 0x668 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR35_LO32 0 0x669 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR35_HI32 0 0x66a 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR36_LO32 0 0x66b 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR36_HI32 0 0x66c 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_END_ADDR37_LO32 0 0x66d 1 0 1 END_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_END_ADDR37_HI32 0 0x66e 1 0 1 END_ADDR_HI4 0 3 mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32 0 0x66f 1 0 1 INVALIDATE_STREAM_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32 0 0x670 1 0 1 INVALIDATE_STREAM_HI6 0 5 mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32 0 0x671 1 0 1 INVALIDATE_REQUEST_PENDING_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32 0 0x672 1 0 1 INVALIDATE_REQUEST_PENDING_HI6 0 5 mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0 0x673 5 0 1 PROTECTIONS 0 7 MEMORY_CLIENT_ID 12 20 MEMORY_CLIENT_RW 24 24 VMID 25 28 ATOMIC 29 29 mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0 0x674 1 0 1 LOGICAL_PAGE_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0 0x675 1 0 1 LOGICAL_PAGE_ADDR_HI4 0 3 mmMMVM_L2_SAW_CNTL 0 0x676 15 0 1 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_CACHE_4K_SWAP_TAG_INDEX_LSBS 26 27 L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS 28 30 mmMMVM_L2_SAW_CNTL2 0 0x677 7 0 1 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_CACHE_BIGK_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmMMVM_L2_SAW_CNTL3 0 0x678 11 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmMMVM_L2_SAW_CNTL4 0 0x679 14 0 1 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED 7 7 VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP 8 8 VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL 9 9 VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED 10 10 VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP 11 11 VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL 12 12 VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED 13 13 VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP 14 14 VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL 15 15 VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED 16 16 VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP 17 17 L2_CACHE_4K_LRU_ADDR_MATCHING 18 18 mmMMVM_L2_SAW_CONTEXT0_CNTL 0 0x67a 24 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 3 3 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 6 6 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 PDE0_PROTECTION_FAULT_ENABLE_SAVE 11 11 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 12 12 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 13 13 VALID_PROTECTION_FAULT_ENABLE_SAVE 14 14 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 READ_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_SAVE 17 17 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 18 18 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 19 19 WRITE_PROTECTION_FAULT_ENABLE_SAVE 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 EXECUTE_PROTECTION_FAULT_ENABLE_SAVE 23 23 PAGE_TABLE_BLOCK_SIZE 24 27 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 28 28 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 29 29 mmMMVM_L2_SAW_CONTEXT0_CNTL2 0 0x67b 5 0 1 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT 1 1 ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT 2 2 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 3 3 WAIT_FOR_IDLE_WHEN_INVALIDATE 4 4 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x67c 1 0 1 PHYSICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x67d 1 0 1 PHYSICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x67e 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x67f 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x680 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x681 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_L2_SAW_CONTEXTS_DISABLE 0 0x682 16 0 1 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmMMVM_L2_SAW_PIPES_BUSY_LO32 0 0x683 1 0 1 PIPES_BUSY_LO32 0 31 mmMMVM_L2_SAW_PIPES_BUSY_HI32 0 0x684 1 0 1 PIPES_BUSY_HI32 0 31 mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS 0 0x685 3 0 1 MORE_FAULTS 0 0 ABORT_STATUS 1 2 STREAM_ID 3 8 mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32 0 0x686 1 0 1 LOGICAL_PAGE_ADDR_LO32 0 31 mmMMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32 0 0x687 1 0 1 LOGICAL_PAGE_ADDR_HI4 0 3 mmMM_ATC_L2_CNTL 0 0x6c0 12 0 1 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS 8 9 NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS 11 12 NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 14 14 NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 15 15 CACHE_INVALIDATE_MODE 16 18 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 19 19 FRAG_APT_INTXN_MODE 20 21 CLI_GPA_REQ_FRAG_SIZE 22 27 mmMM_ATC_L2_CNTL2 0 0x6c1 6 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 mmMM_ATC_L2_CACHE_DATA0 0 0x6c4 4 0 1 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 23 VIRTUAL_PAGE_ADDRESS_HIGH 24 27 mmMM_ATC_L2_CACHE_DATA1 0 0x6c5 1 0 1 VIRTUAL_PAGE_ADDRESS_LOW 0 31 mmMM_ATC_L2_CACHE_DATA2 0 0x6c6 1 0 1 PHYSICAL_PAGE_ADDRESS 0 31 mmMM_ATC_L2_CNTL3 0 0x6c7 6 0 1 L2_SMALLK_CACHE_FRAGMENT_SIZE 0 5 L2_MIDK_CACHE_FRAGMENT_SIZE 6 11 L2_BIGK_CACHE_FRAGMENT_SIZE 12 17 DELAY_SEND_INVALIDATION_REQUEST 18 20 ATS_REQUEST_CREDIT_MINUS1 21 26 COMPCLKREQ_OFF_HYSTERESIS 27 29 mmMM_ATC_L2_CNTL4 0 0x6c8 3 0 1 L2_RT_SMALLK_CACHE_FRAGMENT_SIZE 0 5 L2_RT_MIDK_CACHE_FRAGMENT_SIZE 6 11 L2_RT_BIGK_CACHE_FRAGMENT_SIZE 12 17 mmMM_ATC_L2_CNTL5 0 0x6c9 2 0 1 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 0 9 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 10 19 mmMM_ATC_L2_MM_GROUP_RT_CLASSES 0 0x6ca 1 0 1 GROUP_RT_CLASS 0 31 mmMM_ATC_L2_STATUS 0 0x6cb 2 0 1 BUSY 0 0 PARITY_ERROR_INFO 1 29 mmMM_ATC_L2_STATUS2 0 0x6cc 2 0 1 IFIFO_NON_FATAL_PARITY_ERROR_INFO 0 7 IFIFO_FATAL_PARITY_ERROR_INFO 8 15 mmMM_ATC_L2_MISC_CG 0 0x6cd 3 0 1 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmMM_ATC_L2_MEM_POWER_LS 0 0x6ce 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmMM_ATC_L2_CGTT_CLK_CTRL 0 0x6cf 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmMM_ATC_L2_SDPPORT_CTRL 0 0x6d2 10 0 1 SDPVDCI_RDRSPCKEN 0 0 SDPVDCI_RDRSPCKENRCV 1 1 SDPVDCI_RDRSPDATACKEN 2 2 SDPVDCI_RDRSPDATACKENRCV 3 3 SDPVDCI_WRRSPCKEN 4 4 SDPVDCI_WRRSPCKENRCV 5 5 SDPVDCI_REQCKEN 6 6 SDPVDCI_REQCKENRCV 7 7 SDPVDCI_ORIGDATACKEN 8 8 SDPVDCI_ORIGDATACKENRCV 9 9 mmMMVM_L2_CNTL 0 0x700 14 0 1 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 mmMMVM_L2_CNTL2 0 0x701 7 0 1 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmMMVM_L2_CNTL3 0 0x702 11 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmMMVM_L2_STATUS 0 0x703 7 0 1 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 mmMMVM_DUMMY_PAGE_FAULT_CNTL 0 0x704 3 0 1 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x705 1 0 1 DUMMY_PAGE_ADDR_LO32 0 31 mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x706 1 0 1 DUMMY_PAGE_ADDR_HI4 0 3 mmMMVM_INVALIDATE_CNTL 0 0x707 2 0 1 PRI_REG_ALTERNATING 0 7 MAX_REG_OUTSTANDING 8 15 mmMMVM_L2_PROTECTION_FAULT_CNTL 0 0x708 17 0 1 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 mmMMVM_L2_PROTECTION_FAULT_CNTL2 0 0x709 5 0 1 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x70a 1 0 1 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x70b 1 0 1 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmMMVM_L2_PROTECTION_FAULT_STATUS 0 0x70c 10 0 1 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 29 mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x70d 1 0 1 LOGICAL_PAGE_ADDR_LO32 0 31 mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x70e 1 0 1 LOGICAL_PAGE_ADDR_HI4 0 3 mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x70f 1 0 1 PHYSICAL_PAGE_ADDR_LO32 0 31 mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x710 1 0 1 PHYSICAL_PAGE_ADDR_HI4 0 3 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x712 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x713 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x714 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x715 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x716 1 0 1 PHYSICAL_PAGE_OFFSET_LO32 0 31 mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x717 1 0 1 PHYSICAL_PAGE_OFFSET_HI4 0 3 mmMMVM_L2_CNTL4 0 0x718 7 0 1 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 GC_CH_FGCG_OFF 29 29 mmMMVM_L2_MM_GROUP_RT_CLASSES 0 0x719 32 0 1 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 mmMMVM_L2_BANK_SELECT_RESERVED_CID 0 0x71a 6 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 RESERVED_CACHE_FRAGMENT_SIZE 26 30 mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0 0x71b 6 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 RESERVED_CACHE_FRAGMENT_SIZE 26 30 mmMMVM_L2_CACHE_PARITY_CNTL 0 0x71c 9 0 1 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 mmMMVM_L2_IH_LOG_CNTL 0 0x71d 4 0 1 ENABLE_LOGGING 0 0 USE_L_BIT 1 1 REGISTER_ADDRESS 2 19 LOG_ALL_TRANSLATIONS 20 20 mmMMVM_L2_IH_LOG_BUSY 0 0x71e 2 0 1 PER_VMID_TRANSLATION_BUSY 0 15 PER_VMID_INVALIDATION_BUSY 16 31 mmMMVM_L2_CGTT_CLK_CTRL 0 0x71f 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmMMVM_L2_CNTL5 0 0x720 2 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 WALKER_PRIORITY_CLIENT_ID 5 13 mmMMVM_L2_GCR_CNTL 0 0x721 2 0 1 GCR_ENABLE 0 0 GCR_CLIENT_ID 1 9 mmMMVM_L2_CGTT_BUSY_CTRL 0 0x722 2 0 1 READ_DELAY 0 3 ALWAYS_BUSY 4 4 mmMMVM_L2_PTE_CACHE_DUMP_CNTL 0 0x723 6 0 1 ENABLE 0 0 READY 1 1 BANK 4 7 CACHE 8 11 ASSOC 12 15 INDEX 16 31 mmMMVM_L2_PTE_CACHE_DUMP_READ 0 0x724 1 0 1 DATA 0 31 mmMMVM_CONTEXT0_CNTL 0 0x740 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT1_CNTL 0 0x741 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT2_CNTL 0 0x742 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT3_CNTL 0 0x743 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT4_CNTL 0 0x744 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT5_CNTL 0 0x745 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT6_CNTL 0 0x746 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT7_CNTL 0 0x747 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT8_CNTL 0 0x748 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT9_CNTL 0 0x749 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT10_CNTL 0 0x74a 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT11_CNTL 0 0x74b 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT12_CNTL 0 0x74c 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT13_CNTL 0 0x74d 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT14_CNTL 0 0x74e 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXT15_CNTL 0 0x74f 21 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT 23 23 SECURE_PROTECTION_FAULT_ENABLE_DEFAULT 24 24 mmMMVM_CONTEXTS_DISABLE 0 0x750 16 0 1 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x751 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x752 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x753 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x754 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x755 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x756 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x757 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x758 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x759 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75a 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75b 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75c 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75d 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75e 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x75f 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x760 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0 0x761 3 0 1 L2_CACHE_SMALLK_FRAGMENT_SIZE 0 4 L2_CACHE_BIGK_FRAGMENT_SIZE 5 9 BANK_SELECT 10 15 mmMMMC_VM_L2_PERFCOUNTER0_CFG 0 0x824 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER1_CFG 0 0x825 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER2_CFG 0 0x826 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER3_CFG 0 0x827 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER4_CFG 0 0x828 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER5_CFG 0 0x829 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER6_CFG 0 0x82a 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER7_CFG 0 0x82b 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x82c 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMUTCL2_PERFCOUNTER0_CFG 0 0x82d 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMUTCL2_PERFCOUNTER1_CFG 0 0x82e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMUTCL2_PERFCOUNTER2_CFG 0 0x82f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMUTCL2_PERFCOUNTER3_CFG 0 0x830 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMUTCL2_PERFCOUNTER_RSLT_CNTL 0 0x831 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMMC_VM_L2_PERFCOUNTER_LO 0 0x838 1 0 1 COUNTER_LO 0 31 mmMMMC_VM_L2_PERFCOUNTER_HI 0 0x839 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMUTCL2_PERFCOUNTER_LO 0 0x83a 1 0 1 COUNTER_LO 0 31 mmMMUTCL2_PERFCOUNTER_HI 0 0x83b 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF0 0 0x84c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF1 0 0x84d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF2 0 0x84e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF3 0 0x84f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF4 0 0x850 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF5 0 0x851 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF6 0 0x852 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF7 0 0x853 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF8 0 0x854 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF9 0 0x855 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF10 0 0x856 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF11 0 0x857 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF12 0 0x858 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF13 0 0x859 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF14 0 0x85a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF15 0 0x85b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF16 0 0x85c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF17 0 0x85d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF18 0 0x85e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF19 0 0x85f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF20 0 0x860 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF21 0 0x861 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF22 0 0x862 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF23 0 0x863 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF24 0 0x864 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF25 0 0x865 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF26 0 0x866 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF27 0 0x867 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF28 0 0x868 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF29 0 0x869 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF30 0 0x86a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMMC_VM_FB_SIZE_OFFSET_VF31 0 0x86b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMMVM_IOMMU_MMIO_CNTRL_1 0 0x86c 1 0 1 MARC_EN 8 8 mmMMMC_VM_MARC_BASE_LO_0 0 0x86d 1 0 1 MARC_BASE_LO_0 12 31 mmMMMC_VM_MARC_BASE_LO_1 0 0x86e 1 0 1 MARC_BASE_LO_1 12 31 mmMMMC_VM_MARC_BASE_LO_2 0 0x86f 1 0 1 MARC_BASE_LO_2 12 31 mmMMMC_VM_MARC_BASE_LO_3 0 0x870 1 0 1 MARC_BASE_LO_3 12 31 mmMMMC_VM_MARC_BASE_HI_0 0 0x871 1 0 1 MARC_BASE_HI_0 0 19 mmMMMC_VM_MARC_BASE_HI_1 0 0x872 1 0 1 MARC_BASE_HI_1 0 19 mmMMMC_VM_MARC_BASE_HI_2 0 0x873 1 0 1 MARC_BASE_HI_2 0 19 mmMMMC_VM_MARC_BASE_HI_3 0 0x874 1 0 1 MARC_BASE_HI_3 0 19 mmMMMC_VM_MARC_RELOC_LO_0 0 0x875 3 0 1 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmMMMC_VM_MARC_RELOC_LO_1 0 0x876 3 0 1 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmMMMC_VM_MARC_RELOC_LO_2 0 0x877 3 0 1 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmMMMC_VM_MARC_RELOC_LO_3 0 0x878 3 0 1 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmMMMC_VM_MARC_RELOC_HI_0 0 0x879 1 0 1 MARC_RELOC_HI_0 0 19 mmMMMC_VM_MARC_RELOC_HI_1 0 0x87a 1 0 1 MARC_RELOC_HI_1 0 19 mmMMMC_VM_MARC_RELOC_HI_2 0 0x87b 1 0 1 MARC_RELOC_HI_2 0 19 mmMMMC_VM_MARC_RELOC_HI_3 0 0x87c 1 0 1 MARC_RELOC_HI_3 0 19 mmMMMC_VM_MARC_LEN_LO_0 0 0x87d 1 0 1 MARC_LEN_LO_0 12 31 mmMMMC_VM_MARC_LEN_LO_1 0 0x87e 1 0 1 MARC_LEN_LO_1 12 31 mmMMMC_VM_MARC_LEN_LO_2 0 0x87f 1 0 1 MARC_LEN_LO_2 12 31 mmMMMC_VM_MARC_LEN_LO_3 0 0x880 1 0 1 MARC_LEN_LO_3 12 31 mmMMMC_VM_MARC_LEN_HI_0 0 0x881 1 0 1 MARC_LEN_HI_0 0 19 mmMMMC_VM_MARC_LEN_HI_1 0 0x882 1 0 1 MARC_LEN_HI_1 0 19 mmMMMC_VM_MARC_LEN_HI_2 0 0x883 1 0 1 MARC_LEN_HI_2 0 19 mmMMMC_VM_MARC_LEN_HI_3 0 0x884 1 0 1 MARC_LEN_HI_3 0 19 mmMMVM_IOMMU_CONTROL_REGISTER 0 0x885 1 0 1 IOMMUEN 0 0 mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0 0x886 1 0 1 PERFOPTEN 13 13 mmMMVM_PCIE_ATS_CNTL 0 0x887 2 0 1 STU 16 20 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_0 0 0x888 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_1 0 0x889 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_2 0 0x88a 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_3 0 0x88b 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_4 0 0x88c 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_5 0 0x88d 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_6 0 0x88e 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_7 0 0x88f 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_8 0 0x890 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_9 0 0x891 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_10 0 0x892 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_11 0 0x893 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_12 0 0x894 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_13 0 0x895 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_14 0 0x896 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_15 0 0x897 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_16 0 0x898 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_17 0 0x899 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_18 0 0x89a 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_19 0 0x89b 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_20 0 0x89c 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_21 0 0x89d 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_22 0 0x89e 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_23 0 0x89f 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_24 0 0x8a0 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_25 0 0x8a1 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_26 0 0x8a2 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_27 0 0x8a3 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_28 0 0x8a4 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_29 0 0x8a5 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_30 0 0x8a6 1 0 1 ATC_ENABLE 31 31 mmMMVM_PCIE_ATS_CNTL_VF_31 0 0x8a7 1 0 1 ATC_ENABLE 31 31 mmMMMC_VM_NB_MMIOBASE 0 0x8d0 1 0 1 MMIOBASE 0 31 mmMMMC_VM_NB_MMIOLIMIT 0 0x8d1 1 0 1 MMIOLIMIT 0 31 mmMMMC_VM_NB_PCI_CTRL 0 0x8d2 1 0 1 MMIOENABLE 23 23 mmMMMC_VM_NB_PCI_ARB 0 0x8d3 1 0 1 VGA_HOLE 3 3 mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0 0x8d4 1 0 1 TOP_OF_DRAM 23 31 mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0 0x8d5 2 0 1 ENABLE 0 0 LOWER_TOM2 23 31 mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0 0x8d6 1 0 1 UPPER_TOM2 0 11 mmMMMC_VM_FB_OFFSET 0 0x8d7 1 0 1 FB_OFFSET 0 23 mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x8d8 1 0 1 PHYSICAL_PAGE_NUMBER_LSB 0 31 mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x8d9 1 0 1 PHYSICAL_PAGE_NUMBER_MSB 0 3 mmMMMC_VM_STEERING 0 0x8da 1 0 1 DEFAULT_STEERING 0 1 mmMMMC_SHARED_VIRT_RESET_REQ 0 0x8db 2 0 1 VF 0 30 PF 31 31 mmMMMC_MEM_POWER_LS 0 0x8dc 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0x8dd 1 0 1 ADDRESS 0 19 mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0x8de 1 0 1 ADDRESS 0 19 mmMMMC_VM_APT_CNTL 0 0x8df 3 0 1 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 FRAG_APT_INTXN_MODE 2 3 mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x8e0 1 0 1 LOCK 0 0 mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0 0x8e1 1 0 1 ADDRESS 0 19 mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0 0x8e2 1 0 1 ADDRESS 0 19 mmMMUTCL2_CGTT_CLK_CTRL 0 0x8e3 6 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmMMMC_SHARED_ACTIVE_FCN_ID 0 0x8e4 2 0 1 VFID 0 4 VF 31 31 mmMMMC_SHARED_VIRT_RESET_REQ2 0 0x8e5 1 0 1 VF 0 0 mmMMUTCL2_CGTT_BUSY_CTRL 0 0x8e6 2 0 1 READ_DELAY 0 3 ALWAYS_BUSY 4 4 mmMMUTCL2_HARVEST_BYPASS_GROUPS 0 0x8e7 1 0 1 BYPASS_GROUPS 0 31 mmMMMC_VM_FB_LOCATION_BASE 0 0x8ec 1 0 1 FB_BASE 0 23 mmMMMC_VM_FB_LOCATION_TOP 0 0x8ed 1 0 1 FB_TOP 0 23 mmMMMC_VM_AGP_TOP 0 0x8ee 1 0 1 AGP_TOP 0 23 mmMMMC_VM_AGP_BOT 0 0x8ef 1 0 1 AGP_BOT 0 23 mmMMMC_VM_AGP_BASE 0 0x8f0 1 0 1 AGP_BASE 0 23 mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x8f1 1 0 1 LOGICAL_ADDR 0 29 mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x8f2 1 0 1 LOGICAL_ADDR 0 29 mmMMMC_VM_MX_L1_TLB_CNTL 0 0x8f3 6 0 1 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 13 mmMM_ATC_L2_PERFCOUNTER_LO 0 0x900 1 0 1 COUNTER_LO 0 31 mmMM_ATC_L2_PERFCOUNTER_HI 0 0x901 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMM_ATC_L2_PERFCOUNTER0_CFG 0 0x908 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMM_ATC_L2_PERFCOUNTER1_CFG 0 0x909 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0 0x90a 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x940 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x941 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x942 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x943 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x944 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x945 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE0 0 0x946 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT0_PAGE_TABLE_RESERVE1 0 0x947 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x948 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x949 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x94a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x94b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x94c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x94d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE0 0 0x94e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT1_PAGE_TABLE_RESERVE1 0 0x94f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x950 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x951 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x952 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x953 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x954 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x955 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE0 0 0x956 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT2_PAGE_TABLE_RESERVE1 0 0x957 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x958 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x959 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x95a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x95b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x95c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x95d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE0 0 0x95e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT3_PAGE_TABLE_RESERVE1 0 0x95f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x960 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x961 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x962 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x963 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x964 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x965 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE0 0 0x966 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT4_PAGE_TABLE_RESERVE1 0 0x967 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x968 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x969 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x96a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x96b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x96c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x96d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE0 0 0x96e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT5_PAGE_TABLE_RESERVE1 0 0x96f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x970 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x971 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x972 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x973 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x974 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x975 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE0 0 0x976 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT6_PAGE_TABLE_RESERVE1 0 0x977 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x978 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x979 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x97a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x97b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x97c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x97d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE0 0 0x97e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT7_PAGE_TABLE_RESERVE1 0 0x97f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x980 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x981 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x982 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x983 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x984 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x985 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE0 0 0x986 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT8_PAGE_TABLE_RESERVE1 0 0x987 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x988 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x989 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x98a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x98b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x98c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x98d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE0 0 0x98e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT9_PAGE_TABLE_RESERVE1 0 0x98f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x990 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x991 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x992 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x993 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x994 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x995 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE0 0 0x996 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT10_PAGE_TABLE_RESERVE1 0 0x997 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x998 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x999 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x99a 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x99b 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x99c 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x99d 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE0 0 0x99e 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT11_PAGE_TABLE_RESERVE1 0 0x99f 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x9a0 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x9a1 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x9a2 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x9a3 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x9a4 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x9a5 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE0 0 0x9a6 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT12_PAGE_TABLE_RESERVE1 0 0x9a7 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x9a8 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x9a9 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x9aa 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x9ab 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x9ac 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x9ad 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE0 0 0x9ae 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT13_PAGE_TABLE_RESERVE1 0 0x9af 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x9b0 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x9b1 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x9b2 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x9b3 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x9b4 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x9b5 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE0 0 0x9b6 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT14_PAGE_TABLE_RESERVE1 0 0x9b7 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x9b8 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x9b9 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x9ba 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x9bb 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x9bc 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x9bd 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE0 0 0x9be 1 0 1 DUMMY 0 31 mmMMVM_CONTEXT15_PAGE_TABLE_RESERVE1 0 0x9bf 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG0_SEM 0 0xa00 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG0_REQ 0 0xa01 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG0_ACK 0 0xa02 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0xa03 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0xa04 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG0_RESERVE0 0 0xa05 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG0_RESERVE1 0 0xa06 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG0_RESERVE2 0 0xa07 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG1_SEM 0 0xa08 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG1_REQ 0 0xa09 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG1_ACK 0 0xa0a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0xa0b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0xa0c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG1_RESERVE0 0 0xa0d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG1_RESERVE1 0 0xa0e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG1_RESERVE2 0 0xa0f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG2_SEM 0 0xa10 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG2_REQ 0 0xa11 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG2_ACK 0 0xa12 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0xa13 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0xa14 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG2_RESERVE0 0 0xa15 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG2_RESERVE1 0 0xa16 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG2_RESERVE2 0 0xa17 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG3_SEM 0 0xa18 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG3_REQ 0 0xa19 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG3_ACK 0 0xa1a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0xa1b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0xa1c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG3_RESERVE0 0 0xa1d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG3_RESERVE1 0 0xa1e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG3_RESERVE2 0 0xa1f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG4_SEM 0 0xa20 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG4_REQ 0 0xa21 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG4_ACK 0 0xa22 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0xa23 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0xa24 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG4_RESERVE0 0 0xa25 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG4_RESERVE1 0 0xa26 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG4_RESERVE2 0 0xa27 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG5_SEM 0 0xa28 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG5_REQ 0 0xa29 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG5_ACK 0 0xa2a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0xa2b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0xa2c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG5_RESERVE0 0 0xa2d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG5_RESERVE1 0 0xa2e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG5_RESERVE2 0 0xa2f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG6_SEM 0 0xa30 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG6_REQ 0 0xa31 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG6_ACK 0 0xa32 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0xa33 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0xa34 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG6_RESERVE0 0 0xa35 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG6_RESERVE1 0 0xa36 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG6_RESERVE2 0 0xa37 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG7_SEM 0 0xa38 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG7_REQ 0 0xa39 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG7_ACK 0 0xa3a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0xa3b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0xa3c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG7_RESERVE0 0 0xa3d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG7_RESERVE1 0 0xa3e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG7_RESERVE2 0 0xa3f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG8_SEM 0 0xa40 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG8_REQ 0 0xa41 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG8_ACK 0 0xa42 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0xa43 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0xa44 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG8_RESERVE0 0 0xa45 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG8_RESERVE1 0 0xa46 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG8_RESERVE2 0 0xa47 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG9_SEM 0 0xa48 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG9_REQ 0 0xa49 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG9_ACK 0 0xa4a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0xa4b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0xa4c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG9_RESERVE0 0 0xa4d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG9_RESERVE1 0 0xa4e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG9_RESERVE2 0 0xa4f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG10_SEM 0 0xa50 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG10_REQ 0 0xa51 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG10_ACK 0 0xa52 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0xa53 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0xa54 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG10_RESERVE0 0 0xa55 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG10_RESERVE1 0 0xa56 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG10_RESERVE2 0 0xa57 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG11_SEM 0 0xa58 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG11_REQ 0 0xa59 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG11_ACK 0 0xa5a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0xa5b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0xa5c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG11_RESERVE0 0 0xa5d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG11_RESERVE1 0 0xa5e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG11_RESERVE2 0 0xa5f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG12_SEM 0 0xa60 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG12_REQ 0 0xa61 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG12_ACK 0 0xa62 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0xa63 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0xa64 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG12_RESERVE0 0 0xa65 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG12_RESERVE1 0 0xa66 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG12_RESERVE2 0 0xa67 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG13_SEM 0 0xa68 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG13_REQ 0 0xa69 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG13_ACK 0 0xa6a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0xa6b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0xa6c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG13_RESERVE0 0 0xa6d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG13_RESERVE1 0 0xa6e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG13_RESERVE2 0 0xa6f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG14_SEM 0 0xa70 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG14_REQ 0 0xa71 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG14_ACK 0 0xa72 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0xa73 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0xa74 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG14_RESERVE0 0 0xa75 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG14_RESERVE1 0 0xa76 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG14_RESERVE2 0 0xa77 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG15_SEM 0 0xa78 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG15_REQ 0 0xa79 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG15_ACK 0 0xa7a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0xa7b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0xa7c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG15_RESERVE0 0 0xa7d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG15_RESERVE1 0 0xa7e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG15_RESERVE2 0 0xa7f 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG16_SEM 0 0xa80 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG16_REQ 0 0xa81 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG16_ACK 0 0xa82 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0xa83 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0xa84 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG16_RESERVE0 0 0xa85 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG16_RESERVE1 0 0xa86 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG16_RESERVE2 0 0xa87 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG17_SEM 0 0xa88 1 0 1 SEMAPHORE 0 0 mmMMVM_INVALIDATE_ENG17_REQ 0 0xa89 10 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 18 INVALIDATE_L2_PTES 19 19 INVALIDATE_L2_PDE0 20 20 INVALIDATE_L2_PDE1 21 21 INVALIDATE_L2_PDE2 22 22 INVALIDATE_L1_PTES 23 23 CLEAR_PROTECTION_FAULT_STATUS_ADDR 24 24 LOG_REQUEST 25 25 INVALIDATE_4K_PAGES_ONLY 26 26 mmMMVM_INVALIDATE_ENG17_ACK 0 0xa8a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0xa8b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0xa8c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmMMVM_INVALIDATE_ENG17_RESERVE0 0 0xa8d 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG17_RESERVE1 0 0xa8e 1 0 1 DUMMY 0 31 mmMMVM_INVALIDATE_ENG17_RESERVE2 0 0xa8f 1 0 1 DUMMY 0 31 mmMML2TLB_TLB0_STATUS 0 0xaa5 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMML2TLB_PERFCOUNTER0_CFG 0 0xac0 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMML2TLB_PERFCOUNTER1_CFG 0 0xac1 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMML2TLB_PERFCOUNTER2_CFG 0 0xac2 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMML2TLB_PERFCOUNTER3_CFG 0 0xac3 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMML2TLB_PERFCOUNTER_RSLT_CNTL 0 0xac4 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMML2TLB_PERFCOUNTER_LO 0 0xac8 1 0 1 COUNTER_LO 0 31 mmMML2TLB_PERFCOUNTER_HI 0 0xac9 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31