951 mmDAGB0_RDCLI0 0 0x0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI1 0 0x1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI2 0 0x2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI3 0 0x3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI4 0 0x4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI5 0 0x5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI6 0 0x6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI7 0 0x7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI8 0 0x8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI9 0 0x9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI10 0 0xa 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI11 0 0xb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI12 0 0xc 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI13 0 0xd 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI14 0 0xe 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI15 0 0xf 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RD_CNTL 0 0x10 7 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_RD_GMI_CNTL 0 0x11 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_RD_ADDR_DAGB 0 0x12 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0 0x13 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x14 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_CGTT_CLK_CTRL 0 0x15 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0 0x16 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0 0x17 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0 0x18 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0 0x19 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0 0x1a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0 0x1b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_VC0_CNTL 0 0x1c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC1_CNTL 0 0x1d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC2_CNTL 0 0x1e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC3_CNTL 0 0x1f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC4_CNTL 0 0x20 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC5_CNTL 0 0x21 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC6_CNTL 0 0x22 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC7_CNTL 0 0x23 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_CNTL_MISC 0 0x24 6 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 mmDAGB0_RD_TLB_CREDIT 0 0x25 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_RDCLI_ASK_PENDING 0 0x26 1 0 0 BUSY 0 31 mmDAGB0_RDCLI_GO_PENDING 0 0x27 1 0 0 BUSY 0 31 mmDAGB0_RDCLI_GBLSEND_PENDING 0 0x28 1 0 0 BUSY 0 31 mmDAGB0_RDCLI_TLB_PENDING 0 0x29 1 0 0 BUSY 0 31 mmDAGB0_RDCLI_OARB_PENDING 0 0x2a 1 0 0 BUSY 0 31 mmDAGB0_RDCLI_OSD_PENDING 0 0x2b 1 0 0 BUSY 0 31 mmDAGB0_WRCLI0 0 0x2c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI1 0 0x2d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI2 0 0x2e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI3 0 0x2f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI4 0 0x30 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI5 0 0x31 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI6 0 0x32 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI7 0 0x33 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI8 0 0x34 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI9 0 0x35 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI10 0 0x36 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI11 0 0x37 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI12 0 0x38 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI13 0 0x39 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI14 0 0x3a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI15 0 0x3b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WR_CNTL 0 0x3c 7 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_WR_GMI_CNTL 0 0x3d 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_WR_ADDR_DAGB 0 0x3e 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0 0x3f 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x40 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_CGTT_CLK_CTRL 0 0x41 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0 0x42 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0 0x43 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0 0x44 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0 0x45 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0 0x46 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0 0x47 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB 0 0x48 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0 0x49 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0 0x4a 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0 0x4b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0 0x4c 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_VC0_CNTL 0 0x4d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC1_CNTL 0 0x4e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC2_CNTL 0 0x4f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC3_CNTL 0 0x50 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC4_CNTL 0 0x51 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC5_CNTL 0 0x52 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC6_CNTL 0 0x53 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC7_CNTL 0 0x54 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_CNTL_MISC 0 0x55 6 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 mmDAGB0_WR_TLB_CREDIT 0 0x56 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_WR_DATA_CREDIT 0 0x57 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB0_WR_MISC_CREDIT 0 0x58 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB0_WRCLI_ASK_PENDING 0 0x59 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_GO_PENDING 0 0x5a 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_GBLSEND_PENDING 0 0x5b 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_TLB_PENDING 0 0x5c 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_OARB_PENDING 0 0x5d 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_OSD_PENDING 0 0x5e 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_DBUS_ASK_PENDING 0 0x5f 1 0 0 BUSY 0 31 mmDAGB0_WRCLI_DBUS_GO_PENDING 0 0x60 1 0 0 BUSY 0 31 mmDAGB0_DAGB_DLY 0 0x61 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB0_CNTL_MISC 0 0x62 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB0_CNTL_MISC2 0 0x63 11 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 mmDAGB0_FIFO_EMPTY 0 0x64 1 0 0 EMPTY 0 23 mmDAGB0_FIFO_FULL 0 0x65 1 0 0 FULL 0 22 mmDAGB0_WR_CREDITS_FULL 0 0x66 1 0 0 FULL 0 18 mmDAGB0_RD_CREDITS_FULL 0 0x67 1 0 0 FULL 0 17 mmDAGB0_PERFCOUNTER_LO 0 0x68 1 0 0 COUNTER_LO 0 31 mmDAGB0_PERFCOUNTER_HI 0 0x69 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB0_PERFCOUNTER0_CFG 0 0x6a 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER1_CFG 0 0x6b 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER2_CFG 0 0x6c 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER_RSLT_CNTL 0 0x6d 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB0_RESERVE0 0 0x6e 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE1 0 0x6f 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE2 0 0x70 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE3 0 0x71 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE4 0 0x72 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE5 0 0x73 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE6 0 0x74 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE7 0 0x75 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE8 0 0x76 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE9 0 0x77 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE10 0 0x78 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE11 0 0x79 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE12 0 0x7a 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE13 0 0x7b 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE14 0 0x7c 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE15 0 0x7d 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE16 0 0x7e 1 0 0 RESERVE 0 31 mmDAGB0_RESERVE17 0 0x7f 1 0 0 RESERVE 0 31 mmDAGB1_RDCLI0 0 0x80 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI1 0 0x81 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI2 0 0x82 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI3 0 0x83 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI4 0 0x84 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI5 0 0x85 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI6 0 0x86 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI7 0 0x87 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI8 0 0x88 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI9 0 0x89 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI10 0 0x8a 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI11 0 0x8b 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI12 0 0x8c 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI13 0 0x8d 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI14 0 0x8e 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI15 0 0x8f 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RD_CNTL 0 0x90 7 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB1_RD_GMI_CNTL 0 0x91 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB1_RD_ADDR_DAGB 0 0x92 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0 0x93 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x94 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_RD_CGTT_CLK_CTRL 0 0x95 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0 0x96 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0 0x97 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0 0x98 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0 0x99 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0 0x9a 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0 0x9b 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_RD_VC0_CNTL 0 0x9c 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC1_CNTL 0 0x9d 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC2_CNTL 0 0x9e 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC3_CNTL 0 0x9f 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC4_CNTL 0 0xa0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC5_CNTL 0 0xa1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC6_CNTL 0 0xa2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC7_CNTL 0 0xa3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_CNTL_MISC 0 0xa4 6 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 mmDAGB1_RD_TLB_CREDIT 0 0xa5 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB1_RDCLI_ASK_PENDING 0 0xa6 1 0 0 BUSY 0 31 mmDAGB1_RDCLI_GO_PENDING 0 0xa7 1 0 0 BUSY 0 31 mmDAGB1_RDCLI_GBLSEND_PENDING 0 0xa8 1 0 0 BUSY 0 31 mmDAGB1_RDCLI_TLB_PENDING 0 0xa9 1 0 0 BUSY 0 31 mmDAGB1_RDCLI_OARB_PENDING 0 0xaa 1 0 0 BUSY 0 31 mmDAGB1_RDCLI_OSD_PENDING 0 0xab 1 0 0 BUSY 0 31 mmDAGB1_WRCLI0 0 0xac 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI1 0 0xad 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI2 0 0xae 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI3 0 0xaf 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI4 0 0xb0 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI5 0 0xb1 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI6 0 0xb2 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI7 0 0xb3 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI8 0 0xb4 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI9 0 0xb5 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI10 0 0xb6 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI11 0 0xb7 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI12 0 0xb8 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI13 0 0xb9 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI14 0 0xba 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI15 0 0xbb 10 0 0 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WR_CNTL 0 0xbc 7 0 0 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB1_WR_GMI_CNTL 0 0xbd 4 0 0 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB1_WR_ADDR_DAGB 0 0xbe 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0 0xbf 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0 0xc0 8 0 0 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_WR_CGTT_CLK_CTRL 0 0xc1 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0 0xc2 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0 0xc3 8 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0 0xc4 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0 0xc5 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0 0xc6 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0 0xc7 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_DATA_DAGB 0 0xc8 4 0 0 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0 0xc9 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0 0xca 8 0 0 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0 0xcb 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0 0xcc 8 0 0 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_VC0_CNTL 0 0xcd 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC1_CNTL 0 0xce 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC2_CNTL 0 0xcf 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC3_CNTL 0 0xd0 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC4_CNTL 0 0xd1 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC5_CNTL 0 0xd2 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC6_CNTL 0 0xd3 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC7_CNTL 0 0xd4 8 0 0 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_CNTL_MISC 0 0xd5 6 0 0 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 mmDAGB1_WR_TLB_CREDIT 0 0xd6 6 0 0 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB1_WR_DATA_CREDIT 0 0xd7 4 0 0 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB1_WR_MISC_CREDIT 0 0xd8 4 0 0 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB1_WRCLI_ASK_PENDING 0 0xd9 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_GO_PENDING 0 0xda 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_GBLSEND_PENDING 0 0xdb 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_TLB_PENDING 0 0xdc 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_OARB_PENDING 0 0xdd 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_OSD_PENDING 0 0xde 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_DBUS_ASK_PENDING 0 0xdf 1 0 0 BUSY 0 31 mmDAGB1_WRCLI_DBUS_GO_PENDING 0 0xe0 1 0 0 BUSY 0 31 mmDAGB1_DAGB_DLY 0 0xe1 3 0 0 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB1_CNTL_MISC 0 0xe2 10 0 0 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB1_CNTL_MISC2 0 0xe3 11 0 0 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 mmDAGB1_FIFO_EMPTY 0 0xe4 1 0 0 EMPTY 0 23 mmDAGB1_FIFO_FULL 0 0xe5 1 0 0 FULL 0 22 mmDAGB1_WR_CREDITS_FULL 0 0xe6 1 0 0 FULL 0 18 mmDAGB1_RD_CREDITS_FULL 0 0xe7 1 0 0 FULL 0 17 mmDAGB1_PERFCOUNTER_LO 0 0xe8 1 0 0 COUNTER_LO 0 31 mmDAGB1_PERFCOUNTER_HI 0 0xe9 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB1_PERFCOUNTER0_CFG 0 0xea 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER1_CFG 0 0xeb 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER2_CFG 0 0xec 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER_RSLT_CNTL 0 0xed 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB1_RESERVE0 0 0xee 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE1 0 0xef 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE2 0 0xf0 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE3 0 0xf1 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE4 0 0xf2 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE5 0 0xf3 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE6 0 0xf4 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE7 0 0xf5 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE8 0 0xf6 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE9 0 0xf7 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE10 0 0xf8 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE11 0 0xf9 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE12 0 0xfa 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE13 0 0xfb 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE14 0 0xfc 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE15 0 0xfd 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE16 0 0xfe 1 0 0 RESERVE 0 31 mmDAGB1_RESERVE17 0 0xff 1 0 0 RESERVE 0 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0 0x100 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0 0x101 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0 0x102 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0 0x103 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_RD_GRP2VC_MAP 0 0x104 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_WR_GRP2VC_MAP 0 0x105 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_RD_LAZY 0 0x106 6 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 mmMMEA0_DRAM_WR_LAZY 0 0x107 6 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 mmMMEA0_DRAM_RD_CAM_CNTL 0 0x108 8 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 mmMMEA0_DRAM_WR_CAM_CNTL 0 0x109 8 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 mmMMEA0_DRAM_PAGE_BURST 0 0x10a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_DRAM_RD_PRI_AGE 0 0x10b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_WR_PRI_AGE 0 0x10c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_RD_PRI_QUEUING 0 0x10d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_QUEUING 0 0x10e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_FIXED 0 0x10f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_FIXED 0 0x110 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_URGENCY 0 0x111 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_WR_PRI_URGENCY 0 0x112 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0 0x113 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0 0x114 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0 0x115 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0 0x116 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0 0x117 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0 0x118 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_ADDRNORM_BASE_ADDR0 0 0x134 5 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 4 7 INTLV_ADDR_SEL 8 10 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR0 0 0x135 4 0 0 DST_FABRIC_ID 0 4 INTLV_NUM_SOCKETS 8 8 INTLV_NUM_DIES 10 11 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_BASE_ADDR1 0 0x136 5 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 4 7 INTLV_ADDR_SEL 8 10 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR1 0 0x137 4 0 0 DST_FABRIC_ID 0 4 INTLV_NUM_SOCKETS 8 8 INTLV_NUM_DIES 10 11 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_OFFSET_ADDR1 0 0x138 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0 0x143 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA0_ADDRNORMDRAM_TRICHANNEL_CFG 0 0x145 1 0 0 LOG2_ADDR64K_SPACE 0 5 mmMMEA0_ADDRDEC_BANK_CFG 0 0x147 6 0 0 BANK_MASK_DRAM 0 4 BANK_MASK_GMI 5 9 BANKGROUP_SEL_DRAM 10 12 BANKGROUP_SEL_GMI 13 15 BANKGROUP_INTERLEAVE_DRAM 16 16 BANKGROUP_INTERLEAVE_GMI 17 17 mmMMEA0_ADDRDEC_MISC_CFG 0 0x148 13 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 VCM_EN3 3 3 VCM_EN4 4 4 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x149 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x14a 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x14b 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x14c 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x14d 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0 0x14e 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0 0x14f 1 0 0 BANK_XOR 0 4 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0 0x150 2 0 0 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0 0x151 2 0 0 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0 0x152 4 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0 0x15d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0 0x15e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0 0x15f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0 0x160 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0 0x161 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0 0x162 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0 0x163 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0 0x164 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0 0x165 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0 0x166 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0 0x167 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0 0x168 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0 0x169 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0 0x16a 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0 0x16b 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0 0x16c 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0 0x16d 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0 0x16e 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0 0x16f 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0 0x170 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_RM_SEL_CS01 0 0x171 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_CS23 0 0x172 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0 0x173 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0 0x174 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0 0x175 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0 0x176 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0 0x177 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0 0x178 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0 0x179 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0 0x17a 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0 0x17b 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0 0x17c 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0 0x17d 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0 0x17e 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0 0x17f 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0 0x180 1 0 0 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0 0x181 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0 0x182 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0 0x183 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0 0x184 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0 0x185 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0 0x186 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0 0x187 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0 0x188 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_RM_SEL_CS01 0 0x189 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_CS23 0 0x18a 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0 0x18b 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0 0x18c 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_IO_RD_CLI2GRP_MAP0 0 0x1d5 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_RD_CLI2GRP_MAP1 0 0x1d6 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP0 0 0x1d7 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP1 0 0x1d8 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_RD_COMBINE_FLUSH 0 0x1d9 4 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 mmMMEA0_IO_WR_COMBINE_FLUSH 0 0x1da 4 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 mmMMEA0_IO_GROUP_BURST 0 0x1db 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_IO_RD_PRI_AGE 0 0x1dc 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_WR_PRI_AGE 0 0x1dd 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_RD_PRI_QUEUING 0 0x1de 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_QUEUING 0 0x1df 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_FIXED 0 0x1e0 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_FIXED 0 0x1e1 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_URGENCY 0 0x1e2 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_WR_PRI_URGENCY 0 0x1e3 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_RD_PRI_URGENCY_MASK 0 0x1e4 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_WR_PRI_URGENCY_MASK 0 0x1e5 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_RD_PRI_QUANT_PRI1 0 0x1e6 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI2 0 0x1e7 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI3 0 0x1e8 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI1 0 0x1e9 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI2 0 0x1ea 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI3 0 0x1eb 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_SDP_ARB_DRAM 0 0x1ec 7 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 mmMMEA0_SDP_ARB_FINAL 0 0x1ee 14 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 mmMMEA0_SDP_DRAM_PRIORITY 0 0x1ef 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_IO_PRIORITY 0 0x1f1 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_CREDITS 0 0x1f2 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA0_SDP_TAG_RESERVE0 0 0x1f3 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA0_SDP_TAG_RESERVE1 0 0x1f4 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA0_SDP_VCC_RESERVE0 0 0x1f5 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCC_RESERVE1 0 0x1f6 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_VCD_RESERVE0 0 0x1f7 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCD_RESERVE1 0 0x1f8 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_REQ_CNTL 0 0x1f9 5 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 INNER_DOMAIN_MODE 4 4 mmMMEA0_MISC 0 0x1fa 18 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 RRET_SWAP_MODE 6 6 EARLY_SDP_ORIGDATA 7 7 LINKMGR_DYNAMIC_MODE 8 9 LINKMGR_HALT_THRESHOLD 10 11 LINKMGR_RECONNECT_DELAY 12 13 LINKMGR_IDLE_THRESHOLD 14 18 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 19 19 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 20 20 FAVOUR_LAST_CS_IN_DRAM_ARB 21 21 FAVOUR_LAST_CS_IN_GMI_ARB 22 22 SWITCH_CS_ON_W2R_IN_DRAM_ARB 23 23 SWITCH_CS_ON_W2R_IN_GMI_ARB 24 24 mmMMEA0_LATENCY_SAMPLING 0 0x1fb 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA0_PERFCOUNTER_LO 0 0x1fc 1 0 0 COUNTER_LO 0 31 mmMMEA0_PERFCOUNTER_HI 0 0x1fd 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA0_PERFCOUNTER0_CFG 0 0x1fe 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER1_CFG 0 0x1ff 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER_RSLT_CNTL 0 0x200 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA0_EDC_CNT 0 0x206 15 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA0_EDC_CNT2 0 0x207 8 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 mmMMEA0_DSM_CNTL 0 0x208 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA0_DSM_CNTLA 0 0x209 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA0_DSM_CNTLB 0 0x20a 0 0 0 mmMMEA0_DSM_CNTL2 0 0x20b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA0_DSM_CNTL2A 0 0x20c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA0_DSM_CNTL2B 0 0x20d 0 0 0 mmMMEA0_CGTT_CLK_CTRL 0 0x20f 10 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA0_EDC_MODE 0 0x210 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA0_ERR_STATUS 0 0x211 7 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA0_MISC2 0 0x212 5 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0 0x240 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0 0x241 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0 0x242 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0 0x243 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_DRAM_RD_GRP2VC_MAP 0 0x244 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_DRAM_WR_GRP2VC_MAP 0 0x245 4 0 0 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_DRAM_RD_LAZY 0 0x246 6 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 mmMMEA1_DRAM_WR_LAZY 0 0x247 6 0 0 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 mmMMEA1_DRAM_RD_CAM_CNTL 0 0x248 8 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 mmMMEA1_DRAM_WR_CAM_CNTL 0 0x249 8 0 0 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 mmMMEA1_DRAM_PAGE_BURST 0 0x24a 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA1_DRAM_RD_PRI_AGE 0 0x24b 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_DRAM_WR_PRI_AGE 0 0x24c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_DRAM_RD_PRI_QUEUING 0 0x24d 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_DRAM_WR_PRI_QUEUING 0 0x24e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_DRAM_RD_PRI_FIXED 0 0x24f 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_DRAM_WR_PRI_FIXED 0 0x250 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_DRAM_RD_PRI_URGENCY 0 0x251 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_DRAM_WR_PRI_URGENCY 0 0x252 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0 0x253 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0 0x254 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0 0x255 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0 0x256 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0 0x257 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0 0x258 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_ADDRNORM_BASE_ADDR0 0 0x274 5 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 4 7 INTLV_ADDR_SEL 8 10 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR0 0 0x275 4 0 0 DST_FABRIC_ID 0 4 INTLV_NUM_SOCKETS 8 8 INTLV_NUM_DIES 10 11 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_BASE_ADDR1 0 0x276 5 0 0 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 4 7 INTLV_ADDR_SEL 8 10 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR1 0 0x277 4 0 0 DST_FABRIC_ID 0 4 INTLV_NUM_SOCKETS 8 8 INTLV_NUM_DIES 10 11 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_OFFSET_ADDR1 0 0x278 2 0 0 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0 0x283 2 0 0 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA1_ADDRNORMDRAM_TRICHANNEL_CFG 0 0x285 1 0 0 LOG2_ADDR64K_SPACE 0 5 mmMMEA1_ADDRDEC_BANK_CFG 0 0x287 6 0 0 BANK_MASK_DRAM 0 4 BANK_MASK_GMI 5 9 BANKGROUP_SEL_DRAM 10 12 BANKGROUP_SEL_GMI 13 15 BANKGROUP_INTERLEAVE_DRAM 16 16 BANKGROUP_INTERLEAVE_GMI 17 17 mmMMEA1_ADDRDEC_MISC_CFG 0 0x288 13 0 0 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 VCM_EN3 3 3 VCM_EN4 4 4 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x289 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x28a 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x28b 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x28c 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x28d 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0 0x28e 3 0 0 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0 0x28f 1 0 0 BANK_XOR 0 4 mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0 0x290 2 0 0 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0 0x291 2 0 0 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0 0x292 4 0 0 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0 0x29d 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0 0x29e 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0 0x29f 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0 0x2a0 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0 0x2a1 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0 0x2a2 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0 0x2a3 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0 0x2a4 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0 0x2a5 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0 0x2a6 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0 0x2a7 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0 0x2a8 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0 0x2a9 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0 0x2aa 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0 0x2ab 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0 0x2ac 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0 0x2ad 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0 0x2ae 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0 0x2af 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0 0x2b0 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC0_RM_SEL_CS01 0 0x2b1 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_CS23 0 0x2b2 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0 0x2b3 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0 0x2b4 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0 0x2b5 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0 0x2b6 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0 0x2b7 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0 0x2b8 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0 0x2b9 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0 0x2ba 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0 0x2bb 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0 0x2bc 2 0 0 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0 0x2bd 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0 0x2be 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0 0x2bf 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0 0x2c0 1 0 0 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0 0x2c1 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0 0x2c2 7 0 0 NUM_BANK_GROUPS 2 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0 0x2c3 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0 0x2c4 7 0 0 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0 0x2c5 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0 0x2c6 8 0 0 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0 0x2c7 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0 0x2c8 8 0 0 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC1_RM_SEL_CS01 0 0x2c9 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_CS23 0 0x2ca 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0 0x2cb 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0 0x2cc 6 0 0 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_IO_RD_CLI2GRP_MAP0 0 0x315 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_IO_RD_CLI2GRP_MAP1 0 0x316 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_IO_WR_CLI2GRP_MAP0 0 0x317 16 0 0 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_IO_WR_CLI2GRP_MAP1 0 0x318 16 0 0 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_IO_RD_COMBINE_FLUSH 0 0x319 4 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 mmMMEA1_IO_WR_COMBINE_FLUSH 0 0x31a 4 0 0 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 mmMMEA1_IO_GROUP_BURST 0 0x31b 4 0 0 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA1_IO_RD_PRI_AGE 0 0x31c 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_IO_WR_PRI_AGE 0 0x31d 8 0 0 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_IO_RD_PRI_QUEUING 0 0x31e 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_IO_WR_PRI_QUEUING 0 0x31f 4 0 0 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_IO_RD_PRI_FIXED 0 0x320 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_IO_WR_PRI_FIXED 0 0x321 4 0 0 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_IO_RD_PRI_URGENCY 0 0x322 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_IO_WR_PRI_URGENCY 0 0x323 8 0 0 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_IO_RD_PRI_URGENCY_MASK 0 0x324 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_IO_WR_PRI_URGENCY_MASK 0 0x325 32 0 0 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_IO_RD_PRI_QUANT_PRI1 0 0x326 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_RD_PRI_QUANT_PRI2 0 0x327 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_RD_PRI_QUANT_PRI3 0 0x328 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI1 0 0x329 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI2 0 0x32a 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI3 0 0x32b 4 0 0 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_SDP_ARB_DRAM 0 0x32c 7 0 0 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 mmMMEA1_SDP_ARB_FINAL 0 0x32e 14 0 0 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 mmMMEA1_SDP_DRAM_PRIORITY 0 0x32f 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA1_SDP_IO_PRIORITY 0 0x331 8 0 0 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA1_SDP_CREDITS 0 0x332 3 0 0 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA1_SDP_TAG_RESERVE0 0 0x333 4 0 0 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA1_SDP_TAG_RESERVE1 0 0x334 4 0 0 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA1_SDP_VCC_RESERVE0 0 0x335 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA1_SDP_VCC_RESERVE1 0 0x336 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA1_SDP_VCD_RESERVE0 0 0x337 5 0 0 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA1_SDP_VCD_RESERVE1 0 0x338 4 0 0 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA1_SDP_REQ_CNTL 0 0x339 5 0 0 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 INNER_DOMAIN_MODE 4 4 mmMMEA1_MISC 0 0x33a 18 0 0 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 RRET_SWAP_MODE 6 6 EARLY_SDP_ORIGDATA 7 7 LINKMGR_DYNAMIC_MODE 8 9 LINKMGR_HALT_THRESHOLD 10 11 LINKMGR_RECONNECT_DELAY 12 13 LINKMGR_IDLE_THRESHOLD 14 18 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 19 19 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 20 20 FAVOUR_LAST_CS_IN_DRAM_ARB 21 21 FAVOUR_LAST_CS_IN_GMI_ARB 22 22 SWITCH_CS_ON_W2R_IN_DRAM_ARB 23 23 SWITCH_CS_ON_W2R_IN_GMI_ARB 24 24 mmMMEA1_LATENCY_SAMPLING 0 0x33b 16 0 0 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA1_PERFCOUNTER_LO 0 0x33c 1 0 0 COUNTER_LO 0 31 mmMMEA1_PERFCOUNTER_HI 0 0x33d 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA1_PERFCOUNTER0_CFG 0 0x33e 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA1_PERFCOUNTER1_CFG 0 0x33f 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA1_PERFCOUNTER_RSLT_CNTL 0 0x340 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA1_EDC_CNT 0 0x346 15 0 0 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA1_EDC_CNT2 0 0x347 8 0 0 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 mmMMEA1_DSM_CNTL 0 0x348 16 0 0 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA1_DSM_CNTLA 0 0x349 14 0 0 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA1_DSM_CNTLB 0 0x34a 0 0 0 mmMMEA1_DSM_CNTL2 0 0x34b 17 0 0 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA1_DSM_CNTL2A 0 0x34c 14 0 0 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA1_DSM_CNTL2B 0 0x34d 0 0 0 mmMMEA1_CGTT_CLK_CTRL 0 0x34f 10 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA1_EDC_MODE 0 0x350 5 0 0 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA1_ERR_STATUS 0 0x351 7 0 0 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA1_MISC2 0 0x352 5 0 0 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 mmPCTL_MISC 0 0x380 7 0 0 ALLOW_DEEP_SLEEP_MODE 0 2 STCTRL_RSMU_IDLE_THRESHOLD 3 5 STCTRL_DAGB_IDLE_THRESHOLD 6 10 STCTRL_IGNORE_PROTECTION_FAULT 11 11 IGNORE_EA0_SDP_ACK 12 12 IGNORE_EA1_SDP_ACK 13 13 PGFSM_CMD_STATUS 14 15 mmPCTL_MMHUB_DEEPSLEEP 0 0x381 18 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 SETCLEAR 31 31 mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0 0x382 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL_PG_IGNORE_DEEPSLEEP 0 0x383 18 0 0 ALLIPS 0 0 DS0 1 1 DS1 2 2 DS2 3 3 DS3 4 4 DS4 5 5 DS5 6 6 DS6 7 7 DS7 8 8 DS8 9 9 DS9 10 10 DS10 11 11 DS11 12 12 DS12 13 13 DS13 14 14 DS14 15 15 DS15 16 16 DS16 17 17 mmPCTL_PG_DAGB 0 0x384 17 0 0 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_RENG_RAM_INDEX 0 0x385 1 0 0 RENG_RAM_INDEX 0 10 mmPCTL0_RENG_RAM_DATA 0 0x386 1 0 0 RENG_RAM_DATA 0 31 mmPCTL0_RENG_EXECUTE 0 0x387 6 0 0 RENG_EXECUTE_ON_PWR_UP 0 0 RENG_EXECUTE_NOW 1 1 RENG_EXECUTE_NOW_MODE 2 2 RENG_EXECUTE_NOW_START_PTR 3 13 RENG_EXECUTE_END_PTR 14 24 RENG_EXECUTE_ON_REG_UPDATE 25 25 mmPCTL0_MISC 0 0x388 4 0 0 CRITICAL_REGS_LOCK 11 11 TILE_IDLE_THRESHOLD 12 14 RENG_MEM_LS_ENABLE 15 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 16 mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0 0x389 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0 0x38a 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0 0x38b 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0 0x38c 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0 0x38d 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0 0x38e 2 0 0 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x38f 2 0 0 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmPCTL1_RENG_RAM_INDEX 0 0x390 1 0 0 RENG_RAM_INDEX 0 9 mmPCTL1_RENG_RAM_DATA 0 0x391 1 0 0 RENG_RAM_DATA 0 31 mmPCTL1_RENG_EXECUTE 0 0x392 6 0 0 RENG_EXECUTE_ON_PWR_UP 0 0 RENG_EXECUTE_NOW 1 1 RENG_EXECUTE_NOW_MODE 2 2 RENG_EXECUTE_NOW_START_PTR 3 12 RENG_EXECUTE_END_PTR 13 22 RENG_EXECUTE_ON_REG_UPDATE 23 23 mmPCTL1_MISC 0 0x393 5 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0 0x394 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0 0x395 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0 0x396 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0 0x397 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0 0x398 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0 0x399 2 0 0 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x39a 2 0 0 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmPCTL2_RENG_RAM_INDEX 0 0x39b 1 0 0 RENG_RAM_INDEX 0 9 mmPCTL2_RENG_RAM_DATA 0 0x39c 1 0 0 RENG_RAM_DATA 0 31 mmPCTL2_RENG_EXECUTE 0 0x39d 6 0 0 RENG_EXECUTE_ON_PWR_UP 0 0 RENG_EXECUTE_NOW 1 1 RENG_EXECUTE_NOW_MODE 2 2 RENG_EXECUTE_NOW_START_PTR 3 12 RENG_EXECUTE_END_PTR 13 22 RENG_EXECUTE_ON_REG_UPDATE 23 23 mmPCTL2_MISC 0 0x39e 5 0 0 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0 0x39f 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0 0x3a0 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0 0x3a1 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0 0x3a2 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0 0x3a3 2 0 0 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0 0x3a4 2 0 0 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3a5 2 0 0 STCTRL_REGISTER_SAVE_EXCL2 0 15 STCTRL_REGISTER_SAVE_EXCL3 16 31 mmMC_VM_MX_L1_TLB0_STATUS 0 0x588 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB1_STATUS 0 0x589 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB2_STATUS 0 0x58a 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB3_STATUS 0 0x58b 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB4_STATUS 0 0x58c 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB5_STATUS 0 0x58d 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB6_STATUS 0 0x58e 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_TLB7_STATUS 0 0x58f 2 0 0 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmMC_VM_MX_L1_PERFCOUNTER0_CFG 0 0x594 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_MX_L1_PERFCOUNTER1_CFG 0 0x595 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_MX_L1_PERFCOUNTER2_CFG 0 0x596 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_MX_L1_PERFCOUNTER3_CFG 0 0x597 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0 0x598 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_VM_MX_L1_PERFCOUNTER_LO 0 0x59c 1 0 0 COUNTER_LO 0 31 mmMC_VM_MX_L1_PERFCOUNTER_HI 0 0x59d 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATC_L2_CNTL 0 0x640 6 0 0 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 CACHE_INVALIDATE_MODE 8 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 mmATC_L2_CNTL2 0 0x641 6 0 0 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 mmATC_L2_CACHE_DATA0 0 0x644 4 0 0 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 22 VIRTUAL_PAGE_ADDRESS_HIGH 23 26 mmATC_L2_CACHE_DATA1 0 0x645 1 0 0 VIRTUAL_PAGE_ADDRESS_LOW 0 31 mmATC_L2_CACHE_DATA2 0 0x646 1 0 0 PHYSICAL_PAGE_ADDRESS 0 31 mmATC_L2_CNTL3 0 0x647 3 0 0 DELAY_SEND_INVALIDATION_REQUEST 0 2 ATS_REQUEST_CREDIT_MINUS1 3 8 COMPCLKREQ_OFF_HYSTERESIS 9 11 mmATC_L2_STATUS 0 0x648 2 0 0 BUSY 0 0 PARITY_ERROR_INFO 1 29 mmATC_L2_STATUS2 0 0x649 2 0 0 IFIFO_NON_FATAL_PARITY_ERROR_INFO 0 7 IFIFO_FATAL_PARITY_ERROR_INFO 8 15 mmATC_L2_MISC_CG 0 0x64a 3 0 0 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmATC_L2_MEM_POWER_LS 0 0x64b 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 mmATC_L2_CGTT_CLK_CTRL 0 0x64c 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVM_L2_CNTL 0 0x680 14 0 0 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 mmVM_L2_CNTL2 0 0x681 7 0 0 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmVM_L2_CNTL3 0 0x682 11 0 0 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmVM_L2_STATUS 0 0x683 7 0 0 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 mmVM_DUMMY_PAGE_FAULT_CNTL 0 0x684 3 0 0 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 mmVM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x685 1 0 0 DUMMY_PAGE_ADDR_LO32 0 31 mmVM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x686 1 0 0 DUMMY_PAGE_ADDR_HI4 0 3 mmVM_L2_PROTECTION_FAULT_CNTL 0 0x687 17 0 0 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 mmVM_L2_PROTECTION_FAULT_CNTL2 0 0x688 5 0 0 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 mmVM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x689 1 0 0 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x68a 1 0 0 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVM_L2_PROTECTION_FAULT_STATUS 0 0x68b 10 0 0 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 28 mmVM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x68c 1 0 0 LOGICAL_PAGE_ADDR_LO32 0 31 mmVM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x68d 1 0 0 LOGICAL_PAGE_ADDR_HI4 0 3 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x68e 1 0 0 PHYSICAL_PAGE_ADDR_LO32 0 31 mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x68f 1 0 0 PHYSICAL_PAGE_ADDR_HI4 0 3 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x691 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x692 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x693 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x694 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x695 1 0 0 PHYSICAL_PAGE_OFFSET_LO32 0 31 mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x696 1 0 0 PHYSICAL_PAGE_OFFSET_HI4 0 3 mmVM_L2_CNTL4 0 0x697 6 0 0 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 mmVM_L2_MM_GROUP_RT_CLASSES 0 0x698 32 0 0 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 mmVM_L2_BANK_SELECT_RESERVED_CID 0 0x699 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVM_L2_BANK_SELECT_RESERVED_CID2 0 0x69a 5 0 0 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVM_L2_CACHE_PARITY_CNTL 0 0x69b 9 0 0 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 mmVM_L2_CGTT_CLK_CTRL 0 0x69e 5 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVM_CONTEXT0_CNTL 0 0x6c0 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT1_CNTL 0 0x6c1 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT2_CNTL 0 0x6c2 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT3_CNTL 0 0x6c3 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT4_CNTL 0 0x6c4 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT5_CNTL 0 0x6c5 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT6_CNTL 0 0x6c6 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT7_CNTL 0 0x6c7 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT8_CNTL 0 0x6c8 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT9_CNTL 0 0x6c9 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT10_CNTL 0 0x6ca 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT11_CNTL 0 0x6cb 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT12_CNTL 0 0x6cc 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT13_CNTL 0 0x6cd 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT14_CNTL 0 0x6ce 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXT15_CNTL 0 0x6cf 19 0 0 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVM_CONTEXTS_DISABLE 0 0x6d0 16 0 0 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmVM_INVALIDATE_ENG0_SEM 0 0x6d1 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG1_SEM 0 0x6d2 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG2_SEM 0 0x6d3 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG3_SEM 0 0x6d4 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG4_SEM 0 0x6d5 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG5_SEM 0 0x6d6 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG6_SEM 0 0x6d7 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG7_SEM 0 0x6d8 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG8_SEM 0 0x6d9 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG9_SEM 0 0x6da 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG10_SEM 0 0x6db 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG11_SEM 0 0x6dc 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG12_SEM 0 0x6dd 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG13_SEM 0 0x6de 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG14_SEM 0 0x6df 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG15_SEM 0 0x6e0 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG16_SEM 0 0x6e1 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG17_SEM 0 0x6e2 1 0 0 SEMAPHORE 0 0 mmVM_INVALIDATE_ENG0_REQ 0 0x6e3 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG1_REQ 0 0x6e4 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG2_REQ 0 0x6e5 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG3_REQ 0 0x6e6 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG4_REQ 0 0x6e7 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG5_REQ 0 0x6e8 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG6_REQ 0 0x6e9 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG7_REQ 0 0x6ea 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG8_REQ 0 0x6eb 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG9_REQ 0 0x6ec 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG10_REQ 0 0x6ed 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG11_REQ 0 0x6ee 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG12_REQ 0 0x6ef 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG13_REQ 0 0x6f0 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG14_REQ 0 0x6f1 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG15_REQ 0 0x6f2 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG16_REQ 0 0x6f3 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG17_REQ 0 0x6f4 8 0 0 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVM_INVALIDATE_ENG0_ACK 0 0x6f5 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG1_ACK 0 0x6f6 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG2_ACK 0 0x6f7 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG3_ACK 0 0x6f8 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG4_ACK 0 0x6f9 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG5_ACK 0 0x6fa 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG6_ACK 0 0x6fb 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG7_ACK 0 0x6fc 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG8_ACK 0 0x6fd 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG9_ACK 0 0x6fe 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG10_ACK 0 0x6ff 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG11_ACK 0 0x700 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG12_ACK 0 0x701 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG13_ACK 0 0x702 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG14_ACK 0 0x703 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG15_ACK 0 0x704 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG16_ACK 0 0x705 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG17_ACK 0 0x706 2 0 0 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0x707 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0x708 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0x709 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0x70a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0x70b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0x70c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0x70d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0x70e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0x70f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0x710 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0x711 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0x712 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0x713 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0x714 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0x715 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0x716 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0x717 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0x718 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0x719 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0x71a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0x71b 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0x71c 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0x71d 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0x71e 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0x71f 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0x720 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0x721 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0x722 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0x723 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0x724 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0x725 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0x726 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0x727 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0x728 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0x729 2 0 0 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0x72a 1 0 0 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x72b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x72c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x72d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x72e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x72f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x730 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x731 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x732 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x733 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x734 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x735 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x736 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x737 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x738 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x739 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x73a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x73b 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x73c 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x73d 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x73e 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x73f 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x740 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x741 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x742 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x743 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x744 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x745 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x746 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x747 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x748 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x749 1 0 0 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x74a 1 0 0 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x74b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x74c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x74d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x74e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x74f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x750 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x751 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x752 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x753 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x754 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x755 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x756 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x757 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x758 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x759 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x75a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x75b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x75c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x75d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x75e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x75f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x760 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x761 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x762 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x763 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x764 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x765 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x766 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x767 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x768 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x769 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x76a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x76b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x76c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x76d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x76e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x76f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x770 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x771 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x772 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x773 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x774 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x775 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x776 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x777 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x778 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x779 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x77a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x77b 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x77c 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x77d 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x77e 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x77f 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x780 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x781 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x782 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x783 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x784 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x785 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x786 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x787 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x788 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x789 1 0 0 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x78a 1 0 0 LOGICAL_PAGE_NUMBER_HI4 0 3 mmMC_VM_L2_PERFCOUNTER0_CFG 0 0x7a4 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER1_CFG 0 0x7a5 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER2_CFG 0 0x7a6 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER3_CFG 0 0x7a7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER4_CFG 0 0x7a8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER5_CFG 0 0x7a9 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER6_CFG 0 0x7aa 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER7_CFG 0 0x7ab 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x7ac 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMC_VM_L2_PERFCOUNTER_LO 0 0x7b8 1 0 0 COUNTER_LO 0 31 mmMC_VM_L2_PERFCOUNTER_HI 0 0x7b9 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMC_VM_FB_SIZE_OFFSET_VF0 0 0x7cc 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF1 0 0x7cd 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF2 0 0x7ce 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF3 0 0x7cf 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF4 0 0x7d0 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF5 0 0x7d1 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF6 0 0x7d2 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF7 0 0x7d3 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF8 0 0x7d4 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF9 0 0x7d5 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF10 0 0x7d6 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF11 0 0x7d7 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF12 0 0x7d8 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF13 0 0x7d9 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF14 0 0x7da 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmMC_VM_FB_SIZE_OFFSET_VF15 0 0x7db 2 0 0 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVM_IOMMU_MMIO_CNTRL_1 0 0x7dc 1 0 0 MARC_EN 8 8 mmMC_VM_MARC_BASE_LO_0 0 0x7dd 1 0 0 MARC_BASE_LO_0 12 31 mmMC_VM_MARC_BASE_LO_1 0 0x7de 1 0 0 MARC_BASE_LO_1 12 31 mmMC_VM_MARC_BASE_LO_2 0 0x7df 1 0 0 MARC_BASE_LO_2 12 31 mmMC_VM_MARC_BASE_LO_3 0 0x7e0 1 0 0 MARC_BASE_LO_3 12 31 mmMC_VM_MARC_BASE_HI_0 0 0x7e1 1 0 0 MARC_BASE_HI_0 0 19 mmMC_VM_MARC_BASE_HI_1 0 0x7e2 1 0 0 MARC_BASE_HI_1 0 19 mmMC_VM_MARC_BASE_HI_2 0 0x7e3 1 0 0 MARC_BASE_HI_2 0 19 mmMC_VM_MARC_BASE_HI_3 0 0x7e4 1 0 0 MARC_BASE_HI_3 0 19 mmMC_VM_MARC_RELOC_LO_0 0 0x7e5 3 0 0 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmMC_VM_MARC_RELOC_LO_1 0 0x7e6 3 0 0 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmMC_VM_MARC_RELOC_LO_2 0 0x7e7 3 0 0 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmMC_VM_MARC_RELOC_LO_3 0 0x7e8 3 0 0 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmMC_VM_MARC_RELOC_HI_0 0 0x7e9 1 0 0 MARC_RELOC_HI_0 0 19 mmMC_VM_MARC_RELOC_HI_1 0 0x7ea 1 0 0 MARC_RELOC_HI_1 0 19 mmMC_VM_MARC_RELOC_HI_2 0 0x7eb 1 0 0 MARC_RELOC_HI_2 0 19 mmMC_VM_MARC_RELOC_HI_3 0 0x7ec 1 0 0 MARC_RELOC_HI_3 0 19 mmMC_VM_MARC_LEN_LO_0 0 0x7ed 1 0 0 MARC_LEN_LO_0 12 31 mmMC_VM_MARC_LEN_LO_1 0 0x7ee 1 0 0 MARC_LEN_LO_1 12 31 mmMC_VM_MARC_LEN_LO_2 0 0x7ef 1 0 0 MARC_LEN_LO_2 12 31 mmMC_VM_MARC_LEN_LO_3 0 0x7f0 1 0 0 MARC_LEN_LO_3 12 31 mmMC_VM_MARC_LEN_HI_0 0 0x7f1 1 0 0 MARC_LEN_HI_0 0 19 mmMC_VM_MARC_LEN_HI_1 0 0x7f2 1 0 0 MARC_LEN_HI_1 0 19 mmMC_VM_MARC_LEN_HI_2 0 0x7f3 1 0 0 MARC_LEN_HI_2 0 19 mmMC_VM_MARC_LEN_HI_3 0 0x7f4 1 0 0 MARC_LEN_HI_3 0 19 mmVM_IOMMU_CONTROL_REGISTER 0 0x7f5 1 0 0 IOMMUEN 0 0 mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0 0x7f6 1 0 0 PERFOPTEN 13 13 mmVM_PCIE_ATS_CNTL 0 0x7f7 2 0 0 STU 16 20 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_0 0 0x7f8 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_1 0 0x7f9 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_2 0 0x7fa 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_3 0 0x7fb 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_4 0 0x7fc 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_5 0 0x7fd 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_6 0 0x7fe 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_7 0 0x7ff 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_8 0 0x800 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_9 0 0x801 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_10 0 0x802 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_11 0 0x803 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_12 0 0x804 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_13 0 0x805 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_14 0 0x806 1 0 0 ATC_ENABLE 31 31 mmVM_PCIE_ATS_CNTL_VF_15 0 0x807 1 0 0 ATC_ENABLE 31 31 mmUTCL2_CGTT_CLK_CTRL 0 0x808 6 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmMC_SHARED_ACTIVE_FCN_ID 0 0x809 2 0 0 VFID 0 3 VF 31 31 mmMC_VM_XGMI_GPUIOV_ENABLE 0 0x80a 17 0 0 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_PF 31 31 mmMC_VM_NB_MMIOBASE 0 0x810 1 0 0 MMIOBASE 0 31 mmMC_VM_NB_MMIOLIMIT 0 0x811 1 0 0 MMIOLIMIT 0 31 mmMC_VM_NB_PCI_CTRL 0 0x812 1 0 0 MMIOENABLE 23 23 mmMC_VM_NB_PCI_ARB 0 0x813 1 0 0 VGA_HOLE 3 3 mmMC_VM_NB_TOP_OF_DRAM_SLOT1 0 0x814 1 0 0 TOP_OF_DRAM 23 31 mmMC_VM_NB_LOWER_TOP_OF_DRAM2 0 0x815 2 0 0 ENABLE 0 0 LOWER_TOM2 23 31 mmMC_VM_NB_UPPER_TOP_OF_DRAM2 0 0x816 1 0 0 UPPER_TOM2 0 11 mmMC_VM_FB_OFFSET 0 0x817 1 0 0 FB_OFFSET 0 23 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x818 1 0 0 PHYSICAL_PAGE_NUMBER_LSB 0 31 mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x819 1 0 0 PHYSICAL_PAGE_NUMBER_MSB 0 3 mmMC_VM_STEERING 0 0x81a 1 0 0 DEFAULT_STEERING 0 1 mmMC_SHARED_VIRT_RESET_REQ 0 0x81b 2 0 0 VF 0 15 PF 31 31 mmMC_MEM_POWER_LS 0 0x81c 2 0 0 LS_SETUP 0 5 LS_HOLD 6 11 mmMC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0x81d 1 0 0 ADDRESS 0 19 mmMC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0x81e 1 0 0 ADDRESS 0 19 mmMC_VM_APT_CNTL 0 0x81f 2 0 0 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 mmMC_VM_LOCAL_HBM_ADDRESS_START 0 0x820 1 0 0 ADDRESS 0 19 mmMC_VM_LOCAL_HBM_ADDRESS_END 0 0x821 1 0 0 ADDRESS 0 19 mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x822 1 0 0 LOCK 0 0 mmMC_VM_XGMI_LFB_CNTL 0 0x823 2 0 0 PF_LFB_REGION 0 2 PF_MAX_REGION 3 5 mmMC_VM_XGMI_LFB_SIZE 0 0x824 1 0 0 PF_LFB_SIZE 0 15 mmMC_VM_FB_LOCATION_BASE 0 0x82c 1 0 0 FB_BASE 0 23 mmMC_VM_FB_LOCATION_TOP 0 0x82d 1 0 0 FB_TOP 0 23 mmMC_VM_AGP_TOP 0 0x82e 1 0 0 AGP_TOP 0 23 mmMC_VM_AGP_BOT 0 0x82f 1 0 0 AGP_BOT 0 23 mmMC_VM_AGP_BASE 0 0x830 1 0 0 AGP_BASE 0 23 mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x831 1 0 0 LOGICAL_ADDR 0 29 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x832 1 0 0 LOGICAL_ADDR 0 29 mmMC_VM_MX_L1_TLB_CNTL 0 0x833 7 0 0 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 12 ATC_EN 13 13 mmATC_L2_PERFCOUNTER_LO 0 0x840 1 0 0 COUNTER_LO 0 31 mmATC_L2_PERFCOUNTER_HI 0 0x841 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATC_L2_PERFCOUNTER0_CFG 0 0x848 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_L2_PERFCOUNTER1_CFG 0 0x849 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATC_L2_PERFCOUNTER_RSLT_CNTL 0 0x84a 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26