3776 mmDAGB0_RDCLI0 0 0x0 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI1 0 0x1 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI2 0 0x2 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI3 0 0x3 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI4 0 0x4 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI5 0 0x5 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI6 0 0x6 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI7 0 0x7 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI8 0 0x8 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI9 0 0x9 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI10 0 0xa 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI11 0 0xb 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI12 0 0xc 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI13 0 0xd 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI14 0 0xe 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RDCLI15 0 0xf 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_RD_CNTL 0 0x10 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_RD_GMI_CNTL 0 0x11 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_RD_ADDR_DAGB 0 0x12 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0 0x13 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x14 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_RD_CGTT_CLK_CTRL 0 0x15 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0 0x16 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0 0x17 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0 0x18 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0 0x19 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0 0x1a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0 0x1b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_RD_VC0_CNTL 0 0x1c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC1_CNTL 0 0x1d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC2_CNTL 0 0x1e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC3_CNTL 0 0x1f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC4_CNTL 0 0x20 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC5_CNTL 0 0x21 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC6_CNTL 0 0x22 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_VC7_CNTL 0 0x23 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_RD_CNTL_MISC 0 0x24 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB0_RD_TLB_CREDIT 0 0x25 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_RDCLI_ASK_PENDING 0 0x26 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_GO_PENDING 0 0x27 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_GBLSEND_PENDING 0 0x28 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_TLB_PENDING 0 0x29 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_OARB_PENDING 0 0x2a 1 0 1 BUSY 0 31 mmDAGB0_RDCLI_OSD_PENDING 0 0x2b 1 0 1 BUSY 0 31 mmDAGB0_WRCLI0 0 0x2c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI1 0 0x2d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI2 0 0x2e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI3 0 0x2f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI4 0 0x30 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI5 0 0x31 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI6 0 0x32 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI7 0 0x33 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI8 0 0x34 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI9 0 0x35 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI10 0 0x36 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI11 0 0x37 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI12 0 0x38 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI13 0 0x39 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI14 0 0x3a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WRCLI15 0 0x3b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB0_WR_CNTL 0 0x3c 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB0_WR_GMI_CNTL 0 0x3d 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB0_WR_ADDR_DAGB 0 0x3e 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0 0x3f 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x40 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB0_WR_CGTT_CLK_CTRL 0 0x41 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0 0x42 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0 0x43 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0 0x44 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0 0x45 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0 0x46 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0 0x47 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB 0 0x48 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0 0x49 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0 0x4a 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0 0x4b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0 0x4c 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB0_WR_VC0_CNTL 0 0x4d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC1_CNTL 0 0x4e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC2_CNTL 0 0x4f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC3_CNTL 0 0x50 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC4_CNTL 0 0x51 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC5_CNTL 0 0x52 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC6_CNTL 0 0x53 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_VC7_CNTL 0 0x54 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB0_WR_CNTL_MISC 0 0x55 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB0_WR_TLB_CREDIT 0 0x56 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB0_WR_DATA_CREDIT 0 0x57 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB0_WR_MISC_CREDIT 0 0x58 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB0_WRCLI_ASK_PENDING 0 0x5d 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_GO_PENDING 0 0x5e 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_GBLSEND_PENDING 0 0x5f 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_TLB_PENDING 0 0x60 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_OARB_PENDING 0 0x61 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_OSD_PENDING 0 0x62 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_DBUS_ASK_PENDING 0 0x63 1 0 1 BUSY 0 31 mmDAGB0_WRCLI_DBUS_GO_PENDING 0 0x64 1 0 1 BUSY 0 31 mmDAGB0_DAGB_DLY 0 0x65 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB0_CNTL_MISC 0 0x66 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB0_CNTL_MISC2 0 0x67 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB0_FIFO_EMPTY 0 0x68 1 0 1 EMPTY 0 23 mmDAGB0_FIFO_FULL 0 0x69 1 0 1 FULL 0 22 mmDAGB0_WR_CREDITS_FULL 0 0x6a 1 0 1 FULL 0 28 mmDAGB0_RD_CREDITS_FULL 0 0x6b 1 0 1 FULL 0 17 mmDAGB0_PERFCOUNTER_LO 0 0x6c 1 0 1 COUNTER_LO 0 31 mmDAGB0_PERFCOUNTER_HI 0 0x6d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB0_PERFCOUNTER0_CFG 0 0x6e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER1_CFG 0 0x6f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER2_CFG 0 0x70 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB0_PERFCOUNTER_RSLT_CNTL 0 0x71 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB0_RESERVE0 0 0x72 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE1 0 0x73 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE2 0 0x74 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE3 0 0x75 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE4 0 0x76 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE5 0 0x77 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE6 0 0x78 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE7 0 0x79 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE8 0 0x7a 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE9 0 0x7b 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE10 0 0x7c 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE11 0 0x7d 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE12 0 0x7e 1 0 1 RESERVE 0 31 mmDAGB0_RESERVE13 0 0x7f 1 0 1 RESERVE 0 31 mmDAGB1_RDCLI0 0 0x80 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI1 0 0x81 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI2 0 0x82 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI3 0 0x83 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI4 0 0x84 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI5 0 0x85 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI6 0 0x86 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI7 0 0x87 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI8 0 0x88 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI9 0 0x89 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI10 0 0x8a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI11 0 0x8b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI12 0 0x8c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI13 0 0x8d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI14 0 0x8e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RDCLI15 0 0x8f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_RD_CNTL 0 0x90 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB1_RD_GMI_CNTL 0 0x91 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB1_RD_ADDR_DAGB 0 0x92 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0 0x93 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x94 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_RD_CGTT_CLK_CTRL 0 0x95 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0 0x96 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0 0x97 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0 0x98 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0 0x99 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0 0x9a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0 0x9b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_RD_VC0_CNTL 0 0x9c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC1_CNTL 0 0x9d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC2_CNTL 0 0x9e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC3_CNTL 0 0x9f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC4_CNTL 0 0xa0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC5_CNTL 0 0xa1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC6_CNTL 0 0xa2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_VC7_CNTL 0 0xa3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_RD_CNTL_MISC 0 0xa4 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB1_RD_TLB_CREDIT 0 0xa5 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB1_RDCLI_ASK_PENDING 0 0xa6 1 0 1 BUSY 0 31 mmDAGB1_RDCLI_GO_PENDING 0 0xa7 1 0 1 BUSY 0 31 mmDAGB1_RDCLI_GBLSEND_PENDING 0 0xa8 1 0 1 BUSY 0 31 mmDAGB1_RDCLI_TLB_PENDING 0 0xa9 1 0 1 BUSY 0 31 mmDAGB1_RDCLI_OARB_PENDING 0 0xaa 1 0 1 BUSY 0 31 mmDAGB1_RDCLI_OSD_PENDING 0 0xab 1 0 1 BUSY 0 31 mmDAGB1_WRCLI0 0 0xac 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI1 0 0xad 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI2 0 0xae 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI3 0 0xaf 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI4 0 0xb0 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI5 0 0xb1 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI6 0 0xb2 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI7 0 0xb3 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI8 0 0xb4 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI9 0 0xb5 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI10 0 0xb6 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI11 0 0xb7 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI12 0 0xb8 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI13 0 0xb9 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI14 0 0xba 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WRCLI15 0 0xbb 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB1_WR_CNTL 0 0xbc 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB1_WR_GMI_CNTL 0 0xbd 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB1_WR_ADDR_DAGB 0 0xbe 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0 0xbf 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0 0xc0 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB1_WR_CGTT_CLK_CTRL 0 0xc1 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0 0xc2 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0 0xc3 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0 0xc4 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0 0xc5 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0 0xc6 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0 0xc7 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_DATA_DAGB 0 0xc8 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0 0xc9 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0 0xca 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0 0xcb 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0 0xcc 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB1_WR_VC0_CNTL 0 0xcd 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC1_CNTL 0 0xce 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC2_CNTL 0 0xcf 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC3_CNTL 0 0xd0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC4_CNTL 0 0xd1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC5_CNTL 0 0xd2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC6_CNTL 0 0xd3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_VC7_CNTL 0 0xd4 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB1_WR_CNTL_MISC 0 0xd5 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB1_WR_TLB_CREDIT 0 0xd6 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB1_WR_DATA_CREDIT 0 0xd7 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB1_WR_MISC_CREDIT 0 0xd8 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB1_WRCLI_ASK_PENDING 0 0xdd 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_GO_PENDING 0 0xde 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_GBLSEND_PENDING 0 0xdf 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_TLB_PENDING 0 0xe0 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_OARB_PENDING 0 0xe1 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_OSD_PENDING 0 0xe2 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_DBUS_ASK_PENDING 0 0xe3 1 0 1 BUSY 0 31 mmDAGB1_WRCLI_DBUS_GO_PENDING 0 0xe4 1 0 1 BUSY 0 31 mmDAGB1_DAGB_DLY 0 0xe5 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB1_CNTL_MISC 0 0xe6 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB1_CNTL_MISC2 0 0xe7 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB1_FIFO_EMPTY 0 0xe8 1 0 1 EMPTY 0 23 mmDAGB1_FIFO_FULL 0 0xe9 1 0 1 FULL 0 22 mmDAGB1_WR_CREDITS_FULL 0 0xea 1 0 1 FULL 0 28 mmDAGB1_RD_CREDITS_FULL 0 0xeb 1 0 1 FULL 0 17 mmDAGB1_PERFCOUNTER_LO 0 0xec 1 0 1 COUNTER_LO 0 31 mmDAGB1_PERFCOUNTER_HI 0 0xed 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB1_PERFCOUNTER0_CFG 0 0xee 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER1_CFG 0 0xef 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER2_CFG 0 0xf0 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB1_PERFCOUNTER_RSLT_CNTL 0 0xf1 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB1_RESERVE0 0 0xf2 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE1 0 0xf3 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE2 0 0xf4 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE3 0 0xf5 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE4 0 0xf6 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE5 0 0xf7 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE6 0 0xf8 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE7 0 0xf9 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE8 0 0xfa 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE9 0 0xfb 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE10 0 0xfc 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE11 0 0xfd 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE12 0 0xfe 1 0 1 RESERVE 0 31 mmDAGB1_RESERVE13 0 0xff 1 0 1 RESERVE 0 31 mmDAGB2_RDCLI0 0 0x100 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI1 0 0x101 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI2 0 0x102 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI3 0 0x103 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI4 0 0x104 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI5 0 0x105 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI6 0 0x106 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI7 0 0x107 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI8 0 0x108 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI9 0 0x109 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI10 0 0x10a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI11 0 0x10b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI12 0 0x10c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI13 0 0x10d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI14 0 0x10e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RDCLI15 0 0x10f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_RD_CNTL 0 0x110 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB2_RD_GMI_CNTL 0 0x111 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB2_RD_ADDR_DAGB 0 0x112 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0 0x113 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x114 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB2_RD_CGTT_CLK_CTRL 0 0x115 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0 0x116 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0 0x117 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0 0x118 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0 0x119 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0 0x11a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0 0x11b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_RD_VC0_CNTL 0 0x11c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC1_CNTL 0 0x11d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC2_CNTL 0 0x11e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC3_CNTL 0 0x11f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC4_CNTL 0 0x120 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC5_CNTL 0 0x121 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC6_CNTL 0 0x122 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_VC7_CNTL 0 0x123 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_RD_CNTL_MISC 0 0x124 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB2_RD_TLB_CREDIT 0 0x125 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB2_RDCLI_ASK_PENDING 0 0x126 1 0 1 BUSY 0 31 mmDAGB2_RDCLI_GO_PENDING 0 0x127 1 0 1 BUSY 0 31 mmDAGB2_RDCLI_GBLSEND_PENDING 0 0x128 1 0 1 BUSY 0 31 mmDAGB2_RDCLI_TLB_PENDING 0 0x129 1 0 1 BUSY 0 31 mmDAGB2_RDCLI_OARB_PENDING 0 0x12a 1 0 1 BUSY 0 31 mmDAGB2_RDCLI_OSD_PENDING 0 0x12b 1 0 1 BUSY 0 31 mmDAGB2_WRCLI0 0 0x12c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI1 0 0x12d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI2 0 0x12e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI3 0 0x12f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI4 0 0x130 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI5 0 0x131 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI6 0 0x132 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI7 0 0x133 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI8 0 0x134 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI9 0 0x135 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI10 0 0x136 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI11 0 0x137 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI12 0 0x138 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI13 0 0x139 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI14 0 0x13a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WRCLI15 0 0x13b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB2_WR_CNTL 0 0x13c 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB2_WR_GMI_CNTL 0 0x13d 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB2_WR_ADDR_DAGB 0 0x13e 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0 0x13f 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x140 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB2_WR_CGTT_CLK_CTRL 0 0x141 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0 0x142 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0 0x143 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0 0x144 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0 0x145 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0 0x146 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0 0x147 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_WR_DATA_DAGB 0 0x148 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0 0x149 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0 0x14a 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0 0x14b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0 0x14c 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB2_WR_VC0_CNTL 0 0x14d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC1_CNTL 0 0x14e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC2_CNTL 0 0x14f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC3_CNTL 0 0x150 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC4_CNTL 0 0x151 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC5_CNTL 0 0x152 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC6_CNTL 0 0x153 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_VC7_CNTL 0 0x154 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB2_WR_CNTL_MISC 0 0x155 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB2_WR_TLB_CREDIT 0 0x156 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB2_WR_DATA_CREDIT 0 0x157 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB2_WR_MISC_CREDIT 0 0x158 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB2_WRCLI_ASK_PENDING 0 0x15d 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_GO_PENDING 0 0x15e 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_GBLSEND_PENDING 0 0x15f 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_TLB_PENDING 0 0x160 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_OARB_PENDING 0 0x161 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_OSD_PENDING 0 0x162 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_DBUS_ASK_PENDING 0 0x163 1 0 1 BUSY 0 31 mmDAGB2_WRCLI_DBUS_GO_PENDING 0 0x164 1 0 1 BUSY 0 31 mmDAGB2_DAGB_DLY 0 0x165 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB2_CNTL_MISC 0 0x166 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB2_CNTL_MISC2 0 0x167 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB2_FIFO_EMPTY 0 0x168 1 0 1 EMPTY 0 23 mmDAGB2_FIFO_FULL 0 0x169 1 0 1 FULL 0 22 mmDAGB2_WR_CREDITS_FULL 0 0x16a 1 0 1 FULL 0 28 mmDAGB2_RD_CREDITS_FULL 0 0x16b 1 0 1 FULL 0 17 mmDAGB2_PERFCOUNTER_LO 0 0x16c 1 0 1 COUNTER_LO 0 31 mmDAGB2_PERFCOUNTER_HI 0 0x16d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB2_PERFCOUNTER0_CFG 0 0x16e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB2_PERFCOUNTER1_CFG 0 0x16f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB2_PERFCOUNTER2_CFG 0 0x170 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB2_PERFCOUNTER_RSLT_CNTL 0 0x171 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB2_RESERVE0 0 0x172 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE1 0 0x173 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE2 0 0x174 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE3 0 0x175 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE4 0 0x176 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE5 0 0x177 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE6 0 0x178 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE7 0 0x179 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE8 0 0x17a 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE9 0 0x17b 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE10 0 0x17c 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE11 0 0x17d 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE12 0 0x17e 1 0 1 RESERVE 0 31 mmDAGB2_RESERVE13 0 0x17f 1 0 1 RESERVE 0 31 mmDAGB3_RDCLI0 0 0x180 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI1 0 0x181 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI2 0 0x182 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI3 0 0x183 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI4 0 0x184 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI5 0 0x185 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI6 0 0x186 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI7 0 0x187 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI8 0 0x188 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI9 0 0x189 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI10 0 0x18a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI11 0 0x18b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI12 0 0x18c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI13 0 0x18d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI14 0 0x18e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RDCLI15 0 0x18f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_RD_CNTL 0 0x190 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB3_RD_GMI_CNTL 0 0x191 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB3_RD_ADDR_DAGB 0 0x192 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0 0x193 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x194 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB3_RD_CGTT_CLK_CTRL 0 0x195 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0 0x196 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0 0x197 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0 0x198 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0 0x199 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0 0x19a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0 0x19b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_RD_VC0_CNTL 0 0x19c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC1_CNTL 0 0x19d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC2_CNTL 0 0x19e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC3_CNTL 0 0x19f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC4_CNTL 0 0x1a0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC5_CNTL 0 0x1a1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC6_CNTL 0 0x1a2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_VC7_CNTL 0 0x1a3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_RD_CNTL_MISC 0 0x1a4 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB3_RD_TLB_CREDIT 0 0x1a5 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB3_RDCLI_ASK_PENDING 0 0x1a6 1 0 1 BUSY 0 31 mmDAGB3_RDCLI_GO_PENDING 0 0x1a7 1 0 1 BUSY 0 31 mmDAGB3_RDCLI_GBLSEND_PENDING 0 0x1a8 1 0 1 BUSY 0 31 mmDAGB3_RDCLI_TLB_PENDING 0 0x1a9 1 0 1 BUSY 0 31 mmDAGB3_RDCLI_OARB_PENDING 0 0x1aa 1 0 1 BUSY 0 31 mmDAGB3_RDCLI_OSD_PENDING 0 0x1ab 1 0 1 BUSY 0 31 mmDAGB3_WRCLI0 0 0x1ac 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI1 0 0x1ad 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI2 0 0x1ae 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI3 0 0x1af 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI4 0 0x1b0 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI5 0 0x1b1 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI6 0 0x1b2 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI7 0 0x1b3 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI8 0 0x1b4 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI9 0 0x1b5 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI10 0 0x1b6 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI11 0 0x1b7 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI12 0 0x1b8 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI13 0 0x1b9 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI14 0 0x1ba 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WRCLI15 0 0x1bb 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB3_WR_CNTL 0 0x1bc 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB3_WR_GMI_CNTL 0 0x1bd 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB3_WR_ADDR_DAGB 0 0x1be 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0 0x1bf 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x1c0 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB3_WR_CGTT_CLK_CTRL 0 0x1c1 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0 0x1c2 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0 0x1c3 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0 0x1c4 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0 0x1c5 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0 0x1c6 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0 0x1c7 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_WR_DATA_DAGB 0 0x1c8 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0 0x1c9 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0 0x1ca 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0 0x1cb 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0 0x1cc 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB3_WR_VC0_CNTL 0 0x1cd 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC1_CNTL 0 0x1ce 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC2_CNTL 0 0x1cf 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC3_CNTL 0 0x1d0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC4_CNTL 0 0x1d1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC5_CNTL 0 0x1d2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC6_CNTL 0 0x1d3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_VC7_CNTL 0 0x1d4 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB3_WR_CNTL_MISC 0 0x1d5 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB3_WR_TLB_CREDIT 0 0x1d6 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB3_WR_DATA_CREDIT 0 0x1d7 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB3_WR_MISC_CREDIT 0 0x1d8 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB3_WRCLI_ASK_PENDING 0 0x1dd 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_GO_PENDING 0 0x1de 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_GBLSEND_PENDING 0 0x1df 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_TLB_PENDING 0 0x1e0 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_OARB_PENDING 0 0x1e1 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_OSD_PENDING 0 0x1e2 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_DBUS_ASK_PENDING 0 0x1e3 1 0 1 BUSY 0 31 mmDAGB3_WRCLI_DBUS_GO_PENDING 0 0x1e4 1 0 1 BUSY 0 31 mmDAGB3_DAGB_DLY 0 0x1e5 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB3_CNTL_MISC 0 0x1e6 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB3_CNTL_MISC2 0 0x1e7 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB3_FIFO_EMPTY 0 0x1e8 1 0 1 EMPTY 0 23 mmDAGB3_FIFO_FULL 0 0x1e9 1 0 1 FULL 0 22 mmDAGB3_WR_CREDITS_FULL 0 0x1ea 1 0 1 FULL 0 28 mmDAGB3_RD_CREDITS_FULL 0 0x1eb 1 0 1 FULL 0 17 mmDAGB3_PERFCOUNTER_LO 0 0x1ec 1 0 1 COUNTER_LO 0 31 mmDAGB3_PERFCOUNTER_HI 0 0x1ed 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB3_PERFCOUNTER0_CFG 0 0x1ee 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB3_PERFCOUNTER1_CFG 0 0x1ef 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB3_PERFCOUNTER2_CFG 0 0x1f0 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB3_PERFCOUNTER_RSLT_CNTL 0 0x1f1 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB3_RESERVE0 0 0x1f2 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE1 0 0x1f3 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE2 0 0x1f4 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE3 0 0x1f5 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE4 0 0x1f6 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE5 0 0x1f7 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE6 0 0x1f8 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE7 0 0x1f9 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE8 0 0x1fa 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE9 0 0x1fb 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE10 0 0x1fc 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE11 0 0x1fd 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE12 0 0x1fe 1 0 1 RESERVE 0 31 mmDAGB3_RESERVE13 0 0x1ff 1 0 1 RESERVE 0 31 mmDAGB4_RDCLI0 0 0x200 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI1 0 0x201 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI2 0 0x202 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI3 0 0x203 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI4 0 0x204 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI5 0 0x205 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI6 0 0x206 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI7 0 0x207 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI8 0 0x208 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI9 0 0x209 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI10 0 0x20a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI11 0 0x20b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI12 0 0x20c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI13 0 0x20d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI14 0 0x20e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RDCLI15 0 0x20f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_RD_CNTL 0 0x210 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB4_RD_GMI_CNTL 0 0x211 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB4_RD_ADDR_DAGB 0 0x212 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0 0x213 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x214 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB4_RD_CGTT_CLK_CTRL 0 0x215 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0 0x216 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0 0x217 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0 0x218 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0 0x219 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0 0x21a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0 0x21b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_RD_VC0_CNTL 0 0x21c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC1_CNTL 0 0x21d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC2_CNTL 0 0x21e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC3_CNTL 0 0x21f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC4_CNTL 0 0x220 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC5_CNTL 0 0x221 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC6_CNTL 0 0x222 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_VC7_CNTL 0 0x223 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_RD_CNTL_MISC 0 0x224 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB4_RD_TLB_CREDIT 0 0x225 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB4_RDCLI_ASK_PENDING 0 0x226 1 0 1 BUSY 0 31 mmDAGB4_RDCLI_GO_PENDING 0 0x227 1 0 1 BUSY 0 31 mmDAGB4_RDCLI_GBLSEND_PENDING 0 0x228 1 0 1 BUSY 0 31 mmDAGB4_RDCLI_TLB_PENDING 0 0x229 1 0 1 BUSY 0 31 mmDAGB4_RDCLI_OARB_PENDING 0 0x22a 1 0 1 BUSY 0 31 mmDAGB4_RDCLI_OSD_PENDING 0 0x22b 1 0 1 BUSY 0 31 mmDAGB4_WRCLI0 0 0x22c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI1 0 0x22d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI2 0 0x22e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI3 0 0x22f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI4 0 0x230 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI5 0 0x231 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI6 0 0x232 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI7 0 0x233 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI8 0 0x234 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI9 0 0x235 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI10 0 0x236 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI11 0 0x237 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI12 0 0x238 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI13 0 0x239 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI14 0 0x23a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WRCLI15 0 0x23b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB4_WR_CNTL 0 0x23c 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB4_WR_GMI_CNTL 0 0x23d 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB4_WR_ADDR_DAGB 0 0x23e 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0 0x23f 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x240 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB4_WR_CGTT_CLK_CTRL 0 0x241 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0 0x242 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0 0x243 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0 0x244 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0 0x245 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0 0x246 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0 0x247 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_WR_DATA_DAGB 0 0x248 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0 0x249 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0 0x24a 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0 0x24b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0 0x24c 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB4_WR_VC0_CNTL 0 0x24d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC1_CNTL 0 0x24e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC2_CNTL 0 0x24f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC3_CNTL 0 0x250 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC4_CNTL 0 0x251 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC5_CNTL 0 0x252 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC6_CNTL 0 0x253 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_VC7_CNTL 0 0x254 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB4_WR_CNTL_MISC 0 0x255 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB4_WR_TLB_CREDIT 0 0x256 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB4_WR_DATA_CREDIT 0 0x257 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB4_WR_MISC_CREDIT 0 0x258 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB4_WRCLI_ASK_PENDING 0 0x25d 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_GO_PENDING 0 0x25e 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_GBLSEND_PENDING 0 0x25f 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_TLB_PENDING 0 0x260 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_OARB_PENDING 0 0x261 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_OSD_PENDING 0 0x262 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_DBUS_ASK_PENDING 0 0x263 1 0 1 BUSY 0 31 mmDAGB4_WRCLI_DBUS_GO_PENDING 0 0x264 1 0 1 BUSY 0 31 mmDAGB4_DAGB_DLY 0 0x265 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB4_CNTL_MISC 0 0x266 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB4_CNTL_MISC2 0 0x267 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB4_FIFO_EMPTY 0 0x268 1 0 1 EMPTY 0 23 mmDAGB4_FIFO_FULL 0 0x269 1 0 1 FULL 0 22 mmDAGB4_WR_CREDITS_FULL 0 0x26a 1 0 1 FULL 0 28 mmDAGB4_RD_CREDITS_FULL 0 0x26b 1 0 1 FULL 0 17 mmDAGB4_PERFCOUNTER_LO 0 0x26c 1 0 1 COUNTER_LO 0 31 mmDAGB4_PERFCOUNTER_HI 0 0x26d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB4_PERFCOUNTER0_CFG 0 0x26e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB4_PERFCOUNTER1_CFG 0 0x26f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB4_PERFCOUNTER2_CFG 0 0x270 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB4_PERFCOUNTER_RSLT_CNTL 0 0x271 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB4_RESERVE0 0 0x272 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE1 0 0x273 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE2 0 0x274 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE3 0 0x275 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE4 0 0x276 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE5 0 0x277 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE6 0 0x278 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE7 0 0x279 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE8 0 0x27a 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE9 0 0x27b 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE10 0 0x27c 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE11 0 0x27d 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE12 0 0x27e 1 0 1 RESERVE 0 31 mmDAGB4_RESERVE13 0 0x27f 1 0 1 RESERVE 0 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0 0x280 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0 0x281 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0 0x282 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0 0x283 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_DRAM_RD_GRP2VC_MAP 0 0x284 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_WR_GRP2VC_MAP 0 0x285 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_DRAM_RD_LAZY 0 0x286 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_DRAM_WR_LAZY 0 0x287 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_DRAM_RD_CAM_CNTL 0 0x288 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA0_DRAM_WR_CAM_CNTL 0 0x289 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA0_DRAM_PAGE_BURST 0 0x28a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_DRAM_RD_PRI_AGE 0 0x28b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_WR_PRI_AGE 0 0x28c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_DRAM_RD_PRI_QUEUING 0 0x28d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_QUEUING 0 0x28e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_FIXED 0 0x28f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_WR_PRI_FIXED 0 0x290 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_DRAM_RD_PRI_URGENCY 0 0x291 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_WR_PRI_URGENCY 0 0x292 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0 0x293 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0 0x294 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0 0x295 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0 0x296 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0 0x297 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0 0x298 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_RD_CLI2GRP_MAP0 0 0x299 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_GMI_RD_CLI2GRP_MAP1 0 0x29a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_GMI_WR_CLI2GRP_MAP0 0 0x29b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_GMI_WR_CLI2GRP_MAP1 0 0x29c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_GMI_RD_GRP2VC_MAP 0 0x29d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_GMI_WR_GRP2VC_MAP 0 0x29e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA0_GMI_RD_LAZY 0 0x29f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_GMI_WR_LAZY 0 0x2a0 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA0_GMI_RD_CAM_CNTL 0 0x2a1 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA0_GMI_WR_CAM_CNTL 0 0x2a2 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA0_GMI_PAGE_BURST 0 0x2a3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_GMI_RD_PRI_AGE 0 0x2a4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_GMI_WR_PRI_AGE 0 0x2a5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_GMI_RD_PRI_QUEUING 0 0x2a6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_GMI_WR_PRI_QUEUING 0 0x2a7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_GMI_RD_PRI_FIXED 0 0x2a8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_GMI_WR_PRI_FIXED 0 0x2a9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_GMI_RD_PRI_URGENCY 0 0x2aa 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_GMI_WR_PRI_URGENCY 0 0x2ab 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0 0x2ac 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0 0x2ad 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0 0x2ae 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0 0x2af 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0 0x2b0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0 0x2b1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0 0x2b2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0 0x2b3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_ADDRNORM_BASE_ADDR0 0 0x2b4 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR0 0 0x2b5 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_BASE_ADDR1 0 0x2b6 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR1 0 0x2b7 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_OFFSET_ADDR1 0 0x2b8 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA0_ADDRNORM_BASE_ADDR2 0 0x2b9 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR2 0 0x2ba 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_BASE_ADDR3 0 0x2bb 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR3 0 0x2bc 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_OFFSET_ADDR3 0 0x2bd 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA0_ADDRNORM_BASE_ADDR4 0 0x2be 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR4 0 0x2bf 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_BASE_ADDR5 0 0x2c0 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA0_ADDRNORM_LIMIT_ADDR5 0 0x2c1 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA0_ADDRNORM_OFFSET_ADDR5 0 0x2c2 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0 0x2c3 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0 0x2c4 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x2c5 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x2c6 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA0_ADDRDEC_BANK_CFG 0 0x2c7 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA0_ADDRDEC_MISC_CFG 0 0x2c8 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x2c9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x2ca 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x2cb 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x2cc 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x2cd 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x2ce 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0 0x2cf 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0 0x2d0 1 0 1 BANK_XOR 0 5 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0 0x2d1 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0 0x2d2 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0 0x2d3 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0 0x2d4 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0 0x2d5 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0 0x2d6 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0 0x2d7 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0 0x2d8 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0 0x2d9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0 0x2da 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0 0x2db 1 0 1 BANK_XOR 0 5 mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0 0x2dc 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0 0x2dd 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0 0x2de 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0 0x2df 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0 0x2e0 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0 0x2e1 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0 0x2e2 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0 0x2e3 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0 0x2e4 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0 0x2e5 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0 0x2e6 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0 0x2e7 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0 0x2e8 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0 0x2e9 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0 0x2ea 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0 0x2eb 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0 0x2ec 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0 0x2ed 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0 0x2ee 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0 0x2ef 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0 0x2f0 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0 0x2f1 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0 0x2f2 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0 0x2f3 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0 0x2f4 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC0_RM_SEL_CS01 0 0x2f5 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_CS23 0 0x2f6 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0 0x2f7 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0 0x2f8 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0 0x2f9 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0 0x2fa 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0 0x2fb 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0 0x2fc 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0 0x2fd 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0 0x2fe 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0 0x2ff 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0 0x300 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0 0x301 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0 0x302 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0 0x303 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0 0x304 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0 0x305 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0 0x306 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0 0x307 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0 0x308 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0 0x309 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0 0x30a 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0 0x30b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0 0x30c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0 0x30d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0 0x30e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC1_RM_SEL_CS01 0 0x30f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_CS23 0 0x310 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0 0x311 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0 0x312 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0 0x313 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0 0x314 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0 0x315 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0 0x316 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0 0x317 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0 0x318 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0 0x319 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0 0x31a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0 0x31b 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0 0x31c 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0 0x31d 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0 0x31e 1 0 1 ADDR_MASK 1 31 mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0 0x31f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0 0x320 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0 0x321 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0 0x322 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0 0x323 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0 0x324 1 0 1 BANK5 0 4 mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0 0x325 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0 0x326 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0 0x327 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0 0x328 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA0_ADDRDEC2_RM_SEL_CS01 0 0x329 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC2_RM_SEL_CS23 0 0x32a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0 0x32b 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0 0x32c 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0 0x32d 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0 0x32e 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA0_IO_RD_CLI2GRP_MAP0 0 0x355 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_RD_CLI2GRP_MAP1 0 0x356 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP0 0 0x357 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA0_IO_WR_CLI2GRP_MAP1 0 0x358 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA0_IO_RD_COMBINE_FLUSH 0 0x359 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA0_IO_WR_COMBINE_FLUSH 0 0x35a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA0_IO_GROUP_BURST 0 0x35b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA0_IO_RD_PRI_AGE 0 0x35c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_WR_PRI_AGE 0 0x35d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA0_IO_RD_PRI_QUEUING 0 0x35e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_QUEUING 0 0x35f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_FIXED 0 0x360 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_WR_PRI_FIXED 0 0x361 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA0_IO_RD_PRI_URGENCY 0 0x362 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_WR_PRI_URGENCY 0 0x363 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0 0x364 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0 0x365 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA0_IO_RD_PRI_QUANT_PRI1 0 0x366 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI2 0 0x367 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_RD_PRI_QUANT_PRI3 0 0x368 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI1 0 0x369 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI2 0 0x36a 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_IO_WR_PRI_QUANT_PRI3 0 0x36b 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA0_SDP_ARB_DRAM 0 0x36c 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA0_SDP_ARB_GMI 0 0x36d 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA0_SDP_ARB_FINAL 0 0x36e 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA0_SDP_DRAM_PRIORITY 0 0x36f 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_GMI_PRIORITY 0 0x370 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_IO_PRIORITY 0 0x371 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA0_SDP_CREDITS 0 0x372 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA0_SDP_TAG_RESERVE0 0 0x373 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA0_SDP_TAG_RESERVE1 0 0x374 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA0_SDP_VCC_RESERVE0 0 0x375 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCC_RESERVE1 0 0x376 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_VCD_RESERVE0 0 0x377 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA0_SDP_VCD_RESERVE1 0 0x378 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA0_SDP_REQ_CNTL 0 0x379 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA0_MISC 0 0x37a 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA0_LATENCY_SAMPLING 0 0x37b 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA0_PERFCOUNTER_LO 0 0x37c 1 0 1 COUNTER_LO 0 31 mmMMEA0_PERFCOUNTER_HI 0 0x37d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA0_PERFCOUNTER0_CFG 0 0x37e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER1_CFG 0 0x37f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA0_PERFCOUNTER_RSLT_CNTL 0 0x380 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA0_EDC_CNT 0 0x386 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA0_EDC_CNT2 0 0x387 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA0_DSM_CNTL 0 0x388 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA0_DSM_CNTLA 0 0x389 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA0_DSM_CNTLB 0 0x38a 0 0 1 mmMMEA0_DSM_CNTL2 0 0x38b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA0_DSM_CNTL2A 0 0x38c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA0_DSM_CNTL2B 0 0x38d 0 0 1 mmMMEA0_CGTT_CLK_CTRL 0 0x38f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA0_EDC_MODE 0 0x390 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA0_ERR_STATUS 0 0x391 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA0_MISC2 0 0x392 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA0_ADDRDEC_SELECT 0 0x393 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA0_EDC_CNT3 0 0x394 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0 0x3c0 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0 0x3c1 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0 0x3c2 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0 0x3c3 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_DRAM_RD_GRP2VC_MAP 0 0x3c4 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_DRAM_WR_GRP2VC_MAP 0 0x3c5 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_DRAM_RD_LAZY 0 0x3c6 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA1_DRAM_WR_LAZY 0 0x3c7 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA1_DRAM_RD_CAM_CNTL 0 0x3c8 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA1_DRAM_WR_CAM_CNTL 0 0x3c9 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA1_DRAM_PAGE_BURST 0 0x3ca 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA1_DRAM_RD_PRI_AGE 0 0x3cb 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_DRAM_WR_PRI_AGE 0 0x3cc 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_DRAM_RD_PRI_QUEUING 0 0x3cd 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_DRAM_WR_PRI_QUEUING 0 0x3ce 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_DRAM_RD_PRI_FIXED 0 0x3cf 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_DRAM_WR_PRI_FIXED 0 0x3d0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_DRAM_RD_PRI_URGENCY 0 0x3d1 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_DRAM_WR_PRI_URGENCY 0 0x3d2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0 0x3d3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0 0x3d4 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0 0x3d5 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0 0x3d6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0 0x3d7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0 0x3d8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_RD_CLI2GRP_MAP0 0 0x3d9 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_GMI_RD_CLI2GRP_MAP1 0 0x3da 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_GMI_WR_CLI2GRP_MAP0 0 0x3db 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_GMI_WR_CLI2GRP_MAP1 0 0x3dc 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_GMI_RD_GRP2VC_MAP 0 0x3dd 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_GMI_WR_GRP2VC_MAP 0 0x3de 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA1_GMI_RD_LAZY 0 0x3df 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA1_GMI_WR_LAZY 0 0x3e0 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA1_GMI_RD_CAM_CNTL 0 0x3e1 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA1_GMI_WR_CAM_CNTL 0 0x3e2 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA1_GMI_PAGE_BURST 0 0x3e3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA1_GMI_RD_PRI_AGE 0 0x3e4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_GMI_WR_PRI_AGE 0 0x3e5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_GMI_RD_PRI_QUEUING 0 0x3e6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_GMI_WR_PRI_QUEUING 0 0x3e7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_GMI_RD_PRI_FIXED 0 0x3e8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_GMI_WR_PRI_FIXED 0 0x3e9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_GMI_RD_PRI_URGENCY 0 0x3ea 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_GMI_WR_PRI_URGENCY 0 0x3eb 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0 0x3ec 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0 0x3ed 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0 0x3ee 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0 0x3ef 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0 0x3f0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0 0x3f1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0 0x3f2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0 0x3f3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_ADDRNORM_BASE_ADDR0 0 0x3f4 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR0 0 0x3f5 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_BASE_ADDR1 0 0x3f6 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR1 0 0x3f7 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_OFFSET_ADDR1 0 0x3f8 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA1_ADDRNORM_BASE_ADDR2 0 0x3f9 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR2 0 0x3fa 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_BASE_ADDR3 0 0x3fb 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR3 0 0x3fc 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_OFFSET_ADDR3 0 0x3fd 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA1_ADDRNORM_BASE_ADDR4 0 0x3fe 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR4 0 0x3ff 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_BASE_ADDR5 0 0x400 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA1_ADDRNORM_LIMIT_ADDR5 0 0x401 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA1_ADDRNORM_OFFSET_ADDR5 0 0x402 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0 0x403 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0 0x404 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x405 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x406 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA1_ADDRDEC_BANK_CFG 0 0x407 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA1_ADDRDEC_MISC_CFG 0 0x408 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x409 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x40a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x40b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x40c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x40d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x40e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0 0x40f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0 0x410 1 0 1 BANK_XOR 0 5 mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0 0x411 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0 0x412 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0 0x413 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0 0x414 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0 0x415 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0 0x416 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0 0x417 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0 0x418 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0 0x419 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0 0x41a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0 0x41b 1 0 1 BANK_XOR 0 5 mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0 0x41c 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0 0x41d 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0 0x41e 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0 0x41f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0 0x420 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0 0x421 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0 0x422 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0 0x423 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0 0x424 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0 0x425 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0 0x426 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0 0x427 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0 0x428 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0 0x429 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0 0x42a 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0 0x42b 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0 0x42c 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0 0x42d 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0 0x42e 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0 0x42f 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0 0x430 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0 0x431 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0 0x432 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0 0x433 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0 0x434 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC0_RM_SEL_CS01 0 0x435 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_CS23 0 0x436 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0 0x437 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0 0x438 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0 0x439 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0 0x43a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0 0x43b 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0 0x43c 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0 0x43d 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0 0x43e 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0 0x43f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0 0x440 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0 0x441 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0 0x442 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0 0x443 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0 0x444 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0 0x445 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0 0x446 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0 0x447 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0 0x448 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0 0x449 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0 0x44a 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0 0x44b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0 0x44c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0 0x44d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0 0x44e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC1_RM_SEL_CS01 0 0x44f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_CS23 0 0x450 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0 0x451 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0 0x452 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0 0x453 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0 0x454 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0 0x455 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0 0x456 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0 0x457 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0 0x458 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0 0x459 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0 0x45a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0 0x45b 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0 0x45c 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0 0x45d 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0 0x45e 1 0 1 ADDR_MASK 1 31 mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0 0x45f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0 0x460 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0 0x461 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0 0x462 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0 0x463 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0 0x464 1 0 1 BANK5 0 4 mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0 0x465 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0 0x466 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0 0x467 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0 0x468 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA1_ADDRDEC2_RM_SEL_CS01 0 0x469 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC2_RM_SEL_CS23 0 0x46a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0 0x46b 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0 0x46c 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0 0x46d 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0 0x46e 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA1_IO_RD_CLI2GRP_MAP0 0 0x495 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_IO_RD_CLI2GRP_MAP1 0 0x496 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_IO_WR_CLI2GRP_MAP0 0 0x497 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA1_IO_WR_CLI2GRP_MAP1 0 0x498 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA1_IO_RD_COMBINE_FLUSH 0 0x499 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA1_IO_WR_COMBINE_FLUSH 0 0x49a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA1_IO_GROUP_BURST 0 0x49b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA1_IO_RD_PRI_AGE 0 0x49c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_IO_WR_PRI_AGE 0 0x49d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA1_IO_RD_PRI_QUEUING 0 0x49e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_IO_WR_PRI_QUEUING 0 0x49f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA1_IO_RD_PRI_FIXED 0 0x4a0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_IO_WR_PRI_FIXED 0 0x4a1 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA1_IO_RD_PRI_URGENCY 0 0x4a2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_IO_WR_PRI_URGENCY 0 0x4a3 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0 0x4a4 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0 0x4a5 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA1_IO_RD_PRI_QUANT_PRI1 0 0x4a6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_RD_PRI_QUANT_PRI2 0 0x4a7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_RD_PRI_QUANT_PRI3 0 0x4a8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI1 0 0x4a9 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI2 0 0x4aa 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_IO_WR_PRI_QUANT_PRI3 0 0x4ab 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA1_SDP_ARB_DRAM 0 0x4ac 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA1_SDP_ARB_GMI 0 0x4ad 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA1_SDP_ARB_FINAL 0 0x4ae 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA1_SDP_DRAM_PRIORITY 0 0x4af 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA1_SDP_GMI_PRIORITY 0 0x4b0 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA1_SDP_IO_PRIORITY 0 0x4b1 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA1_SDP_CREDITS 0 0x4b2 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA1_SDP_TAG_RESERVE0 0 0x4b3 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA1_SDP_TAG_RESERVE1 0 0x4b4 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA1_SDP_VCC_RESERVE0 0 0x4b5 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA1_SDP_VCC_RESERVE1 0 0x4b6 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA1_SDP_VCD_RESERVE0 0 0x4b7 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA1_SDP_VCD_RESERVE1 0 0x4b8 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA1_SDP_REQ_CNTL 0 0x4b9 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA1_MISC 0 0x4ba 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA1_LATENCY_SAMPLING 0 0x4bb 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA1_PERFCOUNTER_LO 0 0x4bc 1 0 1 COUNTER_LO 0 31 mmMMEA1_PERFCOUNTER_HI 0 0x4bd 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA1_PERFCOUNTER0_CFG 0 0x4be 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA1_PERFCOUNTER1_CFG 0 0x4bf 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA1_PERFCOUNTER_RSLT_CNTL 0 0x4c0 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA1_EDC_CNT 0 0x4c6 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA1_EDC_CNT2 0 0x4c7 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA1_DSM_CNTL 0 0x4c8 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA1_DSM_CNTLA 0 0x4c9 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA1_DSM_CNTLB 0 0x4ca 0 0 1 mmMMEA1_DSM_CNTL2 0 0x4cb 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA1_DSM_CNTL2A 0 0x4cc 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA1_DSM_CNTL2B 0 0x4cd 0 0 1 mmMMEA1_CGTT_CLK_CTRL 0 0x4cf 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA1_EDC_MODE 0 0x4d0 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA1_ERR_STATUS 0 0x4d1 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA1_MISC2 0 0x4d2 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA1_ADDRDEC_SELECT 0 0x4d3 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA1_EDC_CNT3 0 0x4d4 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0 0x500 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0 0x501 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0 0x502 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0 0x503 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_DRAM_RD_GRP2VC_MAP 0 0x504 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA2_DRAM_WR_GRP2VC_MAP 0 0x505 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA2_DRAM_RD_LAZY 0 0x506 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA2_DRAM_WR_LAZY 0 0x507 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA2_DRAM_RD_CAM_CNTL 0 0x508 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA2_DRAM_WR_CAM_CNTL 0 0x509 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA2_DRAM_PAGE_BURST 0 0x50a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA2_DRAM_RD_PRI_AGE 0 0x50b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_DRAM_WR_PRI_AGE 0 0x50c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_DRAM_RD_PRI_QUEUING 0 0x50d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_DRAM_WR_PRI_QUEUING 0 0x50e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_DRAM_RD_PRI_FIXED 0 0x50f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_DRAM_WR_PRI_FIXED 0 0x510 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_DRAM_RD_PRI_URGENCY 0 0x511 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_DRAM_WR_PRI_URGENCY 0 0x512 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0 0x513 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0 0x514 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0 0x515 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0 0x516 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0 0x517 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0 0x518 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_RD_CLI2GRP_MAP0 0 0x519 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_GMI_RD_CLI2GRP_MAP1 0 0x51a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_GMI_WR_CLI2GRP_MAP0 0 0x51b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_GMI_WR_CLI2GRP_MAP1 0 0x51c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_GMI_RD_GRP2VC_MAP 0 0x51d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA2_GMI_WR_GRP2VC_MAP 0 0x51e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA2_GMI_RD_LAZY 0 0x51f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA2_GMI_WR_LAZY 0 0x520 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA2_GMI_RD_CAM_CNTL 0 0x521 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA2_GMI_WR_CAM_CNTL 0 0x522 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA2_GMI_PAGE_BURST 0 0x523 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA2_GMI_RD_PRI_AGE 0 0x524 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_GMI_WR_PRI_AGE 0 0x525 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_GMI_RD_PRI_QUEUING 0 0x526 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_GMI_WR_PRI_QUEUING 0 0x527 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_GMI_RD_PRI_FIXED 0 0x528 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_GMI_WR_PRI_FIXED 0 0x529 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_GMI_RD_PRI_URGENCY 0 0x52a 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_GMI_WR_PRI_URGENCY 0 0x52b 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0 0x52c 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0 0x52d 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0 0x52e 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0 0x52f 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0 0x530 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0 0x531 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0 0x532 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0 0x533 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_ADDRNORM_BASE_ADDR0 0 0x534 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR0 0 0x535 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_BASE_ADDR1 0 0x536 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR1 0 0x537 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_OFFSET_ADDR1 0 0x538 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA2_ADDRNORM_BASE_ADDR2 0 0x539 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR2 0 0x53a 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_BASE_ADDR3 0 0x53b 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR3 0 0x53c 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_OFFSET_ADDR3 0 0x53d 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA2_ADDRNORM_BASE_ADDR4 0 0x53e 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR4 0 0x53f 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_BASE_ADDR5 0 0x540 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA2_ADDRNORM_LIMIT_ADDR5 0 0x541 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA2_ADDRNORM_OFFSET_ADDR5 0 0x542 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0 0x543 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0 0x544 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x545 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x546 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA2_ADDRDEC_BANK_CFG 0 0x547 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA2_ADDRDEC_MISC_CFG 0 0x548 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x549 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x54a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x54b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x54c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x54d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x54e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0 0x54f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0 0x550 1 0 1 BANK_XOR 0 5 mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0 0x551 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0 0x552 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0 0x553 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0 0x554 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0 0x555 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0 0x556 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0 0x557 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0 0x558 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0 0x559 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0 0x55a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0 0x55b 1 0 1 BANK_XOR 0 5 mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0 0x55c 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0 0x55d 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0 0x55e 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0 0x55f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0 0x560 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0 0x561 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0 0x562 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0 0x563 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0 0x564 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0 0x565 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0 0x566 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0 0x567 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0 0x568 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0 0x569 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0 0x56a 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0 0x56b 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0 0x56c 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0 0x56d 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0 0x56e 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0 0x56f 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0 0x570 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0 0x571 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0 0x572 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0 0x573 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0 0x574 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC0_RM_SEL_CS01 0 0x575 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC0_RM_SEL_CS23 0 0x576 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0 0x577 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0 0x578 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0 0x579 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0 0x57a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0 0x57b 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0 0x57c 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0 0x57d 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0 0x57e 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0 0x57f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0 0x580 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0 0x581 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0 0x582 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0 0x583 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0 0x584 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0 0x585 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0 0x586 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0 0x587 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0 0x588 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0 0x589 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0 0x58a 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0 0x58b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0 0x58c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0 0x58d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0 0x58e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC1_RM_SEL_CS01 0 0x58f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC1_RM_SEL_CS23 0 0x590 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0 0x591 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0 0x592 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0 0x593 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0 0x594 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0 0x595 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0 0x596 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0 0x597 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0 0x598 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0 0x599 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0 0x59a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0 0x59b 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0 0x59c 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0 0x59d 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0 0x59e 1 0 1 ADDR_MASK 1 31 mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0 0x59f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0 0x5a0 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0 0x5a1 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0 0x5a2 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0 0x5a3 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0 0x5a4 1 0 1 BANK5 0 4 mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0 0x5a5 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0 0x5a6 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0 0x5a7 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0 0x5a8 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA2_ADDRDEC2_RM_SEL_CS01 0 0x5a9 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC2_RM_SEL_CS23 0 0x5aa 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0 0x5ab 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0 0x5ac 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0 0x5ad 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0 0x5ae 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA2_IO_RD_CLI2GRP_MAP0 0 0x5d5 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_IO_RD_CLI2GRP_MAP1 0 0x5d6 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_IO_WR_CLI2GRP_MAP0 0 0x5d7 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA2_IO_WR_CLI2GRP_MAP1 0 0x5d8 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA2_IO_RD_COMBINE_FLUSH 0 0x5d9 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA2_IO_WR_COMBINE_FLUSH 0 0x5da 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA2_IO_GROUP_BURST 0 0x5db 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA2_IO_RD_PRI_AGE 0 0x5dc 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_IO_WR_PRI_AGE 0 0x5dd 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA2_IO_RD_PRI_QUEUING 0 0x5de 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_IO_WR_PRI_QUEUING 0 0x5df 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA2_IO_RD_PRI_FIXED 0 0x5e0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_IO_WR_PRI_FIXED 0 0x5e1 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA2_IO_RD_PRI_URGENCY 0 0x5e2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_IO_WR_PRI_URGENCY 0 0x5e3 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA2_IO_RD_PRI_URGENCY_MASKING 0 0x5e4 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA2_IO_WR_PRI_URGENCY_MASKING 0 0x5e5 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA2_IO_RD_PRI_QUANT_PRI1 0 0x5e6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_IO_RD_PRI_QUANT_PRI2 0 0x5e7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_IO_RD_PRI_QUANT_PRI3 0 0x5e8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_IO_WR_PRI_QUANT_PRI1 0 0x5e9 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_IO_WR_PRI_QUANT_PRI2 0 0x5ea 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_IO_WR_PRI_QUANT_PRI3 0 0x5eb 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA2_SDP_ARB_DRAM 0 0x5ec 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA2_SDP_ARB_GMI 0 0x5ed 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA2_SDP_ARB_FINAL 0 0x5ee 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA2_SDP_DRAM_PRIORITY 0 0x5ef 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA2_SDP_GMI_PRIORITY 0 0x5f0 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA2_SDP_IO_PRIORITY 0 0x5f1 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA2_SDP_CREDITS 0 0x5f2 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA2_SDP_TAG_RESERVE0 0 0x5f3 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA2_SDP_TAG_RESERVE1 0 0x5f4 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA2_SDP_VCC_RESERVE0 0 0x5f5 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA2_SDP_VCC_RESERVE1 0 0x5f6 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA2_SDP_VCD_RESERVE0 0 0x5f7 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA2_SDP_VCD_RESERVE1 0 0x5f8 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA2_SDP_REQ_CNTL 0 0x5f9 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA2_MISC 0 0x5fa 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA2_LATENCY_SAMPLING 0 0x5fb 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA2_PERFCOUNTER_LO 0 0x5fc 1 0 1 COUNTER_LO 0 31 mmMMEA2_PERFCOUNTER_HI 0 0x5fd 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA2_PERFCOUNTER0_CFG 0 0x5fe 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA2_PERFCOUNTER1_CFG 0 0x5ff 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA2_PERFCOUNTER_RSLT_CNTL 0 0x600 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA2_EDC_CNT 0 0x606 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA2_EDC_CNT2 0 0x607 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA2_DSM_CNTL 0 0x608 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA2_DSM_CNTLA 0 0x609 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA2_DSM_CNTLB 0 0x60a 0 0 1 mmMMEA2_DSM_CNTL2 0 0x60b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA2_DSM_CNTL2A 0 0x60c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA2_DSM_CNTL2B 0 0x60d 0 0 1 mmMMEA2_CGTT_CLK_CTRL 0 0x60f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA2_EDC_MODE 0 0x610 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA2_ERR_STATUS 0 0x611 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA2_MISC2 0 0x612 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA2_ADDRDEC_SELECT 0 0x613 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA2_EDC_CNT3 0 0x614 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA3_DRAM_RD_CLI2GRP_MAP0 0 0x640 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_DRAM_RD_CLI2GRP_MAP1 0 0x641 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_DRAM_WR_CLI2GRP_MAP0 0 0x642 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_DRAM_WR_CLI2GRP_MAP1 0 0x643 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_DRAM_RD_GRP2VC_MAP 0 0x644 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA3_DRAM_WR_GRP2VC_MAP 0 0x645 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA3_DRAM_RD_LAZY 0 0x646 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA3_DRAM_WR_LAZY 0 0x647 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA3_DRAM_RD_CAM_CNTL 0 0x648 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA3_DRAM_WR_CAM_CNTL 0 0x649 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA3_DRAM_PAGE_BURST 0 0x64a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA3_DRAM_RD_PRI_AGE 0 0x64b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_DRAM_WR_PRI_AGE 0 0x64c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_DRAM_RD_PRI_QUEUING 0 0x64d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_DRAM_WR_PRI_QUEUING 0 0x64e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_DRAM_RD_PRI_FIXED 0 0x64f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_DRAM_WR_PRI_FIXED 0 0x650 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_DRAM_RD_PRI_URGENCY 0 0x651 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_DRAM_WR_PRI_URGENCY 0 0x652 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 0 0x653 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 0 0x654 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 0 0x655 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 0 0x656 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 0 0x657 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 0 0x658 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_RD_CLI2GRP_MAP0 0 0x659 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_GMI_RD_CLI2GRP_MAP1 0 0x65a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_GMI_WR_CLI2GRP_MAP0 0 0x65b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_GMI_WR_CLI2GRP_MAP1 0 0x65c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_GMI_RD_GRP2VC_MAP 0 0x65d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA3_GMI_WR_GRP2VC_MAP 0 0x65e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA3_GMI_RD_LAZY 0 0x65f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA3_GMI_WR_LAZY 0 0x660 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA3_GMI_RD_CAM_CNTL 0 0x661 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA3_GMI_WR_CAM_CNTL 0 0x662 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA3_GMI_PAGE_BURST 0 0x663 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA3_GMI_RD_PRI_AGE 0 0x664 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_GMI_WR_PRI_AGE 0 0x665 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_GMI_RD_PRI_QUEUING 0 0x666 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_GMI_WR_PRI_QUEUING 0 0x667 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_GMI_RD_PRI_FIXED 0 0x668 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_GMI_WR_PRI_FIXED 0 0x669 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_GMI_RD_PRI_URGENCY 0 0x66a 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_GMI_WR_PRI_URGENCY 0 0x66b 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_GMI_RD_PRI_URGENCY_MASKING 0 0x66c 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA3_GMI_WR_PRI_URGENCY_MASKING 0 0x66d 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA3_GMI_RD_PRI_QUANT_PRI1 0 0x66e 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_RD_PRI_QUANT_PRI2 0 0x66f 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_RD_PRI_QUANT_PRI3 0 0x670 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_WR_PRI_QUANT_PRI1 0 0x671 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_WR_PRI_QUANT_PRI2 0 0x672 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_GMI_WR_PRI_QUANT_PRI3 0 0x673 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_ADDRNORM_BASE_ADDR0 0 0x674 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR0 0 0x675 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_BASE_ADDR1 0 0x676 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR1 0 0x677 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_OFFSET_ADDR1 0 0x678 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA3_ADDRNORM_BASE_ADDR2 0 0x679 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR2 0 0x67a 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_BASE_ADDR3 0 0x67b 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR3 0 0x67c 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_OFFSET_ADDR3 0 0x67d 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA3_ADDRNORM_BASE_ADDR4 0 0x67e 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR4 0 0x67f 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_BASE_ADDR5 0 0x680 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA3_ADDRNORM_LIMIT_ADDR5 0 0x681 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA3_ADDRNORM_OFFSET_ADDR5 0 0x682 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA3_ADDRNORMDRAM_HOLE_CNTL 0 0x683 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA3_ADDRNORMGMI_HOLE_CNTL 0 0x684 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x685 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x686 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA3_ADDRDEC_BANK_CFG 0 0x687 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA3_ADDRDEC_MISC_CFG 0 0x688 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x689 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x68a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x68b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x68c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x68d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x68e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC 0 0x68f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 0 0x690 1 0 1 BANK_XOR 0 5 mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 0 0x691 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 0 0x692 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0 0x693 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 0 0x694 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 0 0x695 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 0 0x696 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 0 0x697 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 0 0x698 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 0 0x699 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_PC 0 0x69a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 0 0x69b 1 0 1 BANK_XOR 0 5 mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 0 0x69c 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 0 0x69d 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA3_ADDRDECGMI_HARVEST_ENABLE 0 0x69e 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 0 0x69f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 0 0x6a0 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 0 0x6a1 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 0 0x6a2 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0 0x6a3 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0 0x6a4 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0 0x6a5 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0 0x6a6 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 0 0x6a7 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 0 0x6a8 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0 0x6a9 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0 0x6aa 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 0 0x6ab 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 0 0x6ac 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 0 0x6ad 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 0 0x6ae 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0 0x6af 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0 0x6b0 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0 0x6b1 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0 0x6b2 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0 0x6b3 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0 0x6b4 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC0_RM_SEL_CS01 0 0x6b5 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC0_RM_SEL_CS23 0 0x6b6 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 0 0x6b7 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 0 0x6b8 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 0 0x6b9 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 0 0x6ba 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 0 0x6bb 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 0 0x6bc 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0 0x6bd 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0 0x6be 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0 0x6bf 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0 0x6c0 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 0 0x6c1 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 0 0x6c2 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0 0x6c3 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0 0x6c4 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 0 0x6c5 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 0 0x6c6 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 0 0x6c7 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 0 0x6c8 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0 0x6c9 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0 0x6ca 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0 0x6cb 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0 0x6cc 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0 0x6cd 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0 0x6ce 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC1_RM_SEL_CS01 0 0x6cf 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC1_RM_SEL_CS23 0 0x6d0 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 0 0x6d1 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 0 0x6d2 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 0 0x6d3 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 0 0x6d4 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 0 0x6d5 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 0 0x6d6 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0 0x6d7 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0 0x6d8 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0 0x6d9 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0 0x6da 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 0 0x6db 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 0 0x6dc 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0 0x6dd 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0 0x6de 1 0 1 ADDR_MASK 1 31 mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 0 0x6df 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 0 0x6e0 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 0 0x6e1 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 0 0x6e2 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0 0x6e3 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0 0x6e4 1 0 1 BANK5 0 4 mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0 0x6e5 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0 0x6e6 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0 0x6e7 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0 0x6e8 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA3_ADDRDEC2_RM_SEL_CS01 0 0x6e9 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC2_RM_SEL_CS23 0 0x6ea 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 0 0x6eb 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 0 0x6ec 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0 0x6ed 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0 0x6ee 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA3_IO_RD_CLI2GRP_MAP0 0 0x715 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_IO_RD_CLI2GRP_MAP1 0 0x716 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_IO_WR_CLI2GRP_MAP0 0 0x717 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA3_IO_WR_CLI2GRP_MAP1 0 0x718 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA3_IO_RD_COMBINE_FLUSH 0 0x719 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA3_IO_WR_COMBINE_FLUSH 0 0x71a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA3_IO_GROUP_BURST 0 0x71b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA3_IO_RD_PRI_AGE 0 0x71c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_IO_WR_PRI_AGE 0 0x71d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA3_IO_RD_PRI_QUEUING 0 0x71e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_IO_WR_PRI_QUEUING 0 0x71f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA3_IO_RD_PRI_FIXED 0 0x720 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_IO_WR_PRI_FIXED 0 0x721 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA3_IO_RD_PRI_URGENCY 0 0x722 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_IO_WR_PRI_URGENCY 0 0x723 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA3_IO_RD_PRI_URGENCY_MASKING 0 0x724 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA3_IO_WR_PRI_URGENCY_MASKING 0 0x725 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA3_IO_RD_PRI_QUANT_PRI1 0 0x726 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_IO_RD_PRI_QUANT_PRI2 0 0x727 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_IO_RD_PRI_QUANT_PRI3 0 0x728 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_IO_WR_PRI_QUANT_PRI1 0 0x729 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_IO_WR_PRI_QUANT_PRI2 0 0x72a 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_IO_WR_PRI_QUANT_PRI3 0 0x72b 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA3_SDP_ARB_DRAM 0 0x72c 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA3_SDP_ARB_GMI 0 0x72d 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA3_SDP_ARB_FINAL 0 0x72e 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA3_SDP_DRAM_PRIORITY 0 0x72f 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA3_SDP_GMI_PRIORITY 0 0x730 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA3_SDP_IO_PRIORITY 0 0x731 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA3_SDP_CREDITS 0 0x732 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA3_SDP_TAG_RESERVE0 0 0x733 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA3_SDP_TAG_RESERVE1 0 0x734 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA3_SDP_VCC_RESERVE0 0 0x735 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA3_SDP_VCC_RESERVE1 0 0x736 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA3_SDP_VCD_RESERVE0 0 0x737 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA3_SDP_VCD_RESERVE1 0 0x738 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA3_SDP_REQ_CNTL 0 0x739 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA3_MISC 0 0x73a 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA3_LATENCY_SAMPLING 0 0x73b 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA3_PERFCOUNTER_LO 0 0x73c 1 0 1 COUNTER_LO 0 31 mmMMEA3_PERFCOUNTER_HI 0 0x73d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA3_PERFCOUNTER0_CFG 0 0x73e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA3_PERFCOUNTER1_CFG 0 0x73f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA3_PERFCOUNTER_RSLT_CNTL 0 0x740 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA3_EDC_CNT 0 0x746 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA3_EDC_CNT2 0 0x747 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA3_DSM_CNTL 0 0x748 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA3_DSM_CNTLA 0 0x749 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA3_DSM_CNTLB 0 0x74a 0 0 1 mmMMEA3_DSM_CNTL2 0 0x74b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA3_DSM_CNTL2A 0 0x74c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA3_DSM_CNTL2B 0 0x74d 0 0 1 mmMMEA3_CGTT_CLK_CTRL 0 0x74f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA3_EDC_MODE 0 0x750 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA3_ERR_STATUS 0 0x751 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA3_MISC2 0 0x752 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA3_ADDRDEC_SELECT 0 0x753 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA3_EDC_CNT3 0 0x754 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA4_DRAM_RD_CLI2GRP_MAP0 0 0x780 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_DRAM_RD_CLI2GRP_MAP1 0 0x781 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_DRAM_WR_CLI2GRP_MAP0 0 0x782 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_DRAM_WR_CLI2GRP_MAP1 0 0x783 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_DRAM_RD_GRP2VC_MAP 0 0x784 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA4_DRAM_WR_GRP2VC_MAP 0 0x785 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA4_DRAM_RD_LAZY 0 0x786 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA4_DRAM_WR_LAZY 0 0x787 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA4_DRAM_RD_CAM_CNTL 0 0x788 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA4_DRAM_WR_CAM_CNTL 0 0x789 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA4_DRAM_PAGE_BURST 0 0x78a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA4_DRAM_RD_PRI_AGE 0 0x78b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_DRAM_WR_PRI_AGE 0 0x78c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_DRAM_RD_PRI_QUEUING 0 0x78d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_DRAM_WR_PRI_QUEUING 0 0x78e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_DRAM_RD_PRI_FIXED 0 0x78f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_DRAM_WR_PRI_FIXED 0 0x790 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_DRAM_RD_PRI_URGENCY 0 0x791 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_DRAM_WR_PRI_URGENCY 0 0x792 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 0 0x793 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 0 0x794 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 0 0x795 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 0 0x796 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 0 0x797 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 0 0x798 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_RD_CLI2GRP_MAP0 0 0x799 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_GMI_RD_CLI2GRP_MAP1 0 0x79a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_GMI_WR_CLI2GRP_MAP0 0 0x79b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_GMI_WR_CLI2GRP_MAP1 0 0x79c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_GMI_RD_GRP2VC_MAP 0 0x79d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA4_GMI_WR_GRP2VC_MAP 0 0x79e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA4_GMI_RD_LAZY 0 0x79f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA4_GMI_WR_LAZY 0 0x7a0 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA4_GMI_RD_CAM_CNTL 0 0x7a1 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA4_GMI_WR_CAM_CNTL 0 0x7a2 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA4_GMI_PAGE_BURST 0 0x7a3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA4_GMI_RD_PRI_AGE 0 0x7a4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_GMI_WR_PRI_AGE 0 0x7a5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_GMI_RD_PRI_QUEUING 0 0x7a6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_GMI_WR_PRI_QUEUING 0 0x7a7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_GMI_RD_PRI_FIXED 0 0x7a8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_GMI_WR_PRI_FIXED 0 0x7a9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_GMI_RD_PRI_URGENCY 0 0x7aa 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_GMI_WR_PRI_URGENCY 0 0x7ab 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_GMI_RD_PRI_URGENCY_MASKING 0 0x7ac 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA4_GMI_WR_PRI_URGENCY_MASKING 0 0x7ad 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA4_GMI_RD_PRI_QUANT_PRI1 0 0x7ae 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_RD_PRI_QUANT_PRI2 0 0x7af 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_RD_PRI_QUANT_PRI3 0 0x7b0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_WR_PRI_QUANT_PRI1 0 0x7b1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_WR_PRI_QUANT_PRI2 0 0x7b2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_GMI_WR_PRI_QUANT_PRI3 0 0x7b3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_ADDRNORM_BASE_ADDR0 0 0x7b4 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR0 0 0x7b5 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_BASE_ADDR1 0 0x7b6 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR1 0 0x7b7 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_OFFSET_ADDR1 0 0x7b8 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA4_ADDRNORM_BASE_ADDR2 0 0x7b9 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR2 0 0x7ba 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_BASE_ADDR3 0 0x7bb 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR3 0 0x7bc 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_OFFSET_ADDR3 0 0x7bd 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA4_ADDRNORM_BASE_ADDR4 0 0x7be 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR4 0 0x7bf 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_BASE_ADDR5 0 0x7c0 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA4_ADDRNORM_LIMIT_ADDR5 0 0x7c1 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA4_ADDRNORM_OFFSET_ADDR5 0 0x7c2 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA4_ADDRNORMDRAM_HOLE_CNTL 0 0x7c3 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA4_ADDRNORMGMI_HOLE_CNTL 0 0x7c4 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x7c5 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x7c6 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA4_ADDRDEC_BANK_CFG 0 0x7c7 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA4_ADDRDEC_MISC_CFG 0 0x7c8 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x7c9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x7ca 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x7cb 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x7cc 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x7cd 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x7ce 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC 0 0x7cf 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 0 0x7d0 1 0 1 BANK_XOR 0 5 mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 0 0x7d1 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 0 0x7d2 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0 0x7d3 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 0 0x7d4 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 0 0x7d5 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 0 0x7d6 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 0 0x7d7 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 0 0x7d8 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 0 0x7d9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_PC 0 0x7da 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 0 0x7db 1 0 1 BANK_XOR 0 5 mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 0 0x7dc 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 0 0x7dd 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA4_ADDRDECGMI_HARVEST_ENABLE 0 0x7de 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 0 0x7df 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 0 0x7e0 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 0 0x7e1 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 0 0x7e2 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0 0x7e3 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0 0x7e4 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0 0x7e5 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0 0x7e6 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 0 0x7e7 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 0 0x7e8 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0 0x7e9 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0 0x7ea 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 0 0x7eb 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 0 0x7ec 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 0 0x7ed 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 0 0x7ee 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0 0x7ef 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0 0x7f0 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0 0x7f1 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0 0x7f2 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0 0x7f3 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0 0x7f4 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC0_RM_SEL_CS01 0 0x7f5 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC0_RM_SEL_CS23 0 0x7f6 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 0 0x7f7 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 0 0x7f8 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 0 0x7f9 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 0 0x7fa 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 0 0x7fb 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 0 0x7fc 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0 0x7fd 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0 0x7fe 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0 0x7ff 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0 0x800 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 0 0x801 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 0 0x802 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0 0x803 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0 0x804 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 0 0x805 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 0 0x806 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 0 0x807 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 0 0x808 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0 0x809 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0 0x80a 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0 0x80b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0 0x80c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0 0x80d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0 0x80e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC1_RM_SEL_CS01 0 0x80f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC1_RM_SEL_CS23 0 0x810 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 0 0x811 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 0 0x812 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 0 0x813 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 0 0x814 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 0 0x815 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 0 0x816 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0 0x817 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0 0x818 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0 0x819 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0 0x81a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 0 0x81b 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 0 0x81c 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0 0x81d 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0 0x81e 1 0 1 ADDR_MASK 1 31 mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 0 0x81f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 0 0x820 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 0 0x821 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 0 0x822 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0 0x823 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0 0x824 1 0 1 BANK5 0 4 mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0 0x825 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0 0x826 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0 0x827 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0 0x828 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA4_ADDRDEC2_RM_SEL_CS01 0 0x829 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC2_RM_SEL_CS23 0 0x82a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 0 0x82b 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 0 0x82c 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0 0x82d 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0 0x82e 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA4_IO_RD_CLI2GRP_MAP0 0 0x855 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_IO_RD_CLI2GRP_MAP1 0 0x856 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_IO_WR_CLI2GRP_MAP0 0 0x857 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA4_IO_WR_CLI2GRP_MAP1 0 0x858 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA4_IO_RD_COMBINE_FLUSH 0 0x859 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA4_IO_WR_COMBINE_FLUSH 0 0x85a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA4_IO_GROUP_BURST 0 0x85b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA4_IO_RD_PRI_AGE 0 0x85c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_IO_WR_PRI_AGE 0 0x85d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA4_IO_RD_PRI_QUEUING 0 0x85e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_IO_WR_PRI_QUEUING 0 0x85f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA4_IO_RD_PRI_FIXED 0 0x860 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_IO_WR_PRI_FIXED 0 0x861 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA4_IO_RD_PRI_URGENCY 0 0x862 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_IO_WR_PRI_URGENCY 0 0x863 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA4_IO_RD_PRI_URGENCY_MASKING 0 0x864 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA4_IO_WR_PRI_URGENCY_MASKING 0 0x865 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA4_IO_RD_PRI_QUANT_PRI1 0 0x866 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_IO_RD_PRI_QUANT_PRI2 0 0x867 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_IO_RD_PRI_QUANT_PRI3 0 0x868 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_IO_WR_PRI_QUANT_PRI1 0 0x869 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_IO_WR_PRI_QUANT_PRI2 0 0x86a 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_IO_WR_PRI_QUANT_PRI3 0 0x86b 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA4_SDP_ARB_DRAM 0 0x86c 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA4_SDP_ARB_GMI 0 0x86d 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA4_SDP_ARB_FINAL 0 0x86e 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA4_SDP_DRAM_PRIORITY 0 0x86f 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA4_SDP_GMI_PRIORITY 0 0x870 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA4_SDP_IO_PRIORITY 0 0x871 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA4_SDP_CREDITS 0 0x872 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA4_SDP_TAG_RESERVE0 0 0x873 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA4_SDP_TAG_RESERVE1 0 0x874 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA4_SDP_VCC_RESERVE0 0 0x875 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA4_SDP_VCC_RESERVE1 0 0x876 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA4_SDP_VCD_RESERVE0 0 0x877 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA4_SDP_VCD_RESERVE1 0 0x878 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA4_SDP_REQ_CNTL 0 0x879 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA4_MISC 0 0x87a 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA4_LATENCY_SAMPLING 0 0x87b 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA4_PERFCOUNTER_LO 0 0x87c 1 0 1 COUNTER_LO 0 31 mmMMEA4_PERFCOUNTER_HI 0 0x87d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA4_PERFCOUNTER0_CFG 0 0x87e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA4_PERFCOUNTER1_CFG 0 0x87f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA4_PERFCOUNTER_RSLT_CNTL 0 0x880 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA4_EDC_CNT 0 0x886 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA4_EDC_CNT2 0 0x887 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA4_DSM_CNTL 0 0x888 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA4_DSM_CNTLA 0 0x889 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA4_DSM_CNTLB 0 0x88a 0 0 1 mmMMEA4_DSM_CNTL2 0 0x88b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA4_DSM_CNTL2A 0 0x88c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA4_DSM_CNTL2B 0 0x88d 0 0 1 mmMMEA4_CGTT_CLK_CTRL 0 0x88f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA4_EDC_MODE 0 0x890 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA4_ERR_STATUS 0 0x891 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA4_MISC2 0 0x892 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA4_ADDRDEC_SELECT 0 0x893 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA4_EDC_CNT3 0 0x894 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmPCTL0_CTRL 0 0x8c0 16 0 1 PG_ENABLE 0 0 ALLOW_DEEP_SLEEP_MODE 1 3 STCTRL_RSMU_IDLE_THRESHOLD 4 10 STCTRL_DAGB_IDLE_THRESHOLD 11 15 STCTRL_IGNORE_PROTECTION_FAULT 16 16 OVR_EA0_SDP_PARTACK 17 17 OVR_EA1_SDP_PARTACK 18 18 OVR_EA2_SDP_PARTACK 19 19 OVR_EA3_SDP_PARTACK 20 20 OVR_EA4_SDP_PARTACK 21 21 OVR_EA0_SDP_FULLACK 22 22 OVR_EA1_SDP_FULLACK 23 23 OVR_EA2_SDP_FULLACK 24 24 OVR_EA3_SDP_FULLACK 25 25 OVR_EA4_SDP_FULLACK 26 26 PGFSM_CMD_STATUS 27 28 mmPCTL0_MMHUB_DEEPSLEEP_IB 0 0x8c1 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 SETCLEAR 31 31 mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0 0x8c2 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0 0x8c3 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_PG_IGNORE_DEEPSLEEP 0 0x8c4 19 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 ALLIPS 18 18 mmPCTL0_PG_IGNORE_DEEPSLEEP_IB 0 0x8c5 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 ALLIPS 17 17 mmPCTL0_SLICE0_CFG_DAGB_BUSY 0 0x8c6 1 0 1 DB_LNCFG 0 31 mmPCTL0_SLICE0_CFG_DS_ALLOW 0 0x8c7 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE0_CFG_DS_ALLOW_IB 0 0x8c8 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE1_CFG_DAGB_BUSY 0 0x8c9 1 0 1 DB_LNCFG 0 31 mmPCTL0_SLICE1_CFG_DS_ALLOW 0 0x8ca 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE1_CFG_DS_ALLOW_IB 0 0x8cb 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE2_CFG_DAGB_BUSY 0 0x8cc 1 0 1 DB_LNCFG 0 31 mmPCTL0_SLICE2_CFG_DS_ALLOW 0 0x8cd 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE2_CFG_DS_ALLOW_IB 0 0x8ce 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE3_CFG_DAGB_BUSY 0 0x8cf 1 0 1 DB_LNCFG 0 31 mmPCTL0_SLICE3_CFG_DS_ALLOW 0 0x8d0 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE3_CFG_DS_ALLOW_IB 0 0x8d1 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE4_CFG_DAGB_BUSY 0 0x8d2 1 0 1 DB_LNCFG 0 31 mmPCTL0_SLICE4_CFG_DS_ALLOW 0 0x8d3 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_SLICE4_CFG_DS_ALLOW_IB 0 0x8d4 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL0_UTCL2_MISC 0 0x8d5 6 0 1 CRITICAL_REGS_LOCK 11 11 TILE_IDLE_THRESHOLD 12 14 RENG_MEM_LS_ENABLE 15 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_SLICE0_MISC 0 0x8d6 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_SLICE1_MISC 0 0x8d7 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_SLICE2_MISC 0 0x8d8 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_SLICE3_MISC 0 0x8d9 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_SLICE4_MISC 0 0x8da 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL0_UTCL2_RENG_EXECUTE 0 0x8db 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 12 RENG_EXECUTE_END_PTR 13 23 mmPCTL0_SLICE0_RENG_EXECUTE 0 0x8dc 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL0_SLICE1_RENG_EXECUTE 0 0x8dd 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL0_SLICE2_RENG_EXECUTE 0 0x8de 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL0_SLICE3_RENG_EXECUTE 0 0x8df 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL0_SLICE4_RENG_EXECUTE 0 0x8e0 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL0_UTCL2_RENG_RAM_INDEX 0 0x8e1 1 0 1 RENG_RAM_INDEX 0 10 mmPCTL0_UTCL2_RENG_RAM_DATA 0 0x8e2 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_SLICE0_RENG_RAM_INDEX 0 0x8e3 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL0_SLICE0_RENG_RAM_DATA 0 0x8e4 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_SLICE1_RENG_RAM_INDEX 0 0x8e5 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL0_SLICE1_RENG_RAM_DATA 0 0x8e6 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_SLICE2_RENG_RAM_INDEX 0 0x8e7 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL0_SLICE2_RENG_RAM_DATA 0 0x8e8 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_SLICE3_RENG_RAM_INDEX 0 0x8e9 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL0_SLICE3_RENG_RAM_DATA 0 0x8ea 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_SLICE4_RENG_RAM_INDEX 0 0x8eb 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL0_SLICE4_RENG_RAM_DATA 0 0x8ec 1 0 1 RENG_RAM_DATA 0 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0 0x8ed 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0 0x8ee 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0 0x8ef 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0 0x8f0 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0 0x8f1 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x8f2 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x8f3 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0 0x8f4 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0 0x8f5 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0 0x8f6 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0 0x8f7 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0 0x8f8 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x8f9 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x8fa 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0 0x8fb 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0 0x8fc 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0 0x8fd 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0 0x8fe 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0 0x8ff 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x900 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x901 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0 0x902 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0 0x903 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0 0x904 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0 0x905 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0 0x906 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x907 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x908 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0 0x909 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0 0x90a 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0 0x90b 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0 0x90c 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0 0x90d 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x90e 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x90f 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0 0x910 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0 0x911 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0 0x912 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0 0x913 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0 0x914 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x915 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x916 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmVML1_0_MC_VM_MX_L1_TLB0_STATUS 0 0x948 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB1_STATUS 0 0x949 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB2_STATUS 0 0x94a 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB3_STATUS 0 0x94b 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB4_STATUS 0 0x94c 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB5_STATUS 0 0x94d 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB6_STATUS 0 0x94e 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_0_MC_VM_MX_L1_TLB7_STATUS 0 0x94f 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 0 0x960 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 0 0x961 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 0 0x962 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 0 0x963 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0 0x964 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 0 0x970 1 0 1 COUNTER_LO 0 31 mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 0 0x971 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATCL2_0_ATC_L2_CNTL 0 0x980 10 0 1 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS 8 9 NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS 11 12 NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 14 14 NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 15 15 CACHE_INVALIDATE_MODE 16 18 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 19 19 mmATCL2_0_ATC_L2_CNTL2 0 0x981 8 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 L2_BIGK_FRAGMENT_SIZE 21 26 L2_4K_BIGK_SWAP_ENABLE 27 27 mmATCL2_0_ATC_L2_CACHE_DATA0 0 0x984 4 0 1 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 22 VIRTUAL_PAGE_ADDRESS_HIGH 23 26 mmATCL2_0_ATC_L2_CACHE_DATA1 0 0x985 1 0 1 VIRTUAL_PAGE_ADDRESS_LOW 0 31 mmATCL2_0_ATC_L2_CACHE_DATA2 0 0x986 1 0 1 PHYSICAL_PAGE_ADDRESS 0 31 mmATCL2_0_ATC_L2_CNTL3 0 0x987 3 0 1 DELAY_SEND_INVALIDATION_REQUEST 0 2 ATS_REQUEST_CREDIT_MINUS1 3 8 COMPCLKREQ_OFF_HYSTERESIS 9 11 mmATCL2_0_ATC_L2_STATUS 0 0x988 2 0 1 BUSY 0 0 PARITY_ERROR_INFO 1 30 mmATCL2_0_ATC_L2_STATUS2 0 0x989 2 0 1 IFIFO_NON_FATAL_PARITY_ERROR_INFO 0 7 IFIFO_FATAL_PARITY_ERROR_INFO 8 15 mmATCL2_0_ATC_L2_STATUS3 0 0x98a 2 0 1 BUSY 0 0 PARITY_ERROR_INFO 1 30 mmATCL2_0_ATC_L2_MISC_CG 0 0x98b 3 0 1 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmATCL2_0_ATC_L2_MEM_POWER_LS 0 0x98c 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmATCL2_0_ATC_L2_CGTT_CLK_CTRL 0 0x98d 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 0 0x98e 1 0 1 INDEX 0 7 mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 0 0x98f 1 0 1 INDEX 0 7 mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 0 0x990 9 0 1 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 0 0x991 9 0 1 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 mmATCL2_0_ATC_L2_CNTL4 0 0x992 2 0 1 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 0 9 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 10 19 mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 0 0x993 1 0 1 GROUP_RT_CLASS 0 31 mmVML2PF0_VM_L2_CNTL 0 0x9c0 14 0 1 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 mmVML2PF0_VM_L2_CNTL2 0 0x9c1 7 0 1 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmVML2PF0_VM_L2_CNTL3 0 0x9c2 11 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmVML2PF0_VM_L2_STATUS 0 0x9c3 7 0 1 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 0 0x9c4 3 0 1 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x9c5 1 0 1 DUMMY_PAGE_ADDR_LO32 0 31 mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x9c6 1 0 1 DUMMY_PAGE_ADDR_HI4 0 3 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL 0 0x9c7 17 0 1 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 0 0x9c8 5 0 1 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x9c9 1 0 1 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x9ca 1 0 1 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS 0 0x9cb 10 0 1 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 28 mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x9cc 1 0 1 LOGICAL_PAGE_ADDR_LO32 0 31 mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x9cd 1 0 1 LOGICAL_PAGE_ADDR_HI4 0 3 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x9ce 1 0 1 PHYSICAL_PAGE_ADDR_LO32 0 31 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x9cf 1 0 1 PHYSICAL_PAGE_ADDR_HI4 0 3 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x9d1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x9d2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x9d3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x9d4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x9d5 1 0 1 PHYSICAL_PAGE_OFFSET_LO32 0 31 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x9d6 1 0 1 PHYSICAL_PAGE_OFFSET_HI4 0 3 mmVML2PF0_VM_L2_CNTL4 0 0x9d7 6 0 1 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES 0 0x9d8 32 0 1 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 0 0x9d9 5 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 0 0x9da 5 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVML2PF0_VM_L2_CACHE_PARITY_CNTL 0 0x9db 9 0 1 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 mmVML2PF0_VM_L2_CGTT_CLK_CTRL 0 0x9de 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVML2VC0_VM_CONTEXT0_CNTL 0 0xa00 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT1_CNTL 0 0xa01 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT2_CNTL 0 0xa02 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT3_CNTL 0 0xa03 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT4_CNTL 0 0xa04 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT5_CNTL 0 0xa05 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT6_CNTL 0 0xa06 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT7_CNTL 0 0xa07 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT8_CNTL 0 0xa08 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT9_CNTL 0 0xa09 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT10_CNTL 0 0xa0a 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT11_CNTL 0 0xa0b 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT12_CNTL 0 0xa0c 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT13_CNTL 0 0xa0d 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT14_CNTL 0 0xa0e 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXT15_CNTL 0 0xa0f 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC0_VM_CONTEXTS_DISABLE 0 0xa10 16 0 1 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmVML2VC0_VM_INVALIDATE_ENG0_SEM 0 0xa11 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG1_SEM 0 0xa12 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG2_SEM 0 0xa13 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG3_SEM 0 0xa14 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG4_SEM 0 0xa15 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG5_SEM 0 0xa16 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG6_SEM 0 0xa17 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG7_SEM 0 0xa18 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG8_SEM 0 0xa19 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG9_SEM 0 0xa1a 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG10_SEM 0 0xa1b 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG11_SEM 0 0xa1c 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG12_SEM 0 0xa1d 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG13_SEM 0 0xa1e 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG14_SEM 0 0xa1f 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG15_SEM 0 0xa20 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG16_SEM 0 0xa21 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG17_SEM 0 0xa22 1 0 1 SEMAPHORE 0 0 mmVML2VC0_VM_INVALIDATE_ENG0_REQ 0 0xa23 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG1_REQ 0 0xa24 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG2_REQ 0 0xa25 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG3_REQ 0 0xa26 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG4_REQ 0 0xa27 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG5_REQ 0 0xa28 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG6_REQ 0 0xa29 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG7_REQ 0 0xa2a 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG8_REQ 0 0xa2b 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG9_REQ 0 0xa2c 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG10_REQ 0 0xa2d 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG11_REQ 0 0xa2e 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG12_REQ 0 0xa2f 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG13_REQ 0 0xa30 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG14_REQ 0 0xa31 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG15_REQ 0 0xa32 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG16_REQ 0 0xa33 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG17_REQ 0 0xa34 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC0_VM_INVALIDATE_ENG0_ACK 0 0xa35 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG1_ACK 0 0xa36 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG2_ACK 0 0xa37 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG3_ACK 0 0xa38 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG4_ACK 0 0xa39 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG5_ACK 0 0xa3a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG6_ACK 0 0xa3b 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG7_ACK 0 0xa3c 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG8_ACK 0 0xa3d 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG9_ACK 0 0xa3e 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG10_ACK 0 0xa3f 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG11_ACK 0 0xa40 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG12_ACK 0 0xa41 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG13_ACK 0 0xa42 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG14_ACK 0 0xa43 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG15_ACK 0 0xa44 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG16_ACK 0 0xa45 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG17_ACK 0 0xa46 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0xa47 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0xa48 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0xa49 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0xa4a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0xa4b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0xa4c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0xa4d 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0xa4e 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0xa4f 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0xa50 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0xa51 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0xa52 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0xa53 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0xa54 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0xa55 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0xa56 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0xa57 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0xa58 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0xa59 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0xa5a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0xa5b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0xa5c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0xa5d 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0xa5e 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0xa5f 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0xa60 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0xa61 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0xa62 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0xa63 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0xa64 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0xa65 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0xa66 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0xa67 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0xa68 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0xa69 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0xa6a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0xa6b 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0xa6c 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0xa6d 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0xa6e 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0xa6f 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0xa70 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0xa71 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0xa72 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0xa73 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0xa74 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0xa75 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0xa76 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0xa77 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0xa78 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0xa79 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0xa7a 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0xa7b 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0xa7c 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0xa7d 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0xa7e 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0xa7f 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0xa80 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0xa81 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0xa82 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0xa83 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0xa84 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0xa85 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0xa86 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0xa87 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0xa88 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0xa89 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0xa8a 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0xa8b 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0xa8c 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0xa8d 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0xa8e 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0xa8f 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0xa90 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0xa91 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0xa92 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0xa93 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0xa94 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0xa95 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0xa96 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0xa97 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0xa98 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0xa99 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0xa9a 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0xa9b 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0xa9c 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0xa9d 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0xa9e 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0xa9f 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0xaa0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0xaa1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0xaa2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0xaa3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0xaa4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0xaa5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0xaa6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0xaa7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0xaa8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0xaa9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0xaaa 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0xaab 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0xaac 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0xaad 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0xaae 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0xaaf 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0xab0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0xab1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0xab2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0xab3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0xab4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0xab5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0xab6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0xab7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0xab8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0xab9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0xaba 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0xabb 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0xabc 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0xabd 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0xabe 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0xabf 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0xac0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0xac1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0xac2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0xac3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0xac4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0xac5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0xac6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0xac7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0xac8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0xac9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0xaca 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVMSHAREDPF0_MC_VM_NB_MMIOBASE 0 0xae4 1 0 1 MMIOBASE 0 31 mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT 0 0xae5 1 0 1 MMIOLIMIT 0 31 mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL 0 0xae6 1 0 1 MMIOENABLE 23 23 mmVMSHAREDPF0_MC_VM_NB_PCI_ARB 0 0xae7 1 0 1 VGA_HOLE 3 3 mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 0 0xae8 1 0 1 TOP_OF_DRAM 23 31 mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 0 0xae9 2 0 1 ENABLE 0 0 LOWER_TOM2 23 31 mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 0 0xaea 1 0 1 UPPER_TOM2 0 11 mmVMSHAREDPF0_MC_VM_FB_OFFSET 0 0xaeb 1 0 1 FB_OFFSET 0 23 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0xaec 1 0 1 PHYSICAL_PAGE_NUMBER_LSB 0 31 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0xaed 1 0 1 PHYSICAL_PAGE_NUMBER_MSB 0 3 mmVMSHAREDPF0_MC_VM_STEERING 0 0xaee 1 0 1 DEFAULT_STEERING 0 1 mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 0 0xaef 2 0 1 VF 0 15 PF 31 31 mmVMSHAREDPF0_MC_MEM_POWER_LS 0 0xaf0 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0xaf1 1 0 1 ADDRESS 0 19 mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0xaf2 1 0 1 ADDRESS 0 19 mmVMSHAREDPF0_MC_VM_APT_CNTL 0 0xaf3 2 0 1 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 0 0xaf4 1 0 1 ADDRESS 0 19 mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 0 0xaf5 1 0 1 ADDRESS 0 19 mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0xaf6 1 0 1 LOCK 0 0 mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 0 0xaf7 2 0 1 PF_LFB_REGION 0 3 PF_MAX_REGION 4 7 mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 0 0xaf8 1 0 1 PF_LFB_SIZE 0 16 mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0 0xaf9 1 0 1 ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE 0 0 mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE 0 0xb00 1 0 1 FB_BASE 0 23 mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP 0 0xb01 1 0 1 FB_TOP 0 23 mmVMSHAREDVC0_MC_VM_AGP_TOP 0 0xb02 1 0 1 AGP_TOP 0 23 mmVMSHAREDVC0_MC_VM_AGP_BOT 0 0xb03 1 0 1 AGP_BOT 0 23 mmVMSHAREDVC0_MC_VM_AGP_BASE 0 0xb04 1 0 1 AGP_BASE 0 23 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0xb05 1 0 1 LOGICAL_ADDR 0 29 mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0xb06 1 0 1 LOGICAL_ADDR 0 29 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0 0xb07 7 0 1 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 12 ATC_EN 13 13 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 0 0xb20 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 0 0xb21 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 0 0xb22 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 0 0xb23 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 0 0xb24 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 0 0xb25 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 0 0xb26 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 0 0xb27 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 0 0xb28 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 0 0xb29 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 0 0xb2a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 0 0xb2b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 0 0xb2c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 0 0xb2d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 0 0xb2e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 0 0xb2f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 0 0xb30 1 0 1 MARC_EN 8 8 mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 0 0xb31 1 0 1 MARC_BASE_LO_0 12 31 mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 0 0xb32 1 0 1 MARC_BASE_LO_1 12 31 mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 0 0xb33 1 0 1 MARC_BASE_LO_2 12 31 mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 0 0xb34 1 0 1 MARC_BASE_LO_3 12 31 mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 0 0xb35 1 0 1 MARC_BASE_HI_0 0 19 mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 0 0xb36 1 0 1 MARC_BASE_HI_1 0 19 mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 0 0xb37 1 0 1 MARC_BASE_HI_2 0 19 mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 0 0xb38 1 0 1 MARC_BASE_HI_3 0 19 mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 0 0xb39 3 0 1 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 0 0xb3a 3 0 1 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 0 0xb3b 3 0 1 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 0 0xb3c 3 0 1 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 0 0xb3d 1 0 1 MARC_RELOC_HI_0 0 19 mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 0 0xb3e 1 0 1 MARC_RELOC_HI_1 0 19 mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 0 0xb3f 1 0 1 MARC_RELOC_HI_2 0 19 mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 0 0xb40 1 0 1 MARC_RELOC_HI_3 0 19 mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 0 0xb41 1 0 1 MARC_LEN_LO_0 12 31 mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 0 0xb42 1 0 1 MARC_LEN_LO_1 12 31 mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 0 0xb43 1 0 1 MARC_LEN_LO_2 12 31 mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 0 0xb44 1 0 1 MARC_LEN_LO_3 12 31 mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 0 0xb45 1 0 1 MARC_LEN_HI_0 0 19 mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 0 0xb46 1 0 1 MARC_LEN_HI_1 0 19 mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 0 0xb47 1 0 1 MARC_LEN_HI_2 0 19 mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 0 0xb48 1 0 1 MARC_LEN_HI_3 0 19 mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 0 0xb49 1 0 1 IOMMUEN 0 0 mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0 0xb4a 1 0 1 PERFOPTEN 13 13 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL 0 0xb4b 2 0 1 STU 16 20 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 0 0xb4c 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 0 0xb4d 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 0 0xb4e 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 0 0xb4f 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 0 0xb50 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 0 0xb51 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 0 0xb52 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 0 0xb53 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 0 0xb54 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 0 0xb55 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 0 0xb56 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 0 0xb57 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 0 0xb58 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 0 0xb59 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 0 0xb5a 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 0 0xb5b 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 0 0xb5c 6 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 0 0xb5d 2 0 1 VFID 0 3 VF 31 31 mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 0 0xb5e 17 0 1 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_PF 31 31 mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 0 0xb70 1 0 1 COUNTER_LO 0 31 mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 0 0xb71 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 0 0xb74 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 0 0xb75 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 0 0xb76 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 0 0xb80 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 0 0xb81 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 0 0xb82 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 0 0xb83 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 0 0xb84 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 0 0xb85 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 0 0xb86 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 0 0xb87 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0xb88 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO 0 0xb90 1 0 1 COUNTER_LO 0 31 mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI 0 0xb91 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB5_RDCLI0 0 0x3000 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI1 0 0x3001 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI2 0 0x3002 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI3 0 0x3003 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI4 0 0x3004 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI5 0 0x3005 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI6 0 0x3006 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI7 0 0x3007 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI8 0 0x3008 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI9 0 0x3009 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI10 0 0x300a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI11 0 0x300b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI12 0 0x300c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI13 0 0x300d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI14 0 0x300e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RDCLI15 0 0x300f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_RD_CNTL 0 0x3010 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB5_RD_GMI_CNTL 0 0x3011 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB5_RD_ADDR_DAGB 0 0x3012 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0 0x3013 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x3014 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB5_RD_CGTT_CLK_CTRL 0 0x3015 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0 0x3016 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0 0x3017 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 0 0x3018 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0 0x3019 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 0 0x301a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0 0x301b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_RD_VC0_CNTL 0 0x301c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC1_CNTL 0 0x301d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC2_CNTL 0 0x301e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC3_CNTL 0 0x301f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC4_CNTL 0 0x3020 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC5_CNTL 0 0x3021 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC6_CNTL 0 0x3022 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_VC7_CNTL 0 0x3023 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_RD_CNTL_MISC 0 0x3024 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB5_RD_TLB_CREDIT 0 0x3025 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB5_RDCLI_ASK_PENDING 0 0x3026 1 0 1 BUSY 0 31 mmDAGB5_RDCLI_GO_PENDING 0 0x3027 1 0 1 BUSY 0 31 mmDAGB5_RDCLI_GBLSEND_PENDING 0 0x3028 1 0 1 BUSY 0 31 mmDAGB5_RDCLI_TLB_PENDING 0 0x3029 1 0 1 BUSY 0 31 mmDAGB5_RDCLI_OARB_PENDING 0 0x302a 1 0 1 BUSY 0 31 mmDAGB5_RDCLI_OSD_PENDING 0 0x302b 1 0 1 BUSY 0 31 mmDAGB5_WRCLI0 0 0x302c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI1 0 0x302d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI2 0 0x302e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI3 0 0x302f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI4 0 0x3030 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI5 0 0x3031 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI6 0 0x3032 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI7 0 0x3033 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI8 0 0x3034 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI9 0 0x3035 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI10 0 0x3036 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI11 0 0x3037 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI12 0 0x3038 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI13 0 0x3039 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI14 0 0x303a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WRCLI15 0 0x303b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB5_WR_CNTL 0 0x303c 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB5_WR_GMI_CNTL 0 0x303d 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB5_WR_ADDR_DAGB 0 0x303e 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0 0x303f 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x3040 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB5_WR_CGTT_CLK_CTRL 0 0x3041 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0 0x3042 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0 0x3043 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 0 0x3044 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0 0x3045 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 0 0x3046 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0 0x3047 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_WR_DATA_DAGB 0 0x3048 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB5_WR_DATA_DAGB_MAX_BURST0 0 0x3049 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0 0x304a 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB5_WR_DATA_DAGB_MAX_BURST1 0 0x304b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0 0x304c 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB5_WR_VC0_CNTL 0 0x304d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC1_CNTL 0 0x304e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC2_CNTL 0 0x304f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC3_CNTL 0 0x3050 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC4_CNTL 0 0x3051 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC5_CNTL 0 0x3052 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC6_CNTL 0 0x3053 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_VC7_CNTL 0 0x3054 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB5_WR_CNTL_MISC 0 0x3055 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB5_WR_TLB_CREDIT 0 0x3056 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB5_WR_DATA_CREDIT 0 0x3057 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB5_WR_MISC_CREDIT 0 0x3058 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB5_WRCLI_ASK_PENDING 0 0x305d 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_GO_PENDING 0 0x305e 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_GBLSEND_PENDING 0 0x305f 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_TLB_PENDING 0 0x3060 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_OARB_PENDING 0 0x3061 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_OSD_PENDING 0 0x3062 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_DBUS_ASK_PENDING 0 0x3063 1 0 1 BUSY 0 31 mmDAGB5_WRCLI_DBUS_GO_PENDING 0 0x3064 1 0 1 BUSY 0 31 mmDAGB5_DAGB_DLY 0 0x3065 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB5_CNTL_MISC 0 0x3066 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB5_CNTL_MISC2 0 0x3067 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB5_FIFO_EMPTY 0 0x3068 1 0 1 EMPTY 0 23 mmDAGB5_FIFO_FULL 0 0x3069 1 0 1 FULL 0 22 mmDAGB5_WR_CREDITS_FULL 0 0x306a 1 0 1 FULL 0 28 mmDAGB5_RD_CREDITS_FULL 0 0x306b 1 0 1 FULL 0 17 mmDAGB5_PERFCOUNTER_LO 0 0x306c 1 0 1 COUNTER_LO 0 31 mmDAGB5_PERFCOUNTER_HI 0 0x306d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB5_PERFCOUNTER0_CFG 0 0x306e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB5_PERFCOUNTER1_CFG 0 0x306f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB5_PERFCOUNTER2_CFG 0 0x3070 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB5_PERFCOUNTER_RSLT_CNTL 0 0x3071 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB5_RESERVE0 0 0x3072 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE1 0 0x3073 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE2 0 0x3074 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE3 0 0x3075 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE4 0 0x3076 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE5 0 0x3077 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE6 0 0x3078 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE7 0 0x3079 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE8 0 0x307a 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE9 0 0x307b 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE10 0 0x307c 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE11 0 0x307d 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE12 0 0x307e 1 0 1 RESERVE 0 31 mmDAGB5_RESERVE13 0 0x307f 1 0 1 RESERVE 0 31 mmDAGB6_RDCLI0 0 0x3080 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI1 0 0x3081 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI2 0 0x3082 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI3 0 0x3083 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI4 0 0x3084 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI5 0 0x3085 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI6 0 0x3086 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI7 0 0x3087 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI8 0 0x3088 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI9 0 0x3089 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI10 0 0x308a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI11 0 0x308b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI12 0 0x308c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI13 0 0x308d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI14 0 0x308e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RDCLI15 0 0x308f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_RD_CNTL 0 0x3090 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB6_RD_GMI_CNTL 0 0x3091 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB6_RD_ADDR_DAGB 0 0x3092 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST 0 0x3093 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x3094 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB6_RD_CGTT_CLK_CTRL 0 0x3095 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL 0 0x3096 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL 0 0x3097 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 0 0x3098 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 0 0x3099 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 0 0x309a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 0 0x309b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_RD_VC0_CNTL 0 0x309c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC1_CNTL 0 0x309d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC2_CNTL 0 0x309e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC3_CNTL 0 0x309f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC4_CNTL 0 0x30a0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC5_CNTL 0 0x30a1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC6_CNTL 0 0x30a2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_VC7_CNTL 0 0x30a3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_RD_CNTL_MISC 0 0x30a4 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB6_RD_TLB_CREDIT 0 0x30a5 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB6_RDCLI_ASK_PENDING 0 0x30a6 1 0 1 BUSY 0 31 mmDAGB6_RDCLI_GO_PENDING 0 0x30a7 1 0 1 BUSY 0 31 mmDAGB6_RDCLI_GBLSEND_PENDING 0 0x30a8 1 0 1 BUSY 0 31 mmDAGB6_RDCLI_TLB_PENDING 0 0x30a9 1 0 1 BUSY 0 31 mmDAGB6_RDCLI_OARB_PENDING 0 0x30aa 1 0 1 BUSY 0 31 mmDAGB6_RDCLI_OSD_PENDING 0 0x30ab 1 0 1 BUSY 0 31 mmDAGB6_WRCLI0 0 0x30ac 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI1 0 0x30ad 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI2 0 0x30ae 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI3 0 0x30af 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI4 0 0x30b0 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI5 0 0x30b1 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI6 0 0x30b2 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI7 0 0x30b3 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI8 0 0x30b4 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI9 0 0x30b5 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI10 0 0x30b6 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI11 0 0x30b7 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI12 0 0x30b8 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI13 0 0x30b9 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI14 0 0x30ba 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WRCLI15 0 0x30bb 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB6_WR_CNTL 0 0x30bc 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB6_WR_GMI_CNTL 0 0x30bd 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB6_WR_ADDR_DAGB 0 0x30be 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST 0 0x30bf 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x30c0 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB6_WR_CGTT_CLK_CTRL 0 0x30c1 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL 0 0x30c2 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL 0 0x30c3 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 0 0x30c4 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 0 0x30c5 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 0 0x30c6 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 0 0x30c7 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_WR_DATA_DAGB 0 0x30c8 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB6_WR_DATA_DAGB_MAX_BURST0 0 0x30c9 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 0 0x30ca 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB6_WR_DATA_DAGB_MAX_BURST1 0 0x30cb 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 0 0x30cc 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB6_WR_VC0_CNTL 0 0x30cd 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC1_CNTL 0 0x30ce 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC2_CNTL 0 0x30cf 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC3_CNTL 0 0x30d0 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC4_CNTL 0 0x30d1 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC5_CNTL 0 0x30d2 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC6_CNTL 0 0x30d3 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_VC7_CNTL 0 0x30d4 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB6_WR_CNTL_MISC 0 0x30d5 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB6_WR_TLB_CREDIT 0 0x30d6 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB6_WR_DATA_CREDIT 0 0x30d7 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB6_WR_MISC_CREDIT 0 0x30d8 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB6_WRCLI_ASK_PENDING 0 0x30dd 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_GO_PENDING 0 0x30de 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_GBLSEND_PENDING 0 0x30df 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_TLB_PENDING 0 0x30e0 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_OARB_PENDING 0 0x30e1 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_OSD_PENDING 0 0x30e2 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_DBUS_ASK_PENDING 0 0x30e3 1 0 1 BUSY 0 31 mmDAGB6_WRCLI_DBUS_GO_PENDING 0 0x30e4 1 0 1 BUSY 0 31 mmDAGB6_DAGB_DLY 0 0x30e5 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB6_CNTL_MISC 0 0x30e6 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB6_CNTL_MISC2 0 0x30e7 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB6_FIFO_EMPTY 0 0x30e8 1 0 1 EMPTY 0 23 mmDAGB6_FIFO_FULL 0 0x30e9 1 0 1 FULL 0 22 mmDAGB6_WR_CREDITS_FULL 0 0x30ea 1 0 1 FULL 0 28 mmDAGB6_RD_CREDITS_FULL 0 0x30eb 1 0 1 FULL 0 17 mmDAGB6_PERFCOUNTER_LO 0 0x30ec 1 0 1 COUNTER_LO 0 31 mmDAGB6_PERFCOUNTER_HI 0 0x30ed 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB6_PERFCOUNTER0_CFG 0 0x30ee 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB6_PERFCOUNTER1_CFG 0 0x30ef 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB6_PERFCOUNTER2_CFG 0 0x30f0 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB6_PERFCOUNTER_RSLT_CNTL 0 0x30f1 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB6_RESERVE0 0 0x30f2 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE1 0 0x30f3 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE2 0 0x30f4 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE3 0 0x30f5 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE4 0 0x30f6 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE5 0 0x30f7 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE6 0 0x30f8 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE7 0 0x30f9 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE8 0 0x30fa 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE9 0 0x30fb 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE10 0 0x30fc 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE11 0 0x30fd 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE12 0 0x30fe 1 0 1 RESERVE 0 31 mmDAGB6_RESERVE13 0 0x30ff 1 0 1 RESERVE 0 31 mmDAGB7_RDCLI0 0 0x3100 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI1 0 0x3101 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI2 0 0x3102 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI3 0 0x3103 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI4 0 0x3104 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI5 0 0x3105 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI6 0 0x3106 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI7 0 0x3107 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI8 0 0x3108 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI9 0 0x3109 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI10 0 0x310a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI11 0 0x310b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI12 0 0x310c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI13 0 0x310d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI14 0 0x310e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RDCLI15 0 0x310f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_RD_CNTL 0 0x3110 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB7_RD_GMI_CNTL 0 0x3111 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB7_RD_ADDR_DAGB 0 0x3112 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST 0 0x3113 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 0 0x3114 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB7_RD_CGTT_CLK_CTRL 0 0x3115 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL 0 0x3116 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL 0 0x3117 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 0 0x3118 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 0 0x3119 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 0 0x311a 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 0 0x311b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_RD_VC0_CNTL 0 0x311c 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC1_CNTL 0 0x311d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC2_CNTL 0 0x311e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC3_CNTL 0 0x311f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC4_CNTL 0 0x3120 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC5_CNTL 0 0x3121 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC6_CNTL 0 0x3122 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_VC7_CNTL 0 0x3123 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_RD_CNTL_MISC 0 0x3124 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB7_RD_TLB_CREDIT 0 0x3125 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB7_RDCLI_ASK_PENDING 0 0x3126 1 0 1 BUSY 0 31 mmDAGB7_RDCLI_GO_PENDING 0 0x3127 1 0 1 BUSY 0 31 mmDAGB7_RDCLI_GBLSEND_PENDING 0 0x3128 1 0 1 BUSY 0 31 mmDAGB7_RDCLI_TLB_PENDING 0 0x3129 1 0 1 BUSY 0 31 mmDAGB7_RDCLI_OARB_PENDING 0 0x312a 1 0 1 BUSY 0 31 mmDAGB7_RDCLI_OSD_PENDING 0 0x312b 1 0 1 BUSY 0 31 mmDAGB7_WRCLI0 0 0x312c 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI1 0 0x312d 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI2 0 0x312e 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI3 0 0x312f 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI4 0 0x3130 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI5 0 0x3131 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI6 0 0x3132 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI7 0 0x3133 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI8 0 0x3134 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI9 0 0x3135 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI10 0 0x3136 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI11 0 0x3137 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI12 0 0x3138 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI13 0 0x3139 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI14 0 0x313a 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WRCLI15 0 0x313b 10 0 1 VIRT_CHAN 0 2 CHECK_TLB_CREDIT 3 3 URG_HIGH 4 7 URG_LOW 8 11 MAX_BW_ENABLE 12 12 MAX_BW 13 20 MIN_BW_ENABLE 21 21 MIN_BW 22 24 OSD_LIMITER_ENABLE 25 25 MAX_OSD 26 31 mmDAGB7_WR_CNTL 0 0x313c 7 0 1 SCLK_FREQ 0 3 CLI_MAX_BW_WINDOW 4 9 VC_MAX_BW_WINDOW 10 15 IO_LEVEL_OVERRIDE_ENABLE 16 16 IO_LEVEL 17 19 IO_LEVEL_COMPLY_VC 20 22 SHARE_VC_NUM 23 25 mmDAGB7_WR_GMI_CNTL 0 0x313d 4 0 1 EA_CREDIT 0 5 LEVEL 6 8 MAX_BURST 9 12 LAZY_TIMER 13 16 mmDAGB7_WR_ADDR_DAGB 0 0x313e 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST 0 0x313f 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 0 0x3140 8 0 1 VC0 0 3 VC1 4 7 VC2 8 11 VC3 12 15 VC4 16 19 VC5 20 23 VC6 24 27 VC7 28 31 mmDAGB7_WR_CGTT_CLK_CTRL 0 0x3141 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL 0 0x3142 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL 0 0x3143 8 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_STALL_OVERRIDE 22 22 LS_OVERRIDE 27 27 LS_OVERRIDE_WRITE 28 28 LS_OVERRIDE_READ 29 29 LS_OVERRIDE_RETURN 30 30 LS_OVERRIDE_REGISTER 31 31 mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 0 0x3144 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 0 0x3145 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 0 0x3146 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 0 0x3147 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_WR_DATA_DAGB 0 0x3148 4 0 1 DAGB_ENABLE 0 2 ENABLE_JUMP_AHEAD 3 5 DISABLE_SELF_INIT 6 6 WHOAMI 7 12 mmDAGB7_WR_DATA_DAGB_MAX_BURST0 0 0x3149 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 0 0x314a 8 0 1 CLIENT0 0 3 CLIENT1 4 7 CLIENT2 8 11 CLIENT3 12 15 CLIENT4 16 19 CLIENT5 20 23 CLIENT6 24 27 CLIENT7 28 31 mmDAGB7_WR_DATA_DAGB_MAX_BURST1 0 0x314b 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 0 0x314c 8 0 1 CLIENT8 0 3 CLIENT9 4 7 CLIENT10 8 11 CLIENT11 12 15 CLIENT12 16 19 CLIENT13 20 23 CLIENT14 24 27 CLIENT15 28 31 mmDAGB7_WR_VC0_CNTL 0 0x314d 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC1_CNTL 0 0x314e 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC2_CNTL 0 0x314f 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC3_CNTL 0 0x3150 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC4_CNTL 0 0x3151 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC5_CNTL 0 0x3152 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC6_CNTL 0 0x3153 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_VC7_CNTL 0 0x3154 8 0 1 STOR_CREDIT 0 4 EA_CREDIT 5 10 MAX_BW_ENABLE 11 11 MAX_BW 12 19 MIN_BW_ENABLE 20 20 MIN_BW 21 23 OSD_LIMITER_ENABLE 24 24 MAX_OSD 25 31 mmDAGB7_WR_CNTL_MISC 0 0x3155 7 0 1 STOR_POOL_CREDIT 0 5 EA_POOL_CREDIT 6 12 IO_EA_CREDIT 13 18 STOR_CC_LEGACY_MODE 19 19 EA_CC_LEGACY_MODE 20 20 UTCL2_CID 21 25 RDRET_FIFO_CREDITS 26 31 mmDAGB7_WR_TLB_CREDIT 0 0x3156 6 0 1 TLB0 0 4 TLB1 5 9 TLB2 10 14 TLB3 15 19 TLB4 20 24 TLB5 25 29 mmDAGB7_WR_DATA_CREDIT 0 0x3157 4 0 1 DLOCK_VC_CREDITS 0 7 LARGE_BURST_CREDITS 8 15 MIDDLE_BURST_CREDITS 16 23 SMALL_BURST_CREDITS 24 31 mmDAGB7_WR_MISC_CREDIT 0 0x3158 4 0 1 ATOMIC_CREDIT 0 5 DLOCK_VC_NUM 6 8 OSD_CREDIT 9 15 OSD_DLOCK_CREDIT 16 22 mmDAGB7_WRCLI_ASK_PENDING 0 0x315d 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_GO_PENDING 0 0x315e 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_GBLSEND_PENDING 0 0x315f 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_TLB_PENDING 0 0x3160 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_OARB_PENDING 0 0x3161 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_OSD_PENDING 0 0x3162 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_DBUS_ASK_PENDING 0 0x3163 1 0 1 BUSY 0 31 mmDAGB7_WRCLI_DBUS_GO_PENDING 0 0x3164 1 0 1 BUSY 0 31 mmDAGB7_DAGB_DLY 0 0x3165 3 0 1 DLY 0 7 CLI 8 15 POS 16 19 mmDAGB7_CNTL_MISC 0 0x3166 10 0 1 EA_VC0_REMAP 0 2 EA_VC1_REMAP 3 5 EA_VC2_REMAP 6 8 EA_VC3_REMAP 9 11 EA_VC4_REMAP 12 14 EA_VC5_REMAP 15 17 EA_VC6_REMAP 18 20 EA_VC7_REMAP 21 23 BW_INIT_CYCLE 24 29 BW_RW_GAP_CYCLE 30 31 mmDAGB7_CNTL_MISC2 0 0x3167 13 0 1 URG_BOOST_ENABLE 0 0 URG_HALT_ENABLE 1 1 DISABLE_WRREQ_CG 2 2 DISABLE_WRRET_CG 3 3 DISABLE_RDREQ_CG 4 4 DISABLE_RDRET_CG 5 5 DISABLE_TLBWR_CG 6 6 DISABLE_TLBRD_CG 7 7 DISABLE_EAWRREQ_BUSY 8 8 DISABLE_EARDREQ_BUSY 9 9 SWAP_CTL 10 10 RDRET_FIFO_PERF 11 11 RDRET_FIFO_DLOCK_CREDITS 17 22 mmDAGB7_FIFO_EMPTY 0 0x3168 1 0 1 EMPTY 0 23 mmDAGB7_FIFO_FULL 0 0x3169 1 0 1 FULL 0 22 mmDAGB7_WR_CREDITS_FULL 0 0x316a 1 0 1 FULL 0 28 mmDAGB7_RD_CREDITS_FULL 0 0x316b 1 0 1 FULL 0 17 mmDAGB7_PERFCOUNTER_LO 0 0x316c 1 0 1 COUNTER_LO 0 31 mmDAGB7_PERFCOUNTER_HI 0 0x316d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmDAGB7_PERFCOUNTER0_CFG 0 0x316e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB7_PERFCOUNTER1_CFG 0 0x316f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB7_PERFCOUNTER2_CFG 0 0x3170 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmDAGB7_PERFCOUNTER_RSLT_CNTL 0 0x3171 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmDAGB7_RESERVE0 0 0x3172 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE1 0 0x3173 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE2 0 0x3174 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE3 0 0x3175 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE4 0 0x3176 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE5 0 0x3177 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE6 0 0x3178 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE7 0 0x3179 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE8 0 0x317a 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE9 0 0x317b 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE10 0 0x317c 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE11 0 0x317d 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE12 0 0x317e 1 0 1 RESERVE 0 31 mmDAGB7_RESERVE13 0 0x317f 1 0 1 RESERVE 0 31 mmMMEA5_DRAM_RD_CLI2GRP_MAP0 0 0x3280 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_DRAM_RD_CLI2GRP_MAP1 0 0x3281 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_DRAM_WR_CLI2GRP_MAP0 0 0x3282 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_DRAM_WR_CLI2GRP_MAP1 0 0x3283 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_DRAM_RD_GRP2VC_MAP 0 0x3284 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA5_DRAM_WR_GRP2VC_MAP 0 0x3285 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA5_DRAM_RD_LAZY 0 0x3286 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA5_DRAM_WR_LAZY 0 0x3287 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA5_DRAM_RD_CAM_CNTL 0 0x3288 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA5_DRAM_WR_CAM_CNTL 0 0x3289 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA5_DRAM_PAGE_BURST 0 0x328a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA5_DRAM_RD_PRI_AGE 0 0x328b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_DRAM_WR_PRI_AGE 0 0x328c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_DRAM_RD_PRI_QUEUING 0 0x328d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_DRAM_WR_PRI_QUEUING 0 0x328e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_DRAM_RD_PRI_FIXED 0 0x328f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_DRAM_WR_PRI_FIXED 0 0x3290 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_DRAM_RD_PRI_URGENCY 0 0x3291 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_DRAM_WR_PRI_URGENCY 0 0x3292 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 0 0x3293 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 0 0x3294 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 0 0x3295 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 0 0x3296 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 0 0x3297 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 0 0x3298 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_RD_CLI2GRP_MAP0 0 0x3299 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_GMI_RD_CLI2GRP_MAP1 0 0x329a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_GMI_WR_CLI2GRP_MAP0 0 0x329b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_GMI_WR_CLI2GRP_MAP1 0 0x329c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_GMI_RD_GRP2VC_MAP 0 0x329d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA5_GMI_WR_GRP2VC_MAP 0 0x329e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA5_GMI_RD_LAZY 0 0x329f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA5_GMI_WR_LAZY 0 0x32a0 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA5_GMI_RD_CAM_CNTL 0 0x32a1 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA5_GMI_WR_CAM_CNTL 0 0x32a2 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA5_GMI_PAGE_BURST 0 0x32a3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA5_GMI_RD_PRI_AGE 0 0x32a4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_GMI_WR_PRI_AGE 0 0x32a5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_GMI_RD_PRI_QUEUING 0 0x32a6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_GMI_WR_PRI_QUEUING 0 0x32a7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_GMI_RD_PRI_FIXED 0 0x32a8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_GMI_WR_PRI_FIXED 0 0x32a9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_GMI_RD_PRI_URGENCY 0 0x32aa 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_GMI_WR_PRI_URGENCY 0 0x32ab 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_GMI_RD_PRI_URGENCY_MASKING 0 0x32ac 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA5_GMI_WR_PRI_URGENCY_MASKING 0 0x32ad 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA5_GMI_RD_PRI_QUANT_PRI1 0 0x32ae 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_RD_PRI_QUANT_PRI2 0 0x32af 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_RD_PRI_QUANT_PRI3 0 0x32b0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_WR_PRI_QUANT_PRI1 0 0x32b1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_WR_PRI_QUANT_PRI2 0 0x32b2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_GMI_WR_PRI_QUANT_PRI3 0 0x32b3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_ADDRNORM_BASE_ADDR0 0 0x32b4 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR0 0 0x32b5 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_BASE_ADDR1 0 0x32b6 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR1 0 0x32b7 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_OFFSET_ADDR1 0 0x32b8 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA5_ADDRNORM_BASE_ADDR2 0 0x32b9 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR2 0 0x32ba 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_BASE_ADDR3 0 0x32bb 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR3 0 0x32bc 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_OFFSET_ADDR3 0 0x32bd 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA5_ADDRNORM_BASE_ADDR4 0 0x32be 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR4 0 0x32bf 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_BASE_ADDR5 0 0x32c0 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA5_ADDRNORM_LIMIT_ADDR5 0 0x32c1 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA5_ADDRNORM_OFFSET_ADDR5 0 0x32c2 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA5_ADDRNORMDRAM_HOLE_CNTL 0 0x32c3 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA5_ADDRNORMGMI_HOLE_CNTL 0 0x32c4 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x32c5 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x32c6 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA5_ADDRDEC_BANK_CFG 0 0x32c7 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA5_ADDRDEC_MISC_CFG 0 0x32c8 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x32c9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x32ca 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x32cb 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x32cc 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x32cd 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x32ce 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC 0 0x32cf 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 0 0x32d0 1 0 1 BANK_XOR 0 5 mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 0 0x32d1 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 0 0x32d2 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0 0x32d3 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 0 0x32d4 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 0 0x32d5 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 0 0x32d6 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 0 0x32d7 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 0 0x32d8 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 0 0x32d9 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_PC 0 0x32da 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 0 0x32db 1 0 1 BANK_XOR 0 5 mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 0 0x32dc 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 0 0x32dd 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA5_ADDRDECGMI_HARVEST_ENABLE 0 0x32de 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 0 0x32df 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 0 0x32e0 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 0 0x32e1 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 0 0x32e2 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0 0x32e3 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0 0x32e4 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0 0x32e5 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0 0x32e6 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 0 0x32e7 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 0 0x32e8 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0 0x32e9 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0 0x32ea 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 0 0x32eb 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 0 0x32ec 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 0 0x32ed 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 0 0x32ee 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0 0x32ef 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0 0x32f0 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0 0x32f1 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0 0x32f2 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0 0x32f3 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0 0x32f4 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC0_RM_SEL_CS01 0 0x32f5 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC0_RM_SEL_CS23 0 0x32f6 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 0 0x32f7 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 0 0x32f8 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 0 0x32f9 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 0 0x32fa 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 0 0x32fb 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 0 0x32fc 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0 0x32fd 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0 0x32fe 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0 0x32ff 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0 0x3300 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 0 0x3301 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 0 0x3302 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0 0x3303 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0 0x3304 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 0 0x3305 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 0 0x3306 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 0 0x3307 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 0 0x3308 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0 0x3309 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0 0x330a 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0 0x330b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0 0x330c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0 0x330d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0 0x330e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC1_RM_SEL_CS01 0 0x330f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC1_RM_SEL_CS23 0 0x3310 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 0 0x3311 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 0 0x3312 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 0 0x3313 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 0 0x3314 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 0 0x3315 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 0 0x3316 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0 0x3317 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0 0x3318 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0 0x3319 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0 0x331a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 0 0x331b 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 0 0x331c 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0 0x331d 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0 0x331e 1 0 1 ADDR_MASK 1 31 mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 0 0x331f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 0 0x3320 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 0 0x3321 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 0 0x3322 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0 0x3323 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0 0x3324 1 0 1 BANK5 0 4 mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0 0x3325 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0 0x3326 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0 0x3327 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0 0x3328 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA5_ADDRDEC2_RM_SEL_CS01 0 0x3329 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC2_RM_SEL_CS23 0 0x332a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 0 0x332b 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 0 0x332c 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0 0x332d 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0 0x332e 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA5_IO_RD_CLI2GRP_MAP0 0 0x3355 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_IO_RD_CLI2GRP_MAP1 0 0x3356 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_IO_WR_CLI2GRP_MAP0 0 0x3357 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA5_IO_WR_CLI2GRP_MAP1 0 0x3358 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA5_IO_RD_COMBINE_FLUSH 0 0x3359 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA5_IO_WR_COMBINE_FLUSH 0 0x335a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA5_IO_GROUP_BURST 0 0x335b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA5_IO_RD_PRI_AGE 0 0x335c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_IO_WR_PRI_AGE 0 0x335d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA5_IO_RD_PRI_QUEUING 0 0x335e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_IO_WR_PRI_QUEUING 0 0x335f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA5_IO_RD_PRI_FIXED 0 0x3360 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_IO_WR_PRI_FIXED 0 0x3361 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA5_IO_RD_PRI_URGENCY 0 0x3362 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_IO_WR_PRI_URGENCY 0 0x3363 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA5_IO_RD_PRI_URGENCY_MASKING 0 0x3364 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA5_IO_WR_PRI_URGENCY_MASKING 0 0x3365 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA5_IO_RD_PRI_QUANT_PRI1 0 0x3366 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_IO_RD_PRI_QUANT_PRI2 0 0x3367 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_IO_RD_PRI_QUANT_PRI3 0 0x3368 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_IO_WR_PRI_QUANT_PRI1 0 0x3369 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_IO_WR_PRI_QUANT_PRI2 0 0x336a 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_IO_WR_PRI_QUANT_PRI3 0 0x336b 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA5_SDP_ARB_DRAM 0 0x336c 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA5_SDP_ARB_GMI 0 0x336d 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA5_SDP_ARB_FINAL 0 0x336e 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA5_SDP_DRAM_PRIORITY 0 0x336f 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA5_SDP_GMI_PRIORITY 0 0x3370 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA5_SDP_IO_PRIORITY 0 0x3371 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA5_SDP_CREDITS 0 0x3372 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA5_SDP_TAG_RESERVE0 0 0x3373 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA5_SDP_TAG_RESERVE1 0 0x3374 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA5_SDP_VCC_RESERVE0 0 0x3375 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA5_SDP_VCC_RESERVE1 0 0x3376 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA5_SDP_VCD_RESERVE0 0 0x3377 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA5_SDP_VCD_RESERVE1 0 0x3378 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA5_SDP_REQ_CNTL 0 0x3379 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA5_MISC 0 0x337a 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA5_LATENCY_SAMPLING 0 0x337b 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA5_PERFCOUNTER_LO 0 0x337c 1 0 1 COUNTER_LO 0 31 mmMMEA5_PERFCOUNTER_HI 0 0x337d 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA5_PERFCOUNTER0_CFG 0 0x337e 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA5_PERFCOUNTER1_CFG 0 0x337f 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA5_PERFCOUNTER_RSLT_CNTL 0 0x3380 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA5_EDC_CNT 0 0x3386 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA5_EDC_CNT2 0 0x3387 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA5_DSM_CNTL 0 0x3388 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA5_DSM_CNTLA 0 0x3389 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA5_DSM_CNTLB 0 0x338a 0 0 1 mmMMEA5_DSM_CNTL2 0 0x338b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA5_DSM_CNTL2A 0 0x338c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA5_DSM_CNTL2B 0 0x338d 0 0 1 mmMMEA5_CGTT_CLK_CTRL 0 0x338f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA5_EDC_MODE 0 0x3390 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA5_ERR_STATUS 0 0x3391 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA5_MISC2 0 0x3392 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA5_ADDRDEC_SELECT 0 0x3393 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA5_EDC_CNT3 0 0x3394 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA6_DRAM_RD_CLI2GRP_MAP0 0 0x33c0 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_DRAM_RD_CLI2GRP_MAP1 0 0x33c1 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_DRAM_WR_CLI2GRP_MAP0 0 0x33c2 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_DRAM_WR_CLI2GRP_MAP1 0 0x33c3 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_DRAM_RD_GRP2VC_MAP 0 0x33c4 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA6_DRAM_WR_GRP2VC_MAP 0 0x33c5 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA6_DRAM_RD_LAZY 0 0x33c6 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA6_DRAM_WR_LAZY 0 0x33c7 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA6_DRAM_RD_CAM_CNTL 0 0x33c8 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA6_DRAM_WR_CAM_CNTL 0 0x33c9 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA6_DRAM_PAGE_BURST 0 0x33ca 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA6_DRAM_RD_PRI_AGE 0 0x33cb 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_DRAM_WR_PRI_AGE 0 0x33cc 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_DRAM_RD_PRI_QUEUING 0 0x33cd 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_DRAM_WR_PRI_QUEUING 0 0x33ce 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_DRAM_RD_PRI_FIXED 0 0x33cf 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_DRAM_WR_PRI_FIXED 0 0x33d0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_DRAM_RD_PRI_URGENCY 0 0x33d1 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_DRAM_WR_PRI_URGENCY 0 0x33d2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 0 0x33d3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 0 0x33d4 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 0 0x33d5 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 0 0x33d6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 0 0x33d7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 0 0x33d8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_RD_CLI2GRP_MAP0 0 0x33d9 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_GMI_RD_CLI2GRP_MAP1 0 0x33da 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_GMI_WR_CLI2GRP_MAP0 0 0x33db 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_GMI_WR_CLI2GRP_MAP1 0 0x33dc 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_GMI_RD_GRP2VC_MAP 0 0x33dd 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA6_GMI_WR_GRP2VC_MAP 0 0x33de 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA6_GMI_RD_LAZY 0 0x33df 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA6_GMI_WR_LAZY 0 0x33e0 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA6_GMI_RD_CAM_CNTL 0 0x33e1 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA6_GMI_WR_CAM_CNTL 0 0x33e2 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA6_GMI_PAGE_BURST 0 0x33e3 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA6_GMI_RD_PRI_AGE 0 0x33e4 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_GMI_WR_PRI_AGE 0 0x33e5 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_GMI_RD_PRI_QUEUING 0 0x33e6 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_GMI_WR_PRI_QUEUING 0 0x33e7 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_GMI_RD_PRI_FIXED 0 0x33e8 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_GMI_WR_PRI_FIXED 0 0x33e9 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_GMI_RD_PRI_URGENCY 0 0x33ea 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_GMI_WR_PRI_URGENCY 0 0x33eb 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_GMI_RD_PRI_URGENCY_MASKING 0 0x33ec 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA6_GMI_WR_PRI_URGENCY_MASKING 0 0x33ed 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA6_GMI_RD_PRI_QUANT_PRI1 0 0x33ee 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_RD_PRI_QUANT_PRI2 0 0x33ef 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_RD_PRI_QUANT_PRI3 0 0x33f0 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_WR_PRI_QUANT_PRI1 0 0x33f1 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_WR_PRI_QUANT_PRI2 0 0x33f2 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_GMI_WR_PRI_QUANT_PRI3 0 0x33f3 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_ADDRNORM_BASE_ADDR0 0 0x33f4 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR0 0 0x33f5 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_BASE_ADDR1 0 0x33f6 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR1 0 0x33f7 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_OFFSET_ADDR1 0 0x33f8 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA6_ADDRNORM_BASE_ADDR2 0 0x33f9 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR2 0 0x33fa 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_BASE_ADDR3 0 0x33fb 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR3 0 0x33fc 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_OFFSET_ADDR3 0 0x33fd 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA6_ADDRNORM_BASE_ADDR4 0 0x33fe 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR4 0 0x33ff 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_BASE_ADDR5 0 0x3400 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA6_ADDRNORM_LIMIT_ADDR5 0 0x3401 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA6_ADDRNORM_OFFSET_ADDR5 0 0x3402 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA6_ADDRNORMDRAM_HOLE_CNTL 0 0x3403 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA6_ADDRNORMGMI_HOLE_CNTL 0 0x3404 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x3405 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x3406 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA6_ADDRDEC_BANK_CFG 0 0x3407 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA6_ADDRDEC_MISC_CFG 0 0x3408 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x3409 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x340a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x340b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x340c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x340d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x340e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC 0 0x340f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 0 0x3410 1 0 1 BANK_XOR 0 5 mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 0 0x3411 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 0 0x3412 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE 0 0x3413 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 0 0x3414 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 0 0x3415 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 0 0x3416 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 0 0x3417 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 0 0x3418 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 0 0x3419 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_PC 0 0x341a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 0 0x341b 1 0 1 BANK_XOR 0 5 mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 0 0x341c 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 0 0x341d 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA6_ADDRDECGMI_HARVEST_ENABLE 0 0x341e 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 0 0x341f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 0 0x3420 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 0 0x3421 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 0 0x3422 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 0 0x3423 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 0 0x3424 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 0 0x3425 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 0 0x3426 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 0 0x3427 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 0 0x3428 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 0 0x3429 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 0 0x342a 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 0 0x342b 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 0 0x342c 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 0 0x342d 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 0 0x342e 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 0 0x342f 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 0 0x3430 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 0 0x3431 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 0 0x3432 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 0 0x3433 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 0 0x3434 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC0_RM_SEL_CS01 0 0x3435 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC0_RM_SEL_CS23 0 0x3436 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 0 0x3437 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 0 0x3438 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 0 0x3439 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 0 0x343a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 0 0x343b 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 0 0x343c 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 0 0x343d 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 0 0x343e 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 0 0x343f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 0 0x3440 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 0 0x3441 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 0 0x3442 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 0 0x3443 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 0 0x3444 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 0 0x3445 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 0 0x3446 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 0 0x3447 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 0 0x3448 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 0 0x3449 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 0 0x344a 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 0 0x344b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 0 0x344c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 0 0x344d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 0 0x344e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC1_RM_SEL_CS01 0 0x344f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC1_RM_SEL_CS23 0 0x3450 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 0 0x3451 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 0 0x3452 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 0 0x3453 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 0 0x3454 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 0 0x3455 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 0 0x3456 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 0 0x3457 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 0 0x3458 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 0 0x3459 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 0 0x345a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 0 0x345b 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 0 0x345c 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 0 0x345d 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 0 0x345e 1 0 1 ADDR_MASK 1 31 mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 0 0x345f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 0 0x3460 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 0 0x3461 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 0 0x3462 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 0 0x3463 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 0 0x3464 1 0 1 BANK5 0 4 mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 0 0x3465 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 0 0x3466 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 0 0x3467 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 0 0x3468 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA6_ADDRDEC2_RM_SEL_CS01 0 0x3469 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC2_RM_SEL_CS23 0 0x346a 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 0 0x346b 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 0 0x346c 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL 0 0x346d 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL 0 0x346e 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA6_IO_RD_CLI2GRP_MAP0 0 0x3495 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_IO_RD_CLI2GRP_MAP1 0 0x3496 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_IO_WR_CLI2GRP_MAP0 0 0x3497 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA6_IO_WR_CLI2GRP_MAP1 0 0x3498 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA6_IO_RD_COMBINE_FLUSH 0 0x3499 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA6_IO_WR_COMBINE_FLUSH 0 0x349a 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA6_IO_GROUP_BURST 0 0x349b 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA6_IO_RD_PRI_AGE 0 0x349c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_IO_WR_PRI_AGE 0 0x349d 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA6_IO_RD_PRI_QUEUING 0 0x349e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_IO_WR_PRI_QUEUING 0 0x349f 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA6_IO_RD_PRI_FIXED 0 0x34a0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_IO_WR_PRI_FIXED 0 0x34a1 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA6_IO_RD_PRI_URGENCY 0 0x34a2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_IO_WR_PRI_URGENCY 0 0x34a3 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA6_IO_RD_PRI_URGENCY_MASKING 0 0x34a4 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA6_IO_WR_PRI_URGENCY_MASKING 0 0x34a5 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA6_IO_RD_PRI_QUANT_PRI1 0 0x34a6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_IO_RD_PRI_QUANT_PRI2 0 0x34a7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_IO_RD_PRI_QUANT_PRI3 0 0x34a8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_IO_WR_PRI_QUANT_PRI1 0 0x34a9 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_IO_WR_PRI_QUANT_PRI2 0 0x34aa 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_IO_WR_PRI_QUANT_PRI3 0 0x34ab 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA6_SDP_ARB_DRAM 0 0x34ac 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA6_SDP_ARB_GMI 0 0x34ad 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA6_SDP_ARB_FINAL 0 0x34ae 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA6_SDP_DRAM_PRIORITY 0 0x34af 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA6_SDP_GMI_PRIORITY 0 0x34b0 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA6_SDP_IO_PRIORITY 0 0x34b1 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA6_SDP_CREDITS 0 0x34b2 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA6_SDP_TAG_RESERVE0 0 0x34b3 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA6_SDP_TAG_RESERVE1 0 0x34b4 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA6_SDP_VCC_RESERVE0 0 0x34b5 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA6_SDP_VCC_RESERVE1 0 0x34b6 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA6_SDP_VCD_RESERVE0 0 0x34b7 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA6_SDP_VCD_RESERVE1 0 0x34b8 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA6_SDP_REQ_CNTL 0 0x34b9 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA6_MISC 0 0x34ba 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA6_LATENCY_SAMPLING 0 0x34bb 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA6_PERFCOUNTER_LO 0 0x34bc 1 0 1 COUNTER_LO 0 31 mmMMEA6_PERFCOUNTER_HI 0 0x34bd 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA6_PERFCOUNTER0_CFG 0 0x34be 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA6_PERFCOUNTER1_CFG 0 0x34bf 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA6_PERFCOUNTER_RSLT_CNTL 0 0x34c0 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA6_EDC_CNT 0 0x34c6 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA6_EDC_CNT2 0 0x34c7 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA6_DSM_CNTL 0 0x34c8 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA6_DSM_CNTLA 0 0x34c9 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA6_DSM_CNTLB 0 0x34ca 0 0 1 mmMMEA6_DSM_CNTL2 0 0x34cb 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA6_DSM_CNTL2A 0 0x34cc 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA6_DSM_CNTL2B 0 0x34cd 0 0 1 mmMMEA6_CGTT_CLK_CTRL 0 0x34cf 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA6_EDC_MODE 0 0x34d0 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA6_ERR_STATUS 0 0x34d1 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA6_MISC2 0 0x34d2 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA6_ADDRDEC_SELECT 0 0x34d3 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA6_EDC_CNT3 0 0x34d4 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmMMEA7_DRAM_RD_CLI2GRP_MAP0 0 0x3500 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_DRAM_RD_CLI2GRP_MAP1 0 0x3501 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_DRAM_WR_CLI2GRP_MAP0 0 0x3502 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_DRAM_WR_CLI2GRP_MAP1 0 0x3503 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_DRAM_RD_GRP2VC_MAP 0 0x3504 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA7_DRAM_WR_GRP2VC_MAP 0 0x3505 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA7_DRAM_RD_LAZY 0 0x3506 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA7_DRAM_WR_LAZY 0 0x3507 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA7_DRAM_RD_CAM_CNTL 0 0x3508 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA7_DRAM_WR_CAM_CNTL 0 0x3509 9 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 mmMMEA7_DRAM_PAGE_BURST 0 0x350a 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA7_DRAM_RD_PRI_AGE 0 0x350b 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_DRAM_WR_PRI_AGE 0 0x350c 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_DRAM_RD_PRI_QUEUING 0 0x350d 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_DRAM_WR_PRI_QUEUING 0 0x350e 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_DRAM_RD_PRI_FIXED 0 0x350f 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_DRAM_WR_PRI_FIXED 0 0x3510 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_DRAM_RD_PRI_URGENCY 0 0x3511 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_DRAM_WR_PRI_URGENCY 0 0x3512 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 0 0x3513 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 0 0x3514 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 0 0x3515 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 0 0x3516 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 0 0x3517 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 0 0x3518 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_RD_CLI2GRP_MAP0 0 0x3519 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_GMI_RD_CLI2GRP_MAP1 0 0x351a 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_GMI_WR_CLI2GRP_MAP0 0 0x351b 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_GMI_WR_CLI2GRP_MAP1 0 0x351c 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_GMI_RD_GRP2VC_MAP 0 0x351d 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA7_GMI_WR_GRP2VC_MAP 0 0x351e 4 0 1 GROUP0_VC 0 2 GROUP1_VC 3 5 GROUP2_VC 6 8 GROUP3_VC 9 11 mmMMEA7_GMI_RD_LAZY 0 0x351f 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA7_GMI_WR_LAZY 0 0x3520 7 0 1 GROUP0_DELAY 0 2 GROUP1_DELAY 3 5 GROUP2_DELAY 6 8 GROUP3_DELAY 9 11 REQ_ACCUM_THRESH 12 17 REQ_ACCUM_TIMEOUT 20 26 REQ_ACCUM_IDLEMAX 27 30 mmMMEA7_GMI_RD_CAM_CNTL 0 0x3521 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA7_GMI_WR_CAM_CNTL 0 0x3522 10 0 1 DEPTH_GROUP0 0 3 DEPTH_GROUP1 4 7 DEPTH_GROUP2 8 11 DEPTH_GROUP3 12 15 REORDER_LIMIT_GROUP0 16 18 REORDER_LIMIT_GROUP1 19 21 REORDER_LIMIT_GROUP2 22 24 REORDER_LIMIT_GROUP3 25 27 REFILL_CHAIN 28 28 PAGEBASED_CHAINING 29 29 mmMMEA7_GMI_PAGE_BURST 0 0x3523 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA7_GMI_RD_PRI_AGE 0 0x3524 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_GMI_WR_PRI_AGE 0 0x3525 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_GMI_RD_PRI_QUEUING 0 0x3526 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_GMI_WR_PRI_QUEUING 0 0x3527 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_GMI_RD_PRI_FIXED 0 0x3528 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_GMI_WR_PRI_FIXED 0 0x3529 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_GMI_RD_PRI_URGENCY 0 0x352a 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_GMI_WR_PRI_URGENCY 0 0x352b 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_GMI_RD_PRI_URGENCY_MASKING 0 0x352c 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA7_GMI_WR_PRI_URGENCY_MASKING 0 0x352d 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA7_GMI_RD_PRI_QUANT_PRI1 0 0x352e 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_RD_PRI_QUANT_PRI2 0 0x352f 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_RD_PRI_QUANT_PRI3 0 0x3530 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_WR_PRI_QUANT_PRI1 0 0x3531 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_WR_PRI_QUANT_PRI2 0 0x3532 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_GMI_WR_PRI_QUANT_PRI3 0 0x3533 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_ADDRNORM_BASE_ADDR0 0 0x3534 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR0 0 0x3535 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_BASE_ADDR1 0 0x3536 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR1 0 0x3537 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_OFFSET_ADDR1 0 0x3538 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA7_ADDRNORM_BASE_ADDR2 0 0x3539 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR2 0 0x353a 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_BASE_ADDR3 0 0x353b 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR3 0 0x353c 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_OFFSET_ADDR3 0 0x353d 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA7_ADDRNORM_BASE_ADDR4 0 0x353e 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR4 0 0x353f 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_BASE_ADDR5 0 0x3540 7 0 1 ADDR_RNG_VAL 0 0 LGCY_MMIO_HOLE_EN 1 1 INTLV_NUM_CHAN 2 5 INTLV_NUM_DIES 6 7 INTLV_NUM_SOCKETS 8 8 INTLV_ADDR_SEL 9 11 BASE_ADDR 12 31 mmMMEA7_ADDRNORM_LIMIT_ADDR5 0 0x3541 2 0 1 DST_FABRIC_ID 0 4 LIMIT_ADDR 12 31 mmMMEA7_ADDRNORM_OFFSET_ADDR5 0 0x3542 2 0 1 HI_ADDR_OFFSET_EN 0 0 HI_ADDR_OFFSET 20 31 mmMMEA7_ADDRNORMDRAM_HOLE_CNTL 0 0x3543 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA7_ADDRNORMGMI_HOLE_CNTL 0 0x3544 2 0 1 DRAM_HOLE_VALID 0 0 DRAM_HOLE_OFFSET 7 15 mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 0 0x3545 2 0 1 LOG2_ADDR64K_SPACE0 0 5 LOG2_ADDR64K_SPACE1 6 11 mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 0 0x3546 2 0 1 LOG2_ADDR64K_SPACE2 0 5 LOG2_ADDR64K_SPACE3 6 11 mmMMEA7_ADDRDEC_BANK_CFG 0 0x3547 6 0 1 BANK_MASK_DRAM 0 5 BANK_MASK_GMI 6 11 BANKGROUP_SEL_DRAM 12 14 BANKGROUP_SEL_GMI 15 17 BANKGROUP_INTERLEAVE_DRAM 18 18 BANKGROUP_INTERLEAVE_GMI 19 19 mmMMEA7_ADDRDEC_MISC_CFG 0 0x3548 11 0 1 VCM_EN0 0 0 VCM_EN1 1 1 VCM_EN2 2 2 PCH_MASK_DRAM 8 8 PCH_MASK_GMI 9 9 CH_MASK_DRAM 12 16 CH_MASK_GMI 17 21 CS_MASK_DRAM 22 23 CS_MASK_GMI 24 25 RM_MASK_DRAM 26 28 RM_MASK_GMI 29 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 0 0x3549 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 0 0x354a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 0 0x354b 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 0 0x354c 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 0 0x354d 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 0 0x354e 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC 0 0x354f 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 0 0x3550 1 0 1 BANK_XOR 0 5 mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 0 0x3551 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 0 0x3552 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE 0 0x3553 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 0 0x3554 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 0 0x3555 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 0 0x3556 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 0 0x3557 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 0 0x3558 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 0 0x3559 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_PC 0 0x355a 3 0 1 XOR_ENABLE 0 0 COL_XOR 1 13 ROW_XOR 14 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 0 0x355b 1 0 1 BANK_XOR 0 5 mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 0 0x355c 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 0 0x355d 2 0 1 XOR_ENABLE 0 0 NA_XOR 1 31 mmMMEA7_ADDRDECGMI_HARVEST_ENABLE 0 0x355e 6 0 1 FORCE_B3_EN 0 0 FORCE_B3_VAL 1 1 FORCE_B4_EN 2 2 FORCE_B4_VAL 3 3 FORCE_B5_EN 4 4 FORCE_B5_VAL 5 5 mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 0 0x355f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 0 0x3560 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 0 0x3561 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 0 0x3562 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 0 0x3563 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 0 0x3564 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 0 0x3565 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 0 0x3566 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 0 0x3567 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 0 0x3568 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 0 0x3569 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 0 0x356a 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 0 0x356b 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 0 0x356c 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 0 0x356d 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 0 0x356e 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 0 0x356f 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 0 0x3570 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 0 0x3571 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 0 0x3572 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 0 0x3573 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 0 0x3574 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC0_RM_SEL_CS01 0 0x3575 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC0_RM_SEL_CS23 0 0x3576 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 0 0x3577 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 0 0x3578 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 0 0x3579 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 0 0x357a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 0 0x357b 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 0 0x357c 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 0 0x357d 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 0 0x357e 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 0 0x357f 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 0 0x3580 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 0 0x3581 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 0 0x3582 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 0 0x3583 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 0 0x3584 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 0 0x3585 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 0 0x3586 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 0 0x3587 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 0 0x3588 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 0 0x3589 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 0 0x358a 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 0 0x358b 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 0 0x358c 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 0 0x358d 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 0 0x358e 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC1_RM_SEL_CS01 0 0x358f 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC1_RM_SEL_CS23 0 0x3590 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 0 0x3591 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 0 0x3592 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 0 0x3593 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 0 0x3594 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 0 0x3595 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 0 0x3596 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 0 0x3597 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 0 0x3598 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 0 0x3599 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 0 0x359a 2 0 1 CS_EN 0 0 BASE_ADDR 1 31 mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 0 0x359b 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 0 0x359c 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 0 0x359d 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 0 0x359e 1 0 1 ADDR_MASK 1 31 mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 0 0x359f 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 0 0x35a0 7 0 1 NUM_BANK_GROUPS 1 3 NUM_RM 4 5 NUM_ROW_LO 8 11 NUM_ROW_HI 12 15 NUM_COL 16 19 NUM_BANKS 20 21 HI_COL_EN 31 31 mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 0 0x35a1 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 0 0x35a2 7 0 1 BANK0 0 3 BANK1 4 7 BANK2 8 11 BANK3 12 15 BANK4 16 20 ROW_LO 24 27 ROW_HI 28 31 mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 0 0x35a3 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 0 0x35a4 1 0 1 BANK5 0 4 mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 0 0x35a5 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 0 0x35a6 8 0 1 COL0 0 3 COL1 4 7 COL2 8 11 COL3 12 15 COL4 16 19 COL5 20 23 COL6 24 27 COL7 28 31 mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 0 0x35a7 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 0 0x35a8 8 0 1 COL8 0 3 COL9 4 7 COL10 8 11 COL11 12 15 COL12 16 19 COL13 20 23 COL14 24 27 COL15 28 31 mmMMEA7_ADDRDEC2_RM_SEL_CS01 0 0x35a9 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC2_RM_SEL_CS23 0 0x35aa 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 0 0x35ab 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 0 0x35ac 6 0 1 RM0 0 3 RM1 4 7 RM2 8 11 CHAN_BIT 12 15 INVERT_ROW_MSBS_EVEN 16 17 INVERT_ROW_MSBS_ODD 18 19 mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL 0 0x35ad 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL 0 0x35ae 3 0 1 GLB_HASH_INTLV_CTL_64K 20 20 GLB_HASH_INTLV_CTL_2M 21 21 GLB_HASH_INTLV_CTL_1G 22 22 mmMMEA7_IO_RD_CLI2GRP_MAP0 0 0x35d5 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_IO_RD_CLI2GRP_MAP1 0 0x35d6 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_IO_WR_CLI2GRP_MAP0 0 0x35d7 16 0 1 CID0_GROUP 0 1 CID1_GROUP 2 3 CID2_GROUP 4 5 CID3_GROUP 6 7 CID4_GROUP 8 9 CID5_GROUP 10 11 CID6_GROUP 12 13 CID7_GROUP 14 15 CID8_GROUP 16 17 CID9_GROUP 18 19 CID10_GROUP 20 21 CID11_GROUP 22 23 CID12_GROUP 24 25 CID13_GROUP 26 27 CID14_GROUP 28 29 CID15_GROUP 30 31 mmMMEA7_IO_WR_CLI2GRP_MAP1 0 0x35d8 16 0 1 CID16_GROUP 0 1 CID17_GROUP 2 3 CID18_GROUP 4 5 CID19_GROUP 6 7 CID20_GROUP 8 9 CID21_GROUP 10 11 CID22_GROUP 12 13 CID23_GROUP 14 15 CID24_GROUP 16 17 CID25_GROUP 18 19 CID26_GROUP 20 21 CID27_GROUP 22 23 CID28_GROUP 24 25 CID29_GROUP 26 27 CID30_GROUP 28 29 CID31_GROUP 30 31 mmMMEA7_IO_RD_COMBINE_FLUSH 0 0x35d9 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA7_IO_WR_COMBINE_FLUSH 0 0x35da 5 0 1 GROUP0_TIMER 0 3 GROUP1_TIMER 4 7 GROUP2_TIMER 8 11 GROUP3_TIMER 12 15 FORWARD_COMB_ONLY 16 16 mmMMEA7_IO_GROUP_BURST 0 0x35db 4 0 1 RD_LIMIT_LO 0 7 RD_LIMIT_HI 8 15 WR_LIMIT_LO 16 23 WR_LIMIT_HI 24 31 mmMMEA7_IO_RD_PRI_AGE 0 0x35dc 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_IO_WR_PRI_AGE 0 0x35dd 8 0 1 GROUP0_AGING_RATE 0 2 GROUP1_AGING_RATE 3 5 GROUP2_AGING_RATE 6 8 GROUP3_AGING_RATE 9 11 GROUP0_AGE_COEFFICIENT 12 14 GROUP1_AGE_COEFFICIENT 15 17 GROUP2_AGE_COEFFICIENT 18 20 GROUP3_AGE_COEFFICIENT 21 23 mmMMEA7_IO_RD_PRI_QUEUING 0 0x35de 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_IO_WR_PRI_QUEUING 0 0x35df 4 0 1 GROUP0_QUEUING_COEFFICIENT 0 2 GROUP1_QUEUING_COEFFICIENT 3 5 GROUP2_QUEUING_COEFFICIENT 6 8 GROUP3_QUEUING_COEFFICIENT 9 11 mmMMEA7_IO_RD_PRI_FIXED 0 0x35e0 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_IO_WR_PRI_FIXED 0 0x35e1 4 0 1 GROUP0_FIXED_COEFFICIENT 0 2 GROUP1_FIXED_COEFFICIENT 3 5 GROUP2_FIXED_COEFFICIENT 6 8 GROUP3_FIXED_COEFFICIENT 9 11 mmMMEA7_IO_RD_PRI_URGENCY 0 0x35e2 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_IO_WR_PRI_URGENCY 0 0x35e3 8 0 1 GROUP0_URGENCY_COEFFICIENT 0 2 GROUP1_URGENCY_COEFFICIENT 3 5 GROUP2_URGENCY_COEFFICIENT 6 8 GROUP3_URGENCY_COEFFICIENT 9 11 GROUP0_URGENCY_MODE 12 12 GROUP1_URGENCY_MODE 13 13 GROUP2_URGENCY_MODE 14 14 GROUP3_URGENCY_MODE 15 15 mmMMEA7_IO_RD_PRI_URGENCY_MASKING 0 0x35e4 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA7_IO_WR_PRI_URGENCY_MASKING 0 0x35e5 32 0 1 CID0_MASK 0 0 CID1_MASK 1 1 CID2_MASK 2 2 CID3_MASK 3 3 CID4_MASK 4 4 CID5_MASK 5 5 CID6_MASK 6 6 CID7_MASK 7 7 CID8_MASK 8 8 CID9_MASK 9 9 CID10_MASK 10 10 CID11_MASK 11 11 CID12_MASK 12 12 CID13_MASK 13 13 CID14_MASK 14 14 CID15_MASK 15 15 CID16_MASK 16 16 CID17_MASK 17 17 CID18_MASK 18 18 CID19_MASK 19 19 CID20_MASK 20 20 CID21_MASK 21 21 CID22_MASK 22 22 CID23_MASK 23 23 CID24_MASK 24 24 CID25_MASK 25 25 CID26_MASK 26 26 CID27_MASK 27 27 CID28_MASK 28 28 CID29_MASK 29 29 CID30_MASK 30 30 CID31_MASK 31 31 mmMMEA7_IO_RD_PRI_QUANT_PRI1 0 0x35e6 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_IO_RD_PRI_QUANT_PRI2 0 0x35e7 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_IO_RD_PRI_QUANT_PRI3 0 0x35e8 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_IO_WR_PRI_QUANT_PRI1 0 0x35e9 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_IO_WR_PRI_QUANT_PRI2 0 0x35ea 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_IO_WR_PRI_QUANT_PRI3 0 0x35eb 4 0 1 GROUP0_THRESHOLD 0 7 GROUP1_THRESHOLD 8 15 GROUP2_THRESHOLD 16 23 GROUP3_THRESHOLD 24 31 mmMMEA7_SDP_ARB_DRAM 0 0x35ec 8 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 mmMMEA7_SDP_ARB_GMI 0 0x35ed 9 0 1 RDWR_BURST_LIMIT_CYCL 0 6 RDWR_BURST_LIMIT_DATA 8 14 EARLY_SW2RD_ON_PRI 16 16 EARLY_SW2WR_ON_PRI 17 17 EARLY_SW2RD_ON_RES 18 18 EARLY_SW2WR_ON_RES 19 19 EOB_ON_EXPIRE 20 20 DECOUPLE_RDWR_BNKSTATE 21 21 ALLOW_CHAIN_BREAKING 22 22 mmMMEA7_SDP_ARB_FINAL 0 0x35ee 15 0 1 DRAM_BURST_LIMIT 0 4 GMI_BURST_LIMIT 5 9 IO_BURST_LIMIT 10 14 BURST_LIMIT_MULTIPLIER 15 16 RDONLY_VC0 17 17 RDONLY_VC1 18 18 RDONLY_VC2 19 19 RDONLY_VC3 20 20 RDONLY_VC4 21 21 RDONLY_VC5 22 22 RDONLY_VC6 23 23 RDONLY_VC7 24 24 ERREVENT_ON_ERROR 25 25 HALTREQ_ON_ERROR 26 26 GMI_BURST_STRETCH 27 27 mmMMEA7_SDP_DRAM_PRIORITY 0 0x35ef 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA7_SDP_GMI_PRIORITY 0 0x35f0 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA7_SDP_IO_PRIORITY 0 0x35f1 8 0 1 RD_GROUP0_PRIORITY 0 3 RD_GROUP1_PRIORITY 4 7 RD_GROUP2_PRIORITY 8 11 RD_GROUP3_PRIORITY 12 15 WR_GROUP0_PRIORITY 16 19 WR_GROUP1_PRIORITY 20 23 WR_GROUP2_PRIORITY 24 27 WR_GROUP3_PRIORITY 28 31 mmMMEA7_SDP_CREDITS 0 0x35f2 3 0 1 TAG_LIMIT 0 7 WR_RESP_CREDITS 8 14 RD_RESP_CREDITS 16 22 mmMMEA7_SDP_TAG_RESERVE0 0 0x35f3 4 0 1 VC0 0 7 VC1 8 15 VC2 16 23 VC3 24 31 mmMMEA7_SDP_TAG_RESERVE1 0 0x35f4 4 0 1 VC4 0 7 VC5 8 15 VC6 16 23 VC7 24 31 mmMMEA7_SDP_VCC_RESERVE0 0 0x35f5 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA7_SDP_VCC_RESERVE1 0 0x35f6 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA7_SDP_VCD_RESERVE0 0 0x35f7 5 0 1 VC0_CREDITS 0 5 VC1_CREDITS 6 11 VC2_CREDITS 12 17 VC3_CREDITS 18 23 VC4_CREDITS 24 29 mmMMEA7_SDP_VCD_RESERVE1 0 0x35f8 4 0 1 VC5_CREDITS 0 5 VC6_CREDITS 6 11 VC7_CREDITS 12 17 DISTRIBUTE_POOL 31 31 mmMMEA7_SDP_REQ_CNTL 0 0x35f9 6 0 1 REQ_PASS_PW_OVERRIDE_READ 0 0 REQ_PASS_PW_OVERRIDE_WRITE 1 1 REQ_PASS_PW_OVERRIDE_ATOMIC 2 2 REQ_CHAIN_OVERRIDE_DRAM 3 3 REQ_CHAIN_OVERRIDE_GMI 4 4 INNER_DOMAIN_MODE 5 5 mmMMEA7_MISC 0 0x35fa 25 0 1 RELATIVE_PRI_IN_DRAM_RD_ARB 0 0 RELATIVE_PRI_IN_DRAM_WR_ARB 1 1 RELATIVE_PRI_IN_GMI_RD_ARB 2 2 RELATIVE_PRI_IN_GMI_WR_ARB 3 3 RELATIVE_PRI_IN_IO_RD_ARB 4 4 RELATIVE_PRI_IN_IO_WR_ARB 5 5 EARLYWRRET_ENABLE_VC0 6 6 EARLYWRRET_ENABLE_VC1 7 7 EARLYWRRET_ENABLE_VC2 8 8 EARLYWRRET_ENABLE_VC3 9 9 EARLYWRRET_ENABLE_VC4 10 10 EARLYWRRET_ENABLE_VC5 11 11 EARLYWRRET_ENABLE_VC6 12 12 EARLYWRRET_ENABLE_VC7 13 13 EARLY_SDP_ORIGDATA 14 14 LINKMGR_DYNAMIC_MODE 15 16 LINKMGR_HALT_THRESHOLD 17 18 LINKMGR_RECONNECT_DELAY 19 20 LINKMGR_IDLE_THRESHOLD 21 25 FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB 26 26 FAVOUR_MIDCHAIN_CS_IN_GMI_ARB 27 27 FAVOUR_LAST_CS_IN_DRAM_ARB 28 28 FAVOUR_LAST_CS_IN_GMI_ARB 29 29 SWITCH_CS_ON_W2R_IN_DRAM_ARB 30 30 SWITCH_CS_ON_W2R_IN_GMI_ARB 31 31 mmMMEA7_LATENCY_SAMPLING 0 0x35fb 16 0 1 SAMPLER0_DRAM 0 0 SAMPLER1_DRAM 1 1 SAMPLER0_GMI 2 2 SAMPLER1_GMI 3 3 SAMPLER0_IO 4 4 SAMPLER1_IO 5 5 SAMPLER0_READ 6 6 SAMPLER1_READ 7 7 SAMPLER0_WRITE 8 8 SAMPLER1_WRITE 9 9 SAMPLER0_ATOMIC_RET 10 10 SAMPLER1_ATOMIC_RET 11 11 SAMPLER0_ATOMIC_NORET 12 12 SAMPLER1_ATOMIC_NORET 13 13 SAMPLER0_VC 14 21 SAMPLER1_VC 22 29 mmMMEA7_PERFCOUNTER_LO 0 0x35fc 1 0 1 COUNTER_LO 0 31 mmMMEA7_PERFCOUNTER_HI 0 0x35fd 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmMMEA7_PERFCOUNTER0_CFG 0 0x35fe 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA7_PERFCOUNTER1_CFG 0 0x35ff 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmMMEA7_PERFCOUNTER_RSLT_CNTL 0 0x3600 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmMMEA7_EDC_CNT 0 0x3606 15 0 1 DRAMRD_CMDMEM_SEC_COUNT 0 1 DRAMRD_CMDMEM_DED_COUNT 2 3 DRAMWR_CMDMEM_SEC_COUNT 4 5 DRAMWR_CMDMEM_DED_COUNT 6 7 DRAMWR_DATAMEM_SEC_COUNT 8 9 DRAMWR_DATAMEM_DED_COUNT 10 11 RRET_TAGMEM_SEC_COUNT 12 13 RRET_TAGMEM_DED_COUNT 14 15 WRET_TAGMEM_SEC_COUNT 16 17 WRET_TAGMEM_DED_COUNT 18 19 DRAMRD_PAGEMEM_SED_COUNT 20 21 DRAMWR_PAGEMEM_SED_COUNT 22 23 IORD_CMDMEM_SED_COUNT 24 25 IOWR_CMDMEM_SED_COUNT 26 27 IOWR_DATAMEM_SED_COUNT 28 29 mmMMEA7_EDC_CNT2 0 0x3607 16 0 1 GMIRD_CMDMEM_SEC_COUNT 0 1 GMIRD_CMDMEM_DED_COUNT 2 3 GMIWR_CMDMEM_SEC_COUNT 4 5 GMIWR_CMDMEM_DED_COUNT 6 7 GMIWR_DATAMEM_SEC_COUNT 8 9 GMIWR_DATAMEM_DED_COUNT 10 11 GMIRD_PAGEMEM_SED_COUNT 12 13 GMIWR_PAGEMEM_SED_COUNT 14 15 MAM_D0MEM_SED_COUNT 16 17 MAM_D1MEM_SED_COUNT 18 19 MAM_D2MEM_SED_COUNT 20 21 MAM_D3MEM_SED_COUNT 22 23 MAM_D0MEM_DED_COUNT 24 25 MAM_D1MEM_DED_COUNT 26 27 MAM_D2MEM_DED_COUNT 28 29 MAM_D3MEM_DED_COUNT 30 31 mmMMEA7_DSM_CNTL 0 0x3608 16 0 1 DRAMRD_CMDMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_CMDMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE 5 5 DRAMWR_DATAMEM_DSM_IRRITATOR_DATA 6 7 DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE 8 8 RRET_TAGMEM_DSM_IRRITATOR_DATA 9 10 RRET_TAGMEM_ENABLE_SINGLE_WRITE 11 11 WRET_TAGMEM_DSM_IRRITATOR_DATA 12 13 WRET_TAGMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_CMDMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_CMDMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_CMDMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_CMDMEM_ENABLE_SINGLE_WRITE 20 20 GMIWR_DATAMEM_DSM_IRRITATOR_DATA 21 22 GMIWR_DATAMEM_ENABLE_SINGLE_WRITE 23 23 mmMMEA7_DSM_CNTLA 0 0x3609 14 0 1 DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA 0 1 DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE 2 2 DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA 3 4 DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE 5 5 IORD_CMDMEM_DSM_IRRITATOR_DATA 6 7 IORD_CMDMEM_ENABLE_SINGLE_WRITE 8 8 IOWR_CMDMEM_DSM_IRRITATOR_DATA 9 10 IOWR_CMDMEM_ENABLE_SINGLE_WRITE 11 11 IOWR_DATAMEM_DSM_IRRITATOR_DATA 12 13 IOWR_DATAMEM_ENABLE_SINGLE_WRITE 14 14 GMIRD_PAGEMEM_DSM_IRRITATOR_DATA 15 16 GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE 17 17 GMIWR_PAGEMEM_DSM_IRRITATOR_DATA 18 19 GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE 20 20 mmMMEA7_DSM_CNTLB 0 0x360a 0 0 1 mmMMEA7_DSM_CNTL2 0 0x360b 17 0 1 DRAMRD_CMDMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_CMDMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_CMDMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_CMDMEM_SELECT_INJECT_DELAY 5 5 DRAMWR_DATAMEM_ENABLE_ERROR_INJECT 6 7 DRAMWR_DATAMEM_SELECT_INJECT_DELAY 8 8 RRET_TAGMEM_ENABLE_ERROR_INJECT 9 10 RRET_TAGMEM_SELECT_INJECT_DELAY 11 11 WRET_TAGMEM_ENABLE_ERROR_INJECT 12 13 WRET_TAGMEM_SELECT_INJECT_DELAY 14 14 GMIRD_CMDMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_CMDMEM_SELECT_INJECT_DELAY 17 17 GMIWR_CMDMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_CMDMEM_SELECT_INJECT_DELAY 20 20 GMIWR_DATAMEM_ENABLE_ERROR_INJECT 21 22 GMIWR_DATAMEM_SELECT_INJECT_DELAY 23 23 INJECT_DELAY 26 31 mmMMEA7_DSM_CNTL2A 0 0x360c 14 0 1 DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT 0 1 DRAMRD_PAGEMEM_SELECT_INJECT_DELAY 2 2 DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT 3 4 DRAMWR_PAGEMEM_SELECT_INJECT_DELAY 5 5 IORD_CMDMEM_ENABLE_ERROR_INJECT 6 7 IORD_CMDMEM_SELECT_INJECT_DELAY 8 8 IOWR_CMDMEM_ENABLE_ERROR_INJECT 9 10 IOWR_CMDMEM_SELECT_INJECT_DELAY 11 11 IOWR_DATAMEM_ENABLE_ERROR_INJECT 12 13 IOWR_DATAMEM_SELECT_INJECT_DELAY 14 14 GMIRD_PAGEMEM_ENABLE_ERROR_INJECT 15 16 GMIRD_PAGEMEM_SELECT_INJECT_DELAY 17 17 GMIWR_PAGEMEM_ENABLE_ERROR_INJECT 18 19 GMIWR_PAGEMEM_SELECT_INJECT_DELAY 20 20 mmMMEA7_DSM_CNTL2B 0 0x360d 0 0 1 mmMMEA7_CGTT_CLK_CTRL 0 0x360f 12 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SPARE0 12 19 SOFT_STALL_OVERRIDE_WRITE 20 20 SOFT_STALL_OVERRIDE_READ 21 21 SOFT_STALL_OVERRIDE_RETURN 22 22 SPARE1 23 26 LS_OVERRIDE 27 27 SOFT_OVERRIDE_WRITE 28 28 SOFT_OVERRIDE_READ 29 29 SOFT_OVERRIDE_RETURN 30 30 SOFT_OVERRIDE_REGISTER 31 31 mmMMEA7_EDC_MODE 0 0x3610 5 0 1 COUNT_FED_OUT 16 16 GATE_FUE 17 17 DED_MODE 20 21 PROP_FED 29 29 BYPASS 31 31 mmMMEA7_ERR_STATUS 0 0x3611 7 0 1 SDP_RDRSP_STATUS 0 3 SDP_WRRSP_STATUS 4 7 SDP_RDRSP_DATASTATUS 8 9 SDP_RDRSP_DATAPARITY_ERROR 10 10 CLEAR_ERROR_STATUS 11 11 BUSY_ON_ERROR 12 12 FUE_FLAG 13 13 mmMMEA7_MISC2 0 0x3612 6 0 1 CSGROUP_SWAP_IN_DRAM_ARB 0 0 CSGROUP_SWAP_IN_GMI_ARB 1 1 CSGRP_BURST_LIMIT_DATA_DRAM 2 6 CSGRP_BURST_LIMIT_DATA_GMI 7 11 IO_RDWR_PRIORITY_ENABLE 12 12 RRET_SWAP_MODE 13 13 mmMMEA7_ADDRDEC_SELECT 0 0x3613 4 0 1 DRAM_ADDRDEC_CHANNEL_START 0 4 DRAM_ADDRDEC_CHANNEL_END 5 9 GMI_ADDRDEC_CHANNEL_START 10 14 GMI_ADDRDEC_CHANNEL_END 15 19 mmMMEA7_EDC_CNT3 0 0x3614 7 0 1 DRAMRD_PAGEMEM_DED_COUNT 0 1 DRAMWR_PAGEMEM_DED_COUNT 2 3 IORD_CMDMEM_DED_COUNT 4 5 IOWR_CMDMEM_DED_COUNT 6 7 IOWR_DATAMEM_DED_COUNT 8 9 GMIRD_PAGEMEM_DED_COUNT 10 11 GMIWR_PAGEMEM_DED_COUNT 12 13 mmPCTL1_CTRL 0 0x38c0 16 0 1 PG_ENABLE 0 0 ALLOW_DEEP_SLEEP_MODE 1 3 STCTRL_RSMU_IDLE_THRESHOLD 4 10 STCTRL_DAGB_IDLE_THRESHOLD 11 15 STCTRL_IGNORE_PROTECTION_FAULT 16 16 OVR_EA0_SDP_PARTACK 17 17 OVR_EA1_SDP_PARTACK 18 18 OVR_EA2_SDP_PARTACK 19 19 OVR_EA3_SDP_PARTACK 20 20 OVR_EA4_SDP_PARTACK 21 21 OVR_EA0_SDP_FULLACK 22 22 OVR_EA1_SDP_FULLACK 23 23 OVR_EA2_SDP_FULLACK 24 24 OVR_EA3_SDP_FULLACK 25 25 OVR_EA4_SDP_FULLACK 26 26 PGFSM_CMD_STATUS 27 28 mmPCTL1_MMHUB_DEEPSLEEP_IB 0 0x38c1 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 SETCLEAR 31 31 mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE 0 0x38c2 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 0 0x38c3 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_PG_IGNORE_DEEPSLEEP 0 0x38c4 19 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 DS_ATHUB 17 17 ALLIPS 18 18 mmPCTL1_PG_IGNORE_DEEPSLEEP_IB 0 0x38c5 18 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 ALLIPS 17 17 mmPCTL1_SLICE0_CFG_DAGB_BUSY 0 0x38c6 1 0 1 DB_LNCFG 0 31 mmPCTL1_SLICE0_CFG_DS_ALLOW 0 0x38c7 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE0_CFG_DS_ALLOW_IB 0 0x38c8 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE1_CFG_DAGB_BUSY 0 0x38c9 1 0 1 DB_LNCFG 0 31 mmPCTL1_SLICE1_CFG_DS_ALLOW 0 0x38ca 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE1_CFG_DS_ALLOW_IB 0 0x38cb 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE2_CFG_DAGB_BUSY 0 0x38cc 1 0 1 DB_LNCFG 0 31 mmPCTL1_SLICE2_CFG_DS_ALLOW 0 0x38cd 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE2_CFG_DS_ALLOW_IB 0 0x38ce 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE3_CFG_DAGB_BUSY 0 0x38cf 1 0 1 DB_LNCFG 0 31 mmPCTL1_SLICE3_CFG_DS_ALLOW 0 0x38d0 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE3_CFG_DS_ALLOW_IB 0 0x38d1 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE4_CFG_DAGB_BUSY 0 0x38d2 1 0 1 DB_LNCFG 0 31 mmPCTL1_SLICE4_CFG_DS_ALLOW 0 0x38d3 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_SLICE4_CFG_DS_ALLOW_IB 0 0x38d4 17 0 1 DS0 0 0 DS1 1 1 DS2 2 2 DS3 3 3 DS4 4 4 DS5 5 5 DS6 6 6 DS7 7 7 DS8 8 8 DS9 9 9 DS10 10 10 DS11 11 11 DS12 12 12 DS13 13 13 DS14 14 14 DS15 15 15 DS16 16 16 mmPCTL1_UTCL2_MISC 0 0x38d5 6 0 1 CRITICAL_REGS_LOCK 11 11 TILE_IDLE_THRESHOLD 12 14 RENG_MEM_LS_ENABLE 15 15 STCTRL_FORCE_PGFSM_CMD_DONE 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_SLICE0_MISC 0 0x38d6 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_SLICE1_MISC 0 0x38d7 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_SLICE2_MISC 0 0x38d8 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_SLICE3_MISC 0 0x38d9 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_SLICE4_MISC 0 0x38da 7 0 1 CRITICAL_REGS_LOCK 10 10 TILE_IDLE_THRESHOLD 11 13 RENG_MEM_LS_ENABLE 14 14 STCTRL_FORCE_PGFSM_CMD_DONE 15 15 DEEPSLEEP_DISCSDP 16 16 RENG_EXECUTE_ON_REG_UPDATE 17 17 RD_TIMER_ENABLE 18 18 mmPCTL1_UTCL2_RENG_EXECUTE 0 0x38db 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 12 RENG_EXECUTE_END_PTR 13 23 mmPCTL1_SLICE0_RENG_EXECUTE 0 0x38dc 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL1_SLICE1_RENG_EXECUTE 0 0x38dd 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL1_SLICE2_RENG_EXECUTE 0 0x38de 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL1_SLICE3_RENG_EXECUTE 0 0x38df 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL1_SLICE4_RENG_EXECUTE 0 0x38e0 4 0 1 RENG_EXECUTE_NOW 0 0 RENG_EXECUTE_NOW_MODE 1 1 RENG_EXECUTE_NOW_START_PTR 2 11 RENG_EXECUTE_END_PTR 12 21 mmPCTL1_UTCL2_RENG_RAM_INDEX 0 0x38e1 1 0 1 RENG_RAM_INDEX 0 10 mmPCTL1_UTCL2_RENG_RAM_DATA 0 0x38e2 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_SLICE0_RENG_RAM_INDEX 0 0x38e3 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL1_SLICE0_RENG_RAM_DATA 0 0x38e4 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_SLICE1_RENG_RAM_INDEX 0 0x38e5 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL1_SLICE1_RENG_RAM_DATA 0 0x38e6 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_SLICE2_RENG_RAM_INDEX 0 0x38e7 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL1_SLICE2_RENG_RAM_DATA 0 0x38e8 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_SLICE3_RENG_RAM_INDEX 0 0x38e9 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL1_SLICE3_RENG_RAM_DATA 0 0x38ea 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_SLICE4_RENG_RAM_INDEX 0 0x38eb 1 0 1 RENG_RAM_INDEX 0 9 mmPCTL1_SLICE4_RENG_RAM_DATA 0 0x38ec 1 0 1 RENG_RAM_DATA 0 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0 0x38ed 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0 0x38ee 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0 0x38ef 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0 0x38f0 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0 0x38f1 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x38f2 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x38f3 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0 0x38f4 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0 0x38f5 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0 0x38f6 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0 0x38f7 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0 0x38f8 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x38f9 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x38fa 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0 0x38fb 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0 0x38fc 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0 0x38fd 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0 0x38fe 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0 0x38ff 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3900 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3901 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0 0x3902 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0 0x3903 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0 0x3904 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0 0x3905 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0 0x3906 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3907 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3908 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0 0x3909 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0 0x390a 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0 0x390b 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0 0x390c 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0 0x390d 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x390e 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x390f 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0 0x3910 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0 0x3911 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0 0x3912 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0 0x3913 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0 0x3914 2 0 1 STCTRL_REGISTER_SAVE_BASE 0 15 STCTRL_REGISTER_SAVE_LIMIT 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0 0x3915 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0 0x3916 2 0 1 STCTRL_REGISTER_SAVE_EXCL0 0 15 STCTRL_REGISTER_SAVE_EXCL1 16 31 mmVML1_1_MC_VM_MX_L1_TLB0_STATUS 0 0x3948 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB1_STATUS 0 0x3949 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB2_STATUS 0 0x394a 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB3_STATUS 0 0x394b 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB4_STATUS 0 0x394c 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB5_STATUS 0 0x394d 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB6_STATUS 0 0x394e 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1_1_MC_VM_MX_L1_TLB7_STATUS 0 0x394f 2 0 1 BUSY 0 0 FOUND_PARITY_ERRORS 1 1 mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 0 0x3960 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 0 0x3961 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 0 0x3962 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 0 0x3963 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0 0x3964 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 0 0x3970 1 0 1 COUNTER_LO 0 31 mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 0 0x3971 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATCL2_1_ATC_L2_CNTL 0 0x3980 10 0 1 NUMBER_OF_TRANSLATION_READ_REQUESTS 0 1 NUMBER_OF_TRANSLATION_WRITE_REQUESTS 3 4 NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 6 6 NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 7 7 NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS 8 9 NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS 11 12 NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD 14 14 NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD 15 15 CACHE_INVALIDATE_MODE 16 18 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 19 19 mmATCL2_1_ATC_L2_CNTL2 0 0x3981 8 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE 8 8 L2_CACHE_SWAP_TAG_INDEX_LSBS 9 11 L2_CACHE_VMID_MODE 12 14 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 15 20 L2_BIGK_FRAGMENT_SIZE 21 26 L2_4K_BIGK_SWAP_ENABLE 27 27 mmATCL2_1_ATC_L2_CACHE_DATA0 0 0x3984 4 0 1 DATA_REGISTER_VALID 0 0 CACHE_ENTRY_VALID 1 1 CACHED_ATTRIBUTES 2 22 VIRTUAL_PAGE_ADDRESS_HIGH 23 26 mmATCL2_1_ATC_L2_CACHE_DATA1 0 0x3985 1 0 1 VIRTUAL_PAGE_ADDRESS_LOW 0 31 mmATCL2_1_ATC_L2_CACHE_DATA2 0 0x3986 1 0 1 PHYSICAL_PAGE_ADDRESS 0 31 mmATCL2_1_ATC_L2_CNTL3 0 0x3987 3 0 1 DELAY_SEND_INVALIDATION_REQUEST 0 2 ATS_REQUEST_CREDIT_MINUS1 3 8 COMPCLKREQ_OFF_HYSTERESIS 9 11 mmATCL2_1_ATC_L2_STATUS 0 0x3988 2 0 1 BUSY 0 0 PARITY_ERROR_INFO 1 30 mmATCL2_1_ATC_L2_STATUS2 0 0x3989 2 0 1 IFIFO_NON_FATAL_PARITY_ERROR_INFO 0 7 IFIFO_FATAL_PARITY_ERROR_INFO 8 15 mmATCL2_1_ATC_L2_STATUS3 0 0x398a 2 0 1 BUSY 0 0 PARITY_ERROR_INFO 1 30 mmATCL2_1_ATC_L2_MISC_CG 0 0x398b 3 0 1 OFFDLY 6 11 ENABLE 18 18 MEM_LS_ENABLE 19 19 mmATCL2_1_ATC_L2_MEM_POWER_LS 0 0x398c 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmATCL2_1_ATC_L2_CGTT_CLK_CTRL 0 0x398d 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 0 0x398e 1 0 1 INDEX 0 7 mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 0 0x398f 1 0 1 INDEX 0 7 mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 0 0x3990 9 0 1 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 0 0x3991 9 0 1 INJECT_DELAY 0 5 DSM_IRRITATOR_DATA 6 7 ENABLE_SINGLE_WRITE 8 8 ENABLE_ERROR_INJECT 9 10 SELECT_INJECT_DELAY 11 11 WRITE_COUNTERS 12 12 SEC_COUNT 13 14 DED_COUNT 15 16 TEST_FUE 17 17 mmATCL2_1_ATC_L2_CNTL4 0 0x3992 2 0 1 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 0 9 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 10 19 mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 0 0x3993 1 0 1 GROUP_RT_CLASS 0 31 mmVML2PF1_VM_L2_CNTL 0 0x39c0 14 0 1 ENABLE_L2_CACHE 0 0 ENABLE_L2_FRAGMENT_PROCESSING 1 1 L2_CACHE_PTE_ENDIAN_SWAP_MODE 2 3 L2_CACHE_PDE_ENDIAN_SWAP_MODE 4 5 L2_PDE0_CACHE_TAG_GENERATION_MODE 8 8 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE 9 9 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE 10 10 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY 11 11 L2_PDE0_CACHE_SPLIT_MODE 12 14 EFFECTIVE_L2_QUEUE_SIZE 15 17 PDE_FAULT_CLASSIFICATION 18 18 CONTEXT1_IDENTITY_ACCESS_MODE 19 20 IDENTITY_MODE_FRAGMENT_SIZE 21 25 L2_PTE_CACHE_ADDR_MODE 26 27 mmVML2PF1_VM_L2_CNTL2 0 0x39c1 7 0 1 INVALIDATE_ALL_L1_TLBS 0 0 INVALIDATE_L2_CACHE 1 1 DISABLE_INVALIDATE_PER_DOMAIN 21 21 DISABLE_BIGK_CACHE_OPTIMIZATION 22 22 L2_PTE_CACHE_VMID_MODE 23 25 INVALIDATE_CACHE_MODE 26 27 PDE_CACHE_EFFECTIVE_SIZE 28 30 mmVML2PF1_VM_L2_CNTL3 0 0x39c2 11 0 1 BANK_SELECT 0 5 L2_CACHE_UPDATE_MODE 6 7 L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE 8 12 L2_CACHE_BIGK_FRAGMENT_SIZE 15 19 L2_CACHE_BIGK_ASSOCIATIVITY 20 20 L2_CACHE_4K_EFFECTIVE_SIZE 21 23 L2_CACHE_BIGK_EFFECTIVE_SIZE 24 27 L2_CACHE_4K_FORCE_MISS 28 28 L2_CACHE_BIGK_FORCE_MISS 29 29 PDE_CACHE_FORCE_MISS 30 30 L2_CACHE_4K_ASSOCIATIVITY 31 31 mmVML2PF1_VM_L2_STATUS 0 0x39c3 7 0 1 L2_BUSY 0 0 CONTEXT_DOMAIN_BUSY 1 16 FOUND_4K_PTE_CACHE_PARITY_ERRORS 17 17 FOUND_BIGK_PTE_CACHE_PARITY_ERRORS 18 18 FOUND_PDE0_CACHE_PARITY_ERRORS 19 19 FOUND_PDE1_CACHE_PARITY_ERRORS 20 20 FOUND_PDE2_CACHE_PARITY_ERRORS 21 21 mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 0 0x39c4 3 0 1 DUMMY_PAGE_FAULT_ENABLE 0 0 DUMMY_PAGE_ADDRESS_LOGICAL 1 1 DUMMY_PAGE_COMPARE_MSBS 2 7 mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0 0x39c5 1 0 1 DUMMY_PAGE_ADDR_LO32 0 31 mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0 0x39c6 1 0 1 DUMMY_PAGE_ADDR_HI4 0 3 mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL 0 0x39c7 17 0 1 CLEAR_PROTECTION_FAULT_STATUS_ADDR 0 0 ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES 1 1 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 2 2 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 3 3 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT 4 4 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT 5 5 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT 6 6 NACK_PROTECTION_FAULT_ENABLE_DEFAULT 7 7 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 8 8 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 9 9 READ_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 11 11 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 13 28 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 29 29 CRASH_ON_NO_RETRY_FAULT 30 30 CRASH_ON_RETRY_FAULT 31 31 mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 0 0x39c8 5 0 1 CLIENT_ID_PRT_FAULT_INTERRUPT 0 15 OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT 16 16 ACTIVE_PAGE_MIGRATION_PTE 17 17 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY 18 18 ENABLE_RETRY_FAULT_INTERRUPT 19 19 mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 0 0x39c9 1 0 1 VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 0 0x39ca 1 0 1 VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT 0 31 mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS 0 0x39cb 10 0 1 MORE_FAULTS 0 0 WALKER_ERROR 1 3 PERMISSION_FAULTS 4 7 MAPPING_ERROR 8 8 CID 9 17 RW 18 18 ATOMIC 19 19 VMID 20 23 VF 24 24 VFID 25 28 mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 0 0x39cc 1 0 1 LOGICAL_PAGE_ADDR_LO32 0 31 mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 0 0x39cd 1 0 1 LOGICAL_PAGE_ADDR_HI4 0 3 mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0 0x39ce 1 0 1 PHYSICAL_PAGE_ADDR_LO32 0 31 mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0 0x39cf 1 0 1 PHYSICAL_PAGE_ADDR_HI4 0 3 mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0 0x39d1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0 0x39d2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0 0x39d3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0 0x39d4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0 0x39d5 1 0 1 PHYSICAL_PAGE_OFFSET_LO32 0 31 mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0 0x39d6 1 0 1 PHYSICAL_PAGE_OFFSET_HI4 0 3 mmVML2PF1_VM_L2_CNTL4 0 0x39d7 6 0 1 L2_CACHE_4K_PARTITION_COUNT 0 5 VMC_TAP_PDE_REQUEST_PHYSICAL 6 6 VMC_TAP_PTE_REQUEST_PHYSICAL 7 7 MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 8 17 MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT 18 27 BPM_CGCGLS_OVERRIDE 28 28 mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES 0 0x39d8 32 0 1 GROUP_0_RT_CLASS 0 0 GROUP_1_RT_CLASS 1 1 GROUP_2_RT_CLASS 2 2 GROUP_3_RT_CLASS 3 3 GROUP_4_RT_CLASS 4 4 GROUP_5_RT_CLASS 5 5 GROUP_6_RT_CLASS 6 6 GROUP_7_RT_CLASS 7 7 GROUP_8_RT_CLASS 8 8 GROUP_9_RT_CLASS 9 9 GROUP_10_RT_CLASS 10 10 GROUP_11_RT_CLASS 11 11 GROUP_12_RT_CLASS 12 12 GROUP_13_RT_CLASS 13 13 GROUP_14_RT_CLASS 14 14 GROUP_15_RT_CLASS 15 15 GROUP_16_RT_CLASS 16 16 GROUP_17_RT_CLASS 17 17 GROUP_18_RT_CLASS 18 18 GROUP_19_RT_CLASS 19 19 GROUP_20_RT_CLASS 20 20 GROUP_21_RT_CLASS 21 21 GROUP_22_RT_CLASS 22 22 GROUP_23_RT_CLASS 23 23 GROUP_24_RT_CLASS 24 24 GROUP_25_RT_CLASS 25 25 GROUP_26_RT_CLASS 26 26 GROUP_27_RT_CLASS 27 27 GROUP_28_RT_CLASS 28 28 GROUP_29_RT_CLASS 29 29 GROUP_30_RT_CLASS 30 30 GROUP_31_RT_CLASS 31 31 mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 0 0x39d9 5 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 0 0x39da 5 0 1 RESERVED_READ_CLIENT_ID 0 8 RESERVED_WRITE_CLIENT_ID 10 18 ENABLE 20 20 RESERVED_CACHE_INVALIDATION_MODE 24 24 RESERVED_CACHE_PRIVATE_INVALIDATION 25 25 mmVML2PF1_VM_L2_CACHE_PARITY_CNTL 0 0x39db 9 0 1 ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES 0 0 ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES 1 1 ENABLE_PARITY_CHECKS_IN_PDE_CACHES 2 2 FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE 3 3 FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE 4 4 FORCE_PARITY_MISMATCH_IN_PDE_CACHE 5 5 FORCE_CACHE_BANK 6 8 FORCE_CACHE_NUMBER 9 11 FORCE_CACHE_ASSOC 12 15 mmVML2PF1_VM_L2_CGTT_CLK_CTRL 0 0x39de 5 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVML2VC1_VM_CONTEXT0_CNTL 0 0x3a00 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT1_CNTL 0 0x3a01 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT2_CNTL 0 0x3a02 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT3_CNTL 0 0x3a03 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT4_CNTL 0 0x3a04 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT5_CNTL 0 0x3a05 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT6_CNTL 0 0x3a06 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT7_CNTL 0 0x3a07 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT8_CNTL 0 0x3a08 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT9_CNTL 0 0x3a09 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT10_CNTL 0 0x3a0a 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT11_CNTL 0 0x3a0b 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT12_CNTL 0 0x3a0c 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT13_CNTL 0 0x3a0d 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT14_CNTL 0 0x3a0e 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXT15_CNTL 0 0x3a0f 19 0 1 ENABLE_CONTEXT 0 0 PAGE_TABLE_DEPTH 1 2 PAGE_TABLE_BLOCK_SIZE 3 6 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT 7 7 RETRY_OTHER_FAULT 8 8 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT 9 9 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT 10 10 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT 11 11 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT 12 12 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT 13 13 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT 14 14 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT 15 15 VALID_PROTECTION_FAULT_ENABLE_DEFAULT 16 16 READ_PROTECTION_FAULT_ENABLE_INTERRUPT 17 17 READ_PROTECTION_FAULT_ENABLE_DEFAULT 18 18 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT 19 19 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT 20 20 EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT 21 21 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT 22 22 mmVML2VC1_VM_CONTEXTS_DISABLE 0 0x3a10 16 0 1 DISABLE_CONTEXT_0 0 0 DISABLE_CONTEXT_1 1 1 DISABLE_CONTEXT_2 2 2 DISABLE_CONTEXT_3 3 3 DISABLE_CONTEXT_4 4 4 DISABLE_CONTEXT_5 5 5 DISABLE_CONTEXT_6 6 6 DISABLE_CONTEXT_7 7 7 DISABLE_CONTEXT_8 8 8 DISABLE_CONTEXT_9 9 9 DISABLE_CONTEXT_10 10 10 DISABLE_CONTEXT_11 11 11 DISABLE_CONTEXT_12 12 12 DISABLE_CONTEXT_13 13 13 DISABLE_CONTEXT_14 14 14 DISABLE_CONTEXT_15 15 15 mmVML2VC1_VM_INVALIDATE_ENG0_SEM 0 0x3a11 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG1_SEM 0 0x3a12 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG2_SEM 0 0x3a13 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG3_SEM 0 0x3a14 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG4_SEM 0 0x3a15 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG5_SEM 0 0x3a16 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG6_SEM 0 0x3a17 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG7_SEM 0 0x3a18 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG8_SEM 0 0x3a19 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG9_SEM 0 0x3a1a 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG10_SEM 0 0x3a1b 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG11_SEM 0 0x3a1c 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG12_SEM 0 0x3a1d 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG13_SEM 0 0x3a1e 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG14_SEM 0 0x3a1f 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG15_SEM 0 0x3a20 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG16_SEM 0 0x3a21 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG17_SEM 0 0x3a22 1 0 1 SEMAPHORE 0 0 mmVML2VC1_VM_INVALIDATE_ENG0_REQ 0 0x3a23 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG1_REQ 0 0x3a24 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG2_REQ 0 0x3a25 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG3_REQ 0 0x3a26 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG4_REQ 0 0x3a27 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG5_REQ 0 0x3a28 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG6_REQ 0 0x3a29 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG7_REQ 0 0x3a2a 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG8_REQ 0 0x3a2b 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG9_REQ 0 0x3a2c 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG10_REQ 0 0x3a2d 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG11_REQ 0 0x3a2e 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG12_REQ 0 0x3a2f 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG13_REQ 0 0x3a30 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG14_REQ 0 0x3a31 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG15_REQ 0 0x3a32 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG16_REQ 0 0x3a33 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG17_REQ 0 0x3a34 8 0 1 PER_VMID_INVALIDATE_REQ 0 15 FLUSH_TYPE 16 17 INVALIDATE_L2_PTES 18 18 INVALIDATE_L2_PDE0 19 19 INVALIDATE_L2_PDE1 20 20 INVALIDATE_L2_PDE2 21 21 INVALIDATE_L1_PTES 22 22 CLEAR_PROTECTION_FAULT_STATUS_ADDR 23 23 mmVML2VC1_VM_INVALIDATE_ENG0_ACK 0 0x3a35 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG1_ACK 0 0x3a36 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG2_ACK 0 0x3a37 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG3_ACK 0 0x3a38 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG4_ACK 0 0x3a39 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG5_ACK 0 0x3a3a 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG6_ACK 0 0x3a3b 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG7_ACK 0 0x3a3c 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG8_ACK 0 0x3a3d 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG9_ACK 0 0x3a3e 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG10_ACK 0 0x3a3f 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG11_ACK 0 0x3a40 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG12_ACK 0 0x3a41 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG13_ACK 0 0x3a42 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG14_ACK 0 0x3a43 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG15_ACK 0 0x3a44 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG16_ACK 0 0x3a45 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG17_ACK 0 0x3a46 2 0 1 PER_VMID_INVALIDATE_ACK 0 15 SEMAPHORE 16 16 mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0 0x3a47 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0 0x3a48 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0 0x3a49 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0 0x3a4a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0 0x3a4b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0 0x3a4c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0 0x3a4d 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0 0x3a4e 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0 0x3a4f 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0 0x3a50 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0 0x3a51 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0 0x3a52 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0 0x3a53 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0 0x3a54 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0 0x3a55 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0 0x3a56 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0 0x3a57 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0 0x3a58 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0 0x3a59 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0 0x3a5a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0 0x3a5b 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0 0x3a5c 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0 0x3a5d 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0 0x3a5e 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0 0x3a5f 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0 0x3a60 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0 0x3a61 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0 0x3a62 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0 0x3a63 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0 0x3a64 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0 0x3a65 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0 0x3a66 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0 0x3a67 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0 0x3a68 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0 0x3a69 2 0 1 S_BIT 0 0 LOGI_PAGE_ADDR_RANGE_LO31 1 31 mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0 0x3a6a 1 0 1 LOGI_PAGE_ADDR_RANGE_HI5 0 4 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a6b 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a6c 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a6d 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a6e 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a6f 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a70 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a71 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a72 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a73 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a74 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a75 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a76 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a77 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a78 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a79 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a7a 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a7b 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a7c 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a7d 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a7e 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a7f 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a80 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a81 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a82 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a83 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a84 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a85 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a86 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a87 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a88 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0 0x3a89 1 0 1 PAGE_DIRECTORY_ENTRY_LO32 0 31 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0 0x3a8a 1 0 1 PAGE_DIRECTORY_ENTRY_HI32 0 31 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0 0x3a8b 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0 0x3a8c 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0 0x3a8d 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0 0x3a8e 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0 0x3a8f 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0 0x3a90 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0 0x3a91 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0 0x3a92 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0 0x3a93 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0 0x3a94 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0 0x3a95 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0 0x3a96 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0 0x3a97 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0 0x3a98 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0 0x3a99 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0 0x3a9a 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0 0x3a9b 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0 0x3a9c 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0 0x3a9d 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0 0x3a9e 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0 0x3a9f 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0 0x3aa0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0 0x3aa1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0 0x3aa2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0 0x3aa3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0 0x3aa4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0 0x3aa5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0 0x3aa6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0 0x3aa7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0 0x3aa8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0 0x3aa9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0 0x3aaa 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0 0x3aab 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0 0x3aac 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0 0x3aad 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0 0x3aae 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0 0x3aaf 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0 0x3ab0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0 0x3ab1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0 0x3ab2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0 0x3ab3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0 0x3ab4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0 0x3ab5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0 0x3ab6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0 0x3ab7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0 0x3ab8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0 0x3ab9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0 0x3aba 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0 0x3abb 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0 0x3abc 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0 0x3abd 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0 0x3abe 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0 0x3abf 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0 0x3ac0 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0 0x3ac1 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0 0x3ac2 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0 0x3ac3 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0 0x3ac4 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0 0x3ac5 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0 0x3ac6 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0 0x3ac7 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0 0x3ac8 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0 0x3ac9 1 0 1 LOGICAL_PAGE_NUMBER_LO32 0 31 mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0 0x3aca 1 0 1 LOGICAL_PAGE_NUMBER_HI4 0 3 mmVMSHAREDPF1_MC_VM_NB_MMIOBASE 0 0x3ae4 1 0 1 MMIOBASE 0 31 mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT 0 0x3ae5 1 0 1 MMIOLIMIT 0 31 mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL 0 0x3ae6 1 0 1 MMIOENABLE 23 23 mmVMSHAREDPF1_MC_VM_NB_PCI_ARB 0 0x3ae7 1 0 1 VGA_HOLE 3 3 mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 0 0x3ae8 1 0 1 TOP_OF_DRAM 23 31 mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 0 0x3ae9 2 0 1 ENABLE 0 0 LOWER_TOM2 23 31 mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 0 0x3aea 1 0 1 UPPER_TOM2 0 11 mmVMSHAREDPF1_MC_VM_FB_OFFSET 0 0x3aeb 1 0 1 FB_OFFSET 0 23 mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0 0x3aec 1 0 1 PHYSICAL_PAGE_NUMBER_LSB 0 31 mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0 0x3aed 1 0 1 PHYSICAL_PAGE_NUMBER_MSB 0 3 mmVMSHAREDPF1_MC_VM_STEERING 0 0x3aee 1 0 1 DEFAULT_STEERING 0 1 mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 0 0x3aef 2 0 1 VF 0 15 PF 31 31 mmVMSHAREDPF1_MC_MEM_POWER_LS 0 0x3af0 2 0 1 LS_SETUP 0 5 LS_HOLD 6 11 mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0 0x3af1 1 0 1 ADDRESS 0 19 mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0 0x3af2 1 0 1 ADDRESS 0 19 mmVMSHAREDPF1_MC_VM_APT_CNTL 0 0x3af3 2 0 1 FORCE_MTYPE_UC 0 0 DIRECT_SYSTEM_EN 1 1 mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 0 0x3af4 1 0 1 ADDRESS 0 19 mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 0 0x3af5 1 0 1 ADDRESS 0 19 mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0 0x3af6 1 0 1 LOCK 0 0 mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 0 0x3af7 2 0 1 PF_LFB_REGION 0 3 PF_MAX_REGION 4 7 mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 0 0x3af8 1 0 1 PF_LFB_SIZE 0 16 mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 0 0x3af9 1 0 1 ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE 0 0 mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE 0 0x3b00 1 0 1 FB_BASE 0 23 mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP 0 0x3b01 1 0 1 FB_TOP 0 23 mmVMSHAREDVC1_MC_VM_AGP_TOP 0 0x3b02 1 0 1 AGP_TOP 0 23 mmVMSHAREDVC1_MC_VM_AGP_BOT 0 0x3b03 1 0 1 AGP_BOT 0 23 mmVMSHAREDVC1_MC_VM_AGP_BASE 0 0x3b04 1 0 1 AGP_BASE 0 23 mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0 0x3b05 1 0 1 LOGICAL_ADDR 0 29 mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0 0x3b06 1 0 1 LOGICAL_ADDR 0 29 mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 0 0x3b07 7 0 1 ENABLE_L1_TLB 0 0 SYSTEM_ACCESS_MODE 3 4 SYSTEM_APERTURE_UNMAPPED_ACCESS 5 5 ENABLE_ADVANCED_DRIVER_MODEL 6 6 ECO_BITS 7 10 MTYPE 11 12 ATC_EN 13 13 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 0 0x3b20 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 0 0x3b21 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 0 0x3b22 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 0 0x3b23 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 0 0x3b24 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 0 0x3b25 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 0 0x3b26 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 0 0x3b27 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 0 0x3b28 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 0 0x3b29 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 0 0x3b2a 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 0 0x3b2b 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 0 0x3b2c 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 0 0x3b2d 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 0 0x3b2e 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 0 0x3b2f 2 0 1 VF_FB_SIZE 0 15 VF_FB_OFFSET 16 31 mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 0 0x3b30 1 0 1 MARC_EN 8 8 mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 0 0x3b31 1 0 1 MARC_BASE_LO_0 12 31 mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 0 0x3b32 1 0 1 MARC_BASE_LO_1 12 31 mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 0 0x3b33 1 0 1 MARC_BASE_LO_2 12 31 mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 0 0x3b34 1 0 1 MARC_BASE_LO_3 12 31 mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 0 0x3b35 1 0 1 MARC_BASE_HI_0 0 19 mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 0 0x3b36 1 0 1 MARC_BASE_HI_1 0 19 mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 0 0x3b37 1 0 1 MARC_BASE_HI_2 0 19 mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 0 0x3b38 1 0 1 MARC_BASE_HI_3 0 19 mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 0 0x3b39 3 0 1 MARC_ENABLE_0 0 0 MARC_READONLY_0 1 1 MARC_RELOC_LO_0 12 31 mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 0 0x3b3a 3 0 1 MARC_ENABLE_1 0 0 MARC_READONLY_1 1 1 MARC_RELOC_LO_1 12 31 mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 0 0x3b3b 3 0 1 MARC_ENABLE_2 0 0 MARC_READONLY_2 1 1 MARC_RELOC_LO_2 12 31 mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 0 0x3b3c 3 0 1 MARC_ENABLE_3 0 0 MARC_READONLY_3 1 1 MARC_RELOC_LO_3 12 31 mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 0 0x3b3d 1 0 1 MARC_RELOC_HI_0 0 19 mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 0 0x3b3e 1 0 1 MARC_RELOC_HI_1 0 19 mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 0 0x3b3f 1 0 1 MARC_RELOC_HI_2 0 19 mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 0 0x3b40 1 0 1 MARC_RELOC_HI_3 0 19 mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 0 0x3b41 1 0 1 MARC_LEN_LO_0 12 31 mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 0 0x3b42 1 0 1 MARC_LEN_LO_1 12 31 mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 0 0x3b43 1 0 1 MARC_LEN_LO_2 12 31 mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 0 0x3b44 1 0 1 MARC_LEN_LO_3 12 31 mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 0 0x3b45 1 0 1 MARC_LEN_HI_0 0 19 mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 0 0x3b46 1 0 1 MARC_LEN_HI_1 0 19 mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 0 0x3b47 1 0 1 MARC_LEN_HI_2 0 19 mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 0 0x3b48 1 0 1 MARC_LEN_HI_3 0 19 mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 0 0x3b49 1 0 1 IOMMUEN 0 0 mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0 0x3b4a 1 0 1 PERFOPTEN 13 13 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL 0 0x3b4b 2 0 1 STU 16 20 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 0 0x3b4c 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 0 0x3b4d 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 0 0x3b4e 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 0 0x3b4f 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 0 0x3b50 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 0 0x3b51 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 0 0x3b52 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 0 0x3b53 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 0 0x3b54 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 0 0x3b55 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 0 0x3b56 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 0 0x3b57 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 0 0x3b58 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 0 0x3b59 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 0 0x3b5a 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 0 0x3b5b 1 0 1 ATC_ENABLE 31 31 mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 0 0x3b5c 6 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE_EXTRA 12 14 MGLS_OVERRIDE 15 15 SOFT_STALL_OVERRIDE 16 23 SOFT_OVERRIDE 24 31 mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 0 0x3b5d 2 0 1 VFID 0 3 VF 31 31 mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 0 0x3b5e 17 0 1 ENABLE_VF0 0 0 ENABLE_VF1 1 1 ENABLE_VF2 2 2 ENABLE_VF3 3 3 ENABLE_VF4 4 4 ENABLE_VF5 5 5 ENABLE_VF6 6 6 ENABLE_VF7 7 7 ENABLE_VF8 8 8 ENABLE_VF9 9 9 ENABLE_VF10 10 10 ENABLE_VF11 11 11 ENABLE_VF12 12 12 ENABLE_VF13 13 13 ENABLE_VF14 14 14 ENABLE_VF15 15 15 ENABLE_PF 31 31 mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 0 0x3b70 1 0 1 COUNTER_LO 0 31 mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 0 0x3b71 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31 mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 0 0x3b74 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 0 0x3b75 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 0 0x3b76 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 0 0x3b80 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 0 0x3b81 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 0 0x3b82 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 0 0x3b83 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 0 0x3b84 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 0 0x3b85 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 0 0x3b86 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 0 0x3b87 5 0 1 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0 0x3b88 6 0 1 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO 0 0x3b90 1 0 1 COUNTER_LO 0 31 mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI 0 0x3b91 2 0 1 COUNTER_HI 0 15 COMPARE_VALUE 16 31