1127 cfgVENDOR_ID 3 0x0 2 0 4294967295 VENDOR_ID 0 0 VENDOR_ID_ 0 15 cfgDEVICE_ID 3 0x2 2 0 4294967295 DEVICE_ID 0 0 DEVICE_ID_ 0 15 cfgCOMMAND 3 0x4 22 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 0 0 BUS_MASTER_EN 0 0 SPECIAL_CYCLE_EN 0 0 MEM_WRITE_INVALIDATE_EN 0 0 PAL_SNOOP_EN 0 0 PARITY_ERROR_RESPONSE 0 0 AD_STEPPING 0 0 SERR_EN 0 0 FAST_B2B_EN 0 0 INT_DIS 0 0 IO_ACCESS_EN_ 0 0 MEM_ACCESS_EN_ 1 1 BUS_MASTER_EN_ 2 2 SPECIAL_CYCLE_EN_ 3 3 MEM_WRITE_INVALIDATE_EN_ 4 4 PAL_SNOOP_EN_ 5 5 PARITY_ERROR_RESPONSE_ 6 6 AD_STEPPING_ 7 7 SERR_EN_ 8 8 FAST_B2B_EN_ 9 9 INT_DIS_ 10 10 cfgSTATUS 3 0x6 22 0 4294967295 INT_STATUS 0 0 CAP_LIST 0 0 PCI_66_EN 0 0 FAST_BACK_CAPABLE 0 0 MASTER_DATA_PARITY_ERROR 0 0 DEVSEL_TIMING 0 0 SIGNAL_TARGET_ABORT 0 0 RECEIVED_TARGET_ABORT 0 0 RECEIVED_MASTER_ABORT 0 0 SIGNALED_SYSTEM_ERROR 0 0 PARITY_ERROR_DETECTED 0 0 INT_STATUS_ 3 3 CAP_LIST_ 4 4 PCI_66_EN_ 5 5 FAST_BACK_CAPABLE_ 7 7 MASTER_DATA_PARITY_ERROR_ 8 8 DEVSEL_TIMING_ 9 10 SIGNAL_TARGET_ABORT_ 11 11 RECEIVED_TARGET_ABORT_ 12 12 RECEIVED_MASTER_ABORT_ 13 13 SIGNALED_SYSTEM_ERROR_ 14 14 PARITY_ERROR_DETECTED_ 15 15 cfgREVISION_ID 3 0x8 4 0 4294967295 MINOR_REV_ID 0 0 MAJOR_REV_ID 0 0 MINOR_REV_ID_ 0 3 MAJOR_REV_ID_ 4 7 cfgPROG_INTERFACE 3 0x9 2 0 4294967295 PROG_INTERFACE 0 0 PROG_INTERFACE_ 0 7 cfgSUB_CLASS 3 0xa 2 0 4294967295 SUB_CLASS 0 0 SUB_CLASS_ 0 7 cfgBASE_CLASS 3 0xb 2 0 4294967295 BASE_CLASS 0 0 BASE_CLASS_ 0 7 cfgCACHE_LINE 3 0xc 2 0 4294967295 CACHE_LINE_SIZE 0 0 CACHE_LINE_SIZE_ 0 7 cfgLATENCY 3 0xd 2 0 4294967295 LATENCY_TIMER 0 0 LATENCY_TIMER_ 0 7 cfgHEADER 3 0xe 4 0 4294967295 HEADER_TYPE 0 0 DEVICE_TYPE 0 0 HEADER_TYPE_ 0 6 DEVICE_TYPE_ 7 7 cfgBIST 3 0xf 6 0 4294967295 BIST_COMP 0 0 BIST_STRT 0 0 BIST_CAP 0 0 BIST_COMP_ 0 3 BIST_STRT_ 6 6 BIST_CAP_ 7 7 cfgBASE_ADDR_1 3 0x10 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgBASE_ADDR_2 3 0x14 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgBASE_ADDR_3 3 0x18 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgBASE_ADDR_4 3 0x1c 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgBASE_ADDR_5 3 0x20 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgBASE_ADDR_6 3 0x24 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgADAPTER_ID 3 0x2c 4 0 4294967295 SUBSYSTEM_VENDOR_ID 0 0 SUBSYSTEM_ID 0 0 SUBSYSTEM_VENDOR_ID_ 0 15 SUBSYSTEM_ID_ 16 31 cfgROM_BASE_ADDR 3 0x30 2 0 4294967295 BASE_ADDR 0 0 BASE_ADDR_ 0 31 cfgCAP_PTR 3 0x34 2 0 4294967295 CAP_PTR 0 0 CAP_PTR_ 0 7 cfgINTERRUPT_LINE 3 0x3c 2 0 4294967295 INTERRUPT_LINE 0 0 INTERRUPT_LINE_ 0 7 cfgINTERRUPT_PIN 3 0x3d 2 0 4294967295 INTERRUPT_PIN 0 0 INTERRUPT_PIN_ 0 7 cfgMIN_GRANT 3 0x3e 2 0 4294967295 MIN_GNT 0 0 MIN_GNT_ 0 7 cfgMAX_LATENCY 3 0x3f 2 0 4294967295 MAX_LAT 0 0 MAX_LAT_ 0 7 cfgVENDOR_CAP_LIST 3 0x48 6 0 4294967295 CAP_ID 0 0 NEXT_PTR 0 0 LENGTH 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 LENGTH_ 16 23 cfgADAPTER_ID_W 3 0x4c 4 0 4294967295 SUBSYSTEM_VENDOR_ID 0 0 SUBSYSTEM_ID 0 0 SUBSYSTEM_VENDOR_ID_ 0 15 SUBSYSTEM_ID_ 16 31 cfgPMI_CAP_LIST 3 0x50 4 0 4294967295 CAP_ID 0 0 NEXT_PTR 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 cfgPMI_CAP 3 0x52 14 0 4294967295 VERSION 0 0 PME_CLOCK 0 0 DEV_SPECIFIC_INIT 0 0 AUX_CURRENT 0 0 D1_SUPPORT 0 0 D2_SUPPORT 0 0 PME_SUPPORT 0 0 VERSION_ 0 2 PME_CLOCK_ 3 3 DEV_SPECIFIC_INIT_ 5 5 AUX_CURRENT_ 6 8 D1_SUPPORT_ 9 9 D2_SUPPORT_ 10 10 PME_SUPPORT_ 11 15 cfgPMI_STATUS_CNTL 3 0x54 18 0 4294967295 POWER_STATE 0 0 NO_SOFT_RESET 0 0 PME_EN 0 0 DATA_SELECT 0 0 DATA_SCALE 0 0 PME_STATUS 0 0 B2_B3_SUPPORT 0 0 BUS_PWR_EN 0 0 PMI_DATA 0 0 POWER_STATE_ 0 1 NO_SOFT_RESET_ 3 3 PME_EN_ 8 8 DATA_SELECT_ 9 12 DATA_SCALE_ 13 14 PME_STATUS_ 15 15 B2_B3_SUPPORT_ 22 22 BUS_PWR_EN_ 23 23 PMI_DATA_ 24 31 cfgPCIE_CAP_LIST 3 0x64 4 0 4294967295 CAP_ID 0 0 NEXT_PTR 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 cfgPCIE_CAP 3 0x66 8 0 4294967295 VERSION 0 0 DEVICE_TYPE 0 0 SLOT_IMPLEMENTED 0 0 INT_MESSAGE_NUM 0 0 VERSION_ 0 3 DEVICE_TYPE_ 4 7 SLOT_IMPLEMENTED_ 8 8 INT_MESSAGE_NUM_ 9 13 cfgDEVICE_CAP 3 0x68 18 0 4294967295 MAX_PAYLOAD_SUPPORT 0 0 PHANTOM_FUNC 0 0 EXTENDED_TAG 0 0 L0S_ACCEPTABLE_LATENCY 0 0 L1_ACCEPTABLE_LATENCY 0 0 ROLE_BASED_ERR_REPORTING 0 0 CAPTURED_SLOT_POWER_LIMIT 0 0 CAPTURED_SLOT_POWER_SCALE 0 0 FLR_CAPABLE 0 0 MAX_PAYLOAD_SUPPORT_ 0 2 PHANTOM_FUNC_ 3 4 EXTENDED_TAG_ 5 5 L0S_ACCEPTABLE_LATENCY_ 6 8 L1_ACCEPTABLE_LATENCY_ 9 11 ROLE_BASED_ERR_REPORTING_ 15 15 CAPTURED_SLOT_POWER_LIMIT_ 18 25 CAPTURED_SLOT_POWER_SCALE_ 26 27 FLR_CAPABLE_ 28 28 cfgDEVICE_CNTL 3 0x6c 24 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 0 0 FATAL_ERR_EN 0 0 USR_REPORT_EN 0 0 RELAXED_ORD_EN 0 0 MAX_PAYLOAD_SIZE 0 0 EXTENDED_TAG_EN 0 0 PHANTOM_FUNC_EN 0 0 AUX_POWER_PM_EN 0 0 NO_SNOOP_EN 0 0 MAX_READ_REQUEST_SIZE 0 0 INITIATE_FLR 0 0 CORR_ERR_EN_ 0 0 NON_FATAL_ERR_EN_ 1 1 FATAL_ERR_EN_ 2 2 USR_REPORT_EN_ 3 3 RELAXED_ORD_EN_ 4 4 MAX_PAYLOAD_SIZE_ 5 7 EXTENDED_TAG_EN_ 8 8 PHANTOM_FUNC_EN_ 9 9 AUX_POWER_PM_EN_ 10 10 NO_SNOOP_EN_ 11 11 MAX_READ_REQUEST_SIZE_ 12 14 INITIATE_FLR_ 15 15 cfgDEVICE_STATUS 3 0x6e 12 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 0 0 FATAL_ERR 0 0 USR_DETECTED 0 0 AUX_PWR 0 0 TRANSACTIONS_PEND 0 0 CORR_ERR_ 0 0 NON_FATAL_ERR_ 1 1 FATAL_ERR_ 2 2 USR_DETECTED_ 3 3 AUX_PWR_ 4 4 TRANSACTIONS_PEND_ 5 5 cfgLINK_CAP 3 0x70 22 0 4294967295 LINK_SPEED 0 0 LINK_WIDTH 0 0 PM_SUPPORT 0 0 L0S_EXIT_LATENCY 0 0 L1_EXIT_LATENCY 0 0 CLOCK_POWER_MANAGEMENT 0 0 SURPRISE_DOWN_ERR_REPORTING 0 0 DL_ACTIVE_REPORTING_CAPABLE 0 0 LINK_BW_NOTIFICATION_CAP 0 0 ASPM_OPTIONALITY_COMPLIANCE 0 0 PORT_NUMBER 0 0 LINK_SPEED_ 0 3 LINK_WIDTH_ 4 9 PM_SUPPORT_ 10 11 L0S_EXIT_LATENCY_ 12 14 L1_EXIT_LATENCY_ 15 17 CLOCK_POWER_MANAGEMENT_ 18 18 SURPRISE_DOWN_ERR_REPORTING_ 19 19 DL_ACTIVE_REPORTING_CAPABLE_ 20 20 LINK_BW_NOTIFICATION_CAP_ 21 21 ASPM_OPTIONALITY_COMPLIANCE_ 22 22 PORT_NUMBER_ 24 31 cfgLINK_CNTL 3 0x74 20 0 4294967295 PM_CONTROL 0 0 READ_CPL_BOUNDARY 0 0 LINK_DIS 0 0 RETRAIN_LINK 0 0 COMMON_CLOCK_CFG 0 0 EXTENDED_SYNC 0 0 CLOCK_POWER_MANAGEMENT_EN 0 0 HW_AUTONOMOUS_WIDTH_DISABLE 0 0 LINK_BW_MANAGEMENT_INT_EN 0 0 LINK_AUTONOMOUS_BW_INT_EN 0 0 PM_CONTROL_ 0 1 READ_CPL_BOUNDARY_ 3 3 LINK_DIS_ 4 4 RETRAIN_LINK_ 5 5 COMMON_CLOCK_CFG_ 6 6 EXTENDED_SYNC_ 7 7 CLOCK_POWER_MANAGEMENT_EN_ 8 8 HW_AUTONOMOUS_WIDTH_DISABLE_ 9 9 LINK_BW_MANAGEMENT_INT_EN_ 10 10 LINK_AUTONOMOUS_BW_INT_EN_ 11 11 cfgLINK_STATUS 3 0x76 14 0 4294967295 CURRENT_LINK_SPEED 0 0 NEGOTIATED_LINK_WIDTH 0 0 LINK_TRAINING 0 0 SLOT_CLOCK_CFG 0 0 DL_ACTIVE 0 0 LINK_BW_MANAGEMENT_STATUS 0 0 LINK_AUTONOMOUS_BW_STATUS 0 0 CURRENT_LINK_SPEED_ 0 3 NEGOTIATED_LINK_WIDTH_ 4 9 LINK_TRAINING_ 11 11 SLOT_CLOCK_CFG_ 12 12 DL_ACTIVE_ 13 13 LINK_BW_MANAGEMENT_STATUS_ 14 14 LINK_AUTONOMOUS_BW_STATUS_ 15 15 cfgDEVICE_CAP2 3 0x88 28 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 0 CPL_TIMEOUT_DIS_SUPPORTED 0 0 ARI_FORWARDING_SUPPORTED 0 0 ATOMICOP_ROUTING_SUPPORTED 0 0 ATOMICOP_32CMPLT_SUPPORTED 0 0 ATOMICOP_64CMPLT_SUPPORTED 0 0 CAS128_CMPLT_SUPPORTED 0 0 NO_RO_ENABLED_P2P_PASSING 0 0 LTR_SUPPORTED 0 0 TPH_CPLR_SUPPORTED 0 0 OBFF_SUPPORTED 0 0 EXTENDED_FMT_FIELD_SUPPORTED 0 0 END_END_TLP_PREFIX_SUPPORTED 0 0 MAX_END_END_TLP_PREFIXES 0 0 CPL_TIMEOUT_RANGE_SUPPORTED_ 0 3 CPL_TIMEOUT_DIS_SUPPORTED_ 4 4 ARI_FORWARDING_SUPPORTED_ 5 5 ATOMICOP_ROUTING_SUPPORTED_ 6 6 ATOMICOP_32CMPLT_SUPPORTED_ 7 7 ATOMICOP_64CMPLT_SUPPORTED_ 8 8 CAS128_CMPLT_SUPPORTED_ 9 9 NO_RO_ENABLED_P2P_PASSING_ 10 10 LTR_SUPPORTED_ 11 11 TPH_CPLR_SUPPORTED_ 12 13 OBFF_SUPPORTED_ 18 19 EXTENDED_FMT_FIELD_SUPPORTED_ 20 20 END_END_TLP_PREFIX_SUPPORTED_ 21 21 MAX_END_END_TLP_PREFIXES_ 22 23 cfgDEVICE_CNTL2 3 0x8c 20 0 4294967295 CPL_TIMEOUT_VALUE 0 0 CPL_TIMEOUT_DIS 0 0 ARI_FORWARDING_EN 0 0 ATOMICOP_REQUEST_EN 0 0 ATOMICOP_EGRESS_BLOCKING 0 0 IDO_REQUEST_ENABLE 0 0 IDO_COMPLETION_ENABLE 0 0 LTR_EN 0 0 OBFF_EN 0 0 END_END_TLP_PREFIX_BLOCKING 0 0 CPL_TIMEOUT_VALUE_ 0 3 CPL_TIMEOUT_DIS_ 4 4 ARI_FORWARDING_EN_ 5 5 ATOMICOP_REQUEST_EN_ 6 6 ATOMICOP_EGRESS_BLOCKING_ 7 7 IDO_REQUEST_ENABLE_ 8 8 IDO_COMPLETION_ENABLE_ 9 9 LTR_EN_ 10 10 OBFF_EN_ 13 14 END_END_TLP_PREFIX_BLOCKING_ 15 15 cfgDEVICE_STATUS2 3 0x8e 2 0 4294967295 RESERVED 0 0 RESERVED_ 0 15 cfgLINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 0 0 CROSSLINK_SUPPORTED 0 0 RESERVED 0 0 SUPPORTED_LINK_SPEED_ 1 7 CROSSLINK_SUPPORTED_ 8 8 RESERVED_ 9 31 cfgLINK_CNTL2 3 0x94 16 0 4294967295 TARGET_LINK_SPEED 0 0 ENTER_COMPLIANCE 0 0 HW_AUTONOMOUS_SPEED_DISABLE 0 0 SELECTABLE_DEEMPHASIS 0 0 XMIT_MARGIN 0 0 ENTER_MOD_COMPLIANCE 0 0 COMPLIANCE_SOS 0 0 COMPLIANCE_DEEMPHASIS 0 0 TARGET_LINK_SPEED_ 0 3 ENTER_COMPLIANCE_ 4 4 HW_AUTONOMOUS_SPEED_DISABLE_ 5 5 SELECTABLE_DEEMPHASIS_ 6 6 XMIT_MARGIN_ 7 9 ENTER_MOD_COMPLIANCE_ 10 10 COMPLIANCE_SOS_ 11 11 COMPLIANCE_DEEMPHASIS_ 12 15 cfgLINK_STATUS2 3 0x96 12 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE 0 0 EQUALIZATION_PHASE1_SUCCESS 0 0 EQUALIZATION_PHASE2_SUCCESS 0 0 EQUALIZATION_PHASE3_SUCCESS 0 0 LINK_EQUALIZATION_REQUEST 0 0 CUR_DEEMPHASIS_LEVEL_ 0 0 EQUALIZATION_COMPLETE_ 1 1 EQUALIZATION_PHASE1_SUCCESS_ 2 2 EQUALIZATION_PHASE2_SUCCESS_ 3 3 EQUALIZATION_PHASE3_SUCCESS_ 4 4 LINK_EQUALIZATION_REQUEST_ 5 5 cfgSLOT_CAP2 3 0x98 2 0 4294967295 RESERVED 0 0 RESERVED_ 0 31 cfgSLOT_CNTL2 3 0x9c 2 0 4294967295 RESERVED 0 0 RESERVED_ 0 15 cfgSLOT_STATUS2 3 0x9e 2 0 4294967295 RESERVED 0 0 RESERVED_ 0 15 cfgMSI_CAP_LIST 3 0xa0 4 0 4294967295 CAP_ID 0 0 NEXT_PTR 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 cfgMSI_MSG_CNTL 3 0xa2 10 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 0 0 MSI_MULTI_EN 0 0 MSI_64BIT 0 0 MSI_PERVECTOR_MASKING_CAP 0 0 MSI_EN_ 0 0 MSI_MULTI_CAP_ 1 3 MSI_MULTI_EN_ 4 6 MSI_64BIT_ 7 7 MSI_PERVECTOR_MASKING_CAP_ 8 8 cfgMSI_MSG_ADDR_LO 3 0xa4 2 0 4294967295 MSI_MSG_ADDR_LO 0 0 MSI_MSG_ADDR_LO_ 2 31 cfgMSI_MSG_ADDR_HI 3 0xa8 2 0 4294967295 MSI_MSG_ADDR_HI 0 0 MSI_MSG_ADDR_HI_ 0 31 cfgMSI_MSG_DATA 3 0xa8 2 0 4294967295 MSI_DATA 0 0 MSI_DATA_ 0 15 cfgMSI_MSG_DATA_64 3 0xac 2 0 4294967295 MSI_DATA_64 0 0 MSI_DATA_64_ 0 15 cfgMSI_MASK 3 0xac 2 0 4294967295 MSI_MASK 0 0 MSI_MASK_ 0 31 cfgMSI_PENDING 3 0xb0 2 0 4294967295 MSI_PENDING 0 0 MSI_PENDING_ 0 31 cfgMSI_MASK_64 3 0xb0 2 0 4294967295 MSI_MASK_64 0 0 MSI_MASK_64_ 0 31 cfgMSI_PENDING_64 3 0xb4 2 0 4294967295 MSI_PENDING_64 0 0 MSI_PENDING_64_ 0 31 cfgMSIX_CAP_LIST 3 0xc0 4 0 4294967295 CAP_ID 0 0 NEXT_PTR 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 cfgMSIX_MSG_CNTL 3 0xc2 6 0 4294967295 MSIX_TABLE_SIZE 0 0 MSIX_FUNC_MASK 0 0 MSIX_EN 0 0 MSIX_TABLE_SIZE_ 0 10 MSIX_FUNC_MASK_ 14 14 MSIX_EN_ 15 15 cfgMSIX_TABLE 3 0xc4 4 0 4294967295 MSIX_TABLE_BIR 0 0 MSIX_TABLE_OFFSET 0 0 MSIX_TABLE_BIR_ 0 2 MSIX_TABLE_OFFSET_ 3 31 cfgMSIX_PBA 3 0xc8 4 0 4294967295 MSIX_PBA_BIR 0 0 MSIX_PBA_OFFSET 0 0 MSIX_PBA_BIR_ 0 2 MSIX_PBA_OFFSET_ 3 31 cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_VENDOR_SPECIFIC_HDR 3 0x104 6 0 4294967295 VSEC_ID 0 0 VSEC_REV 0 0 VSEC_LENGTH 0 0 VSEC_ID_ 0 15 VSEC_REV_ 16 19 VSEC_LENGTH_ 20 31 cfgPCIE_VENDOR_SPECIFIC1 3 0x108 2 0 4294967295 SCRATCH 0 0 SCRATCH_ 0 31 cfgPCIE_VENDOR_SPECIFIC2 3 0x10c 2 0 4294967295 SCRATCH 0 0 SCRATCH_ 0 31 cfgPCIE_VC_ENH_CAP_LIST 3 0x110 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_PORT_VC_CAP_REG1 3 0x114 8 0 4294967295 EXT_VC_COUNT 0 0 LOW_PRIORITY_EXT_VC_COUNT 0 0 REF_CLK 0 0 PORT_ARB_TABLE_ENTRY_SIZE 0 0 EXT_VC_COUNT_ 0 2 LOW_PRIORITY_EXT_VC_COUNT_ 4 6 REF_CLK_ 8 9 PORT_ARB_TABLE_ENTRY_SIZE_ 10 11 cfgPCIE_PORT_VC_CAP_REG2 3 0x118 4 0 4294967295 VC_ARB_CAP 0 0 VC_ARB_TABLE_OFFSET 0 0 VC_ARB_CAP_ 0 7 VC_ARB_TABLE_OFFSET_ 24 31 cfgPCIE_PORT_VC_CNTL 3 0x11c 4 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 0 0 LOAD_VC_ARB_TABLE_ 0 0 VC_ARB_SELECT_ 1 3 cfgPCIE_PORT_VC_STATUS 3 0x11e 2 0 4294967295 VC_ARB_TABLE_STATUS 0 0 VC_ARB_TABLE_STATUS_ 0 0 cfgPCIE_VC0_RESOURCE_CAP 3 0x120 8 0 4294967295 PORT_ARB_CAP 0 0 REJECT_SNOOP_TRANS 0 0 MAX_TIME_SLOTS 0 0 PORT_ARB_TABLE_OFFSET 0 0 PORT_ARB_CAP_ 0 7 REJECT_SNOOP_TRANS_ 15 15 MAX_TIME_SLOTS_ 16 21 PORT_ARB_TABLE_OFFSET_ 24 31 cfgPCIE_VC0_RESOURCE_CNTL 3 0x124 12 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 0 0 LOAD_PORT_ARB_TABLE 0 0 PORT_ARB_SELECT 0 0 VC_ID 0 0 VC_ENABLE 0 0 TC_VC_MAP_TC0_ 0 0 TC_VC_MAP_TC1_7_ 1 7 LOAD_PORT_ARB_TABLE_ 16 16 PORT_ARB_SELECT_ 17 19 VC_ID_ 24 26 VC_ENABLE_ 31 31 cfgPCIE_VC0_RESOURCE_STATUS 3 0x12a 4 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 0 0 PORT_ARB_TABLE_STATUS_ 0 0 VC_NEGOTIATION_PENDING_ 1 1 cfgPCIE_VC1_RESOURCE_CAP 3 0x12c 8 0 4294967295 PORT_ARB_CAP 0 0 REJECT_SNOOP_TRANS 0 0 MAX_TIME_SLOTS 0 0 PORT_ARB_TABLE_OFFSET 0 0 PORT_ARB_CAP_ 0 7 REJECT_SNOOP_TRANS_ 15 15 MAX_TIME_SLOTS_ 16 21 PORT_ARB_TABLE_OFFSET_ 24 31 cfgPCIE_VC1_RESOURCE_CNTL 3 0x130 12 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 0 0 LOAD_PORT_ARB_TABLE 0 0 PORT_ARB_SELECT 0 0 VC_ID 0 0 VC_ENABLE 0 0 TC_VC_MAP_TC0_ 0 0 TC_VC_MAP_TC1_7_ 1 7 LOAD_PORT_ARB_TABLE_ 16 16 PORT_ARB_SELECT_ 17 19 VC_ID_ 24 26 VC_ENABLE_ 31 31 cfgPCIE_VC1_RESOURCE_STATUS 3 0x136 4 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 0 0 PORT_ARB_TABLE_STATUS_ 0 0 VC_NEGOTIATION_PENDING_ 1 1 cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_DEV_SERIAL_NUM_DW1 3 0x144 2 0 4294967295 SERIAL_NUMBER_LO 0 0 SERIAL_NUMBER_LO_ 0 31 cfgPCIE_DEV_SERIAL_NUM_DW2 3 0x148 2 0 4294967295 SERIAL_NUMBER_HI 0 0 SERIAL_NUMBER_HI_ 0 31 cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_UNCORR_ERR_STATUS 3 0x154 32 0 4294967295 DLP_ERR_STATUS 0 0 SURPDN_ERR_STATUS 0 0 PSN_ERR_STATUS 0 0 FC_ERR_STATUS 0 0 CPL_TIMEOUT_STATUS 0 0 CPL_ABORT_ERR_STATUS 0 0 UNEXP_CPL_STATUS 0 0 RCV_OVFL_STATUS 0 0 MAL_TLP_STATUS 0 0 ECRC_ERR_STATUS 0 0 UNSUPP_REQ_ERR_STATUS 0 0 ACS_VIOLATION_STATUS 0 0 UNCORR_INT_ERR_STATUS 0 0 MC_BLOCKED_TLP_STATUS 0 0 ATOMICOP_EGRESS_BLOCKED_STATUS 0 0 TLP_PREFIX_BLOCKED_ERR_STATUS 0 0 DLP_ERR_STATUS_ 4 4 SURPDN_ERR_STATUS_ 5 5 PSN_ERR_STATUS_ 12 12 FC_ERR_STATUS_ 13 13 CPL_TIMEOUT_STATUS_ 14 14 CPL_ABORT_ERR_STATUS_ 15 15 UNEXP_CPL_STATUS_ 16 16 RCV_OVFL_STATUS_ 17 17 MAL_TLP_STATUS_ 18 18 ECRC_ERR_STATUS_ 19 19 UNSUPP_REQ_ERR_STATUS_ 20 20 ACS_VIOLATION_STATUS_ 21 21 UNCORR_INT_ERR_STATUS_ 22 22 MC_BLOCKED_TLP_STATUS_ 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS_ 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS_ 25 25 cfgPCIE_UNCORR_ERR_MASK 3 0x158 32 0 4294967295 DLP_ERR_MASK 0 0 SURPDN_ERR_MASK 0 0 PSN_ERR_MASK 0 0 FC_ERR_MASK 0 0 CPL_TIMEOUT_MASK 0 0 CPL_ABORT_ERR_MASK 0 0 UNEXP_CPL_MASK 0 0 RCV_OVFL_MASK 0 0 MAL_TLP_MASK 0 0 ECRC_ERR_MASK 0 0 UNSUPP_REQ_ERR_MASK 0 0 ACS_VIOLATION_MASK 0 0 UNCORR_INT_ERR_MASK 0 0 MC_BLOCKED_TLP_MASK 0 0 ATOMICOP_EGRESS_BLOCKED_MASK 0 0 TLP_PREFIX_BLOCKED_ERR_MASK 0 0 DLP_ERR_MASK_ 4 4 SURPDN_ERR_MASK_ 5 5 PSN_ERR_MASK_ 12 12 FC_ERR_MASK_ 13 13 CPL_TIMEOUT_MASK_ 14 14 CPL_ABORT_ERR_MASK_ 15 15 UNEXP_CPL_MASK_ 16 16 RCV_OVFL_MASK_ 17 17 MAL_TLP_MASK_ 18 18 ECRC_ERR_MASK_ 19 19 UNSUPP_REQ_ERR_MASK_ 20 20 ACS_VIOLATION_MASK_ 21 21 UNCORR_INT_ERR_MASK_ 22 22 MC_BLOCKED_TLP_MASK_ 23 23 ATOMICOP_EGRESS_BLOCKED_MASK_ 24 24 TLP_PREFIX_BLOCKED_ERR_MASK_ 25 25 cfgPCIE_UNCORR_ERR_SEVERITY 3 0x15c 32 0 4294967295 DLP_ERR_SEVERITY 0 0 SURPDN_ERR_SEVERITY 0 0 PSN_ERR_SEVERITY 0 0 FC_ERR_SEVERITY 0 0 CPL_TIMEOUT_SEVERITY 0 0 CPL_ABORT_ERR_SEVERITY 0 0 UNEXP_CPL_SEVERITY 0 0 RCV_OVFL_SEVERITY 0 0 MAL_TLP_SEVERITY 0 0 ECRC_ERR_SEVERITY 0 0 UNSUPP_REQ_ERR_SEVERITY 0 0 ACS_VIOLATION_SEVERITY 0 0 UNCORR_INT_ERR_SEVERITY 0 0 MC_BLOCKED_TLP_SEVERITY 0 0 ATOMICOP_EGRESS_BLOCKED_SEVERITY 0 0 TLP_PREFIX_BLOCKED_ERR_SEVERITY 0 0 DLP_ERR_SEVERITY_ 4 4 SURPDN_ERR_SEVERITY_ 5 5 PSN_ERR_SEVERITY_ 12 12 FC_ERR_SEVERITY_ 13 13 CPL_TIMEOUT_SEVERITY_ 14 14 CPL_ABORT_ERR_SEVERITY_ 15 15 UNEXP_CPL_SEVERITY_ 16 16 RCV_OVFL_SEVERITY_ 17 17 MAL_TLP_SEVERITY_ 18 18 ECRC_ERR_SEVERITY_ 19 19 UNSUPP_REQ_ERR_SEVERITY_ 20 20 ACS_VIOLATION_SEVERITY_ 21 21 UNCORR_INT_ERR_SEVERITY_ 22 22 MC_BLOCKED_TLP_SEVERITY_ 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY_ 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY_ 25 25 cfgPCIE_CORR_ERR_STATUS 3 0x160 16 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 0 0 BAD_DLLP_STATUS 0 0 REPLAY_NUM_ROLLOVER_STATUS 0 0 REPLAY_TIMER_TIMEOUT_STATUS 0 0 ADVISORY_NONFATAL_ERR_STATUS 0 0 CORR_INT_ERR_STATUS 0 0 HDR_LOG_OVFL_STATUS 0 0 RCV_ERR_STATUS_ 0 0 BAD_TLP_STATUS_ 6 6 BAD_DLLP_STATUS_ 7 7 REPLAY_NUM_ROLLOVER_STATUS_ 8 8 REPLAY_TIMER_TIMEOUT_STATUS_ 12 12 ADVISORY_NONFATAL_ERR_STATUS_ 13 13 CORR_INT_ERR_STATUS_ 14 14 HDR_LOG_OVFL_STATUS_ 15 15 cfgPCIE_CORR_ERR_MASK 3 0x164 16 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 0 0 BAD_DLLP_MASK 0 0 REPLAY_NUM_ROLLOVER_MASK 0 0 REPLAY_TIMER_TIMEOUT_MASK 0 0 ADVISORY_NONFATAL_ERR_MASK 0 0 CORR_INT_ERR_MASK 0 0 HDR_LOG_OVFL_MASK 0 0 RCV_ERR_MASK_ 0 0 BAD_TLP_MASK_ 6 6 BAD_DLLP_MASK_ 7 7 REPLAY_NUM_ROLLOVER_MASK_ 8 8 REPLAY_TIMER_TIMEOUT_MASK_ 12 12 ADVISORY_NONFATAL_ERR_MASK_ 13 13 CORR_INT_ERR_MASK_ 14 14 HDR_LOG_OVFL_MASK_ 15 15 cfgPCIE_ADV_ERR_CAP_CNTL 3 0x168 16 0 4294967295 FIRST_ERR_PTR 0 0 ECRC_GEN_CAP 0 0 ECRC_GEN_EN 0 0 ECRC_CHECK_CAP 0 0 ECRC_CHECK_EN 0 0 MULTI_HDR_RECD_CAP 0 0 MULTI_HDR_RECD_EN 0 0 TLP_PREFIX_LOG_PRESENT 0 0 FIRST_ERR_PTR_ 0 4 ECRC_GEN_CAP_ 5 5 ECRC_GEN_EN_ 6 6 ECRC_CHECK_CAP_ 7 7 ECRC_CHECK_EN_ 8 8 MULTI_HDR_RECD_CAP_ 9 9 MULTI_HDR_RECD_EN_ 10 10 TLP_PREFIX_LOG_PRESENT_ 11 11 cfgPCIE_HDR_LOG0 3 0x16c 2 0 4294967295 TLP_HDR 0 0 TLP_HDR_ 0 31 cfgPCIE_HDR_LOG1 3 0x170 2 0 4294967295 TLP_HDR 0 0 TLP_HDR_ 0 31 cfgPCIE_HDR_LOG2 3 0x174 2 0 4294967295 TLP_HDR 0 0 TLP_HDR_ 0 31 cfgPCIE_HDR_LOG3 3 0x178 2 0 4294967295 TLP_HDR 0 0 TLP_HDR_ 0 31 cfgPCIE_ROOT_ERR_CMD 3 0x17c 6 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 0 0 FATAL_ERR_REP_EN 0 0 CORR_ERR_REP_EN_ 0 0 NONFATAL_ERR_REP_EN_ 1 1 FATAL_ERR_REP_EN_ 2 2 cfgPCIE_ROOT_ERR_STATUS 3 0x180 16 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 0 0 ERR_FATAL_NONFATAL_RCVD 0 0 MULT_ERR_FATAL_NONFATAL_RCVD 0 0 FIRST_UNCORRECTABLE_FATAL 0 0 NONFATAL_ERROR_MSG_RCVD 0 0 FATAL_ERROR_MSG_RCVD 0 0 ADV_ERR_INT_MSG_NUM 0 0 ERR_CORR_RCVD_ 0 0 MULT_ERR_CORR_RCVD_ 1 1 ERR_FATAL_NONFATAL_RCVD_ 2 2 MULT_ERR_FATAL_NONFATAL_RCVD_ 3 3 FIRST_UNCORRECTABLE_FATAL_ 4 4 NONFATAL_ERROR_MSG_RCVD_ 5 5 FATAL_ERROR_MSG_RCVD_ 6 6 ADV_ERR_INT_MSG_NUM_ 27 31 cfgPCIE_ERR_SRC_ID 3 0x184 4 0 4294967295 ERR_CORR_SRC_ID 0 0 ERR_FATAL_NONFATAL_SRC_ID 0 0 ERR_CORR_SRC_ID_ 0 15 ERR_FATAL_NONFATAL_SRC_ID_ 16 31 cfgPCIE_TLP_PREFIX_LOG0 3 0x188 2 0 4294967295 TLP_PREFIX 0 0 TLP_PREFIX_ 0 31 cfgPCIE_TLP_PREFIX_LOG1 3 0x18c 2 0 4294967295 TLP_PREFIX 0 0 TLP_PREFIX_ 0 31 cfgPCIE_TLP_PREFIX_LOG2 3 0x190 2 0 4294967295 TLP_PREFIX 0 0 TLP_PREFIX_ 0 31 cfgPCIE_TLP_PREFIX_LOG3 3 0x194 2 0 4294967295 TLP_PREFIX 0 0 TLP_PREFIX_ 0 31 cfgPCIE_BAR_ENH_CAP_LIST 3 0x200 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_BAR1_CAP 3 0x204 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR1_CNTL 3 0x208 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_BAR2_CAP 3 0x20c 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR2_CNTL 3 0x210 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_BAR3_CAP 3 0x214 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR3_CNTL 3 0x218 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_BAR4_CAP 3 0x21c 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR4_CNTL 3 0x220 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_BAR5_CAP 3 0x224 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR5_CNTL 3 0x228 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_BAR6_CAP 3 0x22c 2 0 4294967295 BAR_SIZE_SUPPORTED 0 0 BAR_SIZE_SUPPORTED_ 4 23 cfgPCIE_BAR6_CNTL 3 0x230 6 0 4294967295 BAR_INDEX 0 0 BAR_TOTAL_NUM 0 0 BAR_SIZE 0 0 BAR_INDEX_ 0 2 BAR_TOTAL_NUM_ 5 7 BAR_SIZE_ 8 12 cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_PWR_BUDGET_DATA_SELECT 3 0x244 2 0 4294967295 DATA_SELECT 0 0 DATA_SELECT_ 0 7 cfgPCIE_PWR_BUDGET_DATA 3 0x248 12 0 4294967295 BASE_POWER 0 0 DATA_SCALE 0 0 PM_SUB_STATE 0 0 PM_STATE 0 0 TYPE 0 0 POWER_RAIL 0 0 BASE_POWER_ 0 7 DATA_SCALE_ 8 9 PM_SUB_STATE_ 10 12 PM_STATE_ 13 14 TYPE_ 15 17 POWER_RAIL_ 18 20 cfgPCIE_PWR_BUDGET_CAP 3 0x24c 2 0 4294967295 SYSTEM_ALLOCATED 0 0 SYSTEM_ALLOCATED_ 0 0 cfgPCIE_DPA_ENH_CAP_LIST 3 0x250 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_DPA_CAP 3 0x254 10 0 4294967295 SUBSTATE_MAX 0 0 TRANS_LAT_UNIT 0 0 PWR_ALLOC_SCALE 0 0 TRANS_LAT_VAL_0 0 0 TRANS_LAT_VAL_1 0 0 SUBSTATE_MAX_ 0 4 TRANS_LAT_UNIT_ 8 9 PWR_ALLOC_SCALE_ 12 13 TRANS_LAT_VAL_0_ 16 23 TRANS_LAT_VAL_1_ 24 31 cfgPCIE_DPA_LATENCY_INDICATOR 3 0x258 2 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 0 TRANS_LAT_INDICATOR_BITS_ 0 7 cfgPCIE_DPA_STATUS 3 0x25c 4 0 4294967295 SUBSTATE_STATUS 0 0 SUBSTATE_CNTL_ENABLED 0 0 SUBSTATE_STATUS_ 0 4 SUBSTATE_CNTL_ENABLED_ 8 8 cfgPCIE_DPA_CNTL 3 0x25e 2 0 4294967295 SUBSTATE_CNTL 0 0 SUBSTATE_CNTL_ 0 4 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 2 0 4294967295 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 cfgPCIE_SECONDARY_ENH_CAP_LIST 3 0x270 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_LINK_CNTL3 3 0x274 6 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 0 0 RESERVED 0 0 PERFORM_EQUALIZATION_ 0 0 LINK_EQUALIZATION_REQ_INT_EN_ 1 1 RESERVED_ 2 31 cfgPCIE_LANE_ERROR_STATUS 3 0x278 4 0 4294967295 LANE_ERROR_STATUS_BITS 0 0 RESERVED 0 0 LANE_ERROR_STATUS_BITS_ 0 15 RESERVED_ 16 31 cfgPCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 10 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 0 DOWNSTREAM_PORT_RX_PRESET_HINT 0 0 UPSTREAM_PORT_TX_PRESET 0 0 UPSTREAM_PORT_RX_PRESET_HINT 0 0 RESERVED 0 0 DOWNSTREAM_PORT_TX_PRESET_ 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT_ 4 6 UPSTREAM_PORT_TX_PRESET_ 8 11 UPSTREAM_PORT_RX_PRESET_HINT_ 12 14 RESERVED_ 15 15 cfgPCIE_ACS_ENH_CAP_LIST 3 0x2a0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_ACS_CAP 3 0x2a4 16 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 0 0 P2P_REQUEST_REDIRECT 0 0 P2P_COMPLETION_REDIRECT 0 0 UPSTREAM_FORWARDING 0 0 P2P_EGRESS_CONTROL 0 0 DIRECT_TRANSLATED_P2P 0 0 EGRESS_CONTROL_VECTOR_SIZE 0 0 SOURCE_VALIDATION_ 0 0 TRANSLATION_BLOCKING_ 1 1 P2P_REQUEST_REDIRECT_ 2 2 P2P_COMPLETION_REDIRECT_ 3 3 UPSTREAM_FORWARDING_ 4 4 P2P_EGRESS_CONTROL_ 5 5 DIRECT_TRANSLATED_P2P_ 6 6 EGRESS_CONTROL_VECTOR_SIZE_ 8 15 cfgPCIE_ACS_CNTL 3 0x2a6 14 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 0 0 P2P_REQUEST_REDIRECT_EN 0 0 P2P_COMPLETION_REDIRECT_EN 0 0 UPSTREAM_FORWARDING_EN 0 0 P2P_EGRESS_CONTROL_EN 0 0 DIRECT_TRANSLATED_P2P_EN 0 0 SOURCE_VALIDATION_EN_ 0 0 TRANSLATION_BLOCKING_EN_ 1 1 P2P_REQUEST_REDIRECT_EN_ 2 2 P2P_COMPLETION_REDIRECT_EN_ 3 3 UPSTREAM_FORWARDING_EN_ 4 4 P2P_EGRESS_CONTROL_EN_ 5 5 DIRECT_TRANSLATED_P2P_EN_ 6 6 cfgPCIE_ATS_ENH_CAP_LIST 3 0x2b0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_ATS_CAP 3 0x2b4 6 0 4294967295 INVALIDATE_Q_DEPTH 0 0 PAGE_ALIGNED_REQUEST 0 0 GLOBAL_INVALIDATE_SUPPORTED 0 0 INVALIDATE_Q_DEPTH_ 0 4 PAGE_ALIGNED_REQUEST_ 5 5 GLOBAL_INVALIDATE_SUPPORTED_ 6 6 cfgPCIE_ATS_CNTL 3 0x2b6 4 0 4294967295 STU 0 0 ATC_ENABLE 0 0 STU_ 0 4 ATC_ENABLE_ 15 15 cfgPCIE_PAGE_REQ_ENH_CAP_LIST 3 0x2c0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_PAGE_REQ_CNTL 3 0x2c4 4 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 0 0 PRI_ENABLE_ 0 0 PRI_RESET_ 1 1 cfgPCIE_PAGE_REQ_STATUS 3 0x2c6 8 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 0 0 STOPPED 0 0 PRG_RESPONSE_PASID_REQUIRED 0 0 RESPONSE_FAILURE_ 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX_ 1 1 STOPPED_ 8 8 PRG_RESPONSE_PASID_REQUIRED_ 15 15 cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 3 0x2c8 2 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 0 OUTSTAND_PAGE_REQ_CAPACITY_ 0 31 cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 3 0x2cc 2 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 0 OUTSTAND_PAGE_REQ_ALLOC_ 0 31 cfgPCIE_PASID_ENH_CAP_LIST 3 0x2d0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_PASID_CAP 3 0x2d4 6 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 0 0 PASID_PRIV_MODE_SUPPORTED 0 0 MAX_PASID_WIDTH 0 0 PASID_EXE_PERMISSION_SUPPORTED_ 1 1 PASID_PRIV_MODE_SUPPORTED_ 2 2 MAX_PASID_WIDTH_ 8 12 cfgPCIE_PASID_CNTL 3 0x2d6 6 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 0 0 PASID_PRIV_MODE_SUPPORTED_ENABLE 0 0 PASID_ENABLE_ 0 0 PASID_EXE_PERMISSION_ENABLE_ 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE_ 2 2 cfgPCIE_TPH_REQR_ENH_CAP_LIST 3 0x2e0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_TPH_REQR_CAP 3 0x2e4 12 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 0 0 TPH_REQR_DEV_SPC_MODE_SUPPORTED 0 0 TPH_REQR_EXTND_TPH_REQR_SUPPORED 0 0 TPH_REQR_ST_TABLE_LOCATION 0 0 TPH_REQR_ST_TABLE_SIZE 0 0 TPH_REQR_NO_ST_MODE_SUPPORTED_ 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED_ 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED_ 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED_ 8 8 TPH_REQR_ST_TABLE_LOCATION_ 9 10 TPH_REQR_ST_TABLE_SIZE_ 16 26 cfgPCIE_TPH_REQR_CNTL 3 0x2e8 4 0 4294967295 TPH_REQR_ST_MODE_SEL 0 0 TPH_REQR_EN 0 0 TPH_REQR_ST_MODE_SEL_ 0 2 TPH_REQR_EN_ 8 9 cfgPCIE_MC_ENH_CAP_LIST 3 0x2f0 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_MC_CAP 3 0x2f4 6 0 4294967295 MC_MAX_GROUP 0 0 MC_WIN_SIZE_REQ 0 0 MC_ECRC_REGEN_SUPP 0 0 MC_MAX_GROUP_ 0 5 MC_WIN_SIZE_REQ_ 8 13 MC_ECRC_REGEN_SUPP_ 15 15 cfgPCIE_MC_CNTL 3 0x2f6 4 0 4294967295 MC_NUM_GROUP 0 0 MC_ENABLE 0 0 MC_NUM_GROUP_ 0 5 MC_ENABLE_ 15 15 cfgPCIE_MC_ADDR0 3 0x2f8 4 0 4294967295 MC_INDEX_POS 0 0 MC_BASE_ADDR_0 0 0 MC_INDEX_POS_ 0 5 MC_BASE_ADDR_0_ 12 31 cfgPCIE_MC_ADDR1 3 0x2fc 2 0 4294967295 MC_BASE_ADDR_1 0 0 MC_BASE_ADDR_1_ 0 31 cfgPCIE_MC_RCV0 3 0x300 2 0 4294967295 MC_RECEIVE_0 0 0 MC_RECEIVE_0_ 0 31 cfgPCIE_MC_RCV1 3 0x304 2 0 4294967295 MC_RECEIVE_1 0 0 MC_RECEIVE_1_ 0 31 cfgPCIE_MC_BLOCK_ALL0 3 0x308 2 0 4294967295 MC_BLOCK_ALL_0 0 0 MC_BLOCK_ALL_0_ 0 31 cfgPCIE_MC_BLOCK_ALL1 3 0x30c 2 0 4294967295 MC_BLOCK_ALL_1 0 0 MC_BLOCK_ALL_1_ 0 31 cfgPCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 2 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 0 MC_BLOCK_UNTRANSLATED_0_ 0 31 cfgPCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 2 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 0 MC_BLOCK_UNTRANSLATED_1_ 0 31 cfgPCIE_LTR_ENH_CAP_LIST 3 0x320 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_LTR_CAP 3 0x324 8 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 0 LTR_MAX_S_LATENCY_SCALE 0 0 LTR_MAX_NS_LATENCY_VALUE 0 0 LTR_MAX_NS_LATENCY_SCALE 0 0 LTR_MAX_S_LATENCY_VALUE_ 0 9 LTR_MAX_S_LATENCY_SCALE_ 10 12 LTR_MAX_NS_LATENCY_VALUE_ 16 25 LTR_MAX_NS_LATENCY_SCALE_ 26 28 cfgPCIE_ARI_ENH_CAP_LIST 3 0x328 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_ARI_CAP 3 0x32c 6 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 0 0 ARI_NEXT_FUNC_NUM 0 0 ARI_MFVC_FUNC_GROUPS_CAP_ 0 0 ARI_ACS_FUNC_GROUPS_CAP_ 1 1 ARI_NEXT_FUNC_NUM_ 8 15 cfgPCIE_ARI_CNTL 3 0x32e 6 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 0 0 ARI_FUNCTION_GROUP 0 0 ARI_MFVC_FUNC_GROUPS_EN_ 0 0 ARI_ACS_FUNC_GROUPS_EN_ 1 1 ARI_FUNCTION_GROUP_ 4 6 cfgPCIE_SRIOV_ENH_CAP_LIST 3 0x330 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_SRIOV_CAP 3 0x334 6 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 0 0 SRIOV_VF_MIGRATION_INTR_MSG_NUM 0 0 SRIOV_VF_MIGRATION_CAP_ 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED_ 1 1 SRIOV_VF_MIGRATION_INTR_MSG_NUM_ 21 31 cfgPCIE_SRIOV_CONTROL 3 0x338 10 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 0 0 SRIOV_VF_MIGRATION_INTR_ENABLE 0 0 SRIOV_VF_MSE 0 0 SRIOV_ARI_CAP_HIERARCHY 0 0 SRIOV_VF_ENABLE_ 0 0 SRIOV_VF_MIGRATION_ENABLE_ 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE_ 2 2 SRIOV_VF_MSE_ 3 3 SRIOV_ARI_CAP_HIERARCHY_ 4 4 cfgPCIE_SRIOV_STATUS 3 0x33a 2 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 SRIOV_VF_MIGRATION_STATUS_ 0 0 cfgPCIE_SRIOV_INITIAL_VFS 3 0x33c 2 0 4294967295 SRIOV_INITIAL_VFS 0 0 SRIOV_INITIAL_VFS_ 0 15 cfgPCIE_SRIOV_TOTAL_VFS 3 0x33e 2 0 4294967295 SRIOV_TOTAL_VFS 0 0 SRIOV_TOTAL_VFS_ 0 15 cfgPCIE_SRIOV_NUM_VFS 3 0x340 2 0 4294967295 SRIOV_NUM_VFS 0 0 SRIOV_NUM_VFS_ 0 15 cfgPCIE_SRIOV_FUNC_DEP_LINK 3 0x342 2 0 4294967295 SRIOV_FUNC_DEP_LINK 0 0 SRIOV_FUNC_DEP_LINK_ 0 7 cfgPCIE_SRIOV_FIRST_VF_OFFSET 3 0x344 2 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 0 SRIOV_FIRST_VF_OFFSET_ 0 15 cfgPCIE_SRIOV_VF_STRIDE 3 0x346 2 0 4294967295 SRIOV_VF_STRIDE 0 0 SRIOV_VF_STRIDE_ 0 15 cfgPCIE_SRIOV_VF_DEVICE_ID 3 0x34a 2 0 4294967295 SRIOV_VF_DEVICE_ID 0 0 SRIOV_VF_DEVICE_ID_ 0 15 cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 3 0x34c 2 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 0 SRIOV_SUPPORTED_PAGE_SIZE_ 0 31 cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 3 0x350 2 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 0 SRIOV_SYSTEM_PAGE_SIZE_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_0 3 0x354 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_1 3 0x358 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_2 3 0x35c 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_3 3 0x360 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_4 3 0x364 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_BASE_ADDR_5 3 0x368 2 0 4294967295 VF_BASE_ADDR 0 0 VF_BASE_ADDR_ 0 31 cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 0x36c 4 0 4294967295 SRIOV_VF_MIGRATION_STATE_BIF 0 0 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0 SRIOV_VF_MIGRATION_STATE_BIF_ 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_ 3 31 cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 3 0x400 6 0 4294967295 CAP_ID 0 0 CAP_VER 0 0 NEXT_PTR 0 0 CAP_ID_ 0 15 CAP_VER_ 16 19 NEXT_PTR_ 20 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 3 0x404 6 0 4294967295 VSEC_ID 0 0 VSEC_REV 0 0 VSEC_LENGTH 0 0 VSEC_ID_ 0 15 VSEC_REV_ 16 19 VSEC_LENGTH_ 20 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 3 0x408 4 0 4294967295 VF_EN 0 0 VF_NUM 0 0 VF_EN_ 0 0 VF_NUM_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 3 0x40c 28 0 4294967295 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 0 0 GFX_HANG_NEED_FLR_INTR_EN 0 0 GFX_VM_BUSY_TRANSITION_INTR_EN 0 0 UVD_CMD_COMPLETE_INTR_EN 0 0 UVD_HANG_SELF_RECOVERED_INTR_EN 0 0 UVD_HANG_NEED_FLR_INTR_EN 0 0 UVD_VM_BUSY_TRANSITION_INTR_EN 0 0 VCE_CMD_COMPLETE_INTR_EN 0 0 VCE_HANG_SELF_RECOVERED_INTR_EN 0 0 VCE_HANG_NEED_FLR_INTR_EN 0 0 VCE_VM_BUSY_TRANSITION_INTR_EN 0 0 HVVM_MAILBOX_TRN_ACK_INTR_EN 0 0 HVVM_MAILBOX_RCV_VALID_INTR_EN 0 0 GFX_CMD_COMPLETE_INTR_EN_ 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN_ 1 1 GFX_HANG_NEED_FLR_INTR_EN_ 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN_ 3 3 UVD_CMD_COMPLETE_INTR_EN_ 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN_ 9 9 UVD_HANG_NEED_FLR_INTR_EN_ 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN_ 11 11 VCE_CMD_COMPLETE_INTR_EN_ 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN_ 17 17 VCE_HANG_NEED_FLR_INTR_EN_ 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN_ 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN_ 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN_ 25 25 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 3 0x410 28 0 4294967295 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 0 0 GFX_HANG_NEED_FLR_INTR_STATUS 0 0 GFX_VM_BUSY_TRANSITION_INTR_STATUS 0 0 UVD_CMD_COMPLETE_INTR_STATUS 0 0 UVD_HANG_SELF_RECOVERED_INTR_STATUS 0 0 UVD_HANG_NEED_FLR_INTR_STATUS 0 0 UVD_VM_BUSY_TRANSITION_INTR_STATUS 0 0 VCE_CMD_COMPLETE_INTR_STATUS 0 0 VCE_HANG_SELF_RECOVERED_INTR_STATUS 0 0 VCE_HANG_NEED_FLR_INTR_STATUS 0 0 VCE_VM_BUSY_TRANSITION_INTR_STATUS 0 0 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 0 0 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 0 0 GFX_CMD_COMPLETE_INTR_STATUS_ 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS_ 1 1 GFX_HANG_NEED_FLR_INTR_STATUS_ 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS_ 3 3 UVD_CMD_COMPLETE_INTR_STATUS_ 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS_ 9 9 UVD_HANG_NEED_FLR_INTR_STATUS_ 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS_ 11 11 VCE_CMD_COMPLETE_INTR_STATUS_ 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS_ 17 17 VCE_HANG_NEED_FLR_INTR_STATUS_ 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS_ 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS_ 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS_ 25 25 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 3 0x414 2 0 4294967295 SOFT_PF_FLR 0 0 SOFT_PF_FLR_ 0 0 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 3 0x418 10 0 4294967295 VF_INDEX 0 0 TRN_MSG_DATA 0 0 TRN_MSG_VALID 0 0 RCV_MSG_DATA 0 0 RCV_MSG_ACK 0 0 VF_INDEX_ 0 7 TRN_MSG_DATA_ 8 11 TRN_MSG_VALID_ 15 15 RCV_MSG_DATA_ 16 19 RCV_MSG_ACK_ 24 24 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 3 0x41c 64 0 4294967295 VF0_TRN_ACK 0 0 VF0_RCV_VALID 0 0 VF1_TRN_ACK 0 0 VF1_RCV_VALID 0 0 VF2_TRN_ACK 0 0 VF2_RCV_VALID 0 0 VF3_TRN_ACK 0 0 VF3_RCV_VALID 0 0 VF4_TRN_ACK 0 0 VF4_RCV_VALID 0 0 VF5_TRN_ACK 0 0 VF5_RCV_VALID 0 0 VF6_TRN_ACK 0 0 VF6_RCV_VALID 0 0 VF7_TRN_ACK 0 0 VF7_RCV_VALID 0 0 VF8_TRN_ACK 0 0 VF8_RCV_VALID 0 0 VF9_TRN_ACK 0 0 VF9_RCV_VALID 0 0 VF10_TRN_ACK 0 0 VF10_RCV_VALID 0 0 VF11_TRN_ACK 0 0 VF11_RCV_VALID 0 0 VF12_TRN_ACK 0 0 VF12_RCV_VALID 0 0 VF13_TRN_ACK 0 0 VF13_RCV_VALID 0 0 VF14_TRN_ACK 0 0 VF14_RCV_VALID 0 0 VF15_TRN_ACK 0 0 VF15_RCV_VALID 0 0 VF0_TRN_ACK_ 0 0 VF0_RCV_VALID_ 1 1 VF1_TRN_ACK_ 2 2 VF1_RCV_VALID_ 3 3 VF2_TRN_ACK_ 4 4 VF2_RCV_VALID_ 5 5 VF3_TRN_ACK_ 6 6 VF3_RCV_VALID_ 7 7 VF4_TRN_ACK_ 8 8 VF4_RCV_VALID_ 9 9 VF5_TRN_ACK_ 10 10 VF5_RCV_VALID_ 11 11 VF6_TRN_ACK_ 12 12 VF6_RCV_VALID_ 13 13 VF7_TRN_ACK_ 14 14 VF7_RCV_VALID_ 15 15 VF8_TRN_ACK_ 16 16 VF8_RCV_VALID_ 17 17 VF9_TRN_ACK_ 18 18 VF9_RCV_VALID_ 19 19 VF10_TRN_ACK_ 20 20 VF10_RCV_VALID_ 21 21 VF11_TRN_ACK_ 22 22 VF11_RCV_VALID_ 23 23 VF12_TRN_ACK_ 24 24 VF12_RCV_VALID_ 25 25 VF13_TRN_ACK_ 26 26 VF13_RCV_VALID_ 27 27 VF14_TRN_ACK_ 28 28 VF14_RCV_VALID_ 29 29 VF15_TRN_ACK_ 30 30 VF15_RCV_VALID_ 31 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 3 0x420 4 0 4294967295 PF_TRN_ACK 0 0 PF_RCV_VALID 0 0 PF_TRN_ACK_ 0 0 PF_RCV_VALID_ 1 1 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 3 0x424 6 0 4294967295 CONTEXT_SIZE 0 0 LOC 0 0 CONTEXT_OFFSET 0 0 CONTEXT_SIZE_ 0 6 LOC_ 7 7 CONTEXT_OFFSET_ 10 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 3 0x428 4 0 4294967295 TOTAL_FB_AVAILABLE 0 0 TOTAL_FB_CONSUMED 0 0 TOTAL_FB_AVAILABLE_ 0 15 TOTAL_FB_CONSUMED_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 3 0x42c 6 0 4294967295 UVDSCH_OFFSET 0 0 VCESCH_OFFSET 0 0 GFXSCH_OFFSET 0 0 UVDSCH_OFFSET_ 0 7 VCESCH_OFFSET_ 8 15 GFXSCH_OFFSET_ 16 23 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 3 0x430 4 0 4294967295 VF0_FB_SIZE 0 0 VF0_FB_OFFSET 0 0 VF0_FB_SIZE_ 0 15 VF0_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 3 0x434 4 0 4294967295 VF1_FB_SIZE 0 0 VF1_FB_OFFSET 0 0 VF1_FB_SIZE_ 0 15 VF1_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 3 0x438 4 0 4294967295 VF2_FB_SIZE 0 0 VF2_FB_OFFSET 0 0 VF2_FB_SIZE_ 0 15 VF2_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 3 0x43c 4 0 4294967295 VF3_FB_SIZE 0 0 VF3_FB_OFFSET 0 0 VF3_FB_SIZE_ 0 15 VF3_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 3 0x440 4 0 4294967295 VF4_FB_SIZE 0 0 VF4_FB_OFFSET 0 0 VF4_FB_SIZE_ 0 15 VF4_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 3 0x444 4 0 4294967295 VF5_FB_SIZE 0 0 VF5_FB_OFFSET 0 0 VF5_FB_SIZE_ 0 15 VF5_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 3 0x448 4 0 4294967295 VF6_FB_SIZE 0 0 VF6_FB_OFFSET 0 0 VF6_FB_SIZE_ 0 15 VF6_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 3 0x44c 4 0 4294967295 VF7_FB_SIZE 0 0 VF7_FB_OFFSET 0 0 VF7_FB_SIZE_ 0 15 VF7_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 3 0x450 4 0 4294967295 VF8_FB_SIZE 0 0 VF8_FB_OFFSET 0 0 VF8_FB_SIZE_ 0 15 VF8_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 3 0x454 4 0 4294967295 VF9_FB_SIZE 0 0 VF9_FB_OFFSET 0 0 VF9_FB_SIZE_ 0 15 VF9_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 3 0x458 4 0 4294967295 VF10_FB_SIZE 0 0 VF10_FB_OFFSET 0 0 VF10_FB_SIZE_ 0 15 VF10_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 3 0x45c 4 0 4294967295 VF11_FB_SIZE 0 0 VF11_FB_OFFSET 0 0 VF11_FB_SIZE_ 0 15 VF11_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 3 0x460 4 0 4294967295 VF12_FB_SIZE 0 0 VF12_FB_OFFSET 0 0 VF12_FB_SIZE_ 0 15 VF12_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 3 0x464 4 0 4294967295 VF13_FB_SIZE 0 0 VF13_FB_OFFSET 0 0 VF13_FB_SIZE_ 0 15 VF13_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 3 0x468 4 0 4294967295 VF14_FB_SIZE 0 0 VF14_FB_OFFSET 0 0 VF14_FB_SIZE_ 0 15 VF14_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 3 0x46c 4 0 4294967295 VF15_FB_SIZE 0 0 VF15_FB_OFFSET 0 0 VF15_FB_SIZE_ 0 15 VF15_FB_OFFSET_ 16 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 3 0x470 2 0 4294967295 DW0 0 0 DW0_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 3 0x474 2 0 4294967295 DW1 0 0 DW1_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 3 0x478 2 0 4294967295 DW2 0 0 DW2_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 3 0x47c 2 0 4294967295 DW3 0 0 DW3_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 3 0x480 2 0 4294967295 DW4 0 0 DW4_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 3 0x484 2 0 4294967295 DW5 0 0 DW5_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 3 0x488 2 0 4294967295 DW6 0 0 DW6_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 3 0x48c 2 0 4294967295 DW7 0 0 DW7_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 3 0x490 2 0 4294967295 DW0 0 0 DW0_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 3 0x494 2 0 4294967295 DW1 0 0 DW1_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 3 0x498 2 0 4294967295 DW2 0 0 DW2_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 3 0x49c 2 0 4294967295 DW3 0 0 DW3_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 3 0x4a0 2 0 4294967295 DW4 0 0 DW4_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 3 0x4a4 2 0 4294967295 DW5 0 0 DW5_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 3 0x4a8 2 0 4294967295 DW6 0 0 DW6_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 3 0x4ac 2 0 4294967295 DW7 0 0 DW7_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 3 0x4b0 2 0 4294967295 DW0 0 0 DW0_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 3 0x4b4 2 0 4294967295 DW1 0 0 DW1_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 3 0x4b8 2 0 4294967295 DW2 0 0 DW2_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 3 0x4bc 2 0 4294967295 DW3 0 0 DW3_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 3 0x4c0 2 0 4294967295 DW4 0 0 DW4_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 3 0x4c4 2 0 4294967295 DW5 0 0 DW5_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 3 0x4c8 2 0 4294967295 DW6 0 0 DW6_ 0 31 cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 3 0x4cc 2 0 4294967295 DW7 0 0 DW7_ 0 31 mmSUB_BUS_NUMBER_LATENCY 0 0x6 8 0 0 PRIMARY_BUS 0 0 SECONDARY_BUS 0 0 SUB_BUS_NUM 0 0 SECONDARY_LATENCY_TIMER 0 0 PRIMARY_BUS_ 0 7 SECONDARY_BUS_ 8 15 SUB_BUS_NUM_ 16 23 SECONDARY_LATENCY_TIMER_ 24 31 mmIO_BASE_LIMIT 0 0x7 8 0 0 IO_BASE_TYPE 0 0 IO_BASE 0 0 IO_LIMIT_TYPE 0 0 IO_LIMIT 0 0 IO_BASE_TYPE_ 0 3 IO_BASE_ 4 7 IO_LIMIT_TYPE_ 8 11 IO_LIMIT_ 12 15 mmSECONDARY_STATUS 0 0x7 20 0 0 CAP_LIST 0 0 PCI_66_EN 0 0 FAST_BACK_CAPABLE 0 0 MASTER_DATA_PARITY_ERROR 0 0 DEVSEL_TIMING 0 0 SIGNAL_TARGET_ABORT 0 0 RECEIVED_TARGET_ABORT 0 0 RECEIVED_MASTER_ABORT 0 0 RECEIVED_SYSTEM_ERROR 0 0 PARITY_ERROR_DETECTED 0 0 CAP_LIST_ 4 4 PCI_66_EN_ 5 5 FAST_BACK_CAPABLE_ 7 7 MASTER_DATA_PARITY_ERROR_ 8 8 DEVSEL_TIMING_ 9 10 SIGNAL_TARGET_ABORT_ 11 11 RECEIVED_TARGET_ABORT_ 12 12 RECEIVED_MASTER_ABORT_ 13 13 RECEIVED_SYSTEM_ERROR_ 14 14 PARITY_ERROR_DETECTED_ 15 15 mmMEM_BASE_LIMIT 0 0x8 8 0 0 MEM_BASE_TYPE 0 0 MEM_BASE_31_20 0 0 MEM_LIMIT_TYPE 0 0 MEM_LIMIT_31_20 0 0 MEM_BASE_TYPE_ 0 3 MEM_BASE_31_20_ 4 15 MEM_LIMIT_TYPE_ 16 19 MEM_LIMIT_31_20_ 20 31 mmPREF_BASE_LIMIT 0 0x9 8 0 0 PREF_MEM_BASE_TYPE 0 0 PREF_MEM_BASE_31_20 0 0 PREF_MEM_LIMIT_TYPE 0 0 PREF_MEM_LIMIT_31_20 0 0 PREF_MEM_BASE_TYPE_ 0 3 PREF_MEM_BASE_31_20_ 4 15 PREF_MEM_LIMIT_TYPE_ 16 19 PREF_MEM_LIMIT_31_20_ 20 31 mmPREF_BASE_UPPER 0 0xa 2 0 0 PREF_BASE_UPPER 0 0 PREF_BASE_UPPER_ 0 31 mmPREF_LIMIT_UPPER 0 0xb 2 0 0 PREF_LIMIT_UPPER 0 0 PREF_LIMIT_UPPER_ 0 31 mmIO_BASE_LIMIT_HI 0 0xc 4 0 0 IO_BASE_31_16 0 0 IO_LIMIT_31_16 0 0 IO_BASE_31_16_ 0 15 IO_LIMIT_31_16_ 16 31 mmIRQ_BRIDGE_CNTL 0 0xf 16 0 0 PARITY_RESPONSE_EN 0 0 SERR_EN 0 0 ISA_EN 0 0 VGA_EN 0 0 VGA_DEC 0 0 MASTER_ABORT_MODE 0 0 SECONDARY_BUS_RESET 0 0 FAST_B2B_EN 0 0 PARITY_RESPONSE_EN_ 0 0 SERR_EN_ 1 1 ISA_EN_ 2 2 VGA_EN_ 3 3 VGA_DEC_ 4 4 MASTER_ABORT_MODE_ 5 5 SECONDARY_BUS_RESET_ 6 6 FAST_B2B_EN_ 7 7 mmSLOT_CAP 0 0x1b 24 0 0 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 0 0 MRL_SENSOR_PRESENT 0 0 ATTN_INDICATOR_PRESENT 0 0 PWR_INDICATOR_PRESENT 0 0 HOTPLUG_SURPRISE 0 0 HOTPLUG_CAPABLE 0 0 SLOT_PWR_LIMIT_VALUE 0 0 SLOT_PWR_LIMIT_SCALE 0 0 ELECTROMECH_INTERLOCK_PRESENT 0 0 NO_COMMAND_COMPLETED_SUPPORTED 0 0 PHYSICAL_SLOT_NUM 0 0 ATTN_BUTTON_PRESENT_ 0 0 PWR_CONTROLLER_PRESENT_ 1 1 MRL_SENSOR_PRESENT_ 2 2 ATTN_INDICATOR_PRESENT_ 3 3 PWR_INDICATOR_PRESENT_ 4 4 HOTPLUG_SURPRISE_ 5 5 HOTPLUG_CAPABLE_ 6 6 SLOT_PWR_LIMIT_VALUE_ 7 14 SLOT_PWR_LIMIT_SCALE_ 15 16 ELECTROMECH_INTERLOCK_PRESENT_ 17 17 NO_COMMAND_COMPLETED_SUPPORTED_ 18 18 PHYSICAL_SLOT_NUM_ 19 31 mmSLOT_CNTL 0 0x1c 22 0 0 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 0 0 MRL_SENSOR_CHANGED_EN 0 0 PRESENCE_DETECT_CHANGED_EN 0 0 COMMAND_COMPLETED_INTR_EN 0 0 HOTPLUG_INTR_EN 0 0 ATTN_INDICATOR_CNTL 0 0 PWR_INDICATOR_CNTL 0 0 PWR_CONTROLLER_CNTL 0 0 ELECTROMECH_INTERLOCK_CNTL 0 0 DL_STATE_CHANGED_EN 0 0 ATTN_BUTTON_PRESSED_EN_ 0 0 PWR_FAULT_DETECTED_EN_ 1 1 MRL_SENSOR_CHANGED_EN_ 2 2 PRESENCE_DETECT_CHANGED_EN_ 3 3 COMMAND_COMPLETED_INTR_EN_ 4 4 HOTPLUG_INTR_EN_ 5 5 ATTN_INDICATOR_CNTL_ 6 7 PWR_INDICATOR_CNTL_ 8 9 PWR_CONTROLLER_CNTL_ 10 10 ELECTROMECH_INTERLOCK_CNTL_ 11 11 DL_STATE_CHANGED_EN_ 12 12 mmSLOT_STATUS 0 0x1c 18 0 0 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 0 0 MRL_SENSOR_CHANGED 0 0 PRESENCE_DETECT_CHANGED 0 0 COMMAND_COMPLETED 0 0 MRL_SENSOR_STATE 0 0 PRESENCE_DETECT_STATE 0 0 ELECTROMECH_INTERLOCK_STATUS 0 0 DL_STATE_CHANGED 0 0 ATTN_BUTTON_PRESSED_ 0 0 PWR_FAULT_DETECTED_ 1 1 MRL_SENSOR_CHANGED_ 2 2 PRESENCE_DETECT_CHANGED_ 3 3 COMMAND_COMPLETED_ 4 4 MRL_SENSOR_STATE_ 5 5 PRESENCE_DETECT_STATE_ 6 6 ELECTROMECH_INTERLOCK_STATUS_ 7 7 DL_STATE_CHANGED_ 8 8 mmSSID_CAP_LIST 0 0x30 4 0 0 CAP_ID 0 0 NEXT_PTR 0 0 CAP_ID_ 0 7 NEXT_PTR_ 8 15 mmSSID_CAP 0 0x31 4 0 0 SUBSYSTEM_VENDOR_ID 0 0 SUBSYSTEM_ID 0 0 SUBSYSTEM_VENDOR_ID_ 0 15 SUBSYSTEM_ID_ 16 31 ixSHADOW_COMMAND 2 0x4 4 0 4294967295 IOEN_UP 0 0 MEMEN_UP 0 0 IOEN_UP_ 0 0 MEMEN_UP_ 1 1 ixSHADOW_BASE_ADDR_1 2 0x10 2 0 4294967295 BAR1_UP 0 0 BAR1_UP_ 0 31 ixSHADOW_BASE_ADDR_2 2 0x14 2 0 4294967295 BAR2_UP 0 0 BAR2_UP_ 0 31 ixSHADOW_SUB_BUS_NUMBER_LATENCY 2 0x18 4 0 4294967295 SECONDARY_BUS_UP 0 0 SUB_BUS_NUM_UP 0 0 SECONDARY_BUS_UP_ 8 15 SUB_BUS_NUM_UP_ 16 23 ixSHADOW_IO_BASE_LIMIT 2 0x1c 4 0 4294967295 IO_BASE_UP 0 0 IO_LIMIT_UP 0 0 IO_BASE_UP_ 4 7 IO_LIMIT_UP_ 12 15 ixSHADOW_MEM_BASE_LIMIT 2 0x20 8 0 4294967295 MEM_BASE_TYPE 0 0 MEM_BASE_31_20_UP 0 0 MEM_LIMIT_TYPE 0 0 MEM_LIMIT_31_20_UP 0 0 MEM_BASE_TYPE_ 0 3 MEM_BASE_31_20_UP_ 4 15 MEM_LIMIT_TYPE_ 16 19 MEM_LIMIT_31_20_UP_ 20 31 ixSHADOW_PREF_BASE_LIMIT 2 0x24 8 0 4294967295 PREF_MEM_BASE_TYPE 0 0 PREF_MEM_BASE_31_20_UP 0 0 PREF_MEM_LIMIT_TYPE 0 0 PREF_MEM_LIMIT_31_20_UP 0 0 PREF_MEM_BASE_TYPE_ 0 3 PREF_MEM_BASE_31_20_UP_ 4 15 PREF_MEM_LIMIT_TYPE_ 16 19 PREF_MEM_LIMIT_31_20_UP_ 20 31 ixSHADOW_PREF_BASE_UPPER 2 0x28 2 0 4294967295 PREF_BASE_UPPER_UP 0 0 PREF_BASE_UPPER_UP_ 0 31 ixSHADOW_PREF_LIMIT_UPPER 2 0x2c 2 0 4294967295 PREF_LIMIT_UPPER_UP 0 0 PREF_LIMIT_UPPER_UP_ 0 31 ixSHADOW_IO_BASE_LIMIT_HI 2 0x30 4 0 4294967295 IO_BASE_31_16_UP 0 0 IO_LIMIT_31_16_UP 0 0 IO_BASE_31_16_UP_ 0 15 IO_LIMIT_31_16_UP_ 16 31 ixSHADOW_IRQ_BRIDGE_CNTL 2 0x3e 8 0 4294967295 ISA_EN_UP 0 0 VGA_EN_UP 0 0 VGA_DEC_UP 0 0 SECONDARY_BUS_RESET_UP 0 0 ISA_EN_UP_ 2 2 VGA_EN_UP_ 3 3 VGA_DEC_UP_ 4 4 SECONDARY_BUS_RESET_UP_ 6 6 ixSUC_INDEX 2 0xe0 2 0 4294967295 SUC_INDEX 0 0 SUC_INDEX_ 0 31 ixSUC_DATA 2 0xe4 2 0 4294967295 SUC_DATA 0 0 SUC_DATA_ 0 31 ixSUM_INDEX 2 0xe0 2 0 4294967295 SUM_INDEX 0 0 SUM_INDEX_ 0 31 ixSUM_DATA 2 0xe4 2 0 4294967295 SUM_DATA 0 0 SUM_DATA_ 0 31 mmA2S_CNTL_CL0 0 0x4f0ab0 22 0 3 NSNOOP_MAP 0 0 REQPASSPW_VC0_MAP 0 0 REQPASSPW_NVC0_MAP 0 0 REQRSPPASSPW_VC0_MAP 0 0 REQRSPPASSPW_NVC0_MAP 0 0 BLKLVL_MAP 0 0 DATERR_MAP 0 0 EXOKAY_WR_MAP 0 0 EXOKAY_RD_MAP 0 0 RESP_WR_MAP 0 0 RESP_RD_MAP 0 0 NSNOOP_MAP_ 0 1 REQPASSPW_VC0_MAP_ 2 3 REQPASSPW_NVC0_MAP_ 4 5 REQRSPPASSPW_VC0_MAP_ 6 7 REQRSPPASSPW_NVC0_MAP_ 8 9 BLKLVL_MAP_ 10 11 DATERR_MAP_ 12 13 EXOKAY_WR_MAP_ 14 15 EXOKAY_RD_MAP_ 16 17 RESP_WR_MAP_ 18 19 RESP_RD_MAP_ 20 21 mmA2S_CNTL_CL1 0 0x4f0ab1 22 0 3 NSNOOP_MAP 0 0 REQPASSPW_VC0_MAP 0 0 REQPASSPW_NVC0_MAP 0 0 REQRSPPASSPW_VC0_MAP 0 0 REQRSPPASSPW_NVC0_MAP 0 0 BLKLVL_MAP 0 0 DATERR_MAP 0 0 EXOKAY_WR_MAP 0 0 EXOKAY_RD_MAP 0 0 RESP_WR_MAP 0 0 RESP_RD_MAP 0 0 NSNOOP_MAP_ 0 1 REQPASSPW_VC0_MAP_ 2 3 REQPASSPW_NVC0_MAP_ 4 5 REQRSPPASSPW_VC0_MAP_ 6 7 REQRSPPASSPW_NVC0_MAP_ 8 9 BLKLVL_MAP_ 10 11 DATERR_MAP_ 12 13 EXOKAY_WR_MAP_ 14 15 EXOKAY_RD_MAP_ 16 17 RESP_WR_MAP_ 18 19 RESP_RD_MAP_ 20 21 mmA2S_CNTL_CL2 0 0x4f0ab2 22 0 3 NSNOOP_MAP 0 0 REQPASSPW_VC0_MAP 0 0 REQPASSPW_NVC0_MAP 0 0 REQRSPPASSPW_VC0_MAP 0 0 REQRSPPASSPW_NVC0_MAP 0 0 BLKLVL_MAP 0 0 DATERR_MAP 0 0 EXOKAY_WR_MAP 0 0 EXOKAY_RD_MAP 0 0 RESP_WR_MAP 0 0 RESP_RD_MAP 0 0 NSNOOP_MAP_ 0 1 REQPASSPW_VC0_MAP_ 2 3 REQPASSPW_NVC0_MAP_ 4 5 REQRSPPASSPW_VC0_MAP_ 6 7 REQRSPPASSPW_NVC0_MAP_ 8 9 BLKLVL_MAP_ 10 11 DATERR_MAP_ 12 13 EXOKAY_WR_MAP_ 14 15 EXOKAY_RD_MAP_ 16 17 RESP_WR_MAP_ 18 19 RESP_RD_MAP_ 20 21 mmA2S_CNTL_CL3 0 0x4f0ab3 22 0 3 NSNOOP_MAP 0 0 REQPASSPW_VC0_MAP 0 0 REQPASSPW_NVC0_MAP 0 0 REQRSPPASSPW_VC0_MAP 0 0 REQRSPPASSPW_NVC0_MAP 0 0 BLKLVL_MAP 0 0 DATERR_MAP 0 0 EXOKAY_WR_MAP 0 0 EXOKAY_RD_MAP 0 0 RESP_WR_MAP 0 0 RESP_RD_MAP 0 0 NSNOOP_MAP_ 0 1 REQPASSPW_VC0_MAP_ 2 3 REQPASSPW_NVC0_MAP_ 4 5 REQRSPPASSPW_VC0_MAP_ 6 7 REQRSPPASSPW_NVC0_MAP_ 8 9 BLKLVL_MAP_ 10 11 DATERR_MAP_ 12 13 EXOKAY_WR_MAP_ 14 15 EXOKAY_RD_MAP_ 16 17 RESP_WR_MAP_ 18 19 RESP_RD_MAP_ 20 21 mmA2S_CNTL_CL4 0 0x4f0ab4 22 0 3 NSNOOP_MAP 0 0 REQPASSPW_VC0_MAP 0 0 REQPASSPW_NVC0_MAP 0 0 REQRSPPASSPW_VC0_MAP 0 0 REQRSPPASSPW_NVC0_MAP 0 0 BLKLVL_MAP 0 0 DATERR_MAP 0 0 EXOKAY_WR_MAP 0 0 EXOKAY_RD_MAP 0 0 RESP_WR_MAP 0 0 RESP_RD_MAP 0 0 NSNOOP_MAP_ 0 1 REQPASSPW_VC0_MAP_ 2 3 REQPASSPW_NVC0_MAP_ 4 5 REQRSPPASSPW_VC0_MAP_ 6 7 REQRSPPASSPW_NVC0_MAP_ 8 9 BLKLVL_MAP_ 10 11 DATERR_MAP_ 12 13 EXOKAY_WR_MAP_ 14 15 EXOKAY_RD_MAP_ 16 17 RESP_WR_MAP_ 18 19 RESP_RD_MAP_ 20 21 mmA2S_CNTL_SW0 0 0x4f0ad0 22 0 3 WR_TAG_SET_MIN 0 0 RD_TAG_SET_MIN 0 0 FORCE_RSP_REORDER_EN 0 0 RSP_REORDER_DIS 0 0 WRRSP_ACCUM_SEL 0 0 SDP_WR_CHAIN_DIS 0 0 WRRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_STS_DATSTS_PRIORITY 0 0 WRR_RD_WEIGHT 0 0 WRR_WR_WEIGHT 0 0 WR_TAG_SET_MIN_ 0 2 RD_TAG_SET_MIN_ 3 5 FORCE_RSP_REORDER_EN_ 6 6 RSP_REORDER_DIS_ 7 7 WRRSP_ACCUM_SEL_ 8 8 SDP_WR_CHAIN_DIS_ 9 9 WRRSP_TAGFIFO_CONT_RD_DIS_ 10 10 RDRSP_TAGFIFO_CONT_RD_DIS_ 11 11 RDRSP_STS_DATSTS_PRIORITY_ 12 12 WRR_RD_WEIGHT_ 16 23 WRR_WR_WEIGHT_ 24 31 mmA2S_CNTL_SW1 0 0x4f0ad1 22 0 3 WR_TAG_SET_MIN 0 0 RD_TAG_SET_MIN 0 0 FORCE_RSP_REORDER_EN 0 0 RSP_REORDER_DIS 0 0 WRRSP_ACCUM_SEL 0 0 SDP_WR_CHAIN_DIS 0 0 WRRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_STS_DATSTS_PRIORITY 0 0 WRR_RD_WEIGHT 0 0 WRR_WR_WEIGHT 0 0 WR_TAG_SET_MIN_ 0 2 RD_TAG_SET_MIN_ 3 5 FORCE_RSP_REORDER_EN_ 6 6 RSP_REORDER_DIS_ 7 7 WRRSP_ACCUM_SEL_ 8 8 SDP_WR_CHAIN_DIS_ 9 9 WRRSP_TAGFIFO_CONT_RD_DIS_ 10 10 RDRSP_TAGFIFO_CONT_RD_DIS_ 11 11 RDRSP_STS_DATSTS_PRIORITY_ 12 12 WRR_RD_WEIGHT_ 16 23 WRR_WR_WEIGHT_ 24 31 mmA2S_CNTL_SW2 0 0x4f0ad2 22 0 3 WR_TAG_SET_MIN 0 0 RD_TAG_SET_MIN 0 0 FORCE_RSP_REORDER_EN 0 0 RSP_REORDER_DIS 0 0 WRRSP_ACCUM_SEL 0 0 SDP_WR_CHAIN_DIS 0 0 WRRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_TAGFIFO_CONT_RD_DIS 0 0 RDRSP_STS_DATSTS_PRIORITY 0 0 WRR_RD_WEIGHT 0 0 WRR_WR_WEIGHT 0 0 WR_TAG_SET_MIN_ 0 2 RD_TAG_SET_MIN_ 3 5 FORCE_RSP_REORDER_EN_ 6 6 RSP_REORDER_DIS_ 7 7 WRRSP_ACCUM_SEL_ 8 8 SDP_WR_CHAIN_DIS_ 9 9 WRRSP_TAGFIFO_CONT_RD_DIS_ 10 10 RDRSP_TAGFIFO_CONT_RD_DIS_ 11 11 RDRSP_STS_DATSTS_PRIORITY_ 12 12 WRR_RD_WEIGHT_ 16 23 WRR_WR_WEIGHT_ 24 31 mmNGDC_MGCG_CTRL 0 0x4f0ae0 6 0 3 NGDC_MGCG_EN 0 0 NGDC_MGCG_MODE 0 0 NGDC_MGCG_HYSTERESIS 0 0 NGDC_MGCG_EN_ 0 0 NGDC_MGCG_MODE_ 1 1 NGDC_MGCG_HYSTERESIS_ 2 9 mmA2S_MISC_CNTL 0 0x4f0ae1 4 0 3 BLKLVL_FOR_MSG 0 0 RESERVE_2_CRED_FOR_NPWR_REQ_DIS 0 0 BLKLVL_FOR_MSG_ 0 1 RESERVE_2_CRED_FOR_NPWR_REQ_DIS_ 2 2 mmNGDC_SDP_PORT_CTRL 0 0x4f0ae2 2 0 3 SDP_DISCON_HYSTERESIS 0 0 SDP_DISCON_HYSTERESIS_ 0 5 mmNGDC_RESERVED_0 0 0x4f0aeb 2 0 3 RESERVED 0 0 RESERVED_ 0 31 mmNGDC_RESERVED_1 0 0x4f0aec 2 0 3 RESERVED 0 0 RESERVED_ 0 31 mmBIF_SDMA0_DOORBELL_RANGE 0 0x4f0af0 4 0 3 OFFSET 0 0 SIZE 0 0 OFFSET_ 2 11 SIZE_ 16 20 mmBIF_SDMA1_DOORBELL_RANGE 0 0x4f0af1 4 0 3 OFFSET 0 0 SIZE 0 0 OFFSET_ 2 11 SIZE_ 16 20 mmBIF_IH_DOORBELL_RANGE 0 0x4f0af2 4 0 3 OFFSET 0 0 SIZE 0 0 OFFSET_ 2 11 SIZE_ 16 20 mmBIF_MMSCH0_DOORBELL_RANGE 0 0x4f0af3 4 0 3 OFFSET 0 0 SIZE 0 0 OFFSET_ 2 11 SIZE_ 16 20 mmBIF_DOORBELL_FENCE_CNTL 0 0x4f0afe 2 0 3 DOORBELL_FENCE_ENABLE 0 0 DOORBELL_FENCE_ENABLE_ 0 0 mmS2A_MISC_CNTL 0 0x4f0aff 6 0 3 DOORBELL_64BIT_SUPPORT_SDMA0_DIS 0 0 DOORBELL_64BIT_SUPPORT_SDMA1_DIS 0 0 DOORBELL_64BIT_SUPPORT_CP_DIS 0 0 DOORBELL_64BIT_SUPPORT_SDMA0_DIS_ 0 0 DOORBELL_64BIT_SUPPORT_SDMA1_DIS_ 1 1 DOORBELL_64BIT_SUPPORT_CP_DIS_ 2 2 mmA2S_CNTL2_SEC_CL0 0 0x4f0b00 2 0 3 SECLVL_MAP 0 0 SECLVL_MAP_ 0 2 mmA2S_CNTL2_SEC_CL1 0 0x4f0b01 2 0 3 SECLVL_MAP 0 0 SECLVL_MAP_ 0 2 mmA2S_CNTL2_SEC_CL2 0 0x4f0b02 2 0 3 SECLVL_MAP 0 0 SECLVL_MAP_ 0 2 mmA2S_CNTL2_SEC_CL3 0 0x4f0b03 2 0 3 SECLVL_MAP 0 0 SECLVL_MAP_ 0 2 mmA2S_CNTL2_SEC_CL4 0 0x4f0b04 2 0 3 SECLVL_MAP 0 0 SECLVL_MAP_ 0 2 ixSION_CL0_RdRsp_BurstTarget_REG0 2 0x1e000 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL0_RdRsp_BurstTarget_REG1 2 0x1e004 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL0_RdRsp_TimeSlot_REG0 2 0x1e008 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL0_RdRsp_TimeSlot_REG1 2 0x1e00c 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL0_WrRsp_BurstTarget_REG0 2 0x1e010 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL0_WrRsp_BurstTarget_REG1 2 0x1e014 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL0_WrRsp_TimeSlot_REG0 2 0x1e018 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL0_WrRsp_TimeSlot_REG1 2 0x1e01c 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL0_Req_BurstTarget_REG0 2 0x1e020 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL0_Req_BurstTarget_REG1 2 0x1e024 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL0_Req_TimeSlot_REG0 2 0x1e028 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL0_Req_TimeSlot_REG1 2 0x1e02c 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL0_ReqPoolCredit_Alloc_REG0 2 0x1e030 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL0_ReqPoolCredit_Alloc_REG1 2 0x1e034 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL0_DataPoolCredit_Alloc_REG0 2 0x1e038 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL0_DataPoolCredit_Alloc_REG1 2 0x1e03c 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL0_RdRspPoolCredit_Alloc_REG0 2 0x1e040 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL0_RdRspPoolCredit_Alloc_REG1 2 0x1e044 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL0_WrRspPoolCredit_Alloc_REG0 2 0x1e048 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL0_WrRspPoolCredit_Alloc_REG1 2 0x1e04c 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL1_RdRsp_BurstTarget_REG0 2 0x1e050 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL1_RdRsp_BurstTarget_REG1 2 0x1e054 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL1_RdRsp_TimeSlot_REG0 2 0x1e058 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL1_RdRsp_TimeSlot_REG1 2 0x1e05c 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL1_WrRsp_BurstTarget_REG0 2 0x1e060 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL1_WrRsp_BurstTarget_REG1 2 0x1e064 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL1_WrRsp_TimeSlot_REG0 2 0x1e068 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL1_WrRsp_TimeSlot_REG1 2 0x1e06c 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL1_Req_BurstTarget_REG0 2 0x1e070 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL1_Req_BurstTarget_REG1 2 0x1e074 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL1_Req_TimeSlot_REG0 2 0x1e078 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL1_Req_TimeSlot_REG1 2 0x1e07c 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL1_ReqPoolCredit_Alloc_REG0 2 0x1e080 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL1_ReqPoolCredit_Alloc_REG1 2 0x1e084 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL1_DataPoolCredit_Alloc_REG0 2 0x1e088 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL1_DataPoolCredit_Alloc_REG1 2 0x1e08c 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL1_RdRspPoolCredit_Alloc_REG0 2 0x1e090 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL1_RdRspPoolCredit_Alloc_REG1 2 0x1e094 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL1_WrRspPoolCredit_Alloc_REG0 2 0x1e098 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL1_WrRspPoolCredit_Alloc_REG1 2 0x1e09c 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL2_RdRsp_BurstTarget_REG0 2 0x1e0a0 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL2_RdRsp_BurstTarget_REG1 2 0x1e0a4 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL2_RdRsp_TimeSlot_REG0 2 0x1e0a8 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL2_RdRsp_TimeSlot_REG1 2 0x1e0ac 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL2_WrRsp_BurstTarget_REG0 2 0x1e0b0 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL2_WrRsp_BurstTarget_REG1 2 0x1e0b4 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL2_WrRsp_TimeSlot_REG0 2 0x1e0b8 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL2_WrRsp_TimeSlot_REG1 2 0x1e0bc 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL2_Req_BurstTarget_REG0 2 0x1e0c0 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL2_Req_BurstTarget_REG1 2 0x1e0c4 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL2_Req_TimeSlot_REG0 2 0x1e0c8 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL2_Req_TimeSlot_REG1 2 0x1e0cc 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL2_ReqPoolCredit_Alloc_REG0 2 0x1e0d0 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL2_ReqPoolCredit_Alloc_REG1 2 0x1e0d4 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL2_DataPoolCredit_Alloc_REG0 2 0x1e0d8 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL2_DataPoolCredit_Alloc_REG1 2 0x1e0dc 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL2_RdRspPoolCredit_Alloc_REG0 2 0x1e0e0 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL2_RdRspPoolCredit_Alloc_REG1 2 0x1e0e4 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL2_WrRspPoolCredit_Alloc_REG0 2 0x1e0e8 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL2_WrRspPoolCredit_Alloc_REG1 2 0x1e0ec 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL3_RdRsp_BurstTarget_REG0 2 0x1e0f0 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL3_RdRsp_BurstTarget_REG1 2 0x1e0f4 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL3_RdRsp_TimeSlot_REG0 2 0x1e0f8 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL3_RdRsp_TimeSlot_REG1 2 0x1e0fc 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL3_WrRsp_BurstTarget_REG0 2 0x1e100 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL3_WrRsp_BurstTarget_REG1 2 0x1e104 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL3_WrRsp_TimeSlot_REG0 2 0x1e108 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL3_WrRsp_TimeSlot_REG1 2 0x1e10c 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL3_Req_BurstTarget_REG0 2 0x1e110 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL3_Req_BurstTarget_REG1 2 0x1e114 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL3_Req_TimeSlot_REG0 2 0x1e118 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL3_Req_TimeSlot_REG1 2 0x1e11c 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL3_ReqPoolCredit_Alloc_REG0 2 0x1e120 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL3_ReqPoolCredit_Alloc_REG1 2 0x1e124 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL3_DataPoolCredit_Alloc_REG0 2 0x1e128 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL3_DataPoolCredit_Alloc_REG1 2 0x1e12c 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL3_RdRspPoolCredit_Alloc_REG0 2 0x1e130 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL3_RdRspPoolCredit_Alloc_REG1 2 0x1e134 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL3_WrRspPoolCredit_Alloc_REG0 2 0x1e138 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL3_WrRspPoolCredit_Alloc_REG1 2 0x1e13c 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL4_RdRsp_BurstTarget_REG0 2 0x1e140 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL4_RdRsp_BurstTarget_REG1 2 0x1e144 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL4_RdRsp_TimeSlot_REG0 2 0x1e148 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL4_RdRsp_TimeSlot_REG1 2 0x1e14c 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL4_WrRsp_BurstTarget_REG0 2 0x1e150 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL4_WrRsp_BurstTarget_REG1 2 0x1e154 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL4_WrRsp_TimeSlot_REG0 2 0x1e158 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL4_WrRsp_TimeSlot_REG1 2 0x1e15c 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL4_Req_BurstTarget_REG0 2 0x1e160 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL4_Req_BurstTarget_REG1 2 0x1e164 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL4_Req_TimeSlot_REG0 2 0x1e168 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL4_Req_TimeSlot_REG1 2 0x1e16c 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL4_ReqPoolCredit_Alloc_REG0 2 0x1e170 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL4_ReqPoolCredit_Alloc_REG1 2 0x1e174 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL4_DataPoolCredit_Alloc_REG0 2 0x1e178 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL4_DataPoolCredit_Alloc_REG1 2 0x1e17c 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL4_RdRspPoolCredit_Alloc_REG0 2 0x1e180 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL4_RdRspPoolCredit_Alloc_REG1 2 0x1e184 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL4_WrRspPoolCredit_Alloc_REG0 2 0x1e188 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL4_WrRspPoolCredit_Alloc_REG1 2 0x1e18c 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL5_RdRsp_BurstTarget_REG0 2 0x1e190 2 0 4294967295 RdRsp_BurstTarget_31_0 0 0 RdRsp_BurstTarget_31_0_ 0 31 ixSION_CL5_RdRsp_BurstTarget_REG1 2 0x1e194 2 0 4294967295 RdRsp_BurstTarget_63_32 0 0 RdRsp_BurstTarget_63_32_ 0 31 ixSION_CL5_RdRsp_TimeSlot_REG0 2 0x1e198 2 0 4294967295 RdRsp_TimeSlot_31_0 0 0 RdRsp_TimeSlot_31_0_ 0 31 ixSION_CL5_RdRsp_TimeSlot_REG1 2 0x1e19c 2 0 4294967295 RdRsp_TimeSlot_63_32 0 0 RdRsp_TimeSlot_63_32_ 0 31 ixSION_CL5_WrRsp_BurstTarget_REG0 2 0x1e1a0 2 0 4294967295 WrRsp_BurstTarget_31_0 0 0 WrRsp_BurstTarget_31_0_ 0 31 ixSION_CL5_WrRsp_BurstTarget_REG1 2 0x1e1a4 2 0 4294967295 WrRsp_BurstTarget_63_32 0 0 WrRsp_BurstTarget_63_32_ 0 31 ixSION_CL5_WrRsp_TimeSlot_REG0 2 0x1e1a8 2 0 4294967295 WrRsp_TimeSlot_31_0 0 0 WrRsp_TimeSlot_31_0_ 0 31 ixSION_CL5_WrRsp_TimeSlot_REG1 2 0x1e1ac 2 0 4294967295 WrRsp_TimeSlot_63_32 0 0 WrRsp_TimeSlot_63_32_ 0 31 ixSION_CL5_Req_BurstTarget_REG0 2 0x1e1b0 2 0 4294967295 Req_BurstTarget_31_0 0 0 Req_BurstTarget_31_0_ 0 31 ixSION_CL5_Req_BurstTarget_REG1 2 0x1e1b4 2 0 4294967295 Req_BurstTarget_63_32 0 0 Req_BurstTarget_63_32_ 0 31 ixSION_CL5_Req_TimeSlot_REG0 2 0x1e1b8 2 0 4294967295 Req_TimeSlot_31_0 0 0 Req_TimeSlot_31_0_ 0 31 ixSION_CL5_Req_TimeSlot_REG1 2 0x1e1bc 2 0 4294967295 Req_TimeSlot_63_32 0 0 Req_TimeSlot_63_32_ 0 31 ixSION_CL5_ReqPoolCredit_Alloc_REG0 2 0x1e1c0 2 0 4294967295 ReqPoolCredit_Alloc_31_0 0 0 ReqPoolCredit_Alloc_31_0_ 0 31 ixSION_CL5_ReqPoolCredit_Alloc_REG1 2 0x1e1c4 2 0 4294967295 ReqPoolCredit_Alloc_63_32 0 0 ReqPoolCredit_Alloc_63_32_ 0 31 ixSION_CL5_DataPoolCredit_Alloc_REG0 2 0x1e1c8 2 0 4294967295 DataPoolCredit_Alloc_31_0 0 0 DataPoolCredit_Alloc_31_0_ 0 31 ixSION_CL5_DataPoolCredit_Alloc_REG1 2 0x1e1cc 2 0 4294967295 DataPoolCredit_Alloc_63_32 0 0 DataPoolCredit_Alloc_63_32_ 0 31 ixSION_CL5_RdRspPoolCredit_Alloc_REG0 2 0x1e1d0 2 0 4294967295 RdRspPoolCredit_Alloc_31_0 0 0 RdRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL5_RdRspPoolCredit_Alloc_REG1 2 0x1e1d4 2 0 4294967295 RdRspPoolCredit_Alloc_63_32 0 0 RdRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CL5_WrRspPoolCredit_Alloc_REG0 2 0x1e1d8 2 0 4294967295 WrRspPoolCredit_Alloc_31_0 0 0 WrRspPoolCredit_Alloc_31_0_ 0 31 ixSION_CL5_WrRspPoolCredit_Alloc_REG1 2 0x1e1dc 2 0 4294967295 WrRspPoolCredit_Alloc_63_32 0 0 WrRspPoolCredit_Alloc_63_32_ 0 31 ixSION_CNTL_REG0 2 0x1e1e0 40 0 4294967295 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_ 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_ 1 1 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_ 2 2 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_ 3 3 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_ 4 4 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_ 5 5 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_ 6 6 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_ 7 7 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_ 8 8 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_ 9 9 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_ 10 10 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_ 11 11 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_ 12 12 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_ 13 13 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_ 14 14 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_ 15 15 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_ 16 16 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_ 17 17 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_ 18 18 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_ 19 19 ixSION_CNTL_REG1 2 0x1e1e4 4 0 4294967295 LIVELOCK_WATCHDOG_THRESHOLD 0 0 CG_OFF_HYSTERESIS 0 0 LIVELOCK_WATCHDOG_THRESHOLD_ 0 7 CG_OFF_HYSTERESIS_ 8 15 ixSYSHUB_DS_CTRL_SOCCLK 2 0x10000 36 0 4294967295 HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SOCCLK_DS_EN 0 0 HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 0 0 HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 1 1 HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 2 2 HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 3 3 HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 4 4 HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 5 5 HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 6 6 HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 7 7 DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 16 16 DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 17 17 DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 18 18 DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 19 19 DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 20 20 DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 21 21 DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 22 22 DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 23 23 SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 28 28 SYSHUB_SOCCLK_DS_EN_ 31 31 ixSYSHUB_DS_CTRL2_SOCCLK 2 0x10004 2 0 4294967295 SYSHUB_SOCCLK_DS_TIMER 0 0 SYSHUB_SOCCLK_DS_TIMER_ 0 15 ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 2 0x10008 10 0 4294967295 SYSHUB_bgen_socclk_HST_SW0_bypass_en 0 0 SYSHUB_bgen_socclk_HST_SW1_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW0_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW1_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW2_bypass_en 0 0 SYSHUB_bgen_socclk_HST_SW0_bypass_en_ 0 0 SYSHUB_bgen_socclk_HST_SW1_bypass_en_ 1 1 SYSHUB_bgen_socclk_DMA_SW0_bypass_en_ 15 15 SYSHUB_bgen_socclk_DMA_SW1_bypass_en_ 16 16 SYSHUB_bgen_socclk_DMA_SW2_bypass_en_ 17 17 ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 2 0x1000c 10 0 4294967295 SYSHUB_bgen_socclk_HST_SW0_imm_en 0 0 SYSHUB_bgen_socclk_HST_SW1_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW0_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW1_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW2_imm_en 0 0 SYSHUB_bgen_socclk_HST_SW0_imm_en_ 0 0 SYSHUB_bgen_socclk_HST_SW1_imm_en_ 1 1 SYSHUB_bgen_socclk_DMA_SW0_imm_en_ 15 15 SYSHUB_bgen_socclk_DMA_SW1_imm_en_ 16 16 SYSHUB_bgen_socclk_DMA_SW2_imm_en_ 17 17 ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 2 0x10010 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 2 0x10014 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixDMA_CLK0_SW0_CL0_CNTL 2 0x10018 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW0_CL1_CNTL 2 0x1001c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW0_CL2_CNTL 2 0x10020 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW0_CL3_CNTL 2 0x10024 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW0_CL4_CNTL 2 0x10028 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW0_CL5_CNTL 2 0x1002c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW1_CL0_CNTL 2 0x10030 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK0_SW2_CL0_CNTL 2 0x10034 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUB_CG_CNTL 2 0x10300 6 0 4294967295 SYSHUB_CG_EN 0 0 SYSHUB_CG_IDLE_TIMER 0 0 SYSHUB_CG_WAKEUP_TIMER 0 0 SYSHUB_CG_EN_ 0 0 SYSHUB_CG_IDLE_TIMER_ 8 15 SYSHUB_CG_WAKEUP_TIMER_ 16 23 ixSYSHUB_TRANS_IDLE 2 0x10308 34 0 4294967295 SYSHUB_TRANS_IDLE_VF0 0 0 SYSHUB_TRANS_IDLE_VF1 0 0 SYSHUB_TRANS_IDLE_VF2 0 0 SYSHUB_TRANS_IDLE_VF3 0 0 SYSHUB_TRANS_IDLE_VF4 0 0 SYSHUB_TRANS_IDLE_VF5 0 0 SYSHUB_TRANS_IDLE_VF6 0 0 SYSHUB_TRANS_IDLE_VF7 0 0 SYSHUB_TRANS_IDLE_VF8 0 0 SYSHUB_TRANS_IDLE_VF9 0 0 SYSHUB_TRANS_IDLE_VF10 0 0 SYSHUB_TRANS_IDLE_VF11 0 0 SYSHUB_TRANS_IDLE_VF12 0 0 SYSHUB_TRANS_IDLE_VF13 0 0 SYSHUB_TRANS_IDLE_VF14 0 0 SYSHUB_TRANS_IDLE_VF15 0 0 SYSHUB_TRANS_IDLE_PF 0 0 SYSHUB_TRANS_IDLE_VF0_ 0 0 SYSHUB_TRANS_IDLE_VF1_ 1 1 SYSHUB_TRANS_IDLE_VF2_ 2 2 SYSHUB_TRANS_IDLE_VF3_ 3 3 SYSHUB_TRANS_IDLE_VF4_ 4 4 SYSHUB_TRANS_IDLE_VF5_ 5 5 SYSHUB_TRANS_IDLE_VF6_ 6 6 SYSHUB_TRANS_IDLE_VF7_ 7 7 SYSHUB_TRANS_IDLE_VF8_ 8 8 SYSHUB_TRANS_IDLE_VF9_ 9 9 SYSHUB_TRANS_IDLE_VF10_ 10 10 SYSHUB_TRANS_IDLE_VF11_ 11 11 SYSHUB_TRANS_IDLE_VF12_ 12 12 SYSHUB_TRANS_IDLE_VF13_ 13 13 SYSHUB_TRANS_IDLE_VF14_ 14 14 SYSHUB_TRANS_IDLE_VF15_ 15 15 SYSHUB_TRANS_IDLE_PF_ 16 16 ixSYSHUB_HP_TIMER 2 0x1030c 2 0 4294967295 SYSHUB_HP_TIMER 0 0 SYSHUB_HP_TIMER_ 0 31 ixSYSHUB_SCRATCH 2 0x10f00 2 0 4294967295 SCRATCH 0 0 SCRATCH_ 0 31 ixSYSHUB_DS_CTRL_SHUBCLK 2 0x11000 36 0 4294967295 HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SHUBCLK_DS_EN 0 0 HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 0 0 HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 1 1 HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 2 2 HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 3 3 HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 4 4 HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 5 5 HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 6 6 HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 7 7 DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 16 16 DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 17 17 DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 18 18 DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 19 19 DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 20 20 DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 21 21 DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 22 22 DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 23 23 SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 28 28 SYSHUB_SHUBCLK_DS_EN_ 31 31 ixSYSHUB_DS_CTRL2_SHUBCLK 2 0x11004 2 0 4294967295 SYSHUB_SHUBCLK_DS_TIMER 0 0 SYSHUB_SHUBCLK_DS_TIMER_ 0 15 ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 2 0x11008 4 0 4294967295 SYSHUB_bgen_shubclk_DMA_SW0_bypass_en 0 0 SYSHUB_bgen_shubclk_DMA_SW1_bypass_en 0 0 SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_ 15 15 SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_ 16 16 ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 2 0x1100c 4 0 4294967295 SYSHUB_bgen_shubclk_DMA_SW0_imm_en 0 0 SYSHUB_bgen_shubclk_DMA_SW1_imm_en 0 0 SYSHUB_bgen_shubclk_DMA_SW0_imm_en_ 15 15 SYSHUB_bgen_shubclk_DMA_SW1_imm_en_ 16 16 ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 2 0x11010 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 2 0x11014 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixDMA_CLK1_SW0_CL0_CNTL 2 0x11018 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW0_CL1_CNTL 2 0x1101c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW0_CL2_CNTL 2 0x11020 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW0_CL3_CNTL 2 0x11024 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW0_CL4_CNTL 2 0x11028 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW1_CL0_CNTL 2 0x1102c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW1_CL1_CNTL 2 0x11030 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW1_CL2_CNTL 2 0x11034 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW1_CL3_CNTL 2 0x11038 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixDMA_CLK1_SW1_CL4_CNTL 2 0x1103c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixGDC_RAS_LEAF0_CTRL 2 0x1f800 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixGDC_RAS_LEAF1_CTRL 2 0x1f804 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixGDC_RAS_LEAF2_CTRL 2 0x1f808 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixGDC_RAS_LEAF3_CTRL 2 0x1f80c 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixGDC_RAS_LEAF4_CTRL 2 0x1f810 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixGDC_RAS_LEAF5_CTRL 2 0x1f814 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixSHUB_PF_FLR_RST 2 0x1f000 16 0 4294967295 PF0_FLR_RST 0 0 PF1_FLR_RST 0 0 PF2_FLR_RST 0 0 PF3_FLR_RST 0 0 PF4_FLR_RST 0 0 PF5_FLR_RST 0 0 PF6_FLR_RST 0 0 PF7_FLR_RST 0 0 PF0_FLR_RST_ 0 0 PF1_FLR_RST_ 1 1 PF2_FLR_RST_ 2 2 PF3_FLR_RST_ 3 3 PF4_FLR_RST_ 4 4 PF5_FLR_RST_ 5 5 PF6_FLR_RST_ 6 6 PF7_FLR_RST_ 7 7 ixSHUB_GFX_DRV_MODE1_RST 2 0x1f004 2 0 4294967295 GFX_DRV_MODE1_RST 0 0 GFX_DRV_MODE1_RST_ 0 0 ixSHUB_LINK_RESET 2 0x1f008 2 0 4294967295 LINK_RESET 0 0 LINK_RESET_ 0 0 ixSHUB_PF0_VF_FLR_RST 2 0x1f020 34 0 4294967295 PF0_VF0_FLR_RST 0 0 PF0_VF1_FLR_RST 0 0 PF0_VF2_FLR_RST 0 0 PF0_VF3_FLR_RST 0 0 PF0_VF4_FLR_RST 0 0 PF0_VF5_FLR_RST 0 0 PF0_VF6_FLR_RST 0 0 PF0_VF7_FLR_RST 0 0 PF0_VF8_FLR_RST 0 0 PF0_VF9_FLR_RST 0 0 PF0_VF10_FLR_RST 0 0 PF0_VF11_FLR_RST 0 0 PF0_VF12_FLR_RST 0 0 PF0_VF13_FLR_RST 0 0 PF0_VF14_FLR_RST 0 0 PF0_VF15_FLR_RST 0 0 PF0_SOFTPF_FLR_RST 0 0 PF0_VF0_FLR_RST_ 0 0 PF0_VF1_FLR_RST_ 1 1 PF0_VF2_FLR_RST_ 2 2 PF0_VF3_FLR_RST_ 3 3 PF0_VF4_FLR_RST_ 4 4 PF0_VF5_FLR_RST_ 5 5 PF0_VF6_FLR_RST_ 6 6 PF0_VF7_FLR_RST_ 7 7 PF0_VF8_FLR_RST_ 8 8 PF0_VF9_FLR_RST_ 9 9 PF0_VF10_FLR_RST_ 10 10 PF0_VF11_FLR_RST_ 11 11 PF0_VF12_FLR_RST_ 12 12 PF0_VF13_FLR_RST_ 13 13 PF0_VF14_FLR_RST_ 14 14 PF0_VF15_FLR_RST_ 15 15 PF0_SOFTPF_FLR_RST_ 31 31 ixSHUB_HARD_RST_CTRL 2 0x1f040 10 0 4294967295 COR_RESET_EN 0 0 REG_RESET_EN 0 0 STY_RESET_EN 0 0 NIC400_RESET_EN 0 0 SDP_PORT_RESET_EN 0 0 COR_RESET_EN_ 0 0 REG_RESET_EN_ 1 1 STY_RESET_EN_ 2 2 NIC400_RESET_EN_ 3 3 SDP_PORT_RESET_EN_ 4 4 ixSHUB_SOFT_RST_CTRL 2 0x1f044 10 0 4294967295 COR_RESET_EN 0 0 REG_RESET_EN 0 0 STY_RESET_EN 0 0 NIC400_RESET_EN 0 0 SDP_PORT_RESET_EN 0 0 COR_RESET_EN_ 0 0 REG_RESET_EN_ 1 1 STY_RESET_EN_ 2 2 NIC400_RESET_EN_ 3 3 SDP_PORT_RESET_EN_ 4 4 ixSHUB_SDP_PORT_RST 2 0x1f048 2 0 4294967295 SDP_PORT_RST 0 0 SDP_PORT_RST_ 0 0 mmSBIOS_SCRATCH_0 0 0x48 2 0 0 SBIOS_SCRATCH_DW 0 0 SBIOS_SCRATCH_DW_ 0 31 mmSBIOS_SCRATCH_1 0 0x49 2 0 0 SBIOS_SCRATCH_DW 0 0 SBIOS_SCRATCH_DW_ 0 31 mmSBIOS_SCRATCH_2 0 0x4a 2 0 0 SBIOS_SCRATCH_DW 0 0 SBIOS_SCRATCH_DW_ 0 31 mmSBIOS_SCRATCH_3 0 0x4b 2 0 0 SBIOS_SCRATCH_DW 0 0 SBIOS_SCRATCH_DW_ 0 31 mmBIOS_SCRATCH_0 0 0x4c 2 0 0 BIOS_SCRATCH_0 0 0 BIOS_SCRATCH_0_ 0 31 mmBIOS_SCRATCH_1 0 0x4d 2 0 0 BIOS_SCRATCH_1 0 0 BIOS_SCRATCH_1_ 0 31 mmBIOS_SCRATCH_2 0 0x4e 2 0 0 BIOS_SCRATCH_2 0 0 BIOS_SCRATCH_2_ 0 31 mmBIOS_SCRATCH_3 0 0x4f 2 0 0 BIOS_SCRATCH_3 0 0 BIOS_SCRATCH_3_ 0 31 mmBIOS_SCRATCH_4 0 0x50 2 0 0 BIOS_SCRATCH_4 0 0 BIOS_SCRATCH_4_ 0 31 mmBIOS_SCRATCH_5 0 0x51 2 0 0 BIOS_SCRATCH_5 0 0 BIOS_SCRATCH_5_ 0 31 mmBIOS_SCRATCH_6 0 0x52 2 0 0 BIOS_SCRATCH_6 0 0 BIOS_SCRATCH_6_ 0 31 mmBIOS_SCRATCH_7 0 0x53 2 0 0 BIOS_SCRATCH_7 0 0 BIOS_SCRATCH_7_ 0 31 mmBIOS_SCRATCH_8 0 0x54 2 0 0 BIOS_SCRATCH_8 0 0 BIOS_SCRATCH_8_ 0 31 mmBIOS_SCRATCH_9 0 0x55 2 0 0 BIOS_SCRATCH_9 0 0 BIOS_SCRATCH_9_ 0 31 mmBIOS_SCRATCH_10 0 0x56 2 0 0 BIOS_SCRATCH_10 0 0 BIOS_SCRATCH_10_ 0 31 mmBIOS_SCRATCH_11 0 0x57 2 0 0 BIOS_SCRATCH_11 0 0 BIOS_SCRATCH_11_ 0 31 mmBIOS_SCRATCH_12 0 0x58 2 0 0 BIOS_SCRATCH_12 0 0 BIOS_SCRATCH_12_ 0 31 mmBIOS_SCRATCH_13 0 0x59 2 0 0 BIOS_SCRATCH_13 0 0 BIOS_SCRATCH_13_ 0 31 mmBIOS_SCRATCH_14 0 0x5a 2 0 0 BIOS_SCRATCH_14 0 0 BIOS_SCRATCH_14_ 0 31 mmBIOS_SCRATCH_15 0 0x5b 2 0 0 BIOS_SCRATCH_15 0 0 BIOS_SCRATCH_15_ 0 31 mmBIF_RLC_INTR_CNTL 0 0x60 8 0 0 RLC_CMD_COMPLETE 0 0 RLC_HANG_SELF_RECOVERED 0 0 RLC_HANG_NEED_FLR 0 0 RLC_VM_BUSY_TRANSITION 0 0 RLC_CMD_COMPLETE_ 0 0 RLC_HANG_SELF_RECOVERED_ 1 1 RLC_HANG_NEED_FLR_ 2 2 RLC_VM_BUSY_TRANSITION_ 3 3 mmBIF_VCE_INTR_CNTL 0 0x61 8 0 0 VCE_CMD_COMPLETE 0 0 VCE_HANG_SELF_RECOVERED 0 0 VCE_HANG_NEED_FLR 0 0 VCE_VM_BUSY_TRANSITION 0 0 VCE_CMD_COMPLETE_ 0 0 VCE_HANG_SELF_RECOVERED_ 1 1 VCE_HANG_NEED_FLR_ 2 2 VCE_VM_BUSY_TRANSITION_ 3 3 mmBIF_UVD_INTR_CNTL 0 0x62 8 0 0 UVD_CMD_COMPLETE 0 0 UVD_HANG_SELF_RECOVERED 0 0 UVD_HANG_NEED_FLR 0 0 UVD_VM_BUSY_TRANSITION 0 0 UVD_CMD_COMPLETE_ 0 0 UVD_HANG_SELF_RECOVERED_ 1 1 UVD_HANG_NEED_FLR_ 2 2 UVD_VM_BUSY_TRANSITION_ 3 3 mmGFX_MMIOREG_CAM_ADDR0 0 0x80 2 0 0 CAM_ADDR0 0 0 CAM_ADDR0_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR0 0 0x81 2 0 0 CAM_REMAP_ADDR0 0 0 CAM_REMAP_ADDR0_ 0 19 mmGFX_MMIOREG_CAM_ADDR1 0 0x82 2 0 0 CAM_ADDR1 0 0 CAM_ADDR1_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR1 0 0x83 2 0 0 CAM_REMAP_ADDR1 0 0 CAM_REMAP_ADDR1_ 0 19 mmGFX_MMIOREG_CAM_ADDR2 0 0x84 2 0 0 CAM_ADDR2 0 0 CAM_ADDR2_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR2 0 0x85 2 0 0 CAM_REMAP_ADDR2 0 0 CAM_REMAP_ADDR2_ 0 19 mmGFX_MMIOREG_CAM_ADDR3 0 0x86 2 0 0 CAM_ADDR3 0 0 CAM_ADDR3_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR3 0 0x87 2 0 0 CAM_REMAP_ADDR3 0 0 CAM_REMAP_ADDR3_ 0 19 mmGFX_MMIOREG_CAM_ADDR4 0 0x88 2 0 0 CAM_ADDR4 0 0 CAM_ADDR4_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR4 0 0x89 2 0 0 CAM_REMAP_ADDR4 0 0 CAM_REMAP_ADDR4_ 0 19 mmGFX_MMIOREG_CAM_ADDR5 0 0x8a 2 0 0 CAM_ADDR5 0 0 CAM_ADDR5_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR5 0 0x8b 2 0 0 CAM_REMAP_ADDR5 0 0 CAM_REMAP_ADDR5_ 0 19 mmGFX_MMIOREG_CAM_ADDR6 0 0x8c 2 0 0 CAM_ADDR6 0 0 CAM_ADDR6_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR6 0 0x8d 2 0 0 CAM_REMAP_ADDR6 0 0 CAM_REMAP_ADDR6_ 0 19 mmGFX_MMIOREG_CAM_ADDR7 0 0x8e 2 0 0 CAM_ADDR7 0 0 CAM_ADDR7_ 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR7 0 0x8f 2 0 0 CAM_REMAP_ADDR7 0 0 CAM_REMAP_ADDR7_ 0 19 mmGFX_MMIOREG_CAM_CNTL 0 0x90 2 0 0 CAM_ENABLE 0 0 CAM_ENABLE_ 0 7 mmGFX_MMIOREG_CAM_ZERO_CPL 0 0x91 2 0 0 CAM_ZERO_CPL 0 0 CAM_ZERO_CPL_ 0 31 mmGFX_MMIOREG_CAM_ONE_CPL 0 0x92 2 0 0 CAM_ONE_CPL 0 0 CAM_ONE_CPL_ 0 31 mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0 0x93 2 0 0 CAM_PROGRAMMABLE_CPL 0 0 CAM_PROGRAMMABLE_CPL_ 0 31 mmMM_INDEX 0 0x0 4 0 0 MM_OFFSET 0 0 MM_APER 0 0 MM_OFFSET_ 0 30 MM_APER_ 31 31 mmMM_DATA 0 0x1 2 0 0 MM_DATA 0 0 MM_DATA_ 0 31 mmMM_INDEX_HI 0 0x6 2 0 0 MM_OFFSET_HI 0 0 MM_OFFSET_HI_ 0 31 mmSYSHUB_INDEX_OVLP 0 0x8 2 0 0 SYSHUB_OFFSET 0 0 SYSHUB_OFFSET_ 0 21 mmSYSHUB_DATA_OVLP 0 0x9 2 0 0 SYSHUB_DATA 0 0 SYSHUB_DATA_ 0 31 mmPCIE_INDEX 0 0xc 2 0 0 PCIE_INDEX 0 0 PCIE_INDEX_ 0 31 mmPCIE_DATA 0 0xd 2 0 0 PCIE_DATA 0 0 PCIE_DATA_ 0 31 mmPCIE_INDEX2 0 0xe 2 0 0 PCIE_INDEX2 0 0 PCIE_INDEX2_ 0 31 mmPCIE_DATA2 0 0xf 2 0 0 PCIE_DATA2 0 0 PCIE_DATA2_ 0 31 mmDN_PCIE_RESERVED 0 0xd60 2 0 0 PCIE_RESERVED 0 0 PCIE_RESERVED_ 0 31 mmDN_PCIE_SCRATCH 0 0xd61 2 0 0 PCIE_SCRATCH 0 0 PCIE_SCRATCH_ 0 31 mmDN_PCIE_CNTL 0 0xd63 6 0 0 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 0 0 RX_IGNORE_LTR_MSG_UR 0 0 HWINIT_WR_LOCK_ 0 0 UR_ERR_REPORT_DIS_DN_ 7 7 RX_IGNORE_LTR_MSG_UR_ 30 30 mmDN_PCIE_CONFIG_CNTL 0 0xd64 2 0 0 CI_EXTENDED_TAG_EN_OVERRIDE 0 0 CI_EXTENDED_TAG_EN_OVERRIDE_ 25 26 mmDN_PCIE_RX_CNTL2 0 0xd65 2 0 0 FLR_EXTEND_MODE 0 0 FLR_EXTEND_MODE_ 28 30 mmDN_PCIE_BUS_CNTL 0 0xd66 4 0 0 IMMEDIATE_PMI_DIS 0 0 AER_CPL_TIMEOUT_RO_DIS_SWDN 0 0 IMMEDIATE_PMI_DIS_ 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN_ 8 8 mmDN_PCIE_CFG_CNTL 0 0xd67 6 0 0 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 0 0 CFG_EN_DEC_TO_HIDDEN_REG_ 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG_ 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG_ 2 2 mmDN_PCIE_STRAP_F0 0 0xd68 6 0 0 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 0 0 STRAP_F0_MSI_MULTI_CAP 0 0 STRAP_F0_EN_ 0 0 STRAP_F0_MC_EN_ 17 17 STRAP_F0_MSI_MULTI_CAP_ 21 23 mmDN_PCIE_STRAP_MISC 0 0xd69 4 0 0 STRAP_CLK_PM_EN 0 0 STRAP_MST_ADR64_EN 0 0 STRAP_CLK_PM_EN_ 24 24 STRAP_MST_ADR64_EN_ 29 29 mmDN_PCIE_STRAP_MISC2 0 0xd6a 2 0 0 STRAP_MSTCPL_TIMEOUT_EN 0 0 STRAP_MSTCPL_TIMEOUT_EN_ 2 2 mmPCIEP_RESERVED 0 0xd6c 2 0 0 PCIEP_RESERVED 0 0 PCIEP_RESERVED_ 0 31 mmPCIEP_SCRATCH 0 0xd6d 2 0 0 PCIEP_SCRATCH 0 0 PCIEP_SCRATCH_ 0 31 mmPCIE_ERR_CNTL 0 0xd6f 8 0 0 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 0 0 AER_HDR_LOG_F0_TIMER_EXPIRED 0 0 SEND_ERR_MSG_IMMEDIATELY 0 0 ERR_REPORTING_DIS_ 0 0 AER_HDR_LOG_TIMEOUT_ 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED_ 11 11 SEND_ERR_MSG_IMMEDIATELY_ 17 17 mmPCIE_RX_CNTL 0 0xd70 10 0 0 RX_IGNORE_MAX_PAYLOAD_ERR 0 0 RX_IGNORE_TC_ERR_DN 0 0 RX_PCIE_CPL_TIMEOUT_DIS 0 0 RX_IGNORE_SHORTPREFIX_ERR_DN 0 0 RX_RCB_FLR_TIMEOUT_DIS 0 0 RX_IGNORE_MAX_PAYLOAD_ERR_ 8 8 RX_IGNORE_TC_ERR_DN_ 9 9 RX_PCIE_CPL_TIMEOUT_DIS_ 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN_ 21 21 RX_RCB_FLR_TIMEOUT_DIS_ 27 27 mmPCIE_LC_SPEED_CNTL 0 0xd71 4 0 0 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 0 0 LC_GEN2_EN_STRAP_ 0 0 LC_GEN3_EN_STRAP_ 1 1 mmPCIE_LC_CNTL2 0 0xd72 2 0 0 LC_LINK_BW_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS_ 27 27 mmPCIEP_STRAP_MISC 0 0xd73 2 0 0 STRAP_MULTI_FUNC_EN 0 0 STRAP_MULTI_FUNC_EN_ 10 10 mmLTR_MSG_INFO_FROM_EP 0 0xd74 2 0 0 LTR_MSG_INFO_FROM_EP 0 0 LTR_MSG_INFO_FROM_EP_ 0 31 mmEP_PCIE_SCRATCH 0 0xd43 2 0 0 PCIE_SCRATCH 0 0 PCIE_SCRATCH_ 0 31 mmEP_PCIE_CNTL 0 0xd45 6 0 0 UR_ERR_REPORT_DIS 0 0 PCIE_MALFORM_ATOMIC_OPS 0 0 RX_IGNORE_LTR_MSG_UR 0 0 UR_ERR_REPORT_DIS_ 7 7 PCIE_MALFORM_ATOMIC_OPS_ 8 8 RX_IGNORE_LTR_MSG_UR_ 30 30 mmEP_PCIE_INT_CNTL 0 0xd46 12 0 0 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 0 0 FATAL_ERR_INT_EN 0 0 USR_DETECTED_INT_EN 0 0 MISC_ERR_INT_EN 0 0 POWER_STATE_CHG_INT_EN 0 0 CORR_ERR_INT_EN_ 0 0 NON_FATAL_ERR_INT_EN_ 1 1 FATAL_ERR_INT_EN_ 2 2 USR_DETECTED_INT_EN_ 3 3 MISC_ERR_INT_EN_ 4 4 POWER_STATE_CHG_INT_EN_ 6 6 mmEP_PCIE_INT_STATUS 0 0xd47 12 0 0 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 0 0 FATAL_ERR_INT_STATUS 0 0 USR_DETECTED_INT_STATUS 0 0 MISC_ERR_INT_STATUS 0 0 POWER_STATE_CHG_INT_STATUS 0 0 CORR_ERR_INT_STATUS_ 0 0 NON_FATAL_ERR_INT_STATUS_ 1 1 FATAL_ERR_INT_STATUS_ 2 2 USR_DETECTED_INT_STATUS_ 3 3 MISC_ERR_INT_STATUS_ 4 4 POWER_STATE_CHG_INT_STATUS_ 6 6 mmEP_PCIE_RX_CNTL2 0 0xd48 2 0 0 RX_IGNORE_EP_INVALIDPASID_UR 0 0 RX_IGNORE_EP_INVALIDPASID_UR_ 0 0 mmEP_PCIE_BUS_CNTL 0 0xd49 2 0 0 IMMEDIATE_PMI_DIS 0 0 IMMEDIATE_PMI_DIS_ 7 7 mmEP_PCIE_CFG_CNTL 0 0xd4a 6 0 0 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 0 0 CFG_EN_DEC_TO_HIDDEN_REG_ 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG_ 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG_ 2 2 mmEP_PCIE_OBFF_CNTL 0 0xd4b 24 0 0 TX_OBFF_PRIV_DISABLE 0 0 TX_OBFF_WAKE_SIMPLE_MODE_EN 0 0 TX_OBFF_HOSTMEM_TO_ACTIVE 0 0 TX_OBFF_SLVCPL_TO_ACTIVE 0 0 TX_OBFF_WAKE_MAX_PULSE_WIDTH 0 0 TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH 0 0 TX_OBFF_WAKE_SAMPLING_PERIOD 0 0 TX_OBFF_INTR_TO_ACTIVE 0 0 TX_OBFF_ERR_TO_ACTIVE 0 0 TX_OBFF_ANY_MSG_TO_ACTIVE 0 0 TX_OBFF_ACCEPT_IN_NOND0 0 0 TX_OBFF_PENDING_REQ_TO_ACTIVE 0 0 TX_OBFF_PRIV_DISABLE_ 0 0 TX_OBFF_WAKE_SIMPLE_MODE_EN_ 1 1 TX_OBFF_HOSTMEM_TO_ACTIVE_ 2 2 TX_OBFF_SLVCPL_TO_ACTIVE_ 3 3 TX_OBFF_WAKE_MAX_PULSE_WIDTH_ 4 7 TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH_ 8 11 TX_OBFF_WAKE_SAMPLING_PERIOD_ 12 15 TX_OBFF_INTR_TO_ACTIVE_ 16 16 TX_OBFF_ERR_TO_ACTIVE_ 17 17 TX_OBFF_ANY_MSG_TO_ACTIVE_ 18 18 TX_OBFF_ACCEPT_IN_NOND0_ 19 19 TX_OBFF_PENDING_REQ_TO_ACTIVE_ 20 23 mmEP_PCIE_TX_LTR_CNTL 0 0xd4c 18 0 0 LTR_PRIV_S_SHORT_VALUE 0 0 LTR_PRIV_S_LONG_VALUE 0 0 LTR_PRIV_S_REQUIREMENT 0 0 LTR_PRIV_NS_SHORT_VALUE 0 0 LTR_PRIV_NS_LONG_VALUE 0 0 LTR_PRIV_NS_REQUIREMENT 0 0 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 0 0 LTR_PRIV_RST_LTR_IN_DL_DOWN 0 0 TX_CHK_FC_FOR_L1 0 0 LTR_PRIV_S_SHORT_VALUE_ 0 2 LTR_PRIV_S_LONG_VALUE_ 3 5 LTR_PRIV_S_REQUIREMENT_ 6 6 LTR_PRIV_NS_SHORT_VALUE_ 7 9 LTR_PRIV_NS_LONG_VALUE_ 10 12 LTR_PRIV_NS_REQUIREMENT_ 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0_ 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN_ 15 15 TX_CHK_FC_FOR_L1_ 16 16 mmEP_PCIE_STRAP_MISC 0 0xd4f 2 0 0 STRAP_MST_ADR64_EN 0 0 STRAP_MST_ADR64_EN_ 29 29 mmEP_PCIE_STRAP_MISC2 0 0xd50 2 0 0 STRAP_TPH_SUPPORTED 0 0 STRAP_TPH_SUPPORTED_ 4 4 mmEP_PCIE_STRAP_PI 0 0xd51 0 0 0 mmEP_PCIE_F0_DPA_CAP 0 0xd52 8 0 0 TRANS_LAT_UNIT 0 0 PWR_ALLOC_SCALE 0 0 TRANS_LAT_VAL_0 0 0 TRANS_LAT_VAL_1 0 0 TRANS_LAT_UNIT_ 8 9 PWR_ALLOC_SCALE_ 12 13 TRANS_LAT_VAL_0_ 16 23 TRANS_LAT_VAL_1_ 24 31 mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0xd53 2 0 0 TRANS_LAT_INDICATOR_BITS 0 0 TRANS_LAT_INDICATOR_BITS_ 0 7 mmEP_PCIE_F0_DPA_CNTL 0 0xd53 4 0 0 SUBSTATE_STATUS 0 0 DPA_COMPLIANCE_MODE 0 0 SUBSTATE_STATUS_ 0 4 DPA_COMPLIANCE_MODE_ 8 8 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0xd53 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0xd54 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0xd54 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0xd54 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0xd54 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0xd55 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0xd55 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0xd55 2 0 0 SUBSTATE_PWR_ALLOC 0 0 SUBSTATE_PWR_ALLOC_ 0 7 mmEP_PCIE_PME_CONTROL 0 0xd55 2 0 0 PME_SERVICE_TIMER 0 0 PME_SERVICE_TIMER_ 0 4 mmEP_PCIEP_RESERVED 0 0xd56 2 0 0 PCIEP_RESERVED 0 0 PCIEP_RESERVED_ 0 31 mmEP_PCIE_TX_CNTL 0 0xd58 10 0 0 TX_SNR_OVERRIDE 0 0 TX_RO_OVERRIDE 0 0 TX_F0_TPH_DIS 0 0 TX_F1_TPH_DIS 0 0 TX_F2_TPH_DIS 0 0 TX_SNR_OVERRIDE_ 10 11 TX_RO_OVERRIDE_ 12 13 TX_F0_TPH_DIS_ 24 24 TX_F1_TPH_DIS_ 25 25 TX_F2_TPH_DIS_ 26 26 mmEP_PCIE_TX_REQUESTER_ID 0 0xd59 6 0 0 TX_REQUESTER_ID_FUNCTION 0 0 TX_REQUESTER_ID_DEVICE 0 0 TX_REQUESTER_ID_BUS 0 0 TX_REQUESTER_ID_FUNCTION_ 0 2 TX_REQUESTER_ID_DEVICE_ 3 7 TX_REQUESTER_ID_BUS_ 8 15 mmEP_PCIE_ERR_CNTL 0 0xd5a 24 0 0 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 0 0 SEND_ERR_MSG_IMMEDIATELY 0 0 STRAP_POISONED_ADVISORY_NONFATAL 0 0 AER_HDR_LOG_F0_TIMER_EXPIRED 0 0 AER_HDR_LOG_F1_TIMER_EXPIRED 0 0 AER_HDR_LOG_F2_TIMER_EXPIRED 0 0 AER_HDR_LOG_F3_TIMER_EXPIRED 0 0 AER_HDR_LOG_F4_TIMER_EXPIRED 0 0 AER_HDR_LOG_F5_TIMER_EXPIRED 0 0 AER_HDR_LOG_F6_TIMER_EXPIRED 0 0 AER_HDR_LOG_F7_TIMER_EXPIRED 0 0 ERR_REPORTING_DIS_ 0 0 AER_HDR_LOG_TIMEOUT_ 8 10 SEND_ERR_MSG_IMMEDIATELY_ 17 17 STRAP_POISONED_ADVISORY_NONFATAL_ 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED_ 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED_ 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED_ 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED_ 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED_ 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED_ 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED_ 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED_ 31 31 mmEP_PCIE_RX_CNTL 0 0xd5b 16 0 0 RX_IGNORE_MAX_PAYLOAD_ERR 0 0 RX_IGNORE_TC_ERR 0 0 RX_PCIE_CPL_TIMEOUT_DIS 0 0 RX_IGNORE_SHORTPREFIX_ERR 0 0 RX_IGNORE_MAXPREFIX_ERR 0 0 RX_IGNORE_INVALIDPASID_ERR 0 0 RX_IGNORE_NOT_PASID_UR 0 0 RX_TPH_DIS 0 0 RX_IGNORE_MAX_PAYLOAD_ERR_ 8 8 RX_IGNORE_TC_ERR_ 9 9 RX_PCIE_CPL_TIMEOUT_DIS_ 20 20 RX_IGNORE_SHORTPREFIX_ERR_ 21 21 RX_IGNORE_MAXPREFIX_ERR_ 22 22 RX_IGNORE_INVALIDPASID_ERR_ 24 24 RX_IGNORE_NOT_PASID_UR_ 25 25 RX_TPH_DIS_ 26 26 mmEP_PCIE_LC_SPEED_CNTL 0 0xd5c 4 0 0 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 0 0 LC_GEN2_EN_STRAP_ 0 0 LC_GEN3_EN_STRAP_ 1 1 mmBIF_MM_INDACCESS_CNTL 0 0xe06 2 0 0 MM_INDACCESS_DIS 0 0 MM_INDACCESS_DIS_ 1 1 mmBUS_CNTL 0 0xe07 32 0 0 PMI_INT_DIS_EP 0 0 PMI_INT_DIS_DN 0 0 PMI_INT_DIS_SWUS 0 0 VGA_REG_COHERENCY_DIS 0 0 VGA_MEM_COHERENCY_DIS 0 0 SET_AZ_TC 0 0 SET_MC_TC 0 0 ZERO_BE_WR_EN 0 0 ZERO_BE_RD_EN 0 0 RD_STALL_IO_WR 0 0 DEASRT_INTX_DSTATE_CHK_DIS_EP 0 0 DEASRT_INTX_DSTATE_CHK_DIS_DN 0 0 DEASRT_INTX_DSTATE_CHK_DIS_SWUS 0 0 DEASRT_INTX_IN_NOND0_EN_EP 0 0 DEASRT_INTX_IN_NOND0_EN_DN 0 0 UR_OVRD_FOR_ECRC_EN 0 0 PMI_INT_DIS_EP_ 3 3 PMI_INT_DIS_DN_ 4 4 PMI_INT_DIS_SWUS_ 5 5 VGA_REG_COHERENCY_DIS_ 6 6 VGA_MEM_COHERENCY_DIS_ 7 7 SET_AZ_TC_ 10 12 SET_MC_TC_ 13 15 ZERO_BE_WR_EN_ 16 16 ZERO_BE_RD_EN_ 17 17 RD_STALL_IO_WR_ 18 18 DEASRT_INTX_DSTATE_CHK_DIS_EP_ 19 19 DEASRT_INTX_DSTATE_CHK_DIS_DN_ 20 20 DEASRT_INTX_DSTATE_CHK_DIS_SWUS_ 21 21 DEASRT_INTX_IN_NOND0_EN_EP_ 22 22 DEASRT_INTX_IN_NOND0_EN_DN_ 23 23 UR_OVRD_FOR_ECRC_EN_ 24 24 mmBIF_SCRATCH0 0 0xe08 2 0 0 BIF_SCRATCH0 0 0 BIF_SCRATCH0_ 0 31 mmBIF_SCRATCH1 0 0xe09 2 0 0 BIF_SCRATCH1 0 0 BIF_SCRATCH1_ 0 31 mmBX_RESET_EN 0 0xe0d 10 0 0 COR_RESET_EN 0 0 REG_RESET_EN 0 0 STY_RESET_EN 0 0 FLR_TWICE_EN 0 0 RESET_ON_VFENABLE_LOW_EN 0 0 COR_RESET_EN_ 0 0 REG_RESET_EN_ 1 1 STY_RESET_EN_ 2 2 FLR_TWICE_EN_ 8 8 RESET_ON_VFENABLE_LOW_EN_ 16 16 mmMM_CFGREGS_CNTL 0 0xe0e 6 0 0 MM_CFG_FUNC_SEL 0 0 MM_CFG_DEV_SEL 0 0 MM_WR_TO_CFG_EN 0 0 MM_CFG_FUNC_SEL_ 0 2 MM_CFG_DEV_SEL_ 6 7 MM_WR_TO_CFG_EN_ 31 31 mmBX_RESET_CNTL 0 0xe10 2 0 0 LINK_TRAIN_EN 0 0 LINK_TRAIN_EN_ 0 0 mmINTERRUPT_CNTL 0 0xe11 12 0 0 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 0 0 IH_REQ_NONSNOOP_EN 0 0 IH_INTR_DLY_CNTR 0 0 GEN_IH_INT_EN 0 0 BIF_RB_REQ_NONSNOOP_EN 0 0 IH_DUMMY_RD_OVERRIDE_ 0 0 IH_DUMMY_RD_EN_ 1 1 IH_REQ_NONSNOOP_EN_ 3 3 IH_INTR_DLY_CNTR_ 4 7 GEN_IH_INT_EN_ 8 8 BIF_RB_REQ_NONSNOOP_EN_ 15 15 mmINTERRUPT_CNTL2 0 0xe12 2 0 0 IH_DUMMY_RD_ADDR 0 0 IH_DUMMY_RD_ADDR_ 0 31 mmCLKREQB_PAD_CNTL 0 0xe18 28 0 0 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 0 0 CLKREQB_PAD_MODE 0 0 CLKREQB_PAD_SPARE 0 0 CLKREQB_PAD_SN0 0 0 CLKREQB_PAD_SN1 0 0 CLKREQB_PAD_SN2 0 0 CLKREQB_PAD_SN3 0 0 CLKREQB_PAD_SLEWN 0 0 CLKREQB_PAD_WAKE 0 0 CLKREQB_PAD_SCHMEN 0 0 CLKREQB_PAD_CNTL_EN 0 0 CLKREQB_PAD_Y 0 0 CLKREQB_PERF_COUNTER_UPPER 0 0 CLKREQB_PAD_A_ 0 0 CLKREQB_PAD_SEL_ 1 1 CLKREQB_PAD_MODE_ 2 2 CLKREQB_PAD_SPARE_ 3 4 CLKREQB_PAD_SN0_ 5 5 CLKREQB_PAD_SN1_ 6 6 CLKREQB_PAD_SN2_ 7 7 CLKREQB_PAD_SN3_ 8 8 CLKREQB_PAD_SLEWN_ 9 9 CLKREQB_PAD_WAKE_ 10 10 CLKREQB_PAD_SCHMEN_ 11 11 CLKREQB_PAD_CNTL_EN_ 12 12 CLKREQB_PAD_Y_ 13 13 CLKREQB_PERF_COUNTER_UPPER_ 24 31 mmCLKREQB_PERF_COUNTER 0 0xe19 2 0 0 CLKREQB_PERF_COUNTER_LOWER 0 0 CLKREQB_PERF_COUNTER_LOWER_ 0 31 mmBIF_CLK_CTRL 0 0xe1a 4 0 0 BIF_XSTCLK_READY 0 0 BACO_XSTCLK_SWITCH_BYPASS 0 0 BIF_XSTCLK_READY_ 0 0 BACO_XSTCLK_SWITCH_BYPASS_ 1 1 mmBIF_FEATURES_CONTROL_MISC 0 0xe1b 26 0 0 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 0 0 BIF_SLV_REQ_EP_DIS 0 0 BIF_MST_CPL_EP_DIS 0 0 MC_BIF_REQ_ID_ROUTING_DIS 0 0 AZ_BIF_REQ_ID_ROUTING_DIS 0 0 ATC_PRG_RESP_PASID_UR_EN 0 0 BIF_RB_SET_OVERFLOW_EN 0 0 ATOMIC_ERR_INT_DIS 0 0 BME_HDL_NONVIR_EN 0 0 FLR_MST_PEND_CHK_DIS 0 0 FLR_SLV_PEND_CHK_DIS 0 0 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR 0 0 MST_BIF_REQ_EP_DIS_ 0 0 SLV_BIF_CPL_EP_DIS_ 1 1 BIF_SLV_REQ_EP_DIS_ 2 2 BIF_MST_CPL_EP_DIS_ 3 3 MC_BIF_REQ_ID_ROUTING_DIS_ 9 9 AZ_BIF_REQ_ID_ROUTING_DIS_ 10 10 ATC_PRG_RESP_PASID_UR_EN_ 11 11 BIF_RB_SET_OVERFLOW_EN_ 12 12 ATOMIC_ERR_INT_DIS_ 13 13 BME_HDL_NONVIR_EN_ 15 15 FLR_MST_PEND_CHK_DIS_ 17 17 FLR_SLV_PEND_CHK_DIS_ 18 18 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_ 24 24 mmBIF_DOORBELL_CNTL 0 0xe1c 18 0 0 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 0 0 UNTRANS_LBACK_EN 0 0 NON_CONSECUTIVE_BE_ZERO_DIS 0 0 DOORBELL_MONITOR_EN 0 0 DB_MNTR_INTGEN_DIS 0 0 DB_MNTR_INTGEN_MODE_0 0 0 DB_MNTR_INTGEN_MODE_1 0 0 DB_MNTR_INTGEN_MODE_2 0 0 SELF_RING_DIS_ 0 0 TRANS_CHECK_DIS_ 1 1 UNTRANS_LBACK_EN_ 2 2 NON_CONSECUTIVE_BE_ZERO_DIS_ 3 3 DOORBELL_MONITOR_EN_ 4 4 DB_MNTR_INTGEN_DIS_ 24 24 DB_MNTR_INTGEN_MODE_0_ 25 25 DB_MNTR_INTGEN_MODE_1_ 26 26 DB_MNTR_INTGEN_MODE_2_ 27 27 mmBIF_DOORBELL_INT_CNTL 0 0xe1d 8 0 0 DOORBELL_INTERRUPT_STATUS 0 0 IOHC_RAS_INTERRUPT_STATUS 0 0 DOORBELL_INTERRUPT_CLEAR 0 0 IOHC_RAS_INTERRUPT_CLEAR 0 0 DOORBELL_INTERRUPT_STATUS_ 0 0 IOHC_RAS_INTERRUPT_STATUS_ 1 1 DOORBELL_INTERRUPT_CLEAR_ 16 16 IOHC_RAS_INTERRUPT_CLEAR_ 17 17 mmBIF_SLVARB_MODE 0 0xe1e 2 0 0 SLVARB_MODE 0 0 SLVARB_MODE_ 0 1 mmBIF_FB_EN 0 0xe1f 4 0 0 FB_READ_EN 0 0 FB_WRITE_EN 0 0 FB_READ_EN_ 0 0 FB_WRITE_EN_ 1 1 mmBIF_BUSY_DELAY_CNTR 0 0xe20 2 0 0 DELAY_CNT 0 0 DELAY_CNT_ 0 5 mmBIF_PERFMON_CNTL 0 0xe21 10 0 0 PERFCOUNTER_EN 0 0 PERFCOUNTER_RESET0 0 0 PERFCOUNTER_RESET1 0 0 PERF_SEL0 0 0 PERF_SEL1 0 0 PERFCOUNTER_EN_ 0 0 PERFCOUNTER_RESET0_ 1 1 PERFCOUNTER_RESET1_ 2 2 PERF_SEL0_ 8 12 PERF_SEL1_ 13 17 mmBIF_PERFCOUNTER0_RESULT 0 0xe22 2 0 0 PERFCOUNTER_RESULT 0 0 PERFCOUNTER_RESULT_ 0 31 mmBIF_PERFCOUNTER1_RESULT 0 0xe23 2 0 0 PERFCOUNTER_RESULT 0 0 PERFCOUNTER_RESULT_ 0 31 mmBIF_MST_TRANS_PENDING_VF 0 0xe29 2 0 0 BIF_MST_TRANS_PENDING 0 0 BIF_MST_TRANS_PENDING_ 0 15 mmBIF_SLV_TRANS_PENDING_VF 0 0xe2a 2 0 0 BIF_SLV_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING_ 0 15 mmBACO_CNTL 0 0xe2b 18 0 0 BACO_EN 0 0 BACO_BIF_LCLK_SWITCH 0 0 BACO_DUMMY_EN 0 0 BACO_POWER_OFF 0 0 BACO_DSTATE_BYPASS 0 0 BACO_RST_INTR_MASK 0 0 BACO_MODE 0 0 RCU_BIF_CONFIG_DONE 0 0 BACO_AUTO_EXIT 0 0 BACO_EN_ 0 0 BACO_BIF_LCLK_SWITCH_ 1 1 BACO_DUMMY_EN_ 2 2 BACO_POWER_OFF_ 3 3 BACO_DSTATE_BYPASS_ 5 5 BACO_RST_INTR_MASK_ 6 6 BACO_MODE_ 8 8 RCU_BIF_CONFIG_DONE_ 9 9 BACO_AUTO_EXIT_ 31 31 mmBIF_BACO_EXIT_TIME0 0 0xe2c 2 0 0 BACO_EXIT_PXEN_CLR_TIMER 0 0 BACO_EXIT_PXEN_CLR_TIMER_ 0 19 mmBIF_BACO_EXIT_TIMER1 0 0xe2d 12 0 0 BACO_EXIT_SIDEBAND_TIMER 0 0 BACO_HW_EXIT_DIS 0 0 PX_EN_OE_IN_PX_EN_HIGH 0 0 PX_EN_OE_IN_PX_EN_LOW 0 0 BACO_MODE_SEL 0 0 AUTO_BACO_EXIT_CLR_BY_HW_DIS 0 0 BACO_EXIT_SIDEBAND_TIMER_ 0 19 BACO_HW_EXIT_DIS_ 26 26 PX_EN_OE_IN_PX_EN_HIGH_ 27 27 PX_EN_OE_IN_PX_EN_LOW_ 28 28 BACO_MODE_SEL_ 29 30 AUTO_BACO_EXIT_CLR_BY_HW_DIS_ 31 31 mmBIF_BACO_EXIT_TIMER2 0 0xe2e 2 0 0 BACO_EXIT_LCLK_BAK_TIMER 0 0 BACO_EXIT_LCLK_BAK_TIMER_ 0 19 mmBIF_BACO_EXIT_TIMER3 0 0xe2f 2 0 0 BACO_EXIT_DUMMY_EN_CLR_TIMER 0 0 BACO_EXIT_DUMMY_EN_CLR_TIMER_ 0 19 mmBIF_BACO_EXIT_TIMER4 0 0xe30 2 0 0 BACO_EXIT_BACO_EN_CLR_TIMER 0 0 BACO_EXIT_BACO_EN_CLR_TIMER_ 0 19 mmMEM_TYPE_CNTL 0 0xe31 2 0 0 BF_MEM_PHY_G5_G3 0 0 BF_MEM_PHY_G5_G3_ 0 0 mmSMU_BIF_VDDGFX_PWR_STATUS 0 0xe33 2 0 0 VDDGFX_GFX_PWR_OFF 0 0 VDDGFX_GFX_PWR_OFF_ 0 0 mmBIF_VDDGFX_GFX0_LOWER 0 0xe34 6 0 0 VDDGFX_GFX0_REG_LOWER 0 0 VDDGFX_GFX0_REG_CMP_EN 0 0 VDDGFX_GFX0_REG_STALL_EN 0 0 VDDGFX_GFX0_REG_LOWER_ 2 17 VDDGFX_GFX0_REG_CMP_EN_ 30 30 VDDGFX_GFX0_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX0_UPPER 0 0xe35 2 0 0 VDDGFX_GFX0_REG_UPPER 0 0 VDDGFX_GFX0_REG_UPPER_ 2 17 mmBIF_VDDGFX_GFX1_LOWER 0 0xe36 6 0 0 VDDGFX_GFX1_REG_LOWER 0 0 VDDGFX_GFX1_REG_CMP_EN 0 0 VDDGFX_GFX1_REG_STALL_EN 0 0 VDDGFX_GFX1_REG_LOWER_ 2 17 VDDGFX_GFX1_REG_CMP_EN_ 30 30 VDDGFX_GFX1_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX1_UPPER 0 0xe37 2 0 0 VDDGFX_GFX1_REG_UPPER 0 0 VDDGFX_GFX1_REG_UPPER_ 2 17 mmBIF_VDDGFX_GFX2_LOWER 0 0xe38 6 0 0 VDDGFX_GFX2_REG_LOWER 0 0 VDDGFX_GFX2_REG_CMP_EN 0 0 VDDGFX_GFX2_REG_STALL_EN 0 0 VDDGFX_GFX2_REG_LOWER_ 2 17 VDDGFX_GFX2_REG_CMP_EN_ 30 30 VDDGFX_GFX2_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX2_UPPER 0 0xe39 2 0 0 VDDGFX_GFX2_REG_UPPER 0 0 VDDGFX_GFX2_REG_UPPER_ 2 17 mmBIF_VDDGFX_GFX3_LOWER 0 0xe3a 6 0 0 VDDGFX_GFX3_REG_LOWER 0 0 VDDGFX_GFX3_REG_CMP_EN 0 0 VDDGFX_GFX3_REG_STALL_EN 0 0 VDDGFX_GFX3_REG_LOWER_ 2 17 VDDGFX_GFX3_REG_CMP_EN_ 30 30 VDDGFX_GFX3_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX3_UPPER 0 0xe3b 2 0 0 VDDGFX_GFX3_REG_UPPER 0 0 VDDGFX_GFX3_REG_UPPER_ 2 17 mmBIF_VDDGFX_GFX4_LOWER 0 0xe3c 6 0 0 VDDGFX_GFX4_REG_LOWER 0 0 VDDGFX_GFX4_REG_CMP_EN 0 0 VDDGFX_GFX4_REG_STALL_EN 0 0 VDDGFX_GFX4_REG_LOWER_ 2 17 VDDGFX_GFX4_REG_CMP_EN_ 30 30 VDDGFX_GFX4_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX4_UPPER 0 0xe3d 2 0 0 VDDGFX_GFX4_REG_UPPER 0 0 VDDGFX_GFX4_REG_UPPER_ 2 17 mmBIF_VDDGFX_GFX5_LOWER 0 0xe3e 6 0 0 VDDGFX_GFX5_REG_LOWER 0 0 VDDGFX_GFX5_REG_CMP_EN 0 0 VDDGFX_GFX5_REG_STALL_EN 0 0 VDDGFX_GFX5_REG_LOWER_ 2 17 VDDGFX_GFX5_REG_CMP_EN_ 30 30 VDDGFX_GFX5_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_GFX5_UPPER 0 0xe3f 2 0 0 VDDGFX_GFX5_REG_UPPER 0 0 VDDGFX_GFX5_REG_UPPER_ 2 17 mmBIF_VDDGFX_RSV1_LOWER 0 0xe40 6 0 0 VDDGFX_RSV1_REG_LOWER 0 0 VDDGFX_RSV1_REG_CMP_EN 0 0 VDDGFX_RSV1_REG_STALL_EN 0 0 VDDGFX_RSV1_REG_LOWER_ 2 17 VDDGFX_RSV1_REG_CMP_EN_ 30 30 VDDGFX_RSV1_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_RSV1_UPPER 0 0xe41 2 0 0 VDDGFX_RSV1_REG_UPPER 0 0 VDDGFX_RSV1_REG_UPPER_ 2 17 mmBIF_VDDGFX_RSV2_LOWER 0 0xe42 6 0 0 VDDGFX_RSV2_REG_LOWER 0 0 VDDGFX_RSV2_REG_CMP_EN 0 0 VDDGFX_RSV2_REG_STALL_EN 0 0 VDDGFX_RSV2_REG_LOWER_ 2 17 VDDGFX_RSV2_REG_CMP_EN_ 30 30 VDDGFX_RSV2_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_RSV2_UPPER 0 0xe43 2 0 0 VDDGFX_RSV2_REG_UPPER 0 0 VDDGFX_RSV2_REG_UPPER_ 2 17 mmBIF_VDDGFX_RSV3_LOWER 0 0xe44 6 0 0 VDDGFX_RSV3_REG_LOWER 0 0 VDDGFX_RSV3_REG_CMP_EN 0 0 VDDGFX_RSV3_REG_STALL_EN 0 0 VDDGFX_RSV3_REG_LOWER_ 2 17 VDDGFX_RSV3_REG_CMP_EN_ 30 30 VDDGFX_RSV3_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_RSV3_UPPER 0 0xe45 2 0 0 VDDGFX_RSV3_REG_UPPER 0 0 VDDGFX_RSV3_REG_UPPER_ 2 17 mmBIF_VDDGFX_RSV4_LOWER 0 0xe46 6 0 0 VDDGFX_RSV4_REG_LOWER 0 0 VDDGFX_RSV4_REG_CMP_EN 0 0 VDDGFX_RSV4_REG_STALL_EN 0 0 VDDGFX_RSV4_REG_LOWER_ 2 17 VDDGFX_RSV4_REG_CMP_EN_ 30 30 VDDGFX_RSV4_REG_STALL_EN_ 31 31 mmBIF_VDDGFX_RSV4_UPPER 0 0xe47 2 0 0 VDDGFX_RSV4_REG_UPPER 0 0 VDDGFX_RSV4_REG_UPPER_ 2 17 mmBIF_VDDGFX_FB_CMP 0 0xe48 12 0 0 VDDGFX_FB_HDP_CMP_EN 0 0 VDDGFX_FB_HDP_STALL_EN 0 0 VDDGFX_FB_XDMA_CMP_EN 0 0 VDDGFX_FB_XDMA_STALL_EN 0 0 VDDGFX_FB_VGA_CMP_EN 0 0 VDDGFX_FB_VGA_STALL_EN 0 0 VDDGFX_FB_HDP_CMP_EN_ 0 0 VDDGFX_FB_HDP_STALL_EN_ 1 1 VDDGFX_FB_XDMA_CMP_EN_ 2 2 VDDGFX_FB_XDMA_STALL_EN_ 3 3 VDDGFX_FB_VGA_CMP_EN_ 4 4 VDDGFX_FB_VGA_STALL_EN_ 5 5 mmBIF_DOORBELL_GBLAPER1_LOWER 0 0xe49 4 0 0 DOORBELL_GBLAPER1_LOWER 0 0 DOORBELL_GBLAPER1_EN 0 0 DOORBELL_GBLAPER1_LOWER_ 2 11 DOORBELL_GBLAPER1_EN_ 31 31 mmBIF_DOORBELL_GBLAPER1_UPPER 0 0xe4a 2 0 0 DOORBELL_GBLAPER1_UPPER 0 0 DOORBELL_GBLAPER1_UPPER_ 2 11 mmBIF_DOORBELL_GBLAPER2_LOWER 0 0xe4b 4 0 0 DOORBELL_GBLAPER2_LOWER 0 0 DOORBELL_GBLAPER2_EN 0 0 DOORBELL_GBLAPER2_LOWER_ 2 11 DOORBELL_GBLAPER2_EN_ 31 31 mmBIF_DOORBELL_GBLAPER2_UPPER 0 0xe4c 2 0 0 DOORBELL_GBLAPER2_UPPER 0 0 DOORBELL_GBLAPER2_UPPER_ 2 11 mmREMAP_HDP_MEM_FLUSH_CNTL 0 0xe4d 2 0 0 ADDRESS 0 0 ADDRESS_ 2 18 mmREMAP_HDP_REG_FLUSH_CNTL 0 0xe4e 2 0 0 ADDRESS 0 0 ADDRESS_ 2 18 mmBIF_RB_CNTL 0 0xe4f 12 0 0 RB_ENABLE 0 0 RB_SIZE 0 0 WPTR_WRITEBACK_ENABLE 0 0 WPTR_WRITEBACK_TIMER 0 0 BIF_RB_TRAN 0 0 WPTR_OVERFLOW_CLEAR 0 0 RB_ENABLE_ 0 0 RB_SIZE_ 1 5 WPTR_WRITEBACK_ENABLE_ 8 8 WPTR_WRITEBACK_TIMER_ 9 13 BIF_RB_TRAN_ 17 17 WPTR_OVERFLOW_CLEAR_ 31 31 mmBIF_RB_BASE 0 0xe50 2 0 0 ADDR 0 0 ADDR_ 0 31 mmBIF_RB_RPTR 0 0xe51 2 0 0 OFFSET 0 0 OFFSET_ 2 17 mmBIF_RB_WPTR 0 0xe52 4 0 0 BIF_RB_OVERFLOW 0 0 OFFSET 0 0 BIF_RB_OVERFLOW_ 0 0 OFFSET_ 2 17 mmBIF_RB_WPTR_ADDR_HI 0 0xe53 2 0 0 ADDR 0 0 ADDR_ 0 7 mmBIF_RB_WPTR_ADDR_LO 0 0xe54 2 0 0 ADDR 0 0 ADDR_ 2 31 mmMAILBOX_INDEX 0 0xe55 2 0 0 MAILBOX_INDEX 0 0 MAILBOX_INDEX_ 0 4 mmBIF_GPUIOV_RESET_NOTIFICATION 0 0xe62 2 0 0 RESET_NOTIFICATION 0 0 RESET_NOTIFICATION_ 0 31 mmBIF_UVD_GPUIOV_CFG_SIZE 0 0xe63 2 0 0 UVD_GPUIOV_CFG_SIZE 0 0 UVD_GPUIOV_CFG_SIZE_ 0 3 mmBIF_VCE_GPUIOV_CFG_SIZE 0 0xe64 2 0 0 VCE_GPUIOV_CFG_SIZE 0 0 VCE_GPUIOV_CFG_SIZE_ 0 3 mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0 0xe65 2 0 0 GFX_SDMA_GPUIOV_CFG_SIZE 0 0 GFX_SDMA_GPUIOV_CFG_SIZE_ 0 3 mmBIF_GMI_WRR_WEIGHT 0 0xe66 6 0 0 GMI_REQ_REALTIME_WEIGHT 0 0 GMI_REQ_NORM_P_WEIGHT 0 0 GMI_REQ_NORM_NP_WEIGHT 0 0 GMI_REQ_REALTIME_WEIGHT_ 0 7 GMI_REQ_NORM_P_WEIGHT_ 8 15 GMI_REQ_NORM_NP_WEIGHT_ 16 23 mmNBIF_STRAP_WRITE_CTRL 0 0xe67 2 0 0 NBIF_STRAP_WRITE_ONCE_ENABLE 0 0 NBIF_STRAP_WRITE_ONCE_ENABLE_ 0 0 mmBIF_PERSTB_PAD_CNTL 0 0xe68 2 0 0 PERSTB_PAD_CNTL 0 0 PERSTB_PAD_CNTL_ 0 15 mmBIF_PX_EN_PAD_CNTL 0 0xe69 2 0 0 PX_EN_PAD_CNTL 0 0 PX_EN_PAD_CNTL_ 0 7 mmBIF_REFPADKIN_PAD_CNTL 0 0xe6a 2 0 0 REFPADKIN_PAD_CNTL 0 0 REFPADKIN_PAD_CNTL_ 0 7 mmBIF_CLKREQB_PAD_CNTL 0 0xe6b 2 0 0 CLKREQB_PAD_CNTL 0 0 CLKREQB_PAD_CNTL_ 0 23 mmRCC_BACO_CNTL_MISC 0 0xda7 4 0 0 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 0 0 BIF_ROM_REQ_DIS_ 0 0 BIF_AZ_REQ_DIS_ 1 1 mmRCC_RESET_EN 0 0xda8 2 0 0 DB_APER_RESET_EN 0 0 DB_APER_RESET_EN_ 15 15 mmRCC_VDM_SUPPORT 0 0xda9 10 0 0 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 0 0 OTHER_VDM_SUPPORT 0 0 ROUTE_TO_RC_CHECK_IN_RCMODE 0 0 ROUTE_BROADCAST_CHECK_IN_RCMODE 0 0 MCTP_SUPPORT_ 0 0 AMPTP_SUPPORT_ 1 1 OTHER_VDM_SUPPORT_ 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE_ 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE_ 4 4 mmRCC_PEER_REG_RANGE0 0 0xdde 4 0 0 START_ADDR 0 0 END_ADDR 0 0 START_ADDR_ 0 15 END_ADDR_ 16 31 mmRCC_PEER_REG_RANGE1 0 0xddf 4 0 0 START_ADDR 0 0 END_ADDR 0 0 START_ADDR_ 0 15 END_ADDR_ 16 31 mmRCC_BUS_CNTL 0 0xde1 38 0 0 PMI_IO_DIS 0 0 PMI_MEM_DIS 0 0 PMI_BM_DIS 0 0 PMI_IO_DIS_DN 0 0 PMI_MEM_DIS_DN 0 0 PMI_IO_DIS_UP 0 0 PMI_MEM_DIS_UP 0 0 ROOT_ERR_LOG_ON_EVENT 0 0 HOST_CPL_POISONED_LOG_IN_RC 0 0 DN_SEC_SIG_CPLCA_WITH_EP_ERR 0 0 DN_SEC_RCV_CPLCA_WITH_EP_ERR 0 0 DN_SEC_RCV_CPLUR_WITH_EP_ERR 0 0 DN_PRI_SIG_CPLCA_WITH_EP_ERR 0 0 DN_PRI_RCV_CPLCA_WITH_EP_ERR 0 0 DN_PRI_RCV_CPLUR_WITH_EP_ERR 0 0 MAX_PAYLOAD_SIZE_MODE 0 0 PRIV_MAX_PAYLOAD_SIZE 0 0 MAX_READ_REQUEST_SIZE_MODE 0 0 PRIV_MAX_READ_REQUEST_SIZE 0 0 PMI_IO_DIS_ 2 2 PMI_MEM_DIS_ 3 3 PMI_BM_DIS_ 4 4 PMI_IO_DIS_DN_ 5 5 PMI_MEM_DIS_DN_ 6 6 PMI_IO_DIS_UP_ 7 7 PMI_MEM_DIS_UP_ 8 8 ROOT_ERR_LOG_ON_EVENT_ 12 12 HOST_CPL_POISONED_LOG_IN_RC_ 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR_ 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR_ 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR_ 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR_ 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR_ 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR_ 21 21 MAX_PAYLOAD_SIZE_MODE_ 24 24 PRIV_MAX_PAYLOAD_SIZE_ 25 27 MAX_READ_REQUEST_SIZE_MODE_ 28 28 PRIV_MAX_READ_REQUEST_SIZE_ 29 31 mmRCC_CONFIG_CNTL 0 0xde2 6 0 0 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 0 0 GRPH_ADRSEL 0 0 CFG_VGA_RAM_EN_ 0 0 GENMO_MONO_ADDRESS_B_ 2 2 GRPH_ADRSEL_ 3 4 mmRCC_CONFIG_F0_BASE 0 0xde6 2 0 0 F0_BASE 0 0 F0_BASE_ 0 31 mmRCC_CONFIG_APER_SIZE 0 0xde7 2 0 0 APER_SIZE 0 0 APER_SIZE_ 0 31 mmRCC_CONFIG_REG_APER_SIZE 0 0xde8 2 0 0 REG_APER_SIZE 0 0 REG_APER_SIZE_ 0 19 mmRCC_XDMA_LO 0 0xde9 4 0 0 BIF_XDMA_LOWER_BOUND 0 0 BIF_XDMA_APER_EN 0 0 BIF_XDMA_LOWER_BOUND_ 0 28 BIF_XDMA_APER_EN_ 31 31 mmRCC_XDMA_HI 0 0xdea 2 0 0 BIF_XDMA_UPPER_BOUND 0 0 BIF_XDMA_UPPER_BOUND_ 0 28 mmRCC_FEATURES_CONTROL_MISC 0 0xdeb 28 0 0 UR_PSN_PKT_REPORT_POISON_DIS 0 0 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS 0 0 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS 0 0 ATC_PRG_RESP_PASID_UR_EN 0 0 RX_IGNORE_TRANSMRD_UR 0 0 RX_IGNORE_TRANSMWR_UR 0 0 RX_IGNORE_ATSTRANSREQ_UR 0 0 RX_IGNORE_PAGEREQMSG_UR 0 0 RX_IGNORE_INVCPL_UR 0 0 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 0 0 CHECK_BME_ON_PENDING_PKT_GEN_DIS 0 0 PSN_CHECK_ON_PAYLOAD_DIS 0 0 CLR_MSI_PENDING_ON_MULTIEN_DIS 0 0 SET_DEVICE_ERR_FOR_ECRC_EN 0 0 UR_PSN_PKT_REPORT_POISON_DIS_ 4 4 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_ 5 5 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_ 6 6 ATC_PRG_RESP_PASID_UR_EN_ 8 8 RX_IGNORE_TRANSMRD_UR_ 9 9 RX_IGNORE_TRANSMWR_UR_ 10 10 RX_IGNORE_ATSTRANSREQ_UR_ 11 11 RX_IGNORE_PAGEREQMSG_UR_ 12 12 RX_IGNORE_INVCPL_UR_ 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_ 14 14 CHECK_BME_ON_PENDING_PKT_GEN_DIS_ 15 15 PSN_CHECK_ON_PAYLOAD_DIS_ 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS_ 17 17 SET_DEVICE_ERR_FOR_ECRC_EN_ 18 18 mmRCC_BUSNUM_CNTL1 0 0xdec 2 0 0 ID_MASK 0 0 ID_MASK_ 0 7 mmRCC_BUSNUM_LIST0 0 0xded 8 0 0 ID0 0 0 ID1 0 0 ID2 0 0 ID3 0 0 ID0_ 0 7 ID1_ 8 15 ID2_ 16 23 ID3_ 24 31 mmRCC_BUSNUM_LIST1 0 0xdee 8 0 0 ID4 0 0 ID5 0 0 ID6 0 0 ID7 0 0 ID4_ 0 7 ID5_ 8 15 ID6_ 16 23 ID7_ 24 31 mmRCC_BUSNUM_CNTL2 0 0xdef 8 0 0 AUTOUPDATE_SEL 0 0 AUTOUPDATE_EN 0 0 HDPREG_CNTL 0 0 ERROR_MULTIPLE_ID_MATCH 0 0 AUTOUPDATE_SEL_ 0 7 AUTOUPDATE_EN_ 8 8 HDPREG_CNTL_ 16 16 ERROR_MULTIPLE_ID_MATCH_ 17 17 mmRCC_CAPTURE_HOST_BUSNUM 0 0xdf0 2 0 0 CHECK_EN 0 0 CHECK_EN_ 0 0 mmRCC_HOST_BUSNUM 0 0xdf1 2 0 0 HOST_ID 0 0 HOST_ID_ 0 15 mmRCC_PEER0_FB_OFFSET_HI 0 0xdf2 2 0 0 PEER0_FB_OFFSET_HI 0 0 PEER0_FB_OFFSET_HI_ 0 19 mmRCC_PEER0_FB_OFFSET_LO 0 0xdf3 4 0 0 PEER0_FB_OFFSET_LO 0 0 PEER0_FB_EN 0 0 PEER0_FB_OFFSET_LO_ 0 19 PEER0_FB_EN_ 31 31 mmRCC_PEER1_FB_OFFSET_HI 0 0xdf4 2 0 0 PEER1_FB_OFFSET_HI 0 0 PEER1_FB_OFFSET_HI_ 0 19 mmRCC_PEER1_FB_OFFSET_LO 0 0xdf5 4 0 0 PEER1_FB_OFFSET_LO 0 0 PEER1_FB_EN 0 0 PEER1_FB_OFFSET_LO_ 0 19 PEER1_FB_EN_ 31 31 mmRCC_PEER2_FB_OFFSET_HI 0 0xdf6 2 0 0 PEER2_FB_OFFSET_HI 0 0 PEER2_FB_OFFSET_HI_ 0 19 mmRCC_PEER2_FB_OFFSET_LO 0 0xdf7 4 0 0 PEER2_FB_OFFSET_LO 0 0 PEER2_FB_EN 0 0 PEER2_FB_OFFSET_LO_ 0 19 PEER2_FB_EN_ 31 31 mmRCC_PEER3_FB_OFFSET_HI 0 0xdf8 2 0 0 PEER3_FB_OFFSET_HI 0 0 PEER3_FB_OFFSET_HI_ 0 19 mmRCC_PEER3_FB_OFFSET_LO 0 0xdf9 4 0 0 PEER3_FB_OFFSET_LO 0 0 PEER3_FB_EN 0 0 PEER3_FB_OFFSET_LO_ 0 19 PEER3_FB_EN_ 31 31 mmRCC_DEVFUNCNUM_LIST0 0 0xdfa 8 0 0 DEVFUNC_ID0 0 0 DEVFUNC_ID1 0 0 DEVFUNC_ID2 0 0 DEVFUNC_ID3 0 0 DEVFUNC_ID0_ 0 7 DEVFUNC_ID1_ 8 15 DEVFUNC_ID2_ 16 23 DEVFUNC_ID3_ 24 31 mmRCC_DEVFUNCNUM_LIST1 0 0xdfb 8 0 0 DEVFUNC_ID4 0 0 DEVFUNC_ID5 0 0 DEVFUNC_ID6 0 0 DEVFUNC_ID7 0 0 DEVFUNC_ID4_ 0 7 DEVFUNC_ID5_ 8 15 DEVFUNC_ID6_ 16 23 DEVFUNC_ID7_ 24 31 mmRCC_DEV0_LINK_CNTL 0 0xdfd 4 0 0 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 0 0 LINK_DOWN_EXIT_ 0 0 LINK_DOWN_ENTRY_ 8 8 mmRCC_CMN_LINK_CNTL 0 0xdfe 8 0 0 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 0 0 BLOCK_PME_ON_LDN_DIS 0 0 PM_L1_IDLE_CHECK_DMA_EN 0 0 BLOCK_PME_ON_L0S_DIS_ 0 0 BLOCK_PME_ON_L1_DIS_ 1 1 BLOCK_PME_ON_LDN_DIS_ 2 2 PM_L1_IDLE_CHECK_DMA_EN_ 3 3 mmRCC_EP_REQUESTERID_RESTORE 0 0xdff 4 0 0 EP_REQID_BUS 0 0 EP_REQID_DEV 0 0 EP_REQID_BUS_ 0 7 EP_REQID_DEV_ 8 12 mmRCC_LTR_LSWITCH_CNTL 0 0xe00 2 0 0 LSWITCH_LATENCY_VALUE 0 0 LSWITCH_LATENCY_VALUE_ 0 9 mmRCC_MH_ARB_CNTL 0 0xe01 4 0 0 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 0 0 MH_ARB_MODE_ 0 0 MH_ARB_FIX_PRIORITY_ 1 14 mmGFXMSIX_VECT0_ADDR_LO 0 0x10800 2 0 0 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 mmGFXMSIX_VECT0_ADDR_HI 0 0x10801 2 0 0 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 mmGFXMSIX_VECT0_MSG_DATA 0 0x10802 2 0 0 MSG_DATA 0 0 MSG_DATA_ 0 31 mmGFXMSIX_VECT0_CONTROL 0 0x10803 2 0 0 MASK_BIT 0 0 MASK_BIT_ 0 0 mmGFXMSIX_VECT1_ADDR_LO 0 0x10804 2 0 0 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 mmGFXMSIX_VECT1_ADDR_HI 0 0x10805 2 0 0 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 mmGFXMSIX_VECT1_MSG_DATA 0 0x10806 2 0 0 MSG_DATA 0 0 MSG_DATA_ 0 31 mmGFXMSIX_VECT1_CONTROL 0 0x10807 2 0 0 MASK_BIT 0 0 MASK_BIT_ 0 0 mmGFXMSIX_VECT2_ADDR_LO 0 0x10808 2 0 0 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 mmGFXMSIX_VECT2_ADDR_HI 0 0x10809 2 0 0 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 mmGFXMSIX_VECT2_MSG_DATA 0 0x1080a 2 0 0 MSG_DATA 0 0 MSG_DATA_ 0 31 mmGFXMSIX_VECT2_CONTROL 0 0x1080b 2 0 0 MASK_BIT 0 0 MASK_BIT_ 0 0 mmGFXMSIX_PBA 0 0x10c00 6 0 0 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 0 0 MSIX_PENDING_BITS_2 0 0 MSIX_PENDING_BITS_0_ 0 0 MSIX_PENDING_BITS_1_ 1 1 MSIX_PENDING_BITS_2_ 2 2 mmRCC_DEV0_PORT_STRAP0 0 0xd27 20 0 0 STRAP_ARI_EN_DN_DEV0 0 0 STRAP_ACS_EN_DN_DEV0 0 0 STRAP_AER_EN_DN_DEV0 0 0 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 0 0 STRAP_DEVICE_ID_DN_DEV0 0 0 STRAP_INTERRUPT_PIN_DN_DEV0 0 0 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 0 0 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 0 0 STRAP_EPF0_DUMMY_EN_DEV0 0 0 STRAP_ARI_EN_DN_DEV0_ 1 1 STRAP_ACS_EN_DN_DEV0_ 2 2 STRAP_AER_EN_DN_DEV0_ 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0_ 4 4 STRAP_DEVICE_ID_DN_DEV0_ 5 20 STRAP_INTERRUPT_PIN_DN_DEV0_ 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_ 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_ 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_ 28 30 STRAP_EPF0_DUMMY_EN_DEV0_ 31 31 mmRCC_DEV0_PORT_STRAP1 0 0xd28 4 0 0 STRAP_SUBSYS_ID_DN_DEV0 0 0 STRAP_SUBSYS_VEN_ID_DN_DEV0 0 0 STRAP_SUBSYS_ID_DN_DEV0_ 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0_ 16 31 mmRCC_DEV0_PORT_STRAP2 0 0xd29 42 0 0 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 0 0 STRAP_E2E_PREFIX_EN_DEV0 0 0 STRAP_ECN1P1_EN_DEV0 0 0 STRAP_ECRC_CHECK_EN_DEV0 0 0 STRAP_ECRC_GEN_EN_DEV0 0 0 STRAP_ERR_REPORTING_DIS_DEV0 0 0 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 0 0 STRAP_EXTENDED_TAG_ECN_EN_DEV0 0 0 STRAP_EXT_VC_COUNT_DN_DEV0 0 0 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 0 0 STRAP_GEN2_COMPLIANCE_DEV0 0 0 STRAP_GEN2_EN_DEV0 0 0 STRAP_GEN3_COMPLIANCE_DEV0 0 0 STRAP_TARGET_LINK_SPEED_DEV0 0 0 STRAP_INTERNAL_ERR_EN_DEV0 0 0 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 0 0 STRAP_L0S_EXIT_LATENCY_DEV0 0 0 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 0 0 STRAP_L1_EXIT_LATENCY_DEV0 0 0 STRAP_DE_EMPHASIS_SEL_DN_DEV0_ 0 0 STRAP_DSN_EN_DN_DEV0_ 1 1 STRAP_E2E_PREFIX_EN_DEV0_ 2 2 STRAP_ECN1P1_EN_DEV0_ 3 3 STRAP_ECRC_CHECK_EN_DEV0_ 4 4 STRAP_ECRC_GEN_EN_DEV0_ 5 5 STRAP_ERR_REPORTING_DIS_DEV0_ 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0_ 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0_ 8 8 STRAP_EXT_VC_COUNT_DN_DEV0_ 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_ 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_ 13 13 STRAP_GEN2_COMPLIANCE_DEV0_ 14 14 STRAP_GEN2_EN_DEV0_ 15 15 STRAP_GEN3_COMPLIANCE_DEV0_ 16 16 STRAP_TARGET_LINK_SPEED_DEV0_ 17 18 STRAP_INTERNAL_ERR_EN_DEV0_ 19 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_ 20 22 STRAP_L0S_EXIT_LATENCY_DEV0_ 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0_ 26 28 STRAP_L1_EXIT_LATENCY_DEV0_ 29 31 mmRCC_DEV0_PORT_STRAP3 0 0xd2a 34 0 0 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 0 0 STRAP_LTR_EN_DN_DEV0 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 0 0 STRAP_MSI_EN_DN_DEV0 0 0 STRAP_MSTCPL_TIMEOUT_EN_DEV0 0 0 STRAP_NO_SOFT_RESET_DN_DEV0 0 0 STRAP_OBFF_SUPPORTED_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 0 0 STRAP_PM_SUPPORT_DEV0 0 0 STRAP_PM_SUPPORT_DN_DEV0 0 0 STRAP_ATOMIC_EN_DN_DEV0 0 0 STRAP_VENDOR_ID_BIT_DN_DEV0 0 0 STRAP_PMC_DSI_DN_DEV0 0 0 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_ 0 0 STRAP_LTR_EN_DEV0_ 1 1 STRAP_LTR_EN_DN_DEV0_ 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0_ 3 5 STRAP_MSI_EN_DN_DEV0_ 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0_ 7 7 STRAP_NO_SOFT_RESET_DN_DEV0_ 8 8 STRAP_OBFF_SUPPORTED_DEV0_ 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_ 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_ 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_ 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_ 21 24 STRAP_PM_SUPPORT_DEV0_ 25 26 STRAP_PM_SUPPORT_DN_DEV0_ 27 28 STRAP_ATOMIC_EN_DN_DEV0_ 29 29 STRAP_VENDOR_ID_BIT_DN_DEV0_ 30 30 STRAP_PMC_DSI_DN_DEV0_ 31 31 mmRCC_DEV0_PORT_STRAP4 0 0xd2b 8 0 0 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_ 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_ 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_ 24 31 mmRCC_DEV0_PORT_STRAP5 0 0xd2c 34 0 0 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 0 0 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 0 0 STRAP_ATOMIC_64BIT_EN_DN_DEV0 0 0 STRAP_ATOMIC_ROUTING_EN_DEV0 0 0 STRAP_VC_EN_DN_DEV0 0 0 STRAP_TwoVC_EN_DEV0 0 0 STRAP_TwoVC_EN_DN_DEV0 0 0 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 0 0 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 0 0 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 0 0 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 0 0 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 0 0 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 0 0 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 0 0 STRAP_MSI_MAP_EN_DEV0 0 0 STRAP_SSID_EN_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_ 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_ 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0_ 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0_ 18 18 STRAP_VC_EN_DN_DEV0_ 19 19 STRAP_TwoVC_EN_DEV0_ 20 20 STRAP_TwoVC_EN_DN_DEV0_ 21 21 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_ 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_ 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_ 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_ 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_ 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_ 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_ 29 29 STRAP_MSI_MAP_EN_DEV0_ 30 30 STRAP_SSID_EN_DEV0_ 31 31 mmRCC_DEV0_PORT_STRAP6 0 0xd2d 4 0 0 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 0 0 STRAP_CFG_CRS_EN_DEV0_ 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_ 1 1 mmRCC_DEV0_PORT_STRAP7 0 0xd2e 12 0 0 STRAP_PORT_NUMBER_DEV0 0 0 STRAP_MAJOR_REV_ID_DN_DEV0 0 0 STRAP_MINOR_REV_ID_DN_DEV0 0 0 STRAP_RP_BUSNUM_DEV0 0 0 STRAP_DN_DEVNUM_DEV0 0 0 STRAP_DN_FUNCID_DEV0 0 0 STRAP_PORT_NUMBER_DEV0_ 0 7 STRAP_MAJOR_REV_ID_DN_DEV0_ 8 11 STRAP_MINOR_REV_ID_DN_DEV0_ 12 15 STRAP_RP_BUSNUM_DEV0_ 16 23 STRAP_DN_DEVNUM_DEV0_ 24 28 STRAP_DN_FUNCID_DEV0_ 29 31 mmRCC_DEV0_EPF0_STRAP0 0 0xd2f 16 0 0 STRAP_DEVICE_ID_DEV0_F0 0 0 STRAP_MAJOR_REV_ID_DEV0_F0 0 0 STRAP_MINOR_REV_ID_DEV0_F0 0 0 STRAP_ATI_REV_ID_DEV0_F0 0 0 STRAP_FUNC_EN_DEV0_F0 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 0 0 STRAP_D1_SUPPORT_DEV0_F0 0 0 STRAP_D2_SUPPORT_DEV0_F0 0 0 STRAP_DEVICE_ID_DEV0_F0_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F0_ 16 19 STRAP_MINOR_REV_ID_DEV0_F0_ 20 23 STRAP_ATI_REV_ID_DEV0_F0_ 24 27 STRAP_FUNC_EN_DEV0_F0_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_ 29 29 STRAP_D1_SUPPORT_DEV0_F0_ 30 30 STRAP_D2_SUPPORT_DEV0_F0_ 31 31 mmRCC_DEV0_EPF0_STRAP1 0 0xd30 4 0 0 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 0 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 0 0 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_ 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_ 16 31 mmRCC_DEV0_EPF0_STRAP13 0 0xd31 6 0 0 STRAP_CLASS_CODE_PIF_DEV0_F0 0 0 STRAP_CLASS_CODE_SUB_DEV0_F0 0 0 STRAP_CLASS_CODE_BASE_DEV0_F0 0 0 STRAP_CLASS_CODE_PIF_DEV0_F0_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0_ 16 23 mmRCC_DEV0_EPF0_STRAP2 0 0xd32 42 0 0 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 0 0 STRAP_64BAR_DIS_DEV0_F0 0 0 STRAP_NO_SOFT_RESET_DEV0_F0 0 0 STRAP_RESIZE_BAR_EN_DEV0_F0 0 0 STRAP_MAX_PASID_WIDTH_DEV0_F0 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 0 0 STRAP_ARI_EN_DEV0_F0 0 0 STRAP_AER_EN_DEV0_F0 0 0 STRAP_ACS_EN_DEV0_F0 0 0 STRAP_ATS_EN_DEV0_F0 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 0 0 STRAP_DPA_EN_DEV0_F0 0 0 STRAP_DSN_EN_DEV0_F0 0 0 STRAP_VC_EN_DEV0_F0 0 0 STRAP_MSI_MULTI_CAP_DEV0_F0 0 0 STRAP_PAGE_REQ_EN_DEV0_F0 0 0 STRAP_PASID_EN_DEV0_F0 0 0 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 0 0 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 0 0 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 0 0 STRAP_SRIOV_EN_DEV0_F0_ 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0_ 1 5 STRAP_64BAR_DIS_DEV0_F0_ 6 6 STRAP_NO_SOFT_RESET_DEV0_F0_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0_ 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0_ 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_ 14 14 STRAP_ARI_EN_DEV0_F0_ 15 15 STRAP_AER_EN_DEV0_F0_ 16 16 STRAP_ACS_EN_DEV0_F0_ 17 17 STRAP_ATS_EN_DEV0_F0_ 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0_ 20 20 STRAP_DPA_EN_DEV0_F0_ 21 21 STRAP_DSN_EN_DEV0_F0_ 22 22 STRAP_VC_EN_DEV0_F0_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0_ 24 26 STRAP_PAGE_REQ_EN_DEV0_F0_ 27 27 STRAP_PASID_EN_DEV0_F0_ 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_ 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_ 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_ 31 31 mmRCC_DEV0_EPF0_STRAP3 0 0xd33 22 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 0 0 STRAP_SUBSYS_ID_DEV0_F0 0 0 STRAP_MSI_EN_DEV0_F0 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 0 0 STRAP_MSIX_EN_DEV0_F0 0 0 STRAP_MSIX_TABLE_BIR_DEV0_F0 0 0 STRAP_PMC_DSI_DEV0_F0 0 0 STRAP_VENDOR_ID_BIT_DEV0_F0 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_ 0 0 STRAP_PWR_EN_DEV0_F0_ 1 1 STRAP_SUBSYS_ID_DEV0_F0_ 2 17 STRAP_MSI_EN_DEV0_F0_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0_ 19 19 STRAP_MSIX_EN_DEV0_F0_ 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0_ 21 23 STRAP_PMC_DSI_DEV0_F0_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F0_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_ 27 27 mmRCC_DEV0_EPF0_STRAP4 0 0xd34 14 0 0 STRAP_MSIX_TABLE_OFFSET_DEV0_F0 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F0 0 0 STRAP_ATOMIC_EN_DEV0_F0 0 0 STRAP_FLR_EN_DEV0_F0 0 0 STRAP_PME_SUPPORT_DEV0_F0 0 0 STRAP_INTERRUPT_PIN_DEV0_F0 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F0 0 0 STRAP_MSIX_TABLE_OFFSET_DEV0_F0_ 0 19 STRAP_ATOMIC_64BIT_EN_DEV0_F0_ 20 20 STRAP_ATOMIC_EN_DEV0_F0_ 21 21 STRAP_FLR_EN_DEV0_F0_ 22 22 STRAP_PME_SUPPORT_DEV0_F0_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F0_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0_ 31 31 mmRCC_DEV0_EPF0_STRAP5 0 0xd35 2 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F0_ 0 15 mmRCC_DEV0_EPF0_STRAP8 0 0xd36 36 0 0 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 0 0 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 0 STRAP_DOORBELL_BAR_DIS_DEV0_F0 0 0 STRAP_FB_ALWAYS_ON_DEV0_F0 0 0 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 0 0 STRAP_IO_BAR_DIS_DEV0_F0 0 0 STRAP_LFB_ERRMSG_EN_DEV0_F0 0 0 STRAP_MEM_AP_SIZE_DEV0_F0 0 0 STRAP_REG_AP_SIZE_DEV0_F0 0 0 STRAP_ROM_AP_SIZE_DEV0_F0 0 0 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 0 0 STRAP_VF_MEM_AP_SIZE_DEV0_F0 0 0 STRAP_VF_REG_AP_SIZE_DEV0_F0 0 0 STRAP_VGA_DIS_DEV0_F0 0 0 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 0 0 STRAP_VF_REG_PROT_DIS_DEV0_F0 0 0 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 0 0 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 0 0 STRAP_BAR_COMPLIANCE_EN_DEV0_F0_ 0 0 STRAP_DOORBELL_APER_SIZE_DEV0_F0_ 1 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0_ 3 3 STRAP_FB_ALWAYS_ON_DEV0_F0_ 4 4 STRAP_FB_CPL_TYPE_SEL_DEV0_F0_ 5 6 STRAP_IO_BAR_DIS_DEV0_F0_ 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0_ 8 8 STRAP_MEM_AP_SIZE_DEV0_F0_ 9 11 STRAP_REG_AP_SIZE_DEV0_F0_ 12 13 STRAP_ROM_AP_SIZE_DEV0_F0_ 14 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_ 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0_ 19 21 STRAP_VF_REG_AP_SIZE_DEV0_F0_ 22 23 STRAP_VGA_DIS_DEV0_F0_ 24 24 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_ 25 25 STRAP_VF_REG_PROT_DIS_DEV0_F0_ 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0_ 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_ 30 31 mmRCC_DEV0_EPF0_STRAP9 0 0xd37 0 0 0 mmRCC_DEV0_EPF1_STRAP0 0 0xd38 14 0 0 STRAP_DEVICE_ID_DEV0_F1 0 0 STRAP_MAJOR_REV_ID_DEV0_F1 0 0 STRAP_MINOR_REV_ID_DEV0_F1 0 0 STRAP_FUNC_EN_DEV0_F1 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 0 0 STRAP_D1_SUPPORT_DEV0_F1 0 0 STRAP_D2_SUPPORT_DEV0_F1 0 0 STRAP_DEVICE_ID_DEV0_F1_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F1_ 16 19 STRAP_MINOR_REV_ID_DEV0_F1_ 20 23 STRAP_FUNC_EN_DEV0_F1_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_ 29 29 STRAP_D1_SUPPORT_DEV0_F1_ 30 30 STRAP_D2_SUPPORT_DEV0_F1_ 31 31 mmRCC_DEV0_EPF1_STRAP10 0 0xd39 4 0 0 STRAP_APER1_RESIZE_EN_DEV0_F1 0 0 STRAP_APER1_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER1_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCC_DEV0_EPF1_STRAP11 0 0xd3a 4 0 0 STRAP_APER2_RESIZE_EN_DEV0_F1 0 0 STRAP_APER2_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER2_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCC_DEV0_EPF1_STRAP12 0 0xd3b 4 0 0 STRAP_APER3_RESIZE_EN_DEV0_F1 0 0 STRAP_APER3_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER3_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCC_DEV0_EPF1_STRAP13 0 0xd3c 6 0 0 STRAP_CLASS_CODE_PIF_DEV0_F1 0 0 STRAP_CLASS_CODE_SUB_DEV0_F1 0 0 STRAP_CLASS_CODE_BASE_DEV0_F1 0 0 STRAP_CLASS_CODE_PIF_DEV0_F1_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1_ 16 23 mmRCC_DEV0_EPF1_STRAP2 0 0xd3d 22 0 0 STRAP_NO_SOFT_RESET_DEV0_F1 0 0 STRAP_RESIZE_BAR_EN_DEV0_F1 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 0 0 STRAP_AER_EN_DEV0_F1 0 0 STRAP_ACS_EN_DEV0_F1 0 0 STRAP_ATS_EN_DEV0_F1 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 0 0 STRAP_DPA_EN_DEV0_F1 0 0 STRAP_DSN_EN_DEV0_F1 0 0 STRAP_VC_EN_DEV0_F1 0 0 STRAP_MSI_MULTI_CAP_DEV0_F1 0 0 STRAP_NO_SOFT_RESET_DEV0_F1_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_ 14 14 STRAP_AER_EN_DEV0_F1_ 16 16 STRAP_ACS_EN_DEV0_F1_ 17 17 STRAP_ATS_EN_DEV0_F1_ 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1_ 20 20 STRAP_DPA_EN_DEV0_F1_ 21 21 STRAP_DSN_EN_DEV0_F1_ 22 22 STRAP_VC_EN_DEV0_F1_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1_ 24 26 mmRCC_DEV0_EPF1_STRAP3 0 0xd3e 20 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 0 0 STRAP_SUBSYS_ID_DEV0_F1 0 0 STRAP_MSI_EN_DEV0_F1 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 0 0 STRAP_MSIX_EN_DEV0_F1 0 0 STRAP_PMC_DSI_DEV0_F1 0 0 STRAP_VENDOR_ID_BIT_DEV0_F1 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_ 0 0 STRAP_PWR_EN_DEV0_F1_ 1 1 STRAP_SUBSYS_ID_DEV0_F1_ 2 17 STRAP_MSI_EN_DEV0_F1_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1_ 19 19 STRAP_MSIX_EN_DEV0_F1_ 20 20 STRAP_PMC_DSI_DEV0_F1_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F1_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_ 27 27 mmRCC_DEV0_EPF1_STRAP4 0 0xd3f 12 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F1 0 0 STRAP_ATOMIC_EN_DEV0_F1 0 0 STRAP_FLR_EN_DEV0_F1 0 0 STRAP_PME_SUPPORT_DEV0_F1 0 0 STRAP_INTERRUPT_PIN_DEV0_F1 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F1 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F1_ 20 20 STRAP_ATOMIC_EN_DEV0_F1_ 21 21 STRAP_FLR_EN_DEV0_F1_ 22 22 STRAP_PME_SUPPORT_DEV0_F1_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F1_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1_ 31 31 mmRCC_DEV0_EPF1_STRAP5 0 0xd40 2 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F1_ 0 15 mmRCC_DEV0_EPF1_STRAP6 0 0xd41 20 0 0 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER0_64BAR_EN_DEV0_F1 0 0 STRAP_APER0_AP_SIZE_DEV0_F1 0 0 STRAP_APER1_EN_DEV0_F1 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER2_EN_DEV0_F1 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER3_EN_DEV0_F1 0 0 STRAP_APER3_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER0_EN_DEV0_F1_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_ 1 1 STRAP_APER0_64BAR_EN_DEV0_F1_ 2 2 STRAP_APER0_AP_SIZE_DEV0_F1_ 4 6 STRAP_APER1_EN_DEV0_F1_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_ 9 9 STRAP_APER2_EN_DEV0_F1_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_ 17 17 STRAP_APER3_EN_DEV0_F1_ 24 24 STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_ 25 25 mmRCC_DEV0_EPF1_STRAP7 0 0xd42 4 0 0 STRAP_ROM_APER_EN_DEV0_F1 0 0 STRAP_ROM_APER_SIZE_DEV0_F1 0 0 STRAP_ROM_APER_EN_DEV0_F1_ 0 0 STRAP_ROM_APER_SIZE_DEV0_F1_ 1 4 mmBIF_BME_STATUS 0 0xe0b 4 0 0 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 0 0 DMA_ON_BME_LOW_ 0 0 CLEAR_DMA_ON_BME_LOW_ 16 16 mmBIF_ATOMIC_ERR_LOG 0 0xe0c 8 0 0 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 0 0 CLEAR_UR_ATOMIC_OPCODE 0 0 CLEAR_UR_ATOMIC_REQEN_LOW 0 0 UR_ATOMIC_OPCODE_ 0 0 UR_ATOMIC_REQEN_LOW_ 1 1 CLEAR_UR_ATOMIC_OPCODE_ 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_ 17 17 mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xe13 2 0 0 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0 DOORBELL_SELFRING_GPA_APER_BASE_HIGH_ 0 31 mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xe14 2 0 0 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0 DOORBELL_SELFRING_GPA_APER_BASE_LOW_ 0 31 mmDOORBELL_SELFRING_GPA_APER_CNTL 0 0xe15 4 0 0 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_SIZE 0 0 DOORBELL_SELFRING_GPA_APER_EN_ 0 0 DOORBELL_SELFRING_GPA_APER_SIZE_ 8 15 mmHDP_REG_COHERENCY_FLUSH_CNTL 0 0xe16 2 0 0 HDP_REG_FLUSH_ADDR 0 0 HDP_REG_FLUSH_ADDR_ 0 0 mmHDP_MEM_COHERENCY_FLUSH_CNTL 0 0xe17 2 0 0 HDP_MEM_FLUSH_ADDR 0 0 HDP_MEM_FLUSH_ADDR_ 0 0 mmGPU_HDP_FLUSH_REQ 0 0xe26 24 0 0 CP0 0 0 CP1 0 0 CP2 0 0 CP3 0 0 CP4 0 0 CP5 0 0 CP6 0 0 CP7 0 0 CP8 0 0 CP9 0 0 SDMA0 0 0 SDMA1 0 0 CP0_ 0 0 CP1_ 1 1 CP2_ 2 2 CP3_ 3 3 CP4_ 4 4 CP5_ 5 5 CP6_ 6 6 CP7_ 7 7 CP8_ 8 8 CP9_ 9 9 SDMA0_ 10 10 SDMA1_ 11 11 mmGPU_HDP_FLUSH_DONE 0 0xe27 24 0 0 CP0 0 0 CP1 0 0 CP2 0 0 CP3 0 0 CP4 0 0 CP5 0 0 CP6 0 0 CP7 0 0 CP8 0 0 CP9 0 0 SDMA0 0 0 SDMA1 0 0 CP0_ 0 0 CP1_ 1 1 CP2_ 2 2 CP3_ 3 3 CP4_ 4 4 CP5_ 5 5 CP6_ 6 6 CP7_ 7 7 CP8_ 8 8 CP9_ 9 9 SDMA0_ 10 10 SDMA1_ 11 11 mmBIF_TRANS_PENDING 0 0xe28 4 0 0 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 0 0 BIF_MST_TRANS_PENDING_ 0 0 BIF_SLV_TRANS_PENDING_ 1 1 mmMAILBOX_MSGBUF_TRN_DW0 0 0xe56 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_TRN_DW1 0 0xe57 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_TRN_DW2 0 0xe58 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_TRN_DW3 0 0xe59 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_RCV_DW0 0 0xe5a 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_RCV_DW1 0 0xe5b 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_RCV_DW2 0 0xe5c 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_MSGBUF_RCV_DW3 0 0xe5d 2 0 0 MSGBUF_DATA 0 0 MSGBUF_DATA_ 0 31 mmMAILBOX_CONTROL 0 0xe5e 8 0 0 TRN_MSG_VALID 0 0 TRN_MSG_ACK 0 0 RCV_MSG_VALID 0 0 RCV_MSG_ACK 0 0 TRN_MSG_VALID_ 0 0 TRN_MSG_ACK_ 1 1 RCV_MSG_VALID_ 8 8 RCV_MSG_ACK_ 9 9 mmMAILBOX_INT_CNTL 0 0xe5f 4 0 0 VALID_INT_EN 0 0 ACK_INT_EN 0 0 VALID_INT_EN_ 0 0 ACK_INT_EN_ 1 1 mmBIF_VMHV_MAILBOX 0 0xe60 16 0 0 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 0 0 VMHV_MAILBOX_TRN_MSG_DATA 0 0 VMHV_MAILBOX_TRN_MSG_VALID 0 0 VMHV_MAILBOX_RCV_MSG_DATA 0 0 VMHV_MAILBOX_RCV_MSG_VALID 0 0 VMHV_MAILBOX_TRN_MSG_ACK 0 0 VMHV_MAILBOX_RCV_MSG_ACK 0 0 VMHV_MAILBOX_TRN_ACK_INTR_EN_ 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN_ 1 1 VMHV_MAILBOX_TRN_MSG_DATA_ 8 11 VMHV_MAILBOX_TRN_MSG_VALID_ 15 15 VMHV_MAILBOX_RCV_MSG_DATA_ 16 19 VMHV_MAILBOX_RCV_MSG_VALID_ 23 23 VMHV_MAILBOX_TRN_MSG_ACK_ 24 24 VMHV_MAILBOX_RCV_MSG_ACK_ 25 25 mmRCC_DOORBELL_APER_EN 0 0xde0 2 0 0 BIF_DOORBELL_APER_EN 0 0 BIF_DOORBELL_APER_EN_ 0 0 mmRCC_CONFIG_MEMSIZE 0 0xde3 2 0 0 CONFIG_MEMSIZE 0 0 CONFIG_MEMSIZE_ 0 31 mmRCC_CONFIG_RESERVED 0 0xde4 2 0 0 CONFIG_RESERVED 0 0 CONFIG_RESERVED_ 0 31 mmRCC_IOV_FUNC_IDENTIFIER 0 0xde5 4 0 0 FUNC_IDENTIFIER 0 0 IOV_ENABLE 0 0 FUNC_IDENTIFIER_ 0 0 IOV_ENABLE_ 31 31 mmSYSHUB_INDEX 0 0x8 2 0 0 INDEX 0 0 INDEX_ 0 31 mmSYSHUB_DATA 0 0x9 2 0 0 DATA 0 0 DATA_ 0 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0 0x403c000 20 0 3 STRAP_ARI_EN_DN_DEV0 0 0 STRAP_ACS_EN_DN_DEV0 0 0 STRAP_AER_EN_DN_DEV0 0 0 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 0 0 STRAP_DEVICE_ID_DN_DEV0 0 0 STRAP_INTERRUPT_PIN_DN_DEV0 0 0 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 0 0 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 0 0 STRAP_EPF0_DUMMY_EN_DEV0 0 0 STRAP_ARI_EN_DN_DEV0_ 1 1 STRAP_ACS_EN_DN_DEV0_ 2 2 STRAP_AER_EN_DN_DEV0_ 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0_ 4 4 STRAP_DEVICE_ID_DN_DEV0_ 5 20 STRAP_INTERRUPT_PIN_DN_DEV0_ 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_ 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_ 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_ 28 30 STRAP_EPF0_DUMMY_EN_DEV0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0 0x403c001 4 0 3 STRAP_SUBSYS_ID_DN_DEV0 0 0 STRAP_SUBSYS_VEN_ID_DN_DEV0 0 0 STRAP_SUBSYS_ID_DN_DEV0_ 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0_ 16 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0 0x403c002 42 0 3 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 0 0 STRAP_E2E_PREFIX_EN_DEV0 0 0 STRAP_ECN1P1_EN_DEV0 0 0 STRAP_ECRC_CHECK_EN_DEV0 0 0 STRAP_ECRC_GEN_EN_DEV0 0 0 STRAP_ERR_REPORTING_DIS_DEV0 0 0 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 0 0 STRAP_EXTENDED_TAG_ECN_EN_DEV0 0 0 STRAP_EXT_VC_COUNT_DN_DEV0 0 0 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 0 0 STRAP_GEN2_COMPLIANCE_DEV0 0 0 STRAP_GEN2_EN_DEV0 0 0 STRAP_GEN3_COMPLIANCE_DEV0 0 0 STRAP_TARGET_LINK_SPEED_DEV0 0 0 STRAP_INTERNAL_ERR_EN_DEV0 0 0 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 0 0 STRAP_L0S_EXIT_LATENCY_DEV0 0 0 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 0 0 STRAP_L1_EXIT_LATENCY_DEV0 0 0 STRAP_DE_EMPHASIS_SEL_DN_DEV0_ 0 0 STRAP_DSN_EN_DN_DEV0_ 1 1 STRAP_E2E_PREFIX_EN_DEV0_ 2 2 STRAP_ECN1P1_EN_DEV0_ 3 3 STRAP_ECRC_CHECK_EN_DEV0_ 4 4 STRAP_ECRC_GEN_EN_DEV0_ 5 5 STRAP_ERR_REPORTING_DIS_DEV0_ 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0_ 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0_ 8 8 STRAP_EXT_VC_COUNT_DN_DEV0_ 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_ 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_ 13 13 STRAP_GEN2_COMPLIANCE_DEV0_ 14 14 STRAP_GEN2_EN_DEV0_ 15 15 STRAP_GEN3_COMPLIANCE_DEV0_ 16 16 STRAP_TARGET_LINK_SPEED_DEV0_ 17 18 STRAP_INTERNAL_ERR_EN_DEV0_ 19 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_ 20 22 STRAP_L0S_EXIT_LATENCY_DEV0_ 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0_ 26 28 STRAP_L1_EXIT_LATENCY_DEV0_ 29 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0 0x403c003 34 0 3 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 0 0 STRAP_LTR_EN_DN_DEV0 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 0 0 STRAP_MSI_EN_DN_DEV0 0 0 STRAP_MSTCPL_TIMEOUT_EN_DEV0 0 0 STRAP_NO_SOFT_RESET_DN_DEV0 0 0 STRAP_OBFF_SUPPORTED_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 0 0 STRAP_PM_SUPPORT_DEV0 0 0 STRAP_PM_SUPPORT_DN_DEV0 0 0 STRAP_ATOMIC_EN_DN_DEV0 0 0 STRAP_VENDOR_ID_BIT_DN_DEV0 0 0 STRAP_PMC_DSI_DN_DEV0 0 0 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_ 0 0 STRAP_LTR_EN_DEV0_ 1 1 STRAP_LTR_EN_DN_DEV0_ 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0_ 3 5 STRAP_MSI_EN_DN_DEV0_ 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0_ 7 7 STRAP_NO_SOFT_RESET_DN_DEV0_ 8 8 STRAP_OBFF_SUPPORTED_DEV0_ 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_ 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_ 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_ 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_ 21 24 STRAP_PM_SUPPORT_DEV0_ 25 26 STRAP_PM_SUPPORT_DN_DEV0_ 27 28 STRAP_ATOMIC_EN_DN_DEV0_ 29 29 STRAP_VENDOR_ID_BIT_DN_DEV0_ 30 30 STRAP_PMC_DSI_DN_DEV0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0 0x403c004 8 0 3 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_ 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_ 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_ 24 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0 0x403c005 34 0 3 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 0 0 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 0 0 STRAP_ATOMIC_64BIT_EN_DN_DEV0 0 0 STRAP_ATOMIC_ROUTING_EN_DEV0 0 0 STRAP_VC_EN_DN_DEV0 0 0 STRAP_TwoVC_EN_DEV0 0 0 STRAP_TwoVC_EN_DN_DEV0 0 0 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 0 0 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 0 0 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 0 0 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 0 0 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 0 0 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 0 0 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 0 0 STRAP_MSI_MAP_EN_DEV0 0 0 STRAP_SSID_EN_DEV0 0 0 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_ 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_ 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0_ 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0_ 18 18 STRAP_VC_EN_DN_DEV0_ 19 19 STRAP_TwoVC_EN_DEV0_ 20 20 STRAP_TwoVC_EN_DN_DEV0_ 21 21 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_ 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_ 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_ 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_ 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_ 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_ 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_ 29 29 STRAP_MSI_MAP_EN_DEV0_ 30 30 STRAP_SSID_EN_DEV0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0 0x403c006 4 0 3 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 0 0 STRAP_CFG_CRS_EN_DEV0_ 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_ 1 1 mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0 0x403c007 12 0 3 STRAP_PORT_NUMBER_DEV0 0 0 STRAP_MAJOR_REV_ID_DN_DEV0 0 0 STRAP_MINOR_REV_ID_DN_DEV0 0 0 STRAP_RP_BUSNUM_DEV0 0 0 STRAP_DN_DEVNUM_DEV0 0 0 STRAP_DN_FUNCID_DEV0 0 0 STRAP_PORT_NUMBER_DEV0_ 0 7 STRAP_MAJOR_REV_ID_DN_DEV0_ 8 11 STRAP_MINOR_REV_ID_DN_DEV0_ 12 15 STRAP_RP_BUSNUM_DEV0_ 16 23 STRAP_DN_DEVNUM_DEV0_ 24 28 STRAP_DN_FUNCID_DEV0_ 29 31 mmRCC_DEV1_PORT_STRAP0 0 0x403c080 20 0 3 STRAP_ARI_EN_DN_DEV1 0 0 STRAP_ACS_EN_DN_DEV1 0 0 STRAP_AER_EN_DN_DEV1 0 0 STRAP_CPL_ABORT_ERR_EN_DN_DEV1 0 0 STRAP_DEVICE_ID_DN_DEV1 0 0 STRAP_INTERRUPT_PIN_DN_DEV1 0 0 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1 0 0 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1 0 0 STRAP_EPF0_DUMMY_EN_DEV1 0 0 STRAP_ARI_EN_DN_DEV1_ 1 1 STRAP_ACS_EN_DN_DEV1_ 2 2 STRAP_AER_EN_DN_DEV1_ 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV1_ 4 4 STRAP_DEVICE_ID_DN_DEV1_ 5 20 STRAP_INTERRUPT_PIN_DN_DEV1_ 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_ 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_ 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_ 28 30 STRAP_EPF0_DUMMY_EN_DEV1_ 31 31 mmRCC_DEV1_PORT_STRAP1 0 0x403c081 4 0 3 STRAP_SUBSYS_ID_DN_DEV1 0 0 STRAP_SUBSYS_VEN_ID_DN_DEV1 0 0 STRAP_SUBSYS_ID_DN_DEV1_ 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV1_ 16 31 mmRCC_DEV1_PORT_STRAP2 0 0x403c082 42 0 3 STRAP_DE_EMPHASIS_SEL_DN_DEV1 0 0 STRAP_DSN_EN_DN_DEV1 0 0 STRAP_E2E_PREFIX_EN_DEV1 0 0 STRAP_ECN1P1_EN_DEV1 0 0 STRAP_ECRC_CHECK_EN_DEV1 0 0 STRAP_ECRC_GEN_EN_DEV1 0 0 STRAP_ERR_REPORTING_DIS_DEV1 0 0 STRAP_EXTENDED_FMT_SUPPORTED_DEV1 0 0 STRAP_EXTENDED_TAG_ECN_EN_DEV1 0 0 STRAP_EXT_VC_COUNT_DN_DEV1 0 0 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1 0 0 STRAP_GEN2_COMPLIANCE_DEV1 0 0 STRAP_GEN2_EN_DEV1 0 0 STRAP_GEN3_COMPLIANCE_DEV1 0 0 STRAP_TARGET_LINK_SPEED_DEV1 0 0 STRAP_INTERNAL_ERR_EN_DEV1 0 0 STRAP_L0S_ACCEPTABLE_LATENCY_DEV1 0 0 STRAP_L0S_EXIT_LATENCY_DEV1 0 0 STRAP_L1_ACCEPTABLE_LATENCY_DEV1 0 0 STRAP_L1_EXIT_LATENCY_DEV1 0 0 STRAP_DE_EMPHASIS_SEL_DN_DEV1_ 0 0 STRAP_DSN_EN_DN_DEV1_ 1 1 STRAP_E2E_PREFIX_EN_DEV1_ 2 2 STRAP_ECN1P1_EN_DEV1_ 3 3 STRAP_ECRC_CHECK_EN_DEV1_ 4 4 STRAP_ECRC_GEN_EN_DEV1_ 5 5 STRAP_ERR_REPORTING_DIS_DEV1_ 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV1_ 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV1_ 8 8 STRAP_EXT_VC_COUNT_DN_DEV1_ 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_ 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_ 13 13 STRAP_GEN2_COMPLIANCE_DEV1_ 14 14 STRAP_GEN2_EN_DEV1_ 15 15 STRAP_GEN3_COMPLIANCE_DEV1_ 16 16 STRAP_TARGET_LINK_SPEED_DEV1_ 17 18 STRAP_INTERNAL_ERR_EN_DEV1_ 19 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_ 20 22 STRAP_L0S_EXIT_LATENCY_DEV1_ 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV1_ 26 28 STRAP_L1_EXIT_LATENCY_DEV1_ 29 31 mmRCC_DEV1_PORT_STRAP3 0 0x403c083 34 0 3 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1 0 0 STRAP_LTR_EN_DEV1 0 0 STRAP_LTR_EN_DN_DEV1 0 0 STRAP_MAX_PAYLOAD_SUPPORT_DEV1 0 0 STRAP_MSI_EN_DN_DEV1 0 0 STRAP_MSTCPL_TIMEOUT_EN_DEV1 0 0 STRAP_NO_SOFT_RESET_DN_DEV1 0 0 STRAP_OBFF_SUPPORTED_DEV1 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1 0 0 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1 0 0 STRAP_PM_SUPPORT_DEV1 0 0 STRAP_PM_SUPPORT_DN_DEV1 0 0 STRAP_ATOMIC_EN_DN_DEV1 0 0 STRAP_VENDOR_ID_BIT_DN_DEV1 0 0 STRAP_PMC_DSI_DN_DEV1 0 0 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_ 0 0 STRAP_LTR_EN_DEV1_ 1 1 STRAP_LTR_EN_DN_DEV1_ 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV1_ 3 5 STRAP_MSI_EN_DN_DEV1_ 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV1_ 7 7 STRAP_NO_SOFT_RESET_DN_DEV1_ 8 8 STRAP_OBFF_SUPPORTED_DEV1_ 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_ 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_ 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_ 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_ 21 24 STRAP_PM_SUPPORT_DEV1_ 25 26 STRAP_PM_SUPPORT_DN_DEV1_ 27 28 STRAP_ATOMIC_EN_DN_DEV1_ 29 29 STRAP_VENDOR_ID_BIT_DN_DEV1_ 30 30 STRAP_PMC_DSI_DN_DEV1_ 31 31 mmRCC_DEV1_PORT_STRAP4 0 0x403c084 8 0 3 STRAP_PWR_BUDGET_DATA_8T0_0_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_1_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_2_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_3_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_ 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_ 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_ 24 31 mmRCC_DEV1_PORT_STRAP5 0 0x403c085 34 0 3 STRAP_PWR_BUDGET_DATA_8T0_4_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_5_DEV1 0 0 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1 0 0 STRAP_ATOMIC_64BIT_EN_DN_DEV1 0 0 STRAP_ATOMIC_ROUTING_EN_DEV1 0 0 STRAP_VC_EN_DN_DEV1 0 0 STRAP_TwoVC_EN_DEV1 0 0 STRAP_TwoVC_EN_DN_DEV1 0 0 STRAP_ACS_SOURCE_VALIDATION_DN_DEV1 0 0 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1 0 0 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1 0 0 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1 0 0 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1 0 0 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1 0 0 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1 0 0 STRAP_MSI_MAP_EN_DEV1 0 0 STRAP_SSID_EN_DEV1 0 0 STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_ 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_ 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_ 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV1_ 17 17 STRAP_ATOMIC_ROUTING_EN_DEV1_ 18 18 STRAP_VC_EN_DN_DEV1_ 19 19 STRAP_TwoVC_EN_DEV1_ 20 20 STRAP_TwoVC_EN_DN_DEV1_ 21 21 STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_ 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_ 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_ 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_ 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_ 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_ 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_ 29 29 STRAP_MSI_MAP_EN_DEV1_ 30 30 STRAP_SSID_EN_DEV1_ 31 31 mmRCC_DEV1_PORT_STRAP6 0 0x403c086 4 0 3 STRAP_CFG_CRS_EN_DEV1 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1 0 0 STRAP_CFG_CRS_EN_DEV1_ 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_ 1 1 mmRCC_DEV1_PORT_STRAP7 0 0x403c087 12 0 3 STRAP_PORT_NUMBER_DEV1 0 0 STRAP_MAJOR_REV_ID_DN_DEV1 0 0 STRAP_MINOR_REV_ID_DN_DEV1 0 0 STRAP_RP_BUSNUM_DEV1 0 0 STRAP_DN_DEVNUM_DEV1 0 0 STRAP_DN_FUNCID_DEV1 0 0 STRAP_PORT_NUMBER_DEV1_ 0 7 STRAP_MAJOR_REV_ID_DN_DEV1_ 8 11 STRAP_MINOR_REV_ID_DN_DEV1_ 12 15 STRAP_RP_BUSNUM_DEV1_ 16 23 STRAP_DN_DEVNUM_DEV1_ 24 28 STRAP_DN_FUNCID_DEV1_ 29 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0 0x403cc00 16 0 3 STRAP_DEVICE_ID_DEV0_F0 0 0 STRAP_MAJOR_REV_ID_DEV0_F0 0 0 STRAP_MINOR_REV_ID_DEV0_F0 0 0 STRAP_ATI_REV_ID_DEV0_F0 0 0 STRAP_FUNC_EN_DEV0_F0 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 0 0 STRAP_D1_SUPPORT_DEV0_F0 0 0 STRAP_D2_SUPPORT_DEV0_F0 0 0 STRAP_DEVICE_ID_DEV0_F0_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F0_ 16 19 STRAP_MINOR_REV_ID_DEV0_F0_ 20 23 STRAP_ATI_REV_ID_DEV0_F0_ 24 27 STRAP_FUNC_EN_DEV0_F0_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_ 29 29 STRAP_D1_SUPPORT_DEV0_F0_ 30 30 STRAP_D2_SUPPORT_DEV0_F0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0 0x403cc01 4 0 3 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 0 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 0 0 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_ 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_ 16 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0 0x403cc02 42 0 3 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 0 0 STRAP_64BAR_DIS_DEV0_F0 0 0 STRAP_NO_SOFT_RESET_DEV0_F0 0 0 STRAP_RESIZE_BAR_EN_DEV0_F0 0 0 STRAP_MAX_PASID_WIDTH_DEV0_F0 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 0 0 STRAP_ARI_EN_DEV0_F0 0 0 STRAP_AER_EN_DEV0_F0 0 0 STRAP_ACS_EN_DEV0_F0 0 0 STRAP_ATS_EN_DEV0_F0 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 0 0 STRAP_DPA_EN_DEV0_F0 0 0 STRAP_DSN_EN_DEV0_F0 0 0 STRAP_VC_EN_DEV0_F0 0 0 STRAP_MSI_MULTI_CAP_DEV0_F0 0 0 STRAP_PAGE_REQ_EN_DEV0_F0 0 0 STRAP_PASID_EN_DEV0_F0 0 0 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 0 0 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 0 0 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 0 0 STRAP_SRIOV_EN_DEV0_F0_ 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0_ 1 5 STRAP_64BAR_DIS_DEV0_F0_ 6 6 STRAP_NO_SOFT_RESET_DEV0_F0_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0_ 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0_ 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_ 14 14 STRAP_ARI_EN_DEV0_F0_ 15 15 STRAP_AER_EN_DEV0_F0_ 16 16 STRAP_ACS_EN_DEV0_F0_ 17 17 STRAP_ATS_EN_DEV0_F0_ 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0_ 20 20 STRAP_DPA_EN_DEV0_F0_ 21 21 STRAP_DSN_EN_DEV0_F0_ 22 22 STRAP_VC_EN_DEV0_F0_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0_ 24 26 STRAP_PAGE_REQ_EN_DEV0_F0_ 27 27 STRAP_PASID_EN_DEV0_F0_ 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_ 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_ 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0 0x403cc03 22 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 0 0 STRAP_SUBSYS_ID_DEV0_F0 0 0 STRAP_MSI_EN_DEV0_F0 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 0 0 STRAP_MSIX_EN_DEV0_F0 0 0 STRAP_MSIX_TABLE_BIR_DEV0_F0 0 0 STRAP_PMC_DSI_DEV0_F0 0 0 STRAP_VENDOR_ID_BIT_DEV0_F0 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_ 0 0 STRAP_PWR_EN_DEV0_F0_ 1 1 STRAP_SUBSYS_ID_DEV0_F0_ 2 17 STRAP_MSI_EN_DEV0_F0_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0_ 19 19 STRAP_MSIX_EN_DEV0_F0_ 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0_ 21 23 STRAP_PMC_DSI_DEV0_F0_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F0_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_ 27 27 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0 0x403cc04 14 0 3 STRAP_MSIX_TABLE_OFFSET_DEV0_F0 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F0 0 0 STRAP_ATOMIC_EN_DEV0_F0 0 0 STRAP_FLR_EN_DEV0_F0 0 0 STRAP_PME_SUPPORT_DEV0_F0 0 0 STRAP_INTERRUPT_PIN_DEV0_F0 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F0 0 0 STRAP_MSIX_TABLE_OFFSET_DEV0_F0_ 0 19 STRAP_ATOMIC_64BIT_EN_DEV0_F0_ 20 20 STRAP_ATOMIC_EN_DEV0_F0_ 21 21 STRAP_FLR_EN_DEV0_F0_ 22 22 STRAP_PME_SUPPORT_DEV0_F0_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F0_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0 0x403cc05 2 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F0_ 0 15 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0 0x403cc08 36 0 3 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 0 0 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 0 STRAP_DOORBELL_BAR_DIS_DEV0_F0 0 0 STRAP_FB_ALWAYS_ON_DEV0_F0 0 0 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 0 0 STRAP_IO_BAR_DIS_DEV0_F0 0 0 STRAP_LFB_ERRMSG_EN_DEV0_F0 0 0 STRAP_MEM_AP_SIZE_DEV0_F0 0 0 STRAP_REG_AP_SIZE_DEV0_F0 0 0 STRAP_ROM_AP_SIZE_DEV0_F0 0 0 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 0 0 STRAP_VF_MEM_AP_SIZE_DEV0_F0 0 0 STRAP_VF_REG_AP_SIZE_DEV0_F0 0 0 STRAP_VGA_DIS_DEV0_F0 0 0 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 0 0 STRAP_VF_REG_PROT_DIS_DEV0_F0 0 0 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 0 0 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 0 0 STRAP_BAR_COMPLIANCE_EN_DEV0_F0_ 0 0 STRAP_DOORBELL_APER_SIZE_DEV0_F0_ 1 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0_ 3 3 STRAP_FB_ALWAYS_ON_DEV0_F0_ 4 4 STRAP_FB_CPL_TYPE_SEL_DEV0_F0_ 5 6 STRAP_IO_BAR_DIS_DEV0_F0_ 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0_ 8 8 STRAP_MEM_AP_SIZE_DEV0_F0_ 9 11 STRAP_REG_AP_SIZE_DEV0_F0_ 12 13 STRAP_ROM_AP_SIZE_DEV0_F0_ 14 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_ 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0_ 19 21 STRAP_VF_REG_AP_SIZE_DEV0_F0_ 22 23 STRAP_VGA_DIS_DEV0_F0_ 24 24 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_ 25 25 STRAP_VF_REG_PROT_DIS_DEV0_F0_ 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0_ 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_ 30 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0 0x403cc09 0 0 3 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0 0x403cc0d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F0 0 0 STRAP_CLASS_CODE_SUB_DEV0_F0 0 0 STRAP_CLASS_CODE_BASE_DEV0_F0 0 0 STRAP_CLASS_CODE_PIF_DEV0_F0_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0_ 16 23 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0 0x403cc80 14 0 3 STRAP_DEVICE_ID_DEV0_F1 0 0 STRAP_MAJOR_REV_ID_DEV0_F1 0 0 STRAP_MINOR_REV_ID_DEV0_F1 0 0 STRAP_FUNC_EN_DEV0_F1 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 0 0 STRAP_D1_SUPPORT_DEV0_F1 0 0 STRAP_D2_SUPPORT_DEV0_F1 0 0 STRAP_DEVICE_ID_DEV0_F1_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F1_ 16 19 STRAP_MINOR_REV_ID_DEV0_F1_ 20 23 STRAP_FUNC_EN_DEV0_F1_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_ 29 29 STRAP_D1_SUPPORT_DEV0_F1_ 30 30 STRAP_D2_SUPPORT_DEV0_F1_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0 0x403cc82 22 0 3 STRAP_NO_SOFT_RESET_DEV0_F1 0 0 STRAP_RESIZE_BAR_EN_DEV0_F1 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 0 0 STRAP_AER_EN_DEV0_F1 0 0 STRAP_ACS_EN_DEV0_F1 0 0 STRAP_ATS_EN_DEV0_F1 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 0 0 STRAP_DPA_EN_DEV0_F1 0 0 STRAP_DSN_EN_DEV0_F1 0 0 STRAP_VC_EN_DEV0_F1 0 0 STRAP_MSI_MULTI_CAP_DEV0_F1 0 0 STRAP_NO_SOFT_RESET_DEV0_F1_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_ 14 14 STRAP_AER_EN_DEV0_F1_ 16 16 STRAP_ACS_EN_DEV0_F1_ 17 17 STRAP_ATS_EN_DEV0_F1_ 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1_ 20 20 STRAP_DPA_EN_DEV0_F1_ 21 21 STRAP_DSN_EN_DEV0_F1_ 22 22 STRAP_VC_EN_DEV0_F1_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1_ 24 26 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0 0x403cc83 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 0 0 STRAP_SUBSYS_ID_DEV0_F1 0 0 STRAP_MSI_EN_DEV0_F1 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 0 0 STRAP_MSIX_EN_DEV0_F1 0 0 STRAP_PMC_DSI_DEV0_F1 0 0 STRAP_VENDOR_ID_BIT_DEV0_F1 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_ 0 0 STRAP_PWR_EN_DEV0_F1_ 1 1 STRAP_SUBSYS_ID_DEV0_F1_ 2 17 STRAP_MSI_EN_DEV0_F1_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1_ 19 19 STRAP_MSIX_EN_DEV0_F1_ 20 20 STRAP_PMC_DSI_DEV0_F1_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F1_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_ 27 27 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0 0x403cc84 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F1 0 0 STRAP_ATOMIC_EN_DEV0_F1 0 0 STRAP_FLR_EN_DEV0_F1 0 0 STRAP_PME_SUPPORT_DEV0_F1 0 0 STRAP_INTERRUPT_PIN_DEV0_F1 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F1 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F1_ 20 20 STRAP_ATOMIC_EN_DEV0_F1_ 21 21 STRAP_FLR_EN_DEV0_F1_ 22 22 STRAP_PME_SUPPORT_DEV0_F1_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F1_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1_ 31 31 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0 0x403cc85 2 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F1_ 0 15 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0 0x403cc86 20 0 3 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER0_64BAR_EN_DEV0_F1 0 0 STRAP_APER0_AP_SIZE_DEV0_F1 0 0 STRAP_APER1_EN_DEV0_F1 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER2_EN_DEV0_F1 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER3_EN_DEV0_F1 0 0 STRAP_APER3_PREFETCHABLE_EN_DEV0_F1 0 0 STRAP_APER0_EN_DEV0_F1_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_ 1 1 STRAP_APER0_64BAR_EN_DEV0_F1_ 2 2 STRAP_APER0_AP_SIZE_DEV0_F1_ 4 6 STRAP_APER1_EN_DEV0_F1_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_ 9 9 STRAP_APER2_EN_DEV0_F1_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_ 17 17 STRAP_APER3_EN_DEV0_F1_ 24 24 STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_ 25 25 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0 0x403cc87 4 0 3 STRAP_ROM_APER_EN_DEV0_F1 0 0 STRAP_ROM_APER_SIZE_DEV0_F1 0 0 STRAP_ROM_APER_EN_DEV0_F1_ 0 0 STRAP_ROM_APER_SIZE_DEV0_F1_ 1 4 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0 0x403cc8a 4 0 3 STRAP_APER1_RESIZE_EN_DEV0_F1 0 0 STRAP_APER1_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER1_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0 0x403cc8b 4 0 3 STRAP_APER2_RESIZE_EN_DEV0_F1 0 0 STRAP_APER2_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER2_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0 0x403cc8c 4 0 3 STRAP_APER3_RESIZE_EN_DEV0_F1 0 0 STRAP_APER3_RESIZE_SUPPORT_DEV0_F1 0 0 STRAP_APER3_RESIZE_EN_DEV0_F1_ 0 0 STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_ 1 20 mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0 0x403cc8d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F1 0 0 STRAP_CLASS_CODE_SUB_DEV0_F1 0 0 STRAP_CLASS_CODE_BASE_DEV0_F1 0 0 STRAP_CLASS_CODE_PIF_DEV0_F1_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1_ 16 23 mmRCC_DEV0_EPF2_STRAP0 0 0x403cd00 14 0 3 STRAP_DEVICE_ID_DEV0_F2 0 0 STRAP_MAJOR_REV_ID_DEV0_F2 0 0 STRAP_MINOR_REV_ID_DEV0_F2 0 0 STRAP_FUNC_EN_DEV0_F2 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2 0 0 STRAP_D1_SUPPORT_DEV0_F2 0 0 STRAP_D2_SUPPORT_DEV0_F2 0 0 STRAP_DEVICE_ID_DEV0_F2_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F2_ 16 19 STRAP_MINOR_REV_ID_DEV0_F2_ 20 23 STRAP_FUNC_EN_DEV0_F2_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_ 29 29 STRAP_D1_SUPPORT_DEV0_F2_ 30 30 STRAP_D2_SUPPORT_DEV0_F2_ 31 31 mmRCC_DEV0_EPF2_STRAP2 0 0x403cd02 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F2 0 0 STRAP_RESIZE_BAR_EN_DEV0_F2 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2 0 0 STRAP_AER_EN_DEV0_F2 0 0 STRAP_ACS_EN_DEV0_F2 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F2 0 0 STRAP_DPA_EN_DEV0_F2 0 0 STRAP_VC_EN_DEV0_F2 0 0 STRAP_MSI_MULTI_CAP_DEV0_F2 0 0 STRAP_NO_SOFT_RESET_DEV0_F2_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F2_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_ 14 14 STRAP_AER_EN_DEV0_F2_ 16 16 STRAP_ACS_EN_DEV0_F2_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F2_ 20 20 STRAP_DPA_EN_DEV0_F2_ 21 21 STRAP_VC_EN_DEV0_F2_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F2_ 24 26 mmRCC_DEV0_EPF2_STRAP3 0 0x403cd03 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2 0 0 STRAP_PWR_EN_DEV0_F2 0 0 STRAP_SUBSYS_ID_DEV0_F2 0 0 STRAP_MSI_EN_DEV0_F2 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F2 0 0 STRAP_MSIX_EN_DEV0_F2 0 0 STRAP_PMC_DSI_DEV0_F2 0 0 STRAP_VENDOR_ID_BIT_DEV0_F2 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_ 0 0 STRAP_PWR_EN_DEV0_F2_ 1 1 STRAP_SUBSYS_ID_DEV0_F2_ 2 17 STRAP_MSI_EN_DEV0_F2_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F2_ 19 19 STRAP_MSIX_EN_DEV0_F2_ 20 20 STRAP_PMC_DSI_DEV0_F2_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F2_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_ 27 27 mmRCC_DEV0_EPF2_STRAP4 0 0x403cd04 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F2 0 0 STRAP_ATOMIC_EN_DEV0_F2 0 0 STRAP_FLR_EN_DEV0_F2 0 0 STRAP_PME_SUPPORT_DEV0_F2 0 0 STRAP_INTERRUPT_PIN_DEV0_F2 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F2 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F2_ 20 20 STRAP_ATOMIC_EN_DEV0_F2_ 21 21 STRAP_FLR_EN_DEV0_F2_ 22 22 STRAP_PME_SUPPORT_DEV0_F2_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F2_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F2_ 31 31 mmRCC_DEV0_EPF2_STRAP5 0 0x403cd05 4 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F2 0 0 STRAP_SATAIDP_EN_DEV0_F2 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F2_ 0 15 STRAP_SATAIDP_EN_DEV0_F2_ 24 24 mmRCC_DEV0_EPF2_STRAP6 0 0x403cd06 10 0 3 STRAP_APER0_EN_DEV0_F2 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F2 0 0 STRAP_APER0_AP_SIZE_DEV0_F2 0 0 STRAP_APER1_EN_DEV0_F2 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F2 0 0 STRAP_APER0_EN_DEV0_F2_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F2_ 4 6 STRAP_APER1_EN_DEV0_F2_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F2_ 9 9 mmRCC_DEV0_EPF2_STRAP13 0 0x403cd0d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F2 0 0 STRAP_CLASS_CODE_SUB_DEV0_F2 0 0 STRAP_CLASS_CODE_BASE_DEV0_F2 0 0 STRAP_CLASS_CODE_PIF_DEV0_F2_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F2_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F2_ 16 23 mmRCC_DEV0_EPF3_STRAP0 0 0x403cd80 14 0 3 STRAP_DEVICE_ID_DEV0_F3 0 0 STRAP_MAJOR_REV_ID_DEV0_F3 0 0 STRAP_MINOR_REV_ID_DEV0_F3 0 0 STRAP_FUNC_EN_DEV0_F3 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3 0 0 STRAP_D1_SUPPORT_DEV0_F3 0 0 STRAP_D2_SUPPORT_DEV0_F3 0 0 STRAP_DEVICE_ID_DEV0_F3_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F3_ 16 19 STRAP_MINOR_REV_ID_DEV0_F3_ 20 23 STRAP_FUNC_EN_DEV0_F3_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_ 29 29 STRAP_D1_SUPPORT_DEV0_F3_ 30 30 STRAP_D2_SUPPORT_DEV0_F3_ 31 31 mmRCC_DEV0_EPF3_STRAP2 0 0x403cd82 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F3 0 0 STRAP_RESIZE_BAR_EN_DEV0_F3 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3 0 0 STRAP_AER_EN_DEV0_F3 0 0 STRAP_ACS_EN_DEV0_F3 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F3 0 0 STRAP_DPA_EN_DEV0_F3 0 0 STRAP_VC_EN_DEV0_F3 0 0 STRAP_MSI_MULTI_CAP_DEV0_F3 0 0 STRAP_NO_SOFT_RESET_DEV0_F3_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F3_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_ 14 14 STRAP_AER_EN_DEV0_F3_ 16 16 STRAP_ACS_EN_DEV0_F3_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F3_ 20 20 STRAP_DPA_EN_DEV0_F3_ 21 21 STRAP_VC_EN_DEV0_F3_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F3_ 24 26 mmRCC_DEV0_EPF3_STRAP3 0 0x403cd83 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3 0 0 STRAP_PWR_EN_DEV0_F3 0 0 STRAP_SUBSYS_ID_DEV0_F3 0 0 STRAP_MSI_EN_DEV0_F3 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F3 0 0 STRAP_MSIX_EN_DEV0_F3 0 0 STRAP_PMC_DSI_DEV0_F3 0 0 STRAP_VENDOR_ID_BIT_DEV0_F3 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_ 0 0 STRAP_PWR_EN_DEV0_F3_ 1 1 STRAP_SUBSYS_ID_DEV0_F3_ 2 17 STRAP_MSI_EN_DEV0_F3_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F3_ 19 19 STRAP_MSIX_EN_DEV0_F3_ 20 20 STRAP_PMC_DSI_DEV0_F3_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F3_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_ 27 27 mmRCC_DEV0_EPF3_STRAP4 0 0x403cd84 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F3 0 0 STRAP_ATOMIC_EN_DEV0_F3 0 0 STRAP_FLR_EN_DEV0_F3 0 0 STRAP_PME_SUPPORT_DEV0_F3 0 0 STRAP_INTERRUPT_PIN_DEV0_F3 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F3 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F3_ 20 20 STRAP_ATOMIC_EN_DEV0_F3_ 21 21 STRAP_FLR_EN_DEV0_F3_ 22 22 STRAP_PME_SUPPORT_DEV0_F3_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F3_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F3_ 31 31 mmRCC_DEV0_EPF3_STRAP5 0 0x403cd85 6 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F3 0 0 STRAP_USB_DBESEL_DEV0_F3 0 0 STRAP_USB_DBESELD_DEV0_F3 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F3_ 0 15 STRAP_USB_DBESEL_DEV0_F3_ 16 19 STRAP_USB_DBESELD_DEV0_F3_ 20 23 mmRCC_DEV0_EPF3_STRAP6 0 0x403cd86 6 0 3 STRAP_APER0_EN_DEV0_F3 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F3 0 0 STRAP_APER0_AP_SIZE_DEV0_F3 0 0 STRAP_APER0_EN_DEV0_F3_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F3_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F3_ 4 6 mmRCC_DEV0_EPF3_STRAP13 0 0x403cd8d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F3 0 0 STRAP_CLASS_CODE_SUB_DEV0_F3 0 0 STRAP_CLASS_CODE_BASE_DEV0_F3 0 0 STRAP_CLASS_CODE_PIF_DEV0_F3_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F3_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F3_ 16 23 mmRCC_DEV0_EPF4_STRAP0 0 0x403ce00 14 0 3 STRAP_DEVICE_ID_DEV0_F4 0 0 STRAP_MAJOR_REV_ID_DEV0_F4 0 0 STRAP_MINOR_REV_ID_DEV0_F4 0 0 STRAP_FUNC_EN_DEV0_F4 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4 0 0 STRAP_D1_SUPPORT_DEV0_F4 0 0 STRAP_D2_SUPPORT_DEV0_F4 0 0 STRAP_DEVICE_ID_DEV0_F4_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F4_ 16 19 STRAP_MINOR_REV_ID_DEV0_F4_ 20 23 STRAP_FUNC_EN_DEV0_F4_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_ 29 29 STRAP_D1_SUPPORT_DEV0_F4_ 30 30 STRAP_D2_SUPPORT_DEV0_F4_ 31 31 mmRCC_DEV0_EPF4_STRAP2 0 0x403ce02 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F4 0 0 STRAP_RESIZE_BAR_EN_DEV0_F4 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4 0 0 STRAP_AER_EN_DEV0_F4 0 0 STRAP_ACS_EN_DEV0_F4 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F4 0 0 STRAP_DPA_EN_DEV0_F4 0 0 STRAP_VC_EN_DEV0_F4 0 0 STRAP_MSI_MULTI_CAP_DEV0_F4 0 0 STRAP_NO_SOFT_RESET_DEV0_F4_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F4_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_ 14 14 STRAP_AER_EN_DEV0_F4_ 16 16 STRAP_ACS_EN_DEV0_F4_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F4_ 20 20 STRAP_DPA_EN_DEV0_F4_ 21 21 STRAP_VC_EN_DEV0_F4_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F4_ 24 26 mmRCC_DEV0_EPF4_STRAP3 0 0x403ce03 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4 0 0 STRAP_PWR_EN_DEV0_F4 0 0 STRAP_SUBSYS_ID_DEV0_F4 0 0 STRAP_MSI_EN_DEV0_F4 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F4 0 0 STRAP_MSIX_EN_DEV0_F4 0 0 STRAP_PMC_DSI_DEV0_F4 0 0 STRAP_VENDOR_ID_BIT_DEV0_F4 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_ 0 0 STRAP_PWR_EN_DEV0_F4_ 1 1 STRAP_SUBSYS_ID_DEV0_F4_ 2 17 STRAP_MSI_EN_DEV0_F4_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F4_ 19 19 STRAP_MSIX_EN_DEV0_F4_ 20 20 STRAP_PMC_DSI_DEV0_F4_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F4_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_ 27 27 mmRCC_DEV0_EPF4_STRAP4 0 0x403ce04 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F4 0 0 STRAP_ATOMIC_EN_DEV0_F4 0 0 STRAP_FLR_EN_DEV0_F4 0 0 STRAP_PME_SUPPORT_DEV0_F4 0 0 STRAP_INTERRUPT_PIN_DEV0_F4 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F4 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F4_ 20 20 STRAP_ATOMIC_EN_DEV0_F4_ 21 21 STRAP_FLR_EN_DEV0_F4_ 22 22 STRAP_PME_SUPPORT_DEV0_F4_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F4_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F4_ 31 31 mmRCC_DEV0_EPF4_STRAP5 0 0x403ce05 6 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F4 0 0 STRAP_USB_DBESEL_DEV0_F4 0 0 STRAP_USB_DBESELD_DEV0_F4 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F4_ 0 15 STRAP_USB_DBESEL_DEV0_F4_ 16 19 STRAP_USB_DBESELD_DEV0_F4_ 20 23 mmRCC_DEV0_EPF4_STRAP6 0 0x403ce06 14 0 3 STRAP_APER0_EN_DEV0_F4 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F4 0 0 STRAP_APER0_AP_SIZE_DEV0_F4 0 0 STRAP_APER1_EN_DEV0_F4 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F4 0 0 STRAP_APER2_EN_DEV0_F4 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F4 0 0 STRAP_APER0_EN_DEV0_F4_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F4_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F4_ 4 6 STRAP_APER1_EN_DEV0_F4_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F4_ 9 9 STRAP_APER2_EN_DEV0_F4_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F4_ 17 17 mmRCC_DEV0_EPF4_STRAP13 0 0x403ce0d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F4 0 0 STRAP_CLASS_CODE_SUB_DEV0_F4 0 0 STRAP_CLASS_CODE_BASE_DEV0_F4 0 0 STRAP_CLASS_CODE_PIF_DEV0_F4_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F4_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F4_ 16 23 mmRCC_DEV0_EPF5_STRAP0 0 0x403ce80 14 0 3 STRAP_DEVICE_ID_DEV0_F5 0 0 STRAP_MAJOR_REV_ID_DEV0_F5 0 0 STRAP_MINOR_REV_ID_DEV0_F5 0 0 STRAP_FUNC_EN_DEV0_F5 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5 0 0 STRAP_D1_SUPPORT_DEV0_F5 0 0 STRAP_D2_SUPPORT_DEV0_F5 0 0 STRAP_DEVICE_ID_DEV0_F5_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F5_ 16 19 STRAP_MINOR_REV_ID_DEV0_F5_ 20 23 STRAP_FUNC_EN_DEV0_F5_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_ 29 29 STRAP_D1_SUPPORT_DEV0_F5_ 30 30 STRAP_D2_SUPPORT_DEV0_F5_ 31 31 mmRCC_DEV0_EPF5_STRAP2 0 0x403ce82 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F5 0 0 STRAP_RESIZE_BAR_EN_DEV0_F5 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5 0 0 STRAP_AER_EN_DEV0_F5 0 0 STRAP_ACS_EN_DEV0_F5 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F5 0 0 STRAP_DPA_EN_DEV0_F5 0 0 STRAP_VC_EN_DEV0_F5 0 0 STRAP_MSI_MULTI_CAP_DEV0_F5 0 0 STRAP_NO_SOFT_RESET_DEV0_F5_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F5_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_ 14 14 STRAP_AER_EN_DEV0_F5_ 16 16 STRAP_ACS_EN_DEV0_F5_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F5_ 20 20 STRAP_DPA_EN_DEV0_F5_ 21 21 STRAP_VC_EN_DEV0_F5_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F5_ 24 26 mmRCC_DEV0_EPF5_STRAP3 0 0x403ce83 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5 0 0 STRAP_PWR_EN_DEV0_F5 0 0 STRAP_SUBSYS_ID_DEV0_F5 0 0 STRAP_MSI_EN_DEV0_F5 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F5 0 0 STRAP_MSIX_EN_DEV0_F5 0 0 STRAP_PMC_DSI_DEV0_F5 0 0 STRAP_VENDOR_ID_BIT_DEV0_F5 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_ 0 0 STRAP_PWR_EN_DEV0_F5_ 1 1 STRAP_SUBSYS_ID_DEV0_F5_ 2 17 STRAP_MSI_EN_DEV0_F5_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F5_ 19 19 STRAP_MSIX_EN_DEV0_F5_ 20 20 STRAP_PMC_DSI_DEV0_F5_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F5_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_ 27 27 mmRCC_DEV0_EPF5_STRAP4 0 0x403ce84 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F5 0 0 STRAP_ATOMIC_EN_DEV0_F5 0 0 STRAP_FLR_EN_DEV0_F5 0 0 STRAP_PME_SUPPORT_DEV0_F5 0 0 STRAP_INTERRUPT_PIN_DEV0_F5 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F5 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F5_ 20 20 STRAP_ATOMIC_EN_DEV0_F5_ 21 21 STRAP_FLR_EN_DEV0_F5_ 22 22 STRAP_PME_SUPPORT_DEV0_F5_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F5_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F5_ 31 31 mmRCC_DEV0_EPF5_STRAP5 0 0x403ce85 2 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F5 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F5_ 0 15 mmRCC_DEV0_EPF5_STRAP6 0 0x403ce86 14 0 3 STRAP_APER0_EN_DEV0_F5 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F5 0 0 STRAP_APER0_AP_SIZE_DEV0_F5 0 0 STRAP_APER1_EN_DEV0_F5 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F5 0 0 STRAP_APER2_EN_DEV0_F5 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F5 0 0 STRAP_APER0_EN_DEV0_F5_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F5_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F5_ 4 6 STRAP_APER1_EN_DEV0_F5_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F5_ 9 9 STRAP_APER2_EN_DEV0_F5_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F5_ 17 17 mmRCC_DEV0_EPF5_STRAP13 0 0x403ce8d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F5 0 0 STRAP_CLASS_CODE_SUB_DEV0_F5 0 0 STRAP_CLASS_CODE_BASE_DEV0_F5 0 0 STRAP_CLASS_CODE_PIF_DEV0_F5_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F5_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F5_ 16 23 mmRCC_DEV0_EPF6_STRAP0 0 0x403cf00 14 0 3 STRAP_DEVICE_ID_DEV0_F6 0 0 STRAP_MAJOR_REV_ID_DEV0_F6 0 0 STRAP_MINOR_REV_ID_DEV0_F6 0 0 STRAP_FUNC_EN_DEV0_F6 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6 0 0 STRAP_D1_SUPPORT_DEV0_F6 0 0 STRAP_D2_SUPPORT_DEV0_F6 0 0 STRAP_DEVICE_ID_DEV0_F6_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F6_ 16 19 STRAP_MINOR_REV_ID_DEV0_F6_ 20 23 STRAP_FUNC_EN_DEV0_F6_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_ 29 29 STRAP_D1_SUPPORT_DEV0_F6_ 30 30 STRAP_D2_SUPPORT_DEV0_F6_ 31 31 mmRCC_DEV0_EPF6_STRAP2 0 0x403cf02 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F6 0 0 STRAP_RESIZE_BAR_EN_DEV0_F6 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6 0 0 STRAP_AER_EN_DEV0_F6 0 0 STRAP_ACS_EN_DEV0_F6 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F6 0 0 STRAP_DPA_EN_DEV0_F6 0 0 STRAP_VC_EN_DEV0_F6 0 0 STRAP_MSI_MULTI_CAP_DEV0_F6 0 0 STRAP_NO_SOFT_RESET_DEV0_F6_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F6_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_ 14 14 STRAP_AER_EN_DEV0_F6_ 16 16 STRAP_ACS_EN_DEV0_F6_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F6_ 20 20 STRAP_DPA_EN_DEV0_F6_ 21 21 STRAP_VC_EN_DEV0_F6_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F6_ 24 26 mmRCC_DEV0_EPF6_STRAP3 0 0x403cf03 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6 0 0 STRAP_PWR_EN_DEV0_F6 0 0 STRAP_SUBSYS_ID_DEV0_F6 0 0 STRAP_MSI_EN_DEV0_F6 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F6 0 0 STRAP_MSIX_EN_DEV0_F6 0 0 STRAP_PMC_DSI_DEV0_F6 0 0 STRAP_VENDOR_ID_BIT_DEV0_F6 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_ 0 0 STRAP_PWR_EN_DEV0_F6_ 1 1 STRAP_SUBSYS_ID_DEV0_F6_ 2 17 STRAP_MSI_EN_DEV0_F6_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F6_ 19 19 STRAP_MSIX_EN_DEV0_F6_ 20 20 STRAP_PMC_DSI_DEV0_F6_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F6_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_ 27 27 mmRCC_DEV0_EPF6_STRAP4 0 0x403cf04 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F6 0 0 STRAP_ATOMIC_EN_DEV0_F6 0 0 STRAP_FLR_EN_DEV0_F6 0 0 STRAP_PME_SUPPORT_DEV0_F6 0 0 STRAP_INTERRUPT_PIN_DEV0_F6 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F6 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F6_ 20 20 STRAP_ATOMIC_EN_DEV0_F6_ 21 21 STRAP_FLR_EN_DEV0_F6_ 22 22 STRAP_PME_SUPPORT_DEV0_F6_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F6_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F6_ 31 31 mmRCC_DEV0_EPF6_STRAP5 0 0x403cf05 2 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F6 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F6_ 0 15 mmRCC_DEV0_EPF6_STRAP6 0 0x403cf06 14 0 3 STRAP_APER0_EN_DEV0_F6 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F6 0 0 STRAP_APER0_AP_SIZE_DEV0_F6 0 0 STRAP_APER1_EN_DEV0_F6 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F6 0 0 STRAP_APER2_EN_DEV0_F6 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F6 0 0 STRAP_APER0_EN_DEV0_F6_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F6_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F6_ 4 6 STRAP_APER1_EN_DEV0_F6_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F6_ 9 9 STRAP_APER2_EN_DEV0_F6_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F6_ 17 17 mmRCC_DEV0_EPF6_STRAP13 0 0x403cf0d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F6 0 0 STRAP_CLASS_CODE_SUB_DEV0_F6 0 0 STRAP_CLASS_CODE_BASE_DEV0_F6 0 0 STRAP_CLASS_CODE_PIF_DEV0_F6_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F6_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F6_ 16 23 mmRCC_DEV0_EPF7_STRAP0 0 0x403cf80 14 0 3 STRAP_DEVICE_ID_DEV0_F7 0 0 STRAP_MAJOR_REV_ID_DEV0_F7 0 0 STRAP_MINOR_REV_ID_DEV0_F7 0 0 STRAP_FUNC_EN_DEV0_F7 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7 0 0 STRAP_D1_SUPPORT_DEV0_F7 0 0 STRAP_D2_SUPPORT_DEV0_F7 0 0 STRAP_DEVICE_ID_DEV0_F7_ 0 15 STRAP_MAJOR_REV_ID_DEV0_F7_ 16 19 STRAP_MINOR_REV_ID_DEV0_F7_ 20 23 STRAP_FUNC_EN_DEV0_F7_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7_ 29 29 STRAP_D1_SUPPORT_DEV0_F7_ 30 30 STRAP_D2_SUPPORT_DEV0_F7_ 31 31 mmRCC_DEV0_EPF7_STRAP2 0 0x403cf82 18 0 3 STRAP_NO_SOFT_RESET_DEV0_F7 0 0 STRAP_RESIZE_BAR_EN_DEV0_F7 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7 0 0 STRAP_AER_EN_DEV0_F7 0 0 STRAP_ACS_EN_DEV0_F7 0 0 STRAP_CPL_ABORT_ERR_EN_DEV0_F7 0 0 STRAP_DPA_EN_DEV0_F7 0 0 STRAP_VC_EN_DEV0_F7 0 0 STRAP_MSI_MULTI_CAP_DEV0_F7 0 0 STRAP_NO_SOFT_RESET_DEV0_F7_ 7 7 STRAP_RESIZE_BAR_EN_DEV0_F7_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7_ 14 14 STRAP_AER_EN_DEV0_F7_ 16 16 STRAP_ACS_EN_DEV0_F7_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F7_ 20 20 STRAP_DPA_EN_DEV0_F7_ 21 21 STRAP_VC_EN_DEV0_F7_ 23 23 STRAP_MSI_MULTI_CAP_DEV0_F7_ 24 26 mmRCC_DEV0_EPF7_STRAP3 0 0x403cf83 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7 0 0 STRAP_PWR_EN_DEV0_F7 0 0 STRAP_SUBSYS_ID_DEV0_F7 0 0 STRAP_MSI_EN_DEV0_F7 0 0 STRAP_MSI_CLR_PENDING_EN_DEV0_F7 0 0 STRAP_MSIX_EN_DEV0_F7 0 0 STRAP_PMC_DSI_DEV0_F7 0 0 STRAP_VENDOR_ID_BIT_DEV0_F7 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7_ 0 0 STRAP_PWR_EN_DEV0_F7_ 1 1 STRAP_SUBSYS_ID_DEV0_F7_ 2 17 STRAP_MSI_EN_DEV0_F7_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F7_ 19 19 STRAP_MSIX_EN_DEV0_F7_ 20 20 STRAP_PMC_DSI_DEV0_F7_ 24 24 STRAP_VENDOR_ID_BIT_DEV0_F7_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7_ 27 27 mmRCC_DEV0_EPF7_STRAP4 0 0x403cf84 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV0_F7 0 0 STRAP_ATOMIC_EN_DEV0_F7 0 0 STRAP_FLR_EN_DEV0_F7 0 0 STRAP_PME_SUPPORT_DEV0_F7 0 0 STRAP_INTERRUPT_PIN_DEV0_F7 0 0 STRAP_AUXPWR_SUPPORT_DEV0_F7 0 0 STRAP_ATOMIC_64BIT_EN_DEV0_F7_ 20 20 STRAP_ATOMIC_EN_DEV0_F7_ 21 21 STRAP_FLR_EN_DEV0_F7_ 22 22 STRAP_PME_SUPPORT_DEV0_F7_ 23 27 STRAP_INTERRUPT_PIN_DEV0_F7_ 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F7_ 31 31 mmRCC_DEV0_EPF7_STRAP5 0 0x403cf85 2 0 3 STRAP_SUBSYS_VEN_ID_DEV0_F7 0 0 STRAP_SUBSYS_VEN_ID_DEV0_F7_ 0 15 mmRCC_DEV0_EPF7_STRAP6 0 0x403cf86 14 0 3 STRAP_APER0_EN_DEV0_F7 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F7 0 0 STRAP_APER0_AP_SIZE_DEV0_F7 0 0 STRAP_APER1_EN_DEV0_F7 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV0_F7 0 0 STRAP_APER2_EN_DEV0_F7 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV0_F7 0 0 STRAP_APER0_EN_DEV0_F7_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F7_ 1 1 STRAP_APER0_AP_SIZE_DEV0_F7_ 4 6 STRAP_APER1_EN_DEV0_F7_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F7_ 9 9 STRAP_APER2_EN_DEV0_F7_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV0_F7_ 17 17 mmRCC_DEV0_EPF7_STRAP13 0 0x403cf8d 6 0 3 STRAP_CLASS_CODE_PIF_DEV0_F7 0 0 STRAP_CLASS_CODE_SUB_DEV0_F7 0 0 STRAP_CLASS_CODE_BASE_DEV0_F7 0 0 STRAP_CLASS_CODE_PIF_DEV0_F7_ 0 7 STRAP_CLASS_CODE_SUB_DEV0_F7_ 8 15 STRAP_CLASS_CODE_BASE_DEV0_F7_ 16 23 mmRCC_DEV1_EPF0_STRAP0 0 0x403d000 14 0 3 STRAP_DEVICE_ID_DEV1_F0 0 0 STRAP_MAJOR_REV_ID_DEV1_F0 0 0 STRAP_MINOR_REV_ID_DEV1_F0 0 0 STRAP_FUNC_EN_DEV1_F0 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0 0 0 STRAP_D1_SUPPORT_DEV1_F0 0 0 STRAP_D2_SUPPORT_DEV1_F0 0 0 STRAP_DEVICE_ID_DEV1_F0_ 0 15 STRAP_MAJOR_REV_ID_DEV1_F0_ 16 19 STRAP_MINOR_REV_ID_DEV1_F0_ 20 23 STRAP_FUNC_EN_DEV1_F0_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_ 29 29 STRAP_D1_SUPPORT_DEV1_F0_ 30 30 STRAP_D2_SUPPORT_DEV1_F0_ 31 31 mmRCC_DEV1_EPF0_STRAP2 0 0x403d002 20 0 3 STRAP_NO_SOFT_RESET_DEV1_F0 0 0 STRAP_RESIZE_BAR_EN_DEV1_F0 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0 0 0 STRAP_ARI_EN_DEV1_F0 0 0 STRAP_AER_EN_DEV1_F0 0 0 STRAP_ACS_EN_DEV1_F0 0 0 STRAP_CPL_ABORT_ERR_EN_DEV1_F0 0 0 STRAP_DPA_EN_DEV1_F0 0 0 STRAP_VC_EN_DEV1_F0 0 0 STRAP_MSI_MULTI_CAP_DEV1_F0 0 0 STRAP_NO_SOFT_RESET_DEV1_F0_ 7 7 STRAP_RESIZE_BAR_EN_DEV1_F0_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_ 14 14 STRAP_ARI_EN_DEV1_F0_ 15 15 STRAP_AER_EN_DEV1_F0_ 16 16 STRAP_ACS_EN_DEV1_F0_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV1_F0_ 20 20 STRAP_DPA_EN_DEV1_F0_ 21 21 STRAP_VC_EN_DEV1_F0_ 23 23 STRAP_MSI_MULTI_CAP_DEV1_F0_ 24 26 mmRCC_DEV1_EPF0_STRAP3 0 0x403d003 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0 0 0 STRAP_PWR_EN_DEV1_F0 0 0 STRAP_SUBSYS_ID_DEV1_F0 0 0 STRAP_MSI_EN_DEV1_F0 0 0 STRAP_MSI_CLR_PENDING_EN_DEV1_F0 0 0 STRAP_MSIX_EN_DEV1_F0 0 0 STRAP_PMC_DSI_DEV1_F0 0 0 STRAP_VENDOR_ID_BIT_DEV1_F0 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_ 0 0 STRAP_PWR_EN_DEV1_F0_ 1 1 STRAP_SUBSYS_ID_DEV1_F0_ 2 17 STRAP_MSI_EN_DEV1_F0_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV1_F0_ 19 19 STRAP_MSIX_EN_DEV1_F0_ 20 20 STRAP_PMC_DSI_DEV1_F0_ 24 24 STRAP_VENDOR_ID_BIT_DEV1_F0_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_ 27 27 mmRCC_DEV1_EPF0_STRAP4 0 0x403d004 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV1_F0 0 0 STRAP_ATOMIC_EN_DEV1_F0 0 0 STRAP_FLR_EN_DEV1_F0 0 0 STRAP_PME_SUPPORT_DEV1_F0 0 0 STRAP_INTERRUPT_PIN_DEV1_F0 0 0 STRAP_AUXPWR_SUPPORT_DEV1_F0 0 0 STRAP_ATOMIC_64BIT_EN_DEV1_F0_ 20 20 STRAP_ATOMIC_EN_DEV1_F0_ 21 21 STRAP_FLR_EN_DEV1_F0_ 22 22 STRAP_PME_SUPPORT_DEV1_F0_ 23 27 STRAP_INTERRUPT_PIN_DEV1_F0_ 28 30 STRAP_AUXPWR_SUPPORT_DEV1_F0_ 31 31 mmRCC_DEV1_EPF0_STRAP5 0 0x403d005 4 0 3 STRAP_SUBSYS_VEN_ID_DEV1_F0 0 0 STRAP_SATAIDP_EN_DEV1_F0 0 0 STRAP_SUBSYS_VEN_ID_DEV1_F0_ 0 15 STRAP_SATAIDP_EN_DEV1_F0_ 24 24 mmRCC_DEV1_EPF0_STRAP6 0 0x403d006 6 0 3 STRAP_APER0_EN_DEV1_F0 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F0 0 0 STRAP_APER0_AP_SIZE_DEV1_F0 0 0 STRAP_APER0_EN_DEV1_F0_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F0_ 1 1 STRAP_APER0_AP_SIZE_DEV1_F0_ 4 6 mmRCC_DEV1_EPF0_STRAP13 0 0x403d00d 6 0 3 STRAP_CLASS_CODE_PIF_DEV1_F0 0 0 STRAP_CLASS_CODE_SUB_DEV1_F0 0 0 STRAP_CLASS_CODE_BASE_DEV1_F0 0 0 STRAP_CLASS_CODE_PIF_DEV1_F0_ 0 7 STRAP_CLASS_CODE_SUB_DEV1_F0_ 8 15 STRAP_CLASS_CODE_BASE_DEV1_F0_ 16 23 mmRCC_DEV1_EPF1_STRAP0 0 0x403d080 14 0 3 STRAP_DEVICE_ID_DEV1_F1 0 0 STRAP_MAJOR_REV_ID_DEV1_F1 0 0 STRAP_MINOR_REV_ID_DEV1_F1 0 0 STRAP_FUNC_EN_DEV1_F1 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1 0 0 STRAP_D1_SUPPORT_DEV1_F1 0 0 STRAP_D2_SUPPORT_DEV1_F1 0 0 STRAP_DEVICE_ID_DEV1_F1_ 0 15 STRAP_MAJOR_REV_ID_DEV1_F1_ 16 19 STRAP_MINOR_REV_ID_DEV1_F1_ 20 23 STRAP_FUNC_EN_DEV1_F1_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1_ 29 29 STRAP_D1_SUPPORT_DEV1_F1_ 30 30 STRAP_D2_SUPPORT_DEV1_F1_ 31 31 mmRCC_DEV1_EPF1_STRAP2 0 0x403d082 18 0 3 STRAP_NO_SOFT_RESET_DEV1_F1 0 0 STRAP_RESIZE_BAR_EN_DEV1_F1 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1 0 0 STRAP_AER_EN_DEV1_F1 0 0 STRAP_ACS_EN_DEV1_F1 0 0 STRAP_CPL_ABORT_ERR_EN_DEV1_F1 0 0 STRAP_DPA_EN_DEV1_F1 0 0 STRAP_VC_EN_DEV1_F1 0 0 STRAP_MSI_MULTI_CAP_DEV1_F1 0 0 STRAP_NO_SOFT_RESET_DEV1_F1_ 7 7 STRAP_RESIZE_BAR_EN_DEV1_F1_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1_ 14 14 STRAP_AER_EN_DEV1_F1_ 16 16 STRAP_ACS_EN_DEV1_F1_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV1_F1_ 20 20 STRAP_DPA_EN_DEV1_F1_ 21 21 STRAP_VC_EN_DEV1_F1_ 23 23 STRAP_MSI_MULTI_CAP_DEV1_F1_ 24 26 mmRCC_DEV1_EPF1_STRAP3 0 0x403d083 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1 0 0 STRAP_PWR_EN_DEV1_F1 0 0 STRAP_SUBSYS_ID_DEV1_F1 0 0 STRAP_MSI_EN_DEV1_F1 0 0 STRAP_MSI_CLR_PENDING_EN_DEV1_F1 0 0 STRAP_MSIX_EN_DEV1_F1 0 0 STRAP_PMC_DSI_DEV1_F1 0 0 STRAP_VENDOR_ID_BIT_DEV1_F1 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1_ 0 0 STRAP_PWR_EN_DEV1_F1_ 1 1 STRAP_SUBSYS_ID_DEV1_F1_ 2 17 STRAP_MSI_EN_DEV1_F1_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV1_F1_ 19 19 STRAP_MSIX_EN_DEV1_F1_ 20 20 STRAP_PMC_DSI_DEV1_F1_ 24 24 STRAP_VENDOR_ID_BIT_DEV1_F1_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1_ 27 27 mmRCC_DEV1_EPF1_STRAP4 0 0x403d084 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV1_F1 0 0 STRAP_ATOMIC_EN_DEV1_F1 0 0 STRAP_FLR_EN_DEV1_F1 0 0 STRAP_PME_SUPPORT_DEV1_F1 0 0 STRAP_INTERRUPT_PIN_DEV1_F1 0 0 STRAP_AUXPWR_SUPPORT_DEV1_F1 0 0 STRAP_ATOMIC_64BIT_EN_DEV1_F1_ 20 20 STRAP_ATOMIC_EN_DEV1_F1_ 21 21 STRAP_FLR_EN_DEV1_F1_ 22 22 STRAP_PME_SUPPORT_DEV1_F1_ 23 27 STRAP_INTERRUPT_PIN_DEV1_F1_ 28 30 STRAP_AUXPWR_SUPPORT_DEV1_F1_ 31 31 mmRCC_DEV1_EPF1_STRAP5 0 0x403d085 2 0 3 STRAP_SUBSYS_VEN_ID_DEV1_F1 0 0 STRAP_SUBSYS_VEN_ID_DEV1_F1_ 0 15 mmRCC_DEV1_EPF1_STRAP6 0 0x403d086 18 0 3 STRAP_APER0_EN_DEV1_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F1 0 0 STRAP_APER0_AP_SIZE_DEV1_F1 0 0 STRAP_APER1_EN_DEV1_F1 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV1_F1 0 0 STRAP_APER2_EN_DEV1_F1 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV1_F1 0 0 STRAP_APER3_EN_DEV1_F1 0 0 STRAP_APER3_PREFETCHABLE_EN_DEV1_F1 0 0 STRAP_APER0_EN_DEV1_F1_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F1_ 1 1 STRAP_APER0_AP_SIZE_DEV1_F1_ 4 6 STRAP_APER1_EN_DEV1_F1_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV1_F1_ 9 9 STRAP_APER2_EN_DEV1_F1_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV1_F1_ 17 17 STRAP_APER3_EN_DEV1_F1_ 24 24 STRAP_APER3_PREFETCHABLE_EN_DEV1_F1_ 25 25 mmRCC_DEV1_EPF1_STRAP13 0 0x403d08d 6 0 3 STRAP_CLASS_CODE_PIF_DEV1_F1 0 0 STRAP_CLASS_CODE_SUB_DEV1_F1 0 0 STRAP_CLASS_CODE_BASE_DEV1_F1 0 0 STRAP_CLASS_CODE_PIF_DEV1_F1_ 0 7 STRAP_CLASS_CODE_SUB_DEV1_F1_ 8 15 STRAP_CLASS_CODE_BASE_DEV1_F1_ 16 23 mmRCC_DEV1_EPF2_STRAP0 0 0x403d100 14 0 3 STRAP_DEVICE_ID_DEV1_F2 0 0 STRAP_MAJOR_REV_ID_DEV1_F2 0 0 STRAP_MINOR_REV_ID_DEV1_F2 0 0 STRAP_FUNC_EN_DEV1_F2 0 0 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2 0 0 STRAP_D1_SUPPORT_DEV1_F2 0 0 STRAP_D2_SUPPORT_DEV1_F2 0 0 STRAP_DEVICE_ID_DEV1_F2_ 0 15 STRAP_MAJOR_REV_ID_DEV1_F2_ 16 19 STRAP_MINOR_REV_ID_DEV1_F2_ 20 23 STRAP_FUNC_EN_DEV1_F2_ 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2_ 29 29 STRAP_D1_SUPPORT_DEV1_F2_ 30 30 STRAP_D2_SUPPORT_DEV1_F2_ 31 31 mmRCC_DEV1_EPF2_STRAP2 0 0x403d102 18 0 3 STRAP_NO_SOFT_RESET_DEV1_F2 0 0 STRAP_RESIZE_BAR_EN_DEV1_F2 0 0 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2 0 0 STRAP_AER_EN_DEV1_F2 0 0 STRAP_ACS_EN_DEV1_F2 0 0 STRAP_CPL_ABORT_ERR_EN_DEV1_F2 0 0 STRAP_DPA_EN_DEV1_F2 0 0 STRAP_VC_EN_DEV1_F2 0 0 STRAP_MSI_MULTI_CAP_DEV1_F2 0 0 STRAP_NO_SOFT_RESET_DEV1_F2_ 7 7 STRAP_RESIZE_BAR_EN_DEV1_F2_ 8 8 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2_ 14 14 STRAP_AER_EN_DEV1_F2_ 16 16 STRAP_ACS_EN_DEV1_F2_ 17 17 STRAP_CPL_ABORT_ERR_EN_DEV1_F2_ 20 20 STRAP_DPA_EN_DEV1_F2_ 21 21 STRAP_VC_EN_DEV1_F2_ 23 23 STRAP_MSI_MULTI_CAP_DEV1_F2_ 24 26 mmRCC_DEV1_EPF2_STRAP3 0 0x403d103 20 0 3 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2 0 0 STRAP_PWR_EN_DEV1_F2 0 0 STRAP_SUBSYS_ID_DEV1_F2 0 0 STRAP_MSI_EN_DEV1_F2 0 0 STRAP_MSI_CLR_PENDING_EN_DEV1_F2 0 0 STRAP_MSIX_EN_DEV1_F2 0 0 STRAP_PMC_DSI_DEV1_F2 0 0 STRAP_VENDOR_ID_BIT_DEV1_F2 0 0 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2 0 0 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2_ 0 0 STRAP_PWR_EN_DEV1_F2_ 1 1 STRAP_SUBSYS_ID_DEV1_F2_ 2 17 STRAP_MSI_EN_DEV1_F2_ 18 18 STRAP_MSI_CLR_PENDING_EN_DEV1_F2_ 19 19 STRAP_MSIX_EN_DEV1_F2_ 20 20 STRAP_PMC_DSI_DEV1_F2_ 24 24 STRAP_VENDOR_ID_BIT_DEV1_F2_ 25 25 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2_ 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2_ 27 27 mmRCC_DEV1_EPF2_STRAP4 0 0x403d104 12 0 3 STRAP_ATOMIC_64BIT_EN_DEV1_F2 0 0 STRAP_ATOMIC_EN_DEV1_F2 0 0 STRAP_FLR_EN_DEV1_F2 0 0 STRAP_PME_SUPPORT_DEV1_F2 0 0 STRAP_INTERRUPT_PIN_DEV1_F2 0 0 STRAP_AUXPWR_SUPPORT_DEV1_F2 0 0 STRAP_ATOMIC_64BIT_EN_DEV1_F2_ 20 20 STRAP_ATOMIC_EN_DEV1_F2_ 21 21 STRAP_FLR_EN_DEV1_F2_ 22 22 STRAP_PME_SUPPORT_DEV1_F2_ 23 27 STRAP_INTERRUPT_PIN_DEV1_F2_ 28 30 STRAP_AUXPWR_SUPPORT_DEV1_F2_ 31 31 mmRCC_DEV1_EPF2_STRAP5 0 0x403d105 2 0 3 STRAP_SUBSYS_VEN_ID_DEV1_F2 0 0 STRAP_SUBSYS_VEN_ID_DEV1_F2_ 0 15 mmRCC_DEV1_EPF2_STRAP6 0 0x403d106 18 0 3 STRAP_APER0_EN_DEV1_F2 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F2 0 0 STRAP_APER0_AP_SIZE_DEV1_F2 0 0 STRAP_APER1_EN_DEV1_F2 0 0 STRAP_APER1_PREFETCHABLE_EN_DEV1_F2 0 0 STRAP_APER2_EN_DEV1_F2 0 0 STRAP_APER2_PREFETCHABLE_EN_DEV1_F2 0 0 STRAP_APER3_EN_DEV1_F2 0 0 STRAP_APER3_PREFETCHABLE_EN_DEV1_F2 0 0 STRAP_APER0_EN_DEV1_F2_ 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F2_ 1 1 STRAP_APER0_AP_SIZE_DEV1_F2_ 4 6 STRAP_APER1_EN_DEV1_F2_ 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV1_F2_ 9 9 STRAP_APER2_EN_DEV1_F2_ 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV1_F2_ 17 17 STRAP_APER3_EN_DEV1_F2_ 24 24 STRAP_APER3_PREFETCHABLE_EN_DEV1_F2_ 25 25 mmRCC_DEV1_EPF2_STRAP13 0 0x403d10d 6 0 3 STRAP_CLASS_CODE_PIF_DEV1_F2 0 0 STRAP_CLASS_CODE_SUB_DEV1_F2 0 0 STRAP_CLASS_CODE_BASE_DEV1_F2 0 0 STRAP_CLASS_CODE_PIF_DEV1_F2_ 0 7 STRAP_CLASS_CODE_SUB_DEV1_F2_ 8 15 STRAP_CLASS_CODE_BASE_DEV1_F2_ 16 23 ixHARD_RST_CTRL 2 0x38000 24 0 4294967295 DSPT_CFG_RST_EN 0 0 DSPT_CFG_STICKY_RST_EN 0 0 DSPT_PRV_RST_EN 0 0 DSPT_PRV_STICKY_RST_EN 0 0 EP_CFG_RST_EN 0 0 EP_CFG_STICKY_RST_EN 0 0 EP_PRV_RST_EN 0 0 EP_PRV_STICKY_RST_EN 0 0 SWUS_SHADOW_RST_EN 0 0 CORE_STICKY_RST_EN 0 0 RELOAD_STRAP_EN 0 0 CORE_RST_EN 0 0 DSPT_CFG_RST_EN_ 0 0 DSPT_CFG_STICKY_RST_EN_ 1 1 DSPT_PRV_RST_EN_ 2 2 DSPT_PRV_STICKY_RST_EN_ 3 3 EP_CFG_RST_EN_ 4 4 EP_CFG_STICKY_RST_EN_ 5 5 EP_PRV_RST_EN_ 6 6 EP_PRV_STICKY_RST_EN_ 7 7 SWUS_SHADOW_RST_EN_ 28 28 CORE_STICKY_RST_EN_ 29 29 RELOAD_STRAP_EN_ 30 30 CORE_RST_EN_ 31 31 ixRSMU_SOFT_RST_CTRL 2 0x38004 24 0 4294967295 DSPT_CFG_RST_EN 0 0 DSPT_CFG_STICKY_RST_EN 0 0 DSPT_PRV_RST_EN 0 0 DSPT_PRV_STICKY_RST_EN 0 0 EP_CFG_RST_EN 0 0 EP_CFG_STICKY_RST_EN 0 0 EP_PRV_RST_EN 0 0 EP_PRV_STICKY_RST_EN 0 0 SWUS_SHADOW_RST_EN 0 0 CORE_STICKY_RST_EN 0 0 RELOAD_STRAP_EN 0 0 CORE_RST_EN 0 0 DSPT_CFG_RST_EN_ 0 0 DSPT_CFG_STICKY_RST_EN_ 1 1 DSPT_PRV_RST_EN_ 2 2 DSPT_PRV_STICKY_RST_EN_ 3 3 EP_CFG_RST_EN_ 4 4 EP_CFG_STICKY_RST_EN_ 5 5 EP_PRV_RST_EN_ 6 6 EP_PRV_STICKY_RST_EN_ 7 7 SWUS_SHADOW_RST_EN_ 28 28 CORE_STICKY_RST_EN_ 29 29 RELOAD_STRAP_EN_ 30 30 CORE_RST_EN_ 31 31 ixSELF_SOFT_RST 2 0x38008 26 0 4294967295 DSPT0_CFG_RST 0 0 DSPT0_CFG_STICKY_RST 0 0 DSPT0_PRV_RST 0 0 DSPT0_PRV_STICKY_RST 0 0 EP0_CFG_RST 0 0 EP0_CFG_STICKY_RST 0 0 EP0_PRV_RST 0 0 EP0_PRV_STICKY_RST 0 0 SDP_PORT_RST 0 0 SWUS_SHADOW_RST 0 0 CORE_STICKY_RST 0 0 RELOAD_STRAP 0 0 CORE_RST 0 0 DSPT0_CFG_RST_ 0 0 DSPT0_CFG_STICKY_RST_ 1 1 DSPT0_PRV_RST_ 2 2 DSPT0_PRV_STICKY_RST_ 3 3 EP0_CFG_RST_ 4 4 EP0_CFG_STICKY_RST_ 5 5 EP0_PRV_RST_ 6 6 EP0_PRV_STICKY_RST_ 7 7 SDP_PORT_RST_ 27 27 SWUS_SHADOW_RST_ 28 28 CORE_STICKY_RST_ 29 29 RELOAD_STRAP_ 30 30 CORE_RST_ 31 31 ixGFX_DRV_MODE1_RST_CTRL 2 0x3800c 16 0 4294967295 DRV_MODE1_PF_CFG_RST 0 0 DRV_MODE1_PF_CFG_FLR_EXC_RST 0 0 DRV_MODE1_PF_CFG_STICKY_RST 0 0 DRV_MODE1_PF_PRV_RST 0 0 DRV_MODE1_PF_PRV_STICKY_RST 0 0 DRV_MODE1_VF_CFG_RST 0 0 DRV_MODE1_VF_CFG_STICKY_RST 0 0 DRV_MODE1_VF_PRV_RST 0 0 DRV_MODE1_PF_CFG_RST_ 0 0 DRV_MODE1_PF_CFG_FLR_EXC_RST_ 1 1 DRV_MODE1_PF_CFG_STICKY_RST_ 2 2 DRV_MODE1_PF_PRV_RST_ 3 3 DRV_MODE1_PF_PRV_STICKY_RST_ 4 4 DRV_MODE1_VF_CFG_RST_ 5 5 DRV_MODE1_VF_CFG_STICKY_RST_ 6 6 DRV_MODE1_VF_PRV_RST_ 7 7 ixBIF_RST_MISC_CTRL 2 0x38010 26 0 4294967295 ERRSTATUS_KEPT_IN_PERSTB 0 0 DRV_RST_MODE 0 0 DRV_RST_CFG_MASK 0 0 DRV_RST_BITS_AUTO_CLEAR 0 0 FLR_RST_BIT_AUTO_CLEAR 0 0 STRAP_EP_LNK_RST_IOV_EN 0 0 LNK_RST_GRACE_MODE 0 0 LNK_RST_GRACE_TIMEOUT 0 0 LNK_RST_TIMER_SEL 0 0 LNK_RST_TIMER2_SEL 0 0 SRIOV_SAVE_VFS_ON_VFENABLE_CLR 0 0 LNK_RST_DMA_DUMMY_DIS 0 0 LNK_RST_DMA_DUMMY_RSPSTS 0 0 ERRSTATUS_KEPT_IN_PERSTB_ 0 0 DRV_RST_MODE_ 2 3 DRV_RST_CFG_MASK_ 4 4 DRV_RST_BITS_AUTO_CLEAR_ 5 5 FLR_RST_BIT_AUTO_CLEAR_ 6 6 STRAP_EP_LNK_RST_IOV_EN_ 8 8 LNK_RST_GRACE_MODE_ 9 9 LNK_RST_GRACE_TIMEOUT_ 10 12 LNK_RST_TIMER_SEL_ 13 14 LNK_RST_TIMER2_SEL_ 15 16 SRIOV_SAVE_VFS_ON_VFENABLE_CLR_ 17 18 LNK_RST_DMA_DUMMY_DIS_ 23 23 LNK_RST_DMA_DUMMY_RSPSTS_ 24 25 ixBIF_RST_MISC_CTRL2 2 0x38014 8 0 4294967295 SWUS_LNK_RST_TRANS_IDLE 0 0 SWDS_LNK_RST_TRANS_IDLE 0 0 ENDP0_LNK_RST_TRANS_IDLE 0 0 ALL_RST_TRANS_IDLE 0 0 SWUS_LNK_RST_TRANS_IDLE_ 16 16 SWDS_LNK_RST_TRANS_IDLE_ 17 17 ENDP0_LNK_RST_TRANS_IDLE_ 18 18 ALL_RST_TRANS_IDLE_ 31 31 ixBIF_RST_MISC_CTRL3 2 0x38018 12 0 4294967295 TIMER_SCALE 0 0 PME_TURNOFF_TIMEOUT 0 0 PME_TURNOFF_MODE 0 0 RELOAD_STRAP_DELAY_HARD 0 0 RELOAD_STRAP_DELAY_SOFT 0 0 RELOAD_STRAP_DELAY_SELF 0 0 TIMER_SCALE_ 0 3 PME_TURNOFF_TIMEOUT_ 4 5 PME_TURNOFF_MODE_ 6 6 RELOAD_STRAP_DELAY_HARD_ 7 9 RELOAD_STRAP_DELAY_SOFT_ 10 12 RELOAD_STRAP_DELAY_SELF_ 13 15 ixBIF_RST_GFXVF_FLR_IDLE 2 0x3801c 34 0 4294967295 VF0_TRANS_IDLE 0 0 VF1_TRANS_IDLE 0 0 VF2_TRANS_IDLE 0 0 VF3_TRANS_IDLE 0 0 VF4_TRANS_IDLE 0 0 VF5_TRANS_IDLE 0 0 VF6_TRANS_IDLE 0 0 VF7_TRANS_IDLE 0 0 VF8_TRANS_IDLE 0 0 VF9_TRANS_IDLE 0 0 VF10_TRANS_IDLE 0 0 VF11_TRANS_IDLE 0 0 VF12_TRANS_IDLE 0 0 VF13_TRANS_IDLE 0 0 VF14_TRANS_IDLE 0 0 VF15_TRANS_IDLE 0 0 SOFTPF_TRANS_IDLE 0 0 VF0_TRANS_IDLE_ 0 0 VF1_TRANS_IDLE_ 1 1 VF2_TRANS_IDLE_ 2 2 VF3_TRANS_IDLE_ 3 3 VF4_TRANS_IDLE_ 4 4 VF5_TRANS_IDLE_ 5 5 VF6_TRANS_IDLE_ 6 6 VF7_TRANS_IDLE_ 7 7 VF8_TRANS_IDLE_ 8 8 VF9_TRANS_IDLE_ 9 9 VF10_TRANS_IDLE_ 10 10 VF11_TRANS_IDLE_ 11 11 VF12_TRANS_IDLE_ 12 12 VF13_TRANS_IDLE_ 13 13 VF14_TRANS_IDLE_ 14 14 VF15_TRANS_IDLE_ 15 15 SOFTPF_TRANS_IDLE_ 31 31 ixDEV0_PF0_FLR_RST_CTRL 2 0x38020 42 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 VF_CFG_EN 0 0 VF_CFG_STICKY_EN 0 0 VF_PRV_EN 0 0 SOFT_PF_CFG_EN 0 0 SOFT_PF_CFG_FLR_EXC_EN 0 0 SOFT_PF_CFG_STICKY_EN 0 0 SOFT_PF_PRV_EN 0 0 SOFT_PF_PRV_STICKY_EN 0 0 VF_VF_CFG_EN 0 0 VF_VF_CFG_STICKY_EN 0 0 VF_VF_PRV_EN 0 0 FLR_TWICE_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 VF_CFG_EN_ 5 5 VF_CFG_STICKY_EN_ 6 6 VF_PRV_EN_ 7 7 SOFT_PF_CFG_EN_ 8 8 SOFT_PF_CFG_FLR_EXC_EN_ 9 9 SOFT_PF_CFG_STICKY_EN_ 10 10 SOFT_PF_PRV_EN_ 11 11 SOFT_PF_PRV_STICKY_EN_ 12 12 VF_VF_CFG_EN_ 13 13 VF_VF_CFG_STICKY_EN_ 14 14 VF_VF_PRV_EN_ 15 15 FLR_TWICE_EN_ 16 16 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF1_FLR_RST_CTRL 2 0x38024 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF2_FLR_RST_CTRL 2 0x38028 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF3_FLR_RST_CTRL 2 0x3802c 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF4_FLR_RST_CTRL 2 0x38030 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF5_FLR_RST_CTRL 2 0x38034 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF6_FLR_RST_CTRL 2 0x38038 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixDEV0_PF7_FLR_RST_CTRL 2 0x3803c 18 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 FLR_GRACE_MODE 0 0 FLR_GRACE_TIMEOUT 0 0 FLR_DMA_DUMMY_RSPSTS 0 0 FLR_HST_DUMMY_RSPSTS 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 FLR_GRACE_MODE_ 17 17 FLR_GRACE_TIMEOUT_ 18 20 FLR_DMA_DUMMY_RSPSTS_ 23 24 FLR_HST_DUMMY_RSPSTS_ 25 26 ixBIF_INST_RESET_INTR_STS 2 0x38040 10 0 4294967295 EP0_LINK_RESET_INTR_STS 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_STS 0 0 DRV_RESET_M0_INTR_STS 0 0 DRV_RESET_M1_INTR_STS 0 0 DRV_RESET_M2_INTR_STS 0 0 EP0_LINK_RESET_INTR_STS_ 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_STS_ 1 1 DRV_RESET_M0_INTR_STS_ 2 2 DRV_RESET_M1_INTR_STS_ 3 3 DRV_RESET_M2_INTR_STS_ 4 4 ixBIF_PF_FLR_INTR_STS 2 0x38044 16 0 4294967295 DEV0_PF0_FLR_INTR_STS 0 0 DEV0_PF1_FLR_INTR_STS 0 0 DEV0_PF2_FLR_INTR_STS 0 0 DEV0_PF3_FLR_INTR_STS 0 0 DEV0_PF4_FLR_INTR_STS 0 0 DEV0_PF5_FLR_INTR_STS 0 0 DEV0_PF6_FLR_INTR_STS 0 0 DEV0_PF7_FLR_INTR_STS 0 0 DEV0_PF0_FLR_INTR_STS_ 0 0 DEV0_PF1_FLR_INTR_STS_ 1 1 DEV0_PF2_FLR_INTR_STS_ 2 2 DEV0_PF3_FLR_INTR_STS_ 3 3 DEV0_PF4_FLR_INTR_STS_ 4 4 DEV0_PF5_FLR_INTR_STS_ 5 5 DEV0_PF6_FLR_INTR_STS_ 6 6 DEV0_PF7_FLR_INTR_STS_ 7 7 ixBIF_D3HOTD0_INTR_STS 2 0x38048 16 0 4294967295 DEV0_PF0_D3HOTD0_INTR_STS 0 0 DEV0_PF1_D3HOTD0_INTR_STS 0 0 DEV0_PF2_D3HOTD0_INTR_STS 0 0 DEV0_PF3_D3HOTD0_INTR_STS 0 0 DEV0_PF4_D3HOTD0_INTR_STS 0 0 DEV0_PF5_D3HOTD0_INTR_STS 0 0 DEV0_PF6_D3HOTD0_INTR_STS 0 0 DEV0_PF7_D3HOTD0_INTR_STS 0 0 DEV0_PF0_D3HOTD0_INTR_STS_ 0 0 DEV0_PF1_D3HOTD0_INTR_STS_ 1 1 DEV0_PF2_D3HOTD0_INTR_STS_ 2 2 DEV0_PF3_D3HOTD0_INTR_STS_ 3 3 DEV0_PF4_D3HOTD0_INTR_STS_ 4 4 DEV0_PF5_D3HOTD0_INTR_STS_ 5 5 DEV0_PF6_D3HOTD0_INTR_STS_ 6 6 DEV0_PF7_D3HOTD0_INTR_STS_ 7 7 ixBIF_POWER_INTR_STS 2 0x38050 4 0 4294967295 DEV0_PME_TURN_OFF_INTR_STS 0 0 PORT0_DSTATE_INTR_STS 0 0 DEV0_PME_TURN_OFF_INTR_STS_ 0 0 PORT0_DSTATE_INTR_STS_ 16 16 ixBIF_PF_DSTATE_INTR_STS 2 0x38054 16 0 4294967295 DEV0_PF0_DSTATE_INTR_STS 0 0 DEV0_PF1_DSTATE_INTR_STS 0 0 DEV0_PF2_DSTATE_INTR_STS 0 0 DEV0_PF3_DSTATE_INTR_STS 0 0 DEV0_PF4_DSTATE_INTR_STS 0 0 DEV0_PF5_DSTATE_INTR_STS 0 0 DEV0_PF6_DSTATE_INTR_STS 0 0 DEV0_PF7_DSTATE_INTR_STS 0 0 DEV0_PF0_DSTATE_INTR_STS_ 0 0 DEV0_PF1_DSTATE_INTR_STS_ 1 1 DEV0_PF2_DSTATE_INTR_STS_ 2 2 DEV0_PF3_DSTATE_INTR_STS_ 3 3 DEV0_PF4_DSTATE_INTR_STS_ 4 4 DEV0_PF5_DSTATE_INTR_STS_ 5 5 DEV0_PF6_DSTATE_INTR_STS_ 6 6 DEV0_PF7_DSTATE_INTR_STS_ 7 7 ixBIF_PF0_VF_FLR_INTR_STS 2 0x38060 34 0 4294967295 PF0_VF0_FLR_INTR_STS 0 0 PF0_VF1_FLR_INTR_STS 0 0 PF0_VF2_FLR_INTR_STS 0 0 PF0_VF3_FLR_INTR_STS 0 0 PF0_VF4_FLR_INTR_STS 0 0 PF0_VF5_FLR_INTR_STS 0 0 PF0_VF6_FLR_INTR_STS 0 0 PF0_VF7_FLR_INTR_STS 0 0 PF0_VF8_FLR_INTR_STS 0 0 PF0_VF9_FLR_INTR_STS 0 0 PF0_VF10_FLR_INTR_STS 0 0 PF0_VF11_FLR_INTR_STS 0 0 PF0_VF12_FLR_INTR_STS 0 0 PF0_VF13_FLR_INTR_STS 0 0 PF0_VF14_FLR_INTR_STS 0 0 PF0_VF15_FLR_INTR_STS 0 0 PF0_SOFTPF_FLR_INTR_STS 0 0 PF0_VF0_FLR_INTR_STS_ 0 0 PF0_VF1_FLR_INTR_STS_ 1 1 PF0_VF2_FLR_INTR_STS_ 2 2 PF0_VF3_FLR_INTR_STS_ 3 3 PF0_VF4_FLR_INTR_STS_ 4 4 PF0_VF5_FLR_INTR_STS_ 5 5 PF0_VF6_FLR_INTR_STS_ 6 6 PF0_VF7_FLR_INTR_STS_ 7 7 PF0_VF8_FLR_INTR_STS_ 8 8 PF0_VF9_FLR_INTR_STS_ 9 9 PF0_VF10_FLR_INTR_STS_ 10 10 PF0_VF11_FLR_INTR_STS_ 11 11 PF0_VF12_FLR_INTR_STS_ 12 12 PF0_VF13_FLR_INTR_STS_ 13 13 PF0_VF14_FLR_INTR_STS_ 14 14 PF0_VF15_FLR_INTR_STS_ 15 15 PF0_SOFTPF_FLR_INTR_STS_ 31 31 ixBIF_INST_RESET_INTR_MASK 2 0x38080 10 0 4294967295 EP0_LINK_RESET_INTR_MASK 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_MASK 0 0 DRV_RESET_M0_INTR_MASK 0 0 DRV_RESET_M1_INTR_MASK 0 0 DRV_RESET_M2_INTR_MASK 0 0 EP0_LINK_RESET_INTR_MASK_ 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_MASK_ 1 1 DRV_RESET_M0_INTR_MASK_ 2 2 DRV_RESET_M1_INTR_MASK_ 3 3 DRV_RESET_M2_INTR_MASK_ 4 4 ixBIF_PF_FLR_INTR_MASK 2 0x38084 16 0 4294967295 DEV0_PF0_FLR_INTR_MASK 0 0 DEV0_PF1_FLR_INTR_MASK 0 0 DEV0_PF2_FLR_INTR_MASK 0 0 DEV0_PF3_FLR_INTR_MASK 0 0 DEV0_PF4_FLR_INTR_MASK 0 0 DEV0_PF5_FLR_INTR_MASK 0 0 DEV0_PF6_FLR_INTR_MASK 0 0 DEV0_PF7_FLR_INTR_MASK 0 0 DEV0_PF0_FLR_INTR_MASK_ 0 0 DEV0_PF1_FLR_INTR_MASK_ 1 1 DEV0_PF2_FLR_INTR_MASK_ 2 2 DEV0_PF3_FLR_INTR_MASK_ 3 3 DEV0_PF4_FLR_INTR_MASK_ 4 4 DEV0_PF5_FLR_INTR_MASK_ 5 5 DEV0_PF6_FLR_INTR_MASK_ 6 6 DEV0_PF7_FLR_INTR_MASK_ 7 7 ixBIF_D3HOTD0_INTR_MASK 2 0x38088 16 0 4294967295 DEV0_PF0_D3HOTD0_INTR_MASK 0 0 DEV0_PF1_D3HOTD0_INTR_MASK 0 0 DEV0_PF2_D3HOTD0_INTR_MASK 0 0 DEV0_PF3_D3HOTD0_INTR_MASK 0 0 DEV0_PF4_D3HOTD0_INTR_MASK 0 0 DEV0_PF5_D3HOTD0_INTR_MASK 0 0 DEV0_PF6_D3HOTD0_INTR_MASK 0 0 DEV0_PF7_D3HOTD0_INTR_MASK 0 0 DEV0_PF0_D3HOTD0_INTR_MASK_ 0 0 DEV0_PF1_D3HOTD0_INTR_MASK_ 1 1 DEV0_PF2_D3HOTD0_INTR_MASK_ 2 2 DEV0_PF3_D3HOTD0_INTR_MASK_ 3 3 DEV0_PF4_D3HOTD0_INTR_MASK_ 4 4 DEV0_PF5_D3HOTD0_INTR_MASK_ 5 5 DEV0_PF6_D3HOTD0_INTR_MASK_ 6 6 DEV0_PF7_D3HOTD0_INTR_MASK_ 7 7 ixBIF_POWER_INTR_MASK 2 0x38090 4 0 4294967295 DEV0_PME_TURN_OFF_INTR_MASK 0 0 PORT0_DSTATE_INTR_MASK 0 0 DEV0_PME_TURN_OFF_INTR_MASK_ 0 0 PORT0_DSTATE_INTR_MASK_ 16 16 ixBIF_PF_DSTATE_INTR_MASK 2 0x38094 16 0 4294967295 DEV0_PF0_DSTATE_INTR_MASK 0 0 DEV0_PF1_DSTATE_INTR_MASK 0 0 DEV0_PF2_DSTATE_INTR_MASK 0 0 DEV0_PF3_DSTATE_INTR_MASK 0 0 DEV0_PF4_DSTATE_INTR_MASK 0 0 DEV0_PF5_DSTATE_INTR_MASK 0 0 DEV0_PF6_DSTATE_INTR_MASK 0 0 DEV0_PF7_DSTATE_INTR_MASK 0 0 DEV0_PF0_DSTATE_INTR_MASK_ 0 0 DEV0_PF1_DSTATE_INTR_MASK_ 1 1 DEV0_PF2_DSTATE_INTR_MASK_ 2 2 DEV0_PF3_DSTATE_INTR_MASK_ 3 3 DEV0_PF4_DSTATE_INTR_MASK_ 4 4 DEV0_PF5_DSTATE_INTR_MASK_ 5 5 DEV0_PF6_DSTATE_INTR_MASK_ 6 6 DEV0_PF7_DSTATE_INTR_MASK_ 7 7 ixBIF_PF0_VF_FLR_INTR_MASK 2 0x380a0 34 0 4294967295 PF0_VF0_FLR_INTR_MASK 0 0 PF0_VF1_FLR_INTR_MASK 0 0 PF0_VF2_FLR_INTR_MASK 0 0 PF0_VF3_FLR_INTR_MASK 0 0 PF0_VF4_FLR_INTR_MASK 0 0 PF0_VF5_FLR_INTR_MASK 0 0 PF0_VF6_FLR_INTR_MASK 0 0 PF0_VF7_FLR_INTR_MASK 0 0 PF0_VF8_FLR_INTR_MASK 0 0 PF0_VF9_FLR_INTR_MASK 0 0 PF0_VF10_FLR_INTR_MASK 0 0 PF0_VF11_FLR_INTR_MASK 0 0 PF0_VF12_FLR_INTR_MASK 0 0 PF0_VF13_FLR_INTR_MASK 0 0 PF0_VF14_FLR_INTR_MASK 0 0 PF0_VF15_FLR_INTR_MASK 0 0 PF0_SOFTPF_FLR_INTR_MASK 0 0 PF0_VF0_FLR_INTR_MASK_ 0 0 PF0_VF1_FLR_INTR_MASK_ 1 1 PF0_VF2_FLR_INTR_MASK_ 2 2 PF0_VF3_FLR_INTR_MASK_ 3 3 PF0_VF4_FLR_INTR_MASK_ 4 4 PF0_VF5_FLR_INTR_MASK_ 5 5 PF0_VF6_FLR_INTR_MASK_ 6 6 PF0_VF7_FLR_INTR_MASK_ 7 7 PF0_VF8_FLR_INTR_MASK_ 8 8 PF0_VF9_FLR_INTR_MASK_ 9 9 PF0_VF10_FLR_INTR_MASK_ 10 10 PF0_VF11_FLR_INTR_MASK_ 11 11 PF0_VF12_FLR_INTR_MASK_ 12 12 PF0_VF13_FLR_INTR_MASK_ 13 13 PF0_VF14_FLR_INTR_MASK_ 14 14 PF0_VF15_FLR_INTR_MASK_ 15 15 PF0_SOFTPF_FLR_INTR_MASK_ 31 31 ixBIF_PF_FLR_RST 2 0x38100 16 0 4294967295 DEV0_PF0_FLR_RST 0 0 DEV0_PF1_FLR_RST 0 0 DEV0_PF2_FLR_RST 0 0 DEV0_PF3_FLR_RST 0 0 DEV0_PF4_FLR_RST 0 0 DEV0_PF5_FLR_RST 0 0 DEV0_PF6_FLR_RST 0 0 DEV0_PF7_FLR_RST 0 0 DEV0_PF0_FLR_RST_ 0 0 DEV0_PF1_FLR_RST_ 1 1 DEV0_PF2_FLR_RST_ 2 2 DEV0_PF3_FLR_RST_ 3 3 DEV0_PF4_FLR_RST_ 4 4 DEV0_PF5_FLR_RST_ 5 5 DEV0_PF6_FLR_RST_ 6 6 DEV0_PF7_FLR_RST_ 7 7 ixBIF_PF0_VF_FLR_RST 2 0x38120 34 0 4294967295 PF0_VF0_FLR_RST 0 0 PF0_VF1_FLR_RST 0 0 PF0_VF2_FLR_RST 0 0 PF0_VF3_FLR_RST 0 0 PF0_VF4_FLR_RST 0 0 PF0_VF5_FLR_RST 0 0 PF0_VF6_FLR_RST 0 0 PF0_VF7_FLR_RST 0 0 PF0_VF8_FLR_RST 0 0 PF0_VF9_FLR_RST 0 0 PF0_VF10_FLR_RST 0 0 PF0_VF11_FLR_RST 0 0 PF0_VF12_FLR_RST 0 0 PF0_VF13_FLR_RST 0 0 PF0_VF14_FLR_RST 0 0 PF0_VF15_FLR_RST 0 0 PF0_SOFTPF_FLR_RST 0 0 PF0_VF0_FLR_RST_ 0 0 PF0_VF1_FLR_RST_ 1 1 PF0_VF2_FLR_RST_ 2 2 PF0_VF3_FLR_RST_ 3 3 PF0_VF4_FLR_RST_ 4 4 PF0_VF5_FLR_RST_ 5 5 PF0_VF6_FLR_RST_ 6 6 PF0_VF7_FLR_RST_ 7 7 PF0_VF8_FLR_RST_ 8 8 PF0_VF9_FLR_RST_ 9 9 PF0_VF10_FLR_RST_ 10 10 PF0_VF11_FLR_RST_ 11 11 PF0_VF12_FLR_RST_ 12 12 PF0_VF13_FLR_RST_ 13 13 PF0_VF14_FLR_RST_ 14 14 PF0_VF15_FLR_RST_ 15 15 PF0_SOFTPF_FLR_RST_ 31 31 ixBIF_DEV0_PF0_DSTATE_VALUE 2 0x38140 6 0 4294967295 DEV0_PF0_DSTATE_TGT_VALUE 0 0 DEV0_PF0_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF0_DSTATE_ACK_VALUE 0 0 DEV0_PF0_DSTATE_TGT_VALUE_ 0 1 DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF0_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF1_DSTATE_VALUE 2 0x38144 6 0 4294967295 DEV0_PF1_DSTATE_TGT_VALUE 0 0 DEV0_PF1_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF1_DSTATE_ACK_VALUE 0 0 DEV0_PF1_DSTATE_TGT_VALUE_ 0 1 DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF1_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF2_DSTATE_VALUE 2 0x38148 6 0 4294967295 DEV0_PF2_DSTATE_TGT_VALUE 0 0 DEV0_PF2_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF2_DSTATE_ACK_VALUE 0 0 DEV0_PF2_DSTATE_TGT_VALUE_ 0 1 DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF2_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF3_DSTATE_VALUE 2 0x3814c 6 0 4294967295 DEV0_PF3_DSTATE_TGT_VALUE 0 0 DEV0_PF3_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF3_DSTATE_ACK_VALUE 0 0 DEV0_PF3_DSTATE_TGT_VALUE_ 0 1 DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF3_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF4_DSTATE_VALUE 2 0x38150 6 0 4294967295 DEV0_PF4_DSTATE_TGT_VALUE 0 0 DEV0_PF4_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF4_DSTATE_ACK_VALUE 0 0 DEV0_PF4_DSTATE_TGT_VALUE_ 0 1 DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF4_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF5_DSTATE_VALUE 2 0x38154 6 0 4294967295 DEV0_PF5_DSTATE_TGT_VALUE 0 0 DEV0_PF5_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF5_DSTATE_ACK_VALUE 0 0 DEV0_PF5_DSTATE_TGT_VALUE_ 0 1 DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF5_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF6_DSTATE_VALUE 2 0x38158 6 0 4294967295 DEV0_PF6_DSTATE_TGT_VALUE 0 0 DEV0_PF6_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF6_DSTATE_ACK_VALUE 0 0 DEV0_PF6_DSTATE_TGT_VALUE_ 0 1 DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF6_DSTATE_ACK_VALUE_ 16 17 ixBIF_DEV0_PF7_DSTATE_VALUE 2 0x3815c 6 0 4294967295 DEV0_PF7_DSTATE_TGT_VALUE 0 0 DEV0_PF7_DSTATE_NEED_D3TOD0_RESET 0 0 DEV0_PF7_DSTATE_ACK_VALUE 0 0 DEV0_PF7_DSTATE_TGT_VALUE_ 0 1 DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_ 2 2 DEV0_PF7_DSTATE_ACK_VALUE_ 16 17 ixDEV0_PF0_D3HOTD0_RST_CTRL 2 0x381e0 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF1_D3HOTD0_RST_CTRL 2 0x381e4 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF2_D3HOTD0_RST_CTRL 2 0x381e8 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF3_D3HOTD0_RST_CTRL 2 0x381ec 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF4_D3HOTD0_RST_CTRL 2 0x381f0 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF5_D3HOTD0_RST_CTRL 2 0x381f4 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF6_D3HOTD0_RST_CTRL 2 0x381f8 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixDEV0_PF7_D3HOTD0_RST_CTRL 2 0x381fc 10 0 4294967295 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 0 0 PF_CFG_STICKY_EN 0 0 PF_PRV_EN 0 0 PF_PRV_STICKY_EN 0 0 PF_CFG_EN_ 0 0 PF_CFG_FLR_EXC_EN_ 1 1 PF_CFG_STICKY_EN_ 2 2 PF_PRV_EN_ 3 3 PF_PRV_STICKY_EN_ 4 4 ixBIF_PORT0_DSTATE_VALUE 2 0x388c0 4 0 4294967295 PORT0_DSTATE_TGT_VALUE 0 0 PORT0_DSTATE_ACK_VALUE 0 0 PORT0_DSTATE_TGT_VALUE_ 0 1 PORT0_DSTATE_ACK_VALUE_ 16 17 ixMISC_SCRATCH 2 0x3a000 2 0 4294967295 MISC_SCRATCH0 0 0 MISC_SCRATCH0_ 0 31 ixINTR_LINE_POLARITY 2 0x3a004 2 0 4294967295 INTR_LINE_POLARITY_DEV0 0 0 INTR_LINE_POLARITY_DEV0_ 0 7 ixINTR_LINE_ENABLE 2 0x3a008 2 0 4294967295 INTR_LINE_ENABLE_DEV0 0 0 INTR_LINE_ENABLE_DEV0_ 0 7 ixOUTSTANDING_VC_ALLOC 2 0x3a00c 24 0 4294967295 DMA_OUTSTANDING_VC0_ALLOC 0 0 DMA_OUTSTANDING_VC1_ALLOC 0 0 DMA_OUTSTANDING_VC2_ALLOC 0 0 DMA_OUTSTANDING_VC3_ALLOC 0 0 DMA_OUTSTANDING_VC4_ALLOC 0 0 DMA_OUTSTANDING_VC5_ALLOC 0 0 DMA_OUTSTANDING_VC6_ALLOC 0 0 DMA_OUTSTANDING_VC7_ALLOC 0 0 DMA_OUTSTANDING_THRD 0 0 HST_OUTSTANDING_VC0_ALLOC 0 0 HST_OUTSTANDING_VC1_ALLOC 0 0 HST_OUTSTANDING_THRD 0 0 DMA_OUTSTANDING_VC0_ALLOC_ 0 1 DMA_OUTSTANDING_VC1_ALLOC_ 2 3 DMA_OUTSTANDING_VC2_ALLOC_ 4 5 DMA_OUTSTANDING_VC3_ALLOC_ 6 7 DMA_OUTSTANDING_VC4_ALLOC_ 8 9 DMA_OUTSTANDING_VC5_ALLOC_ 10 11 DMA_OUTSTANDING_VC6_ALLOC_ 12 13 DMA_OUTSTANDING_VC7_ALLOC_ 14 15 DMA_OUTSTANDING_THRD_ 16 19 HST_OUTSTANDING_VC0_ALLOC_ 24 25 HST_OUTSTANDING_VC1_ALLOC_ 26 27 HST_OUTSTANDING_THRD_ 28 31 ixBIFC_MISC_CTRL0 2 0x3a010 26 0 4294967295 VWIRE_TARG_UNITID_CHECK_EN 0 0 VWIRE_SRC_UNITID_CHECK_EN 0 0 DMA_CHAIN_BREAK_IN_RCMODE 0 0 HST_ARB_CHAIN_LOCK 0 0 GSI_SST_ARB_CHAIN_LOCK 0 0 DMA_ATOMIC_LENGTH_CHK_DIS 0 0 DMA_ATOMIC_FAILED_STS_SEL 0 0 PCIE_CAPABILITY_PROT_DIS 0 0 VC7_DMA_IOCFG_DIS 0 0 DMA_2ND_REQ_DIS 0 0 PORT_DSTATE_BYPASS_MODE 0 0 PME_TURNOFF_MODE 0 0 PCIESWUS_SELECTION 0 0 VWIRE_TARG_UNITID_CHECK_EN_ 0 0 VWIRE_SRC_UNITID_CHECK_EN_ 1 2 DMA_CHAIN_BREAK_IN_RCMODE_ 8 8 HST_ARB_CHAIN_LOCK_ 9 9 GSI_SST_ARB_CHAIN_LOCK_ 10 10 DMA_ATOMIC_LENGTH_CHK_DIS_ 16 16 DMA_ATOMIC_FAILED_STS_SEL_ 17 17 PCIE_CAPABILITY_PROT_DIS_ 24 24 VC7_DMA_IOCFG_DIS_ 25 25 DMA_2ND_REQ_DIS_ 26 26 PORT_DSTATE_BYPASS_MODE_ 27 27 PME_TURNOFF_MODE_ 28 28 PCIESWUS_SELECTION_ 31 31 ixBIFC_MISC_CTRL1 2 0x3a014 36 0 4294967295 THT_HST_CPLD_POISON_REPORT 0 0 DMA_REQ_POISON_REPORT 0 0 DMA_REQ_ACSVIO_REPORT 0 0 DMA_RSP_POISON_CPLD_REPORT 0 0 GSI_SMN_WORST_ERR_STSTUS 0 0 GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR 0 0 GSI_RDWR_BALANCE_DIS 0 0 GMI_MSG_BLOCKLVL_SEL 0 0 HST_UNSUPPORT_SDPCMD_STS 0 0 HST_UNSUPPORT_SDPCMD_DATASTS 0 0 DROP_OTHER_HT_ADDR_REQ 0 0 DMAWRREQ_HSTRDRSP_ORDER_FORCE 0 0 DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE 0 0 UPS_SDP_RDY_TIE1 0 0 GMI_RCC_DN_BME_DROP_DIS 0 0 GMI_RCC_EP_BME_DROP_DIS 0 0 GMI_BIH_DN_BME_DROP_DIS 0 0 GMI_BIH_EP_BME_DROP_DIS 0 0 THT_HST_CPLD_POISON_REPORT_ 0 0 DMA_REQ_POISON_REPORT_ 1 1 DMA_REQ_ACSVIO_REPORT_ 2 2 DMA_RSP_POISON_CPLD_REPORT_ 3 3 GSI_SMN_WORST_ERR_STSTUS_ 4 4 GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_ 5 5 GSI_RDWR_BALANCE_DIS_ 6 6 GMI_MSG_BLOCKLVL_SEL_ 7 7 HST_UNSUPPORT_SDPCMD_STS_ 8 9 HST_UNSUPPORT_SDPCMD_DATASTS_ 10 11 DROP_OTHER_HT_ADDR_REQ_ 12 12 DMAWRREQ_HSTRDRSP_ORDER_FORCE_ 13 13 DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_ 14 14 UPS_SDP_RDY_TIE1_ 15 15 GMI_RCC_DN_BME_DROP_DIS_ 16 16 GMI_RCC_EP_BME_DROP_DIS_ 17 17 GMI_BIH_DN_BME_DROP_DIS_ 18 18 GMI_BIH_EP_BME_DROP_DIS_ 19 19 ixBIFC_BME_ERR_LOG 2 0x3a018 32 0 4294967295 DMA_ON_BME_LOW_DEV0_F0 0 0 DMA_ON_BME_LOW_DEV0_F1 0 0 DMA_ON_BME_LOW_DEV0_F2 0 0 DMA_ON_BME_LOW_DEV0_F3 0 0 DMA_ON_BME_LOW_DEV0_F4 0 0 DMA_ON_BME_LOW_DEV0_F5 0 0 DMA_ON_BME_LOW_DEV0_F6 0 0 DMA_ON_BME_LOW_DEV0_F7 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F0 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F1 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F2 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F3 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F4 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F5 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F6 0 0 CLEAR_DMA_ON_BME_LOW_DEV0_F7 0 0 DMA_ON_BME_LOW_DEV0_F0_ 0 0 DMA_ON_BME_LOW_DEV0_F1_ 1 1 DMA_ON_BME_LOW_DEV0_F2_ 2 2 DMA_ON_BME_LOW_DEV0_F3_ 3 3 DMA_ON_BME_LOW_DEV0_F4_ 4 4 DMA_ON_BME_LOW_DEV0_F5_ 5 5 DMA_ON_BME_LOW_DEV0_F6_ 6 6 DMA_ON_BME_LOW_DEV0_F7_ 7 7 CLEAR_DMA_ON_BME_LOW_DEV0_F0_ 16 16 CLEAR_DMA_ON_BME_LOW_DEV0_F1_ 17 17 CLEAR_DMA_ON_BME_LOW_DEV0_F2_ 18 18 CLEAR_DMA_ON_BME_LOW_DEV0_F3_ 19 19 CLEAR_DMA_ON_BME_LOW_DEV0_F4_ 20 20 CLEAR_DMA_ON_BME_LOW_DEV0_F5_ 21 21 CLEAR_DMA_ON_BME_LOW_DEV0_F6_ 22 22 CLEAR_DMA_ON_BME_LOW_DEV0_F7_ 23 23 ixBIFC_RCCBIH_BME_ERR_LOG 2 0x3a01c 32 0 4294967295 RCCBIH_ON_BME_LOW_DEV0_F0 0 0 RCCBIH_ON_BME_LOW_DEV0_F1 0 0 RCCBIH_ON_BME_LOW_DEV0_F2 0 0 RCCBIH_ON_BME_LOW_DEV0_F3 0 0 RCCBIH_ON_BME_LOW_DEV0_F4 0 0 RCCBIH_ON_BME_LOW_DEV0_F5 0 0 RCCBIH_ON_BME_LOW_DEV0_F6 0 0 RCCBIH_ON_BME_LOW_DEV0_F7 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6 0 0 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7 0 0 RCCBIH_ON_BME_LOW_DEV0_F0_ 0 0 RCCBIH_ON_BME_LOW_DEV0_F1_ 1 1 RCCBIH_ON_BME_LOW_DEV0_F2_ 2 2 RCCBIH_ON_BME_LOW_DEV0_F3_ 3 3 RCCBIH_ON_BME_LOW_DEV0_F4_ 4 4 RCCBIH_ON_BME_LOW_DEV0_F5_ 5 5 RCCBIH_ON_BME_LOW_DEV0_F6_ 6 6 RCCBIH_ON_BME_LOW_DEV0_F7_ 7 7 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_ 16 16 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_ 17 17 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_ 18 18 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_ 19 19 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_ 20 20 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_ 21 21 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_ 22 22 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_ 23 23 ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 2 0x3a020 24 0 4294967295 TX_IDO_OVERIDE_P_DEV0_F0 0 0 TX_IDO_OVERIDE_NP_DEV0_F0 0 0 TX_RO_OVERIDE_P_DEV0_F0 0 0 TX_RO_OVERIDE_NP_DEV0_F0 0 0 TX_SNR_OVERIDE_P_DEV0_F0 0 0 TX_SNR_OVERIDE_NP_DEV0_F0 0 0 TX_IDO_OVERIDE_P_DEV0_F1 0 0 TX_IDO_OVERIDE_NP_DEV0_F1 0 0 TX_RO_OVERIDE_P_DEV0_F1 0 0 TX_RO_OVERIDE_NP_DEV0_F1 0 0 TX_SNR_OVERIDE_P_DEV0_F1 0 0 TX_SNR_OVERIDE_NP_DEV0_F1 0 0 TX_IDO_OVERIDE_P_DEV0_F0_ 0 1 TX_IDO_OVERIDE_NP_DEV0_F0_ 2 3 TX_RO_OVERIDE_P_DEV0_F0_ 6 7 TX_RO_OVERIDE_NP_DEV0_F0_ 8 9 TX_SNR_OVERIDE_P_DEV0_F0_ 10 11 TX_SNR_OVERIDE_NP_DEV0_F0_ 12 13 TX_IDO_OVERIDE_P_DEV0_F1_ 16 17 TX_IDO_OVERIDE_NP_DEV0_F1_ 18 19 TX_RO_OVERIDE_P_DEV0_F1_ 22 23 TX_RO_OVERIDE_NP_DEV0_F1_ 24 25 TX_SNR_OVERIDE_P_DEV0_F1_ 26 27 TX_SNR_OVERIDE_NP_DEV0_F1_ 28 29 ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 2 0x3a024 24 0 4294967295 TX_IDO_OVERIDE_P_DEV0_F2 0 0 TX_IDO_OVERIDE_NP_DEV0_F2 0 0 TX_RO_OVERIDE_P_DEV0_F2 0 0 TX_RO_OVERIDE_NP_DEV0_F2 0 0 TX_SNR_OVERIDE_P_DEV0_F2 0 0 TX_SNR_OVERIDE_NP_DEV0_F2 0 0 TX_IDO_OVERIDE_P_DEV0_F3 0 0 TX_IDO_OVERIDE_NP_DEV0_F3 0 0 TX_RO_OVERIDE_P_DEV0_F3 0 0 TX_RO_OVERIDE_NP_DEV0_F3 0 0 TX_SNR_OVERIDE_P_DEV0_F3 0 0 TX_SNR_OVERIDE_NP_DEV0_F3 0 0 TX_IDO_OVERIDE_P_DEV0_F2_ 0 1 TX_IDO_OVERIDE_NP_DEV0_F2_ 2 3 TX_RO_OVERIDE_P_DEV0_F2_ 6 7 TX_RO_OVERIDE_NP_DEV0_F2_ 8 9 TX_SNR_OVERIDE_P_DEV0_F2_ 10 11 TX_SNR_OVERIDE_NP_DEV0_F2_ 12 13 TX_IDO_OVERIDE_P_DEV0_F3_ 16 17 TX_IDO_OVERIDE_NP_DEV0_F3_ 18 19 TX_RO_OVERIDE_P_DEV0_F3_ 22 23 TX_RO_OVERIDE_NP_DEV0_F3_ 24 25 TX_SNR_OVERIDE_P_DEV0_F3_ 26 27 TX_SNR_OVERIDE_NP_DEV0_F3_ 28 29 ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 2 0x3a028 24 0 4294967295 TX_IDO_OVERIDE_P_DEV0_F4 0 0 TX_IDO_OVERIDE_NP_DEV0_F4 0 0 TX_RO_OVERIDE_P_DEV0_F4 0 0 TX_RO_OVERIDE_NP_DEV0_F4 0 0 TX_SNR_OVERIDE_P_DEV0_F4 0 0 TX_SNR_OVERIDE_NP_DEV0_F4 0 0 TX_IDO_OVERIDE_P_DEV0_F5 0 0 TX_IDO_OVERIDE_NP_DEV0_F5 0 0 TX_RO_OVERIDE_P_DEV0_F5 0 0 TX_RO_OVERIDE_NP_DEV0_F5 0 0 TX_SNR_OVERIDE_P_DEV0_F5 0 0 TX_SNR_OVERIDE_NP_DEV0_F5 0 0 TX_IDO_OVERIDE_P_DEV0_F4_ 0 1 TX_IDO_OVERIDE_NP_DEV0_F4_ 2 3 TX_RO_OVERIDE_P_DEV0_F4_ 6 7 TX_RO_OVERIDE_NP_DEV0_F4_ 8 9 TX_SNR_OVERIDE_P_DEV0_F4_ 10 11 TX_SNR_OVERIDE_NP_DEV0_F4_ 12 13 TX_IDO_OVERIDE_P_DEV0_F5_ 16 17 TX_IDO_OVERIDE_NP_DEV0_F5_ 18 19 TX_RO_OVERIDE_P_DEV0_F5_ 22 23 TX_RO_OVERIDE_NP_DEV0_F5_ 24 25 TX_SNR_OVERIDE_P_DEV0_F5_ 26 27 TX_SNR_OVERIDE_NP_DEV0_F5_ 28 29 ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 2 0x3a02c 24 0 4294967295 TX_IDO_OVERIDE_P_DEV0_F6 0 0 TX_IDO_OVERIDE_NP_DEV0_F6 0 0 TX_RO_OVERIDE_P_DEV0_F6 0 0 TX_RO_OVERIDE_NP_DEV0_F6 0 0 TX_SNR_OVERIDE_P_DEV0_F6 0 0 TX_SNR_OVERIDE_NP_DEV0_F6 0 0 TX_IDO_OVERIDE_P_DEV0_F7 0 0 TX_IDO_OVERIDE_NP_DEV0_F7 0 0 TX_RO_OVERIDE_P_DEV0_F7 0 0 TX_RO_OVERIDE_NP_DEV0_F7 0 0 TX_SNR_OVERIDE_P_DEV0_F7 0 0 TX_SNR_OVERIDE_NP_DEV0_F7 0 0 TX_IDO_OVERIDE_P_DEV0_F6_ 0 1 TX_IDO_OVERIDE_NP_DEV0_F6_ 2 3 TX_RO_OVERIDE_P_DEV0_F6_ 6 7 TX_RO_OVERIDE_NP_DEV0_F6_ 8 9 TX_SNR_OVERIDE_P_DEV0_F6_ 10 11 TX_SNR_OVERIDE_NP_DEV0_F6_ 12 13 TX_IDO_OVERIDE_P_DEV0_F7_ 16 17 TX_IDO_OVERIDE_NP_DEV0_F7_ 18 19 TX_RO_OVERIDE_P_DEV0_F7_ 22 23 TX_RO_OVERIDE_NP_DEV0_F7_ 24 25 TX_SNR_OVERIDE_P_DEV0_F7_ 26 27 TX_SNR_OVERIDE_NP_DEV0_F7_ 28 29 ixNBIF_VWIRE_CTRL 2 0x3a040 8 0 4294967295 SMN_VWR_RESET_DELAY_CNT 0 0 SMN_VWR_POSTED 0 0 SDP_VWR_RESET_DELAY_CNT 0 0 SDP_VWR_BLOCKLVL 0 0 SMN_VWR_RESET_DELAY_CNT_ 4 7 SMN_VWR_POSTED_ 8 8 SDP_VWR_RESET_DELAY_CNT_ 20 23 SDP_VWR_BLOCKLVL_ 26 27 ixNBIF_SMN_VWR_VCHG_DIS_CTRL 2 0x3a044 14 0 4294967295 SMN_VWR_VCHG_SET0_DIS 0 0 SMN_VWR_VCHG_SET1_DIS 0 0 SMN_VWR_VCHG_SET2_DIS 0 0 SMN_VWR_VCHG_SET3_DIS 0 0 SMN_VWR_VCHG_SET4_DIS 0 0 SMN_VWR_VCHG_SET5_DIS 0 0 SMN_VWR_VCHG_SET6_DIS 0 0 SMN_VWR_VCHG_SET0_DIS_ 0 0 SMN_VWR_VCHG_SET1_DIS_ 1 1 SMN_VWR_VCHG_SET2_DIS_ 2 2 SMN_VWR_VCHG_SET3_DIS_ 3 3 SMN_VWR_VCHG_SET4_DIS_ 4 4 SMN_VWR_VCHG_SET5_DIS_ 5 5 SMN_VWR_VCHG_SET6_DIS_ 6 6 ixNBIF_SMN_VWR_VCHG_RST_CTRL0 2 0x3a048 14 0 4294967295 SMN_VWR_VCHG_SET0_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET1_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET2_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET3_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET4_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET5_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET6_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET0_RST_DEF_REV_ 0 0 SMN_VWR_VCHG_SET1_RST_DEF_REV_ 1 1 SMN_VWR_VCHG_SET2_RST_DEF_REV_ 2 2 SMN_VWR_VCHG_SET3_RST_DEF_REV_ 3 3 SMN_VWR_VCHG_SET4_RST_DEF_REV_ 4 4 SMN_VWR_VCHG_SET5_RST_DEF_REV_ 5 5 SMN_VWR_VCHG_SET6_RST_DEF_REV_ 6 6 ixNBIF_SMN_VWR_VCHG_TRIG 2 0x3a050 14 0 4294967295 SMN_VWR_VCHG_SET0_TRIG 0 0 SMN_VWR_VCHG_SET1_TRIG 0 0 SMN_VWR_VCHG_SET2_TRIG 0 0 SMN_VWR_VCHG_SET3_TRIG 0 0 SMN_VWR_VCHG_SET4_TRIG 0 0 SMN_VWR_VCHG_SET5_TRIG 0 0 SMN_VWR_VCHG_SET6_TRIG 0 0 SMN_VWR_VCHG_SET0_TRIG_ 0 0 SMN_VWR_VCHG_SET1_TRIG_ 1 1 SMN_VWR_VCHG_SET2_TRIG_ 2 2 SMN_VWR_VCHG_SET3_TRIG_ 3 3 SMN_VWR_VCHG_SET4_TRIG_ 4 4 SMN_VWR_VCHG_SET5_TRIG_ 5 5 SMN_VWR_VCHG_SET6_TRIG_ 6 6 ixNBIF_SMN_VWR_WTRIG_CNTL 2 0x3a054 14 0 4294967295 SMN_VWR_WTRIG_SET0_DIS 0 0 SMN_VWR_WTRIG_SET1_DIS 0 0 SMN_VWR_WTRIG_SET2_DIS 0 0 SMN_VWR_WTRIG_SET3_DIS 0 0 SMN_VWR_WTRIG_SET4_DIS 0 0 SMN_VWR_WTRIG_SET5_DIS 0 0 SMN_VWR_WTRIG_SET6_DIS 0 0 SMN_VWR_WTRIG_SET0_DIS_ 0 0 SMN_VWR_WTRIG_SET1_DIS_ 1 1 SMN_VWR_WTRIG_SET2_DIS_ 2 2 SMN_VWR_WTRIG_SET3_DIS_ 3 3 SMN_VWR_WTRIG_SET4_DIS_ 4 4 SMN_VWR_WTRIG_SET5_DIS_ 5 5 SMN_VWR_WTRIG_SET6_DIS_ 6 6 ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 2 0x3a058 14 0 4294967295 SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_ 0 0 SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_ 1 1 SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_ 2 2 SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_ 3 3 SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_ 4 4 SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_ 5 5 SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_ 6 6 ixNBIF_MGCG_CTRL 2 0x3a05c 6 0 4294967295 NBIF_MGCG_EN 0 0 NBIF_MGCG_MODE 0 0 NBIF_MGCG_HYSTERESIS 0 0 NBIF_MGCG_EN_ 0 0 NBIF_MGCG_MODE_ 1 1 NBIF_MGCG_HYSTERESIS_ 2 9 ixNBIF_DS_CTRL_LCLK 2 0x3a060 4 0 4294967295 NBIF_LCLK_DS_EN 0 0 NBIF_LCLK_DS_TIMER 0 0 NBIF_LCLK_DS_EN_ 0 0 NBIF_LCLK_DS_TIMER_ 16 31 ixSMN_MST_CNTL0 2 0x3a064 18 0 4294967295 SMN_ARB_MODE 0 0 SMN_ZERO_BE_WR_EN_UPS 0 0 SMN_ZERO_BE_RD_EN_UPS 0 0 SMN_POST_MASK_EN_UPS 0 0 MULTI_SMN_TRANS_ID_DIS_UPS 0 0 SMN_ZERO_BE_WR_EN_DNS_DEV0 0 0 SMN_ZERO_BE_RD_EN_DNS_DEV0 0 0 SMN_POST_MASK_EN_DNS_DEV0 0 0 MULTI_SMN_TRANS_ID_DIS_DNS_DEV0 0 0 SMN_ARB_MODE_ 0 1 SMN_ZERO_BE_WR_EN_UPS_ 8 8 SMN_ZERO_BE_RD_EN_UPS_ 9 9 SMN_POST_MASK_EN_UPS_ 10 10 MULTI_SMN_TRANS_ID_DIS_UPS_ 11 11 SMN_ZERO_BE_WR_EN_DNS_DEV0_ 16 16 SMN_ZERO_BE_RD_EN_DNS_DEV0_ 20 20 SMN_POST_MASK_EN_DNS_DEV0_ 24 24 MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_ 28 28 ixSMN_MST_EP_CNTL1 2 0x3a068 16 0 4294967295 SMN_POST_MASK_EN_EP_DEV0_PF0 0 0 SMN_POST_MASK_EN_EP_DEV0_PF1 0 0 SMN_POST_MASK_EN_EP_DEV0_PF2 0 0 SMN_POST_MASK_EN_EP_DEV0_PF3 0 0 SMN_POST_MASK_EN_EP_DEV0_PF4 0 0 SMN_POST_MASK_EN_EP_DEV0_PF5 0 0 SMN_POST_MASK_EN_EP_DEV0_PF6 0 0 SMN_POST_MASK_EN_EP_DEV0_PF7 0 0 SMN_POST_MASK_EN_EP_DEV0_PF0_ 0 0 SMN_POST_MASK_EN_EP_DEV0_PF1_ 1 1 SMN_POST_MASK_EN_EP_DEV0_PF2_ 2 2 SMN_POST_MASK_EN_EP_DEV0_PF3_ 3 3 SMN_POST_MASK_EN_EP_DEV0_PF4_ 4 4 SMN_POST_MASK_EN_EP_DEV0_PF5_ 5 5 SMN_POST_MASK_EN_EP_DEV0_PF6_ 6 6 SMN_POST_MASK_EN_EP_DEV0_PF7_ 7 7 ixSMN_MST_EP_CNTL2 2 0x3a06c 16 0 4294967295 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_ 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_ 1 1 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_ 2 2 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_ 3 3 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_ 4 4 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_ 5 5 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_ 6 6 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_ 7 7 ixNBIF_SDP_VWR_VCHG_DIS_CTRL 2 0x3a070 18 0 4294967295 SDP_VWR_VCHG_ENDP_F0_DIS 0 0 SDP_VWR_VCHG_ENDP_F1_DIS 0 0 SDP_VWR_VCHG_ENDP_F2_DIS 0 0 SDP_VWR_VCHG_ENDP_F3_DIS 0 0 SDP_VWR_VCHG_ENDP_F4_DIS 0 0 SDP_VWR_VCHG_ENDP_F5_DIS 0 0 SDP_VWR_VCHG_ENDP_F6_DIS 0 0 SDP_VWR_VCHG_ENDP_F7_DIS 0 0 SDP_VWR_VCHG_SWDS_P0_DIS 0 0 SDP_VWR_VCHG_ENDP_F0_DIS_ 0 0 SDP_VWR_VCHG_ENDP_F1_DIS_ 1 1 SDP_VWR_VCHG_ENDP_F2_DIS_ 2 2 SDP_VWR_VCHG_ENDP_F3_DIS_ 3 3 SDP_VWR_VCHG_ENDP_F4_DIS_ 4 4 SDP_VWR_VCHG_ENDP_F5_DIS_ 5 5 SDP_VWR_VCHG_ENDP_F6_DIS_ 6 6 SDP_VWR_VCHG_ENDP_F7_DIS_ 7 7 SDP_VWR_VCHG_SWDS_P0_DIS_ 24 24 ixNBIF_SDP_VWR_VCHG_RST_CTRL0 2 0x3a074 18 0 4294967295 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN 0 0 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_ 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_ 1 1 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_ 2 2 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_ 3 3 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_ 4 4 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_ 5 5 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_ 6 6 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_ 7 7 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_ 24 24 ixNBIF_SDP_VWR_VCHG_RST_CTRL1 2 0x3a078 18 0 4294967295 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_ 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_ 1 1 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_ 2 2 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_ 3 3 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_ 4 4 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_ 5 5 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_ 6 6 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_ 7 7 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_ 24 24 ixNBIF_SDP_VWR_VCHG_TRIG 2 0x3a07c 18 0 4294967295 SDP_VWR_VCHG_ENDP_F0_TRIG 0 0 SDP_VWR_VCHG_ENDP_F1_TRIG 0 0 SDP_VWR_VCHG_ENDP_F2_TRIG 0 0 SDP_VWR_VCHG_ENDP_F3_TRIG 0 0 SDP_VWR_VCHG_ENDP_F4_TRIG 0 0 SDP_VWR_VCHG_ENDP_F5_TRIG 0 0 SDP_VWR_VCHG_ENDP_F6_TRIG 0 0 SDP_VWR_VCHG_ENDP_F7_TRIG 0 0 SDP_VWR_VCHG_SWDS_P0_TRIG 0 0 SDP_VWR_VCHG_ENDP_F0_TRIG_ 0 0 SDP_VWR_VCHG_ENDP_F1_TRIG_ 1 1 SDP_VWR_VCHG_ENDP_F2_TRIG_ 2 2 SDP_VWR_VCHG_ENDP_F3_TRIG_ 3 3 SDP_VWR_VCHG_ENDP_F4_TRIG_ 4 4 SDP_VWR_VCHG_ENDP_F5_TRIG_ 5 5 SDP_VWR_VCHG_ENDP_F6_TRIG_ 6 6 SDP_VWR_VCHG_ENDP_F7_TRIG_ 7 7 SDP_VWR_VCHG_SWDS_P0_TRIG_ 24 24 ixBME_DUMMY_CNTL_0 2 0x3a098 16 0 4294967295 BME_DUMMY_RSPSTS_DEV0_F0 0 0 BME_DUMMY_RSPSTS_DEV0_F1 0 0 BME_DUMMY_RSPSTS_DEV0_F2 0 0 BME_DUMMY_RSPSTS_DEV0_F3 0 0 BME_DUMMY_RSPSTS_DEV0_F4 0 0 BME_DUMMY_RSPSTS_DEV0_F5 0 0 BME_DUMMY_RSPSTS_DEV0_F6 0 0 BME_DUMMY_RSPSTS_DEV0_F7 0 0 BME_DUMMY_RSPSTS_DEV0_F0_ 0 1 BME_DUMMY_RSPSTS_DEV0_F1_ 2 3 BME_DUMMY_RSPSTS_DEV0_F2_ 4 5 BME_DUMMY_RSPSTS_DEV0_F3_ 6 7 BME_DUMMY_RSPSTS_DEV0_F4_ 8 9 BME_DUMMY_RSPSTS_DEV0_F5_ 10 11 BME_DUMMY_RSPSTS_DEV0_F6_ 12 13 BME_DUMMY_RSPSTS_DEV0_F7_ 14 15 ixBIFC_THT_CNTL 2 0x3a09c 6 0 4294967295 CREDIT_ALLOC_THT_RD_VC0 0 0 CREDIT_ALLOC_THT_WR_VC0 0 0 CREDIT_ALLOC_THT_WR_VC1 0 0 CREDIT_ALLOC_THT_RD_VC0_ 0 3 CREDIT_ALLOC_THT_WR_VC0_ 4 7 CREDIT_ALLOC_THT_WR_VC1_ 8 11 ixBIFC_HSTARB_CNTL 2 0x3a0a0 2 0 4294967295 SLVARB_MODE 0 0 SLVARB_MODE_ 0 1 ixBIFC_GSI_CNTL 2 0x3a0a4 18 0 4294967295 GSI_SDP_RSP_ARB_MODE 0 0 GSI_CPL_RSP_ARB_MODE 0 0 GSI_CPL_INTERLEAVING_EN 0 0 GSI_CPL_PCR_EP_CAUSE_UR_EN 0 0 GSI_CPL_SMN_P_EP_CAUSE_UR_EN 0 0 GSI_CPL_SMN_NP_EP_CAUSE_UR_EN 0 0 GSI_CPL_SST_EP_CAUSE_UR_EN 0 0 GSI_SDP_REQ_ARB_MODE 0 0 GSI_SMN_REQ_ARB_MODE 0 0 GSI_SDP_RSP_ARB_MODE_ 0 1 GSI_CPL_RSP_ARB_MODE_ 2 4 GSI_CPL_INTERLEAVING_EN_ 5 5 GSI_CPL_PCR_EP_CAUSE_UR_EN_ 6 6 GSI_CPL_SMN_P_EP_CAUSE_UR_EN_ 7 7 GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_ 8 8 GSI_CPL_SST_EP_CAUSE_UR_EN_ 9 9 GSI_SDP_REQ_ARB_MODE_ 10 11 GSI_SMN_REQ_ARB_MODE_ 12 13 ixBIFC_PCIEFUNC_CNTL 2 0x3a0a8 4 0 4294967295 DMA_NON_PCIEFUNC_BUSDEVFUNC 0 0 MP1SYSHUBDATA_DRAM_IS_PCIEFUNC 0 0 DMA_NON_PCIEFUNC_BUSDEVFUNC_ 0 15 MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_ 16 16 ixBIFC_SDP_CNTL_0 2 0x3a0b0 8 0 4294967295 HRP_SDP_DISCON_HYSTERESIS 0 0 GSI_SDP_DISCON_HYSTERESIS 0 0 GMI_DNS_SDP_DISCON_HYSTERESIS 0 0 GMI_UPS_SDP_DISCON_HYSTERESIS 0 0 HRP_SDP_DISCON_HYSTERESIS_ 0 5 GSI_SDP_DISCON_HYSTERESIS_ 6 11 GMI_DNS_SDP_DISCON_HYSTERESIS_ 12 17 GMI_UPS_SDP_DISCON_HYSTERESIS_ 18 23 ixBIFC_PERF_CNTL_0 2 0x3a0c0 12 0 4294967295 PERF_CNT_MMIO_RD_EN 0 0 PERF_CNT_MMIO_WR_EN 0 0 PERF_CNT_MMIO_RD_RESET 0 0 PERF_CNT_MMIO_WR_RESET 0 0 PERF_CNT_MMIO_RD_SEL 0 0 PERF_CNT_MMIO_WR_SEL 0 0 PERF_CNT_MMIO_RD_EN_ 0 0 PERF_CNT_MMIO_WR_EN_ 1 1 PERF_CNT_MMIO_RD_RESET_ 8 8 PERF_CNT_MMIO_WR_RESET_ 9 9 PERF_CNT_MMIO_RD_SEL_ 16 20 PERF_CNT_MMIO_WR_SEL_ 24 28 ixBIFC_PERF_CNTL_1 2 0x3a0c4 12 0 4294967295 PERF_CNT_DMA_RD_EN 0 0 PERF_CNT_DMA_WR_EN 0 0 PERF_CNT_DMA_RD_RESET 0 0 PERF_CNT_DMA_WR_RESET 0 0 PERF_CNT_DMA_RD_SEL 0 0 PERF_CNT_DMA_WR_SEL 0 0 PERF_CNT_DMA_RD_EN_ 0 0 PERF_CNT_DMA_WR_EN_ 1 1 PERF_CNT_DMA_RD_RESET_ 8 8 PERF_CNT_DMA_WR_RESET_ 9 9 PERF_CNT_DMA_RD_SEL_ 16 21 PERF_CNT_DMA_WR_SEL_ 24 30 ixBIFC_PERF_CNT_MMIO_RD 2 0x3a0c8 2 0 4294967295 PERF_CNT_MMIO_RD_VALUE 0 0 PERF_CNT_MMIO_RD_VALUE_ 0 31 ixBIFC_PERF_CNT_MMIO_WR 2 0x3a0cc 2 0 4294967295 PERF_CNT_MMIO_WR_VALUE 0 0 PERF_CNT_MMIO_WR_VALUE_ 0 31 ixBIFC_PERF_CNT_DMA_RD 2 0x3a0d0 2 0 4294967295 PERF_CNT_DMA_RD_VALUE 0 0 PERF_CNT_DMA_RD_VALUE_ 0 31 ixBIFC_PERF_CNT_DMA_WR 2 0x3a0d4 2 0 4294967295 PERF_CNT_DMA_WR_VALUE 0 0 PERF_CNT_DMA_WR_VALUE_ 0 31 ixNBIF_REGIF_ERRSET_CTRL 2 0x3a0d8 2 0 4294967295 DROP_NONPF_MMREGREQ_SETERR_DIS 0 0 DROP_NONPF_MMREGREQ_SETERR_DIS_ 0 0 ixSMN_MST_EP_CNTL3 2 0x3a0f0 16 0 4294967295 SMN_ZERO_BE_WR_EN_EP_DEV0_PF0 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF1 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF2 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF3 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF4 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF5 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF6 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF7 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_ 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_ 1 1 SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_ 2 2 SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_ 3 3 SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_ 4 4 SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_ 5 5 SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_ 6 6 SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_ 7 7 ixSMN_MST_EP_CNTL4 2 0x3a0f4 16 0 4294967295 SMN_ZERO_BE_RD_EN_EP_DEV0_PF0 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF1 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF2 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF3 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF4 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF5 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF6 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF7 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_ 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_ 1 1 SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_ 2 2 SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_ 3 3 SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_ 4 4 SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_ 5 5 SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_ 6 6 SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_ 7 7 ixBIF_SELFRING_BUFFER_VID 2 0x3a100 4 0 4294967295 DOORBELL_MONITOR_CID 0 0 IOHUB_RAS_INTR_CID 0 0 DOORBELL_MONITOR_CID_ 0 7 IOHUB_RAS_INTR_CID_ 8 15 ixBIF_SELFRING_VECTOR_CNTL 2 0x3a104 2 0 4294967295 MISC_DB_MNTR_INTR_DIS 0 0 MISC_DB_MNTR_INTR_DIS_ 0 0 ixBIF_RAS_LEAF0_CTRL 2 0x39000 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixBIF_RAS_LEAF1_CTRL 2 0x39004 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixBIF_RAS_LEAF2_CTRL 2 0x39008 24 0 4294967295 POISON_DET_EN 0 0 POISON_ERREVENT_EN 0 0 POISON_STALL_EN 0 0 PARITY_DET_EN 0 0 PARITY_ERREVENT_EN 0 0 PARITY_STALL_EN 0 0 ERR_EVENT_RECV 0 0 LINK_DIS_RECV 0 0 POISON_ERR_DET 0 0 PARITY_ERR_DET 0 0 ERR_EVENT_SENT 0 0 EGRESS_STALLED 0 0 POISON_DET_EN_ 0 0 POISON_ERREVENT_EN_ 1 1 POISON_STALL_EN_ 2 2 PARITY_DET_EN_ 4 4 PARITY_ERREVENT_EN_ 5 5 PARITY_STALL_EN_ 6 6 ERR_EVENT_RECV_ 16 16 LINK_DIS_RECV_ 17 17 POISON_ERR_DET_ 18 18 PARITY_ERR_DET_ 19 19 ERR_EVENT_SENT_ 20 20 EGRESS_STALLED_ 21 21 ixBIF_RAS_MISC_CTRL 2 0x39100 2 0 4294967295 LINKDIS_TRIG_ERREVENT_EN 0 0 LINKDIS_TRIG_ERREVENT_EN_ 0 0 ixBIF_IOHUB_RAS_IH_CNTL 2 0x39ff8 2 0 4294967295 RAS_IH_INTR_EN 0 0 RAS_IH_INTR_EN_ 0 0 ixBIF_RAS_VWR_FROM_IOHUB 2 0x39ffc 2 0 4294967295 RAS_IH_INTR_TRIG 0 0 RAS_IH_INTR_TRIG_ 0 0 ixRCC_PFC_LTR_CNTL 2 0x100 12 0 4294967295 SNOOP_LATENCY_VALUE 0 0 SNOOP_LATENCY_SCALE 0 0 SNOOP_REQUIREMENT 0 0 NONSNOOP_LATENCY_VALUE 0 0 NONSNOOP_LATENCY_SCALE 0 0 NONSNOOP_REQUIREMENT 0 0 SNOOP_LATENCY_VALUE_ 0 9 SNOOP_LATENCY_SCALE_ 10 12 SNOOP_REQUIREMENT_ 15 15 NONSNOOP_LATENCY_VALUE_ 16 25 NONSNOOP_LATENCY_SCALE_ 26 28 NONSNOOP_REQUIREMENT_ 31 31 ixRCC_PFC_PME_RESTORE 2 0x104 4 0 4294967295 PME_RESTORE_PME_EN 0 0 PME_RESTORE_PME_STATUS 0 0 PME_RESTORE_PME_EN_ 0 0 PME_RESTORE_PME_STATUS_ 8 8 ixRCC_PFC_STICKY_RESTORE_0 2 0x108 16 0 4294967295 RESTORE_PSN_ERR_STATUS 0 0 RESTORE_CPL_TIMEOUT_STATUS 0 0 RESTORE_CPL_ABORT_ERR_STATUS 0 0 RESTORE_UNEXP_CPL_STATUS 0 0 RESTORE_MAL_TLP_STATUS 0 0 RESTORE_ECRC_ERR_STATUS 0 0 RESTORE_UNSUPP_REQ_ERR_STATUS 0 0 RESTORE_ADVISORY_NONFATAL_ERR_STATUS 0 0 RESTORE_PSN_ERR_STATUS_ 0 0 RESTORE_CPL_TIMEOUT_STATUS_ 1 1 RESTORE_CPL_ABORT_ERR_STATUS_ 2 2 RESTORE_UNEXP_CPL_STATUS_ 3 3 RESTORE_MAL_TLP_STATUS_ 4 4 RESTORE_ECRC_ERR_STATUS_ 5 5 RESTORE_UNSUPP_REQ_ERR_STATUS_ 6 6 RESTORE_ADVISORY_NONFATAL_ERR_STATUS_ 7 7 ixRCC_PFC_STICKY_RESTORE_1 2 0x10c 2 0 4294967295 RESTORE_TLP_HDR_0 0 0 RESTORE_TLP_HDR_0_ 0 31 ixRCC_PFC_STICKY_RESTORE_2 2 0x110 2 0 4294967295 RESTORE_TLP_HDR_1 0 0 RESTORE_TLP_HDR_1_ 0 31 ixRCC_PFC_STICKY_RESTORE_3 2 0x114 2 0 4294967295 RESTORE_TLP_HDR_2 0 0 RESTORE_TLP_HDR_2_ 0 31 ixRCC_PFC_STICKY_RESTORE_4 2 0x118 2 0 4294967295 RESTORE_TLP_HDR_3 0 0 RESTORE_TLP_HDR_3_ 0 31 ixRCC_PFC_STICKY_RESTORE_5 2 0x11c 2 0 4294967295 RESTORE_TLP_PREFIX 0 0 RESTORE_TLP_PREFIX_ 0 31 ixRCC_PFC_AUXPWR_CNTL 2 0x120 4 0 4294967295 AUX_CURRENT_OVERRIDE 0 0 AUX_POWER_DETECTED_OVERRIDE 0 0 AUX_CURRENT_OVERRIDE_ 0 2 AUX_POWER_DETECTED_OVERRIDE_ 3 3 ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 2 0x100 12 0 4294967295 SNOOP_LATENCY_VALUE 0 0 SNOOP_LATENCY_SCALE 0 0 SNOOP_REQUIREMENT 0 0 NONSNOOP_LATENCY_VALUE 0 0 NONSNOOP_LATENCY_SCALE 0 0 NONSNOOP_REQUIREMENT 0 0 SNOOP_LATENCY_VALUE_ 0 9 SNOOP_LATENCY_SCALE_ 10 12 SNOOP_REQUIREMENT_ 15 15 NONSNOOP_LATENCY_VALUE_ 16 25 NONSNOOP_LATENCY_SCALE_ 26 28 NONSNOOP_REQUIREMENT_ 31 31 ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 2 0x104 4 0 4294967295 PME_RESTORE_PME_EN 0 0 PME_RESTORE_PME_STATUS 0 0 PME_RESTORE_PME_EN_ 0 0 PME_RESTORE_PME_STATUS_ 8 8 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 2 0x108 16 0 4294967295 RESTORE_PSN_ERR_STATUS 0 0 RESTORE_CPL_TIMEOUT_STATUS 0 0 RESTORE_CPL_ABORT_ERR_STATUS 0 0 RESTORE_UNEXP_CPL_STATUS 0 0 RESTORE_MAL_TLP_STATUS 0 0 RESTORE_ECRC_ERR_STATUS 0 0 RESTORE_UNSUPP_REQ_ERR_STATUS 0 0 RESTORE_ADVISORY_NONFATAL_ERR_STATUS 0 0 RESTORE_PSN_ERR_STATUS_ 0 0 RESTORE_CPL_TIMEOUT_STATUS_ 1 1 RESTORE_CPL_ABORT_ERR_STATUS_ 2 2 RESTORE_UNEXP_CPL_STATUS_ 3 3 RESTORE_MAL_TLP_STATUS_ 4 4 RESTORE_ECRC_ERR_STATUS_ 5 5 RESTORE_UNSUPP_REQ_ERR_STATUS_ 6 6 RESTORE_ADVISORY_NONFATAL_ERR_STATUS_ 7 7 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 2 0x10c 2 0 4294967295 RESTORE_TLP_HDR_0 0 0 RESTORE_TLP_HDR_0_ 0 31 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 2 0x110 2 0 4294967295 RESTORE_TLP_HDR_1 0 0 RESTORE_TLP_HDR_1_ 0 31 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 2 0x114 2 0 4294967295 RESTORE_TLP_HDR_2 0 0 RESTORE_TLP_HDR_2_ 0 31 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 2 0x118 2 0 4294967295 RESTORE_TLP_HDR_3 0 0 RESTORE_TLP_HDR_3_ 0 31 ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 2 0x11c 2 0 4294967295 RESTORE_TLP_PREFIX 0 0 RESTORE_TLP_PREFIX_ 0 31 ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 2 0x120 4 0 4294967295 AUX_CURRENT_OVERRIDE 0 0 AUX_POWER_DETECTED_OVERRIDE 0 0 AUX_CURRENT_OVERRIDE_ 0 2 AUX_POWER_DETECTED_OVERRIDE_ 3 3 ixPCIEMSIX_VECT0_ADDR_LO 2 0x0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT0_ADDR_HI 2 0x4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT0_MSG_DATA 2 0x8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT0_CONTROL 2 0xc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT1_ADDR_LO 2 0x10 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT1_ADDR_HI 2 0x14 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT1_MSG_DATA 2 0x18 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT1_CONTROL 2 0x1c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT2_ADDR_LO 2 0x20 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT2_ADDR_HI 2 0x24 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT2_MSG_DATA 2 0x28 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT2_CONTROL 2 0x2c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT3_ADDR_LO 2 0x30 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT3_ADDR_HI 2 0x34 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT3_MSG_DATA 2 0x38 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT3_CONTROL 2 0x3c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT4_ADDR_LO 2 0x40 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT4_ADDR_HI 2 0x44 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT4_MSG_DATA 2 0x48 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT4_CONTROL 2 0x4c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT5_ADDR_LO 2 0x50 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT5_ADDR_HI 2 0x54 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT5_MSG_DATA 2 0x58 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT5_CONTROL 2 0x5c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT6_ADDR_LO 2 0x60 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT6_ADDR_HI 2 0x64 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT6_MSG_DATA 2 0x68 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT6_CONTROL 2 0x6c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT7_ADDR_LO 2 0x70 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT7_ADDR_HI 2 0x74 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT7_MSG_DATA 2 0x78 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT7_CONTROL 2 0x7c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT8_ADDR_LO 2 0x80 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT8_ADDR_HI 2 0x84 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT8_MSG_DATA 2 0x88 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT8_CONTROL 2 0x8c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT9_ADDR_LO 2 0x90 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT9_ADDR_HI 2 0x94 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT9_MSG_DATA 2 0x98 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT9_CONTROL 2 0x9c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT10_ADDR_LO 2 0xa0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT10_ADDR_HI 2 0xa4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT10_MSG_DATA 2 0xa8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT10_CONTROL 2 0xac 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT11_ADDR_LO 2 0xb0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT11_ADDR_HI 2 0xb4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT11_MSG_DATA 2 0xb8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT11_CONTROL 2 0xbc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT12_ADDR_LO 2 0xc0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT12_ADDR_HI 2 0xc4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT12_MSG_DATA 2 0xc8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT12_CONTROL 2 0xcc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT13_ADDR_LO 2 0xd0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT13_ADDR_HI 2 0xd4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT13_MSG_DATA 2 0xd8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT13_CONTROL 2 0xdc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT14_ADDR_LO 2 0xe0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT14_ADDR_HI 2 0xe4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT14_MSG_DATA 2 0xe8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT14_CONTROL 2 0xec 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT15_ADDR_LO 2 0xf0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT15_ADDR_HI 2 0xf4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT15_MSG_DATA 2 0xf8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT15_CONTROL 2 0xfc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT16_ADDR_LO 2 0x100 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT16_ADDR_HI 2 0x104 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT16_MSG_DATA 2 0x108 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT16_CONTROL 2 0x10c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT17_ADDR_LO 2 0x110 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT17_ADDR_HI 2 0x114 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT17_MSG_DATA 2 0x118 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT17_CONTROL 2 0x11c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT18_ADDR_LO 2 0x120 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT18_ADDR_HI 2 0x124 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT18_MSG_DATA 2 0x128 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT18_CONTROL 2 0x12c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT19_ADDR_LO 2 0x130 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT19_ADDR_HI 2 0x134 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT19_MSG_DATA 2 0x138 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT19_CONTROL 2 0x13c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT20_ADDR_LO 2 0x140 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT20_ADDR_HI 2 0x144 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT20_MSG_DATA 2 0x148 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT20_CONTROL 2 0x14c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT21_ADDR_LO 2 0x150 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT21_ADDR_HI 2 0x154 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT21_MSG_DATA 2 0x158 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT21_CONTROL 2 0x15c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT22_ADDR_LO 2 0x160 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT22_ADDR_HI 2 0x164 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT22_MSG_DATA 2 0x168 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT22_CONTROL 2 0x16c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT23_ADDR_LO 2 0x170 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT23_ADDR_HI 2 0x174 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT23_MSG_DATA 2 0x178 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT23_CONTROL 2 0x17c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT24_ADDR_LO 2 0x180 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT24_ADDR_HI 2 0x184 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT24_MSG_DATA 2 0x188 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT24_CONTROL 2 0x18c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT25_ADDR_LO 2 0x190 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT25_ADDR_HI 2 0x194 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT25_MSG_DATA 2 0x198 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT25_CONTROL 2 0x19c 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT26_ADDR_LO 2 0x1a0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT26_ADDR_HI 2 0x1a4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT26_MSG_DATA 2 0x1a8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT26_CONTROL 2 0x1ac 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT27_ADDR_LO 2 0x1b0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT27_ADDR_HI 2 0x1b4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT27_MSG_DATA 2 0x1b8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT27_CONTROL 2 0x1bc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT28_ADDR_LO 2 0x1c0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT28_ADDR_HI 2 0x1c4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT28_MSG_DATA 2 0x1c8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT28_CONTROL 2 0x1cc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT29_ADDR_LO 2 0x1d0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT29_ADDR_HI 2 0x1d4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT29_MSG_DATA 2 0x1d8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT29_CONTROL 2 0x1dc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT30_ADDR_LO 2 0x1e0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT30_ADDR_HI 2 0x1e4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT30_MSG_DATA 2 0x1e8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT30_CONTROL 2 0x1ec 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_VECT31_ADDR_LO 2 0x1f0 2 0 4294967295 MSG_ADDR_LO 0 0 MSG_ADDR_LO_ 2 31 ixPCIEMSIX_VECT31_ADDR_HI 2 0x1f4 2 0 4294967295 MSG_ADDR_HI 0 0 MSG_ADDR_HI_ 0 31 ixPCIEMSIX_VECT31_MSG_DATA 2 0x1f8 2 0 4294967295 MSG_DATA 0 0 MSG_DATA_ 0 31 ixPCIEMSIX_VECT31_CONTROL 2 0x1fc 2 0 4294967295 MASK_BIT 0 0 MASK_BIT_ 0 0 ixPCIEMSIX_PBA 2 0x0 2 0 4294967295 MSIX_PENDING_BITS 0 0 MSIX_PENDING_BITS_ 0 31 ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 2 0x10000 36 0 4294967295 HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SOCCLK_DS_EN 0 0 HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 0 0 HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 1 1 HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 2 2 HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 3 3 HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 4 4 HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 5 5 HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 6 6 HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 7 7 DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 16 16 DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 17 17 DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 18 18 DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 19 19 DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 20 20 DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 21 21 DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 22 22 DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 23 23 SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_ 28 28 SYSHUB_SOCCLK_DS_EN_ 31 31 ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 2 0x10004 2 0 4294967295 SYSHUB_SOCCLK_DS_TIMER 0 0 SYSHUB_SOCCLK_DS_TIMER_ 0 15 ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 2 0x10008 10 0 4294967295 SYSHUB_bgen_socclk_HST_SW0_bypass_en 0 0 SYSHUB_bgen_socclk_HST_SW1_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW0_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW1_bypass_en 0 0 SYSHUB_bgen_socclk_DMA_SW2_bypass_en 0 0 SYSHUB_bgen_socclk_HST_SW0_bypass_en_ 0 0 SYSHUB_bgen_socclk_HST_SW1_bypass_en_ 1 1 SYSHUB_bgen_socclk_DMA_SW0_bypass_en_ 15 15 SYSHUB_bgen_socclk_DMA_SW1_bypass_en_ 16 16 SYSHUB_bgen_socclk_DMA_SW2_bypass_en_ 17 17 ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 2 0x1000c 10 0 4294967295 SYSHUB_bgen_socclk_HST_SW0_imm_en 0 0 SYSHUB_bgen_socclk_HST_SW1_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW0_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW1_imm_en 0 0 SYSHUB_bgen_socclk_DMA_SW2_imm_en 0 0 SYSHUB_bgen_socclk_HST_SW0_imm_en_ 0 0 SYSHUB_bgen_socclk_HST_SW1_imm_en_ 1 1 SYSHUB_bgen_socclk_DMA_SW0_imm_en_ 15 15 SYSHUB_bgen_socclk_DMA_SW1_imm_en_ 16 16 SYSHUB_bgen_socclk_DMA_SW2_imm_en_ 17 17 ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 2 0x10010 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 2 0x10014 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 2 0x10018 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 2 0x1001c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 2 0x10020 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 2 0x10024 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 2 0x10028 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 2 0x1002c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 2 0x10030 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 2 0x10034 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 2 0x10300 6 0 4294967295 SYSHUB_CG_EN 0 0 SYSHUB_CG_IDLE_TIMER 0 0 SYSHUB_CG_WAKEUP_TIMER 0 0 SYSHUB_CG_EN_ 0 0 SYSHUB_CG_IDLE_TIMER_ 8 15 SYSHUB_CG_WAKEUP_TIMER_ 16 23 ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 2 0x10308 34 0 4294967295 SYSHUB_TRANS_IDLE_VF0 0 0 SYSHUB_TRANS_IDLE_VF1 0 0 SYSHUB_TRANS_IDLE_VF2 0 0 SYSHUB_TRANS_IDLE_VF3 0 0 SYSHUB_TRANS_IDLE_VF4 0 0 SYSHUB_TRANS_IDLE_VF5 0 0 SYSHUB_TRANS_IDLE_VF6 0 0 SYSHUB_TRANS_IDLE_VF7 0 0 SYSHUB_TRANS_IDLE_VF8 0 0 SYSHUB_TRANS_IDLE_VF9 0 0 SYSHUB_TRANS_IDLE_VF10 0 0 SYSHUB_TRANS_IDLE_VF11 0 0 SYSHUB_TRANS_IDLE_VF12 0 0 SYSHUB_TRANS_IDLE_VF13 0 0 SYSHUB_TRANS_IDLE_VF14 0 0 SYSHUB_TRANS_IDLE_VF15 0 0 SYSHUB_TRANS_IDLE_PF 0 0 SYSHUB_TRANS_IDLE_VF0_ 0 0 SYSHUB_TRANS_IDLE_VF1_ 1 1 SYSHUB_TRANS_IDLE_VF2_ 2 2 SYSHUB_TRANS_IDLE_VF3_ 3 3 SYSHUB_TRANS_IDLE_VF4_ 4 4 SYSHUB_TRANS_IDLE_VF5_ 5 5 SYSHUB_TRANS_IDLE_VF6_ 6 6 SYSHUB_TRANS_IDLE_VF7_ 7 7 SYSHUB_TRANS_IDLE_VF8_ 8 8 SYSHUB_TRANS_IDLE_VF9_ 9 9 SYSHUB_TRANS_IDLE_VF10_ 10 10 SYSHUB_TRANS_IDLE_VF11_ 11 11 SYSHUB_TRANS_IDLE_VF12_ 12 12 SYSHUB_TRANS_IDLE_VF13_ 13 13 SYSHUB_TRANS_IDLE_VF14_ 14 14 SYSHUB_TRANS_IDLE_VF15_ 15 15 SYSHUB_TRANS_IDLE_PF_ 16 16 ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 2 0x1030c 2 0 4294967295 SYSHUB_HP_TIMER 0 0 SYSHUB_HP_TIMER_ 0 31 ixSYSHUBMMREGIND_SYSHUB_SCRATCH 2 0x10f00 2 0 4294967295 SCRATCH 0 0 SCRATCH_ 0 31 ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 2 0x11000 36 0 4294967295 HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE 0 0 SYSHUB_SHUBCLK_DS_EN 0 0 HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 0 0 HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 1 1 HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 2 2 HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 3 3 HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 4 4 HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 5 5 HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 6 6 HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 7 7 DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 16 16 DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 17 17 DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 18 18 DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 19 19 DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 20 20 DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 21 21 DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 22 22 DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 23 23 SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_ 28 28 SYSHUB_SHUBCLK_DS_EN_ 31 31 ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 2 0x11004 2 0 4294967295 SYSHUB_SHUBCLK_DS_TIMER 0 0 SYSHUB_SHUBCLK_DS_TIMER_ 0 15 ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 2 0x11008 4 0 4294967295 SYSHUB_bgen_shubclk_DMA_SW0_bypass_en 0 0 SYSHUB_bgen_shubclk_DMA_SW1_bypass_en 0 0 SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_ 15 15 SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_ 16 16 ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 2 0x1100c 4 0 4294967295 SYSHUB_bgen_shubclk_DMA_SW0_imm_en 0 0 SYSHUB_bgen_shubclk_DMA_SW1_imm_en 0 0 SYSHUB_bgen_shubclk_DMA_SW0_imm_en_ 15 15 SYSHUB_bgen_shubclk_DMA_SW1_imm_en_ 16 16 ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 2 0x11010 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 2 0x11014 6 0 4294967295 QOS_CNTL_MODE 0 0 QOS_MAX_VALUE 0 0 QOS_MIN_VALUE 0 0 QOS_CNTL_MODE_ 0 0 QOS_MAX_VALUE_ 1 4 QOS_MIN_VALUE_ 5 8 ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 2 0x11018 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 2 0x1101c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 2 0x11020 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 2 0x11024 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 2 0x11028 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 2 0x1102c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 2 0x11030 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 2 0x11034 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 2 0x11038 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31 ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 2 0x1103c 12 0 4294967295 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 0 0 QOS_STATIC_OVERRIDE_EN 0 0 QOS_STATIC_OVERRIDE_VALUE 0 0 READ_WRR_WEIGHT 0 0 WRITE_WRR_WEIGHT 0 0 FLR_ON_RS_RESET_EN_ 0 0 LKRST_ON_RS_RESET_EN_ 1 1 QOS_STATIC_OVERRIDE_EN_ 8 8 QOS_STATIC_OVERRIDE_VALUE_ 9 12 READ_WRR_WEIGHT_ 16 23 WRITE_WRR_WEIGHT_ 24 31