17627 cfgBIF_CFG_DEV0_RC_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_RC_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_RC_COMMAND 3 0x4 11 0 4294967295 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_RC_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_RC_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_RC_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_RC_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_RC_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_RC_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_RC_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_RC_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIF_CFG_DEV0_RC_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_RC_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_RC_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_RC_DEVICE_CAP 3 0x5c 7 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_RC_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_RC_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_RC_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_RC_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIF_CFG_DEV0_RC_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIF_CFG_DEV0_RC_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIF_CFG_DEV0_RC_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIF_CFG_DEV0_RC_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIF_CFG_DEV0_RC_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_RC_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_RC_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_RC_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_RC_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_RC_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_RC_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV1_RC_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV1_RC_COMMAND 3 0x4 11 0 4294967295 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV1_RC_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV1_RC_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV1_RC_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV1_RC_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV1_RC_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV1_RC_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV1_RC_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV1_RC_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV1_RC_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV1_RC_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV1_RC_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIF_CFG_DEV1_RC_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV1_RC_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV1_RC_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV1_RC_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIF_CFG_DEV1_RC_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIF_CFG_DEV1_RC_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV1_RC_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV1_RC_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV1_RC_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIF_CFG_DEV1_RC_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV1_RC_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV1_RC_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV1_RC_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV1_RC_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV1_RC_DEVICE_CAP 3 0x5c 7 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV1_RC_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIF_CFG_DEV1_RC_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV1_RC_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV1_RC_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV1_RC_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV1_RC_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIF_CFG_DEV1_RC_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIF_CFG_DEV1_RC_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIF_CFG_DEV1_RC_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIF_CFG_DEV1_RC_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIF_CFG_DEV1_RC_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIF_CFG_DEV1_RC_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV1_RC_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV1_RC_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV1_RC_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV1_RC_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV1_RC_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV1_RC_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV1_RC_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV1_RC_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV1_RC_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV1_RC_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV1_RC_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV1_RC_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV1_RC_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV1_RC_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV1_RC_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV1_RC_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV1_RC_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV1_RC_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV1_RC_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV1_RC_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST 3 0x2c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL 3 0x2c4 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS 3 0x2c6 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 3 0x2c8 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 3 0x2cc 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 3 0x320 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 3 0x324 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 3 0x330 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 3 0x334 4 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 3 0x338 6 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 3 0x33a 1 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 3 0x33c 1 0 4294967295 SRIOV_INITIAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 3 0x33e 1 0 4294967295 SRIOV_TOTAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 3 0x340 1 0 4294967295 SRIOV_NUM_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 3 0x342 1 0 4294967295 SRIOV_FUNC_DEP_LINK 0 7 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 3 0x344 1 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 3 0x346 1 0 4294967295 SRIOV_VF_STRIDE 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 3 0x34a 1 0 4294967295 SRIOV_VF_DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 3 0x34c 1 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 3 0x350 1 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 3 0x354 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 3 0x358 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 3 0x35c 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 3 0x360 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 3 0x364 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 3 0x368 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 0x36c 2 0 4294967295 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 3 0x4c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP 3 0x4c4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL 3 0x4c8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP 3 0x4cc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL 3 0x4d0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP 3 0x4d4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL 3 0x4d8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP 3 0x4dc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL 3 0x4e0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP 3 0x4e4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL 3 0x4e8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP 3 0x4ec 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL 3 0x4f0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 3 0x500 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 3 0x504 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 3 0x508 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 3 0x50c 18 0 4294967295 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 3 0x510 18 0 4294967295 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 3 0x514 1 0 4294967295 SOFT_PF_FLR 0 0 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 3 0x518 5 0 4294967295 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 3 0x51c 32 0 4294967295 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 3 0x520 32 0 4294967295 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 3 0x524 3 0 4294967295 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 3 0x528 2 0 4294967295 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 3 0x52c 3 0 4294967295 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 3 0x530 2 0 4294967295 LFB_REGION 0 2 MAX_REGION 4 6 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 3 0x534 2 0 4294967295 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 3 0x538 2 0 4294967295 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 3 0x53c 2 0 4294967295 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 3 0x540 2 0 4294967295 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 3 0x544 2 0 4294967295 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 3 0x548 2 0 4294967295 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 3 0x54c 2 0 4294967295 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 3 0x550 2 0 4294967295 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 3 0x554 2 0 4294967295 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 3 0x558 2 0 4294967295 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 3 0x55c 2 0 4294967295 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 3 0x560 2 0 4294967295 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 3 0x564 2 0 4294967295 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 3 0x568 2 0 4294967295 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 3 0x56c 2 0 4294967295 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 3 0x570 2 0 4294967295 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 3 0x574 2 0 4294967295 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 3 0x578 2 0 4294967295 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 3 0x57c 2 0 4294967295 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 3 0x580 2 0 4294967295 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 3 0x584 2 0 4294967295 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 3 0x588 2 0 4294967295 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 3 0x58c 2 0 4294967295 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 3 0x590 2 0 4294967295 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 3 0x594 2 0 4294967295 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 3 0x598 2 0 4294967295 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 3 0x59c 2 0 4294967295 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 3 0x5a0 2 0 4294967295 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 3 0x5a4 2 0 4294967295 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 3 0x5a8 2 0 4294967295 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 3 0x5ac 2 0 4294967295 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 3 0x5b0 2 0 4294967295 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 3 0x5c0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 3 0x5c4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 3 0x5c8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 3 0x5cc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 3 0x5d0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 3 0x5d4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 3 0x5d8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 3 0x5dc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 3 0x5e0 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 3 0x5f0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 3 0x5f4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 3 0x5f8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 3 0x5fc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 3 0x600 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 3 0x604 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 3 0x608 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 3 0x60c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 3 0x610 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 3 0x620 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 3 0x624 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 3 0x628 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 3 0x62c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 3 0x630 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 3 0x634 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 3 0x638 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 3 0x63c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 3 0x640 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 3 0x650 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 3 0x654 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 3 0x658 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 3 0x65c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 3 0x660 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 3 0x664 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 3 0x668 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 3 0x66c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 3 0x670 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF1_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF1_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF1_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF1_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF1_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF1_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF1_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF1_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST 3 0x2c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL 3 0x2c4 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 cfgBIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS 3 0x2c6 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 3 0x2c8 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 3 0x2cc 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST 3 0x320 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_LTR_CAP 3 0x324 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST 3 0x330 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP 3 0x334 4 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL 3 0x338 6 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS 3 0x33a 1 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS 3 0x33c 1 0 4294967295 SRIOV_INITIAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS 3 0x33e 1 0 4294967295 SRIOV_TOTAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS 3 0x340 1 0 4294967295 SRIOV_NUM_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK 3 0x342 1 0 4294967295 SRIOV_FUNC_DEP_LINK 0 7 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET 3 0x344 1 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE 3 0x346 1 0 4294967295 SRIOV_VF_STRIDE 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID 3 0x34a 1 0 4294967295 SRIOV_VF_DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 3 0x34c 1 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 3 0x350 1 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0 3 0x354 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1 3 0x358 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2 3 0x35c 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3 3 0x360 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4 3 0x364 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5 3 0x368 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 0x36c 2 0 4294967295 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF1_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF1_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 3 0x4c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP 3 0x4c4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL 3 0x4c8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP 3 0x4cc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL 3 0x4d0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP 3 0x4d4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL 3 0x4d8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP 3 0x4dc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL 3 0x4e0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP 3 0x4e4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL 3 0x4e8 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP 3 0x4ec 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL 3 0x4f0 4 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 3 0x500 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 3 0x504 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 3 0x508 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 3 0x50c 18 0 4294967295 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 3 0x510 18 0 4294967295 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 3 0x514 1 0 4294967295 SOFT_PF_FLR 0 0 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 3 0x518 5 0 4294967295 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 3 0x51c 32 0 4294967295 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 3 0x520 32 0 4294967295 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 3 0x524 3 0 4294967295 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 3 0x528 2 0 4294967295 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 3 0x52c 3 0 4294967295 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 3 0x530 2 0 4294967295 LFB_REGION 0 2 MAX_REGION 4 6 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 3 0x534 2 0 4294967295 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 3 0x538 2 0 4294967295 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 3 0x53c 2 0 4294967295 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 3 0x540 2 0 4294967295 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 3 0x544 2 0 4294967295 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 3 0x548 2 0 4294967295 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 3 0x54c 2 0 4294967295 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 3 0x550 2 0 4294967295 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 3 0x554 2 0 4294967295 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 3 0x558 2 0 4294967295 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 3 0x55c 2 0 4294967295 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 3 0x560 2 0 4294967295 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 3 0x564 2 0 4294967295 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 3 0x568 2 0 4294967295 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 3 0x56c 2 0 4294967295 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 3 0x570 2 0 4294967295 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 3 0x574 2 0 4294967295 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 3 0x578 2 0 4294967295 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 3 0x57c 2 0 4294967295 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 3 0x580 2 0 4294967295 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 3 0x584 2 0 4294967295 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 3 0x588 2 0 4294967295 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 3 0x58c 2 0 4294967295 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 3 0x590 2 0 4294967295 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 3 0x594 2 0 4294967295 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 3 0x598 2 0 4294967295 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 3 0x59c 2 0 4294967295 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 3 0x5a0 2 0 4294967295 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 3 0x5a4 2 0 4294967295 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 3 0x5a8 2 0 4294967295 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 3 0x5ac 2 0 4294967295 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 3 0x5b0 2 0 4294967295 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 3 0x5c0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 3 0x5c4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 3 0x5c8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 3 0x5cc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 3 0x5d0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 3 0x5d4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 3 0x5d8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 3 0x5dc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 3 0x5e0 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 3 0x5f0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 3 0x5f4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 3 0x5f8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 3 0x5fc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 3 0x600 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 3 0x604 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 3 0x608 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 3 0x60c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 3 0x610 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 3 0x620 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 3 0x624 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 3 0x628 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 3 0x62c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 3 0x630 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 3 0x634 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 3 0x638 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 3 0x63c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 3 0x640 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 3 0x650 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 3 0x654 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 3 0x658 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 3 0x65c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 3 0x660 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 3 0x664 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 3 0x668 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 3 0x66c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 3 0x670 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF2_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF2_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF2_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF2_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF2_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF2_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF2_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF2_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF2_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF2_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF2_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF2_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF2_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF2_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF2_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF2_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF2_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF2_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF2_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF2_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF2_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF2_SBRN 3 0x60 1 0 4294967295 SBRN 0 7 cfgBIF_CFG_DEV0_EPF2_FLADJ 3 0x61 2 0 4294967295 FLADJ 0 5 NFC 6 6 cfgBIF_CFG_DEV0_EPF2_DBESL_DBESLD 3 0x62 2 0 4294967295 DBESL 0 3 DBESLD 4 7 cfgBIF_CFG_DEV0_EPF2_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF2_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF2_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF2_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF2_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF2_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF2_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF2_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF2_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF2_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF2_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF2_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF2_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF2_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF2_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF2_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF2_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF2_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF2_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0 3 0x37c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1 3 0x37e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2 3 0x380 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3 3 0x382 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4 3 0x384 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5 3 0x386 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6 3 0x388 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7 3 0x38a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8 3 0x38c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9 3 0x38e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10 3 0x390 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11 3 0x392 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12 3 0x394 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13 3 0x396 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14 3 0x398 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15 3 0x39a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16 3 0x39c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17 3 0x39e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18 3 0x3a0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19 3 0x3a2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20 3 0x3a4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21 3 0x3a6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22 3 0x3a8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23 3 0x3aa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24 3 0x3ac 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25 3 0x3ae 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26 3 0x3b0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27 3 0x3b2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28 3 0x3b4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29 3 0x3b6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30 3 0x3b8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31 3 0x3ba 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32 3 0x3bc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33 3 0x3be 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34 3 0x3c0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35 3 0x3c2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36 3 0x3c4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37 3 0x3c6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38 3 0x3c8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39 3 0x3ca 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40 3 0x3cc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41 3 0x3ce 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42 3 0x3d0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43 3 0x3d2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44 3 0x3d4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45 3 0x3d6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46 3 0x3d8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47 3 0x3da 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48 3 0x3dc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49 3 0x3de 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50 3 0x3e0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51 3 0x3e2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52 3 0x3e4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53 3 0x3e6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54 3 0x3e8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55 3 0x3ea 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56 3 0x3ec 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57 3 0x3ee 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58 3 0x3f0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59 3 0x3f2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60 3 0x3f4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61 3 0x3f6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62 3 0x3f8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63 3 0x3fa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF3_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF3_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF3_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF3_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF3_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF3_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF3_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF3_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF3_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF3_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF3_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF3_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF3_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF3_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF3_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF3_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF3_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF3_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF3_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF3_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF3_SBRN 3 0x60 1 0 4294967295 SBRN 0 7 cfgBIF_CFG_DEV0_EPF3_FLADJ 3 0x61 2 0 4294967295 FLADJ 0 5 NFC 6 6 cfgBIF_CFG_DEV0_EPF3_DBESL_DBESLD 3 0x62 2 0 4294967295 DBESL 0 3 DBESLD 4 7 cfgBIF_CFG_DEV0_EPF3_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF3_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF3_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF3_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF3_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF3_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF3_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF3_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF3_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF3_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF3_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF3_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF3_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF3_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF3_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF3_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF3_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF3_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF3_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0 3 0x37c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1 3 0x37e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2 3 0x380 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3 3 0x382 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4 3 0x384 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5 3 0x386 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6 3 0x388 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7 3 0x38a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8 3 0x38c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9 3 0x38e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10 3 0x390 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11 3 0x392 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12 3 0x394 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13 3 0x396 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14 3 0x398 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15 3 0x39a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16 3 0x39c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17 3 0x39e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18 3 0x3a0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19 3 0x3a2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20 3 0x3a4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21 3 0x3a6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22 3 0x3a8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23 3 0x3aa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24 3 0x3ac 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25 3 0x3ae 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26 3 0x3b0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27 3 0x3b2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28 3 0x3b4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29 3 0x3b6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30 3 0x3b8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31 3 0x3ba 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32 3 0x3bc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33 3 0x3be 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34 3 0x3c0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35 3 0x3c2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36 3 0x3c4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37 3 0x3c6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38 3 0x3c8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39 3 0x3ca 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40 3 0x3cc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41 3 0x3ce 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42 3 0x3d0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43 3 0x3d2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44 3 0x3d4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45 3 0x3d6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46 3 0x3d8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47 3 0x3da 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48 3 0x3dc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49 3 0x3de 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50 3 0x3e0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51 3 0x3e2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52 3 0x3e4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53 3 0x3e6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54 3 0x3e8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55 3 0x3ea 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56 3 0x3ec 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57 3 0x3ee 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58 3 0x3f0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59 3 0x3f2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60 3 0x3f4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61 3 0x3f6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62 3 0x3f8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63 3 0x3fa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF4_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF4_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF4_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF4_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF4_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF4_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF4_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF4_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF4_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF4_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF4_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF4_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF4_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF4_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF4_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF4_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF4_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF4_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF4_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF4_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF4_SBRN 3 0x60 1 0 4294967295 SBRN 0 7 cfgBIF_CFG_DEV0_EPF4_FLADJ 3 0x61 2 0 4294967295 FLADJ 0 5 NFC 6 6 cfgBIF_CFG_DEV0_EPF4_DBESL_DBESLD 3 0x62 2 0 4294967295 DBESL 0 3 DBESLD 4 7 cfgBIF_CFG_DEV0_EPF4_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF4_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF4_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF4_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF4_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF4_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF4_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF4_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF4_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF4_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF4_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF4_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF4_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF4_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF4_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF4_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF4_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF4_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF4_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0 3 0x37c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1 3 0x37e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2 3 0x380 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3 3 0x382 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4 3 0x384 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5 3 0x386 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6 3 0x388 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7 3 0x38a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8 3 0x38c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9 3 0x38e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10 3 0x390 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11 3 0x392 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12 3 0x394 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13 3 0x396 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14 3 0x398 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15 3 0x39a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16 3 0x39c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17 3 0x39e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18 3 0x3a0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19 3 0x3a2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20 3 0x3a4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21 3 0x3a6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22 3 0x3a8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23 3 0x3aa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24 3 0x3ac 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25 3 0x3ae 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26 3 0x3b0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27 3 0x3b2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28 3 0x3b4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29 3 0x3b6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30 3 0x3b8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31 3 0x3ba 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32 3 0x3bc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33 3 0x3be 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34 3 0x3c0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35 3 0x3c2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36 3 0x3c4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37 3 0x3c6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38 3 0x3c8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39 3 0x3ca 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40 3 0x3cc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41 3 0x3ce 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42 3 0x3d0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43 3 0x3d2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44 3 0x3d4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45 3 0x3d6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46 3 0x3d8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47 3 0x3da 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48 3 0x3dc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49 3 0x3de 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50 3 0x3e0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51 3 0x3e2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52 3 0x3e4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53 3 0x3e6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54 3 0x3e8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55 3 0x3ea 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56 3 0x3ec 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57 3 0x3ee 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58 3 0x3f0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59 3 0x3f2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60 3 0x3f4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61 3 0x3f6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62 3 0x3f8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63 3 0x3fa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF5_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF5_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF5_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF5_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF5_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF5_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF5_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF5_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF5_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF5_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF5_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF5_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF5_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF5_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF5_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF5_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF5_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF5_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF5_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF5_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF5_SBRN 3 0x60 1 0 4294967295 SBRN 0 7 cfgBIF_CFG_DEV0_EPF5_FLADJ 3 0x61 2 0 4294967295 FLADJ 0 5 NFC 6 6 cfgBIF_CFG_DEV0_EPF5_DBESL_DBESLD 3 0x62 2 0 4294967295 DBESL 0 3 DBESLD 4 7 cfgBIF_CFG_DEV0_EPF5_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF5_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF5_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF5_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF5_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF5_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF5_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF5_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF5_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF5_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF5_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF5_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF5_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF5_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF5_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF5_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF5_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF5_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF5_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0 3 0x37c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1 3 0x37e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2 3 0x380 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3 3 0x382 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4 3 0x384 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5 3 0x386 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6 3 0x388 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7 3 0x38a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8 3 0x38c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9 3 0x38e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10 3 0x390 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11 3 0x392 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12 3 0x394 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13 3 0x396 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14 3 0x398 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15 3 0x39a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16 3 0x39c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17 3 0x39e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18 3 0x3a0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19 3 0x3a2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20 3 0x3a4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21 3 0x3a6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22 3 0x3a8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23 3 0x3aa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24 3 0x3ac 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25 3 0x3ae 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26 3 0x3b0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27 3 0x3b2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28 3 0x3b4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29 3 0x3b6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30 3 0x3b8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31 3 0x3ba 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32 3 0x3bc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33 3 0x3be 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34 3 0x3c0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35 3 0x3c2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36 3 0x3c4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37 3 0x3c6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38 3 0x3c8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39 3 0x3ca 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40 3 0x3cc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41 3 0x3ce 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42 3 0x3d0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43 3 0x3d2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44 3 0x3d4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45 3 0x3d6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46 3 0x3d8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47 3 0x3da 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48 3 0x3dc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49 3 0x3de 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50 3 0x3e0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51 3 0x3e2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52 3 0x3e4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53 3 0x3e6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54 3 0x3e8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55 3 0x3ea 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56 3 0x3ec 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57 3 0x3ee 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58 3 0x3f0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59 3 0x3f2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60 3 0x3f4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61 3 0x3f6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62 3 0x3f8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63 3 0x3fa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF6_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF6_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF6_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF6_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF6_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF6_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF6_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF6_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF6_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF6_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF6_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR 3 0x28 1 0 4294967295 CARDBUS_CIS_PTR 0 31 cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF6_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF6_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF6_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF6_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF6_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF6_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF6_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF6_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF6_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF6_SBRN 3 0x60 1 0 4294967295 SBRN 0 7 cfgBIF_CFG_DEV0_EPF6_FLADJ 3 0x61 2 0 4294967295 FLADJ 0 5 NFC 6 6 cfgBIF_CFG_DEV0_EPF6_DBESL_DBESLD 3 0x62 2 0 4294967295 DBESL 0 3 DBESLD 4 7 cfgBIF_CFG_DEV0_EPF6_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF6_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF6_LINK_CNTL 3 0x74 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIF_CFG_DEV0_EPF6_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF6_DEVICE_CAP2 3 0x88 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF6_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF6_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF6_LINK_CAP2 3 0x90 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIF_CFG_DEV0_EPF6_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF6_LINK_STATUS2 3 0x96 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIF_CFG_DEV0_EPF6_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF6_MSI_MSG_CNTL 3 0xa2 7 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA 3 0xaa 1 0 4294967295 MSI_EXT_DATA 0 15 cfgBIF_CFG_DEV0_EPF6_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64 3 0xae 1 0 4294967295 MSI_EXT_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF6_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF6_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF6_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF6_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF6_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF6_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL 3 0x208 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL 3 0x210 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL 3 0x218 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL 3 0x220 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL 3 0x228 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 31 cfgBIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL 3 0x230 4 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0 3 0x37c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1 3 0x37e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2 3 0x380 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3 3 0x382 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4 3 0x384 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5 3 0x386 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6 3 0x388 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7 3 0x38a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8 3 0x38c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9 3 0x38e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10 3 0x390 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11 3 0x392 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12 3 0x394 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13 3 0x396 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14 3 0x398 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15 3 0x39a 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16 3 0x39c 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17 3 0x39e 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18 3 0x3a0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19 3 0x3a2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20 3 0x3a4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21 3 0x3a6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22 3 0x3a8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23 3 0x3aa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24 3 0x3ac 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25 3 0x3ae 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26 3 0x3b0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27 3 0x3b2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28 3 0x3b4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29 3 0x3b6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30 3 0x3b8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31 3 0x3ba 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32 3 0x3bc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33 3 0x3be 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34 3 0x3c0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35 3 0x3c2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36 3 0x3c4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37 3 0x3c6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38 3 0x3c8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39 3 0x3ca 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40 3 0x3cc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41 3 0x3ce 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42 3 0x3d0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43 3 0x3d2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44 3 0x3d4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45 3 0x3d6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46 3 0x3d8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47 3 0x3da 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48 3 0x3dc 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49 3 0x3de 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50 3 0x3e0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51 3 0x3e2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52 3 0x3e4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53 3 0x3e6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54 3 0x3e8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55 3 0x3ea 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56 3 0x3ec 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57 3 0x3ee 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58 3 0x3f0 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59 3 0x3f2 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60 3 0x3f4 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61 3 0x3f6 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62 3 0x3f8 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63 3 0x3fa 2 0 4294967295 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 cfgBIFPLR0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR0_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR0_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR0_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR0_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR0_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR0_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR0_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR0_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR0_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR0_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR0_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR0_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR0_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR0_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR0_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR0_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR0_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR0_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR0_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR0_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR0_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR0_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR0_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR0_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR0_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR0_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR0_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR0_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR0_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR0_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR0_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR0_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR0_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR0_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR0_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR0_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR0_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR0_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR0_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR0_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR0_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR0_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR0_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR0_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR0_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR0_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR0_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR0_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR0_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR0_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR0_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR0_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR0_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR0_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR0_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR0_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR0_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR0_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR0_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR0_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR0_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR0_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR0_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR0_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR0_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR0_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR0_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR0_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR0_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR0_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR0_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR0_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR0_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR0_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR0_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR0_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR0_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR0_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR0_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR0_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR0_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR0_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR0_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR0_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR0_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR0_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR0_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR1_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR1_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR1_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR1_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR1_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR1_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR1_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR1_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR1_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR1_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR1_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR1_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR1_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR1_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR1_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR1_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR1_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR1_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR1_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR1_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR1_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR1_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR1_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR1_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR1_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR1_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR1_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR1_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR1_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR1_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR1_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR1_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR1_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR1_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR1_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR1_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR1_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR1_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR1_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR1_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR1_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR1_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR1_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR1_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR1_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR1_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR1_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR1_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR1_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR1_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR1_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR1_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR1_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR1_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR1_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR1_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR1_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR1_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR1_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR1_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR1_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR1_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR1_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR1_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR1_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR1_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR1_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR1_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR1_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR1_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR1_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR1_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR1_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR1_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR1_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR1_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR1_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR1_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR1_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR1_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR1_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR1_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR1_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR1_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR1_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR1_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR1_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR1_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR1_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR1_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR1_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR1_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR1_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR1_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR1_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR1_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR1_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR1_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR1_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR1_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR1_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR1_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR1_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR1_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR1_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR1_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR1_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR1_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR1_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR1_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR1_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR1_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR1_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR1_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR1_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR1_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR1_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR1_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR1_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR1_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR1_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR1_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR1_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR1_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR1_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR1_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR1_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR1_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR1_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR1_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR1_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR1_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR1_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR1_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR1_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR1_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR1_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR1_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR1_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR2_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR2_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR2_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR2_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR2_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR2_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR2_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR2_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR2_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR2_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR2_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR2_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR2_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR2_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR2_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR2_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR2_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR2_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR2_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR2_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR2_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR2_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR2_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR2_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR2_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR2_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR2_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR2_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR2_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR2_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR2_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR2_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR2_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR2_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR2_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR2_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR2_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR2_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR2_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR2_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR2_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR2_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR2_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR2_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR2_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR2_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR2_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR2_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR2_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR2_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR2_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR2_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR2_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR2_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR2_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR2_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR2_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR2_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR2_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR2_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR2_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR2_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR2_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR2_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR2_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR2_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR2_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR2_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR2_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR2_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR2_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR2_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR2_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR2_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR2_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR2_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR2_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR2_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR2_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR2_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR2_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR2_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR2_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR2_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR2_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR2_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR2_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR2_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR2_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR2_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR2_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR2_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR2_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR2_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR2_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR2_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR2_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR2_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR2_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR2_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR2_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR2_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR2_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR2_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR2_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR2_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR2_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR2_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR2_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR2_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR2_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR2_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR2_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR2_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR2_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR2_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR2_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR2_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR2_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR2_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR2_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR2_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR2_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR2_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR2_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR2_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR2_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR2_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR2_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR2_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR2_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR2_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR2_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR2_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR2_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR2_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR2_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR2_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR2_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR3_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR3_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR3_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR3_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR3_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR3_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR3_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR3_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR3_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR3_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR3_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR3_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR3_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR3_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR3_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR3_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR3_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR3_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR3_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR3_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR3_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR3_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR3_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR3_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR3_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR3_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR3_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR3_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR3_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR3_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR3_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR3_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR3_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR3_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR3_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR3_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR3_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR3_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR3_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR3_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR3_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR3_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR3_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR3_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR3_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR3_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR3_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR3_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR3_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR3_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR3_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR3_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR3_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR3_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR3_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR3_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR3_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR3_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR3_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR3_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR3_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR3_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR3_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR3_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR3_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR3_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR3_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR3_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR3_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR3_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR3_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR3_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR3_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR3_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR3_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR3_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR3_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR3_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR3_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR3_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR3_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR3_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR3_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR3_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR3_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR3_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR3_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR3_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR3_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR3_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR3_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR3_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR3_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR3_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR3_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR3_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR3_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR3_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR3_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR3_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR3_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR3_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR3_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR3_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR3_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR3_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR3_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR3_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR3_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR3_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR3_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR3_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR3_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR3_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR3_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR3_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR3_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR3_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR3_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR3_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR3_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR3_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR3_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR3_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR3_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR3_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR3_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR3_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR3_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR3_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR3_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR3_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR3_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR3_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR3_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR3_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR3_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR3_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR3_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR4_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR4_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR4_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR4_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR4_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR4_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR4_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR4_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR4_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR4_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR4_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR4_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR4_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR4_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR4_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR4_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR4_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR4_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR4_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR4_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR4_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR4_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR4_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR4_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR4_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR4_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR4_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR4_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR4_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR4_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR4_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR4_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR4_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR4_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR4_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR4_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR4_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR4_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR4_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR4_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR4_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR4_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR4_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR4_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR4_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR4_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR4_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR4_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR4_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR4_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR4_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR4_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR4_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR4_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR4_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR4_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR4_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR4_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR4_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR4_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR4_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR4_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR4_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR4_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR4_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR4_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR4_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR4_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR4_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR4_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR4_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR4_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR4_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR4_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR4_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR4_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR4_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR4_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR4_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR4_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR4_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR4_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR4_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR4_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR4_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR4_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR4_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR4_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR4_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR4_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR4_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR4_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR4_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR4_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR4_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR4_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR4_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR4_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR4_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR4_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR4_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR4_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR4_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR4_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR4_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR4_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR4_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR4_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR4_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR4_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR4_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR4_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR4_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR4_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR4_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR4_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR4_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR4_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR4_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR4_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR4_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR4_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR4_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR4_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR4_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR4_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR4_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR4_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR4_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR4_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR4_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR4_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR4_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR4_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR4_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR4_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR4_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR4_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR4_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR5_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR5_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR5_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR5_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR5_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR5_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR5_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR5_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR5_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR5_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR5_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR5_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR5_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR5_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR5_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR5_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR5_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR5_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR5_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR5_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR5_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR5_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR5_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR5_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR5_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR5_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR5_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR5_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR5_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR5_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR5_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR5_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR5_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR5_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR5_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR5_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR5_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR5_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR5_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR5_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR5_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR5_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR5_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR5_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR5_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR5_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR5_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR5_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR5_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR5_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR5_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR5_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR5_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR5_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR5_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR5_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR5_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR5_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR5_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR5_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR5_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR5_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR5_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR5_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR5_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR5_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR5_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR5_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR5_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR5_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR5_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR5_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR5_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR5_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR5_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR5_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR5_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR5_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR5_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR5_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR5_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR5_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR5_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR5_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR5_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR5_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR5_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR5_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR5_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR5_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR5_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR5_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR5_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR5_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR5_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR5_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR5_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR5_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR5_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR5_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR5_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR5_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR5_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR5_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR5_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR5_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR5_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR5_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR5_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR5_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR5_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR5_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR5_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR5_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR5_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR5_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR5_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR5_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR5_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR5_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR5_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR5_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR5_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR5_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR5_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR5_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR5_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR5_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR5_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR5_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR5_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR5_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR5_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR5_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR5_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR5_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR5_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR5_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR5_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 cfgBIFPLR6_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIFPLR6_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIFPLR6_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIFPLR6_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR6_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIFPLR6_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIFPLR6_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIFPLR6_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIFPLR6_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIFPLR6_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIFPLR6_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIFPLR6_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIFPLR6_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIFPLR6_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIFPLR6_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIFPLR6_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIFPLR6_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIFPLR6_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIFPLR6_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIFPLR6_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIFPLR6_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIFPLR6_ROM_BASE_ADDR 3 0x38 1 0 4294967295 BASE_ADDR 0 31 cfgBIFPLR6_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIFPLR6_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIFPLR6_IRQ_BRIDGE_CNTL 3 0x3e 12 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 cfgBIFPLR6_EXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgBIFPLR6_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIFPLR6_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR6_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR6_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIFPLR6_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIFPLR6_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR6_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIFPLR6_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIFPLR6_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIFPLR6_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIFPLR6_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIFPLR6_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgBIFPLR6_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIFPLR6_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIFPLR6_SLOT_CNTL 3 0x70 12 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 cfgBIFPLR6_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIFPLR6_ROOT_CNTL 3 0x74 5 0 4294967295 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 cfgBIFPLR6_ROOT_CAP 3 0x76 1 0 4294967295 CRS_SOFTWARE_VISIBILITY 0 0 cfgBIFPLR6_ROOT_STATUS 3 0x78 3 0 4294967295 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 cfgBIFPLR6_DEVICE_CAP2 3 0x7c 20 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 cfgBIFPLR6_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIFPLR6_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIFPLR6_LINK_CAP2 3 0x84 6 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgBIFPLR6_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIFPLR6_LINK_STATUS2 3 0x8a 11 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgBIFPLR6_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIFPLR6_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIFPLR6_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIFPLR6_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR6_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIFPLR6_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIFPLR6_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIFPLR6_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIFPLR6_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIFPLR6_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR6_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIFPLR6_MSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIFPLR6_MSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgBIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIFPLR6_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR6_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIFPLR6_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIFPLR6_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIFPLR6_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIFPLR6_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIFPLR6_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR6_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR6_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR6_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 cfgBIFPLR6_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIFPLR6_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIFPLR6_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgBIFPLR6_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgBIFPLR6_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgBIFPLR6_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIFPLR6_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIFPLR6_PCIE_ADV_ERR_CAP_CNTL 3 0x168 7 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIFPLR6_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_ROOT_ERR_CMD 3 0x17c 3 0 4294967295 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 cfgBIFPLR6_PCIE_ROOT_ERR_STATUS 3 0x180 8 0 4294967295 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 cfgBIFPLR6_PCIE_ERR_SRC_ID 3 0x184 2 0 4294967295 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 cfgBIFPLR6_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_LINK_CNTL3 3 0x274 2 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 cfgBIFPLR6_PCIE_LANE_ERROR_STATUS 3 0x278 1 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 cfgBIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgBIFPLR6_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIFPLR6_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIFPLR6_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIFPLR6_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIFPLR6_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIFPLR6_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIFPLR6_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIFPLR6_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIFPLR6_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIFPLR6_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIFPLR6_PCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgBIFPLR6_PCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgBIFPLR6_PCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgBIFPLR6_PCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgBIFPLR6_PCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgBIFPLR6_PCIE_DPC_ENH_CAP_LIST 3 0x380 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_DPC_CAP_LIST 3 0x384 6 0 4294967295 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 cfgBIFPLR6_PCIE_DPC_CNTL 3 0x386 7 0 4294967295 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 cfgBIFPLR6_PCIE_DPC_STATUS 3 0x388 6 0 4294967295 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 cfgBIFPLR6_PCIE_DPC_ERROR_SOURCE_ID 3 0x38a 1 0 4294967295 DPC_ERROR_SOURCE_ID 0 15 cfgBIFPLR6_PCIE_RP_PIO_STATUS 3 0x38c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR6_PCIE_RP_PIO_MASK 3 0x390 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR6_PCIE_RP_PIO_SEVERITY 3 0x394 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR6_PCIE_RP_PIO_SYSERROR 3 0x398 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR6_PCIE_RP_PIO_EXCEPTION 3 0x39c 9 0 4294967295 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG0 3 0x3a0 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG1 3 0x3a4 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG2 3 0x3a8 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_RP_PIO_HDR_LOG3 3 0x3ac 1 0 4294967295 TLP_HDR 0 31 cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG0 3 0x3b4 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG1 3 0x3b8 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG2 3 0x3bc 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_RP_PIO_PREFIX_LOG3 3 0x3c0 1 0 4294967295 TLP_PREFIX 0 31 cfgBIFPLR6_PCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgBIFPLR6_PCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR6_PCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgBIFPLR6_PCIE_ESM_CTRL 3 0x3d0 1 0 4294967295 ESM_ENABLED 15 15 cfgBIFPLR6_PCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgBIFPLR6_PCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgBIFPLR6_PCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgBIFPLR6_PCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgBIFPLR6_PCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgBIFPLR6_PCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgBIFPLR6_PCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgBIFPLR6_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIFPLR6_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIFPLR6_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIFPLR6_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIFPLR6_PCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIFPLR6_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIFPLR6_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIFPLR6_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIFPLR6_PCIE_CCIX_CAP_LIST 3 0x488 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIFPLR6_PCIE_CCIX_HEADER_1 3 0x48c 3 0 4294967295 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 cfgBIFPLR6_PCIE_CCIX_HEADER_2 3 0x490 1 0 4294967295 CAP_ID 0 15 cfgBIFPLR6_PCIE_CCIX_CAP 3 0x492 5 0 4294967295 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 cfgBIFPLR6_PCIE_CCIX_ESM_REQD_CAP 3 0x494 6 0 4294967295 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 cfgBIFPLR6_PCIE_CCIX_ESM_OPTL_CAP 3 0x498 1 0 4294967295 RESERVED 0 31 cfgBIFPLR6_PCIE_CCIX_ESM_STATUS 3 0x49c 2 0 4294967295 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 cfgBIFPLR6_PCIE_CCIX_ESM_CNTL 3 0x4a0 9 0 4294967295 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 cfgBIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT 3 0x4a4 2 0 4294967295 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT 3 0x4a5 2 0 4294967295 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT 3 0x4a6 2 0 4294967295 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT 3 0x4a7 2 0 4294967295 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT 3 0x4a8 2 0 4294967295 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT 3 0x4a9 2 0 4294967295 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT 3 0x4aa 2 0 4294967295 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT 3 0x4ab 2 0 4294967295 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT 3 0x4ac 2 0 4294967295 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT 3 0x4ad 2 0 4294967295 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT 3 0x4ae 2 0 4294967295 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT 3 0x4af 2 0 4294967295 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT 3 0x4b0 2 0 4294967295 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT 3 0x4b1 2 0 4294967295 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT 3 0x4b2 2 0 4294967295 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT 3 0x4b3 2 0 4294967295 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT 3 0x4b4 2 0 4294967295 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT 3 0x4b5 2 0 4294967295 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT 3 0x4b6 2 0 4294967295 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT 3 0x4b7 2 0 4294967295 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT 3 0x4b8 2 0 4294967295 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT 3 0x4b9 2 0 4294967295 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT 3 0x4ba 2 0 4294967295 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT 3 0x4bb 2 0 4294967295 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT 3 0x4bc 2 0 4294967295 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT 3 0x4bd 2 0 4294967295 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT 3 0x4be 2 0 4294967295 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT 3 0x4bf 2 0 4294967295 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT 3 0x4c0 2 0 4294967295 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT 3 0x4c1 2 0 4294967295 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT 3 0x4c2 2 0 4294967295 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT 3 0x4c3 2 0 4294967295 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 cfgBIFPLR6_PCIE_CCIX_TRANS_CAP 3 0x4c4 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 cfgBIFPLR6_PCIE_CCIX_TRANS_CNTL 3 0x4c8 1 0 4294967295 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIF_BX_PF0_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 regBIF_BX_PF0_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 regBIF_BX_PF0_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 regBIF_BX_PF0_RSMU_INDEX 0 0x0 1 0 1 RSMU_INDEX 0 31 regBIF_BX_PF0_RSMU_DATA 0 0x1 1 0 1 RSMU_DATA 0 31 regBIF_BX0_PCIE_INDEX 0 0xc 1 0 0 PCIE_INDEX 0 31 regBIF_BX0_PCIE_DATA 0 0xd 1 0 0 PCIE_DATA 0 31 regBIF_BX0_PCIE_INDEX2 0 0xe 1 0 0 PCIE_INDEX2 0 31 regBIF_BX0_PCIE_DATA2 0 0xf 1 0 0 PCIE_DATA2 0 31 regBIF_BX0_SBIOS_SCRATCH_0 0 0x34 1 0 1 SBIOS_SCRATCH_DW 0 31 regBIF_BX0_SBIOS_SCRATCH_1 0 0x35 1 0 1 SBIOS_SCRATCH_DW 0 31 regBIF_BX0_SBIOS_SCRATCH_2 0 0x36 1 0 1 SBIOS_SCRATCH_DW 0 31 regBIF_BX0_SBIOS_SCRATCH_3 0 0x37 1 0 1 SBIOS_SCRATCH_DW 0 31 regBIF_BX0_BIOS_SCRATCH_0 0 0x38 1 0 1 BIOS_SCRATCH_0 0 31 regBIF_BX0_BIOS_SCRATCH_1 0 0x39 1 0 1 BIOS_SCRATCH_1 0 31 regBIF_BX0_BIOS_SCRATCH_2 0 0x3a 1 0 1 BIOS_SCRATCH_2 0 31 regBIF_BX0_BIOS_SCRATCH_3 0 0x3b 1 0 1 BIOS_SCRATCH_3 0 31 regBIF_BX0_BIOS_SCRATCH_4 0 0x3c 1 0 1 BIOS_SCRATCH_4 0 31 regBIF_BX0_BIOS_SCRATCH_5 0 0x3d 1 0 1 BIOS_SCRATCH_5 0 31 regBIF_BX0_BIOS_SCRATCH_6 0 0x3e 1 0 1 BIOS_SCRATCH_6 0 31 regBIF_BX0_BIOS_SCRATCH_7 0 0x3f 1 0 1 BIOS_SCRATCH_7 0 31 regBIF_BX0_BIOS_SCRATCH_8 0 0x40 1 0 1 BIOS_SCRATCH_8 0 31 regBIF_BX0_BIOS_SCRATCH_9 0 0x41 1 0 1 BIOS_SCRATCH_9 0 31 regBIF_BX0_BIOS_SCRATCH_10 0 0x42 1 0 1 BIOS_SCRATCH_10 0 31 regBIF_BX0_BIOS_SCRATCH_11 0 0x43 1 0 1 BIOS_SCRATCH_11 0 31 regBIF_BX0_BIOS_SCRATCH_12 0 0x44 1 0 1 BIOS_SCRATCH_12 0 31 regBIF_BX0_BIOS_SCRATCH_13 0 0x45 1 0 1 BIOS_SCRATCH_13 0 31 regBIF_BX0_BIOS_SCRATCH_14 0 0x46 1 0 1 BIOS_SCRATCH_14 0 31 regBIF_BX0_BIOS_SCRATCH_15 0 0x47 1 0 1 BIOS_SCRATCH_15 0 31 regBIF_BX0_BIF_RLC_INTR_CNTL 0 0x4c 4 0 1 RLC_CMD_COMPLETE 0 0 RLC_HANG_SELF_RECOVERED 1 1 RLC_HANG_NEED_FLR 2 2 RLC_VM_BUSY_TRANSITION 3 3 regBIF_BX0_BIF_VCE_INTR_CNTL 0 0x4d 4 0 1 VCE_CMD_COMPLETE 0 0 VCE_HANG_SELF_RECOVERED 1 1 VCE_HANG_NEED_FLR 2 2 VCE_VM_BUSY_TRANSITION 3 3 regBIF_BX0_BIF_UVD_INTR_CNTL 0 0x4e 5 0 1 UVD_CMD_COMPLETE 0 0 UVD_HANG_SELF_RECOVERED 1 1 UVD_HANG_NEED_FLR 2 2 UVD_VM_BUSY_TRANSITION 3 3 UVD_INST_SEL 28 31 regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0 0x6c 1 0 1 CAM_ADDR0 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0 0x6d 1 0 1 CAM_REMAP_ADDR0 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0 0x6e 1 0 1 CAM_ADDR1 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0 0x6f 1 0 1 CAM_REMAP_ADDR1 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0 0x70 1 0 1 CAM_ADDR2 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0 0x71 1 0 1 CAM_REMAP_ADDR2 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0 0x72 1 0 1 CAM_ADDR3 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0 0x73 1 0 1 CAM_REMAP_ADDR3 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0 0x74 1 0 1 CAM_ADDR4 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0 0x75 1 0 1 CAM_REMAP_ADDR4 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0 0x76 1 0 1 CAM_ADDR5 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0 0x77 1 0 1 CAM_REMAP_ADDR5 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0 0x78 1 0 1 CAM_ADDR6 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0 0x79 1 0 1 CAM_REMAP_ADDR6 0 19 regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0 0x7a 1 0 1 CAM_ADDR7 0 19 regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0 0x7b 1 0 1 CAM_REMAP_ADDR7 0 19 regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0 0x7c 1 0 1 CAM_ENABLE 0 7 regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0 0x7d 1 0 1 CAM_ZERO_CPL 0 31 regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0 0x7e 1 0 1 CAM_ONE_CPL 0 31 regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0 0x7f 1 0 1 CAM_PROGRAMMABLE_CPL 0 31 regRCC_STRAP0_RCC_BIF_STRAP0 0 0x0 22 0 2 STRAP_GEN4_DIS_PIN 0 0 STRAP_VGA_DIS_PIN 2 2 STRAP_MEM_AP_SIZE_PIN 3 5 STRAP_BIOS_ROM_EN_PIN 6 6 STRAP_PX_CAPABLE 7 7 STRAP_BIF_KILL_GEN3 8 8 STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN 9 9 STRAP_NBIF_IGNORE_ERR_INFLR 10 10 STRAP_PME_SUPPORT_COMPLIANCE_EN 11 11 STRAP_RX_IGNORE_EP_ERR 12 12 STRAP_RX_IGNORE_MSG_ERR 13 13 STRAP_RX_IGNORE_MAX_PAYLOAD_ERR 14 14 STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN 15 15 STRAP_RX_IGNORE_TC_ERR 16 16 STRAP_RX_IGNORE_TC_ERR_DN 17 17 STRAP_GEN3_DIS 24 24 STRAP_BIF_KILL_GEN4 25 25 STRAP_QUICKSIM_START 26 26 STRAP_NO_RO_ENABLED_P2P_PASSING 27 27 STRAP_CFG0_RD_VF_BUSNUM_CHK_EN 29 29 STRAP_BIGAPU_MODE 30 30 STRAP_LINK_DOWN_RESET_EN 31 31 regRCC_STRAP0_RCC_BIF_STRAP1 0 0x1 21 0 2 ROMSTRAP_VALID 1 1 STRAP_ECRC_INTERMEDIATE_CHK_EN 3 3 STRAP_IGNORE_E2E_PREFIX_UR_SWUS 5 5 STRAP_MARGINING_USES_SOFTWARE 6 6 STRAP_MARGINING_READY 7 7 STRAP_SWUS_APER_EN 8 8 STRAP_SWUS_64BAR_EN 9 9 STRAP_SWUS_AP_SIZE 10 11 STRAP_SWUS_APER_PREFETCHABLE 12 12 STRAP_HWREV_LSB2 13 14 STRAP_SWREV_LSB2 15 16 STRAP_LINK_RST_CFG_ONLY 17 17 STRAP_BIF_IOV_LKRST_DIS 18 18 STRAP_DLF_EN 19 19 STRAP_PHY_16GT_EN 20 20 STRAP_MARGIN_EN 21 21 STRAP_BIF_PSN_UR_RPT_EN 22 22 STRAP_BIF_SLOT_POWER_SUPPORT_EN 23 23 STRAP_GFX_FUNC_LTR_MODE 26 26 STRAP_GSI_SMN_POSTWR_MULTI_EN 27 28 STRAP_DLF_EN_EP 29 29 regRCC_STRAP0_RCC_BIF_STRAP2 0 0x2 14 0 2 STRAP_PCIESWUS_INDEX_APER_RANGE 0 0 STRAP_SUC_IND_ACCESS_DIS 3 3 STRAP_SUM_IND_ACCESS_DIS 4 4 STRAP_ENDP_LINKDOWN_DROP_DMA 5 5 STRAP_SWITCH_LINKDOWN_DROP_DMA 6 6 STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS 8 8 STRAP_ACS_MSKSEV_EP_HIDE_DIS 9 9 STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN 10 11 RESERVED_BIF_STRAP2 13 13 STRAP_LTR_IN_ASPML1_DIS 14 14 STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN 15 15 STRAP_PWRBRK_DEGLITCH_CYCLE 16 23 STRAP_PWRBRK_DEGLITCH_BYPASS 24 24 STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS 31 31 regRCC_STRAP0_RCC_BIF_STRAP3 0 0x3 2 0 2 STRAP_VLINK_ASPM_IDLE_TIMER 0 15 STRAP_VLINK_PM_L1_ENTRY_TIMER 16 31 regRCC_STRAP0_RCC_BIF_STRAP4 0 0x4 2 0 2 STRAP_VLINK_L0S_EXIT_TIMER 0 15 STRAP_VLINK_L1_EXIT_TIMER 16 31 regRCC_STRAP0_RCC_BIF_STRAP5 0 0x5 11 0 2 STRAP_VLINK_LDN_ENTRY_TIMER 0 15 STRAP_VLINK_LDN_ON_SWUS_LDN_EN 16 16 STRAP_VLINK_LDN_ON_SWUS_SECRST_EN 17 17 STRAP_VLINK_ENTER_COMPLIANCE_DIS 18 18 STRAP_IGNORE_PSN_ON_VDM1_DIS 19 19 STRAP_SMN_ERR_STATUS_MASK_EN_UPS 20 20 STRAP_SMN_ERRRSP_DATA_FORCE 22 23 STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE 24 24 STRAP_EMER_POWER_REDUCTION_SUPPORTED 25 26 STRAP_EMER_POWER_REDUCTION_INIT_REQ 27 27 STRAP_PWRBRK_STATUS_TIMER 28 30 regRCC_STRAP0_RCC_BIF_STRAP6 0 0x6 0 0 2 regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0 0x7 10 0 2 STRAP_ARI_EN_DN_DEV0 1 1 STRAP_ACS_EN_DN_DEV0 2 2 STRAP_AER_EN_DN_DEV0 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 4 4 STRAP_DEVICE_ID_DN_DEV0 5 20 STRAP_INTERRUPT_PIN_DN_DEV0 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 28 30 STRAP_EPF0_DUMMY_EN_DEV0 31 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0 0x8 2 0 2 STRAP_SUBSYS_ID_DN_DEV0 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0 16 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0 0x9 20 0 2 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 1 1 STRAP_E2E_PREFIX_EN_DEV0 2 2 STRAP_ECN1P1_EN_DEV0 3 3 STRAP_ECRC_CHECK_EN_DEV0 4 4 STRAP_ERR_REPORTING_DIS_DEV0 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0 8 8 STRAP_EXT_VC_COUNT_DN_DEV0 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 13 13 STRAP_GEN2_COMPLIANCE_DEV0 14 14 STRAP_GEN2_EN_DEV0 15 15 STRAP_GEN3_COMPLIANCE_DEV0 16 16 STRAP_GEN4_COMPLIANCE_DEV0 17 17 STRAP_TARGET_LINK_SPEED_DEV0 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 20 22 STRAP_L0S_EXIT_LATENCY_DEV0 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 26 28 STRAP_L1_EXIT_LATENCY_DEV0 29 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0 0xa 16 0 2 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 1 1 STRAP_LTR_EN_DN_DEV0 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 3 5 STRAP_MSI_EN_DN_DEV0 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0 7 7 STRAP_NO_SOFT_RESET_DN_DEV0 8 8 STRAP_OBFF_SUPPORTED_DEV0 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 21 24 STRAP_PM_SUPPORT_DEV0 25 26 STRAP_PM_SUPPORT_DN_DEV0 27 28 STRAP_ATOMIC_EN_DN_DEV0 29 29 STRAP_PMC_DSI_DN_DEV0 31 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0 0xb 4 0 2 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 24 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0 0xc 18 0 2 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0 18 18 STRAP_VC_EN_DN_DEV0 19 19 STRAP_TwoVC_EN_DEV0 20 20 STRAP_TwoVC_EN_DN_DEV0 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV0 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 29 29 STRAP_MSI_MAP_EN_DEV0 30 30 STRAP_SSID_EN_DEV0 31 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0 0xd 12 0 2 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV0 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0 19 19 regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0 0xe 6 0 2 STRAP_PORT_NUMBER_DEV0 0 7 STRAP_MAJOR_REV_ID_DN_DEV0 8 11 STRAP_MINOR_REV_ID_DN_DEV0 12 15 STRAP_RP_BUSNUM_DEV0 16 23 STRAP_DN_DEVNUM_DEV0 24 28 STRAP_DN_FUNCID_DEV0 29 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0 0xf 4 0 2 STRAP_PWR_BUDGET_DATA_8T0_6_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV0 24 31 regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0 0x10 3 0 2 STRAP_PWR_BUDGET_DATA_8T0_a_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV0 8 15 STRAP_VENDOR_ID_DN_DEV0 16 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0 0x11 8 0 2 STRAP_DEVICE_ID_DEV0_F0 0 15 STRAP_MAJOR_REV_ID_DEV0_F0 16 19 STRAP_MINOR_REV_ID_DEV0_F0 20 23 STRAP_ATI_REV_ID_DEV0_F0 24 27 STRAP_FUNC_EN_DEV0_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 29 29 STRAP_D1_SUPPORT_DEV0_F0 30 30 STRAP_D2_SUPPORT_DEV0_F0 31 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0 0x12 2 0 2 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 16 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0 0x13 3 0 2 STRAP_CLASS_CODE_PIF_DEV0_F0 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0 16 23 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0 0x14 1 0 2 STRAP_VENDOR_ID_DEV0_F0 0 15 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0 0x15 21 0 2 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 1 5 STRAP_64BAR_DIS_DEV0_F0 6 6 STRAP_NO_SOFT_RESET_DEV0_F0 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 14 14 STRAP_ARI_EN_DEV0_F0 15 15 STRAP_AER_EN_DEV0_F0 16 16 STRAP_ACS_EN_DEV0_F0 17 17 STRAP_ATS_EN_DEV0_F0 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 20 20 STRAP_DPA_EN_DEV0_F0 21 21 STRAP_DSN_EN_DEV0_F0 22 22 STRAP_VC_EN_DEV0_F0 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0 24 26 STRAP_PAGE_REQ_EN_DEV0_F0 27 27 STRAP_PASID_EN_DEV0_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 31 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0 0x16 13 0 2 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 1 1 STRAP_SUBSYS_ID_DEV0_F0 2 17 STRAP_MSI_EN_DEV0_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 19 19 STRAP_MSIX_EN_DEV0_F0 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0 21 23 STRAP_PMC_DSI_DEV0_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 27 27 STRAP_VF_RESIZE_BAR_EN_DEV0_F0 28 28 STRAP_CLK_PM_EN_DEV0_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F0 30 30 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0 0x17 7 0 2 STRAP_RESERVED_STRAP4_DEV0_F0 0 9 STRAP_ATOMIC_64BIT_EN_DEV0_F0 20 20 STRAP_ATOMIC_EN_DEV0_F0 21 21 STRAP_FLR_EN_DEV0_F0 22 22 STRAP_PME_SUPPORT_DEV0_F0 23 27 STRAP_INTERRUPT_PIN_DEV0_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0 31 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0 0x18 2 0 2 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0 30 30 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0 0x19 13 0 2 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0 3 3 STRAP_ROM_AP_SIZE_DEV0_F0 4 6 STRAP_IO_BAR_DIS_DEV0_F0 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0 8 8 STRAP_MEM_AP_SIZE_DEV0_F0 9 12 STRAP_REG_AP_SIZE_DEV0_F0 13 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0 19 22 STRAP_VF_REG_AP_SIZE_DEV0_F0 23 25 STRAP_VGA_DIS_DEV0_F0 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 30 31 regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0 0x1a 7 0 2 STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0 0 15 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 18 18 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 19 19 STRAP_VF_REG_PROT_DIS_DEV0_F0 20 20 STRAP_FB_ALWAYS_ON_DEV0_F0 21 21 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 22 23 STRAP_GPUIOV_VSEC_REV_DEV0_F0 24 27 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0 0x1b 7 0 2 STRAP_DEVICE_ID_DEV0_F1 0 15 STRAP_MAJOR_REV_ID_DEV0_F1 16 19 STRAP_MINOR_REV_ID_DEV0_F1 20 23 STRAP_FUNC_EN_DEV0_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 29 29 STRAP_D1_SUPPORT_DEV0_F1 30 30 STRAP_D2_SUPPORT_DEV0_F1 31 31 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10 0 0x1c 0 0 2 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11 0 0x1d 0 0 2 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12 0 0x1e 0 0 2 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13 0 0x1f 3 0 2 STRAP_CLASS_CODE_PIF_DEV0_F1 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1 16 23 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14 0 0x20 1 0 2 STRAP_VENDOR_ID_DEV0_F1 0 15 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0 0x21 16 0 2 STRAP_NO_SOFT_RESET_DEV0_F1 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 14 14 STRAP_AER_EN_DEV0_F1 16 16 STRAP_ACS_EN_DEV0_F1 17 17 STRAP_ATS_EN_DEV0_F1 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 20 20 STRAP_DPA_EN_DEV0_F1 21 21 STRAP_DSN_EN_DEV0_F1 22 22 STRAP_VC_EN_DEV0_F1 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1 24 26 STRAP_PASID_EN_DEV0_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1 31 31 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0 0x22 11 0 2 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 1 1 STRAP_SUBSYS_ID_DEV0_F1 2 17 STRAP_MSI_EN_DEV0_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 19 19 STRAP_MSIX_EN_DEV0_F1 20 20 STRAP_PMC_DSI_DEV0_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 27 27 STRAP_CLK_PM_EN_DEV0_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F1 30 30 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0 0x23 6 0 2 STRAP_ATOMIC_64BIT_EN_DEV0_F1 20 20 STRAP_ATOMIC_EN_DEV0_F1 21 21 STRAP_FLR_EN_DEV0_F1 22 22 STRAP_PME_SUPPORT_DEV0_F1 23 27 STRAP_INTERRUPT_PIN_DEV0_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1 31 31 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0 0x24 2 0 2 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1 30 30 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0 0x25 3 0 2 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 1 1 STRAP_APER0_64BAR_EN_DEV0_F1 2 2 regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0 0x26 0 0 2 regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0 0x27 1 0 2 PCIE_SCRATCH 0 31 regRCC_EP_DEV0_0_EP_PCIE_CNTL 0 0x29 3 0 2 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0 0x2a 6 0 2 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0 0x2b 6 0 2 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0 0x2c 1 0 2 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0 0x2d 1 0 2 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0 0x2e 4 0 2 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0 0x30 10 0 2 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0 0x31 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0 0x31 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0 0x31 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0 0x31 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0 0x32 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0 0x32 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0 0x32 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0 0x32 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0 0x33 1 0 2 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0 0x34 1 0 2 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0 0x36 4 0 2 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0x37 1 0 2 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0 0x37 2 0 2 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0x37 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0x38 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0x38 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0x38 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0x38 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0x39 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0x39 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0x39 1 0 2 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0 0x39 1 0 2 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0 0x3a 1 0 2 PCIEP_RESERVED 0 31 regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0 0x3c 5 0 2 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0 0x3d 3 0 2 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0 0x3e 12 0 2 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0 0x3f 8 0 2 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0 0x40 3 0 2 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0 0x42 1 0 2 PCIE_RESERVED 0 31 regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0 0x43 1 0 2 PCIE_SCRATCH 0 31 regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0 0x45 3 0 2 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0 0x46 1 0 2 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0 0x47 1 0 2 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0 0x48 2 0 2 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0 0x49 4 0 2 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0 0x4a 3 0 2 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0 0x4b 2 0 2 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0 0x4c 1 0 2 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0 0x4f 4 0 2 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0 0x50 5 0 2 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0 0x51 3 0 2 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0 0x52 2 0 2 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0 0x53 1 0 2 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0 0x54 1 0 2 LTR_MSG_INFO_FROM_EP 0 31 regRCC_DEV0_EPF0_0_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_0_RCC_ERR_LOG_1 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_0_RCC_ERR_LOG_2 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_0_RCC_ERR_INT_CNTL 0 0x86 1 0 2 INVALID_REG_ACCESS_IN_SRIOV_INT_EN 0 0 regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0 0x87 2 0 2 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 regRCC_DEV0_0_RCC_RESET_EN 0 0x88 1 0 2 DB_APER_RESET_EN 15 15 regRCC_DEV0_0_RCC_VDM_SUPPORT 0 0x89 5 0 2 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0 0x8a 9 0 2 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0 0x8b 4 0 2 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_DEV0_0_RCC_GPUIOV_REGION 0 0x8c 2 0 2 LFB_REGION 0 2 MAX_REGION 4 6 regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0 0x8d 1 0 2 GPU_HOSTVM_EN 0 0 regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0 0x8e 2 0 2 RCC_CONSOLE_IOV_MODE_ENABLE 0 0 MULTIOS_IH_SUPPORT_EN 1 1 regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0 0x8f 1 0 2 CONSOLE_IOV_FIRST_VF_OFFSET 0 15 regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0 0x8f 1 0 2 CONSOLE_IOV_VF_STRIDE 0 15 regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0 0xbe 2 0 2 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0 0xbf 2 0 2 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_0_RCC_BUS_CNTL 0 0xc1 19 0 2 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV0_0_RCC_CONFIG_CNTL 0 0xc2 3 0 2 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0 0xc6 1 0 2 F0_BASE 0 31 regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0 0xc7 1 0 2 APER_SIZE 0 31 regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0 0xc8 1 0 2 REG_APER_SIZE 0 26 regRCC_DEV0_0_RCC_XDMA_LO 0 0xc9 2 0 2 BIF_XDMA_LOWER_BOUND 0 30 BIF_XDMA_APER_EN 31 31 regRCC_DEV0_0_RCC_XDMA_HI 0 0xca 1 0 2 BIF_XDMA_UPPER_BOUND 0 30 regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0 0xcb 12 0 2 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0 0xcc 1 0 2 ID_MASK 0 7 regRCC_DEV0_0_RCC_BUSNUM_LIST0 0 0xcd 4 0 2 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 regRCC_DEV0_0_RCC_BUSNUM_LIST1 0 0xce 4 0 2 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0 0xcf 4 0 2 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0 0xd0 1 0 2 CHECK_EN 0 0 regRCC_DEV0_0_RCC_HOST_BUSNUM 0 0xd1 1 0 2 HOST_ID 0 15 regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0 0xd2 1 0 2 PEER0_FB_OFFSET_HI 0 19 regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0 0xd3 2 0 2 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0 0xd4 1 0 2 PEER1_FB_OFFSET_HI 0 19 regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0 0xd5 2 0 2 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0 0xd6 1 0 2 PEER2_FB_OFFSET_HI 0 19 regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0 0xd7 2 0 2 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0 0xd8 1 0 2 PEER3_FB_OFFSET_HI 0 19 regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0 0xd9 2 0 2 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0 0xda 4 0 2 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0 0xdb 4 0 2 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0 0xdd 2 0 2 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0 0xde 5 0 2 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0 0xdf 2 0 2 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0 0xe0 1 0 2 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV0_0_RCC_MH_ARB_CNTL 0 0xe1 2 0 2 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regBIF_BX0_CC_BIF_BX_STRAP0 0 0xe2 1 0 2 STRAP_RESERVED 25 31 regBIF_BX0_CC_BIF_BX_PINSTRAP0 0 0xe4 0 0 2 regBIF_BX0_BIF_MM_INDACCESS_CNTL 0 0xe6 1 0 2 MM_INDACCESS_DIS 1 1 regBIF_BX0_BUS_CNTL 0 0xe7 15 0 2 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 HDP_FB_FLUSH_STALL_DOORBELL_DIS 24 24 PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS 25 25 PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS 26 26 MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS 27 27 HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS 28 28 HDP_REG_FLUSH_VF_MASK_EN 29 29 VGAFB_ZERO_BE_WR_EN 30 30 VGAFB_ZERO_BE_RD_EN 31 31 regBIF_BX0_BIF_SCRATCH0 0 0xe8 1 0 2 BIF_SCRATCH0 0 31 regBIF_BX0_BIF_SCRATCH1 0 0xe9 1 0 2 BIF_SCRATCH1 0 31 regBIF_BX0_BX_RESET_EN 0 0xed 1 0 2 RESET_ON_VFENABLE_LOW_EN 16 16 regBIF_BX0_MM_CFGREGS_CNTL 0 0xee 3 0 2 MM_CFG_FUNC_SEL 0 2 MM_CFG_DEV_SEL 6 7 MM_WR_TO_CFG_EN 31 31 regBIF_BX0_BX_RESET_CNTL 0 0xf0 1 0 2 LINK_TRAIN_EN 0 0 regBIF_BX0_INTERRUPT_CNTL 0 0xf1 8 0 2 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 BIF_RB_REQ_NONSNOOP_EN 15 15 DUMMYRD_BYPASS_IN_MSI_EN 16 16 ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS 17 17 BIF_RB_REQ_RELAX_ORDER_EN 18 18 regBIF_BX0_INTERRUPT_CNTL2 0 0xf2 1 0 2 IH_DUMMY_RD_ADDR 0 31 regBIF_BX0_CLKREQB_PAD_CNTL 0 0xf8 13 0 2 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_Y 13 13 regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0 0xfb 10 0 2 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 BIF_RB_MSI_VEC_NOT_ENABLED_MODE 11 11 BIF_RB_SET_OVERFLOW_EN 12 12 ATOMIC_ERR_INT_DIS 13 13 BME_HDL_NONVIR_EN 15 15 HDP_NP_OSTD_LIMIT 16 23 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR 24 24 regBIF_BX0_BIF_DOORBELL_CNTL 0 0xfc 9 0 2 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 DOORBELL_MONITOR_EN 4 4 DB_MNTR_INTGEN_DIS 24 24 DB_MNTR_INTGEN_MODE_0 25 25 DB_MNTR_INTGEN_MODE_1 26 26 DB_MNTR_INTGEN_MODE_2 27 27 regBIF_BX0_BIF_DOORBELL_INT_CNTL 0 0xfd 12 0 2 DOORBELL_INTERRUPT_STATUS 0 0 RAS_CNTLR_INTERRUPT_STATUS 1 1 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS 2 2 DOORBELL_INTERRUPT_CLEAR 16 16 RAS_CNTLR_INTERRUPT_CLEAR 17 17 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR 18 18 DOORBELL_INTERRUPT_DISABLE 24 24 RAS_CNTLR_INTERRUPT_DISABLE 25 25 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE 26 26 SET_DB_INTR_STATUS_WHEN_RB_ENABLE 28 28 SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE 29 29 SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE 30 30 regBIF_BX0_BIF_FB_EN 0 0xff 2 0 2 FB_READ_EN 0 0 FB_WRITE_EN 1 1 regBIF_BX0_BIF_INTR_CNTL 0 0x100 1 0 2 RAS_INTR_VEC_SEL 0 0 regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0 0x109 1 0 2 BIF_MST_TRANS_PENDING 0 30 regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0 0x10a 1 0 2 BIF_SLV_TRANS_PENDING 0 30 regBIF_BX0_MEM_TYPE_CNTL 0 0x111 1 0 2 BF_MEM_PHY_G5_G3 0 0 regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0 0x113 3 0 2 LUT_ENABLE 0 0 MSI_ADDR_MODE 1 1 LUT_BC_MODE 8 8 regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0 0x114 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0 0x115 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0 0x116 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0 0x117 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0 0x118 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0 0x119 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0 0x11a 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0 0x11b 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0 0x11c 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0 0x11d 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0 0x11e 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0 0x11f 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0 0x120 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0 0x121 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0 0x122 1 0 2 ADDR 0 23 regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0 0x123 1 0 2 ADDR 0 23 regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0 0x12d 1 0 2 ADDRESS 2 18 regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0 0x12e 1 0 2 ADDRESS 2 18 regBIF_BX0_BIF_RB_CNTL 0 0x12f 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 BIF_RB_TRAN 17 17 RB_INTR_FIX_PRIORITY 26 28 RB_INTR_ARB_MODE 29 29 RB_RST_BY_FLR_DISABLE 30 30 WPTR_OVERFLOW_CLEAR 31 31 regBIF_BX0_BIF_RB_BASE 0 0x130 1 0 2 ADDR 0 31 regBIF_BX0_BIF_RB_RPTR 0 0x131 1 0 2 OFFSET 2 17 regBIF_BX0_BIF_RB_WPTR 0 0x132 2 0 2 BIF_RB_OVERFLOW 0 0 OFFSET 2 17 regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0 0x133 1 0 2 ADDR 0 7 regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0 0x134 1 0 2 ADDR 2 31 regBIF_BX_PF0_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0 0xf9 1 0 2 HDP_MEM_FLUSH_ONLY_ADDR 0 0 regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0 0xfa 1 0 2 HDP_MEM_INVALIDATE_ONLY_ADDR 0 0 regBIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ 0 0x104 32 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ 0 0x105 32 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0 0x106 32 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0 0x107 32 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF0_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1 0 0x400 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2 0 0x400 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1 0 0x401 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2 0 0x401 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1 0 0x402 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2 0 0x402 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1 0 0x403 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2 0 0x403 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1 0 0x404 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2 0 0x404 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1 0 0x405 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2 0 0x405 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1 0 0x406 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2 0 0x406 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1 0 0x407 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2 0 0x407 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1 0 0x408 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2 0 0x408 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1 0 0x409 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2 0 0x409 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1 0 0x40a 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2 0 0x40a 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1 0 0x40b 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2 0 0x40b 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO 0 0x40c 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1 0 0x40c 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2 0 0x40c 1 0 3 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI 0 0x40d 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1 0 0x40d 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2 0 0x40d 1 0 3 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA 0 0x40e 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1 0 0x40e 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2 0 0x40e 1 0 3 MSG_DATA 0 31 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL 0 0x40f 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1 0 0x40f 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2 0 0x40f 1 0 3 MASK_BIT 0 0 regRCC_DEV0_EPF0_0_GFXMSIX_PBA 0 0x800 4 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regRCC_DEV0_EPF0_0_GFXMSIX_PBA_1 0 0x800 4 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regRCC_DEV0_EPF0_0_GFXMSIX_PBA_2 0 0x800 4 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regGDC0_NGDC_SDP_PORT_CTRL 0 0x4f0ae2 3 0 3 SDP_DISCON_HYSTERESIS 0 7 NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN 15 15 SDP_DISCON_HYSTERESIS_H 16 19 regGDC0_SHUB_REGS_IF_CTL 0 0x4f0ae3 1 0 3 SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS 0 0 regGDC0_NGDC_SDP_PORT_CTRL_SOCCLK 0 0x4f0aed 6 0 3 SDP_DISCON_HYSTERESIS_SOCCLK 0 7 ATDMA_RDRSP_POOL_NUM_SOCCLK 8 15 ATDMA_RDRSP_CRDT_VC0_RSV 16 19 ATDMA_RDRSP_CRDT_VC5_RSV 20 23 ATDMA_RDRSP_CRDT_VC6_RSV 24 27 SDP_DISCON_HYSTERESIS_SOCCLK_H 28 31 regGDC0_NGDC_SDP_PORT_CTRL1_SOCCLK 0 0x4f0aee 6 0 3 ATDMA_REQ_CRDT_VC0_RSV 0 3 ATDMA_REQ_CRDT_VC1_RSV 4 7 ATDMA_REQ_CRDT_VC5_RSV 8 11 ATDMA_REQ_CRDT_VC6_RSV 12 15 ATDMA_ORIGDATA_CRDT_VC0_RSV 16 19 ATDMA_ORIGDATA_CRDT_VC1_RSV 20 23 regGDC0_NBIF_GFX_DOORBELL_STATUS 0 0x4f0aef 1 0 3 NBIF_GFX_DOORBELL_SENT 0 0 regGDC0_BIF_SDMA0_DOORBELL_RANGE 0 0x4f0af0 2 0 3 OFFSET 2 11 SIZE 16 20 regGDC0_BIF_IH_DOORBELL_RANGE 0 0x4f0af2 2 0 3 OFFSET 2 11 SIZE 16 20 regGDC0_BIF_VCN0_DOORBELL_RANGE 0 0x4f0af3 2 0 3 OFFSET 2 11 SIZE 16 20 regGDC0_BIF_RLC_DOORBELL_RANGE 0 0x4f0af5 2 0 3 OFFSET 2 11 SIZE 16 20 regGDC0_ATDMA_MISC_CNTL 0 0x4f0afd 6 0 3 WRR_ARB_MODE 0 0 INSERT_RD_ON_2ND_WDAT_EN 1 1 RDRSP_ARB_MODE 2 3 WRR_VC6_WEIGHT 8 15 WRR_VC0_WEIGHT 16 23 WRR_VC1_WEIGHT 24 31 regGDC0_BIF_DOORBELL_FENCE_CNTL 0 0x4f0afe 9 0 3 DOORBELL_FENCE_CP_ENABLE 0 0 DOORBELL_FENCE_SDMA0_ENABLE 1 1 DOORBELL_FENCE_SDMA1_ENABLE 2 2 DOORBELL_FENCE_RLC_ENABLE 4 4 DOORBELL_FENCE_SDMA2_ENABLE 5 5 DOORBELL_FENCE_SDMA3_ENABLE 6 6 DOORBELL_FENCE_SDMA4_ENABLE 7 7 DOORBELL_FENCE_SDMA5_ENABLE 8 8 DOORBELL_FENCE_ONCE_TRIGGER_DIS 16 16 regGDC0_S2A_MISC_CNTL 0 0x4f0aff 12 0 3 DOORBELL_64BIT_SUPPORT_SDMA0_DIS 0 0 DOORBELL_64BIT_SUPPORT_SDMA1_DIS 1 1 DOORBELL_64BIT_SUPPORT_CP_DIS 2 2 DOORBELL_64BIT_SUPPORT_RLC_DIS 5 5 ATM_ARB_MODE 8 9 RB_ARB_MODE 10 11 HSTR_ARB_MODE 12 13 WRSP_ARB_MODE 16 19 DOORBELL_64BIT_SUPPORT_SDMA2_DIS 24 24 DOORBELL_64BIT_SUPPORT_SDMA3_DIS 25 25 DOORBELL_64BIT_SUPPORT_SDMA4_DIS 26 26 DOORBELL_64BIT_SUPPORT_SDMA5_DIS 27 27 regGDC0_SHUBCLK_DPM_CTRL 0 0x4f0b1b 5 0 3 SHUBCLK_DPM_MODE 0 0 SHUBCLK_DPM_ENABLE 1 1 SHUBCLK_DPM_DMAWR_QUANT 2 9 SHUBCLK_DPM_DMARD_QUANT 10 17 SHUBCLK_DPM_CLEAR 18 18 regGDC0_SHUBCLK_DPM_WR_WEIGHT 0 0x4f0b1c 5 0 3 SHUBCLK_DPM_WR_WEIGHT_4B 0 4 SHUBCLK_DPM_WR_WEIGHT_8B 5 9 SHUBCLK_DPM_WR_WEIGHT_16B 10 14 SHUBCLK_DPM_WR_WEIGHT_32B 15 19 SHUBCLK_DPM_WR_WEIGHT_64B 20 24 regGDC0_SHUBCLK_DPM_RD_WEIGHT 0 0x4f0b1d 5 0 3 SHUBCLK_DPM_RD_WEIGHT_4B 0 4 SHUBCLK_DPM_RD_WEIGHT_8B 5 9 SHUBCLK_DPM_RD_WEIGHT_16B 10 14 SHUBCLK_DPM_RD_WEIGHT_32B 15 19 SHUBCLK_DPM_RD_WEIGHT_64B 20 24 regGDC0_SHUBCLK_DPM_WR_CNT 0 0x4f0b1e 1 0 3 SHUBCLK_DPM_WR_COUNTER 0 31 regGDC0_SHUBCLK_DPM_RD_CNT 0 0x4f0b1f 1 0 3 SHUBCLK_DPM_RD_COUNTER 0 31 regOBFF_EMU_CFG_SOCCLK 0 0x4f3c10 2 0 3 OBFF_EMU_DMA_EN 0 0 ATHUB_URGENT_MODE 1 2 regHST_CLK0_SW0_CL0_CNTL 0 0x4f3d40 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regHST_CLK0_SW0_CL1_CNTL 0 0x4f3d41 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regHST_CLK0_SW0_CL2_CNTL 0 0x4f3d42 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regHST_CLK0_SW1_CL0_CNTL 0 0x4f3d60 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regHST_CLK0_SW1_CL1_CNTL 0 0x4f3d61 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regOBFF_EMU_CFG_SHUBCLK 0 0x4f4010 1 0 3 URGENT_MERGE_CTRL0 0 0 regHST_CLK1_SW0_CL0_CNTL 0 0x4f4140 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regOBFF_EMU_CFG_NICCLK 0 0x4f4410 0 0 3 regHST_CLK2_SW0_CL0_CNTL 0 0x4f4540 2 0 3 FLR_ON_RS_RESET_EN 0 0 LKRST_ON_RS_RESET_EN 1 1 regGDCSOC_ERR_RSP_CNTL 0 0x4f5c00 6 0 3 GDCSOC_RDRSP_BYPASS 0 0 GDCSOC_RDRSP_ACCUM_SEL 1 1 GDCSOC_RDRSP_FORCE_EN 2 2 GDCSOC_RDRSP_FORCE_DATA 3 3 GDCSOC_RDRSP_STATUS_ACCUM_EN 4 4 GDCSOC_RDRSP_DATASTATUS_ACCUM_EN 5 5 regGDCSOC_RAS_CENTRAL_STATUS 0 0x4f5c10 4 0 3 GDCSOC_L2C_EgStall_det 0 0 GDCSOC_L2C_ErrEvent_det 1 1 GDCSOC_C2L_EgStall_det 2 2 GDCSOC_C2L_ErrEvent_det 3 3 regGDCSOC_RAS_LEAF0_CTRL 0 0x4f5c20 9 0 3 GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF1_CTRL 0 0x4f5c21 9 0 3 GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF2_CTRL 0 0x4f5c22 9 0 3 GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF3_CTRL 0 0x4f5c23 9 0 3 GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF4_CTRL 0 0x4f5c24 9 0 3 GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF5_CTRL 0 0x4f5c25 9 0 3 GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN 0 0 GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN 1 1 GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN 2 2 GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN 3 3 GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN 4 4 GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSOC_RAS_LEAF0_STATUS 0 0x4f5c30 7 0 3 GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSOC_RAS_LEAF1_STATUS 0 0x4f5c31 7 0 3 GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSOC_RAS_LEAF2_STATUS 0 0x4f5c32 7 0 3 GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSOC_RAS_LEAF3_STATUS 0 0x4f5c33 7 0 3 GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSOC_RAS_LEAF4_STATUS 0 0x4f5c34 7 0 3 GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSOC_RAS_LEAF5_STATUS 0 0x4f5c35 7 0 3 GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV 0 0 GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET 1 1 GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET 2 2 GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSHUB_ERR_RSP_CNTL 0 0x4f5e00 6 0 3 GDCSHUB_RDRSP_BYPASS 0 0 GDCSHUB_RDRSP_ACCUM_SEL 1 1 GDCSHUB_RDRSP_FORCE_EN 2 2 GDCSHUB_RDRSP_FORCE_DATA 3 3 GDCSHUB_RDRSP_STATUS_ACCUM_EN 4 4 GDCSHUB_RDRSP_DATASTATUS_ACCUM_EN 5 5 regGDCSHUB_RAS_CENTRAL_STATUS 0 0x4f5e10 4 0 3 GDCSHUB_L2C_EgStall_det 0 0 GDCSHUB_L2C_ErrEvent_det 1 1 GDCSHUB_C2L_EgStall_det 2 2 GDCSHUB_C2L_ErrEvent_det 3 3 regGDCSHUB_RAS_LEAF0_CTRL 0 0x4f5e20 9 0 3 GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN 0 0 GDCSHUB_RAS_LEAF0_CTRL_POISON_ERREVENT_EN 1 1 GDCSHUB_RAS_LEAF0_CTRL_POISON_STALL_EN 2 2 GDCSHUB_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN 3 3 GDCSHUB_RAS_LEAF0_CTRL_PARITY_STALL_EN 4 4 GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSHUB_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSHUB_RAS_LEAF1_CTRL 0 0x4f5e21 9 0 3 GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN 0 0 GDCSHUB_RAS_LEAF1_CTRL_POISON_ERREVENT_EN 1 1 GDCSHUB_RAS_LEAF1_CTRL_POISON_STALL_EN 2 2 GDCSHUB_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN 3 3 GDCSHUB_RAS_LEAF1_CTRL_PARITY_STALL_EN 4 4 GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSHUB_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSHUB_RAS_LEAF2_CTRL 0 0x4f5e22 9 0 3 GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN 0 0 GDCSHUB_RAS_LEAF2_CTRL_POISON_ERREVENT_EN 1 1 GDCSHUB_RAS_LEAF2_CTRL_POISON_STALL_EN 2 2 GDCSHUB_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN 3 3 GDCSHUB_RAS_LEAF2_CTRL_PARITY_STALL_EN 4 4 GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSHUB_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSHUB_RAS_LEAF3_CTRL 0 0x4f5e23 9 0 3 GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN 0 0 GDCSHUB_RAS_LEAF3_CTRL_POISON_ERREVENT_EN 1 1 GDCSHUB_RAS_LEAF3_CTRL_POISON_STALL_EN 2 2 GDCSHUB_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN 3 3 GDCSHUB_RAS_LEAF3_CTRL_PARITY_STALL_EN 4 4 GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN 6 6 GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN 10 10 GDCSHUB_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCSHUB_RAS_LEAF0_STATUS 0 0x4f5e30 7 0 3 GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_RECV 0 0 GDCSHUB_RAS_LEAF0_STATUS_POISON_ERR_DET 1 1 GDCSHUB_RAS_LEAF0_STATUS_PARITY_ERR_DET 2 2 GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSHUB_RAS_LEAF1_STATUS 0 0x4f5e31 7 0 3 GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_RECV 0 0 GDCSHUB_RAS_LEAF1_STATUS_POISON_ERR_DET 1 1 GDCSHUB_RAS_LEAF1_STATUS_PARITY_ERR_DET 2 2 GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSHUB_RAS_LEAF2_STATUS 0 0x4f5e32 7 0 3 GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_RECV 0 0 GDCSHUB_RAS_LEAF2_STATUS_POISON_ERR_DET 1 1 GDCSHUB_RAS_LEAF2_STATUS_PARITY_ERR_DET 2 2 GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCSHUB_RAS_LEAF3_STATUS 0 0x4f5e33 7 0 3 GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_RECV 0 0 GDCSHUB_RAS_LEAF3_STATUS_POISON_ERR_DET 1 1 GDCSHUB_RAS_LEAF3_STATUS_PARITY_ERR_DET 2 2 GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCNIC_ERR_RSP_CNTL 0 0x4f6000 6 0 3 GDCNIC_RDRSP_BYPASS 0 0 GDCNIC_RDRSP_ACCUM_SEL 1 1 GDCNIC_RDRSP_FORCE_EN 2 2 GDCNIC_RDRSP_FORCE_DATA 3 3 GDCNIC_RDRSP_STATUS_ACCUM_EN 4 4 GDCNIC_RDRSP_DATASTATUS_ACCUM_EN 5 5 regGDCNIC_RAS_CENTRAL_STATUS 0 0x4f6010 4 0 3 GDCNIC_L2C_EgStall_det 0 0 GDCNIC_L2C_ErrEvent_det 1 1 GDCNIC_C2L_EgStall_det 2 2 GDCNIC_C2L_ErrEvent_det 3 3 regGDCNIC_RAS_LEAF0_CTRL 0 0x4f6020 9 0 3 GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN 0 0 GDCNIC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN 1 1 GDCNIC_RAS_LEAF0_CTRL_POISON_STALL_EN 2 2 GDCNIC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN 3 3 GDCNIC_RAS_LEAF0_CTRL_PARITY_STALL_EN 4 4 GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN 6 6 GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN 10 10 GDCNIC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCNIC_RAS_LEAF1_CTRL 0 0x4f6021 9 0 3 GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN 0 0 GDCNIC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN 1 1 GDCNIC_RAS_LEAF1_CTRL_POISON_STALL_EN 2 2 GDCNIC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN 3 3 GDCNIC_RAS_LEAF1_CTRL_PARITY_STALL_EN 4 4 GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN 6 6 GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN 10 10 GDCNIC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCNIC_RAS_LEAF2_CTRL 0 0x4f6022 9 0 3 GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN 0 0 GDCNIC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN 1 1 GDCNIC_RAS_LEAF2_CTRL_POISON_STALL_EN 2 2 GDCNIC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN 3 3 GDCNIC_RAS_LEAF2_CTRL_PARITY_STALL_EN 4 4 GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN 5 5 GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN 6 6 GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN 10 10 GDCNIC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN 11 11 regGDCNIC_RAS_LEAF0_STATUS 0 0x4f6030 7 0 3 GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_RECV 0 0 GDCNIC_RAS_LEAF0_STATUS_POISON_ERR_DET 1 1 GDCNIC_RAS_LEAF0_STATUS_PARITY_ERR_DET 2 2 GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCNIC_RAS_LEAF1_STATUS 0 0x4f6031 7 0 3 GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_RECV 0 0 GDCNIC_RAS_LEAF1_STATUS_POISON_ERR_DET 1 1 GDCNIC_RAS_LEAF1_STATUS_PARITY_ERR_DET 2 2 GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regGDCNIC_RAS_LEAF2_STATUS 0 0x4f6032 7 0 3 GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_RECV 0 0 GDCNIC_RAS_LEAF2_STATUS_POISON_ERR_DET 1 1 GDCNIC_RAS_LEAF2_STATUS_PARITY_ERR_DET 2 2 GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT 8 8 GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT 9 9 GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT 10 10 GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT 11 11 regSHUB_PF_FLR_RST 0 0x4f7800 13 0 3 DEV0_PF0_FLR_RST 0 0 DEV0_PF1_FLR_RST 1 1 DEV0_PF2_FLR_RST 2 2 DEV0_PF3_FLR_RST 3 3 DEV0_PF4_FLR_RST 4 4 DEV0_PF5_FLR_RST 5 5 DEV0_PF6_FLR_RST 6 6 DEV0_PF7_FLR_RST 7 7 DEV1_PF0_FLR_RST 8 8 DEV1_PF1_FLR_RST 9 9 DEV2_PF0_FLR_RST 16 16 DEV2_PF1_FLR_RST 17 17 DEV2_PF2_FLR_RST 18 18 regSHUB_GFX_DRV_VPU_RST 0 0x4f7801 1 0 3 GFX_DRV_MODE1_RST 0 0 regSHUB_LINK_RESET 0 0x4f7802 4 0 3 LINK_P0_RESET 0 0 LINK_P1_RESET 1 1 LINK_P2_RESET 2 2 LINK_P3_RESET 3 3 regSHUB_HARD_RST_CTRL 0 0x4f7810 5 0 3 COR_RESET_EN 0 0 REG_RESET_EN 1 1 STY_RESET_EN 2 2 SDP_PORT_RESET_EN 4 4 SION_AON_RESET_EN 5 5 regSHUB_SOFT_RST_CTRL 0 0x4f7811 5 0 3 COR_RESET_EN 0 0 REG_RESET_EN 1 1 STY_RESET_EN 2 2 SDP_PORT_RESET_EN 4 4 SION_AON_RESET_EN 5 5 regSHUB_SDP_PORT_RST 0 0x4f7812 9 0 3 NBIFSION_BIF_SDP_PORT_RST 1 1 ATHUB_HST_SDP_PORT_RST 2 2 ATHUB_DMA_SDP_PORT_RST 3 3 ATDMA_NBIFSOIN_SDP_PORT_RST 4 4 MP4SDP_SDP_PORT_RST 6 6 GDC_HST_SDP_PORT_RST 7 7 NTB_HST_SDP_PORT_RST 8 8 NTB_DMA_SDP_PORT_RST 9 9 SION_AON_RST 24 24 regSHUB_RST_MISC_TRL 0 0x4f7813 0 0 3 regBIF_CFG_DEV0_RC0_VENDOR_ID 0 0x0 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_RC0_DEVICE_ID 0 0x0 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_RC0_COMMAND 0 0x1 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_RC0_STATUS 0 0x1 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_RC0_REVISION_ID 0 0x2 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0 0x2 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_RC0_SUB_CLASS 0 0x2 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_RC0_BASE_CLASS 0 0x2 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_RC0_CACHE_LINE 0 0x3 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_RC0_LATENCY 0 0x3 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_RC0_HEADER 0 0x3 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_RC0_BIST 0 0x3 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0 0x4 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0 0x5 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0 0x6 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0 0x7 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0 0x7 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0 0x8 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0 0x9 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0 0xa 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0 0xb 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0 0xc 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV0_RC0_CAP_PTR 0 0xd 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0 0xe 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0 0xf 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0 0xf 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0 0xf 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0 0x10 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0 0x14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC0_PMI_CAP 0 0x14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0 0x15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0 0x16 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC0_PCIE_CAP 0 0x16 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_RC0_DEVICE_CAP 0 0x17 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0 0x18 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0 0x18 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_RC0_LINK_CAP 0 0x19 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_RC0_LINK_CNTL 0 0x1a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_RC0_LINK_STATUS 0 0x1a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_RC0_SLOT_CAP 0 0x1b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV0_RC0_SLOT_CNTL 0 0x1c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV0_RC0_SLOT_STATUS 0 0x1c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV0_RC0_ROOT_CNTL 0 0x1d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV0_RC0_ROOT_CAP 0 0x1d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV0_RC0_ROOT_STATUS 0 0x1e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0 0x1f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0 0x20 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0 0x20 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC0_LINK_CAP2 0 0x21 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_RC0_LINK_CNTL2 0 0x22 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_RC0_LINK_STATUS2 0 0x22 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_RC0_SLOT_CAP2 0 0x23 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0 0x24 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0 0x24 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0 0x28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0 0x28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0 0x29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0 0x2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0 0x2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0 0x2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0 0x2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0 0x2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0 0x30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC0_SSID_CAP 0 0x31 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST 0 0x32 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC0_MSI_MAP_CAP 0 0x32 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0 0x41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0 0x42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0 0x43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0 0x44 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0 0x45 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0 0x46 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0 0x47 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0 0x47 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0 0x48 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0 0x49 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0 0x4a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0 0x4b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0 0x4c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0 0x4d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x50 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0 0x51 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0 0x52 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0 0x55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0 0x56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0 0x57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0 0x58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0 0x59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0 0x5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0 0x5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0 0x5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0 0x5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0 0x5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0 0x5f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0 0x60 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0 0x61 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0 0x62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0 0x63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0 0x64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0 0x65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x9c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0 0x9d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0 0x9e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x9f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x9f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0xa0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0xa0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0xa1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0xa1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0xa2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0xa2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0xa3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0xa3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0xa4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0xa4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0xa5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0xa5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0xa6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0xa6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0 0xa8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0 0xa9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0 0xa9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0 0x100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0 0x101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0 0x102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0 0x105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0 0x106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0 0x107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x10a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x10c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x10c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x10c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x10c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x10d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x10d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x10d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x10d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x10e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x10e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x10e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x10e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x10f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x10f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x10f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x10f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0 0x110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0 0x111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0 0x111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0 0x112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0 0x112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0 0x113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0 0x113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0 0x114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0 0x114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0 0x115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0 0x115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0 0x116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0 0x116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0 0x117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0 0x117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0 0x118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0 0x118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0 0x119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0 0x119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0 0x11a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0 0x11a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0 0x11b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0 0x11b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0 0x11c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0 0x11c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0 0x11d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0 0x11d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0 0x11e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0 0x11e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0 0x11f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0 0x11f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0 0x120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0 0x120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0 0x121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0 0x121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_VENDOR_ID 0 0x400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_RC0_DEVICE_ID 0 0x400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_RC0_COMMAND 0 0x401 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_RC0_STATUS 0 0x401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_RC0_REVISION_ID 0 0x402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_RC0_PROG_INTERFACE 0 0x402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_RC0_SUB_CLASS 0 0x402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_RC0_BASE_CLASS 0 0x402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_RC0_CACHE_LINE 0 0x403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_RC0_LATENCY 0 0x403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_RC0_HEADER 0 0x403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_RC0_BIST 0 0x403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_RC0_BASE_ADDR_1 0 0x404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC0_BASE_ADDR_2 0 0x405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY 0 0x406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT 0 0x407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV1_RC0_SECONDARY_STATUS 0 0x407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT 0 0x408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT 0 0x409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV1_RC0_PREF_BASE_UPPER 0 0x40a 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER 0 0x40b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI 0 0x40c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV1_RC0_CAP_PTR 0 0x40d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_RC0_ROM_BASE_ADDR 0 0x40e 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC0_INTERRUPT_LINE 0 0x40f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_RC0_INTERRUPT_PIN 0 0x40f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL 0 0x40f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL 0 0x410 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV1_RC0_PMI_CAP_LIST 0 0x414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC0_PMI_CAP 0 0x414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL 0 0x415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_RC0_PCIE_CAP_LIST 0 0x416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC0_PCIE_CAP 0 0x416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_RC0_DEVICE_CAP 0 0x417 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_RC0_DEVICE_CNTL 0 0x418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV1_RC0_DEVICE_STATUS 0 0x418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_RC0_LINK_CAP 0 0x419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_RC0_LINK_CNTL 0 0x41a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_RC0_LINK_STATUS 0 0x41a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_RC0_SLOT_CAP 0 0x41b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV1_RC0_SLOT_CNTL 0 0x41c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV1_RC0_SLOT_STATUS 0 0x41c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV1_RC0_ROOT_CNTL 0 0x41d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV1_RC0_ROOT_CAP 0 0x41d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV1_RC0_ROOT_STATUS 0 0x41e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV1_RC0_DEVICE_CAP2 0 0x41f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_RC0_DEVICE_CNTL2 0 0x420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_RC0_DEVICE_STATUS2 0 0x420 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC0_LINK_CAP2 0 0x421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_RC0_LINK_CNTL2 0 0x422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_RC0_LINK_STATUS2 0 0x422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_RC0_SLOT_CAP2 0 0x423 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC0_SLOT_CNTL2 0 0x424 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC0_SLOT_STATUS2 0 0x424 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC0_MSI_CAP_LIST 0 0x428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC0_MSI_MSG_CNTL 0 0x428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO 0 0x429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI 0 0x42a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_RC0_MSI_MSG_DATA 0 0x42a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA 0 0x42a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 0 0x42b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64 0 0x42b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_RC0_SSID_CAP_LIST 0 0x430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC0_SSID_CAP 0 0x431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST 0 0x432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC0_MSI_MAP_CAP 0 0x432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR 0 0x441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 0 0x442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 0 0x443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST 0 0x444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 0 0x445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 0 0x446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL 0 0x447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS 0 0x447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP 0 0x448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL 0 0x449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS 0 0x44a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP 0 0x44b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL 0 0x44c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS 0 0x44d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 0 0x451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 0 0x452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS 0 0x455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK 0 0x456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY 0 0x457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS 0 0x458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK 0 0x459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL 0 0x45a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 0 0x45b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 0 0x45c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 0 0x45d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 0 0x45e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD 0 0x45f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS 0 0x460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID 0 0x461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 0 0x462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 0 0x463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 0 0x464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 0 0x465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x49c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 0 0x49d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS 0 0x49e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x49f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x49f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST 0 0x4a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_PCIE_ACS_CAP 0 0x4a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL 0 0x4a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST 0 0x500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP 0 0x501 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS 0 0x502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_LINK_CAP_16GT 0 0x505 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC0_LINK_CNTL_16GT 0 0x506 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC0_LINK_STATUS_16GT 0 0x507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x50a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x50c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x50c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x50c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x50c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x50d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x50d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x50d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x50d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x50e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x50e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x50e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x50e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x50f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x50f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x50f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x50f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST 0 0x510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC0_MARGINING_PORT_CAP 0 0x511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS 0 0x511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL 0 0x512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS 0 0x512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL 0 0x513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS 0 0x513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL 0 0x514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS 0 0x514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL 0 0x515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS 0 0x515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL 0 0x516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS 0 0x516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL 0 0x517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS 0 0x517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL 0 0x518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS 0 0x518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL 0 0x519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS 0 0x519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL 0 0x51a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS 0 0x51a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL 0 0x51b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS 0 0x51b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL 0 0x51c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS 0 0x51c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL 0 0x51d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS 0 0x51d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL 0 0x51e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS 0 0x51e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL 0 0x51f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS 0 0x51f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL 0 0x520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS 0 0x520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL 0 0x521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS 0 0x521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_VENDOR_ID 0 0x800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_RC0_DEVICE_ID 0 0x800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_RC0_COMMAND 0 0x801 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_RC0_STATUS 0 0x801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_RC0_REVISION_ID 0 0x802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_RC0_PROG_INTERFACE 0 0x802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_RC0_SUB_CLASS 0 0x802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_RC0_BASE_CLASS 0 0x802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_RC0_CACHE_LINE 0 0x803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_RC0_LATENCY 0 0x803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_RC0_HEADER 0 0x803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_RC0_BIST 0 0x803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_RC0_BASE_ADDR_1 0 0x804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC0_BASE_ADDR_2 0 0x805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY 0 0x806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT 0 0x807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV2_RC0_SECONDARY_STATUS 0 0x807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_RC0_MEM_BASE_LIMIT 0 0x808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV2_RC0_PREF_BASE_LIMIT 0 0x809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV2_RC0_PREF_BASE_UPPER 0 0x80a 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER 0 0x80b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI 0 0x80c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV2_RC0_CAP_PTR 0 0x80d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_RC0_ROM_BASE_ADDR 0 0x80e 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC0_INTERRUPT_LINE 0 0x80f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_RC0_INTERRUPT_PIN 0 0x80f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL 0 0x80f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL 0 0x810 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV2_RC0_PMI_CAP_LIST 0 0x814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC0_PMI_CAP 0 0x814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_RC0_PMI_STATUS_CNTL 0 0x815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_RC0_PCIE_CAP_LIST 0 0x816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC0_PCIE_CAP 0 0x816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_RC0_DEVICE_CAP 0 0x817 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_RC0_DEVICE_CNTL 0 0x818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV2_RC0_DEVICE_STATUS 0 0x818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_RC0_LINK_CAP 0 0x819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_RC0_LINK_CNTL 0 0x81a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_RC0_LINK_STATUS 0 0x81a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_RC0_SLOT_CAP 0 0x81b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV2_RC0_SLOT_CNTL 0 0x81c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV2_RC0_SLOT_STATUS 0 0x81c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV2_RC0_ROOT_CNTL 0 0x81d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV2_RC0_ROOT_CAP 0 0x81d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV2_RC0_ROOT_STATUS 0 0x81e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV2_RC0_DEVICE_CAP2 0 0x81f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_RC0_DEVICE_CNTL2 0 0x820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_RC0_DEVICE_STATUS2 0 0x820 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC0_LINK_CAP2 0 0x821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_RC0_LINK_CNTL2 0 0x822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_RC0_LINK_STATUS2 0 0x822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_RC0_SLOT_CAP2 0 0x823 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC0_SLOT_CNTL2 0 0x824 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC0_SLOT_STATUS2 0 0x824 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC0_MSI_CAP_LIST 0 0x828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC0_MSI_MSG_CNTL 0 0x828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO 0 0x829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI 0 0x82a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_RC0_MSI_MSG_DATA 0 0x82a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA 0 0x82a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_RC0_MSI_MSG_DATA_64 0 0x82b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64 0 0x82b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_RC0_SSID_CAP_LIST 0 0x830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC0_SSID_CAP 0 0x831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST 0 0x832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC0_MSI_MAP_CAP 0 0x832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR 0 0x841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1 0 0x842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2 0 0x843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST 0 0x844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1 0 0x845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2 0 0x846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL 0 0x847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS 0 0x847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP 0 0x848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL 0 0x849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS 0 0x84a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP 0 0x84b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL 0 0x84c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS 0 0x84d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1 0 0x851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2 0 0x852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS 0 0x855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK 0 0x856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY 0 0x857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS 0 0x858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK 0 0x859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL 0 0x85a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG0 0 0x85b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG1 0 0x85c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG2 0 0x85d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC0_PCIE_HDR_LOG3 0 0x85e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD 0 0x85f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS 0 0x860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID 0 0x861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0 0 0x862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1 0 0x863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2 0 0x864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3 0 0x865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x89c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3 0 0x89d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS 0 0x89e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x89f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x89f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x8a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x8a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x8a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x8a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x8a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x8a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x8a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x8a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x8a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x8a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x8a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x8a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x8a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x8a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST 0 0x8a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_PCIE_ACS_CAP 0 0x8a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_RC0_PCIE_ACS_CNTL 0 0x8a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST 0 0x900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP 0 0x901 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS 0 0x902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_LINK_CAP_16GT 0 0x905 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC0_LINK_CNTL_16GT 0 0x906 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC0_LINK_STATUS_16GT 0 0x907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x90a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x90c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x90c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x90c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x90c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x90d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x90d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x90d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x90d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x90e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x90e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x90e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x90e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x90f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x90f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x90f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x90f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST 0 0x910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC0_MARGINING_PORT_CAP 0 0x911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS 0 0x911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL 0 0x912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS 0 0x912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL 0 0x913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS 0 0x913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL 0 0x914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS 0 0x914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL 0 0x915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS 0 0x915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL 0 0x916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS 0 0x916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL 0 0x917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS 0 0x917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL 0 0x918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS 0 0x918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL 0 0x919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS 0 0x919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL 0 0x91a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS 0 0x91a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL 0 0x91b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS 0 0x91b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL 0 0x91c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS 0 0x91c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL 0 0x91d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS 0 0x91d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL 0 0x91e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS 0 0x91e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL 0 0x91f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS 0 0x91f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL 0 0x920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS 0 0x920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL 0 0x921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS 0 0x921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_BX_PF1_MM_INDEX 0 0x8000 2 0 5 MM_OFFSET 0 30 MM_APER 31 31 regBIF_BX_PF1_MM_DATA 0 0x8001 1 0 5 MM_DATA 0 31 regBIF_BX_PF1_MM_INDEX_HI 0 0x8006 1 0 5 MM_OFFSET_HI 0 31 regBIF_BX1_PCIE_INDEX 0 0x800c 1 0 5 PCIE_INDEX 0 31 regBIF_BX1_PCIE_DATA 0 0x800d 1 0 5 PCIE_DATA 0 31 regBIF_BX1_PCIE_INDEX2 0 0x800e 1 0 5 PCIE_INDEX2 0 31 regBIF_BX1_PCIE_DATA2 0 0x800f 1 0 5 PCIE_DATA2 0 31 regBIF_BX1_SBIOS_SCRATCH_0 0 0x8048 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX1_SBIOS_SCRATCH_1 0 0x8049 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX1_SBIOS_SCRATCH_2 0 0x804a 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX1_SBIOS_SCRATCH_3 0 0x804b 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX1_BIOS_SCRATCH_0 0 0x804c 1 0 5 BIOS_SCRATCH_0 0 31 regBIF_BX1_BIOS_SCRATCH_1 0 0x804d 1 0 5 BIOS_SCRATCH_1 0 31 regBIF_BX1_BIOS_SCRATCH_2 0 0x804e 1 0 5 BIOS_SCRATCH_2 0 31 regBIF_BX1_BIOS_SCRATCH_3 0 0x804f 1 0 5 BIOS_SCRATCH_3 0 31 regBIF_BX1_BIOS_SCRATCH_4 0 0x8050 1 0 5 BIOS_SCRATCH_4 0 31 regBIF_BX1_BIOS_SCRATCH_5 0 0x8051 1 0 5 BIOS_SCRATCH_5 0 31 regBIF_BX1_BIOS_SCRATCH_6 0 0x8052 1 0 5 BIOS_SCRATCH_6 0 31 regBIF_BX1_BIOS_SCRATCH_7 0 0x8053 1 0 5 BIOS_SCRATCH_7 0 31 regBIF_BX1_BIOS_SCRATCH_8 0 0x8054 1 0 5 BIOS_SCRATCH_8 0 31 regBIF_BX1_BIOS_SCRATCH_9 0 0x8055 1 0 5 BIOS_SCRATCH_9 0 31 regBIF_BX1_BIOS_SCRATCH_10 0 0x8056 1 0 5 BIOS_SCRATCH_10 0 31 regBIF_BX1_BIOS_SCRATCH_11 0 0x8057 1 0 5 BIOS_SCRATCH_11 0 31 regBIF_BX1_BIOS_SCRATCH_12 0 0x8058 1 0 5 BIOS_SCRATCH_12 0 31 regBIF_BX1_BIOS_SCRATCH_13 0 0x8059 1 0 5 BIOS_SCRATCH_13 0 31 regBIF_BX1_BIOS_SCRATCH_14 0 0x805a 1 0 5 BIOS_SCRATCH_14 0 31 regBIF_BX1_BIOS_SCRATCH_15 0 0x805b 1 0 5 BIOS_SCRATCH_15 0 31 regBIF_BX1_BIF_RLC_INTR_CNTL 0 0x8060 4 0 5 RLC_CMD_COMPLETE 0 0 RLC_HANG_SELF_RECOVERED 1 1 RLC_HANG_NEED_FLR 2 2 RLC_VM_BUSY_TRANSITION 3 3 regBIF_BX1_BIF_VCE_INTR_CNTL 0 0x8061 4 0 5 VCE_CMD_COMPLETE 0 0 VCE_HANG_SELF_RECOVERED 1 1 VCE_HANG_NEED_FLR 2 2 VCE_VM_BUSY_TRANSITION 3 3 regBIF_BX1_BIF_UVD_INTR_CNTL 0 0x8062 5 0 5 UVD_CMD_COMPLETE 0 0 UVD_HANG_SELF_RECOVERED 1 1 UVD_HANG_NEED_FLR 2 2 UVD_VM_BUSY_TRANSITION 3 3 UVD_INST_SEL 28 31 regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0 0x8080 1 0 5 CAM_ADDR0 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0 0x8081 1 0 5 CAM_REMAP_ADDR0 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0 0x8082 1 0 5 CAM_ADDR1 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0 0x8083 1 0 5 CAM_REMAP_ADDR1 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0 0x8084 1 0 5 CAM_ADDR2 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0 0x8085 1 0 5 CAM_REMAP_ADDR2 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0 0x8086 1 0 5 CAM_ADDR3 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0 0x8087 1 0 5 CAM_REMAP_ADDR3 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0 0x8088 1 0 5 CAM_ADDR4 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0 0x8089 1 0 5 CAM_REMAP_ADDR4 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0 0x808a 1 0 5 CAM_ADDR5 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0 0x808b 1 0 5 CAM_REMAP_ADDR5 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0 0x808c 1 0 5 CAM_ADDR6 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0 0x808d 1 0 5 CAM_REMAP_ADDR6 0 19 regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0 0x808e 1 0 5 CAM_ADDR7 0 19 regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0 0x808f 1 0 5 CAM_REMAP_ADDR7 0 19 regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0 0x8090 1 0 5 CAM_ENABLE 0 7 regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0 0x8091 1 0 5 CAM_ZERO_CPL 0 31 regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0 0x8092 1 0 5 CAM_ONE_CPL 0 31 regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0 0x8093 1 0 5 CAM_PROGRAMMABLE_CPL 0 31 regRCC_STRAP1_RCC_BIF_STRAP0 0 0x8d20 22 0 5 STRAP_GEN4_DIS_PIN 0 0 STRAP_VGA_DIS_PIN 2 2 STRAP_MEM_AP_SIZE_PIN 3 5 STRAP_BIOS_ROM_EN_PIN 6 6 STRAP_PX_CAPABLE 7 7 STRAP_BIF_KILL_GEN3 8 8 STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN 9 9 STRAP_NBIF_IGNORE_ERR_INFLR 10 10 STRAP_PME_SUPPORT_COMPLIANCE_EN 11 11 STRAP_RX_IGNORE_EP_ERR 12 12 STRAP_RX_IGNORE_MSG_ERR 13 13 STRAP_RX_IGNORE_MAX_PAYLOAD_ERR 14 14 STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN 15 15 STRAP_RX_IGNORE_TC_ERR 16 16 STRAP_RX_IGNORE_TC_ERR_DN 17 17 STRAP_GEN3_DIS 24 24 STRAP_BIF_KILL_GEN4 25 25 STRAP_QUICKSIM_START 26 26 STRAP_NO_RO_ENABLED_P2P_PASSING 27 27 STRAP_CFG0_RD_VF_BUSNUM_CHK_EN 29 29 STRAP_BIGAPU_MODE 30 30 STRAP_LINK_DOWN_RESET_EN 31 31 regRCC_STRAP1_RCC_BIF_STRAP1 0 0x8d21 21 0 5 ROMSTRAP_VALID 1 1 STRAP_ECRC_INTERMEDIATE_CHK_EN 3 3 STRAP_IGNORE_E2E_PREFIX_UR_SWUS 5 5 STRAP_MARGINING_USES_SOFTWARE 6 6 STRAP_MARGINING_READY 7 7 STRAP_SWUS_APER_EN 8 8 STRAP_SWUS_64BAR_EN 9 9 STRAP_SWUS_AP_SIZE 10 11 STRAP_SWUS_APER_PREFETCHABLE 12 12 STRAP_HWREV_LSB2 13 14 STRAP_SWREV_LSB2 15 16 STRAP_LINK_RST_CFG_ONLY 17 17 STRAP_BIF_IOV_LKRST_DIS 18 18 STRAP_DLF_EN 19 19 STRAP_PHY_16GT_EN 20 20 STRAP_MARGIN_EN 21 21 STRAP_BIF_PSN_UR_RPT_EN 22 22 STRAP_BIF_SLOT_POWER_SUPPORT_EN 23 23 STRAP_GFX_FUNC_LTR_MODE 26 26 STRAP_GSI_SMN_POSTWR_MULTI_EN 27 28 STRAP_DLF_EN_EP 29 29 regRCC_STRAP1_RCC_BIF_STRAP2 0 0x8d22 14 0 5 STRAP_PCIESWUS_INDEX_APER_RANGE 0 0 STRAP_SUC_IND_ACCESS_DIS 3 3 STRAP_SUM_IND_ACCESS_DIS 4 4 STRAP_ENDP_LINKDOWN_DROP_DMA 5 5 STRAP_SWITCH_LINKDOWN_DROP_DMA 6 6 STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS 8 8 STRAP_ACS_MSKSEV_EP_HIDE_DIS 9 9 STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN 10 11 RESERVED_BIF_STRAP2 13 13 STRAP_LTR_IN_ASPML1_DIS 14 14 STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN 15 15 STRAP_PWRBRK_DEGLITCH_CYCLE 16 23 STRAP_PWRBRK_DEGLITCH_BYPASS 24 24 STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS 31 31 regRCC_STRAP1_RCC_BIF_STRAP3 0 0x8d23 2 0 5 STRAP_VLINK_ASPM_IDLE_TIMER 0 15 STRAP_VLINK_PM_L1_ENTRY_TIMER 16 31 regRCC_STRAP1_RCC_BIF_STRAP4 0 0x8d24 2 0 5 STRAP_VLINK_L0S_EXIT_TIMER 0 15 STRAP_VLINK_L1_EXIT_TIMER 16 31 regRCC_STRAP1_RCC_BIF_STRAP5 0 0x8d25 11 0 5 STRAP_VLINK_LDN_ENTRY_TIMER 0 15 STRAP_VLINK_LDN_ON_SWUS_LDN_EN 16 16 STRAP_VLINK_LDN_ON_SWUS_SECRST_EN 17 17 STRAP_VLINK_ENTER_COMPLIANCE_DIS 18 18 STRAP_IGNORE_PSN_ON_VDM1_DIS 19 19 STRAP_SMN_ERR_STATUS_MASK_EN_UPS 20 20 STRAP_SMN_ERRRSP_DATA_FORCE 22 23 STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE 24 24 STRAP_EMER_POWER_REDUCTION_SUPPORTED 25 26 STRAP_EMER_POWER_REDUCTION_INIT_REQ 27 27 STRAP_PWRBRK_STATUS_TIMER 28 30 regRCC_STRAP1_RCC_BIF_STRAP6 0 0x8d26 0 0 5 regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0 0x8d27 10 0 5 STRAP_ARI_EN_DN_DEV0 1 1 STRAP_ACS_EN_DN_DEV0 2 2 STRAP_AER_EN_DN_DEV0 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 4 4 STRAP_DEVICE_ID_DN_DEV0 5 20 STRAP_INTERRUPT_PIN_DN_DEV0 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 28 30 STRAP_EPF0_DUMMY_EN_DEV0 31 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0 0x8d28 2 0 5 STRAP_SUBSYS_ID_DN_DEV0 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0 16 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0 0x8d29 20 0 5 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 1 1 STRAP_E2E_PREFIX_EN_DEV0 2 2 STRAP_ECN1P1_EN_DEV0 3 3 STRAP_ECRC_CHECK_EN_DEV0 4 4 STRAP_ERR_REPORTING_DIS_DEV0 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0 8 8 STRAP_EXT_VC_COUNT_DN_DEV0 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 13 13 STRAP_GEN2_COMPLIANCE_DEV0 14 14 STRAP_GEN2_EN_DEV0 15 15 STRAP_GEN3_COMPLIANCE_DEV0 16 16 STRAP_GEN4_COMPLIANCE_DEV0 17 17 STRAP_TARGET_LINK_SPEED_DEV0 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 20 22 STRAP_L0S_EXIT_LATENCY_DEV0 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 26 28 STRAP_L1_EXIT_LATENCY_DEV0 29 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0 0x8d2a 16 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 1 1 STRAP_LTR_EN_DN_DEV0 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 3 5 STRAP_MSI_EN_DN_DEV0 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0 7 7 STRAP_NO_SOFT_RESET_DN_DEV0 8 8 STRAP_OBFF_SUPPORTED_DEV0 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 21 24 STRAP_PM_SUPPORT_DEV0 25 26 STRAP_PM_SUPPORT_DN_DEV0 27 28 STRAP_ATOMIC_EN_DN_DEV0 29 29 STRAP_PMC_DSI_DN_DEV0 31 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0 0x8d2b 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 24 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0 0x8d2c 18 0 5 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0 18 18 STRAP_VC_EN_DN_DEV0 19 19 STRAP_TwoVC_EN_DEV0 20 20 STRAP_TwoVC_EN_DN_DEV0 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV0 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 29 29 STRAP_MSI_MAP_EN_DEV0 30 30 STRAP_SSID_EN_DEV0 31 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0 0x8d2d 12 0 5 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV0 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0 19 19 regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0 0x8d2e 6 0 5 STRAP_PORT_NUMBER_DEV0 0 7 STRAP_MAJOR_REV_ID_DN_DEV0 8 11 STRAP_MINOR_REV_ID_DN_DEV0 12 15 STRAP_RP_BUSNUM_DEV0 16 23 STRAP_DN_DEVNUM_DEV0 24 28 STRAP_DN_FUNCID_DEV0 29 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0 0x8d2f 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_6_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV0 24 31 regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0 0x8d30 3 0 5 STRAP_PWR_BUDGET_DATA_8T0_a_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV0 8 15 STRAP_VENDOR_ID_DN_DEV0 16 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0 0x8d31 8 0 5 STRAP_DEVICE_ID_DEV0_F0 0 15 STRAP_MAJOR_REV_ID_DEV0_F0 16 19 STRAP_MINOR_REV_ID_DEV0_F0 20 23 STRAP_ATI_REV_ID_DEV0_F0 24 27 STRAP_FUNC_EN_DEV0_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 29 29 STRAP_D1_SUPPORT_DEV0_F0 30 30 STRAP_D2_SUPPORT_DEV0_F0 31 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0 0x8d32 2 0 5 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 16 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0 0x8d33 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F0 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0 16 23 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0 0x8d34 1 0 5 STRAP_VENDOR_ID_DEV0_F0 0 15 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0 0x8d35 21 0 5 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 1 5 STRAP_64BAR_DIS_DEV0_F0 6 6 STRAP_NO_SOFT_RESET_DEV0_F0 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 14 14 STRAP_ARI_EN_DEV0_F0 15 15 STRAP_AER_EN_DEV0_F0 16 16 STRAP_ACS_EN_DEV0_F0 17 17 STRAP_ATS_EN_DEV0_F0 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 20 20 STRAP_DPA_EN_DEV0_F0 21 21 STRAP_DSN_EN_DEV0_F0 22 22 STRAP_VC_EN_DEV0_F0 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0 24 26 STRAP_PAGE_REQ_EN_DEV0_F0 27 27 STRAP_PASID_EN_DEV0_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 31 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0 0x8d36 13 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 1 1 STRAP_SUBSYS_ID_DEV0_F0 2 17 STRAP_MSI_EN_DEV0_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 19 19 STRAP_MSIX_EN_DEV0_F0 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0 21 23 STRAP_PMC_DSI_DEV0_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 27 27 STRAP_VF_RESIZE_BAR_EN_DEV0_F0 28 28 STRAP_CLK_PM_EN_DEV0_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F0 30 30 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0 0x8d37 7 0 5 STRAP_RESERVED_STRAP4_DEV0_F0 0 9 STRAP_ATOMIC_64BIT_EN_DEV0_F0 20 20 STRAP_ATOMIC_EN_DEV0_F0 21 21 STRAP_FLR_EN_DEV0_F0 22 22 STRAP_PME_SUPPORT_DEV0_F0 23 27 STRAP_INTERRUPT_PIN_DEV0_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0 31 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0 0x8d38 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0 30 30 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0 0x8d39 13 0 5 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0 3 3 STRAP_ROM_AP_SIZE_DEV0_F0 4 6 STRAP_IO_BAR_DIS_DEV0_F0 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0 8 8 STRAP_MEM_AP_SIZE_DEV0_F0 9 12 STRAP_REG_AP_SIZE_DEV0_F0 13 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0 19 22 STRAP_VF_REG_AP_SIZE_DEV0_F0 23 25 STRAP_VGA_DIS_DEV0_F0 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 30 31 regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0 0x8d3a 7 0 5 STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0 0 15 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 18 18 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 19 19 STRAP_VF_REG_PROT_DIS_DEV0_F0 20 20 STRAP_FB_ALWAYS_ON_DEV0_F0 21 21 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 22 23 STRAP_GPUIOV_VSEC_REV_DEV0_F0 24 27 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0 0x8d3b 7 0 5 STRAP_DEVICE_ID_DEV0_F1 0 15 STRAP_MAJOR_REV_ID_DEV0_F1 16 19 STRAP_MINOR_REV_ID_DEV0_F1 20 23 STRAP_FUNC_EN_DEV0_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 29 29 STRAP_D1_SUPPORT_DEV0_F1 30 30 STRAP_D2_SUPPORT_DEV0_F1 31 31 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10 0 0x8d3c 0 0 5 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11 0 0x8d3d 0 0 5 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12 0 0x8d3e 0 0 5 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13 0 0x8d3f 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F1 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1 16 23 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14 0 0x8d40 1 0 5 STRAP_VENDOR_ID_DEV0_F1 0 15 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0 0x8d41 16 0 5 STRAP_NO_SOFT_RESET_DEV0_F1 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 14 14 STRAP_AER_EN_DEV0_F1 16 16 STRAP_ACS_EN_DEV0_F1 17 17 STRAP_ATS_EN_DEV0_F1 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 20 20 STRAP_DPA_EN_DEV0_F1 21 21 STRAP_DSN_EN_DEV0_F1 22 22 STRAP_VC_EN_DEV0_F1 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1 24 26 STRAP_PASID_EN_DEV0_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1 31 31 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0 0x8d42 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 1 1 STRAP_SUBSYS_ID_DEV0_F1 2 17 STRAP_MSI_EN_DEV0_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 19 19 STRAP_MSIX_EN_DEV0_F1 20 20 STRAP_PMC_DSI_DEV0_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 27 27 STRAP_CLK_PM_EN_DEV0_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F1 30 30 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0 0x8d43 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F1 20 20 STRAP_ATOMIC_EN_DEV0_F1 21 21 STRAP_FLR_EN_DEV0_F1 22 22 STRAP_PME_SUPPORT_DEV0_F1 23 27 STRAP_INTERRUPT_PIN_DEV0_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1 31 31 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0 0x8d44 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1 30 30 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0 0x8d45 3 0 5 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 1 1 STRAP_APER0_64BAR_EN_DEV0_F1 2 2 regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0 0x8d46 0 0 5 regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0 0x8d47 1 0 5 PCIE_SCRATCH 0 31 regRCC_EP_DEV0_1_EP_PCIE_CNTL 0 0x8d49 3 0 5 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0 0x8d4a 6 0 5 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0 0x8d4b 6 0 5 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0 0x8d4c 1 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0 0x8d4d 1 0 5 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0 0x8d4e 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0 0x8d50 10 0 5 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0 0x8d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0 0x8d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0 0x8d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0 0x8d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0 0x8d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0 0x8d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0 0x8d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0 0x8d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0 0x8d53 1 0 5 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0 0x8d54 1 0 5 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0 0x8d56 4 0 5 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0x8d57 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0 0x8d57 2 0 5 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0x8d57 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0x8d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0x8d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0x8d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0x8d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0x8d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0x8d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0x8d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0 0x8d59 1 0 5 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0 0x8d5a 1 0 5 PCIEP_RESERVED 0 31 regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0 0x8d5c 5 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0 0x8d5d 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0 0x8d5e 12 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0 0x8d5f 8 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0 0x8d60 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0 0x8d62 1 0 5 PCIE_RESERVED 0 31 regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0 0x8d63 1 0 5 PCIE_SCRATCH 0 31 regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0 0x8d65 3 0 5 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0 0x8d66 1 0 5 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0 0x8d67 1 0 5 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0 0x8d68 2 0 5 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0 0x8d69 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0 0x8d6a 3 0 5 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0 0x8d6b 2 0 5 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0 0x8d6c 1 0 5 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0 0x8d6f 4 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0 0x8d70 5 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0 0x8d71 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0 0x8d72 2 0 5 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0 0x8d73 1 0 5 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0 0x8d74 1 0 5 LTR_MSG_INFO_FROM_EP 0 31 regRCC_DEV0_1_RCC_ERR_INT_CNTL 0 0x8da6 1 0 5 INVALID_REG_ACCESS_IN_SRIOV_INT_EN 0 0 regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0 0x8da7 2 0 5 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 regRCC_DEV0_1_RCC_RESET_EN 0 0x8da8 1 0 5 DB_APER_RESET_EN 15 15 regRCC_DEV0_1_RCC_VDM_SUPPORT 0 0x8da9 5 0 5 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0 0x8daa 9 0 5 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0 0x8dab 4 0 5 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_DEV0_1_RCC_GPUIOV_REGION 0 0x8dac 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0 0x8dad 1 0 5 GPU_HOSTVM_EN 0 0 regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0 0x8dae 2 0 5 RCC_CONSOLE_IOV_MODE_ENABLE 0 0 MULTIOS_IH_SUPPORT_EN 1 1 regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0 0x8daf 1 0 5 CONSOLE_IOV_FIRST_VF_OFFSET 0 15 regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0 0x8daf 1 0 5 CONSOLE_IOV_VF_STRIDE 0 15 regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0 0x8dde 2 0 5 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0 0x8ddf 2 0 5 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_1_RCC_BUS_CNTL 0 0x8de1 19 0 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV0_1_RCC_CONFIG_CNTL 0 0x8de2 3 0 5 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0 0x8de6 1 0 5 F0_BASE 0 31 regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0 0x8de7 1 0 5 APER_SIZE 0 31 regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0 0x8de8 1 0 5 REG_APER_SIZE 0 26 regRCC_DEV0_1_RCC_XDMA_LO 0 0x8de9 2 0 5 BIF_XDMA_LOWER_BOUND 0 30 BIF_XDMA_APER_EN 31 31 regRCC_DEV0_1_RCC_XDMA_HI 0 0x8dea 1 0 5 BIF_XDMA_UPPER_BOUND 0 30 regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0 0x8deb 12 0 5 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0 0x8dec 1 0 5 ID_MASK 0 7 regRCC_DEV0_1_RCC_BUSNUM_LIST0 0 0x8ded 4 0 5 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 regRCC_DEV0_1_RCC_BUSNUM_LIST1 0 0x8dee 4 0 5 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0 0x8def 4 0 5 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0 0x8df0 1 0 5 CHECK_EN 0 0 regRCC_DEV0_1_RCC_HOST_BUSNUM 0 0x8df1 1 0 5 HOST_ID 0 15 regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0 0x8df2 1 0 5 PEER0_FB_OFFSET_HI 0 19 regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0 0x8df3 2 0 5 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0 0x8df4 1 0 5 PEER1_FB_OFFSET_HI 0 19 regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0 0x8df5 2 0 5 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0 0x8df6 1 0 5 PEER2_FB_OFFSET_HI 0 19 regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0 0x8df7 2 0 5 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0 0x8df8 1 0 5 PEER3_FB_OFFSET_HI 0 19 regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0 0x8df9 2 0 5 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0 0x8dfa 4 0 5 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0 0x8dfb 4 0 5 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0 0x8dfd 2 0 5 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0 0x8dfe 5 0 5 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0 0x8dff 2 0 5 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0 0x8e00 1 0 5 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV0_1_RCC_MH_ARB_CNTL 0 0x8e01 2 0 5 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regBIF_BX1_CC_BIF_BX_STRAP0 0 0x8e02 1 0 5 STRAP_RESERVED 25 31 regBIF_BX1_CC_BIF_BX_PINSTRAP0 0 0x8e04 0 0 5 regBIF_BX1_BIF_MM_INDACCESS_CNTL 0 0x8e06 1 0 5 MM_INDACCESS_DIS 1 1 regBIF_BX1_BUS_CNTL 0 0x8e07 15 0 5 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 HDP_FB_FLUSH_STALL_DOORBELL_DIS 24 24 PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS 25 25 PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS 26 26 MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS 27 27 HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS 28 28 HDP_REG_FLUSH_VF_MASK_EN 29 29 VGAFB_ZERO_BE_WR_EN 30 30 VGAFB_ZERO_BE_RD_EN 31 31 regBIF_BX1_BIF_SCRATCH0 0 0x8e08 1 0 5 BIF_SCRATCH0 0 31 regBIF_BX1_BIF_SCRATCH1 0 0x8e09 1 0 5 BIF_SCRATCH1 0 31 regBIF_BX1_BX_RESET_EN 0 0x8e0d 1 0 5 RESET_ON_VFENABLE_LOW_EN 16 16 regBIF_BX1_MM_CFGREGS_CNTL 0 0x8e0e 3 0 5 MM_CFG_FUNC_SEL 0 2 MM_CFG_DEV_SEL 6 7 MM_WR_TO_CFG_EN 31 31 regBIF_BX1_BX_RESET_CNTL 0 0x8e10 1 0 5 LINK_TRAIN_EN 0 0 regBIF_BX1_INTERRUPT_CNTL 0 0x8e11 8 0 5 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 BIF_RB_REQ_NONSNOOP_EN 15 15 DUMMYRD_BYPASS_IN_MSI_EN 16 16 ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS 17 17 BIF_RB_REQ_RELAX_ORDER_EN 18 18 regBIF_BX1_INTERRUPT_CNTL2 0 0x8e12 1 0 5 IH_DUMMY_RD_ADDR 0 31 regBIF_BX1_CLKREQB_PAD_CNTL 0 0x8e18 13 0 5 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_Y 13 13 regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0 0x8e1b 10 0 5 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 BIF_RB_MSI_VEC_NOT_ENABLED_MODE 11 11 BIF_RB_SET_OVERFLOW_EN 12 12 ATOMIC_ERR_INT_DIS 13 13 BME_HDL_NONVIR_EN 15 15 HDP_NP_OSTD_LIMIT 16 23 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR 24 24 regBIF_BX1_BIF_DOORBELL_CNTL 0 0x8e1c 9 0 5 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 DOORBELL_MONITOR_EN 4 4 DB_MNTR_INTGEN_DIS 24 24 DB_MNTR_INTGEN_MODE_0 25 25 DB_MNTR_INTGEN_MODE_1 26 26 DB_MNTR_INTGEN_MODE_2 27 27 regBIF_BX1_BIF_DOORBELL_INT_CNTL 0 0x8e1d 12 0 5 DOORBELL_INTERRUPT_STATUS 0 0 RAS_CNTLR_INTERRUPT_STATUS 1 1 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS 2 2 DOORBELL_INTERRUPT_CLEAR 16 16 RAS_CNTLR_INTERRUPT_CLEAR 17 17 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR 18 18 DOORBELL_INTERRUPT_DISABLE 24 24 RAS_CNTLR_INTERRUPT_DISABLE 25 25 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE 26 26 SET_DB_INTR_STATUS_WHEN_RB_ENABLE 28 28 SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE 29 29 SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE 30 30 regBIF_BX1_BIF_FB_EN 0 0x8e1f 2 0 5 FB_READ_EN 0 0 FB_WRITE_EN 1 1 regBIF_BX1_BIF_INTR_CNTL 0 0x8e20 1 0 5 RAS_INTR_VEC_SEL 0 0 regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0 0x8e29 1 0 5 BIF_MST_TRANS_PENDING 0 30 regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0 0x8e2a 1 0 5 BIF_SLV_TRANS_PENDING 0 30 regBIF_BX1_MEM_TYPE_CNTL 0 0x8e31 1 0 5 BF_MEM_PHY_G5_G3 0 0 regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0 0x8e33 3 0 5 LUT_ENABLE 0 0 MSI_ADDR_MODE 1 1 LUT_BC_MODE 8 8 regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0 0x8e34 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0 0x8e35 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0 0x8e36 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0 0x8e37 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0 0x8e38 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0 0x8e39 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0 0x8e3a 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0 0x8e3b 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0 0x8e3c 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0 0x8e3d 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0 0x8e3e 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0 0x8e3f 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0 0x8e40 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0 0x8e41 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0 0x8e42 1 0 5 ADDR 0 23 regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0 0x8e43 1 0 5 ADDR 0 23 regBIF_BX1_VF_REGWR_EN 0 0x8e44 31 0 5 VF_REGWR_EN_VF0 0 0 VF_REGWR_EN_VF1 1 1 VF_REGWR_EN_VF2 2 2 VF_REGWR_EN_VF3 3 3 VF_REGWR_EN_VF4 4 4 VF_REGWR_EN_VF5 5 5 VF_REGWR_EN_VF6 6 6 VF_REGWR_EN_VF7 7 7 VF_REGWR_EN_VF8 8 8 VF_REGWR_EN_VF9 9 9 VF_REGWR_EN_VF10 10 10 VF_REGWR_EN_VF11 11 11 VF_REGWR_EN_VF12 12 12 VF_REGWR_EN_VF13 13 13 VF_REGWR_EN_VF14 14 14 VF_REGWR_EN_VF15 15 15 VF_REGWR_EN_VF16 16 16 VF_REGWR_EN_VF17 17 17 VF_REGWR_EN_VF18 18 18 VF_REGWR_EN_VF19 19 19 VF_REGWR_EN_VF20 20 20 VF_REGWR_EN_VF21 21 21 VF_REGWR_EN_VF22 22 22 VF_REGWR_EN_VF23 23 23 VF_REGWR_EN_VF24 24 24 VF_REGWR_EN_VF25 25 25 VF_REGWR_EN_VF26 26 26 VF_REGWR_EN_VF27 27 27 VF_REGWR_EN_VF28 28 28 VF_REGWR_EN_VF29 29 29 VF_REGWR_EN_VF30 30 30 regBIF_BX1_VF_DOORBELL_EN 0 0x8e45 32 0 5 VF_DOORBELL_EN_VF0 0 0 VF_DOORBELL_EN_VF1 1 1 VF_DOORBELL_EN_VF2 2 2 VF_DOORBELL_EN_VF3 3 3 VF_DOORBELL_EN_VF4 4 4 VF_DOORBELL_EN_VF5 5 5 VF_DOORBELL_EN_VF6 6 6 VF_DOORBELL_EN_VF7 7 7 VF_DOORBELL_EN_VF8 8 8 VF_DOORBELL_EN_VF9 9 9 VF_DOORBELL_EN_VF10 10 10 VF_DOORBELL_EN_VF11 11 11 VF_DOORBELL_EN_VF12 12 12 VF_DOORBELL_EN_VF13 13 13 VF_DOORBELL_EN_VF14 14 14 VF_DOORBELL_EN_VF15 15 15 VF_DOORBELL_EN_VF16 16 16 VF_DOORBELL_EN_VF17 17 17 VF_DOORBELL_EN_VF18 18 18 VF_DOORBELL_EN_VF19 19 19 VF_DOORBELL_EN_VF20 20 20 VF_DOORBELL_EN_VF21 21 21 VF_DOORBELL_EN_VF22 22 22 VF_DOORBELL_EN_VF23 23 23 VF_DOORBELL_EN_VF24 24 24 VF_DOORBELL_EN_VF25 25 25 VF_DOORBELL_EN_VF26 26 26 VF_DOORBELL_EN_VF27 27 27 VF_DOORBELL_EN_VF28 28 28 VF_DOORBELL_EN_VF29 29 29 VF_DOORBELL_EN_VF30 30 30 VF_DOORBELL_RD_LOG_DIS 31 31 regBIF_BX1_VF_FB_EN 0 0x8e46 31 0 5 VF_FB_EN_VF0 0 0 VF_FB_EN_VF1 1 1 VF_FB_EN_VF2 2 2 VF_FB_EN_VF3 3 3 VF_FB_EN_VF4 4 4 VF_FB_EN_VF5 5 5 VF_FB_EN_VF6 6 6 VF_FB_EN_VF7 7 7 VF_FB_EN_VF8 8 8 VF_FB_EN_VF9 9 9 VF_FB_EN_VF10 10 10 VF_FB_EN_VF11 11 11 VF_FB_EN_VF12 12 12 VF_FB_EN_VF13 13 13 VF_FB_EN_VF14 14 14 VF_FB_EN_VF15 15 15 VF_FB_EN_VF16 16 16 VF_FB_EN_VF17 17 17 VF_FB_EN_VF18 18 18 VF_FB_EN_VF19 19 19 VF_FB_EN_VF20 20 20 VF_FB_EN_VF21 21 21 VF_FB_EN_VF22 22 22 VF_FB_EN_VF23 23 23 VF_FB_EN_VF24 24 24 VF_FB_EN_VF25 25 25 VF_FB_EN_VF26 26 26 VF_FB_EN_VF27 27 27 VF_FB_EN_VF28 28 28 VF_FB_EN_VF29 29 29 VF_FB_EN_VF30 30 30 regBIF_BX1_VF_REGWR_STATUS 0 0x8e47 31 0 5 VF_REGWR_STATUS_VF0 0 0 VF_REGWR_STATUS_VF1 1 1 VF_REGWR_STATUS_VF2 2 2 VF_REGWR_STATUS_VF3 3 3 VF_REGWR_STATUS_VF4 4 4 VF_REGWR_STATUS_VF5 5 5 VF_REGWR_STATUS_VF6 6 6 VF_REGWR_STATUS_VF7 7 7 VF_REGWR_STATUS_VF8 8 8 VF_REGWR_STATUS_VF9 9 9 VF_REGWR_STATUS_VF10 10 10 VF_REGWR_STATUS_VF11 11 11 VF_REGWR_STATUS_VF12 12 12 VF_REGWR_STATUS_VF13 13 13 VF_REGWR_STATUS_VF14 14 14 VF_REGWR_STATUS_VF15 15 15 VF_REGWR_STATUS_VF16 16 16 VF_REGWR_STATUS_VF17 17 17 VF_REGWR_STATUS_VF18 18 18 VF_REGWR_STATUS_VF19 19 19 VF_REGWR_STATUS_VF20 20 20 VF_REGWR_STATUS_VF21 21 21 VF_REGWR_STATUS_VF22 22 22 VF_REGWR_STATUS_VF23 23 23 VF_REGWR_STATUS_VF24 24 24 VF_REGWR_STATUS_VF25 25 25 VF_REGWR_STATUS_VF26 26 26 VF_REGWR_STATUS_VF27 27 27 VF_REGWR_STATUS_VF28 28 28 VF_REGWR_STATUS_VF29 29 29 VF_REGWR_STATUS_VF30 30 30 regBIF_BX1_VF_DOORBELL_STATUS 0 0x8e48 31 0 5 VF_DOORBELL_STATUS_VF0 0 0 VF_DOORBELL_STATUS_VF1 1 1 VF_DOORBELL_STATUS_VF2 2 2 VF_DOORBELL_STATUS_VF3 3 3 VF_DOORBELL_STATUS_VF4 4 4 VF_DOORBELL_STATUS_VF5 5 5 VF_DOORBELL_STATUS_VF6 6 6 VF_DOORBELL_STATUS_VF7 7 7 VF_DOORBELL_STATUS_VF8 8 8 VF_DOORBELL_STATUS_VF9 9 9 VF_DOORBELL_STATUS_VF10 10 10 VF_DOORBELL_STATUS_VF11 11 11 VF_DOORBELL_STATUS_VF12 12 12 VF_DOORBELL_STATUS_VF13 13 13 VF_DOORBELL_STATUS_VF14 14 14 VF_DOORBELL_STATUS_VF15 15 15 VF_DOORBELL_STATUS_VF16 16 16 VF_DOORBELL_STATUS_VF17 17 17 VF_DOORBELL_STATUS_VF18 18 18 VF_DOORBELL_STATUS_VF19 19 19 VF_DOORBELL_STATUS_VF20 20 20 VF_DOORBELL_STATUS_VF21 21 21 VF_DOORBELL_STATUS_VF22 22 22 VF_DOORBELL_STATUS_VF23 23 23 VF_DOORBELL_STATUS_VF24 24 24 VF_DOORBELL_STATUS_VF25 25 25 VF_DOORBELL_STATUS_VF26 26 26 VF_DOORBELL_STATUS_VF27 27 27 VF_DOORBELL_STATUS_VF28 28 28 VF_DOORBELL_STATUS_VF29 29 29 VF_DOORBELL_STATUS_VF30 30 30 regBIF_BX1_VF_FB_STATUS 0 0x8e49 31 0 5 VF_FB_STATUS_VF0 0 0 VF_FB_STATUS_VF1 1 1 VF_FB_STATUS_VF2 2 2 VF_FB_STATUS_VF3 3 3 VF_FB_STATUS_VF4 4 4 VF_FB_STATUS_VF5 5 5 VF_FB_STATUS_VF6 6 6 VF_FB_STATUS_VF7 7 7 VF_FB_STATUS_VF8 8 8 VF_FB_STATUS_VF9 9 9 VF_FB_STATUS_VF10 10 10 VF_FB_STATUS_VF11 11 11 VF_FB_STATUS_VF12 12 12 VF_FB_STATUS_VF13 13 13 VF_FB_STATUS_VF14 14 14 VF_FB_STATUS_VF15 15 15 VF_FB_STATUS_VF16 16 16 VF_FB_STATUS_VF17 17 17 VF_FB_STATUS_VF18 18 18 VF_FB_STATUS_VF19 19 19 VF_FB_STATUS_VF20 20 20 VF_FB_STATUS_VF21 21 21 VF_FB_STATUS_VF22 22 22 VF_FB_STATUS_VF23 23 23 VF_FB_STATUS_VF24 24 24 VF_FB_STATUS_VF25 25 25 VF_FB_STATUS_VF26 26 26 VF_FB_STATUS_VF27 27 27 VF_FB_STATUS_VF28 28 28 VF_FB_STATUS_VF29 29 29 VF_FB_STATUS_VF30 30 30 regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0 0x8e4d 1 0 5 ADDRESS 2 18 regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0 0x8e4e 1 0 5 ADDRESS 2 18 regBIF_BX1_BIF_RB_CNTL 0 0x8e4f 9 0 5 RB_ENABLE 0 0 RB_SIZE 1 5 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 BIF_RB_TRAN 17 17 RB_INTR_FIX_PRIORITY 26 28 RB_INTR_ARB_MODE 29 29 RB_RST_BY_FLR_DISABLE 30 30 WPTR_OVERFLOW_CLEAR 31 31 regBIF_BX1_BIF_RB_BASE 0 0x8e50 1 0 5 ADDR 0 31 regBIF_BX1_BIF_RB_RPTR 0 0x8e51 1 0 5 OFFSET 2 17 regBIF_BX1_BIF_RB_WPTR 0 0x8e52 2 0 5 BIF_RB_OVERFLOW 0 0 OFFSET 2 17 regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0 0x8e53 1 0 5 ADDR 0 7 regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0 0x8e54 1 0 5 ADDR 2 31 regBIF_BX1_MAILBOX_INDEX 0 0x8e55 1 0 5 MAILBOX_INDEX 0 4 regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0 0x8e63 1 0 5 VCN0_GPUIOV_CFG_SIZE 0 3 regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0 0x8e64 1 0 5 VCN1_GPUIOV_CFG_SIZE 0 3 regBIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0 0x8e65 1 0 5 GFX_SDMA_GPUIOV_CFG_SIZE 0 3 regBIF_BX1_BIF_PERSTB_PAD_CNTL 0 0x8e68 1 0 5 PERSTB_PAD_CNTL 0 15 regBIF_BX1_BIF_PX_EN_PAD_CNTL 0 0x8e69 1 0 5 PX_EN_PAD_CNTL 0 7 regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0 0x8e6a 1 0 5 REFPADKIN_PAD_CNTL 0 7 regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0 0x8e6b 1 0 5 CLKREQB_PAD_CNTL 0 23 regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0 0x8e6c 1 0 5 PWRBRK_PAD_CNTL 0 7 regBIF_BX1_BIF_WAKEB_PAD_CNTL 0 0x8e6d 8 0 5 GPIO33_ITXIMPSEL 0 0 GPIO33_ICTFEN 1 1 GPIO33_IPD 2 2 GPIO33_IPU 3 3 GPIO33_IRXEN 4 4 GPIO33_IRXSEL0 5 5 GPIO33_IRXSEL1 6 6 GPIO33_RESERVED 7 7 regBIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL 0 0x8e6e 6 0 5 GPIO_IPD 0 0 GPIO_IPU 1 1 GPIO_IRXEN 2 2 GPIO_IRXSEL0 3 3 GPIO_IRXSEL1 4 4 GPIO_ITXIMPSEL 5 5 regBIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL 0 0x8e70 2 0 5 PCIE_PAR_SAVE_VALID 0 0 PCIE_PAR_SAVE_SCRATCH 1 31 regBIF_BX1_BIF_S5_MEM_POWER_CTRL0 0 0x8e71 1 0 5 MEM_POWER_CTRL_S5_31_0 0 31 regBIF_BX1_BIF_S5_MEM_POWER_CTRL1 0 0x8e72 2 0 5 MEM_POWER_CTRL_S5_41_32 0 9 MEM_POWER_CTRL_SEL 10 10 regBIF_BX1_BIF_S5_DUMMY_REGS 0 0x8e73 1 0 5 BIF_S5_DUMMY_REGS 0 31 regBIF_BX_PF1_BIF_BME_STATUS 0 0x8e0b 2 0 5 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0 0x8e0c 8 0 5 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0x8e13 1 0 5 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0x8e14 1 0 5 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0 0x8e15 3 0 5 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0 0x8e16 1 0 5 HDP_REG_FLUSH_ADDR 0 0 regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0x8e17 1 0 5 HDP_MEM_FLUSH_ADDR 0 0 regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0 0x8e19 1 0 5 HDP_MEM_FLUSH_ONLY_ADDR 0 0 regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0 0x8e1a 1 0 5 HDP_MEM_INVALIDATE_ONLY_ADDR 0 0 regBIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ 0 0x8e24 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ 0 0x8e25 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0 0x8e26 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0 0x8e27 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF1_BIF_TRANS_PENDING 0 0x8e28 2 0 5 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0 0x8e32 1 0 5 LUT_BYPASS 0 0 regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0 0x8e56 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0 0x8e57 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0 0x8e58 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0 0x8e59 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0 0x8e5a 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0 0x8e5b 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0 0x8e5c 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0 0x8e5d 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF1_MAILBOX_CONTROL 0 0x8e5e 4 0 5 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 regBIF_BX_PF1_MAILBOX_INT_CNTL 0 0x8e5f 2 0 5 VALID_INT_EN 0 0 ACK_INT_EN 1 1 regBIF_BX_PF1_BIF_VMHV_MAILBOX 0 0x8e60 8 0 5 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0 0xc400 10 0 5 STRAP_ARI_EN_DN_DEV0 1 1 STRAP_ACS_EN_DN_DEV0 2 2 STRAP_AER_EN_DN_DEV0 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 4 4 STRAP_DEVICE_ID_DN_DEV0 5 20 STRAP_INTERRUPT_PIN_DN_DEV0 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 28 30 STRAP_EPF0_DUMMY_EN_DEV0 31 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0 0xc401 2 0 5 STRAP_SUBSYS_ID_DN_DEV0 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0 16 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0 0xc402 20 0 5 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 1 1 STRAP_E2E_PREFIX_EN_DEV0 2 2 STRAP_ECN1P1_EN_DEV0 3 3 STRAP_ECRC_CHECK_EN_DEV0 4 4 STRAP_ERR_REPORTING_DIS_DEV0 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0 8 8 STRAP_EXT_VC_COUNT_DN_DEV0 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 13 13 STRAP_GEN2_COMPLIANCE_DEV0 14 14 STRAP_GEN2_EN_DEV0 15 15 STRAP_GEN3_COMPLIANCE_DEV0 16 16 STRAP_GEN4_COMPLIANCE_DEV0 17 17 STRAP_TARGET_LINK_SPEED_DEV0 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 20 22 STRAP_L0S_EXIT_LATENCY_DEV0 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 26 28 STRAP_L1_EXIT_LATENCY_DEV0 29 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0 0xc403 16 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 1 1 STRAP_LTR_EN_DN_DEV0 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 3 5 STRAP_MSI_EN_DN_DEV0 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0 7 7 STRAP_NO_SOFT_RESET_DN_DEV0 8 8 STRAP_OBFF_SUPPORTED_DEV0 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 21 24 STRAP_PM_SUPPORT_DEV0 25 26 STRAP_PM_SUPPORT_DN_DEV0 27 28 STRAP_ATOMIC_EN_DN_DEV0 29 29 STRAP_PMC_DSI_DN_DEV0 31 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0 0xc404 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 24 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0 0xc405 18 0 5 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0 18 18 STRAP_VC_EN_DN_DEV0 19 19 STRAP_TwoVC_EN_DEV0 20 20 STRAP_TwoVC_EN_DN_DEV0 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV0 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 29 29 STRAP_MSI_MAP_EN_DEV0 30 30 STRAP_SSID_EN_DEV0 31 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0 0xc406 12 0 5 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV0 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0 19 19 regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0 0xc407 6 0 5 STRAP_PORT_NUMBER_DEV0 0 7 STRAP_MAJOR_REV_ID_DN_DEV0 8 11 STRAP_MINOR_REV_ID_DN_DEV0 12 15 STRAP_RP_BUSNUM_DEV0 16 23 STRAP_DN_DEVNUM_DEV0 24 28 STRAP_DN_FUNCID_DEV0 29 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0 0xc408 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_6_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV0 24 31 regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0 0xc409 3 0 5 STRAP_PWR_BUDGET_DATA_8T0_a_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV0 8 15 STRAP_VENDOR_ID_DN_DEV0 16 31 regRCC_DEV1_PORT_STRAP0 0 0xc480 10 0 5 STRAP_ARI_EN_DN_DEV1 1 1 STRAP_ACS_EN_DN_DEV1 2 2 STRAP_AER_EN_DN_DEV1 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV1 4 4 STRAP_DEVICE_ID_DN_DEV1 5 20 STRAP_INTERRUPT_PIN_DN_DEV1 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1 28 30 STRAP_EPF0_DUMMY_EN_DEV1 31 31 regRCC_DEV1_PORT_STRAP1 0 0xc481 2 0 5 STRAP_SUBSYS_ID_DN_DEV1 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV1 16 31 regRCC_DEV1_PORT_STRAP2 0 0xc482 20 0 5 STRAP_DE_EMPHASIS_SEL_DN_DEV1 0 0 STRAP_DSN_EN_DN_DEV1 1 1 STRAP_E2E_PREFIX_EN_DEV1 2 2 STRAP_ECN1P1_EN_DEV1 3 3 STRAP_ECRC_CHECK_EN_DEV1 4 4 STRAP_ERR_REPORTING_DIS_DEV1 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV1 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV1 8 8 STRAP_EXT_VC_COUNT_DN_DEV1 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1 13 13 STRAP_GEN2_COMPLIANCE_DEV1 14 14 STRAP_GEN2_EN_DEV1 15 15 STRAP_GEN3_COMPLIANCE_DEV1 16 16 STRAP_GEN4_COMPLIANCE_DEV1 17 17 STRAP_TARGET_LINK_SPEED_DEV1 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV1 20 22 STRAP_L0S_EXIT_LATENCY_DEV1 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV1 26 28 STRAP_L1_EXIT_LATENCY_DEV1 29 31 regRCC_DEV1_PORT_STRAP3 0 0xc483 16 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1 0 0 STRAP_LTR_EN_DEV1 1 1 STRAP_LTR_EN_DN_DEV1 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV1 3 5 STRAP_MSI_EN_DN_DEV1 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV1 7 7 STRAP_NO_SOFT_RESET_DN_DEV1 8 8 STRAP_OBFF_SUPPORTED_DEV1 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1 21 24 STRAP_PM_SUPPORT_DEV1 25 26 STRAP_PM_SUPPORT_DN_DEV1 27 28 STRAP_ATOMIC_EN_DN_DEV1 29 29 STRAP_PMC_DSI_DN_DEV1 31 31 regRCC_DEV1_PORT_STRAP4 0 0xc484 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_0_DEV1 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV1 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV1 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV1 24 31 regRCC_DEV1_PORT_STRAP5 0 0xc485 18 0 5 STRAP_PWR_BUDGET_DATA_8T0_4_DEV1 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV1 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV1 17 17 STRAP_ATOMIC_ROUTING_EN_DEV1 18 18 STRAP_VC_EN_DN_DEV1 19 19 STRAP_TwoVC_EN_DEV1 20 20 STRAP_TwoVC_EN_DN_DEV1 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV1 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV1 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1 29 29 STRAP_MSI_MAP_EN_DEV1 30 30 STRAP_SSID_EN_DEV1 31 31 regRCC_DEV1_PORT_STRAP6 0 0xc486 12 0 5 STRAP_CFG_CRS_EN_DEV1 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV1 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV1 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV1 19 19 regRCC_DEV1_PORT_STRAP7 0 0xc487 6 0 5 STRAP_PORT_NUMBER_DEV1 0 7 STRAP_MAJOR_REV_ID_DN_DEV1 8 11 STRAP_MINOR_REV_ID_DN_DEV1 12 15 STRAP_RP_BUSNUM_DEV1 16 23 STRAP_DN_DEVNUM_DEV1 24 28 STRAP_DN_FUNCID_DEV1 29 31 regRCC_DEV1_PORT_STRAP8 0 0xc488 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_6_DEV1 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV1 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV1 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV1 24 31 regRCC_DEV1_PORT_STRAP9 0 0xc489 3 0 5 STRAP_PWR_BUDGET_DATA_8T0_a_DEV1 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV1 8 15 STRAP_VENDOR_ID_DN_DEV1 16 31 regRCC_DEV2_PORT_STRAP0 0 0xc500 10 0 5 STRAP_ARI_EN_DN_DEV2 1 1 STRAP_ACS_EN_DN_DEV2 2 2 STRAP_AER_EN_DN_DEV2 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV2 4 4 STRAP_DEVICE_ID_DN_DEV2 5 20 STRAP_INTERRUPT_PIN_DN_DEV2 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2 28 30 STRAP_EPF0_DUMMY_EN_DEV2 31 31 regRCC_DEV2_PORT_STRAP1 0 0xc501 2 0 5 STRAP_SUBSYS_ID_DN_DEV2 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV2 16 31 regRCC_DEV2_PORT_STRAP2 0 0xc502 20 0 5 STRAP_DE_EMPHASIS_SEL_DN_DEV2 0 0 STRAP_DSN_EN_DN_DEV2 1 1 STRAP_E2E_PREFIX_EN_DEV2 2 2 STRAP_ECN1P1_EN_DEV2 3 3 STRAP_ECRC_CHECK_EN_DEV2 4 4 STRAP_ERR_REPORTING_DIS_DEV2 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV2 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV2 8 8 STRAP_EXT_VC_COUNT_DN_DEV2 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2 13 13 STRAP_GEN2_COMPLIANCE_DEV2 14 14 STRAP_GEN2_EN_DEV2 15 15 STRAP_GEN3_COMPLIANCE_DEV2 16 16 STRAP_GEN4_COMPLIANCE_DEV2 17 17 STRAP_TARGET_LINK_SPEED_DEV2 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV2 20 22 STRAP_L0S_EXIT_LATENCY_DEV2 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV2 26 28 STRAP_L1_EXIT_LATENCY_DEV2 29 31 regRCC_DEV2_PORT_STRAP3 0 0xc503 16 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2 0 0 STRAP_LTR_EN_DEV2 1 1 STRAP_LTR_EN_DN_DEV2 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV2 3 5 STRAP_MSI_EN_DN_DEV2 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV2 7 7 STRAP_NO_SOFT_RESET_DN_DEV2 8 8 STRAP_OBFF_SUPPORTED_DEV2 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2 21 24 STRAP_PM_SUPPORT_DEV2 25 26 STRAP_PM_SUPPORT_DN_DEV2 27 28 STRAP_ATOMIC_EN_DN_DEV2 29 29 STRAP_PMC_DSI_DN_DEV2 31 31 regRCC_DEV2_PORT_STRAP4 0 0xc504 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_0_DEV2 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV2 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV2 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV2 24 31 regRCC_DEV2_PORT_STRAP5 0 0xc505 18 0 5 STRAP_PWR_BUDGET_DATA_8T0_4_DEV2 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV2 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV2 17 17 STRAP_ATOMIC_ROUTING_EN_DEV2 18 18 STRAP_VC_EN_DN_DEV2 19 19 STRAP_TwoVC_EN_DEV2 20 20 STRAP_TwoVC_EN_DN_DEV2 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV2 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV2 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2 29 29 STRAP_MSI_MAP_EN_DEV2 30 30 STRAP_SSID_EN_DEV2 31 31 regRCC_DEV2_PORT_STRAP6 0 0xc506 12 0 5 STRAP_CFG_CRS_EN_DEV2 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV2 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV2 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV2 19 19 regRCC_DEV2_PORT_STRAP7 0 0xc507 6 0 5 STRAP_PORT_NUMBER_DEV2 0 7 STRAP_MAJOR_REV_ID_DN_DEV2 8 11 STRAP_MINOR_REV_ID_DN_DEV2 12 15 STRAP_RP_BUSNUM_DEV2 16 23 STRAP_DN_DEVNUM_DEV2 24 28 STRAP_DN_FUNCID_DEV2 29 31 regRCC_DEV2_PORT_STRAP8 0 0xc508 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_6_DEV2 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV2 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV2 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV2 24 31 regRCC_DEV2_PORT_STRAP9 0 0xc509 3 0 5 STRAP_PWR_BUDGET_DATA_8T0_a_DEV2 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV2 8 15 STRAP_VENDOR_ID_DN_DEV2 16 31 regRCC_STRAP2_RCC_BIF_STRAP0 0 0xc600 22 0 5 STRAP_GEN4_DIS_PIN 0 0 STRAP_VGA_DIS_PIN 2 2 STRAP_MEM_AP_SIZE_PIN 3 5 STRAP_BIOS_ROM_EN_PIN 6 6 STRAP_PX_CAPABLE 7 7 STRAP_BIF_KILL_GEN3 8 8 STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN 9 9 STRAP_NBIF_IGNORE_ERR_INFLR 10 10 STRAP_PME_SUPPORT_COMPLIANCE_EN 11 11 STRAP_RX_IGNORE_EP_ERR 12 12 STRAP_RX_IGNORE_MSG_ERR 13 13 STRAP_RX_IGNORE_MAX_PAYLOAD_ERR 14 14 STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN 15 15 STRAP_RX_IGNORE_TC_ERR 16 16 STRAP_RX_IGNORE_TC_ERR_DN 17 17 STRAP_GEN3_DIS 24 24 STRAP_BIF_KILL_GEN4 25 25 STRAP_QUICKSIM_START 26 26 STRAP_NO_RO_ENABLED_P2P_PASSING 27 27 STRAP_CFG0_RD_VF_BUSNUM_CHK_EN 29 29 STRAP_BIGAPU_MODE 30 30 STRAP_LINK_DOWN_RESET_EN 31 31 regRCC_STRAP2_RCC_BIF_STRAP1 0 0xc601 21 0 5 ROMSTRAP_VALID 1 1 STRAP_ECRC_INTERMEDIATE_CHK_EN 3 3 STRAP_IGNORE_E2E_PREFIX_UR_SWUS 5 5 STRAP_MARGINING_USES_SOFTWARE 6 6 STRAP_MARGINING_READY 7 7 STRAP_SWUS_APER_EN 8 8 STRAP_SWUS_64BAR_EN 9 9 STRAP_SWUS_AP_SIZE 10 11 STRAP_SWUS_APER_PREFETCHABLE 12 12 STRAP_HWREV_LSB2 13 14 STRAP_SWREV_LSB2 15 16 STRAP_LINK_RST_CFG_ONLY 17 17 STRAP_BIF_IOV_LKRST_DIS 18 18 STRAP_DLF_EN 19 19 STRAP_PHY_16GT_EN 20 20 STRAP_MARGIN_EN 21 21 STRAP_BIF_PSN_UR_RPT_EN 22 22 STRAP_BIF_SLOT_POWER_SUPPORT_EN 23 23 STRAP_GFX_FUNC_LTR_MODE 26 26 STRAP_GSI_SMN_POSTWR_MULTI_EN 27 28 STRAP_DLF_EN_EP 29 29 regRCC_STRAP2_RCC_BIF_STRAP2 0 0xc602 14 0 5 STRAP_PCIESWUS_INDEX_APER_RANGE 0 0 STRAP_SUC_IND_ACCESS_DIS 3 3 STRAP_SUM_IND_ACCESS_DIS 4 4 STRAP_ENDP_LINKDOWN_DROP_DMA 5 5 STRAP_SWITCH_LINKDOWN_DROP_DMA 6 6 STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS 8 8 STRAP_ACS_MSKSEV_EP_HIDE_DIS 9 9 STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN 10 11 RESERVED_BIF_STRAP2 13 13 STRAP_LTR_IN_ASPML1_DIS 14 14 STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN 15 15 STRAP_PWRBRK_DEGLITCH_CYCLE 16 23 STRAP_PWRBRK_DEGLITCH_BYPASS 24 24 STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS 31 31 regRCC_STRAP2_RCC_BIF_STRAP3 0 0xc603 2 0 5 STRAP_VLINK_ASPM_IDLE_TIMER 0 15 STRAP_VLINK_PM_L1_ENTRY_TIMER 16 31 regRCC_STRAP2_RCC_BIF_STRAP4 0 0xc604 2 0 5 STRAP_VLINK_L0S_EXIT_TIMER 0 15 STRAP_VLINK_L1_EXIT_TIMER 16 31 regRCC_STRAP2_RCC_BIF_STRAP5 0 0xc605 11 0 5 STRAP_VLINK_LDN_ENTRY_TIMER 0 15 STRAP_VLINK_LDN_ON_SWUS_LDN_EN 16 16 STRAP_VLINK_LDN_ON_SWUS_SECRST_EN 17 17 STRAP_VLINK_ENTER_COMPLIANCE_DIS 18 18 STRAP_IGNORE_PSN_ON_VDM1_DIS 19 19 STRAP_SMN_ERR_STATUS_MASK_EN_UPS 20 20 STRAP_SMN_ERRRSP_DATA_FORCE 22 23 STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE 24 24 STRAP_EMER_POWER_REDUCTION_SUPPORTED 25 26 STRAP_EMER_POWER_REDUCTION_INIT_REQ 27 27 STRAP_PWRBRK_STATUS_TIMER 28 30 regRCC_STRAP2_RCC_BIF_STRAP6 0 0xc606 0 0 5 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0 0xd000 8 0 5 STRAP_DEVICE_ID_DEV0_F0 0 15 STRAP_MAJOR_REV_ID_DEV0_F0 16 19 STRAP_MINOR_REV_ID_DEV0_F0 20 23 STRAP_ATI_REV_ID_DEV0_F0 24 27 STRAP_FUNC_EN_DEV0_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 29 29 STRAP_D1_SUPPORT_DEV0_F0 30 30 STRAP_D2_SUPPORT_DEV0_F0 31 31 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0 0xd001 2 0 5 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 16 31 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0 0xd002 21 0 5 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 1 5 STRAP_64BAR_DIS_DEV0_F0 6 6 STRAP_NO_SOFT_RESET_DEV0_F0 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 14 14 STRAP_ARI_EN_DEV0_F0 15 15 STRAP_AER_EN_DEV0_F0 16 16 STRAP_ACS_EN_DEV0_F0 17 17 STRAP_ATS_EN_DEV0_F0 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 20 20 STRAP_DPA_EN_DEV0_F0 21 21 STRAP_DSN_EN_DEV0_F0 22 22 STRAP_VC_EN_DEV0_F0 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0 24 26 STRAP_PAGE_REQ_EN_DEV0_F0 27 27 STRAP_PASID_EN_DEV0_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 31 31 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0 0xd003 13 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 1 1 STRAP_SUBSYS_ID_DEV0_F0 2 17 STRAP_MSI_EN_DEV0_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 19 19 STRAP_MSIX_EN_DEV0_F0 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0 21 23 STRAP_PMC_DSI_DEV0_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 27 27 STRAP_VF_RESIZE_BAR_EN_DEV0_F0 28 28 STRAP_CLK_PM_EN_DEV0_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F0 30 30 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0 0xd004 7 0 5 STRAP_RESERVED_STRAP4_DEV0_F0 0 9 STRAP_ATOMIC_64BIT_EN_DEV0_F0 20 20 STRAP_ATOMIC_EN_DEV0_F0 21 21 STRAP_FLR_EN_DEV0_F0 22 22 STRAP_PME_SUPPORT_DEV0_F0 23 27 STRAP_INTERRUPT_PIN_DEV0_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0 31 31 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0 0xd005 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0 30 30 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0 0xd008 13 0 5 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0 3 3 STRAP_ROM_AP_SIZE_DEV0_F0 4 6 STRAP_IO_BAR_DIS_DEV0_F0 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0 8 8 STRAP_MEM_AP_SIZE_DEV0_F0 9 12 STRAP_REG_AP_SIZE_DEV0_F0 13 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0 19 22 STRAP_VF_REG_AP_SIZE_DEV0_F0 23 25 STRAP_VGA_DIS_DEV0_F0 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 30 31 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0 0xd009 7 0 5 STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0 0 15 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 18 18 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 19 19 STRAP_VF_REG_PROT_DIS_DEV0_F0 20 20 STRAP_FB_ALWAYS_ON_DEV0_F0 21 21 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 22 23 STRAP_GPUIOV_VSEC_REV_DEV0_F0 24 27 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0 0xd00d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F0 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0 16 23 regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0 0xd00e 1 0 5 STRAP_VENDOR_ID_DEV0_F0 0 15 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0 0xd080 7 0 5 STRAP_DEVICE_ID_DEV0_F1 0 15 STRAP_MAJOR_REV_ID_DEV0_F1 16 19 STRAP_MINOR_REV_ID_DEV0_F1 20 23 STRAP_FUNC_EN_DEV0_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 29 29 STRAP_D1_SUPPORT_DEV0_F1 30 30 STRAP_D2_SUPPORT_DEV0_F1 31 31 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0 0xd082 16 0 5 STRAP_NO_SOFT_RESET_DEV0_F1 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 14 14 STRAP_AER_EN_DEV0_F1 16 16 STRAP_ACS_EN_DEV0_F1 17 17 STRAP_ATS_EN_DEV0_F1 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 20 20 STRAP_DPA_EN_DEV0_F1 21 21 STRAP_DSN_EN_DEV0_F1 22 22 STRAP_VC_EN_DEV0_F1 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1 24 26 STRAP_PASID_EN_DEV0_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1 31 31 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0 0xd083 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 1 1 STRAP_SUBSYS_ID_DEV0_F1 2 17 STRAP_MSI_EN_DEV0_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 19 19 STRAP_MSIX_EN_DEV0_F1 20 20 STRAP_PMC_DSI_DEV0_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 27 27 STRAP_CLK_PM_EN_DEV0_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F1 30 30 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0 0xd084 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F1 20 20 STRAP_ATOMIC_EN_DEV0_F1 21 21 STRAP_FLR_EN_DEV0_F1 22 22 STRAP_PME_SUPPORT_DEV0_F1 23 27 STRAP_INTERRUPT_PIN_DEV0_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1 31 31 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0 0xd085 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1 30 30 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0 0xd086 3 0 5 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 1 1 STRAP_APER0_64BAR_EN_DEV0_F1 2 2 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0 0xd087 0 0 5 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10 0 0xd08a 0 0 5 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11 0 0xd08b 0 0 5 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12 0 0xd08c 0 0 5 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13 0 0xd08d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F1 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1 16 23 regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14 0 0xd08e 1 0 5 STRAP_VENDOR_ID_DEV0_F1 0 15 regRCC_DEV0_EPF2_STRAP0 0 0xd100 7 0 5 STRAP_DEVICE_ID_DEV0_F2 0 15 STRAP_MAJOR_REV_ID_DEV0_F2 16 19 STRAP_MINOR_REV_ID_DEV0_F2 20 23 STRAP_FUNC_EN_DEV0_F2 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2 29 29 STRAP_D1_SUPPORT_DEV0_F2 30 30 STRAP_D2_SUPPORT_DEV0_F2 31 31 regRCC_DEV0_EPF2_STRAP2 0 0xd102 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F2 7 7 STRAP_RESIZE_BAR_EN_DEV0_F2 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F2 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2 14 14 STRAP_AER_EN_DEV0_F2 16 16 STRAP_ACS_EN_DEV0_F2 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F2 20 20 STRAP_DPA_EN_DEV0_F2 21 21 STRAP_VC_EN_DEV0_F2 23 23 STRAP_MSI_MULTI_CAP_DEV0_F2 24 26 STRAP_PASID_EN_DEV0_F2 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2 31 31 regRCC_DEV0_EPF2_STRAP3 0 0xd103 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2 0 0 STRAP_PWR_EN_DEV0_F2 1 1 STRAP_SUBSYS_ID_DEV0_F2 2 17 STRAP_MSI_EN_DEV0_F2 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F2 19 19 STRAP_MSIX_EN_DEV0_F2 20 20 STRAP_PMC_DSI_DEV0_F2 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2 27 27 STRAP_CLK_PM_EN_DEV0_F2 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F2 30 30 regRCC_DEV0_EPF2_STRAP4 0 0xd104 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F2 20 20 STRAP_ATOMIC_EN_DEV0_F2 21 21 STRAP_FLR_EN_DEV0_F2 22 22 STRAP_PME_SUPPORT_DEV0_F2 23 27 STRAP_INTERRUPT_PIN_DEV0_F2 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F2 31 31 regRCC_DEV0_EPF2_STRAP5 0 0xd105 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F2 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2 30 30 regRCC_DEV0_EPF2_STRAP6 0 0xd106 4 0 5 STRAP_APER0_EN_DEV0_F2 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F2 1 1 STRAP_APER1_EN_DEV0_F2 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F2 9 9 regRCC_DEV0_EPF2_STRAP7 0 0xd107 0 0 5 regRCC_DEV0_EPF2_STRAP10 0 0xd10a 0 0 5 regRCC_DEV0_EPF2_STRAP11 0 0xd10b 0 0 5 regRCC_DEV0_EPF2_STRAP12 0 0xd10c 0 0 5 regRCC_DEV0_EPF2_STRAP13 0 0xd10d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F2 0 7 STRAP_CLASS_CODE_SUB_DEV0_F2 8 15 STRAP_CLASS_CODE_BASE_DEV0_F2 16 23 regRCC_DEV0_EPF2_STRAP14 0 0xd10e 1 0 5 STRAP_VENDOR_ID_DEV0_F2 0 15 regRCC_DEV0_EPF3_STRAP0 0 0xd180 7 0 5 STRAP_DEVICE_ID_DEV0_F3 0 15 STRAP_MAJOR_REV_ID_DEV0_F3 16 19 STRAP_MINOR_REV_ID_DEV0_F3 20 23 STRAP_FUNC_EN_DEV0_F3 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3 29 29 STRAP_D1_SUPPORT_DEV0_F3 30 30 STRAP_D2_SUPPORT_DEV0_F3 31 31 regRCC_DEV0_EPF3_STRAP2 0 0xd182 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F3 7 7 STRAP_RESIZE_BAR_EN_DEV0_F3 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F3 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3 14 14 STRAP_AER_EN_DEV0_F3 16 16 STRAP_ACS_EN_DEV0_F3 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F3 20 20 STRAP_DPA_EN_DEV0_F3 21 21 STRAP_VC_EN_DEV0_F3 23 23 STRAP_MSI_MULTI_CAP_DEV0_F3 24 26 STRAP_PASID_EN_DEV0_F3 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3 31 31 regRCC_DEV0_EPF3_STRAP3 0 0xd183 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3 0 0 STRAP_PWR_EN_DEV0_F3 1 1 STRAP_SUBSYS_ID_DEV0_F3 2 17 STRAP_MSI_EN_DEV0_F3 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F3 19 19 STRAP_MSIX_EN_DEV0_F3 20 20 STRAP_PMC_DSI_DEV0_F3 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3 27 27 STRAP_CLK_PM_EN_DEV0_F3 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F3 30 30 regRCC_DEV0_EPF3_STRAP4 0 0xd184 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F3 20 20 STRAP_ATOMIC_EN_DEV0_F3 21 21 STRAP_FLR_EN_DEV0_F3 22 22 STRAP_PME_SUPPORT_DEV0_F3 23 27 STRAP_INTERRUPT_PIN_DEV0_F3 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F3 31 31 regRCC_DEV0_EPF3_STRAP5 0 0xd185 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F3 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3 30 30 regRCC_DEV0_EPF3_STRAP6 0 0xd186 2 0 5 STRAP_APER0_EN_DEV0_F3 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F3 1 1 regRCC_DEV0_EPF3_STRAP7 0 0xd187 1 0 5 STRAP_MSIX_TABLE_SIZE_DEV0_F3 5 15 regRCC_DEV0_EPF3_STRAP10 0 0xd18a 0 0 5 regRCC_DEV0_EPF3_STRAP11 0 0xd18b 0 0 5 regRCC_DEV0_EPF3_STRAP12 0 0xd18c 0 0 5 regRCC_DEV0_EPF3_STRAP13 0 0xd18d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F3 0 7 STRAP_CLASS_CODE_SUB_DEV0_F3 8 15 STRAP_CLASS_CODE_BASE_DEV0_F3 16 23 regRCC_DEV0_EPF3_STRAP14 0 0xd18e 1 0 5 STRAP_VENDOR_ID_DEV0_F3 0 15 regRCC_DEV0_EPF4_STRAP0 0 0xd200 7 0 5 STRAP_DEVICE_ID_DEV0_F4 0 15 STRAP_MAJOR_REV_ID_DEV0_F4 16 19 STRAP_MINOR_REV_ID_DEV0_F4 20 23 STRAP_FUNC_EN_DEV0_F4 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4 29 29 STRAP_D1_SUPPORT_DEV0_F4 30 30 STRAP_D2_SUPPORT_DEV0_F4 31 31 regRCC_DEV0_EPF4_STRAP2 0 0xd202 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F4 7 7 STRAP_RESIZE_BAR_EN_DEV0_F4 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F4 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4 14 14 STRAP_AER_EN_DEV0_F4 16 16 STRAP_ACS_EN_DEV0_F4 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F4 20 20 STRAP_DPA_EN_DEV0_F4 21 21 STRAP_VC_EN_DEV0_F4 23 23 STRAP_MSI_MULTI_CAP_DEV0_F4 24 26 STRAP_PASID_EN_DEV0_F4 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4 31 31 regRCC_DEV0_EPF4_STRAP3 0 0xd203 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4 0 0 STRAP_PWR_EN_DEV0_F4 1 1 STRAP_SUBSYS_ID_DEV0_F4 2 17 STRAP_MSI_EN_DEV0_F4 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F4 19 19 STRAP_MSIX_EN_DEV0_F4 20 20 STRAP_PMC_DSI_DEV0_F4 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4 27 27 STRAP_CLK_PM_EN_DEV0_F4 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F4 30 30 regRCC_DEV0_EPF4_STRAP4 0 0xd204 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F4 20 20 STRAP_ATOMIC_EN_DEV0_F4 21 21 STRAP_FLR_EN_DEV0_F4 22 22 STRAP_PME_SUPPORT_DEV0_F4 23 27 STRAP_INTERRUPT_PIN_DEV0_F4 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F4 31 31 regRCC_DEV0_EPF4_STRAP5 0 0xd205 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F4 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F4 30 30 regRCC_DEV0_EPF4_STRAP6 0 0xd206 2 0 5 STRAP_APER0_EN_DEV0_F4 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F4 1 1 regRCC_DEV0_EPF4_STRAP7 0 0xd207 1 0 5 STRAP_MSIX_TABLE_SIZE_DEV0_F4 5 15 regRCC_DEV0_EPF4_STRAP13 0 0xd20d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F4 0 7 STRAP_CLASS_CODE_SUB_DEV0_F4 8 15 STRAP_CLASS_CODE_BASE_DEV0_F4 16 23 regRCC_DEV0_EPF4_STRAP14 0 0xd20e 1 0 5 STRAP_VENDOR_ID_DEV0_F4 0 15 regRCC_DEV0_EPF5_STRAP0 0 0xd280 7 0 5 STRAP_DEVICE_ID_DEV0_F5 0 15 STRAP_MAJOR_REV_ID_DEV0_F5 16 19 STRAP_MINOR_REV_ID_DEV0_F5 20 23 STRAP_FUNC_EN_DEV0_F5 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5 29 29 STRAP_D1_SUPPORT_DEV0_F5 30 30 STRAP_D2_SUPPORT_DEV0_F5 31 31 regRCC_DEV0_EPF5_STRAP2 0 0xd282 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F5 7 7 STRAP_RESIZE_BAR_EN_DEV0_F5 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F5 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5 14 14 STRAP_AER_EN_DEV0_F5 16 16 STRAP_ACS_EN_DEV0_F5 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F5 20 20 STRAP_DPA_EN_DEV0_F5 21 21 STRAP_VC_EN_DEV0_F5 23 23 STRAP_MSI_MULTI_CAP_DEV0_F5 24 26 STRAP_PASID_EN_DEV0_F5 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5 31 31 regRCC_DEV0_EPF5_STRAP3 0 0xd283 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5 0 0 STRAP_PWR_EN_DEV0_F5 1 1 STRAP_SUBSYS_ID_DEV0_F5 2 17 STRAP_MSI_EN_DEV0_F5 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F5 19 19 STRAP_MSIX_EN_DEV0_F5 20 20 STRAP_PMC_DSI_DEV0_F5 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5 27 27 STRAP_CLK_PM_EN_DEV0_F5 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F5 30 30 regRCC_DEV0_EPF5_STRAP4 0 0xd284 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F5 20 20 STRAP_ATOMIC_EN_DEV0_F5 21 21 STRAP_FLR_EN_DEV0_F5 22 22 STRAP_PME_SUPPORT_DEV0_F5 23 27 STRAP_INTERRUPT_PIN_DEV0_F5 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F5 31 31 regRCC_DEV0_EPF5_STRAP5 0 0xd285 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F5 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F5 30 30 regRCC_DEV0_EPF5_STRAP6 0 0xd286 2 0 5 STRAP_APER0_EN_DEV0_F5 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F5 1 1 regRCC_DEV0_EPF5_STRAP7 0 0xd287 0 0 5 regRCC_DEV0_EPF5_STRAP13 0 0xd28d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F5 0 7 STRAP_CLASS_CODE_SUB_DEV0_F5 8 15 STRAP_CLASS_CODE_BASE_DEV0_F5 16 23 regRCC_DEV0_EPF5_STRAP14 0 0xd28e 1 0 5 STRAP_VENDOR_ID_DEV0_F5 0 15 regRCC_DEV0_EPF6_STRAP0 0 0xd300 7 0 5 STRAP_DEVICE_ID_DEV0_F6 0 15 STRAP_MAJOR_REV_ID_DEV0_F6 16 19 STRAP_MINOR_REV_ID_DEV0_F6 20 23 STRAP_FUNC_EN_DEV0_F6 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6 29 29 STRAP_D1_SUPPORT_DEV0_F6 30 30 STRAP_D2_SUPPORT_DEV0_F6 31 31 regRCC_DEV0_EPF6_STRAP2 0 0xd302 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F6 7 7 STRAP_RESIZE_BAR_EN_DEV0_F6 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F6 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6 14 14 STRAP_AER_EN_DEV0_F6 16 16 STRAP_ACS_EN_DEV0_F6 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F6 20 20 STRAP_DPA_EN_DEV0_F6 21 21 STRAP_VC_EN_DEV0_F6 23 23 STRAP_MSI_MULTI_CAP_DEV0_F6 24 26 STRAP_PASID_EN_DEV0_F6 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6 31 31 regRCC_DEV0_EPF6_STRAP3 0 0xd303 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6 0 0 STRAP_PWR_EN_DEV0_F6 1 1 STRAP_SUBSYS_ID_DEV0_F6 2 17 STRAP_MSI_EN_DEV0_F6 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F6 19 19 STRAP_MSIX_EN_DEV0_F6 20 20 STRAP_PMC_DSI_DEV0_F6 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6 27 27 STRAP_CLK_PM_EN_DEV0_F6 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F6 30 30 regRCC_DEV0_EPF6_STRAP4 0 0xd304 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F6 20 20 STRAP_ATOMIC_EN_DEV0_F6 21 21 STRAP_FLR_EN_DEV0_F6 22 22 STRAP_PME_SUPPORT_DEV0_F6 23 27 STRAP_INTERRUPT_PIN_DEV0_F6 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F6 31 31 regRCC_DEV0_EPF6_STRAP5 0 0xd305 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F6 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F6 30 30 regRCC_DEV0_EPF6_STRAP6 0 0xd306 2 0 5 STRAP_APER0_EN_DEV0_F6 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F6 1 1 regRCC_DEV0_EPF6_STRAP7 0 0xd307 0 0 5 regRCC_DEV0_EPF6_STRAP13 0 0xd30d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F6 0 7 STRAP_CLASS_CODE_SUB_DEV0_F6 8 15 STRAP_CLASS_CODE_BASE_DEV0_F6 16 23 regRCC_DEV0_EPF6_STRAP14 0 0xd30e 1 0 5 STRAP_VENDOR_ID_DEV0_F6 0 15 regRCC_DEV0_EPF7_STRAP0 0 0xd380 7 0 5 STRAP_DEVICE_ID_DEV0_F7 0 15 STRAP_MAJOR_REV_ID_DEV0_F7 16 19 STRAP_MINOR_REV_ID_DEV0_F7 20 23 STRAP_FUNC_EN_DEV0_F7 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7 29 29 STRAP_D1_SUPPORT_DEV0_F7 30 30 STRAP_D2_SUPPORT_DEV0_F7 31 31 regRCC_DEV0_EPF7_STRAP2 0 0xd382 14 0 5 STRAP_NO_SOFT_RESET_DEV0_F7 7 7 STRAP_RESIZE_BAR_EN_DEV0_F7 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F7 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7 14 14 STRAP_AER_EN_DEV0_F7 16 16 STRAP_ACS_EN_DEV0_F7 17 17 STRAP_CPL_ABORT_ERR_EN_DEV0_F7 20 20 STRAP_DPA_EN_DEV0_F7 21 21 STRAP_VC_EN_DEV0_F7 23 23 STRAP_MSI_MULTI_CAP_DEV0_F7 24 26 STRAP_PASID_EN_DEV0_F7 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F7 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F7 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F7 31 31 regRCC_DEV0_EPF7_STRAP3 0 0xd383 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7 0 0 STRAP_PWR_EN_DEV0_F7 1 1 STRAP_SUBSYS_ID_DEV0_F7 2 17 STRAP_MSI_EN_DEV0_F7 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F7 19 19 STRAP_MSIX_EN_DEV0_F7 20 20 STRAP_PMC_DSI_DEV0_F7 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7 27 27 STRAP_CLK_PM_EN_DEV0_F7 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F7 30 30 regRCC_DEV0_EPF7_STRAP4 0 0xd384 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F7 20 20 STRAP_ATOMIC_EN_DEV0_F7 21 21 STRAP_FLR_EN_DEV0_F7 22 22 STRAP_PME_SUPPORT_DEV0_F7 23 27 STRAP_INTERRUPT_PIN_DEV0_F7 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F7 31 31 regRCC_DEV0_EPF7_STRAP5 0 0xd385 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F7 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F7 30 30 regRCC_DEV0_EPF7_STRAP6 0 0xd386 4 0 5 STRAP_APER0_EN_DEV0_F7 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F7 1 1 STRAP_APER1_EN_DEV0_F7 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV0_F7 9 9 regRCC_DEV0_EPF7_STRAP7 0 0xd387 0 0 5 regRCC_DEV0_EPF7_STRAP13 0 0xd38d 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F7 0 7 STRAP_CLASS_CODE_SUB_DEV0_F7 8 15 STRAP_CLASS_CODE_BASE_DEV0_F7 16 23 regRCC_DEV0_EPF7_STRAP14 0 0xd38e 1 0 5 STRAP_VENDOR_ID_DEV0_F7 0 15 regRCC_DEV1_EPF0_STRAP0 0 0xd400 7 0 5 STRAP_DEVICE_ID_DEV1_F0 0 15 STRAP_MAJOR_REV_ID_DEV1_F0 16 19 STRAP_MINOR_REV_ID_DEV1_F0 20 23 STRAP_FUNC_EN_DEV1_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0 29 29 STRAP_D1_SUPPORT_DEV1_F0 30 30 STRAP_D2_SUPPORT_DEV1_F0 31 31 regRCC_DEV1_EPF0_STRAP2 0 0xd402 15 0 5 STRAP_NO_SOFT_RESET_DEV1_F0 7 7 STRAP_RESIZE_BAR_EN_DEV1_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV1_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0 14 14 STRAP_ARI_EN_DEV1_F0 15 15 STRAP_AER_EN_DEV1_F0 16 16 STRAP_ACS_EN_DEV1_F0 17 17 STRAP_CPL_ABORT_ERR_EN_DEV1_F0 20 20 STRAP_DPA_EN_DEV1_F0 21 21 STRAP_VC_EN_DEV1_F0 23 23 STRAP_MSI_MULTI_CAP_DEV1_F0 24 26 STRAP_PASID_EN_DEV1_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0 31 31 regRCC_DEV1_EPF0_STRAP3 0 0xd403 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0 0 0 STRAP_PWR_EN_DEV1_F0 1 1 STRAP_SUBSYS_ID_DEV1_F0 2 17 STRAP_MSI_EN_DEV1_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV1_F0 19 19 STRAP_MSIX_EN_DEV1_F0 20 20 STRAP_PMC_DSI_DEV1_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0 27 27 STRAP_CLK_PM_EN_DEV1_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV1_F0 30 30 regRCC_DEV1_EPF0_STRAP4 0 0xd404 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV1_F0 20 20 STRAP_ATOMIC_EN_DEV1_F0 21 21 STRAP_FLR_EN_DEV1_F0 22 22 STRAP_PME_SUPPORT_DEV1_F0 23 27 STRAP_INTERRUPT_PIN_DEV1_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV1_F0 31 31 regRCC_DEV1_EPF0_STRAP5 0 0xd405 2 0 5 STRAP_SUBSYS_VEN_ID_DEV1_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F0 30 30 regRCC_DEV1_EPF0_STRAP6 0 0xd406 2 0 5 STRAP_APER0_EN_DEV1_F0 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F0 1 1 regRCC_DEV1_EPF0_STRAP7 0 0xd407 0 0 5 regRCC_DEV1_EPF0_STRAP13 0 0xd40d 3 0 5 STRAP_CLASS_CODE_PIF_DEV1_F0 0 7 STRAP_CLASS_CODE_SUB_DEV1_F0 8 15 STRAP_CLASS_CODE_BASE_DEV1_F0 16 23 regRCC_DEV1_EPF0_STRAP14 0 0xd40e 1 0 5 STRAP_VENDOR_ID_DEV1_F0 0 15 regRCC_DEV1_EPF1_STRAP0 0 0xd480 7 0 5 STRAP_DEVICE_ID_DEV1_F1 0 15 STRAP_MAJOR_REV_ID_DEV1_F1 16 19 STRAP_MINOR_REV_ID_DEV1_F1 20 23 STRAP_FUNC_EN_DEV1_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1 29 29 STRAP_D1_SUPPORT_DEV1_F1 30 30 STRAP_D2_SUPPORT_DEV1_F1 31 31 regRCC_DEV1_EPF1_STRAP2 0 0xd482 14 0 5 STRAP_NO_SOFT_RESET_DEV1_F1 7 7 STRAP_RESIZE_BAR_EN_DEV1_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV1_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1 14 14 STRAP_AER_EN_DEV1_F1 16 16 STRAP_ACS_EN_DEV1_F1 17 17 STRAP_CPL_ABORT_ERR_EN_DEV1_F1 20 20 STRAP_DPA_EN_DEV1_F1 21 21 STRAP_VC_EN_DEV1_F1 23 23 STRAP_MSI_MULTI_CAP_DEV1_F1 24 26 STRAP_PASID_EN_DEV1_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F1 31 31 regRCC_DEV1_EPF1_STRAP3 0 0xd483 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1 0 0 STRAP_PWR_EN_DEV1_F1 1 1 STRAP_SUBSYS_ID_DEV1_F1 2 17 STRAP_MSI_EN_DEV1_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV1_F1 19 19 STRAP_MSIX_EN_DEV1_F1 20 20 STRAP_PMC_DSI_DEV1_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1 27 27 STRAP_CLK_PM_EN_DEV1_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV1_F1 30 30 regRCC_DEV1_EPF1_STRAP4 0 0xd484 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV1_F1 20 20 STRAP_ATOMIC_EN_DEV1_F1 21 21 STRAP_FLR_EN_DEV1_F1 22 22 STRAP_PME_SUPPORT_DEV1_F1 23 27 STRAP_INTERRUPT_PIN_DEV1_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV1_F1 31 31 regRCC_DEV1_EPF1_STRAP5 0 0xd485 2 0 5 STRAP_SUBSYS_VEN_ID_DEV1_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F1 30 30 regRCC_DEV1_EPF1_STRAP6 0 0xd486 6 0 5 STRAP_APER0_EN_DEV1_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV1_F1 1 1 STRAP_APER1_EN_DEV1_F1 8 8 STRAP_APER1_PREFETCHABLE_EN_DEV1_F1 9 9 STRAP_APER2_EN_DEV1_F1 16 16 STRAP_APER2_PREFETCHABLE_EN_DEV1_F1 17 17 regRCC_DEV1_EPF1_STRAP7 0 0xd487 1 0 5 STRAP_MSIX_TABLE_SIZE_DEV1_F1 5 15 regRCC_DEV1_EPF1_STRAP13 0 0xd48d 3 0 5 STRAP_CLASS_CODE_PIF_DEV1_F1 0 7 STRAP_CLASS_CODE_SUB_DEV1_F1 8 15 STRAP_CLASS_CODE_BASE_DEV1_F1 16 23 regRCC_DEV1_EPF1_STRAP14 0 0xd48e 1 0 5 STRAP_VENDOR_ID_DEV1_F1 0 15 regRCC_DEV1_EPF2_STRAP0 0 0xd500 0 0 5 regRCC_DEV1_EPF2_STRAP2 0 0xd502 0 0 5 regRCC_DEV1_EPF2_STRAP3 0 0xd503 0 0 5 regRCC_DEV1_EPF2_STRAP4 0 0xd504 0 0 5 regRCC_DEV1_EPF2_STRAP5 0 0xd505 0 0 5 regRCC_DEV1_EPF2_STRAP6 0 0xd506 0 0 5 regRCC_DEV1_EPF2_STRAP13 0 0xd50d 0 0 5 regRCC_DEV1_EPF2_STRAP14 0 0xd50e 0 0 5 regRCC_DEV1_EPF3_STRAP0 0 0xd580 0 0 5 regRCC_DEV1_EPF3_STRAP2 0 0xd582 0 0 5 regRCC_DEV1_EPF3_STRAP3 0 0xd583 0 0 5 regRCC_DEV1_EPF3_STRAP4 0 0xd584 0 0 5 regRCC_DEV1_EPF3_STRAP5 0 0xd585 0 0 5 regRCC_DEV1_EPF3_STRAP6 0 0xd586 0 0 5 regRCC_DEV1_EPF3_STRAP13 0 0xd58d 0 0 5 regRCC_DEV1_EPF3_STRAP14 0 0xd58e 0 0 5 regRCC_DEV1_EPF4_STRAP0 0 0xd600 0 0 5 regRCC_DEV1_EPF4_STRAP2 0 0xd602 0 0 5 regRCC_DEV1_EPF4_STRAP3 0 0xd603 0 0 5 regRCC_DEV1_EPF4_STRAP4 0 0xd604 0 0 5 regRCC_DEV1_EPF4_STRAP5 0 0xd605 0 0 5 regRCC_DEV1_EPF4_STRAP6 0 0xd606 0 0 5 regRCC_DEV1_EPF4_STRAP13 0 0xd60d 0 0 5 regRCC_DEV1_EPF4_STRAP14 0 0xd60e 0 0 5 regRCC_DEV1_EPF5_STRAP0 0 0xd680 0 0 5 regRCC_DEV1_EPF5_STRAP2 0 0xd682 0 0 5 regRCC_DEV1_EPF5_STRAP3 0 0xd683 0 0 5 regRCC_DEV1_EPF5_STRAP4 0 0xd684 0 0 5 regRCC_DEV1_EPF5_STRAP5 0 0xd685 0 0 5 regRCC_DEV1_EPF5_STRAP6 0 0xd686 0 0 5 regRCC_DEV1_EPF5_STRAP13 0 0xd68d 0 0 5 regRCC_DEV1_EPF5_STRAP14 0 0xd68e 0 0 5 regRCC_DEV2_EPF0_STRAP0 0 0xd800 7 0 5 STRAP_DEVICE_ID_DEV2_F0 0 15 STRAP_MAJOR_REV_ID_DEV2_F0 16 19 STRAP_MINOR_REV_ID_DEV2_F0 20 23 STRAP_FUNC_EN_DEV2_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0 29 29 STRAP_D1_SUPPORT_DEV2_F0 30 30 STRAP_D2_SUPPORT_DEV2_F0 31 31 regRCC_DEV2_EPF0_STRAP2 0 0xd802 15 0 5 STRAP_NO_SOFT_RESET_DEV2_F0 7 7 STRAP_RESIZE_BAR_EN_DEV2_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV2_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0 14 14 STRAP_ARI_EN_DEV2_F0 15 15 STRAP_AER_EN_DEV2_F0 16 16 STRAP_ACS_EN_DEV2_F0 17 17 STRAP_CPL_ABORT_ERR_EN_DEV2_F0 20 20 STRAP_DPA_EN_DEV2_F0 21 21 STRAP_VC_EN_DEV2_F0 23 23 STRAP_MSI_MULTI_CAP_DEV2_F0 24 26 STRAP_PASID_EN_DEV2_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0 31 31 regRCC_DEV2_EPF0_STRAP3 0 0xd803 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0 0 0 STRAP_PWR_EN_DEV2_F0 1 1 STRAP_SUBSYS_ID_DEV2_F0 2 17 STRAP_MSI_EN_DEV2_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV2_F0 19 19 STRAP_MSIX_EN_DEV2_F0 20 20 STRAP_PMC_DSI_DEV2_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0 27 27 STRAP_CLK_PM_EN_DEV2_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV2_F0 30 30 regRCC_DEV2_EPF0_STRAP4 0 0xd804 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV2_F0 20 20 STRAP_ATOMIC_EN_DEV2_F0 21 21 STRAP_FLR_EN_DEV2_F0 22 22 STRAP_PME_SUPPORT_DEV2_F0 23 27 STRAP_INTERRUPT_PIN_DEV2_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV2_F0 31 31 regRCC_DEV2_EPF0_STRAP5 0 0xd805 2 0 5 STRAP_SUBSYS_VEN_ID_DEV2_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F0 30 30 regRCC_DEV2_EPF0_STRAP6 0 0xd806 2 0 5 STRAP_APER0_EN_DEV2_F0 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV2_F0 1 1 regRCC_DEV2_EPF0_STRAP7 0 0xd807 1 0 5 STRAP_MSIX_TABLE_SIZE_DEV2_F0 5 15 regRCC_DEV2_EPF0_STRAP13 0 0xd80d 3 0 5 STRAP_CLASS_CODE_PIF_DEV2_F0 0 7 STRAP_CLASS_CODE_SUB_DEV2_F0 8 15 STRAP_CLASS_CODE_BASE_DEV2_F0 16 23 regRCC_DEV2_EPF0_STRAP14 0 0xd80e 1 0 5 STRAP_VENDOR_ID_DEV2_F0 0 15 regRCC_DEV2_EPF1_STRAP0 0 0xd880 7 0 5 STRAP_DEVICE_ID_DEV2_F1 0 15 STRAP_MAJOR_REV_ID_DEV2_F1 16 19 STRAP_MINOR_REV_ID_DEV2_F1 20 23 STRAP_FUNC_EN_DEV2_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F1 29 29 STRAP_D1_SUPPORT_DEV2_F1 30 30 STRAP_D2_SUPPORT_DEV2_F1 31 31 regRCC_DEV2_EPF1_STRAP2 0 0xd882 14 0 5 STRAP_NO_SOFT_RESET_DEV2_F1 7 7 STRAP_RESIZE_BAR_EN_DEV2_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV2_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F1 14 14 STRAP_AER_EN_DEV2_F1 16 16 STRAP_ACS_EN_DEV2_F1 17 17 STRAP_CPL_ABORT_ERR_EN_DEV2_F1 20 20 STRAP_DPA_EN_DEV2_F1 21 21 STRAP_VC_EN_DEV2_F1 23 23 STRAP_MSI_MULTI_CAP_DEV2_F1 24 26 STRAP_PASID_EN_DEV2_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F1 31 31 regRCC_DEV2_EPF1_STRAP3 0 0xd883 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F1 0 0 STRAP_PWR_EN_DEV2_F1 1 1 STRAP_SUBSYS_ID_DEV2_F1 2 17 STRAP_MSI_EN_DEV2_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV2_F1 19 19 STRAP_MSIX_EN_DEV2_F1 20 20 STRAP_PMC_DSI_DEV2_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F1 27 27 STRAP_CLK_PM_EN_DEV2_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV2_F1 30 30 regRCC_DEV2_EPF1_STRAP4 0 0xd884 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV2_F1 20 20 STRAP_ATOMIC_EN_DEV2_F1 21 21 STRAP_FLR_EN_DEV2_F1 22 22 STRAP_PME_SUPPORT_DEV2_F1 23 27 STRAP_INTERRUPT_PIN_DEV2_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV2_F1 31 31 regRCC_DEV2_EPF1_STRAP5 0 0xd885 2 0 5 STRAP_SUBSYS_VEN_ID_DEV2_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F1 30 30 regRCC_DEV2_EPF1_STRAP6 0 0xd886 5 0 5 STRAP_APER0_EN_DEV2_F1 0 0 STRAP_APER1_EN_DEV2_F1 8 8 STRAP_APER2_EN_DEV2_F1 16 16 STRAP_APER3_EN_DEV2_F1 24 24 STRAP_APER3_PREFETCHABLE_EN_DEV2_F1 25 25 regRCC_DEV2_EPF1_STRAP13 0 0xd88d 3 0 5 STRAP_CLASS_CODE_PIF_DEV2_F1 0 7 STRAP_CLASS_CODE_SUB_DEV2_F1 8 15 STRAP_CLASS_CODE_BASE_DEV2_F1 16 23 regRCC_DEV2_EPF1_STRAP14 0 0xd88e 1 0 5 STRAP_VENDOR_ID_DEV2_F1 0 15 regRCC_DEV2_EPF2_STRAP0 0 0xd900 7 0 5 STRAP_DEVICE_ID_DEV2_F2 0 15 STRAP_MAJOR_REV_ID_DEV2_F2 16 19 STRAP_MINOR_REV_ID_DEV2_F2 20 23 STRAP_FUNC_EN_DEV2_F2 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F2 29 29 STRAP_D1_SUPPORT_DEV2_F2 30 30 STRAP_D2_SUPPORT_DEV2_F2 31 31 regRCC_DEV2_EPF2_STRAP2 0 0xd902 14 0 5 STRAP_NO_SOFT_RESET_DEV2_F2 7 7 STRAP_RESIZE_BAR_EN_DEV2_F2 8 8 STRAP_MAX_PASID_WIDTH_DEV2_F2 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F2 14 14 STRAP_AER_EN_DEV2_F2 16 16 STRAP_ACS_EN_DEV2_F2 17 17 STRAP_CPL_ABORT_ERR_EN_DEV2_F2 20 20 STRAP_DPA_EN_DEV2_F2 21 21 STRAP_VC_EN_DEV2_F2 23 23 STRAP_MSI_MULTI_CAP_DEV2_F2 24 26 STRAP_PASID_EN_DEV2_F2 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F2 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F2 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F2 31 31 regRCC_DEV2_EPF2_STRAP3 0 0xd903 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F2 0 0 STRAP_PWR_EN_DEV2_F2 1 1 STRAP_SUBSYS_ID_DEV2_F2 2 17 STRAP_MSI_EN_DEV2_F2 18 18 STRAP_MSI_CLR_PENDING_EN_DEV2_F2 19 19 STRAP_MSIX_EN_DEV2_F2 20 20 STRAP_PMC_DSI_DEV2_F2 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F2 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F2 27 27 STRAP_CLK_PM_EN_DEV2_F2 29 29 STRAP_TRUE_PM_STATUS_EN_DEV2_F2 30 30 regRCC_DEV2_EPF2_STRAP4 0 0xd904 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV2_F2 20 20 STRAP_ATOMIC_EN_DEV2_F2 21 21 STRAP_FLR_EN_DEV2_F2 22 22 STRAP_PME_SUPPORT_DEV2_F2 23 27 STRAP_INTERRUPT_PIN_DEV2_F2 28 30 STRAP_AUXPWR_SUPPORT_DEV2_F2 31 31 regRCC_DEV2_EPF2_STRAP5 0 0xd905 2 0 5 STRAP_SUBSYS_VEN_ID_DEV2_F2 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F2 30 30 regRCC_DEV2_EPF2_STRAP6 0 0xd906 3 0 5 STRAP_APER0_EN_DEV2_F2 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV2_F2 1 1 STRAP_APER1_EN_DEV2_F2 8 8 regRCC_DEV2_EPF2_STRAP13 0 0xd90d 3 0 5 STRAP_CLASS_CODE_PIF_DEV2_F2 0 7 STRAP_CLASS_CODE_SUB_DEV2_F2 8 15 STRAP_CLASS_CODE_BASE_DEV2_F2 16 23 regRCC_DEV2_EPF2_STRAP14 0 0xd90e 1 0 5 STRAP_VENDOR_ID_DEV2_F2 0 15 regRCC_DEV0_2_RCC_VDM_SUPPORT 0 0xc440 5 0 5 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV0_2_RCC_BUS_CNTL 0 0xc441 19 0 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0 0xc442 12 0 5 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0 0xc443 2 0 5 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0 0xc444 5 0 5 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0 0xc445 2 0 5 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0 0xc446 1 0 5 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV0_2_RCC_MH_ARB_CNTL 0 0xc447 2 0 5 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0 0xc448 9 0 5 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0 0xc449 4 0 5 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0 0xc44c 1 0 5 PCIE_SCRATCH 0 31 regRCC_EP_DEV0_2_EP_PCIE_CNTL 0 0xc44e 3 0 5 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0 0xc44f 6 0 5 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0 0xc450 6 0 5 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0 0xc451 1 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0 0xc452 1 0 5 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0 0xc453 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0 0xc454 10 0 5 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0 0xc455 1 0 5 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0 0xc456 1 0 5 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0 0xc457 4 0 5 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0xc458 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0 0xc458 2 0 5 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0xc458 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0xc459 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0xc459 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0xc459 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0xc459 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0xc45a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0xc45a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0xc45a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0 0xc45c 1 0 5 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0 0xc45d 1 0 5 PCIEP_RESERVED 0 31 regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0 0xc45f 5 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0 0xc460 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0 0xc461 12 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0 0xc462 8 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0 0xc463 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0 0xc468 1 0 5 PCIE_RESERVED 0 31 regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0 0xc469 1 0 5 PCIE_SCRATCH 0 31 regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0 0xc46b 3 0 5 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0 0xc46c 1 0 5 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0 0xc46d 1 0 5 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0 0xc46e 2 0 5 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0 0xc46f 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0 0xc470 3 0 5 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0 0xc471 2 0 5 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0 0xc472 1 0 5 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0 0xc475 4 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0 0xc476 5 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0 0xc477 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0 0xc478 2 0 5 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0 0xc479 1 0 5 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0 0xc47a 1 0 5 LTR_MSG_INFO_FROM_EP 0 31 regRCC_DEV1_RCC_VDM_SUPPORT 0 0xc4c0 5 0 5 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV1_RCC_BUS_CNTL 0 0xc4c1 19 0 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV1_RCC_FEATURES_CONTROL_MISC 0 0xc4c2 12 0 5 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV1_RCC_DEV0_LINK_CNTL 0 0xc4c3 2 0 5 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV1_RCC_CMN_LINK_CNTL 0 0xc4c4 5 0 5 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV1_RCC_EP_REQUESTERID_RESTORE 0 0xc4c5 2 0 5 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV1_RCC_LTR_LSWITCH_CNTL 0 0xc4c6 1 0 5 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV1_RCC_MH_ARB_CNTL 0 0xc4c7 2 0 5 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regRCC_DEV1_RCC_MARGIN_PARAM_CNTL0 0 0xc4c8 9 0 5 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV1_RCC_MARGIN_PARAM_CNTL1 0 0xc4c9 4 0 5 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_EP_DEV1_EP_PCIE_SCRATCH 0 0xc4cc 1 0 5 PCIE_SCRATCH 0 31 regRCC_EP_DEV1_EP_PCIE_CNTL 0 0xc4ce 3 0 5 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV1_EP_PCIE_INT_CNTL 0 0xc4cf 6 0 5 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV1_EP_PCIE_INT_STATUS 0 0xc4d0 6 0 5 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV1_EP_PCIE_RX_CNTL2 0 0xc4d1 1 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV1_EP_PCIE_BUS_CNTL 0 0xc4d2 1 0 5 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV1_EP_PCIE_CFG_CNTL 0 0xc4d3 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL 0 0xc4d4 10 0 5 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV1_EP_PCIE_STRAP_MISC 0 0xc4d5 1 0 5 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV1_EP_PCIE_STRAP_MISC2 0 0xc4d6 1 0 5 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP 0 0xc4d7 4 0 5 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0xc4d8 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL 0 0xc4d8 2 0 5 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0xc4d8 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0xc4d9 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0xc4d9 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0xc4d9 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0xc4d9 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0xc4da 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0xc4da 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0xc4da 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV1_EP_PCIE_PME_CONTROL 0 0xc4dc 1 0 5 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV1_EP_PCIEP_RESERVED 0 0xc4dd 1 0 5 PCIEP_RESERVED 0 31 regRCC_EP_DEV1_EP_PCIE_TX_CNTL 0 0xc4df 5 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID 0 0xc4e0 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV1_EP_PCIE_ERR_CNTL 0 0xc4e1 12 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV1_EP_PCIE_RX_CNTL 0 0xc4e2 8 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL 0 0xc4e3 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV1_DN_PCIE_RESERVED 0 0xc4e8 1 0 5 PCIE_RESERVED 0 31 regRCC_DWN_DEV1_DN_PCIE_SCRATCH 0 0xc4e9 1 0 5 PCIE_SCRATCH 0 31 regRCC_DWN_DEV1_DN_PCIE_CNTL 0 0xc4eb 3 0 5 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL 0 0xc4ec 1 0 5 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV1_DN_PCIE_RX_CNTL2 0 0xc4ed 1 0 5 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV1_DN_PCIE_BUS_CNTL 0 0xc4ee 2 0 5 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV1_DN_PCIE_CFG_CNTL 0 0xc4ef 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV1_DN_PCIE_STRAP_F0 0 0xc4f0 3 0 5 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC 0 0xc4f1 2 0 5 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV1_DN_PCIE_STRAP_MISC2 0 0xc4f2 1 0 5 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV1_PCIE_ERR_CNTL 0 0xc4f5 4 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV1_PCIE_RX_CNTL 0 0xc4f6 5 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL 0 0xc4f7 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV1_PCIE_LC_CNTL2 0 0xc4f8 2 0 5 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV1_PCIEP_STRAP_MISC 0 0xc4f9 1 0 5 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP 0 0xc4fa 1 0 5 LTR_MSG_INFO_FROM_EP 0 31 regRCC_DEV2_RCC_VDM_SUPPORT 0 0xc540 5 0 5 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV2_RCC_BUS_CNTL 0 0xc541 19 0 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV2_RCC_FEATURES_CONTROL_MISC 0 0xc542 12 0 5 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV2_RCC_DEV0_LINK_CNTL 0 0xc543 2 0 5 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV2_RCC_CMN_LINK_CNTL 0 0xc544 5 0 5 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV2_RCC_EP_REQUESTERID_RESTORE 0 0xc545 2 0 5 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV2_RCC_LTR_LSWITCH_CNTL 0 0xc546 1 0 5 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV2_RCC_MH_ARB_CNTL 0 0xc547 2 0 5 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regRCC_DEV2_RCC_MARGIN_PARAM_CNTL0 0 0xc548 9 0 5 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV2_RCC_MARGIN_PARAM_CNTL1 0 0xc549 4 0 5 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_EP_DEV2_EP_PCIE_SCRATCH 0 0xc54c 1 0 5 PCIE_SCRATCH 0 31 regRCC_EP_DEV2_EP_PCIE_CNTL 0 0xc54e 3 0 5 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV2_EP_PCIE_INT_CNTL 0 0xc54f 6 0 5 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV2_EP_PCIE_INT_STATUS 0 0xc550 6 0 5 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV2_EP_PCIE_RX_CNTL2 0 0xc551 1 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV2_EP_PCIE_BUS_CNTL 0 0xc552 1 0 5 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV2_EP_PCIE_CFG_CNTL 0 0xc553 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL 0 0xc554 10 0 5 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV2_EP_PCIE_STRAP_MISC 0 0xc555 1 0 5 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV2_EP_PCIE_STRAP_MISC2 0 0xc556 1 0 5 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV2_EP_PCIE_F0_DPA_CAP 0 0xc557 4 0 5 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0xc558 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL 0 0xc558 2 0 5 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0xc558 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0xc559 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0xc559 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0xc559 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0xc559 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0xc55a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0xc55a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0xc55a 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV2_EP_PCIE_PME_CONTROL 0 0xc55c 1 0 5 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV2_EP_PCIEP_RESERVED 0 0xc55d 1 0 5 PCIEP_RESERVED 0 31 regRCC_EP_DEV2_EP_PCIE_TX_CNTL 0 0xc55f 5 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID 0 0xc560 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV2_EP_PCIE_ERR_CNTL 0 0xc561 12 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV2_EP_PCIE_RX_CNTL 0 0xc562 8 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL 0 0xc563 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV2_DN_PCIE_RESERVED 0 0xc568 1 0 5 PCIE_RESERVED 0 31 regRCC_DWN_DEV2_DN_PCIE_SCRATCH 0 0xc569 1 0 5 PCIE_SCRATCH 0 31 regRCC_DWN_DEV2_DN_PCIE_CNTL 0 0xc56b 3 0 5 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL 0 0xc56c 1 0 5 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV2_DN_PCIE_RX_CNTL2 0 0xc56d 1 0 5 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV2_DN_PCIE_BUS_CNTL 0 0xc56e 2 0 5 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV2_DN_PCIE_CFG_CNTL 0 0xc56f 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV2_DN_PCIE_STRAP_F0 0 0xc570 3 0 5 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC 0 0xc571 2 0 5 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV2_DN_PCIE_STRAP_MISC2 0 0xc572 1 0 5 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV2_PCIE_ERR_CNTL 0 0xc575 4 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV2_PCIE_RX_CNTL 0 0xc576 5 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL 0 0xc577 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV2_PCIE_LC_CNTL2 0 0xc578 2 0 5 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV2_PCIEP_STRAP_MISC 0 0xc579 1 0 5 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP 0 0xc57a 1 0 5 LTR_MSG_INFO_FROM_EP 0 31 regNBIF_STRAP_BIOS_CNTL 0 0xcc81 1 0 5 NBIF_STRAP_BIOS_EN 0 0 regMISC_SCRATCH 0 0xe800 1 0 5 MISC_SCRATCH0 0 31 regINTR_LINE_POLARITY 0 0xe801 3 0 5 INTR_LINE_POLARITY_DEV0 0 7 INTR_LINE_POLARITY_DEV1 8 15 INTR_LINE_POLARITY_DEV2 16 23 regINTR_LINE_ENABLE 0 0xe802 3 0 5 INTR_LINE_ENABLE_DEV0 0 7 INTR_LINE_ENABLE_DEV1 8 15 INTR_LINE_ENABLE_DEV2 16 23 regOUTSTANDING_VC_ALLOC 0 0xe803 12 0 5 DMA_OUTSTANDING_VC0_ALLOC 0 1 DMA_OUTSTANDING_VC1_ALLOC 2 3 DMA_OUTSTANDING_VC2_ALLOC 4 5 DMA_OUTSTANDING_VC3_ALLOC 6 7 DMA_OUTSTANDING_VC4_ALLOC 8 9 DMA_OUTSTANDING_VC5_ALLOC 10 11 DMA_OUTSTANDING_VC6_ALLOC 12 13 DMA_OUTSTANDING_VC7_ALLOC 14 15 DMA_OUTSTANDING_THRD 16 19 HST_OUTSTANDING_VC0_ALLOC 24 25 HST_OUTSTANDING_VC1_ALLOC 26 27 HST_OUTSTANDING_THRD 28 31 regBIFC_MISC_CTRL0 0 0xe804 19 0 5 DMA_VC4_NON_DVM_STS 4 7 DMA_CHAIN_BREAK_IN_RCMODE 8 8 HST_ARB_CHAIN_LOCK 9 9 GSI_SST_ARB_CHAIN_LOCK 10 10 GSI_RD_SPLIT_STALL_FLUSH_EN 11 11 GSI_RD_SPLIT_STALL_NPWR_DIS 12 12 GSI_SET_PRECEEDINGWR_DIS 13 13 DMA_ATOMIC_LENGTH_CHK_DIS 16 16 DMA_ATOMIC_FAILED_STS_SEL 17 17 DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW 18 18 DMA_ADDR_KEEP_PH 19 19 RCC_GMI_TD_FORCE_ZERO 20 20 VC5_DMA_IOCFG_DIS 23 23 PCIE_CAPABILITY_PROT_DIS 24 24 VC7_DMA_IOCFG_DIS 25 25 DMA_2ND_REQ_DIS 26 26 PORT_DSTATE_BYPASS_MODE 27 27 PME_TURNOFF_MODE 28 28 PCIESWUS_SELECTION 31 31 regBIFC_MISC_CTRL1 0 0xe805 27 0 5 THT_HST_CPLD_POISON_REPORT 0 0 DMA_REQ_POISON_REPORT 1 1 DMA_REQ_ACSVIO_REPORT 2 2 DMA_RSP_POISON_CPLD_REPORT 3 3 GSI_SMN_WORST_ERR_STSTUS 4 4 GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR 5 5 GSI_RDWR_BALANCE_DIS 6 6 GMI_ATOMIC_POISON_DROP 7 7 HST_UNSUPPORT_SDPCMD_STS 8 9 HST_UNSUPPORT_SDPCMD_DATASTS 10 11 DROP_OTHER_HT_ADDR_REQ 12 12 DMAWRREQ_HSTRDRSP_ORDER_FORCE 13 13 DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE 14 14 UPS_SDP_RDY_TIE1 15 15 GMI_RCC_DN_BME_DROP_DIS 16 16 GMI_RCC_EP_BME_DROP_DIS 17 17 GMI_BIH_DN_BME_DROP_DIS 18 18 GMI_BIH_EP_BME_DROP_DIS 19 19 GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR 20 20 GMI_ATOMIC_POISON_FOR_AERLOG 23 23 GMI_RDSIZED_REQATTR_MASK 24 24 GMI_RDSIZEDDW_REQATTR_MASK 25 25 GMI_WRSIZED_REQATTR_MASK 26 26 GMI_WRSIZEDFL_REQATTR_MASK 27 27 GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT 28 28 GMI_CPLBUF_EN 29 29 GMI_MSG_BLOCKLVL_SEL 30 31 regBIFC_BME_ERR_LOG 0 0xe806 26 0 5 DMA_ON_BME_LOW_DEV0_F0 0 0 DMA_ON_BME_LOW_DEV0_F1 1 1 DMA_ON_BME_LOW_DEV0_F2 2 2 DMA_ON_BME_LOW_DEV0_F3 3 3 DMA_ON_BME_LOW_DEV0_F4 4 4 DMA_ON_BME_LOW_DEV0_F5 5 5 DMA_ON_BME_LOW_DEV0_F6 6 6 DMA_ON_BME_LOW_DEV0_F7 7 7 DMA_ON_BME_LOW_DEV1_F0 8 8 DMA_ON_BME_LOW_DEV1_F1 9 9 DMA_ON_BME_LOW_DEV2_F0 12 12 DMA_ON_BME_LOW_DEV2_F1 13 13 DMA_ON_BME_LOW_DEV2_F2 14 14 CLEAR_DMA_ON_BME_LOW_DEV0_F0 16 16 CLEAR_DMA_ON_BME_LOW_DEV0_F1 17 17 CLEAR_DMA_ON_BME_LOW_DEV0_F2 18 18 CLEAR_DMA_ON_BME_LOW_DEV0_F3 19 19 CLEAR_DMA_ON_BME_LOW_DEV0_F4 20 20 CLEAR_DMA_ON_BME_LOW_DEV0_F5 21 21 CLEAR_DMA_ON_BME_LOW_DEV0_F6 22 22 CLEAR_DMA_ON_BME_LOW_DEV0_F7 23 23 CLEAR_DMA_ON_BME_LOW_DEV1_F0 24 24 CLEAR_DMA_ON_BME_LOW_DEV1_F1 25 25 CLEAR_DMA_ON_BME_LOW_DEV2_F0 28 28 CLEAR_DMA_ON_BME_LOW_DEV2_F1 29 29 CLEAR_DMA_ON_BME_LOW_DEV2_F2 30 30 regBIFC_LC_TIMER_CTRL 0 0xe807 2 0 5 ASPM_IDLE_TIMER_SCALE 0 15 L1_EXIT_TIMER_SCALE 16 31 regBIFC_RCCBIH_BME_ERR_LOG0 0 0xe808 20 0 5 RCCBIH_ON_BME_LOW_DEV0_F0 0 0 RCCBIH_ON_BME_LOW_DEV0_F1 1 1 RCCBIH_ON_BME_LOW_DEV0_F2 2 2 RCCBIH_ON_BME_LOW_DEV0_F3 3 3 RCCBIH_ON_BME_LOW_DEV0_F4 4 4 RCCBIH_ON_BME_LOW_DEV0_F5 5 5 RCCBIH_ON_BME_LOW_DEV0_F6 6 6 RCCBIH_ON_BME_LOW_DEV0_F7 7 7 RCCBIH_ON_BME_LOW_DEV1_F0 8 8 RCCBIH_ON_BME_LOW_DEV1_F1 9 9 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0 16 16 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1 17 17 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2 18 18 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3 19 19 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4 20 20 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5 21 21 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6 22 22 CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7 23 23 CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0 24 24 CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1 25 25 regBIFC_RCCBIH_BME_ERR_LOG1 0 0xe809 6 0 5 RCCBIH_ON_BME_LOW_DEV2_F0 0 0 RCCBIH_ON_BME_LOW_DEV2_F1 1 1 RCCBIH_ON_BME_LOW_DEV2_F2 2 2 CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0 16 16 CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1 17 17 CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2 18 18 regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0 0xe80a 16 0 5 TX_IDO_OVERIDE_P_DEV0_F0 0 1 TX_IDO_OVERIDE_NP_DEV0_F0 2 3 BLKLVL_FOR_IDO_DEV0_F0 4 5 TX_RO_OVERIDE_P_DEV0_F0 6 7 TX_RO_OVERIDE_NP_DEV0_F0 8 9 TX_SNR_OVERIDE_P_DEV0_F0 10 11 TX_SNR_OVERIDE_NP_DEV0_F0 12 13 BLKLVL_FOR_NONIDO_DEV0_F0 14 15 TX_IDO_OVERIDE_P_DEV0_F1 16 17 TX_IDO_OVERIDE_NP_DEV0_F1 18 19 BLKLVL_FOR_IDO_DEV0_F1 20 21 TX_RO_OVERIDE_P_DEV0_F1 22 23 TX_RO_OVERIDE_NP_DEV0_F1 24 25 TX_SNR_OVERIDE_P_DEV0_F1 26 27 TX_SNR_OVERIDE_NP_DEV0_F1 28 29 BLKLVL_FOR_NONIDO_DEV0_F1 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0 0xe80b 16 0 5 TX_IDO_OVERIDE_P_DEV0_F2 0 1 TX_IDO_OVERIDE_NP_DEV0_F2 2 3 BLKLVL_FOR_IDO_DEV0_F2 4 5 TX_RO_OVERIDE_P_DEV0_F2 6 7 TX_RO_OVERIDE_NP_DEV0_F2 8 9 TX_SNR_OVERIDE_P_DEV0_F2 10 11 TX_SNR_OVERIDE_NP_DEV0_F2 12 13 BLKLVL_FOR_NONIDO_DEV0_F2 14 15 TX_IDO_OVERIDE_P_DEV0_F3 16 17 TX_IDO_OVERIDE_NP_DEV0_F3 18 19 BLKLVL_FOR_IDO_DEV0_F3 20 21 TX_RO_OVERIDE_P_DEV0_F3 22 23 TX_RO_OVERIDE_NP_DEV0_F3 24 25 TX_SNR_OVERIDE_P_DEV0_F3 26 27 TX_SNR_OVERIDE_NP_DEV0_F3 28 29 BLKLVL_FOR_NONIDO_DEV0_F3 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0 0xe80c 16 0 5 TX_IDO_OVERIDE_P_DEV0_F4 0 1 TX_IDO_OVERIDE_NP_DEV0_F4 2 3 BLKLVL_FOR_IDO_DEV0_F4 4 5 TX_RO_OVERIDE_P_DEV0_F4 6 7 TX_RO_OVERIDE_NP_DEV0_F4 8 9 TX_SNR_OVERIDE_P_DEV0_F4 10 11 TX_SNR_OVERIDE_NP_DEV0_F4 12 13 BLKLVL_FOR_NONIDO_DEV0_F4 14 15 TX_IDO_OVERIDE_P_DEV0_F5 16 17 TX_IDO_OVERIDE_NP_DEV0_F5 18 19 BLKLVL_FOR_IDO_DEV0_F5 20 21 TX_RO_OVERIDE_P_DEV0_F5 22 23 TX_RO_OVERIDE_NP_DEV0_F5 24 25 TX_SNR_OVERIDE_P_DEV0_F5 26 27 TX_SNR_OVERIDE_NP_DEV0_F5 28 29 BLKLVL_FOR_NONIDO_DEV0_F5 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0 0xe80d 16 0 5 TX_IDO_OVERIDE_P_DEV0_F6 0 1 TX_IDO_OVERIDE_NP_DEV0_F6 2 3 BLKLVL_FOR_IDO_DEV0_F6 4 5 TX_RO_OVERIDE_P_DEV0_F6 6 7 TX_RO_OVERIDE_NP_DEV0_F6 8 9 TX_SNR_OVERIDE_P_DEV0_F6 10 11 TX_SNR_OVERIDE_NP_DEV0_F6 12 13 BLKLVL_FOR_NONIDO_DEV0_F6 14 15 TX_IDO_OVERIDE_P_DEV0_F7 16 17 TX_IDO_OVERIDE_NP_DEV0_F7 18 19 BLKLVL_FOR_IDO_DEV0_F7 20 21 TX_RO_OVERIDE_P_DEV0_F7 22 23 TX_RO_OVERIDE_NP_DEV0_F7 24 25 TX_SNR_OVERIDE_P_DEV0_F7 26 27 TX_SNR_OVERIDE_NP_DEV0_F7 28 29 BLKLVL_FOR_NONIDO_DEV0_F7 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1 0 0xe80e 16 0 5 TX_IDO_OVERIDE_P_DEV1_F0 0 1 TX_IDO_OVERIDE_NP_DEV1_F0 2 3 BLKLVL_FOR_IDO_DEV1_F0 4 5 TX_RO_OVERIDE_P_DEV1_F0 6 7 TX_RO_OVERIDE_NP_DEV1_F0 8 9 TX_SNR_OVERIDE_P_DEV1_F0 10 11 TX_SNR_OVERIDE_NP_DEV1_F0 12 13 BLKLVL_FOR_NONIDO_DEV1_F0 14 15 TX_IDO_OVERIDE_P_DEV1_F1 16 17 TX_IDO_OVERIDE_NP_DEV1_F1 18 19 BLKLVL_FOR_IDO_DEV1_F1 20 21 TX_RO_OVERIDE_P_DEV1_F1 22 23 TX_RO_OVERIDE_NP_DEV1_F1 24 25 TX_SNR_OVERIDE_P_DEV1_F1 26 27 TX_SNR_OVERIDE_NP_DEV1_F1 28 29 BLKLVL_FOR_NONIDO_DEV1_F1 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3 0 0xe80f 16 0 5 TX_IDO_OVERIDE_P_DEV1_F2 0 1 TX_IDO_OVERIDE_NP_DEV1_F2 2 3 BLKLVL_FOR_IDO_DEV1_F2 4 5 TX_RO_OVERIDE_P_DEV1_F2 6 7 TX_RO_OVERIDE_NP_DEV1_F2 8 9 TX_SNR_OVERIDE_P_DEV1_F2 10 11 TX_SNR_OVERIDE_NP_DEV1_F2 12 13 BLKLVL_FOR_NONIDO_DEV1_F2 14 15 TX_IDO_OVERIDE_P_DEV1_F3 16 17 TX_IDO_OVERIDE_NP_DEV1_F3 18 19 BLKLVL_FOR_IDO_DEV1_F3 20 21 TX_RO_OVERIDE_P_DEV1_F3 22 23 TX_RO_OVERIDE_NP_DEV1_F3 24 25 TX_SNR_OVERIDE_P_DEV1_F3 26 27 TX_SNR_OVERIDE_NP_DEV1_F3 28 29 BLKLVL_FOR_NONIDO_DEV1_F3 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5 0 0xe810 16 0 5 TX_IDO_OVERIDE_P_DEV1_F4 0 1 TX_IDO_OVERIDE_NP_DEV1_F4 2 3 BLKLVL_FOR_IDO_DEV1_F4 4 5 TX_RO_OVERIDE_P_DEV1_F4 6 7 TX_RO_OVERIDE_NP_DEV1_F4 8 9 TX_SNR_OVERIDE_P_DEV1_F4 10 11 TX_SNR_OVERIDE_NP_DEV1_F4 12 13 BLKLVL_FOR_NONIDO_DEV1_F4 14 15 TX_IDO_OVERIDE_P_DEV1_F5 16 17 TX_IDO_OVERIDE_NP_DEV1_F5 18 19 BLKLVL_FOR_IDO_DEV1_F5 20 21 TX_RO_OVERIDE_P_DEV1_F5 22 23 TX_RO_OVERIDE_NP_DEV1_F5 24 25 TX_SNR_OVERIDE_P_DEV1_F5 26 27 TX_SNR_OVERIDE_NP_DEV1_F5 28 29 BLKLVL_FOR_NONIDO_DEV1_F5 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7 0 0xe811 16 0 5 TX_IDO_OVERIDE_P_DEV1_F6 0 1 TX_IDO_OVERIDE_NP_DEV1_F6 2 3 BLKLVL_FOR_IDO_DEV1_F6 4 5 TX_RO_OVERIDE_P_DEV1_F6 6 7 TX_RO_OVERIDE_NP_DEV1_F6 8 9 TX_SNR_OVERIDE_P_DEV1_F6 10 11 TX_SNR_OVERIDE_NP_DEV1_F6 12 13 BLKLVL_FOR_NONIDO_DEV1_F6 14 15 TX_IDO_OVERIDE_P_DEV1_F7 16 17 TX_IDO_OVERIDE_NP_DEV1_F7 18 19 BLKLVL_FOR_IDO_DEV1_F7 20 21 TX_RO_OVERIDE_P_DEV1_F7 22 23 TX_RO_OVERIDE_NP_DEV1_F7 24 25 TX_SNR_OVERIDE_P_DEV1_F7 26 27 TX_SNR_OVERIDE_NP_DEV1_F7 28 29 BLKLVL_FOR_NONIDO_DEV1_F7 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1 0 0xe812 16 0 5 TX_IDO_OVERIDE_P_DEV2_F0 0 1 TX_IDO_OVERIDE_NP_DEV2_F0 2 3 BLKLVL_FOR_IDO_DEV2_F0 4 5 TX_RO_OVERIDE_P_DEV2_F0 6 7 TX_RO_OVERIDE_NP_DEV2_F0 8 9 TX_SNR_OVERIDE_P_DEV2_F0 10 11 TX_SNR_OVERIDE_NP_DEV2_F0 12 13 BLKLVL_FOR_NONIDO_DEV2_F0 14 15 TX_IDO_OVERIDE_P_DEV2_F1 16 17 TX_IDO_OVERIDE_NP_DEV2_F1 18 19 BLKLVL_FOR_IDO_DEV2_F1 20 21 TX_RO_OVERIDE_P_DEV2_F1 22 23 TX_RO_OVERIDE_NP_DEV2_F1 24 25 TX_SNR_OVERIDE_P_DEV2_F1 26 27 TX_SNR_OVERIDE_NP_DEV2_F1 28 29 BLKLVL_FOR_NONIDO_DEV2_F1 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3 0 0xe813 16 0 5 TX_IDO_OVERIDE_P_DEV2_F2 0 1 TX_IDO_OVERIDE_NP_DEV2_F2 2 3 BLKLVL_FOR_IDO_DEV2_F2 4 5 TX_RO_OVERIDE_P_DEV2_F2 6 7 TX_RO_OVERIDE_NP_DEV2_F2 8 9 TX_SNR_OVERIDE_P_DEV2_F2 10 11 TX_SNR_OVERIDE_NP_DEV2_F2 12 13 BLKLVL_FOR_NONIDO_DEV2_F2 14 15 TX_IDO_OVERIDE_P_DEV2_F3 16 17 TX_IDO_OVERIDE_NP_DEV2_F3 18 19 BLKLVL_FOR_IDO_DEV2_F3 20 21 TX_RO_OVERIDE_P_DEV2_F3 22 23 TX_RO_OVERIDE_NP_DEV2_F3 24 25 TX_SNR_OVERIDE_P_DEV2_F3 26 27 TX_SNR_OVERIDE_NP_DEV2_F3 28 29 BLKLVL_FOR_NONIDO_DEV2_F3 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5 0 0xe814 16 0 5 TX_IDO_OVERIDE_P_DEV2_F4 0 1 TX_IDO_OVERIDE_NP_DEV2_F4 2 3 BLKLVL_FOR_IDO_DEV2_F4 4 5 TX_RO_OVERIDE_P_DEV2_F4 6 7 TX_RO_OVERIDE_NP_DEV2_F4 8 9 TX_SNR_OVERIDE_P_DEV2_F4 10 11 TX_SNR_OVERIDE_NP_DEV2_F4 12 13 BLKLVL_FOR_NONIDO_DEV2_F4 14 15 TX_IDO_OVERIDE_P_DEV2_F5 16 17 TX_IDO_OVERIDE_NP_DEV2_F5 18 19 BLKLVL_FOR_IDO_DEV2_F5 20 21 TX_RO_OVERIDE_P_DEV2_F5 22 23 TX_RO_OVERIDE_NP_DEV2_F5 24 25 TX_SNR_OVERIDE_P_DEV2_F5 26 27 TX_SNR_OVERIDE_NP_DEV2_F5 28 29 BLKLVL_FOR_NONIDO_DEV2_F5 30 31 regBIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7 0 0xe815 16 0 5 TX_IDO_OVERIDE_P_DEV2_F6 0 1 TX_IDO_OVERIDE_NP_DEV2_F6 2 3 BLKLVL_FOR_IDO_DEV2_F6 4 5 TX_RO_OVERIDE_P_DEV2_F6 6 7 TX_RO_OVERIDE_NP_DEV2_F6 8 9 TX_SNR_OVERIDE_P_DEV2_F6 10 11 TX_SNR_OVERIDE_NP_DEV2_F6 12 13 BLKLVL_FOR_NONIDO_DEV2_F6 14 15 TX_IDO_OVERIDE_P_DEV2_F7 16 17 TX_IDO_OVERIDE_NP_DEV2_F7 18 19 BLKLVL_FOR_IDO_DEV2_F7 20 21 TX_RO_OVERIDE_P_DEV2_F7 22 23 TX_RO_OVERIDE_NP_DEV2_F7 24 25 TX_SNR_OVERIDE_P_DEV2_F7 26 27 TX_SNR_OVERIDE_NP_DEV2_F7 28 29 BLKLVL_FOR_NONIDO_DEV2_F7 30 31 regBIFC_DMA_ATTR_CNTL2_DEV0 0 0xe81a 8 0 5 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0 0 0 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1 4 4 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2 8 8 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3 12 12 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4 16 16 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5 20 20 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6 24 24 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7 28 28 regBIFC_DMA_ATTR_CNTL2_DEV1 0 0xe81b 8 0 5 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0 0 0 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1 4 4 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2 8 8 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3 12 12 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4 16 16 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5 20 20 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6 24 24 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7 28 28 regBIFC_DMA_ATTR_CNTL2_DEV2 0 0xe81c 8 0 5 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0 0 0 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1 4 4 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2 8 8 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3 12 12 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4 16 16 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5 20 20 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6 24 24 BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7 28 28 regBME_DUMMY_CNTL_0 0 0xe825 16 0 5 BME_DUMMY_RSPSTS_DEV0_F0 0 1 BME_DUMMY_RSPSTS_DEV0_F1 2 3 BME_DUMMY_RSPSTS_DEV0_F2 4 5 BME_DUMMY_RSPSTS_DEV0_F3 6 7 BME_DUMMY_RSPSTS_DEV0_F4 8 9 BME_DUMMY_RSPSTS_DEV0_F5 10 11 BME_DUMMY_RSPSTS_DEV0_F6 12 13 BME_DUMMY_RSPSTS_DEV0_F7 14 15 BME_DUMMY_RSPSTS_DEV1_F0 16 17 BME_DUMMY_RSPSTS_DEV1_F1 18 19 BME_DUMMY_RSPSTS_DEV1_F2 20 21 BME_DUMMY_RSPSTS_DEV1_F3 22 23 BME_DUMMY_RSPSTS_DEV1_F4 24 25 BME_DUMMY_RSPSTS_DEV1_F5 26 27 BME_DUMMY_RSPSTS_DEV1_F6 28 29 BME_DUMMY_RSPSTS_DEV1_F7 30 31 regBME_DUMMY_CNTL_1 0 0xe826 8 0 5 BME_DUMMY_RSPSTS_DEV2_F0 0 1 BME_DUMMY_RSPSTS_DEV2_F1 2 3 BME_DUMMY_RSPSTS_DEV2_F2 4 5 BME_DUMMY_RSPSTS_DEV2_F3 6 7 BME_DUMMY_RSPSTS_DEV2_F4 8 9 BME_DUMMY_RSPSTS_DEV2_F5 10 11 BME_DUMMY_RSPSTS_DEV2_F6 12 13 BME_DUMMY_RSPSTS_DEV2_F7 14 15 regBIFC_HSTARB_CNTL 0 0xe828 2 0 5 SLVARB_MODE 0 1 CFG_BLOCK_P_EN 8 8 regBIFC_GSI_CNTL 0 0xe829 18 0 5 GSI_SDP_RSP_ARB_MODE 0 1 GSI_CPL_RSP_ARB_MODE 2 4 GSI_CPL_INTERLEAVING_EN 5 5 GSI_CPL_PCR_EP_CAUSE_UR_EN 6 6 GSI_CPL_SMN_P_EP_CAUSE_UR_EN 7 7 GSI_CPL_SMN_NP_EP_CAUSE_UR_EN 8 8 GSI_CPL_SST_EP_CAUSE_UR_EN 9 9 GSI_SDP_REQ_ARB_MODE 10 11 GSI_SMN_REQ_ARB_MODE 12 13 GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN 14 14 GSI_SMN_PARITY_CHK_BE_MSK 15 15 GSI_SMN_BURST_EN 16 16 GSI_SMN_256B_SPLIT_64B_EN 17 17 SMN_PP_PIPE_ENABLE 27 27 HDP_FB_UPLIMIT_COUNT_FBFLUSH 28 28 HDP_FB_UPLIMIT_COUNT_HDPFLUSH 29 29 HDP_FB_UPLIMIT_COUNT_HDPRD 30 30 HDP_FB_UPLIMIT_COUNT_ALL 31 31 regBIFC_PCIEFUNC_CNTL 0 0xe82a 2 0 5 DMA_NON_PCIEFUNC_BUSDEVFUNC 0 15 MP1SYSHUBDATA_DRAM_IS_PCIEFUNC 16 16 regBIFC_PASID_CHECK_DIS 0 0xe82b 13 0 5 PASID_CHECK_DIS_DEV0_F0 0 0 PASID_CHECK_DIS_DEV0_F1 1 1 PASID_CHECK_DIS_DEV0_F2 2 2 PASID_CHECK_DIS_DEV0_F3 3 3 PASID_CHECK_DIS_DEV0_F4 4 4 PASID_CHECK_DIS_DEV0_F5 5 5 PASID_CHECK_DIS_DEV0_F6 6 6 PASID_CHECK_DIS_DEV0_F7 7 7 PASID_CHECK_DIS_DEV1_F0 8 8 PASID_CHECK_DIS_DEV1_F1 9 9 PASID_CHECK_DIS_DEV2_F0 16 16 PASID_CHECK_DIS_DEV2_F1 17 17 PASID_CHECK_DIS_DEV2_F2 18 18 regBIFC_SDP_CNTL_0 0 0xe82c 4 0 5 HRP_SDP_DISCON_HYSTERESIS 0 7 GSI_SDP_DISCON_HYSTERESIS 8 15 GMI_DNS_SDP_DISCON_HYSTERESIS 16 23 GMI_UPS_SDP_DISCON_HYSTERESIS 24 31 regBIFC_SDP_CNTL_1 0 0xe82d 9 0 5 HRP_SDP_DISCON_DIS 0 0 GSI_SDP_DISCON_DIS 1 1 GMI_DNS_SDP_DISCON_DIS 2 2 GMI_UPS_SDP_DISCON_DIS 3 3 HRP_SDP_DISCON_VLINK_NONL0_ONLY 4 4 NP_KEEP_GOING_STALL_P 5 5 GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY 7 7 ATOMIC_STALL_BY_RDWR_EN 8 8 NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN 30 30 regBIFC_PASID_STS 0 0xe82e 1 0 5 PASID_STS 0 3 regBIFC_ATHUB_ACT_CNTL 0 0xe82f 5 0 5 ATHUB_ACT_GSI_RSP_STS_TYPE 0 2 ATHUB_ACT_GSI_REQ_DROP_DIS 8 8 GSI_ATHUB_ACT_FLUSH_DIS 9 9 GMI_ATHUB_ACT_FLUSH_DIS 10 10 ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN 11 11 regBIFC_PERF_CNTL_0 0 0xe830 6 0 5 PERF_CNT_MMIO_RD_EN 0 0 PERF_CNT_MMIO_WR_EN 1 1 PERF_CNT_MMIO_RD_RESET 8 8 PERF_CNT_MMIO_WR_RESET 9 9 PERF_CNT_MMIO_RD_SEL 16 22 PERF_CNT_MMIO_WR_SEL 24 30 regBIFC_PERF_CNTL_1 0 0xe831 6 0 5 PERF_CNT_DMA_RD_EN 0 0 PERF_CNT_DMA_WR_EN 1 1 PERF_CNT_DMA_RD_RESET 8 8 PERF_CNT_DMA_WR_RESET 9 9 PERF_CNT_DMA_RD_SEL 16 22 PERF_CNT_DMA_WR_SEL 24 31 regBIFC_PERF_CNT_MMIO_RD 0 0xe832 1 0 5 PERF_CNT_MMIO_RD_VALUE 0 31 regBIFC_PERF_CNT_MMIO_WR 0 0xe833 1 0 5 PERF_CNT_MMIO_WR_VALUE 0 31 regBIFC_PERF_CNT_DMA_RD 0 0xe834 1 0 5 PERF_CNT_DMA_RD_VALUE 0 31 regBIFC_PERF_CNT_DMA_WR 0 0xe835 1 0 5 PERF_CNT_DMA_WR_VALUE 0 31 regNBIF_REGIF_ERRSET_CTRL 0 0xe836 1 0 5 DROP_NONPF_MMREGREQ_SETERR_DIS 0 0 regBIFC_SDP_CNTL_2 0 0xe837 4 0 5 SDP_SION_DISCON_HYSTERESIS 0 7 SDP_SION_DISCON_HYSTERESIS_H 8 11 HRP_SDP_DISCON_HYSTERESIS_H 16 19 GSI_SDP_DISCON_HYSTERESIS_H 24 27 regNBIF_PGMST_CTRL 0 0xe838 4 0 5 NBIF_CFG_PG_HYSTERESIS 0 7 NBIF_CFG_PG_EN 8 8 NBIF_CFG_IDLENESS_COUNT_EN 10 13 NBIF_CFG_FW_PG_EXIT_EN 14 15 regNBIF_PGSLV_CTRL 0 0xe839 2 0 5 NBIF_CFG_IDLE_HYSTERESIS 0 4 NBIF_CFG_PGSLV_EXTCLK_0_IDLE_HYSTERESIS 5 9 regNBIF_PG_MISC_CTRL 0 0xe83a 9 0 5 NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS 0 4 NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS 5 9 NBIF_PG_ENDP_D3_ONLY 10 10 NBIF_PG_CLK_PERM1 13 13 NBIF_PG_DS_ALLOW_DIS 14 14 NBIF_PG_CLK_PERM2 16 16 NBIF_CFG_REFCLK_CYCLE_FOR_200NS 24 29 NBIF_PG_PCIE_NBIF_LD_MASK 30 30 NBIF_CFG_PG_EXIT_OVERRIDE 31 31 regNBIF_HST_MISC_CTRL 0 0xe83b 0 0 5 regSMN_MST_EP_CNTL3 0 0xe83c 24 0 5 SMN_ZERO_BE_WR_EN_EP_DEV0_PF0 0 0 SMN_ZERO_BE_WR_EN_EP_DEV0_PF1 1 1 SMN_ZERO_BE_WR_EN_EP_DEV0_PF2 2 2 SMN_ZERO_BE_WR_EN_EP_DEV0_PF3 3 3 SMN_ZERO_BE_WR_EN_EP_DEV0_PF4 4 4 SMN_ZERO_BE_WR_EN_EP_DEV0_PF5 5 5 SMN_ZERO_BE_WR_EN_EP_DEV0_PF6 6 6 SMN_ZERO_BE_WR_EN_EP_DEV0_PF7 7 7 SMN_ZERO_BE_WR_EN_EP_DEV1_PF0 8 8 SMN_ZERO_BE_WR_EN_EP_DEV1_PF1 9 9 SMN_ZERO_BE_WR_EN_EP_DEV1_PF2 10 10 SMN_ZERO_BE_WR_EN_EP_DEV1_PF3 11 11 SMN_ZERO_BE_WR_EN_EP_DEV1_PF4 12 12 SMN_ZERO_BE_WR_EN_EP_DEV1_PF5 13 13 SMN_ZERO_BE_WR_EN_EP_DEV1_PF6 14 14 SMN_ZERO_BE_WR_EN_EP_DEV1_PF7 15 15 SMN_ZERO_BE_WR_EN_EP_DEV2_PF0 16 16 SMN_ZERO_BE_WR_EN_EP_DEV2_PF1 17 17 SMN_ZERO_BE_WR_EN_EP_DEV2_PF2 18 18 SMN_ZERO_BE_WR_EN_EP_DEV2_PF3 19 19 SMN_ZERO_BE_WR_EN_EP_DEV2_PF4 20 20 SMN_ZERO_BE_WR_EN_EP_DEV2_PF5 21 21 SMN_ZERO_BE_WR_EN_EP_DEV2_PF6 22 22 SMN_ZERO_BE_WR_EN_EP_DEV2_PF7 23 23 regSMN_MST_EP_CNTL4 0 0xe83d 24 0 5 SMN_ZERO_BE_RD_EN_EP_DEV0_PF0 0 0 SMN_ZERO_BE_RD_EN_EP_DEV0_PF1 1 1 SMN_ZERO_BE_RD_EN_EP_DEV0_PF2 2 2 SMN_ZERO_BE_RD_EN_EP_DEV0_PF3 3 3 SMN_ZERO_BE_RD_EN_EP_DEV0_PF4 4 4 SMN_ZERO_BE_RD_EN_EP_DEV0_PF5 5 5 SMN_ZERO_BE_RD_EN_EP_DEV0_PF6 6 6 SMN_ZERO_BE_RD_EN_EP_DEV0_PF7 7 7 SMN_ZERO_BE_RD_EN_EP_DEV1_PF0 8 8 SMN_ZERO_BE_RD_EN_EP_DEV1_PF1 9 9 SMN_ZERO_BE_RD_EN_EP_DEV1_PF2 10 10 SMN_ZERO_BE_RD_EN_EP_DEV1_PF3 11 11 SMN_ZERO_BE_RD_EN_EP_DEV1_PF4 12 12 SMN_ZERO_BE_RD_EN_EP_DEV1_PF5 13 13 SMN_ZERO_BE_RD_EN_EP_DEV1_PF6 14 14 SMN_ZERO_BE_RD_EN_EP_DEV1_PF7 15 15 SMN_ZERO_BE_RD_EN_EP_DEV2_PF0 16 16 SMN_ZERO_BE_RD_EN_EP_DEV2_PF1 17 17 SMN_ZERO_BE_RD_EN_EP_DEV2_PF2 18 18 SMN_ZERO_BE_RD_EN_EP_DEV2_PF3 19 19 SMN_ZERO_BE_RD_EN_EP_DEV2_PF4 20 20 SMN_ZERO_BE_RD_EN_EP_DEV2_PF5 21 21 SMN_ZERO_BE_RD_EN_EP_DEV2_PF6 22 22 SMN_ZERO_BE_RD_EN_EP_DEV2_PF7 23 23 regSMN_MST_CNTL1 0 0xe83e 4 0 5 SMN_ERRRSP_DATA_ALLF_DIS_UPS 0 0 SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0 16 16 SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1 17 17 SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2 18 18 regSMN_MST_EP_CNTL5 0 0xe83f 24 0 5 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0 0 0 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1 1 1 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2 2 2 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3 3 3 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4 4 4 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5 5 5 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6 6 6 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7 7 7 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0 8 8 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1 9 9 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2 10 10 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3 11 11 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4 12 12 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5 13 13 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6 14 14 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7 15 15 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0 16 16 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1 17 17 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2 18 18 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3 19 19 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4 20 20 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5 21 21 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6 22 22 SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7 23 23 regBIF_SELFRING_BUFFER_VID 0 0xe840 3 0 5 DOORBELL_MONITOR_CID 0 7 RAS_CNTLR_INTR_CID 8 15 RAS_ATHUB_ERR_EVENT_INTR_CID 16 23 regBIF_SELFRING_VECTOR_CNTL 0 0xe841 2 0 5 MISC_DB_MNTR_INTR_DIS 0 0 DB_MNTR_TS_FROM 1 1 regNBIF_STRAP_WRITE_CTRL 0 0xe845 1 0 5 NBIF_STRAP_WRITE_ONCE_ENABLE 0 0 regNBIF_INTX_DSTATE_MISC_CNTL 0 0xe846 8 0 5 DEASRT_INTX_DSTATE_CHK_DIS_EP 0 0 DEASRT_INTX_DSTATE_CHK_DIS_DN 1 1 DEASRT_INTX_DSTATE_CHK_DIS_SWUS 2 2 DEASRT_INTX_IN_NOND0_EN_EP 3 3 DEASRT_INTX_IN_NOND0_EN_DN 4 4 PMI_INT_DIS_EP 5 5 PMI_INT_DIS_DN 6 6 PMI_INT_DIS_SWUS 7 7 regNBIF_PENDING_MISC_CNTL 0 0xe847 2 0 5 FLR_MST_PEND_CHK_DIS 0 0 FLR_SLV_PEND_CHK_DIS 1 1 regBIF_GMI_WRR_WEIGHT 0 0xe848 3 0 5 GMI_REQ_WRR_LRG_COUNTER_MODE 29 29 GMI_REQ_WRR_LRG_MODE 30 30 GMI_REQ_WRR_LRG_SIZE_MODE 31 31 regBIF_GMI_WRR_WEIGHT2 0 0xe849 4 0 5 GMI_REQ_ENTRY0_WEIGHT 0 7 GMI_REQ_ENTRY1_WEIGHT 8 15 GMI_REQ_ENTRY2_WEIGHT 16 23 GMI_REQ_ENTRY3_WEIGHT 24 31 regBIF_GMI_WRR_WEIGHT3 0 0xe84a 4 0 5 GMI_REQ_ENTRY4_WEIGHT 0 7 GMI_REQ_ENTRY5_WEIGHT 8 15 GMI_REQ_ENTRY6_WEIGHT 16 23 GMI_REQ_ENTRY7_WEIGHT 24 31 regNBIF_PWRBRK_REQUEST 0 0xe84c 1 0 5 NBIF_PWRBRK_REQUEST 0 0 regBIF_ATOMIC_ERR_LOG_DEV0_F0 0 0xe850 8 0 5 UR_ATOMIC_OPCODE_DEV0_F0 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F0 1 1 UR_ATOMIC_LENGTH_DEV0_F0 2 2 UR_ATOMIC_NR_DEV0_F0 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F0 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F0 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F0 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F1 0 0xe851 8 0 5 UR_ATOMIC_OPCODE_DEV0_F1 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F1 1 1 UR_ATOMIC_LENGTH_DEV0_F1 2 2 UR_ATOMIC_NR_DEV0_F1 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F1 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F1 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F1 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F2 0 0xe852 8 0 5 UR_ATOMIC_OPCODE_DEV0_F2 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F2 1 1 UR_ATOMIC_LENGTH_DEV0_F2 2 2 UR_ATOMIC_NR_DEV0_F2 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F2 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F2 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F2 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F3 0 0xe853 8 0 5 UR_ATOMIC_OPCODE_DEV0_F3 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F3 1 1 UR_ATOMIC_LENGTH_DEV0_F3 2 2 UR_ATOMIC_NR_DEV0_F3 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F3 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F3 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F3 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F4 0 0xe854 8 0 5 UR_ATOMIC_OPCODE_DEV0_F4 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F4 1 1 UR_ATOMIC_LENGTH_DEV0_F4 2 2 UR_ATOMIC_NR_DEV0_F4 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F4 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F4 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F4 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F5 0 0xe855 8 0 5 UR_ATOMIC_OPCODE_DEV0_F5 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F5 1 1 UR_ATOMIC_LENGTH_DEV0_F5 2 2 UR_ATOMIC_NR_DEV0_F5 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F5 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F5 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F5 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F6 0 0xe856 8 0 5 UR_ATOMIC_OPCODE_DEV0_F6 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F6 1 1 UR_ATOMIC_LENGTH_DEV0_F6 2 2 UR_ATOMIC_NR_DEV0_F6 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F6 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F6 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F6 19 19 regBIF_ATOMIC_ERR_LOG_DEV0_F7 0 0xe857 8 0 5 UR_ATOMIC_OPCODE_DEV0_F7 0 0 UR_ATOMIC_REQEN_LOW_DEV0_F7 1 1 UR_ATOMIC_LENGTH_DEV0_F7 2 2 UR_ATOMIC_NR_DEV0_F7 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV0_F7 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV0_F7 18 18 CLEAR_UR_ATOMIC_NR_DEV0_F7 19 19 regBIF_ATOMIC_ERR_LOG_DEV1_F0 0 0xe858 8 0 5 UR_ATOMIC_OPCODE_DEV1_F0 0 0 UR_ATOMIC_REQEN_LOW_DEV1_F0 1 1 UR_ATOMIC_LENGTH_DEV1_F0 2 2 UR_ATOMIC_NR_DEV1_F0 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV1_F0 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F0 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV1_F0 18 18 CLEAR_UR_ATOMIC_NR_DEV1_F0 19 19 regBIF_ATOMIC_ERR_LOG_DEV1_F1 0 0xe859 8 0 5 UR_ATOMIC_OPCODE_DEV1_F1 0 0 UR_ATOMIC_REQEN_LOW_DEV1_F1 1 1 UR_ATOMIC_LENGTH_DEV1_F1 2 2 UR_ATOMIC_NR_DEV1_F1 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV1_F1 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F1 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV1_F1 18 18 CLEAR_UR_ATOMIC_NR_DEV1_F1 19 19 regBIF_ATOMIC_ERR_LOG_DEV2_F0 0 0xe85a 8 0 5 UR_ATOMIC_OPCODE_DEV2_F0 0 0 UR_ATOMIC_REQEN_LOW_DEV2_F0 1 1 UR_ATOMIC_LENGTH_DEV2_F0 2 2 UR_ATOMIC_NR_DEV2_F0 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV2_F0 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F0 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV2_F0 18 18 CLEAR_UR_ATOMIC_NR_DEV2_F0 19 19 regBIF_ATOMIC_ERR_LOG_DEV2_F1 0 0xe85b 8 0 5 UR_ATOMIC_OPCODE_DEV2_F1 0 0 UR_ATOMIC_REQEN_LOW_DEV2_F1 1 1 UR_ATOMIC_LENGTH_DEV2_F1 2 2 UR_ATOMIC_NR_DEV2_F1 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV2_F1 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F1 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV2_F1 18 18 CLEAR_UR_ATOMIC_NR_DEV2_F1 19 19 regBIF_ATOMIC_ERR_LOG_DEV2_F2 0 0xe85c 8 0 5 UR_ATOMIC_OPCODE_DEV2_F2 0 0 UR_ATOMIC_REQEN_LOW_DEV2_F2 1 1 UR_ATOMIC_LENGTH_DEV2_F2 2 2 UR_ATOMIC_NR_DEV2_F2 3 3 CLEAR_UR_ATOMIC_OPCODE_DEV2_F2 16 16 CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F2 17 17 CLEAR_UR_ATOMIC_LENGTH_DEV2_F2 18 18 CLEAR_UR_ATOMIC_NR_DEV2_F2 19 19 regBIF_DMA_MP4_ERR_LOG 0 0xe870 4 0 5 MP4SDP_VC4_NON_DVM_ERR 0 0 MP4SDP_ATOMIC_REQEN_LOW_ERR 1 1 CLEAR_MP4SDP_VC4_NON_DVM_ERR 16 16 CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR 17 17 regBIF_PASID_ERR_LOG 0 0xe871 13 0 5 PASID_ERR_DEV0_F0 0 0 PASID_ERR_DEV0_F1 1 1 PASID_ERR_DEV0_F2 2 2 PASID_ERR_DEV0_F3 3 3 PASID_ERR_DEV0_F4 4 4 PASID_ERR_DEV0_F5 5 5 PASID_ERR_DEV0_F6 6 6 PASID_ERR_DEV0_F7 7 7 PASID_ERR_DEV1_F0 8 8 PASID_ERR_DEV1_F1 9 9 PASID_ERR_DEV2_F0 16 16 PASID_ERR_DEV2_F1 17 17 PASID_ERR_DEV2_F2 18 18 regBIF_PASID_ERR_CLR 0 0xe872 13 0 5 PASID_ERR_CLR_DEV0_F0 0 0 PASID_ERR_CLR_DEV0_F1 1 1 PASID_ERR_CLR_DEV0_F2 2 2 PASID_ERR_CLR_DEV0_F3 3 3 PASID_ERR_CLR_DEV0_F4 4 4 PASID_ERR_CLR_DEV0_F5 5 5 PASID_ERR_CLR_DEV0_F6 6 6 PASID_ERR_CLR_DEV0_F7 7 7 PASID_ERR_CLR_DEV1_F0 8 8 PASID_ERR_CLR_DEV1_F1 9 9 PASID_ERR_CLR_DEV2_F0 16 16 PASID_ERR_CLR_DEV2_F1 17 17 PASID_ERR_CLR_DEV2_F2 18 18 regOBFF_EMU_CFG 0 0xe874 1 0 5 OBFF_EMU_INTR_EN 0 0 regEP0_INTR_URGENT_CAP 0 0xe875 8 0 5 EP0_F0_INTR_URGENT_MODE 0 1 EP0_F1_INTR_URGENT_MODE 2 3 EP0_F2_INTR_URGENT_MODE 4 5 EP0_F3_INTR_URGENT_MODE 6 7 EP0_F4_INTR_URGENT_MODE 8 9 EP0_F5_INTR_URGENT_MODE 10 11 EP0_F6_INTR_URGENT_MODE 12 13 EP0_F7_INTR_URGENT_MODE 14 15 regEP1_INTR_URGENT_CAP 0 0xe876 2 0 5 EP1_F0_INTR_URGENT_MODE 0 1 EP1_F1_INTR_URGENT_MODE 2 3 regEP2_INTR_URGENT_CAP 0 0xe877 3 0 5 EP2_F0_INTR_URGENT_MODE 0 1 EP2_F1_INTR_URGENT_MODE 2 3 EP2_F2_INTR_URGENT_MODE 4 5 regEP_PEND_BLOCK_MSK 0 0xe87c 13 0 5 EP0_F0_PEND_BLOCK_MSK 0 0 EP0_F1_PEND_BLOCK_MSK 1 1 EP0_F2_PEND_BLOCK_MSK 2 2 EP0_F3_PEND_BLOCK_MSK 3 3 EP0_F4_PEND_BLOCK_MSK 4 4 EP0_F5_PEND_BLOCK_MSK 5 5 EP0_F6_PEND_BLOCK_MSK 6 6 EP0_F7_PEND_BLOCK_MSK 7 7 EP1_F0_PEND_BLOCK_MSK 8 8 EP1_F1_PEND_BLOCK_MSK 9 9 EP2_F0_PEND_BLOCK_MSK 16 16 EP2_F1_PEND_BLOCK_MSK 17 17 EP2_F2_PEND_BLOCK_MSK 18 18 regNBIF_VWIRE_CTRL 0 0xe880 6 0 5 NBIF_SMN_VWR_DIS 0 0 SMN_VWR_RESET_DELAY_CNT 4 7 SMN_VWR_POSTED 8 8 NBIF_SDP_UPS_VWR_DIS 16 16 SDP_VWR_RESET_DELAY_CNT 20 23 SDP_VWR_BLOCKLVL 26 27 regNBIF_SMN_VWR_VCHG_DIS_CTRL 0 0xe881 27 0 5 SMN_VWR_VCHG_SET0_DIS 0 0 SMN_VWR_VCHG_SET1_DIS 1 1 SMN_VWR_VCHG_SET2_DIS 2 2 SMN_VWR_VCHG_SET3_DIS 3 3 SMN_VWR_VCHG_SET4_DIS 4 4 SMN_VWR_VCHG_SET5_DIS 5 5 SMN_VWR_VCHG_SET6_DIS 6 6 SMN_VWR_VCHG_SET7_DIS 7 7 SMN_VWR_VCHG_SET8_DIS 8 8 SMN_VWR_VCHG_SET9_DIS 9 9 SMN_VWR_VCHG_SET10_DIS 10 10 SMN_VWR_VCHG_SET11_DIS 11 11 SMN_VWR_VCHG_SET12_DIS 12 12 SMN_VWR_VCHG_SET13_DIS 13 13 SMN_VWR_VCHG_SET14_DIS 14 14 SMN_VWR_VCHG_SET15_DIS 15 15 SMN_VWR_VCHG_SET16_DIS 16 16 SMN_VWR_VCHG_SET17_DIS 17 17 SMN_VWR_VCHG_SET18_DIS 18 18 SMN_VWR_VCHG_SET19_DIS 19 19 SMN_VWR_VCHG_SET20_DIS 20 20 SMN_VWR_VCHG_SET21_DIS 21 21 SMN_VWR_VCHG_SET22_DIS 22 22 SMN_VWR_VCHG_SET23_DIS 23 23 SMN_VWR_VCHG_SET24_DIS 24 24 SMN_VWR_VCHG_SET25_DIS 25 25 SMN_VWR_VCHG_SET26_DIS 26 26 regNBIF_SMN_VWR_VCHG_RST_CTRL0 0 0xe882 27 0 5 SMN_VWR_VCHG_SET0_RST_DEF_REV 0 0 SMN_VWR_VCHG_SET1_RST_DEF_REV 1 1 SMN_VWR_VCHG_SET2_RST_DEF_REV 2 2 SMN_VWR_VCHG_SET3_RST_DEF_REV 3 3 SMN_VWR_VCHG_SET4_RST_DEF_REV 4 4 SMN_VWR_VCHG_SET5_RST_DEF_REV 5 5 SMN_VWR_VCHG_SET6_RST_DEF_REV 6 6 SMN_VWR_VCHG_SET7_RST_DEF_REV 7 7 SMN_VWR_VCHG_SET8_RST_DEF_REV 8 8 SMN_VWR_VCHG_SET9_RST_DEF_REV 9 9 SMN_VWR_VCHG_SET10_RST_DEF_REV 10 10 SMN_VWR_VCHG_SET11_RST_DEF_REV 11 11 SMN_VWR_VCHG_SET12_RST_DEF_REV 12 12 SMN_VWR_VCHG_SET13_RST_DEF_REV 13 13 SMN_VWR_VCHG_SET14_RST_DEF_REV 14 14 SMN_VWR_VCHG_SET15_RST_DEF_REV 15 15 SMN_VWR_VCHG_SET16_RST_DEF_REV 16 16 SMN_VWR_VCHG_SET17_RST_DEF_REV 17 17 SMN_VWR_VCHG_SET18_RST_DEF_REV 18 18 SMN_VWR_VCHG_SET19_RST_DEF_REV 19 19 SMN_VWR_VCHG_SET20_RST_DEF_REV 20 20 SMN_VWR_VCHG_SET21_RST_DEF_REV 21 21 SMN_VWR_VCHG_SET22_RST_DEF_REV 22 22 SMN_VWR_VCHG_SET23_RST_DEF_REV 23 23 SMN_VWR_VCHG_SET24_RST_DEF_REV 24 24 SMN_VWR_VCHG_SET25_RST_DEF_REV 25 25 SMN_VWR_VCHG_SET26_RST_DEF_REV 26 26 regNBIF_SMN_VWR_VCHG_TRIG 0 0xe884 27 0 5 SMN_VWR_VCHG_SET0_TRIG 0 0 SMN_VWR_VCHG_SET1_TRIG 1 1 SMN_VWR_VCHG_SET2_TRIG 2 2 SMN_VWR_VCHG_SET3_TRIG 3 3 SMN_VWR_VCHG_SET4_TRIG 4 4 SMN_VWR_VCHG_SET5_TRIG 5 5 SMN_VWR_VCHG_SET6_TRIG 6 6 SMN_VWR_VCHG_SET7_TRIG 7 7 SMN_VWR_VCHG_SET8_TRIG 8 8 SMN_VWR_VCHG_SET9_TRIG 9 9 SMN_VWR_VCHG_SET10_TRIG 10 10 SMN_VWR_VCHG_SET11_TRIG 11 11 SMN_VWR_VCHG_SET12_TRIG 12 12 SMN_VWR_VCHG_SET13_TRIG 13 13 SMN_VWR_VCHG_SET14_TRIG 14 14 SMN_VWR_VCHG_SET15_TRIG 15 15 SMN_VWR_VCHG_SET16_TRIG 16 16 SMN_VWR_VCHG_SET17_TRIG 17 17 SMN_VWR_VCHG_SET18_TRIG 18 18 SMN_VWR_VCHG_SET19_TRIG 19 19 SMN_VWR_VCHG_SET20_TRIG 20 20 SMN_VWR_VCHG_SET21_TRIG 21 21 SMN_VWR_VCHG_SET22_TRIG 22 22 SMN_VWR_VCHG_SET23_TRIG 23 23 SMN_VWR_VCHG_SET24_TRIG 24 24 SMN_VWR_VCHG_SET25_TRIG 25 25 SMN_VWR_VCHG_SET26_TRIG 26 26 regNBIF_SMN_VWR_WTRIG_CNTL 0 0xe885 27 0 5 SMN_VWR_WTRIG_SET0_DIS 0 0 SMN_VWR_WTRIG_SET1_DIS 1 1 SMN_VWR_WTRIG_SET2_DIS 2 2 SMN_VWR_WTRIG_SET3_DIS 3 3 SMN_VWR_WTRIG_SET4_DIS 4 4 SMN_VWR_WTRIG_SET5_DIS 5 5 SMN_VWR_WTRIG_SET6_DIS 6 6 SMN_VWR_WTRIG_SET7_DIS 7 7 SMN_VWR_WTRIG_SET8_DIS 8 8 SMN_VWR_WTRIG_SET9_DIS 9 9 SMN_VWR_WTRIG_SET10_DIS 10 10 SMN_VWR_WTRIG_SET11_DIS 11 11 SMN_VWR_WTRIG_SET12_DIS 12 12 SMN_VWR_WTRIG_SET13_DIS 13 13 SMN_VWR_WTRIG_SET14_DIS 14 14 SMN_VWR_WTRIG_SET15_DIS 15 15 SMN_VWR_WTRIG_SET16_DIS 16 16 SMN_VWR_WTRIG_SET17_DIS 17 17 SMN_VWR_WTRIG_SET18_DIS 18 18 SMN_VWR_WTRIG_SET19_DIS 19 19 SMN_VWR_WTRIG_SET20_DIS 20 20 SMN_VWR_WTRIG_SET21_DIS 21 21 SMN_VWR_WTRIG_SET22_DIS 22 22 SMN_VWR_WTRIG_SET23_DIS 23 23 SMN_VWR_WTRIG_SET24_DIS 24 24 SMN_VWR_WTRIG_SET25_DIS 25 25 SMN_VWR_WTRIG_SET26_DIS 26 26 regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0 0xe886 27 0 5 SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV 0 0 SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV 1 1 SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV 2 2 SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV 3 3 SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV 4 4 SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV 5 5 SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV 6 6 SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV 7 7 SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV 8 8 SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV 9 9 SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV 10 10 SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV 11 11 SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV 12 12 SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV 13 13 SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV 14 14 SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV 15 15 SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV 16 16 SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV 17 17 SMN_VWR_VCHG_SET18_DIFFDET_DEF_REV 18 18 SMN_VWR_VCHG_SET19_DIFFDET_DEF_REV 19 19 SMN_VWR_VCHG_SET20_DIFFDET_DEF_REV 20 20 SMN_VWR_VCHG_SET21_DIFFDET_DEF_REV 21 21 SMN_VWR_VCHG_SET22_DIFFDET_DEF_REV 22 22 SMN_VWR_VCHG_SET23_DIFFDET_DEF_REV 23 23 SMN_VWR_VCHG_SET24_DIFFDET_DEF_REV 24 24 SMN_VWR_VCHG_SET25_DIFFDET_DEF_REV 25 25 SMN_VWR_VCHG_SET26_DIFFDET_DEF_REV 26 26 regNBIF_MGCG_CTRL_LCLK 0 0xe887 7 0 5 NBIF_MGCG_EN_LCLK 0 0 NBIF_MGCG_MODE_LCLK 1 1 NBIF_MGCG_HYSTERESIS_LCLK 2 9 NBIF_MGCG_HST_DIS_LCLK 10 10 NBIF_MGCG_DMA_DIS_LCLK 11 11 NBIF_MGCG_REG_DIS_LCLK 12 12 NBIF_MGCG_AER_DIS_LCLK 13 13 regNBIF_DS_CTRL_LCLK 0 0xe888 2 0 5 NBIF_LCLK_DS_EN 0 0 NBIF_LCLK_DS_TIMER 16 31 regSMN_MST_CNTL0 0 0xe889 17 0 5 SMN_ARB_MODE 0 1 SMN_ZERO_BE_WR_EN_UPS 8 8 SMN_ZERO_BE_RD_EN_UPS 9 9 SMN_POST_MASK_EN_UPS 10 10 MULTI_SMN_TRANS_ID_DIS_UPS 11 11 SMN_ZERO_BE_WR_EN_DNS_DEV0 16 16 SMN_ZERO_BE_WR_EN_DNS_DEV1 17 17 SMN_ZERO_BE_WR_EN_DNS_DEV2 18 18 SMN_ZERO_BE_RD_EN_DNS_DEV0 20 20 SMN_ZERO_BE_RD_EN_DNS_DEV1 21 21 SMN_ZERO_BE_RD_EN_DNS_DEV2 22 22 SMN_POST_MASK_EN_DNS_DEV0 24 24 SMN_POST_MASK_EN_DNS_DEV1 25 25 SMN_POST_MASK_EN_DNS_DEV2 26 26 MULTI_SMN_TRANS_ID_DIS_DNS_DEV0 28 28 MULTI_SMN_TRANS_ID_DIS_DNS_DEV1 29 29 MULTI_SMN_TRANS_ID_DIS_DNS_DEV2 30 30 regSMN_MST_EP_CNTL1 0 0xe88a 24 0 5 SMN_POST_MASK_EN_EP_DEV0_PF0 0 0 SMN_POST_MASK_EN_EP_DEV0_PF1 1 1 SMN_POST_MASK_EN_EP_DEV0_PF2 2 2 SMN_POST_MASK_EN_EP_DEV0_PF3 3 3 SMN_POST_MASK_EN_EP_DEV0_PF4 4 4 SMN_POST_MASK_EN_EP_DEV0_PF5 5 5 SMN_POST_MASK_EN_EP_DEV0_PF6 6 6 SMN_POST_MASK_EN_EP_DEV0_PF7 7 7 SMN_POST_MASK_EN_EP_DEV1_PF0 8 8 SMN_POST_MASK_EN_EP_DEV1_PF1 9 9 SMN_POST_MASK_EN_EP_DEV1_PF2 10 10 SMN_POST_MASK_EN_EP_DEV1_PF3 11 11 SMN_POST_MASK_EN_EP_DEV1_PF4 12 12 SMN_POST_MASK_EN_EP_DEV1_PF5 13 13 SMN_POST_MASK_EN_EP_DEV1_PF6 14 14 SMN_POST_MASK_EN_EP_DEV1_PF7 15 15 SMN_POST_MASK_EN_EP_DEV2_PF0 16 16 SMN_POST_MASK_EN_EP_DEV2_PF1 17 17 SMN_POST_MASK_EN_EP_DEV2_PF2 18 18 SMN_POST_MASK_EN_EP_DEV2_PF3 19 19 SMN_POST_MASK_EN_EP_DEV2_PF4 20 20 SMN_POST_MASK_EN_EP_DEV2_PF5 21 21 SMN_POST_MASK_EN_EP_DEV2_PF6 22 22 SMN_POST_MASK_EN_EP_DEV2_PF7 23 23 regSMN_MST_EP_CNTL2 0 0xe88b 24 0 5 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0 0 0 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1 1 1 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2 2 2 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3 3 3 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4 4 4 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5 5 5 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6 6 6 MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7 7 7 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0 8 8 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1 9 9 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2 10 10 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3 11 11 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4 12 12 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5 13 13 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6 14 14 MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7 15 15 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0 16 16 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1 17 17 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2 18 18 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3 19 19 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4 20 20 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5 21 21 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6 22 22 MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7 23 23 regNBIF_SDP_VWR_VCHG_DIS_CTRL 0 0xe88c 9 0 5 SDP_VWR_VCHG_ENDP_F0_DIS 0 0 SDP_VWR_VCHG_ENDP_F1_DIS 1 1 SDP_VWR_VCHG_ENDP_F2_DIS 2 2 SDP_VWR_VCHG_ENDP_F3_DIS 3 3 SDP_VWR_VCHG_ENDP_F4_DIS 4 4 SDP_VWR_VCHG_ENDP_F5_DIS 5 5 SDP_VWR_VCHG_ENDP_F6_DIS 6 6 SDP_VWR_VCHG_ENDP_F7_DIS 7 7 SDP_VWR_VCHG_SWDS_P0_DIS 24 24 regNBIF_SDP_VWR_VCHG_RST_CTRL0 0 0xe88d 9 0 5 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN 1 1 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN 2 2 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN 3 3 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN 4 4 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN 5 5 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN 6 6 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN 7 7 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN 24 24 regNBIF_SDP_VWR_VCHG_RST_CTRL1 0 0xe88e 9 0 5 SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL 0 0 SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL 1 1 SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL 2 2 SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL 3 3 SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL 4 4 SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL 5 5 SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL 6 6 SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL 7 7 SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL 24 24 regNBIF_SDP_VWR_VCHG_TRIG 0 0xe88f 9 0 5 SDP_VWR_VCHG_ENDP_F0_TRIG 0 0 SDP_VWR_VCHG_ENDP_F1_TRIG 1 1 SDP_VWR_VCHG_ENDP_F2_TRIG 2 2 SDP_VWR_VCHG_ENDP_F3_TRIG 3 3 SDP_VWR_VCHG_ENDP_F4_TRIG 4 4 SDP_VWR_VCHG_ENDP_F5_TRIG 5 5 SDP_VWR_VCHG_ENDP_F6_TRIG 6 6 SDP_VWR_VCHG_ENDP_F7_TRIG 7 7 SDP_VWR_VCHG_SWDS_P0_TRIG 24 24 regNBIF_SHUB_TODET_CTRL 0 0xe898 4 0 5 NBIF_SHUB_TODET_EN 0 0 NBIF_SHUB_TODET_AER_LOG_EN 1 1 NBIF_SHUB_TODET_TIMER_UNIT 8 10 NBIF_SHUB_TIMEOUT_COUNT 16 31 regNBIF_SHUB_TODET_CLIENT_CTRL 0 0xe899 1 0 5 NBIF_SHUB_TODET_SLVERR_EN 0 31 regNBIF_SHUB_TODET_CLIENT_STATUS 0 0xe89a 1 0 5 NBIF_SHUB_TODET_CLIENT_STATUS 0 31 regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0 0xe89b 1 0 5 NBIF_SHUB_TODET_SYNCFLOOD_EN 0 31 regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0 0xe8c0 2 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0 0xe8c1 2 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0 0xe8c2 8 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 VC2_ALLOC 8 11 VC3_ALLOC 12 15 VC4_ALLOC 16 19 VC5_ALLOC 20 23 VC6_ALLOC 24 27 VC7_ALLOC 28 31 regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0 0xe8c3 8 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 VC2_ALLOC 8 11 VC3_ALLOC 12 15 VC4_ALLOC 16 19 VC5_ALLOC 20 23 VC6_ALLOC 24 27 VC7_ALLOC 28 31 regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC 0 0xe8c4 8 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 VC2_ALLOC 8 11 VC3_ALLOC 12 15 VC4_ALLOC 16 19 VC5_ALLOC 20 23 VC6_ALLOC 24 27 VC7_ALLOC 28 31 regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC 0 0xe8c5 8 0 5 VC0_ALLOC 0 3 VC1_ALLOC 4 7 VC2_ALLOC 8 11 VC3_ALLOC 12 15 VC4_ALLOC 16 19 VC5_ALLOC 20 23 VC6_ALLOC 24 27 VC7_ALLOC 28 31 regDISCON_HYSTERESIS_HEAD_CTRL 0 0xe8c6 2 0 5 GMI_DNS_SDP_DISCON_HYSTERESIS_H 0 3 GMI_UPS_SDP_DISCON_HYSTERESIS_H 8 11 regBIFC_PCIE_BDF_CNTL0 0 0xe8d0 2 0 5 DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0 0 15 DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1 16 31 regBIFC_PCIE_BDF_CNTL1 0 0xe8d1 2 0 5 DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2 0 15 DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3 16 31 regBIFC_EARLY_WAKEUP_CNTL 0 0xe8d2 3 0 5 NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE 0 0 NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT 1 1 NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE 2 2 regHARD_RST_CTRL 0 0xe000 15 0 5 DSPT_CFG_RST_EN 0 0 DSPT_CFG_STICKY_RST_EN 1 1 DSPT_PRV_RST_EN 2 2 DSPT_PRV_STICKY_RST_EN 3 3 EP_CFG_RST_EN 4 4 EP_CFG_STICKY_RST_EN 5 5 EP_PRV_RST_EN 6 6 EP_PRV_STICKY_RST_EN 7 7 SDP_PORT_RESET_EN 9 9 SION_AON_RESET_EN 10 10 STRAP_RST_EN 23 23 SWUS_SHADOW_RST_EN 28 28 CORE_STICKY_RST_EN 29 29 RELOAD_STRAP_EN 30 30 CORE_RST_EN 31 31 regSELF_SOFT_RST 0 0xe002 32 0 5 DSPT0_CFG_RST 0 0 DSPT0_CFG_STICKY_RST 1 1 DSPT0_PRV_RST 2 2 DSPT0_PRV_STICKY_RST 3 3 EP0_CFG_RST 4 4 EP0_CFG_STICKY_RST 5 5 EP0_PRV_RST 6 6 EP0_PRV_STICKY_RST 7 7 DSPT1_CFG_RST 8 8 DSPT1_CFG_STICKY_RST 9 9 DSPT1_PRV_RST 10 10 DSPT1_PRV_STICKY_RST 11 11 EP1_CFG_RST 12 12 EP1_CFG_STICKY_RST 13 13 EP1_PRV_RST 14 14 EP1_PRV_STICKY_RST 15 15 DSPT2_CFG_RST 16 16 DSPT2_CFG_STICKY_RST 17 17 DSPT2_PRV_RST 18 18 DSPT2_PRV_STICKY_RST 19 19 EP2_CFG_RST 20 20 EP2_CFG_STICKY_RST 21 21 EP2_PRV_RST 22 22 EP2_PRV_STICKY_RST 23 23 HRPU_SDP_PORT_RST 24 24 GSID_SDP_PORT_RST 25 25 GMIU_SDP_PORT_RST 26 26 GMID_SDP_PORT_RST 27 27 SWUS_SHADOW_RST 28 28 CORE_STICKY_RST 29 29 RELOAD_STRAP 30 30 CORE_RST 31 31 regBIF_GFX_DRV_VPU_RST 0 0xe003 8 0 5 DRV_MODE1_PF_CFG_RST 0 0 DRV_MODE1_PF_CFG_FLR_EXC_RST 1 1 DRV_MODE1_PF_CFG_STICKY_RST 2 2 DRV_MODE1_PF_PRV_RST 3 3 DRV_MODE1_PF_PRV_STICKY_RST 4 4 DRV_MODE1_VF_CFG_RST 5 5 DRV_MODE1_VF_CFG_STICKY_RST 6 6 DRV_MODE1_VF_PRV_RST 7 7 regBIF_RST_MISC_CTRL 0 0xe004 13 0 5 ERRSTATUS_KEPT_IN_PERSTB 0 0 DRV_RST_MODE 2 3 DRV_RST_CFG_MASK 4 4 DRV_RST_BITS_AUTO_CLEAR 5 5 FLR_RST_BIT_AUTO_CLEAR 6 6 STRAP_EP_LNK_RST_IOV_EN 8 8 LNK_RST_GRACE_MODE 9 9 LNK_RST_GRACE_TIMEOUT 10 12 LNK_RST_TIMER_SEL 13 14 LNK_RST_TIMER2_SEL 15 16 SRIOV_SAVE_VFS_ON_VFENABLE_CLR 17 19 LNK_RST_DMA_DUMMY_DIS 23 23 LNK_RST_DMA_DUMMY_RSPSTS 24 25 regBIF_RST_MISC_CTRL2 0 0xe005 6 0 5 SWUS_LNK_RST_TRANS_IDLE 16 16 SWDS_LNK_RST_TRANS_IDLE 17 17 ENDP0_LNK_RST_TRANS_IDLE 18 18 ENDP1_LNK_RST_TRANS_IDLE 19 19 ENDP2_LNK_RST_TRANS_IDLE 20 20 ALL_RST_TRANS_IDLE 31 31 regBIF_RST_MISC_CTRL3 0 0xe006 6 0 5 TIMER_SCALE 0 3 PME_TURNOFF_TIMEOUT 4 5 PME_TURNOFF_MODE 6 6 RELOAD_STRAP_DELAY_HARD 7 9 RELOAD_STRAP_DELAY_SOFT 10 12 RELOAD_STRAP_DELAY_SELF 13 15 regDEV0_PF0_FLR_RST_CTRL 0 0xe008 22 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 VF_CFG_EN 5 5 VF_CFG_STICKY_EN 6 6 VF_PRV_EN 7 7 SOFT_PF_CFG_EN 8 8 SOFT_PF_CFG_FLR_EXC_EN 9 9 SOFT_PF_CFG_STICKY_EN 10 10 SOFT_PF_PRV_EN 11 11 SOFT_PF_PRV_STICKY_EN 12 12 VF_VF_CFG_EN 13 13 VF_VF_CFG_STICKY_EN 14 14 VF_VF_PRV_EN 15 15 FLR_TWICE_EN 16 16 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 SOFT_PF_PFCOPY_PRV_EN 31 31 regDEV0_PF1_FLR_RST_CTRL 0 0xe009 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF2_FLR_RST_CTRL 0 0xe00a 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF3_FLR_RST_CTRL 0 0xe00b 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF4_FLR_RST_CTRL 0 0xe00c 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF5_FLR_RST_CTRL 0 0xe00d 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF6_FLR_RST_CTRL 0 0xe00e 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV0_PF7_FLR_RST_CTRL 0 0xe00f 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regBIF_INST_RESET_INTR_STS 0 0xe010 9 0 5 EP0_LINK_RESET_INTR_STS 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_STS 1 1 DRV_RESET_M0_INTR_STS 2 2 DRV_RESET_M1_INTR_STS 3 3 DRV_RESET_M2_INTR_STS 4 4 EP1_LINK_RESET_INTR_STS 8 8 EP1_LINK_RESET_CFG_ONLY_INTR_STS 9 9 EP2_LINK_RESET_INTR_STS 10 10 EP2_LINK_RESET_CFG_ONLY_INTR_STS 11 11 regBIF_PF_FLR_INTR_STS 0 0xe011 24 0 5 DEV0_PF0_FLR_INTR_STS 0 0 DEV0_PF1_FLR_INTR_STS 1 1 DEV0_PF2_FLR_INTR_STS 2 2 DEV0_PF3_FLR_INTR_STS 3 3 DEV0_PF4_FLR_INTR_STS 4 4 DEV0_PF5_FLR_INTR_STS 5 5 DEV0_PF6_FLR_INTR_STS 6 6 DEV0_PF7_FLR_INTR_STS 7 7 DEV1_PF0_FLR_INTR_STS 8 8 DEV1_PF1_FLR_INTR_STS 9 9 DEV1_PF2_FLR_INTR_STS 10 10 DEV1_PF3_FLR_INTR_STS 11 11 DEV1_PF4_FLR_INTR_STS 12 12 DEV1_PF5_FLR_INTR_STS 13 13 DEV1_PF6_FLR_INTR_STS 14 14 DEV1_PF7_FLR_INTR_STS 15 15 DEV2_PF0_FLR_INTR_STS 16 16 DEV2_PF1_FLR_INTR_STS 17 17 DEV2_PF2_FLR_INTR_STS 18 18 DEV2_PF3_FLR_INTR_STS 19 19 DEV2_PF4_FLR_INTR_STS 20 20 DEV2_PF5_FLR_INTR_STS 21 21 DEV2_PF6_FLR_INTR_STS 22 22 DEV2_PF7_FLR_INTR_STS 23 23 regBIF_D3HOTD0_INTR_STS 0 0xe012 24 0 5 DEV0_PF0_D3HOTD0_INTR_STS 0 0 DEV0_PF1_D3HOTD0_INTR_STS 1 1 DEV0_PF2_D3HOTD0_INTR_STS 2 2 DEV0_PF3_D3HOTD0_INTR_STS 3 3 DEV0_PF4_D3HOTD0_INTR_STS 4 4 DEV0_PF5_D3HOTD0_INTR_STS 5 5 DEV0_PF6_D3HOTD0_INTR_STS 6 6 DEV0_PF7_D3HOTD0_INTR_STS 7 7 DEV1_PF0_D3HOTD0_INTR_STS 8 8 DEV1_PF1_D3HOTD0_INTR_STS 9 9 DEV1_PF2_D3HOTD0_INTR_STS 10 10 DEV1_PF3_D3HOTD0_INTR_STS 11 11 DEV1_PF4_D3HOTD0_INTR_STS 12 12 DEV1_PF5_D3HOTD0_INTR_STS 13 13 DEV1_PF6_D3HOTD0_INTR_STS 14 14 DEV1_PF7_D3HOTD0_INTR_STS 15 15 DEV2_PF0_D3HOTD0_INTR_STS 16 16 DEV2_PF1_D3HOTD0_INTR_STS 17 17 DEV2_PF2_D3HOTD0_INTR_STS 18 18 DEV2_PF3_D3HOTD0_INTR_STS 19 19 DEV2_PF4_D3HOTD0_INTR_STS 20 20 DEV2_PF5_D3HOTD0_INTR_STS 21 21 DEV2_PF6_D3HOTD0_INTR_STS 22 22 DEV2_PF7_D3HOTD0_INTR_STS 23 23 regBIF_POWER_INTR_STS 0 0xe014 6 0 5 DEV0_PME_TURN_OFF_INTR_STS 0 0 DEV1_PME_TURN_OFF_INTR_STS 1 1 DEV2_PME_TURN_OFF_INTR_STS 2 2 PORT0_DSTATE_INTR_STS 16 16 PORT1_DSTATE_INTR_STS 17 17 PORT2_DSTATE_INTR_STS 18 18 regBIF_PF_DSTATE_INTR_STS 0 0xe015 24 0 5 DEV0_PF0_DSTATE_INTR_STS 0 0 DEV0_PF1_DSTATE_INTR_STS 1 1 DEV0_PF2_DSTATE_INTR_STS 2 2 DEV0_PF3_DSTATE_INTR_STS 3 3 DEV0_PF4_DSTATE_INTR_STS 4 4 DEV0_PF5_DSTATE_INTR_STS 5 5 DEV0_PF6_DSTATE_INTR_STS 6 6 DEV0_PF7_DSTATE_INTR_STS 7 7 DEV1_PF0_DSTATE_INTR_STS 8 8 DEV1_PF1_DSTATE_INTR_STS 9 9 DEV1_PF2_DSTATE_INTR_STS 10 10 DEV1_PF3_DSTATE_INTR_STS 11 11 DEV1_PF4_DSTATE_INTR_STS 12 12 DEV1_PF5_DSTATE_INTR_STS 13 13 DEV1_PF6_DSTATE_INTR_STS 14 14 DEV1_PF7_DSTATE_INTR_STS 15 15 DEV2_PF0_DSTATE_INTR_STS 16 16 DEV2_PF1_DSTATE_INTR_STS 17 17 DEV2_PF2_DSTATE_INTR_STS 18 18 DEV2_PF3_DSTATE_INTR_STS 19 19 DEV2_PF4_DSTATE_INTR_STS 20 20 DEV2_PF5_DSTATE_INTR_STS 21 21 DEV2_PF6_DSTATE_INTR_STS 22 22 DEV2_PF7_DSTATE_INTR_STS 23 23 regSELF_SOFT_RST_2 0 0xe016 10 0 5 DSPT3_CFG_RST 0 0 DSPT3_CFG_STICKY_RST 1 1 DSPT3_PRV_RST 2 2 DSPT3_PRV_STICKY_RST 3 3 EP3_CFG_RST 4 4 EP3_CFG_STICKY_RST 5 5 EP3_PRV_RST 6 6 EP3_PRV_STICKY_RST 7 7 GMISP0_SDP_PORT_RST 24 24 STRAP_RST 25 25 regBIF_INST_RESET_INTR_MASK 0 0xe020 9 0 5 EP0_LINK_RESET_INTR_MASK 0 0 EP0_LINK_RESET_CFG_ONLY_INTR_MASK 1 1 DRV_RESET_M0_INTR_MASK 2 2 DRV_RESET_M1_INTR_MASK 3 3 DRV_RESET_M2_INTR_MASK 4 4 EP1_LINK_RESET_INTR_MASK 8 8 EP1_LINK_RESET_CFG_ONLY_INTR_MASK 9 9 EP2_LINK_RESET_INTR_MASK 10 10 EP2_LINK_RESET_CFG_ONLY_INTR_MASK 11 11 regBIF_PF_FLR_INTR_MASK 0 0xe021 24 0 5 DEV0_PF0_FLR_INTR_MASK 0 0 DEV0_PF1_FLR_INTR_MASK 1 1 DEV0_PF2_FLR_INTR_MASK 2 2 DEV0_PF3_FLR_INTR_MASK 3 3 DEV0_PF4_FLR_INTR_MASK 4 4 DEV0_PF5_FLR_INTR_MASK 5 5 DEV0_PF6_FLR_INTR_MASK 6 6 DEV0_PF7_FLR_INTR_MASK 7 7 DEV1_PF0_FLR_INTR_MASK 8 8 DEV1_PF1_FLR_INTR_MASK 9 9 DEV1_PF2_FLR_INTR_MASK 10 10 DEV1_PF3_FLR_INTR_MASK 11 11 DEV1_PF4_FLR_INTR_MASK 12 12 DEV1_PF5_FLR_INTR_MASK 13 13 DEV1_PF6_FLR_INTR_MASK 14 14 DEV1_PF7_FLR_INTR_MASK 15 15 DEV2_PF0_FLR_INTR_MASK 16 16 DEV2_PF1_FLR_INTR_MASK 17 17 DEV2_PF2_FLR_INTR_MASK 18 18 DEV2_PF3_FLR_INTR_MASK 19 19 DEV2_PF4_FLR_INTR_MASK 20 20 DEV2_PF5_FLR_INTR_MASK 21 21 DEV2_PF6_FLR_INTR_MASK 22 22 DEV2_PF7_FLR_INTR_MASK 23 23 regBIF_D3HOTD0_INTR_MASK 0 0xe022 24 0 5 DEV0_PF0_D3HOTD0_INTR_MASK 0 0 DEV0_PF1_D3HOTD0_INTR_MASK 1 1 DEV0_PF2_D3HOTD0_INTR_MASK 2 2 DEV0_PF3_D3HOTD0_INTR_MASK 3 3 DEV0_PF4_D3HOTD0_INTR_MASK 4 4 DEV0_PF5_D3HOTD0_INTR_MASK 5 5 DEV0_PF6_D3HOTD0_INTR_MASK 6 6 DEV0_PF7_D3HOTD0_INTR_MASK 7 7 DEV1_PF0_D3HOTD0_INTR_MASK 8 8 DEV1_PF1_D3HOTD0_INTR_MASK 9 9 DEV1_PF2_D3HOTD0_INTR_MASK 10 10 DEV1_PF3_D3HOTD0_INTR_MASK 11 11 DEV1_PF4_D3HOTD0_INTR_MASK 12 12 DEV1_PF5_D3HOTD0_INTR_MASK 13 13 DEV1_PF6_D3HOTD0_INTR_MASK 14 14 DEV1_PF7_D3HOTD0_INTR_MASK 15 15 DEV2_PF0_D3HOTD0_INTR_MASK 16 16 DEV2_PF1_D3HOTD0_INTR_MASK 17 17 DEV2_PF2_D3HOTD0_INTR_MASK 18 18 DEV2_PF3_D3HOTD0_INTR_MASK 19 19 DEV2_PF4_D3HOTD0_INTR_MASK 20 20 DEV2_PF5_D3HOTD0_INTR_MASK 21 21 DEV2_PF6_D3HOTD0_INTR_MASK 22 22 DEV2_PF7_D3HOTD0_INTR_MASK 23 23 regBIF_POWER_INTR_MASK 0 0xe024 6 0 5 DEV0_PME_TURN_OFF_INTR_MASK 0 0 DEV1_PME_TURN_OFF_INTR_MASK 1 1 DEV2_PME_TURN_OFF_INTR_MASK 2 2 PORT0_DSTATE_INTR_MASK 16 16 PORT1_DSTATE_INTR_MASK 17 17 PORT2_DSTATE_INTR_MASK 18 18 regBIF_PF_DSTATE_INTR_MASK 0 0xe025 24 0 5 DEV0_PF0_DSTATE_INTR_MASK 0 0 DEV0_PF1_DSTATE_INTR_MASK 1 1 DEV0_PF2_DSTATE_INTR_MASK 2 2 DEV0_PF3_DSTATE_INTR_MASK 3 3 DEV0_PF4_DSTATE_INTR_MASK 4 4 DEV0_PF5_DSTATE_INTR_MASK 5 5 DEV0_PF6_DSTATE_INTR_MASK 6 6 DEV0_PF7_DSTATE_INTR_MASK 7 7 DEV1_PF0_DSTATE_INTR_MASK 8 8 DEV1_PF1_DSTATE_INTR_MASK 9 9 DEV1_PF2_DSTATE_INTR_MASK 10 10 DEV1_PF3_DSTATE_INTR_MASK 11 11 DEV1_PF4_DSTATE_INTR_MASK 12 12 DEV1_PF5_DSTATE_INTR_MASK 13 13 DEV1_PF6_DSTATE_INTR_MASK 14 14 DEV1_PF7_DSTATE_INTR_MASK 15 15 DEV2_PF0_DSTATE_INTR_MASK 16 16 DEV2_PF1_DSTATE_INTR_MASK 17 17 DEV2_PF2_DSTATE_INTR_MASK 18 18 DEV2_PF3_DSTATE_INTR_MASK 19 19 DEV2_PF4_DSTATE_INTR_MASK 20 20 DEV2_PF5_DSTATE_INTR_MASK 21 21 DEV2_PF6_DSTATE_INTR_MASK 22 22 DEV2_PF7_DSTATE_INTR_MASK 23 23 regBIF_PF_FLR_RST 0 0xe040 24 0 5 DEV0_PF0_FLR_RST 0 0 DEV0_PF1_FLR_RST 1 1 DEV0_PF2_FLR_RST 2 2 DEV0_PF3_FLR_RST 3 3 DEV0_PF4_FLR_RST 4 4 DEV0_PF5_FLR_RST 5 5 DEV0_PF6_FLR_RST 6 6 DEV0_PF7_FLR_RST 7 7 DEV1_PF0_FLR_RST 8 8 DEV1_PF1_FLR_RST 9 9 DEV1_PF2_FLR_RST 10 10 DEV1_PF3_FLR_RST 11 11 DEV1_PF4_FLR_RST 12 12 DEV1_PF5_FLR_RST 13 13 DEV1_PF6_FLR_RST 14 14 DEV1_PF7_FLR_RST 15 15 DEV2_PF0_FLR_RST 16 16 DEV2_PF1_FLR_RST 17 17 DEV2_PF2_FLR_RST 18 18 DEV2_PF3_FLR_RST 19 19 DEV2_PF4_FLR_RST 20 20 DEV2_PF5_FLR_RST 21 21 DEV2_PF6_FLR_RST 22 22 DEV2_PF7_FLR_RST 23 23 regBIF_DEV0_PF0_DSTATE_VALUE 0 0xe050 3 0 5 DEV0_PF0_DSTATE_TGT_VALUE 0 1 DEV0_PF0_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF0_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF1_DSTATE_VALUE 0 0xe051 3 0 5 DEV0_PF1_DSTATE_TGT_VALUE 0 1 DEV0_PF1_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF1_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF2_DSTATE_VALUE 0 0xe052 3 0 5 DEV0_PF2_DSTATE_TGT_VALUE 0 1 DEV0_PF2_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF2_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF3_DSTATE_VALUE 0 0xe053 3 0 5 DEV0_PF3_DSTATE_TGT_VALUE 0 1 DEV0_PF3_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF3_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF4_DSTATE_VALUE 0 0xe054 3 0 5 DEV0_PF4_DSTATE_TGT_VALUE 0 1 DEV0_PF4_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF4_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF5_DSTATE_VALUE 0 0xe055 3 0 5 DEV0_PF5_DSTATE_TGT_VALUE 0 1 DEV0_PF5_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF5_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF6_DSTATE_VALUE 0 0xe056 3 0 5 DEV0_PF6_DSTATE_TGT_VALUE 0 1 DEV0_PF6_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF6_DSTATE_ACK_VALUE 16 17 regBIF_DEV0_PF7_DSTATE_VALUE 0 0xe057 3 0 5 DEV0_PF7_DSTATE_TGT_VALUE 0 1 DEV0_PF7_DSTATE_NEED_D3TOD0_RESET 2 2 DEV0_PF7_DSTATE_ACK_VALUE 16 17 regDEV0_PF0_D3HOTD0_RST_CTRL 0 0xe078 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF1_D3HOTD0_RST_CTRL 0 0xe079 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF2_D3HOTD0_RST_CTRL 0 0xe07a 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF3_D3HOTD0_RST_CTRL 0 0xe07b 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF4_D3HOTD0_RST_CTRL 0 0xe07c 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF5_D3HOTD0_RST_CTRL 0 0xe07d 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF6_D3HOTD0_RST_CTRL 0 0xe07e 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV0_PF7_D3HOTD0_RST_CTRL 0 0xe07f 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF0_FLR_RST_CTRL 0 0xe200 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF1_FLR_RST_CTRL 0 0xe201 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF2_FLR_RST_CTRL 0 0xe202 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF3_FLR_RST_CTRL 0 0xe203 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF4_FLR_RST_CTRL 0 0xe204 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF5_FLR_RST_CTRL 0 0xe205 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF6_FLR_RST_CTRL 0 0xe206 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV1_PF7_FLR_RST_CTRL 0 0xe207 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regBIF_DEV1_PF0_DSTATE_VALUE 0 0xe208 3 0 5 DEV1_PF0_DSTATE_TGT_VALUE 0 1 DEV1_PF0_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF0_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF1_DSTATE_VALUE 0 0xe209 3 0 5 DEV1_PF1_DSTATE_TGT_VALUE 0 1 DEV1_PF1_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF1_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF2_DSTATE_VALUE 0 0xe20a 3 0 5 DEV1_PF2_DSTATE_TGT_VALUE 0 1 DEV1_PF2_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF2_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF3_DSTATE_VALUE 0 0xe20b 3 0 5 DEV1_PF3_DSTATE_TGT_VALUE 0 1 DEV1_PF3_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF3_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF4_DSTATE_VALUE 0 0xe20c 3 0 5 DEV1_PF4_DSTATE_TGT_VALUE 0 1 DEV1_PF4_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF4_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF5_DSTATE_VALUE 0 0xe20d 3 0 5 DEV1_PF5_DSTATE_TGT_VALUE 0 1 DEV1_PF5_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF5_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF6_DSTATE_VALUE 0 0xe20e 3 0 5 DEV1_PF6_DSTATE_TGT_VALUE 0 1 DEV1_PF6_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF6_DSTATE_ACK_VALUE 16 17 regBIF_DEV1_PF7_DSTATE_VALUE 0 0xe20f 3 0 5 DEV1_PF7_DSTATE_TGT_VALUE 0 1 DEV1_PF7_DSTATE_NEED_D3TOD0_RESET 2 2 DEV1_PF7_DSTATE_ACK_VALUE 16 17 regDEV1_PF0_D3HOTD0_RST_CTRL 0 0xe210 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF1_D3HOTD0_RST_CTRL 0 0xe211 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF2_D3HOTD0_RST_CTRL 0 0xe212 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF3_D3HOTD0_RST_CTRL 0 0xe213 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF4_D3HOTD0_RST_CTRL 0 0xe214 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF5_D3HOTD0_RST_CTRL 0 0xe215 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF6_D3HOTD0_RST_CTRL 0 0xe216 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV1_PF7_D3HOTD0_RST_CTRL 0 0xe217 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF0_FLR_RST_CTRL 0 0xe218 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF1_FLR_RST_CTRL 0 0xe219 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF2_FLR_RST_CTRL 0 0xe21a 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF3_FLR_RST_CTRL 0 0xe21b 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF4_FLR_RST_CTRL 0 0xe21c 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF5_FLR_RST_CTRL 0 0xe21d 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF6_FLR_RST_CTRL 0 0xe21e 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regDEV2_PF7_FLR_RST_CTRL 0 0xe21f 9 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 FLR_GRACE_MODE 17 17 FLR_GRACE_TIMEOUT 18 20 FLR_DMA_DUMMY_RSPSTS 23 24 FLR_HST_DUMMY_RSPSTS 25 26 regBIF_DEV2_PF0_DSTATE_VALUE 0 0xe220 3 0 5 DEV2_PF0_DSTATE_TGT_VALUE 0 1 DEV2_PF0_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF0_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF1_DSTATE_VALUE 0 0xe221 3 0 5 DEV2_PF1_DSTATE_TGT_VALUE 0 1 DEV2_PF1_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF1_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF2_DSTATE_VALUE 0 0xe222 3 0 5 DEV2_PF2_DSTATE_TGT_VALUE 0 1 DEV2_PF2_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF2_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF3_DSTATE_VALUE 0 0xe223 3 0 5 DEV2_PF3_DSTATE_TGT_VALUE 0 1 DEV2_PF3_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF3_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF4_DSTATE_VALUE 0 0xe224 3 0 5 DEV2_PF4_DSTATE_TGT_VALUE 0 1 DEV2_PF4_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF4_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF5_DSTATE_VALUE 0 0xe225 3 0 5 DEV2_PF5_DSTATE_TGT_VALUE 0 1 DEV2_PF5_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF5_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF6_DSTATE_VALUE 0 0xe226 3 0 5 DEV2_PF6_DSTATE_TGT_VALUE 0 1 DEV2_PF6_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF6_DSTATE_ACK_VALUE 16 17 regBIF_DEV2_PF7_DSTATE_VALUE 0 0xe227 3 0 5 DEV2_PF7_DSTATE_TGT_VALUE 0 1 DEV2_PF7_DSTATE_NEED_D3TOD0_RESET 2 2 DEV2_PF7_DSTATE_ACK_VALUE 16 17 regDEV2_PF0_D3HOTD0_RST_CTRL 0 0xe228 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF1_D3HOTD0_RST_CTRL 0 0xe229 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF2_D3HOTD0_RST_CTRL 0 0xe22a 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF3_D3HOTD0_RST_CTRL 0 0xe22b 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF4_D3HOTD0_RST_CTRL 0 0xe22c 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF5_D3HOTD0_RST_CTRL 0 0xe22d 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF6_D3HOTD0_RST_CTRL 0 0xe22e 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regDEV2_PF7_D3HOTD0_RST_CTRL 0 0xe22f 5 0 5 PF_CFG_EN 0 0 PF_CFG_FLR_EXC_EN 1 1 PF_CFG_STICKY_EN 2 2 PF_PRV_EN 3 3 PF_PRV_STICKY_EN 4 4 regBIF_PORT0_DSTATE_VALUE 0 0xe230 2 0 5 PORT0_DSTATE_TGT_VALUE 0 1 PORT0_DSTATE_ACK_VALUE 16 17 regBIF_PORT1_DSTATE_VALUE 0 0xe231 2 0 5 PORT1_DSTATE_TGT_VALUE 0 1 PORT1_DSTATE_ACK_VALUE 16 17 regBIF_PORT2_DSTATE_VALUE 0 0xe232 2 0 5 PORT2_DSTATE_TGT_VALUE 0 1 PORT2_DSTATE_ACK_VALUE 16 17 regBIFL_RAS_CENTRAL_CNTL 0 0xe400 3 0 5 BIFL_RAS_CONTL_ERREVENT_DIS 29 29 BIFL_RAS_CONTL_INTR_DIS 30 30 BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS 31 31 regBIFL_RAS_CENTRAL_STATUS 0 0xe410 7 0 5 BIFL_L2C_EgStall_det 0 0 BIFL_L2C_ErrEvent_det 1 1 BIFL_C2L_EgStall_det 2 2 BIFL_C2L_ErrEvent_det 3 3 BIFL_RasContller_ErrEvent_Recv 29 29 BIFL_RasContller_Intr_Recv 30 30 BIFL_LinkDis_Recv 31 31 regBIFL_RAS_LEAF0_CTRL 0 0xe420 10 0 5 ERR_EVENT_DET_EN 0 0 POISON_ERREVENT_EN 1 1 POISON_STALL_EN 2 2 PARITY_ERREVENT_EN 3 3 PARITY_STALL_EN 4 4 RCVERREVENT_ERREVENT_EN 5 5 RCVERREVENT_STALL_EN 6 6 ERR_EVENT_PROP_EN 10 10 EGRESS_STALL_PROP_EN 11 11 ERR_EVENT_RAS_INTR_EN 16 16 regBIFL_RAS_LEAF1_CTRL 0 0xe421 10 0 5 ERR_EVENT_DET_EN 0 0 POISON_ERREVENT_EN 1 1 POISON_STALL_EN 2 2 PARITY_ERREVENT_EN 3 3 PARITY_STALL_EN 4 4 RCVERREVENT_ERREVENT_EN 5 5 RCVERREVENT_STALL_EN 6 6 ERR_EVENT_PROP_EN 10 10 EGRESS_STALL_PROP_EN 11 11 ERR_EVENT_RAS_INTR_EN 16 16 regBIFL_RAS_LEAF2_CTRL 0 0xe422 10 0 5 ERR_EVENT_DET_EN 0 0 POISON_ERREVENT_EN 1 1 POISON_STALL_EN 2 2 PARITY_ERREVENT_EN 3 3 PARITY_STALL_EN 4 4 RCVERREVENT_ERREVENT_EN 5 5 RCVERREVENT_STALL_EN 6 6 ERR_EVENT_PROP_EN 10 10 EGRESS_STALL_PROP_EN 11 11 ERR_EVENT_RAS_INTR_EN 16 16 regBIFL_RAS_LEAF3_CTRL 0 0xe423 10 0 5 ERR_EVENT_DET_EN 0 0 POISON_ERREVENT_EN 1 1 POISON_STALL_EN 2 2 PARITY_ERREVENT_EN 3 3 PARITY_STALL_EN 4 4 RCVERREVENT_ERREVENT_EN 5 5 RCVERREVENT_STALL_EN 6 6 ERR_EVENT_PROP_EN 10 10 EGRESS_STALL_PROP_EN 11 11 ERR_EVENT_RAS_INTR_EN 16 16 regBIFL_RAS_LEAF0_STATUS 0 0xe430 7 0 5 ERR_EVENT_RECV 0 0 POISON_ERR_DET 1 1 PARITY_ERR_DET 2 2 ERR_EVENT_GENN_STAT 8 8 EGRESS_STALLED_GENN_STAT 9 9 ERR_EVENT_PROP_STAT 10 10 EGRESS_STALLED_PROP_STAT 11 11 regBIFL_RAS_LEAF1_STATUS 0 0xe431 7 0 5 ERR_EVENT_RECV 0 0 POISON_ERR_DET 1 1 PARITY_ERR_DET 2 2 ERR_EVENT_GENN_STAT 8 8 EGRESS_STALLED_GENN_STAT 9 9 ERR_EVENT_PROP_STAT 10 10 EGRESS_STALLED_PROP_STAT 11 11 regBIFL_RAS_LEAF2_STATUS 0 0xe432 7 0 5 ERR_EVENT_RECV 0 0 POISON_ERR_DET 1 1 PARITY_ERR_DET 2 2 ERR_EVENT_GENN_STAT 8 8 EGRESS_STALLED_GENN_STAT 9 9 ERR_EVENT_PROP_STAT 10 10 EGRESS_STALLED_PROP_STAT 11 11 regBIFL_RAS_LEAF3_STATUS 0 0xe433 7 0 5 ERR_EVENT_RECV 0 0 POISON_ERR_DET 1 1 PARITY_ERR_DET 2 2 ERR_EVENT_GENN_STAT 8 8 EGRESS_STALLED_GENN_STAT 9 9 ERR_EVENT_PROP_STAT 10 10 EGRESS_STALLED_PROP_STAT 11 11 regBIFL_IOHUB_RAS_IH_CNTL 0 0xe7fe 1 0 5 BIFL_RAS_IH_INTR_EN 0 0 regBIFL_RAS_VWR_FROM_IOHUB 0 0xe7ff 1 0 5 BIFL_RAS_IH_INTR_TRIG 0 0 regSION_CL0_RdRsp_BurstTarget_REG0 0 0xe900 1 0 5 RdRsp_BurstTarget_31_0 0 31 regSION_CL0_RdRsp_BurstTarget_REG1 0 0xe901 1 0 5 RdRsp_BurstTarget_63_32 0 31 regSION_CL0_RdRsp_TimeSlot_REG0 0 0xe902 1 0 5 RdRsp_TimeSlot_31_0 0 31 regSION_CL0_RdRsp_TimeSlot_REG1 0 0xe903 1 0 5 RdRsp_TimeSlot_63_32 0 31 regSION_CL0_WrRsp_BurstTarget_REG0 0 0xe904 1 0 5 WrRsp_BurstTarget_31_0 0 31 regSION_CL0_WrRsp_BurstTarget_REG1 0 0xe905 1 0 5 WrRsp_BurstTarget_63_32 0 31 regSION_CL0_WrRsp_TimeSlot_REG0 0 0xe906 1 0 5 WrRsp_TimeSlot_31_0 0 31 regSION_CL0_WrRsp_TimeSlot_REG1 0 0xe907 1 0 5 WrRsp_TimeSlot_63_32 0 31 regSION_CL0_Req_BurstTarget_REG0 0 0xe908 1 0 5 Req_BurstTarget_31_0 0 31 regSION_CL0_Req_BurstTarget_REG1 0 0xe909 1 0 5 Req_BurstTarget_63_32 0 31 regSION_CL0_Req_TimeSlot_REG0 0 0xe90a 1 0 5 Req_TimeSlot_31_0 0 31 regSION_CL0_Req_TimeSlot_REG1 0 0xe90b 1 0 5 Req_TimeSlot_63_32 0 31 regSION_CL0_ReqPoolCredit_Alloc_REG0 0 0xe90c 1 0 5 ReqPoolCredit_Alloc_31_0 0 31 regSION_CL0_ReqPoolCredit_Alloc_REG1 0 0xe90d 1 0 5 ReqPoolCredit_Alloc_63_32 0 31 regSION_CL0_DataPoolCredit_Alloc_REG0 0 0xe90e 1 0 5 DataPoolCredit_Alloc_31_0 0 31 regSION_CL0_DataPoolCredit_Alloc_REG1 0 0xe90f 1 0 5 DataPoolCredit_Alloc_63_32 0 31 regSION_CL0_RdRspPoolCredit_Alloc_REG0 0 0xe910 1 0 5 RdRspPoolCredit_Alloc_31_0 0 31 regSION_CL0_RdRspPoolCredit_Alloc_REG1 0 0xe911 1 0 5 RdRspPoolCredit_Alloc_63_32 0 31 regSION_CL0_WrRspPoolCredit_Alloc_REG0 0 0xe912 1 0 5 WrRspPoolCredit_Alloc_31_0 0 31 regSION_CL0_WrRspPoolCredit_Alloc_REG1 0 0xe913 1 0 5 WrRspPoolCredit_Alloc_63_32 0 31 regSION_CL1_RdRsp_BurstTarget_REG0 0 0xe914 1 0 5 RdRsp_BurstTarget_31_0 0 31 regSION_CL1_RdRsp_BurstTarget_REG1 0 0xe915 1 0 5 RdRsp_BurstTarget_63_32 0 31 regSION_CL1_RdRsp_TimeSlot_REG0 0 0xe916 1 0 5 RdRsp_TimeSlot_31_0 0 31 regSION_CL1_RdRsp_TimeSlot_REG1 0 0xe917 1 0 5 RdRsp_TimeSlot_63_32 0 31 regSION_CL1_WrRsp_BurstTarget_REG0 0 0xe918 1 0 5 WrRsp_BurstTarget_31_0 0 31 regSION_CL1_WrRsp_BurstTarget_REG1 0 0xe919 1 0 5 WrRsp_BurstTarget_63_32 0 31 regSION_CL1_WrRsp_TimeSlot_REG0 0 0xe91a 1 0 5 WrRsp_TimeSlot_31_0 0 31 regSION_CL1_WrRsp_TimeSlot_REG1 0 0xe91b 1 0 5 WrRsp_TimeSlot_63_32 0 31 regSION_CL1_Req_BurstTarget_REG0 0 0xe91c 1 0 5 Req_BurstTarget_31_0 0 31 regSION_CL1_Req_BurstTarget_REG1 0 0xe91d 1 0 5 Req_BurstTarget_63_32 0 31 regSION_CL1_Req_TimeSlot_REG0 0 0xe91e 1 0 5 Req_TimeSlot_31_0 0 31 regSION_CL1_Req_TimeSlot_REG1 0 0xe91f 1 0 5 Req_TimeSlot_63_32 0 31 regSION_CL1_ReqPoolCredit_Alloc_REG0 0 0xe920 1 0 5 ReqPoolCredit_Alloc_31_0 0 31 regSION_CL1_ReqPoolCredit_Alloc_REG1 0 0xe921 1 0 5 ReqPoolCredit_Alloc_63_32 0 31 regSION_CL1_DataPoolCredit_Alloc_REG0 0 0xe922 1 0 5 DataPoolCredit_Alloc_31_0 0 31 regSION_CL1_DataPoolCredit_Alloc_REG1 0 0xe923 1 0 5 DataPoolCredit_Alloc_63_32 0 31 regSION_CL1_RdRspPoolCredit_Alloc_REG0 0 0xe924 1 0 5 RdRspPoolCredit_Alloc_31_0 0 31 regSION_CL1_RdRspPoolCredit_Alloc_REG1 0 0xe925 1 0 5 RdRspPoolCredit_Alloc_63_32 0 31 regSION_CL1_WrRspPoolCredit_Alloc_REG0 0 0xe926 1 0 5 WrRspPoolCredit_Alloc_31_0 0 31 regSION_CL1_WrRspPoolCredit_Alloc_REG1 0 0xe927 1 0 5 WrRspPoolCredit_Alloc_63_32 0 31 regSION_CL2_RdRsp_BurstTarget_REG0 0 0xe928 1 0 5 RdRsp_BurstTarget_31_0 0 31 regSION_CL2_RdRsp_BurstTarget_REG1 0 0xe929 1 0 5 RdRsp_BurstTarget_63_32 0 31 regSION_CL2_RdRsp_TimeSlot_REG0 0 0xe92a 1 0 5 RdRsp_TimeSlot_31_0 0 31 regSION_CL2_RdRsp_TimeSlot_REG1 0 0xe92b 1 0 5 RdRsp_TimeSlot_63_32 0 31 regSION_CL2_WrRsp_BurstTarget_REG0 0 0xe92c 1 0 5 WrRsp_BurstTarget_31_0 0 31 regSION_CL2_WrRsp_BurstTarget_REG1 0 0xe92d 1 0 5 WrRsp_BurstTarget_63_32 0 31 regSION_CL2_WrRsp_TimeSlot_REG0 0 0xe92e 1 0 5 WrRsp_TimeSlot_31_0 0 31 regSION_CL2_WrRsp_TimeSlot_REG1 0 0xe92f 1 0 5 WrRsp_TimeSlot_63_32 0 31 regSION_CL2_Req_BurstTarget_REG0 0 0xe930 1 0 5 Req_BurstTarget_31_0 0 31 regSION_CL2_Req_BurstTarget_REG1 0 0xe931 1 0 5 Req_BurstTarget_63_32 0 31 regSION_CL2_Req_TimeSlot_REG0 0 0xe932 1 0 5 Req_TimeSlot_31_0 0 31 regSION_CL2_Req_TimeSlot_REG1 0 0xe933 1 0 5 Req_TimeSlot_63_32 0 31 regSION_CL2_ReqPoolCredit_Alloc_REG0 0 0xe934 1 0 5 ReqPoolCredit_Alloc_31_0 0 31 regSION_CL2_ReqPoolCredit_Alloc_REG1 0 0xe935 1 0 5 ReqPoolCredit_Alloc_63_32 0 31 regSION_CL2_DataPoolCredit_Alloc_REG0 0 0xe936 1 0 5 DataPoolCredit_Alloc_31_0 0 31 regSION_CL2_DataPoolCredit_Alloc_REG1 0 0xe937 1 0 5 DataPoolCredit_Alloc_63_32 0 31 regSION_CL2_RdRspPoolCredit_Alloc_REG0 0 0xe938 1 0 5 RdRspPoolCredit_Alloc_31_0 0 31 regSION_CL2_RdRspPoolCredit_Alloc_REG1 0 0xe939 1 0 5 RdRspPoolCredit_Alloc_63_32 0 31 regSION_CL2_WrRspPoolCredit_Alloc_REG0 0 0xe93a 1 0 5 WrRspPoolCredit_Alloc_31_0 0 31 regSION_CL2_WrRspPoolCredit_Alloc_REG1 0 0xe93b 1 0 5 WrRspPoolCredit_Alloc_63_32 0 31 regSION_CNTL_REG0 0 0xe93c 20 0 5 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0 0 0 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1 1 1 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2 2 2 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3 3 3 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4 4 4 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5 5 5 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6 6 6 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7 7 7 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8 8 8 NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9 9 9 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0 10 10 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1 11 11 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2 12 12 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3 13 13 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4 14 14 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5 15 15 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6 16 16 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7 17 17 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8 18 18 NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9 19 19 regSION_CNTL_REG1 0 0xe93d 2 0 5 LIVELOCK_WATCHDOG_THRESHOLD 0 7 CG_OFF_HYSTERESIS 8 15 regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0 0x10000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0 0x10000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF0_0_COMMAND 0 0x10001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF0_0_STATUS 0 0x10001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0 0x10002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0 0x10002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0 0x10002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0 0x10002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0 0x10003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF0_0_LATENCY 0 0x10003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF0_0_HEADER 0 0x10003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF0_0_BIST 0 0x10003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0 0x10004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0 0x10005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0 0x10006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0 0x10007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0 0x10008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0 0x10009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0 0x1000a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0 0x1000b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0 0x1000c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0 0x1000d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0 0x1000f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0 0x1000f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0 0x1000f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0 0x1000f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0 0x10012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0 0x10013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0 0x10014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0 0x10014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0 0x10015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0 0x10019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0 0x10019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0 0x1001a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0 0x1001b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0 0x1001b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0 0x1001c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0 0x1001d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0 0x1001d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0 0x10022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0 0x10023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0 0x10023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0 0x10024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0 0x10025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0 0x10025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0 0x10028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0 0x10028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0 0x10029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0 0x1002a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0 0x1002a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0 0x1002a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0 0x1002b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0 0x1002b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0 0x1002b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0 0x1002c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0 0x1002c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0 0x1002d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0 0x10030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0 0x10030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0 0x10031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0 0x10032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x10040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x10041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0 0x10042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0 0x10043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0 0x10044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0 0x10045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0 0x10046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0 0x10047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0 0x10047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0 0x10048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0 0x10049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0 0x1004a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0 0x1004b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0 0x1004c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0 0x1004d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x10050 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x10051 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x10052 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x10054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0 0x10055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0 0x10056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0 0x10057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0 0x10058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0 0x10059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1005a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0 0x1005b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0 0x1005c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0 0x1005d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0 0x1005e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0 0x10062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0 0x10063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0 0x10064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0 0x10065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0 0x10080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0 0x10081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0 0x10082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0 0x10083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0 0x10084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0 0x10085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0 0x10086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0 0x10087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0 0x10088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0 0x10089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0 0x1008a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0 0x1008b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0 0x1008c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x10090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x10091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0 0x10092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0 0x10093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0 0x10094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0 0x10095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0 0x10096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0 0x10097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0 0x10097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x10098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x10098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x10098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x10098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x10099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x10099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x10099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x10099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x1009c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0 0x1009d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0 0x1009e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x1009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x1009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x100a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x100a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x100a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x100a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x100a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x100a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x100a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x100a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x100a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x100a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x100a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x100a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x100a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x100a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0 0x100a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0 0x100a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0 0x100a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0 0x100ac 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0 0x100ad 3 0 5 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0 0x100ad 2 0 5 STU 0 4 ATC_ENABLE 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0 0x100b0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0 0x100b1 2 0 5 PRI_ENABLE 0 0 PRI_RESET 1 1 regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0 0x100b1 4 0 5 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0x100b2 1 0 5 OUTSTAND_PAGE_REQ_CAPACITY 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0x100b3 1 0 5 OUTSTAND_PAGE_REQ_ALLOC 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0 0x100b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0 0x100b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0 0x100b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0 0x100bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0 0x100bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0 0x100bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0 0x100be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0 0x100bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0 0x100c0 1 0 5 MC_RECEIVE_0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0 0x100c1 1 0 5 MC_RECEIVE_1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0 0x100c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0 0x100c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x100c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x100c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0 0x100c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0 0x100c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0 0x100ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0 0x100cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0 0x100cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0 0x100cc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0 0x100cd 4 0 5 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0 0x100ce 6 0 5 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0 0x100ce 1 0 5 SRIOV_VF_MIGRATION_STATUS 0 0 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0 0x100cf 1 0 5 SRIOV_INITIAL_VFS 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0 0x100cf 1 0 5 SRIOV_TOTAL_VFS 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0 0x100d0 1 0 5 SRIOV_NUM_VFS 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0 0x100d0 1 0 5 SRIOV_FUNC_DEP_LINK 0 7 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0 0x100d1 1 0 5 SRIOV_FIRST_VF_OFFSET 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0 0x100d1 1 0 5 SRIOV_VF_STRIDE 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0 0x100d2 1 0 5 SRIOV_VF_DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0 0x100d3 1 0 5 SRIOV_SUPPORTED_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0 0x100d4 1 0 5 SRIOV_SYSTEM_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0 0x100d5 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0 0x100d6 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0 0x100d7 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0 0x100d8 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0 0x100d9 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0 0x100da 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0x100db 2 0 5 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x100dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0 0x100dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0 0x100de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0 0x10100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0 0x10101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0 0x10102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x10104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0 0x10105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0 0x10106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0 0x10107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x10108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x10109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x1010a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x1010c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x1010c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x1010c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x1010c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x1010d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x1010d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x1010d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x1010d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x1010e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x1010e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x1010e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x1010e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x1010f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x1010f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x1010f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x1010f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x10110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0 0x10111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0 0x10111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0 0x10112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0 0x10112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0 0x10113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0 0x10113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0 0x10114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0 0x10114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0 0x10115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0 0x10115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0 0x10116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0 0x10116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0 0x10117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0 0x10117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0 0x10118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0 0x10118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0 0x10119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0 0x10119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0 0x1011a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0 0x1011a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0 0x1011b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0 0x1011b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0 0x1011c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0 0x1011c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0 0x1011d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0 0x1011d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0 0x1011e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0 0x1011e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0 0x1011f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0 0x1011f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0 0x10120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0 0x10120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0 0x10121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0 0x10121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0 0x10130 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0 0x10131 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0 0x10132 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0 0x10133 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0 0x10134 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0 0x10135 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0 0x10136 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0 0x10137 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0 0x10138 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0 0x10139 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0 0x1013a 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0 0x1013b 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0 0x1013c 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0 0x10140 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0 0x10141 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0 0x10142 2 0 5 VF_EN 0 0 VF_NUM 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0 0x10143 18 0 5 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0 0x10144 18 0 5 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0 0x10145 1 0 5 SOFT_PF_FLR 0 0 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0 0x10146 5 0 5 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0 0x10147 32 0 5 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0 0x10148 32 0 5 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0 0x10149 3 0 5 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0 0x1014a 2 0 5 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0 0x1014b 3 0 5 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0 0x1014c 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0 0x1014d 2 0 5 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0 0x1014e 2 0 5 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0 0x1014f 2 0 5 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0 0x10150 2 0 5 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0 0x10151 2 0 5 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0 0x10152 2 0 5 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0 0x10153 2 0 5 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0 0x10154 2 0 5 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0 0x10155 2 0 5 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0 0x10156 2 0 5 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0 0x10157 2 0 5 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0 0x10158 2 0 5 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0 0x10159 2 0 5 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0 0x1015a 2 0 5 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0 0x1015b 2 0 5 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0 0x1015c 2 0 5 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0 0x1015d 2 0 5 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0 0x1015e 2 0 5 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0 0x1015f 2 0 5 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0 0x10160 2 0 5 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0 0x10161 2 0 5 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0 0x10162 2 0 5 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0 0x10163 2 0 5 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0 0x10164 2 0 5 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0 0x10165 2 0 5 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0 0x10166 2 0 5 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0 0x10167 2 0 5 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0 0x10168 2 0 5 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0 0x10169 2 0 5 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0 0x1016a 2 0 5 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0 0x1016b 2 0 5 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0 0x1016c 2 0 5 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0 0x10170 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0 0x10171 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0 0x10172 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0 0x10173 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0 0x10174 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0 0x10175 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0 0x10176 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0 0x10177 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0 0x10178 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0 0x1017c 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0 0x1017d 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0 0x1017e 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0 0x1017f 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0 0x10180 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0 0x10181 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0 0x10182 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0 0x10183 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0 0x10184 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0 0x10188 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0 0x10189 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0 0x1018a 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0 0x1018b 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0 0x1018c 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0 0x1018d 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0 0x1018e 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0 0x1018f 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0 0x10190 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0 0x10194 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0 0x10195 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0 0x10196 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0 0x10197 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0 0x10198 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0 0x10199 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0 0x1019a 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0 0x1019b 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0 0x1019c 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0 0x10400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0 0x10400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF1_0_COMMAND 0 0x10401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF1_0_STATUS 0 0x10401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0 0x10402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0 0x10402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0 0x10402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0 0x10402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0 0x10403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF1_0_LATENCY 0 0x10403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF1_0_HEADER 0 0x10403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF1_0_BIST 0 0x10403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0 0x10404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0 0x10405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0 0x10406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0 0x10407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0 0x10408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0 0x10409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0 0x1040a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0 0x1040b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0 0x1040c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0 0x1040d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0 0x1040f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0 0x1040f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0 0x1040f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0 0x1040f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0 0x10412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0 0x10413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0 0x10414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0 0x10414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0 0x10415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0 0x10419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0 0x10419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0 0x1041a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0 0x1041b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0 0x1041b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0 0x1041c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0 0x1041d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0 0x1041d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0 0x10422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0 0x10423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0 0x10423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0 0x10424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0 0x10425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0 0x10425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0 0x10428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0 0x10428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0 0x10429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0 0x1042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0 0x1042a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0 0x1042a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0 0x1042b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0 0x1042b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0 0x1042b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0 0x1042c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0 0x1042c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0 0x1042d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0 0x10430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0 0x10430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0 0x10431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0 0x10432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x10440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x10441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0 0x10442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0 0x10443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0 0x10444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0 0x10445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0 0x10446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0 0x10447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0 0x10447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0 0x10448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0 0x10449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0 0x1044a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0 0x1044b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0 0x1044c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0 0x1044d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x10450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x10451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x10452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x10454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0 0x10455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0 0x10456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0 0x10457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0 0x10458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0 0x10459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0 0x1045b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0 0x1045c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0 0x1045d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0 0x1045e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0 0x10462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0 0x10463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0 0x10464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0 0x10465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0 0x10480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0 0x10481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0 0x10482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0 0x10483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0 0x10484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0 0x10485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0 0x10486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0 0x10487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0 0x10488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0 0x10489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0 0x1048a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0 0x1048b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0 0x1048c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x10490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x10491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0 0x10492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0 0x10493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0 0x10494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0 0x10495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0 0x10496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0 0x10497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0 0x10497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x10498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x10498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x10498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x10498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x10499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x10499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x10499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x10499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x1049c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0 0x1049d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0 0x1049e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x1049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x1049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x104a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x104a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x104a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x104a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x104a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x104a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x104a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x104a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x104a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x104a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x104a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x104a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x104a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x104a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0 0x104a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0 0x104a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0 0x104a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0 0x104ac 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0 0x104ad 3 0 5 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 regBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0 0x104ad 2 0 5 STU 0 4 ATC_ENABLE 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0 0x104b0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0 0x104b1 2 0 5 PRI_ENABLE 0 0 PRI_RESET 1 1 regBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0 0x104b1 4 0 5 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0x104b2 1 0 5 OUTSTAND_PAGE_REQ_CAPACITY 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0x104b3 1 0 5 OUTSTAND_PAGE_REQ_ALLOC 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0 0x104b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0 0x104b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0 0x104b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0 0x104bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0 0x104bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0 0x104bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0 0x104be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0 0x104bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0 0x104c0 1 0 5 MC_RECEIVE_0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0 0x104c1 1 0 5 MC_RECEIVE_1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0 0x104c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0 0x104c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x104c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x104c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0 0x104c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0 0x104c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0 0x104ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0 0x104cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0 0x104cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0 0x104cc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0 0x104cd 4 0 5 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0 0x104ce 6 0 5 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0 0x104ce 1 0 5 SRIOV_VF_MIGRATION_STATUS 0 0 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0 0x104cf 1 0 5 SRIOV_INITIAL_VFS 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0 0x104cf 1 0 5 SRIOV_TOTAL_VFS 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0 0x104d0 1 0 5 SRIOV_NUM_VFS 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0 0x104d0 1 0 5 SRIOV_FUNC_DEP_LINK 0 7 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0 0x104d1 1 0 5 SRIOV_FIRST_VF_OFFSET 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0 0x104d1 1 0 5 SRIOV_VF_STRIDE 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0 0x104d2 1 0 5 SRIOV_VF_DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0 0x104d3 1 0 5 SRIOV_SUPPORTED_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0 0x104d4 1 0 5 SRIOV_SYSTEM_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0 0x104d5 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0 0x104d6 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0 0x104d7 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0 0x104d8 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0 0x104d9 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0 0x104da 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0x104db 2 0 5 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x104dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0 0x104dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0 0x104de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0 0x10500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0 0x10501 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0 0x10502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x10504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0 0x10505 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0 0x10506 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0 0x10507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x10508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x10509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x1050a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x1050c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x1050c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x1050c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x1050c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x1050d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x1050d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x1050d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x1050d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x1050e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x1050e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x1050e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x1050e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x1050f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x1050f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x1050f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x1050f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x10510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0 0x10511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0 0x10511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0 0x10512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0 0x10512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0 0x10513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0 0x10513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0 0x10514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0 0x10514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0 0x10515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0 0x10515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0 0x10516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0 0x10516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0 0x10517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0 0x10517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0 0x10518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0 0x10518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0 0x10519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0 0x10519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0 0x1051a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0 0x1051a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0 0x1051b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0 0x1051b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0 0x1051c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0 0x1051c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0 0x1051d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0 0x1051d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0 0x1051e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0 0x1051e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0 0x1051f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0 0x1051f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0 0x10520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0 0x10520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0 0x10521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0 0x10521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0 0x10530 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0 0x10531 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0 0x10532 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0 0x10533 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0 0x10534 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0 0x10535 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0 0x10536 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0 0x10537 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0 0x10538 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0 0x10539 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0 0x1053a 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0 0x1053b 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0 0x1053c 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0 0x10540 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0 0x10541 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0 0x10542 2 0 5 VF_EN 0 0 VF_NUM 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0 0x10543 18 0 5 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0 0x10544 18 0 5 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0 0x10545 1 0 5 SOFT_PF_FLR 0 0 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0 0x10546 5 0 5 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0 0x10547 32 0 5 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0 0x10548 32 0 5 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0 0x10549 3 0 5 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0 0x1054a 2 0 5 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0 0x1054b 3 0 5 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0 0x1054c 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0 0x1054d 2 0 5 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0 0x1054e 2 0 5 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0 0x1054f 2 0 5 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0 0x10550 2 0 5 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0 0x10551 2 0 5 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0 0x10552 2 0 5 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0 0x10553 2 0 5 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0 0x10554 2 0 5 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0 0x10555 2 0 5 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0 0x10556 2 0 5 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0 0x10557 2 0 5 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0 0x10558 2 0 5 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0 0x10559 2 0 5 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0 0x1055a 2 0 5 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0 0x1055b 2 0 5 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0 0x1055c 2 0 5 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0 0x1055d 2 0 5 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0 0x1055e 2 0 5 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0 0x1055f 2 0 5 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0 0x10560 2 0 5 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0 0x10561 2 0 5 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0 0x10562 2 0 5 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0 0x10563 2 0 5 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0 0x10564 2 0 5 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0 0x10565 2 0 5 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0 0x10566 2 0 5 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0 0x10567 2 0 5 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0 0x10568 2 0 5 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0 0x10569 2 0 5 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0 0x1056a 2 0 5 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0 0x1056b 2 0 5 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0 0x1056c 2 0 5 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0 0x10570 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0 0x10571 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0 0x10572 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0 0x10573 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0 0x10574 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0 0x10575 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0 0x10576 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0 0x10577 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0 0x10578 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0 0x1057c 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0 0x1057d 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0 0x1057e 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0 0x1057f 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0 0x10580 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0 0x10581 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0 0x10582 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0 0x10583 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0 0x10584 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0 0x10588 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0 0x10589 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0 0x1058a 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0 0x1058b 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0 0x1058c 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0 0x1058d 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0 0x1058e 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0 0x1058f 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0 0x10590 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0 0x10594 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0 0x10595 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0 0x10596 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0 0x10597 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0 0x10598 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0 0x10599 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0 0x1059a 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0 0x1059b 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0 0x1059c 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0 0x10800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0 0x10800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF2_0_COMMAND 0 0x10801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF2_0_STATUS 0 0x10801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF2_0_REVISION_ID 0 0x10802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0 0x10802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0 0x10802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0 0x10802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0 0x10803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF2_0_LATENCY 0 0x10803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF2_0_HEADER 0 0x10803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF2_0_BIST 0 0x10803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0 0x10804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0 0x10805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0 0x10806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0 0x10807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0 0x10808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0 0x10809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0 0x1080a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0 0x1080b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0 0x1080c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_0_CAP_PTR 0 0x1080d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0 0x1080f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0 0x1080f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0 0x1080f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0 0x1080f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0 0x10812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0 0x10813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0 0x10814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_0_PMI_CAP 0 0x10814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0 0x10815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF2_0_SBRN 0 0x10818 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF2_0_FLADJ 0 0x10818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0 0x10818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0 0x10819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0 0x10819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0 0x1081a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0 0x1081b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0 0x1081b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF2_0_LINK_CAP 0 0x1081c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0 0x1081d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0 0x1081d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0 0x10822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0 0x10823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0 0x10823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0 0x10824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0 0x10825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0 0x10825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0 0x10828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0 0x10828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0 0x10829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0 0x1082a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0 0x1082a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA 0 0x1082a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF2_0_MSI_MASK 0 0x1082b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0 0x1082b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64 0 0x1082b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0 0x1082c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0 0x1082c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0 0x1082d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0 0x10830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0 0x10830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0 0x10831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0 0x10832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x10840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x10841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0 0x10842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0 0x10843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x10854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0 0x10855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0 0x10856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0 0x10857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0 0x10858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0 0x10859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1085a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0 0x1085b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0 0x1085c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0 0x1085d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0 0x1085e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0 0x10862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0 0x10863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0 0x10864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0 0x10865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0 0x10880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0 0x10881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0 0x10882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0 0x10883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0 0x10884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0 0x10885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0 0x10886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0 0x10887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0 0x10888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0 0x10889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0 0x1088a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0 0x1088b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0 0x1088c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x10890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x10891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0 0x10892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0 0x10893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0 0x10894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0 0x10895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0 0x10896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0 0x10897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0 0x10897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x10898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x10898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x10898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x10898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x10899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x10899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x10899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x10899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0 0x108a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0 0x108a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0 0x108a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0 0x108b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0 0x108b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0 0x108b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0 0x108ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0 0x108cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0 0x108cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x108dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP 0 0x108dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL 0 0x108de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0 0 0x108df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1 0 0x108df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2 0 0x108e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3 0 0x108e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4 0 0x108e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5 0 0x108e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6 0 0x108e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7 0 0x108e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8 0 0x108e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9 0 0x108e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10 0 0x108e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11 0 0x108e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12 0 0x108e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13 0 0x108e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14 0 0x108e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15 0 0x108e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16 0 0x108e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17 0 0x108e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18 0 0x108e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19 0 0x108e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20 0 0x108e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21 0 0x108e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22 0 0x108ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23 0 0x108ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24 0 0x108eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25 0 0x108eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26 0 0x108ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27 0 0x108ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28 0 0x108ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29 0 0x108ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30 0 0x108ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31 0 0x108ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32 0 0x108ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33 0 0x108ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34 0 0x108f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35 0 0x108f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36 0 0x108f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37 0 0x108f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38 0 0x108f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39 0 0x108f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40 0 0x108f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41 0 0x108f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42 0 0x108f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43 0 0x108f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44 0 0x108f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45 0 0x108f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46 0 0x108f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47 0 0x108f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48 0 0x108f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49 0 0x108f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50 0 0x108f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51 0 0x108f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52 0 0x108f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53 0 0x108f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54 0 0x108fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55 0 0x108fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56 0 0x108fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57 0 0x108fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58 0 0x108fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59 0 0x108fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60 0 0x108fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61 0 0x108fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62 0 0x108fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63 0 0x108fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0 0x10c00 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0 0x10c00 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF3_0_COMMAND 0 0x10c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF3_0_STATUS 0 0x10c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF3_0_REVISION_ID 0 0x10c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0 0x10c02 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0 0x10c02 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0 0x10c02 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0 0x10c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF3_0_LATENCY 0 0x10c03 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF3_0_HEADER 0 0x10c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF3_0_BIST 0 0x10c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0 0x10c04 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0 0x10c05 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0 0x10c06 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0 0x10c07 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0 0x10c08 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0 0x10c09 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0 0x10c0a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0 0x10c0b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0 0x10c0c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_0_CAP_PTR 0 0x10c0d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0 0x10c0f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0 0x10c0f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0 0x10c0f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0 0x10c0f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0 0x10c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0 0x10c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0 0x10c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_0_PMI_CAP 0 0x10c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0 0x10c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF3_0_SBRN 0 0x10c18 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF3_0_FLADJ 0 0x10c18 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0 0x10c18 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0 0x10c19 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0 0x10c19 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0 0x10c1a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0 0x10c1b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0 0x10c1b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF3_0_LINK_CAP 0 0x10c1c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0 0x10c1d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0 0x10c1d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0 0x10c22 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0 0x10c23 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0 0x10c23 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0 0x10c24 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0 0x10c25 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0 0x10c25 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0 0x10c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0 0x10c28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0 0x10c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0 0x10c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0 0x10c2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA 0 0x10c2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF3_0_MSI_MASK 0 0x10c2b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0 0x10c2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64 0 0x10c2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0 0x10c2c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0 0x10c2c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0 0x10c2d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0 0x10c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0 0x10c30 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0 0x10c31 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0 0x10c32 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x10c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x10c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0 0x10c42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0 0x10c43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x10c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0 0x10c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0 0x10c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0 0x10c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0 0x10c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0 0x10c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0 0x10c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0 0x10c5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0 0x10c5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0 0x10c5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0 0x10c5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0 0x10c62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0 0x10c63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0 0x10c64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0 0x10c65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0 0x10c80 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0 0x10c81 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0 0x10c82 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0 0x10c83 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0 0x10c84 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0 0x10c85 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0 0x10c86 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0 0x10c87 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0 0x10c88 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0 0x10c89 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0 0x10c8a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0 0x10c8b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0 0x10c8c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x10c90 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x10c91 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0 0x10c92 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0 0x10c93 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0 0x10c94 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0 0x10c95 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0 0x10c96 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0 0x10c97 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0 0x10c97 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x10c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x10c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x10c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x10c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x10c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x10c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x10c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x10c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0 0x10ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0 0x10ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0 0x10ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0 0x10cb4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0 0x10cb5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0 0x10cb5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0 0x10cca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0 0x10ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0 0x10ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x10cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP 0 0x10cdd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL 0 0x10cde 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0 0 0x10cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1 0 0x10cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2 0 0x10ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3 0 0x10ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4 0 0x10ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5 0 0x10ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6 0 0x10ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7 0 0x10ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8 0 0x10ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9 0 0x10ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10 0 0x10ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11 0 0x10ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12 0 0x10ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13 0 0x10ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14 0 0x10ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15 0 0x10ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16 0 0x10ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17 0 0x10ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18 0 0x10ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19 0 0x10ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20 0 0x10ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21 0 0x10ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22 0 0x10cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23 0 0x10cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24 0 0x10ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25 0 0x10ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26 0 0x10cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27 0 0x10cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28 0 0x10ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29 0 0x10ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30 0 0x10cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31 0 0x10cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32 0 0x10cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33 0 0x10cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34 0 0x10cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35 0 0x10cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36 0 0x10cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37 0 0x10cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38 0 0x10cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39 0 0x10cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40 0 0x10cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41 0 0x10cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42 0 0x10cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43 0 0x10cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44 0 0x10cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45 0 0x10cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46 0 0x10cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47 0 0x10cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48 0 0x10cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49 0 0x10cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50 0 0x10cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51 0 0x10cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52 0 0x10cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53 0 0x10cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54 0 0x10cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55 0 0x10cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56 0 0x10cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57 0 0x10cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58 0 0x10cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59 0 0x10cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60 0 0x10cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61 0 0x10cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62 0 0x10cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63 0 0x10cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_VENDOR_ID 0 0x11000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF4_0_DEVICE_ID 0 0x11000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF4_0_COMMAND 0 0x11001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF4_0_STATUS 0 0x11001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF4_0_REVISION_ID 0 0x11002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE 0 0x11002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF4_0_SUB_CLASS 0 0x11002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF4_0_BASE_CLASS 0 0x11002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF4_0_CACHE_LINE 0 0x11003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF4_0_LATENCY 0 0x11003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF4_0_HEADER 0 0x11003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF4_0_BIST 0 0x11003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 0 0x11004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 0 0x11005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 0 0x11006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 0 0x11007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 0 0x11008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 0 0x11009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR 0 0x1100a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID 0 0x1100b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR 0 0x1100c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_0_CAP_PTR 0 0x1100d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE 0 0x1100f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN 0 0x1100f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF4_0_MIN_GRANT 0 0x1100f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF4_0_MAX_LATENCY 0 0x1100f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST 0 0x11012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W 0 0x11013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST 0 0x11014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_0_PMI_CAP 0 0x11014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL 0 0x11015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF4_0_SBRN 0 0x11018 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF4_0_FLADJ 0 0x11018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD 0 0x11018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST 0 0x11019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_CAP 0 0x11019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP 0 0x1101a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL 0 0x1101b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS 0 0x1101b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF4_0_LINK_CAP 0 0x1101c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF4_0_LINK_CNTL 0 0x1101d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF4_0_LINK_STATUS 0 0x1101d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 0 0x11022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 0 0x11023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 0 0x11023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF4_0_LINK_CAP2 0 0x11024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF4_0_LINK_CNTL2 0 0x11025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF4_0_LINK_STATUS2 0 0x11025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST 0 0x11028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL 0 0x11028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO 0 0x11029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI 0 0x1102a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA 0 0x1102a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA 0 0x1102a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF4_0_MSI_MASK 0 0x1102b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 0 0x1102b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64 0 0x1102b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF4_0_MSI_MASK_64 0 0x1102c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF4_0_MSI_PENDING 0 0x1102c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 0 0x1102d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST 0 0x11030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL 0 0x11030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF4_0_MSIX_TABLE 0 0x11031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF4_0_MSIX_PBA 0 0x11032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x11040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x11041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 0 0x11042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 0 0x11043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x11054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS 0 0x11055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK 0 0x11056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY 0 0x11057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS 0 0x11058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK 0 0x11059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1105a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 0 0x1105b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 0 0x1105c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 0 0x1105d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 0 0x1105e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 0 0x11062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 0 0x11063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 0 0x11064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 0 0x11065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST 0 0x11080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP 0 0x11081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL 0 0x11082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP 0 0x11083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL 0 0x11084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP 0 0x11085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL 0 0x11086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP 0 0x11087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL 0 0x11088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP 0 0x11089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL 0 0x1108a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP 0 0x1108b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL 0 0x1108c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x11090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x11091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA 0 0x11092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP 0 0x11093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST 0 0x11094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP 0 0x11095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR 0 0x11096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS 0 0x11097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL 0 0x11097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x11098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x11098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x11098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x11098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x11099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x11099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x11099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x11099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST 0 0x110a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP 0 0x110a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL 0 0x110a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST 0 0x110b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP 0 0x110b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL 0 0x110b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST 0 0x110ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP 0 0x110cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL 0 0x110cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x110dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP 0 0x110dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL 0 0x110de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0 0 0x110df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1 0 0x110df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2 0 0x110e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3 0 0x110e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4 0 0x110e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5 0 0x110e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6 0 0x110e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7 0 0x110e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8 0 0x110e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9 0 0x110e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10 0 0x110e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11 0 0x110e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12 0 0x110e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13 0 0x110e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14 0 0x110e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15 0 0x110e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16 0 0x110e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17 0 0x110e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18 0 0x110e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19 0 0x110e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20 0 0x110e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21 0 0x110e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22 0 0x110ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23 0 0x110ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24 0 0x110eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25 0 0x110eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26 0 0x110ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27 0 0x110ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28 0 0x110ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29 0 0x110ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30 0 0x110ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31 0 0x110ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32 0 0x110ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33 0 0x110ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34 0 0x110f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35 0 0x110f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36 0 0x110f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37 0 0x110f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38 0 0x110f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39 0 0x110f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40 0 0x110f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41 0 0x110f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42 0 0x110f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43 0 0x110f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44 0 0x110f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45 0 0x110f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46 0 0x110f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47 0 0x110f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48 0 0x110f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49 0 0x110f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50 0 0x110f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51 0 0x110f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52 0 0x110f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53 0 0x110f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54 0 0x110fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55 0 0x110fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56 0 0x110fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57 0 0x110fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58 0 0x110fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59 0 0x110fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60 0 0x110fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61 0 0x110fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62 0 0x110fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63 0 0x110fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_VENDOR_ID 0 0x11400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF5_0_DEVICE_ID 0 0x11400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF5_0_COMMAND 0 0x11401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF5_0_STATUS 0 0x11401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF5_0_REVISION_ID 0 0x11402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE 0 0x11402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF5_0_SUB_CLASS 0 0x11402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF5_0_BASE_CLASS 0 0x11402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF5_0_CACHE_LINE 0 0x11403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF5_0_LATENCY 0 0x11403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF5_0_HEADER 0 0x11403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF5_0_BIST 0 0x11403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 0 0x11404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 0 0x11405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 0 0x11406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 0 0x11407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 0 0x11408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 0 0x11409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR 0 0x1140a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID 0 0x1140b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR 0 0x1140c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_0_CAP_PTR 0 0x1140d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE 0 0x1140f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN 0 0x1140f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF5_0_MIN_GRANT 0 0x1140f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF5_0_MAX_LATENCY 0 0x1140f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST 0 0x11412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W 0 0x11413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST 0 0x11414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_0_PMI_CAP 0 0x11414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL 0 0x11415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF5_0_SBRN 0 0x11418 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF5_0_FLADJ 0 0x11418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD 0 0x11418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST 0 0x11419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_CAP 0 0x11419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP 0 0x1141a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL 0 0x1141b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS 0 0x1141b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF5_0_LINK_CAP 0 0x1141c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF5_0_LINK_CNTL 0 0x1141d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF5_0_LINK_STATUS 0 0x1141d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 0 0x11422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 0 0x11423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 0 0x11423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF5_0_LINK_CAP2 0 0x11424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF5_0_LINK_CNTL2 0 0x11425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF5_0_LINK_STATUS2 0 0x11425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST 0 0x11428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL 0 0x11428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO 0 0x11429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI 0 0x1142a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA 0 0x1142a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA 0 0x1142a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF5_0_MSI_MASK 0 0x1142b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 0 0x1142b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64 0 0x1142b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF5_0_MSI_MASK_64 0 0x1142c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF5_0_MSI_PENDING 0 0x1142c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 0 0x1142d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST 0 0x11430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL 0 0x11430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF5_0_MSIX_TABLE 0 0x11431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF5_0_MSIX_PBA 0 0x11432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x11440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x11441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 0 0x11442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 0 0x11443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x11454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS 0 0x11455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK 0 0x11456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY 0 0x11457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS 0 0x11458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK 0 0x11459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1145a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 0 0x1145b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 0 0x1145c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 0 0x1145d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 0 0x1145e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 0 0x11462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 0 0x11463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 0 0x11464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 0 0x11465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST 0 0x11480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP 0 0x11481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL 0 0x11482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP 0 0x11483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL 0 0x11484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP 0 0x11485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL 0 0x11486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP 0 0x11487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL 0 0x11488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP 0 0x11489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL 0 0x1148a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP 0 0x1148b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL 0 0x1148c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x11490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x11491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA 0 0x11492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP 0 0x11493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST 0 0x11494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP 0 0x11495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR 0 0x11496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS 0 0x11497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL 0 0x11497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x11498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x11498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x11498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x11498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x11499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x11499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x11499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x11499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST 0 0x114a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP 0 0x114a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL 0 0x114a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST 0 0x114b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP 0 0x114b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL 0 0x114b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST 0 0x114ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP 0 0x114cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL 0 0x114cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x114dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP 0 0x114dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL 0 0x114de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0 0 0x114df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1 0 0x114df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2 0 0x114e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3 0 0x114e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4 0 0x114e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5 0 0x114e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6 0 0x114e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7 0 0x114e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8 0 0x114e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9 0 0x114e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10 0 0x114e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11 0 0x114e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12 0 0x114e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13 0 0x114e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14 0 0x114e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15 0 0x114e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16 0 0x114e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17 0 0x114e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18 0 0x114e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19 0 0x114e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20 0 0x114e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21 0 0x114e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22 0 0x114ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23 0 0x114ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24 0 0x114eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25 0 0x114eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26 0 0x114ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27 0 0x114ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28 0 0x114ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29 0 0x114ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30 0 0x114ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31 0 0x114ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32 0 0x114ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33 0 0x114ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34 0 0x114f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35 0 0x114f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36 0 0x114f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37 0 0x114f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38 0 0x114f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39 0 0x114f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40 0 0x114f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41 0 0x114f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42 0 0x114f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43 0 0x114f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44 0 0x114f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45 0 0x114f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46 0 0x114f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47 0 0x114f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48 0 0x114f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49 0 0x114f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50 0 0x114f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51 0 0x114f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52 0 0x114f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53 0 0x114f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54 0 0x114fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55 0 0x114fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56 0 0x114fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57 0 0x114fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58 0 0x114fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59 0 0x114fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60 0 0x114fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61 0 0x114fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62 0 0x114fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63 0 0x114fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_VENDOR_ID 0 0x11800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF6_0_DEVICE_ID 0 0x11800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF6_0_COMMAND 0 0x11801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF6_0_STATUS 0 0x11801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF6_0_REVISION_ID 0 0x11802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE 0 0x11802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF6_0_SUB_CLASS 0 0x11802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF6_0_BASE_CLASS 0 0x11802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF6_0_CACHE_LINE 0 0x11803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF6_0_LATENCY 0 0x11803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF6_0_HEADER 0 0x11803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF6_0_BIST 0 0x11803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 0 0x11804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 0 0x11805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 0 0x11806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 0 0x11807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 0 0x11808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 0 0x11809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR 0 0x1180a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID 0 0x1180b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR 0 0x1180c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_0_CAP_PTR 0 0x1180d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE 0 0x1180f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN 0 0x1180f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF6_0_MIN_GRANT 0 0x1180f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF6_0_MAX_LATENCY 0 0x1180f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST 0 0x11812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W 0 0x11813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST 0 0x11814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_0_PMI_CAP 0 0x11814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL 0 0x11815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF6_0_SBRN 0 0x11818 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF6_0_FLADJ 0 0x11818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD 0 0x11818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST 0 0x11819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_CAP 0 0x11819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP 0 0x1181a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL 0 0x1181b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS 0 0x1181b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF6_0_LINK_CAP 0 0x1181c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF6_0_LINK_CNTL 0 0x1181d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF6_0_LINK_STATUS 0 0x1181d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 0 0x11822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 0 0x11823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 0 0x11823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF6_0_LINK_CAP2 0 0x11824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF6_0_LINK_CNTL2 0 0x11825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF6_0_LINK_STATUS2 0 0x11825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST 0 0x11828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL 0 0x11828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO 0 0x11829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI 0 0x1182a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA 0 0x1182a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA 0 0x1182a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF6_0_MSI_MASK 0 0x1182b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 0 0x1182b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64 0 0x1182b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF6_0_MSI_MASK_64 0 0x1182c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF6_0_MSI_PENDING 0 0x1182c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 0 0x1182d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST 0 0x11830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL 0 0x11830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF6_0_MSIX_TABLE 0 0x11831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF6_0_MSIX_PBA 0 0x11832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x11840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x11841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 0 0x11842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 0 0x11843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x11854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS 0 0x11855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK 0 0x11856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY 0 0x11857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS 0 0x11858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK 0 0x11859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1185a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 0 0x1185b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 0 0x1185c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 0 0x1185d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 0 0x1185e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 0 0x11862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 0 0x11863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 0 0x11864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 0 0x11865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST 0 0x11880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP 0 0x11881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL 0 0x11882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP 0 0x11883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL 0 0x11884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP 0 0x11885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL 0 0x11886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP 0 0x11887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL 0 0x11888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP 0 0x11889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL 0 0x1188a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP 0 0x1188b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL 0 0x1188c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x11890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x11891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA 0 0x11892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP 0 0x11893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST 0 0x11894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP 0 0x11895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR 0 0x11896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS 0 0x11897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL 0 0x11897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x11898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x11898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x11898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x11898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x11899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x11899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x11899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x11899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST 0 0x118a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP 0 0x118a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL 0 0x118a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST 0 0x118b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP 0 0x118b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL 0 0x118b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST 0 0x118ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP 0 0x118cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL 0 0x118cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x118dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP 0 0x118dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL 0 0x118de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0 0 0x118df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1 0 0x118df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2 0 0x118e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3 0 0x118e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4 0 0x118e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5 0 0x118e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6 0 0x118e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7 0 0x118e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8 0 0x118e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9 0 0x118e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10 0 0x118e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11 0 0x118e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12 0 0x118e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13 0 0x118e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14 0 0x118e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15 0 0x118e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16 0 0x118e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17 0 0x118e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18 0 0x118e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19 0 0x118e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20 0 0x118e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21 0 0x118e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22 0 0x118ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23 0 0x118ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24 0 0x118eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25 0 0x118eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26 0 0x118ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27 0 0x118ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28 0 0x118ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29 0 0x118ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30 0 0x118ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31 0 0x118ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32 0 0x118ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33 0 0x118ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34 0 0x118f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35 0 0x118f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36 0 0x118f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37 0 0x118f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38 0 0x118f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39 0 0x118f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40 0 0x118f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41 0 0x118f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42 0 0x118f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43 0 0x118f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44 0 0x118f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45 0 0x118f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46 0 0x118f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47 0 0x118f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48 0 0x118f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49 0 0x118f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50 0 0x118f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51 0 0x118f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52 0 0x118f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53 0 0x118f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54 0 0x118fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55 0 0x118fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56 0 0x118fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57 0 0x118fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58 0 0x118fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59 0 0x118fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60 0 0x118fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61 0 0x118fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62 0 0x118fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63 0 0x118fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_VENDOR_ID 0 0x11c00 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF7_0_DEVICE_ID 0 0x11c00 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF7_0_COMMAND 0 0x11c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF7_0_STATUS 0 0x11c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF7_0_REVISION_ID 0 0x11c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE 0 0x11c02 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF7_0_SUB_CLASS 0 0x11c02 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF7_0_BASE_CLASS 0 0x11c02 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF7_0_CACHE_LINE 0 0x11c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF7_0_LATENCY 0 0x11c03 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF7_0_HEADER 0 0x11c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF7_0_BIST 0 0x11c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 0 0x11c04 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 0 0x11c05 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 0 0x11c06 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 0 0x11c07 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 0 0x11c08 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 0 0x11c09 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR 0 0x11c0a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID 0 0x11c0b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR 0 0x11c0c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_0_CAP_PTR 0 0x11c0d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE 0 0x11c0f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN 0 0x11c0f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF7_0_MIN_GRANT 0 0x11c0f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF7_0_MAX_LATENCY 0 0x11c0f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST 0 0x11c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W 0 0x11c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST 0 0x11c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_0_PMI_CAP 0 0x11c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL 0 0x11c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF7_0_SBRN 0 0x11c18 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF7_0_FLADJ 0 0x11c18 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD 0 0x11c18 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST 0 0x11c19 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_CAP 0 0x11c19 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP 0 0x11c1a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL 0 0x11c1b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS 0 0x11c1b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF7_0_LINK_CAP 0 0x11c1c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF7_0_LINK_CNTL 0 0x11c1d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF7_0_LINK_STATUS 0 0x11c1d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 0 0x11c22 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 0 0x11c23 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 0 0x11c23 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF7_0_LINK_CAP2 0 0x11c24 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF7_0_LINK_CNTL2 0 0x11c25 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF7_0_LINK_STATUS2 0 0x11c25 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST 0 0x11c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL 0 0x11c28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO 0 0x11c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI 0 0x11c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA 0 0x11c2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA 0 0x11c2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF7_0_MSI_MASK 0 0x11c2b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 0 0x11c2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64 0 0x11c2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF7_0_MSI_MASK_64 0 0x11c2c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF7_0_MSI_PENDING 0 0x11c2c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 0 0x11c2d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST 0 0x11c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL 0 0x11c30 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF7_0_MSIX_TABLE 0 0x11c31 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF7_0_MSIX_PBA 0 0x11c32 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x11c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x11c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 0 0x11c42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 0 0x11c43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x11c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS 0 0x11c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK 0 0x11c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY 0 0x11c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS 0 0x11c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK 0 0x11c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL 0 0x11c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 0 0x11c5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 0 0x11c5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 0 0x11c5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 0 0x11c5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 0 0x11c62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 0 0x11c63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 0 0x11c64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 0 0x11c65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST 0 0x11c80 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP 0 0x11c81 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL 0 0x11c82 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP 0 0x11c83 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL 0 0x11c84 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP 0 0x11c85 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL 0 0x11c86 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP 0 0x11c87 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL 0 0x11c88 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP 0 0x11c89 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL 0 0x11c8a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP 0 0x11c8b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL 0 0x11c8c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x11c90 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x11c91 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA 0 0x11c92 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP 0 0x11c93 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST 0 0x11c94 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP 0 0x11c95 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR 0 0x11c96 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS 0 0x11c97 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL 0 0x11c97 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x11c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x11c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x11c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x11c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x11c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x11c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x11c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x11c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST 0 0x11ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP 0 0x11ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL 0 0x11ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST 0 0x11cb4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP 0 0x11cb5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL 0 0x11cb5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST 0 0x11cca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP 0 0x11ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL 0 0x11ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x11cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP 0 0x11cdd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL 0 0x11cde 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0 0 0x11cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1 0 0x11cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2 0 0x11ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3 0 0x11ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4 0 0x11ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5 0 0x11ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6 0 0x11ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7 0 0x11ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8 0 0x11ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9 0 0x11ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10 0 0x11ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11 0 0x11ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12 0 0x11ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13 0 0x11ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14 0 0x11ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15 0 0x11ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16 0 0x11ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17 0 0x11ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18 0 0x11ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19 0 0x11ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20 0 0x11ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21 0 0x11ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22 0 0x11cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23 0 0x11cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24 0 0x11ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25 0 0x11ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26 0 0x11cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27 0 0x11cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28 0 0x11ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29 0 0x11ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30 0 0x11cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31 0 0x11cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32 0 0x11cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33 0 0x11cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34 0 0x11cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35 0 0x11cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36 0 0x11cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37 0 0x11cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38 0 0x11cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39 0 0x11cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40 0 0x11cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41 0 0x11cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42 0 0x11cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43 0 0x11cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44 0 0x11cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45 0 0x11cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46 0 0x11cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47 0 0x11cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48 0 0x11cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49 0 0x11cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50 0 0x11cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51 0 0x11cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52 0 0x11cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53 0 0x11cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54 0 0x11cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55 0 0x11cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56 0 0x11cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57 0 0x11cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58 0 0x11cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59 0 0x11cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60 0 0x11cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61 0 0x11cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62 0 0x11cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63 0 0x11cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_VENDOR_ID 0 0x12000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_EPF0_0_DEVICE_ID 0 0x12000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_EPF0_0_COMMAND 0 0x12001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_EPF0_0_STATUS 0 0x12001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_EPF0_0_REVISION_ID 0 0x12002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE 0 0x12002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_EPF0_0_SUB_CLASS 0 0x12002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_EPF0_0_BASE_CLASS 0 0x12002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_EPF0_0_CACHE_LINE 0 0x12003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_EPF0_0_LATENCY 0 0x12003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_EPF0_0_HEADER 0 0x12003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_EPF0_0_BIST 0 0x12003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 0 0x12004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 0 0x12005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 0 0x12006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 0 0x12007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 0 0x12008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 0 0x12009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR 0 0x1200a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID 0 0x1200b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR 0 0x1200c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_0_CAP_PTR 0 0x1200d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE 0 0x1200f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN 0 0x1200f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_EPF0_0_MIN_GRANT 0 0x1200f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV1_EPF0_0_MAX_LATENCY 0 0x1200f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST 0 0x12012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W 0 0x12013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST 0 0x12014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_0_PMI_CAP 0 0x12014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL 0 0x12015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_EPF0_0_SBRN 0 0x12018 1 0 5 SBRN 0 7 regBIF_CFG_DEV1_EPF0_0_FLADJ 0 0x12018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV1_EPF0_0_DBESL_DBESLD 0 0x12018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST 0 0x12019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_CAP 0 0x12019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP 0 0x1201a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL 0 0x1201b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS 0 0x1201b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_EPF0_0_LINK_CAP 0 0x1201c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_EPF0_0_LINK_CNTL 0 0x1201d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_EPF0_0_LINK_STATUS 0 0x1201d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 0 0x12022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 0 0x12023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 0 0x12023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_EPF0_0_LINK_CAP2 0 0x12024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF0_0_LINK_CNTL2 0 0x12025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_EPF0_0_LINK_STATUS2 0 0x12025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST 0 0x12028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL 0 0x12028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO 0 0x12029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI 0 0x1202a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA 0 0x1202a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA 0 0x1202a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_EPF0_0_MSI_MASK 0 0x1202b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 0 0x1202b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64 0 0x1202b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_EPF0_0_MSI_MASK_64 0 0x1202c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV1_EPF0_0_MSI_PENDING 0 0x1202c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 0 0x1202d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST 0 0x12030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL 0 0x12030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV1_EPF0_0_MSIX_TABLE 0 0x12031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV1_EPF0_0_MSIX_PBA 0 0x12032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x12040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x12041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 0 0x12042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 0 0x12043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST 0 0x12044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 0 0x12045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 0 0x12046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL 0 0x12047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS 0 0x12047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP 0 0x12048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0 0x12049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0 0x1204a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP 0 0x1204b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0 0x1204c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0 0x1204d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x12054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS 0 0x12055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK 0 0x12056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0 0x12057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS 0 0x12058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK 0 0x12059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1205a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 0 0x1205b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 0 0x1205c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 0 0x1205d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 0 0x1205e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 0 0x12062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 0 0x12063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 0 0x12064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 0 0x12065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0 0x12080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP 0 0x12081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL 0 0x12082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP 0 0x12083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL 0 0x12084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP 0 0x12085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL 0 0x12086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP 0 0x12087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL 0 0x12088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP 0 0x12089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL 0 0x1208a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP 0 0x1208b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL 0 0x1208c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x12090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x12091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA 0 0x12092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP 0 0x12093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0 0x12094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP 0 0x12095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0 0x12096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS 0 0x12097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL 0 0x12097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x12098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x12098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x12098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x12098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x12099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x12099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x12099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x12099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x1209c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 0 0x1209d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS 0 0x1209e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x1209f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x1209f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x120a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x120a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x120a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x120a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x120a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x120a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x120a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x120a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x120a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x120a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x120a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x120a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x120a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x120a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0 0x120a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP 0 0x120a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL 0 0x120a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0 0x120b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP 0 0x120b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL 0 0x120b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0 0x120c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP 0 0x120c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0 0x120ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP 0 0x120cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL 0 0x120cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x120dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP 0 0x120dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL 0 0x120de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0 0 0x120df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1 0 0x120df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2 0 0x120e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3 0 0x120e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4 0 0x120e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5 0 0x120e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6 0 0x120e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7 0 0x120e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8 0 0x120e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9 0 0x120e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10 0 0x120e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11 0 0x120e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12 0 0x120e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13 0 0x120e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14 0 0x120e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15 0 0x120e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16 0 0x120e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17 0 0x120e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18 0 0x120e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19 0 0x120e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20 0 0x120e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21 0 0x120e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22 0 0x120ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23 0 0x120ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24 0 0x120eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25 0 0x120eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26 0 0x120ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27 0 0x120ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28 0 0x120ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29 0 0x120ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30 0 0x120ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31 0 0x120ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32 0 0x120ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33 0 0x120ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34 0 0x120f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35 0 0x120f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36 0 0x120f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37 0 0x120f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38 0 0x120f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39 0 0x120f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40 0 0x120f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41 0 0x120f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42 0 0x120f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43 0 0x120f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44 0 0x120f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45 0 0x120f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46 0 0x120f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47 0 0x120f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48 0 0x120f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49 0 0x120f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50 0 0x120f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51 0 0x120f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52 0 0x120f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53 0 0x120f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54 0 0x120fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55 0 0x120fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56 0 0x120fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57 0 0x120fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58 0 0x120fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59 0 0x120fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60 0 0x120fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61 0 0x120fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62 0 0x120fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63 0 0x120fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0 0x12100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP 0 0x12101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS 0 0x12102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x12104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT 0 0x12105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT 0 0x12106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT 0 0x12107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x12108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x12109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x1210a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x1210c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x1210c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x1210c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x1210c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x1210d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x1210d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x1210d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x1210d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x1210e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x1210e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x1210e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x1210e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x1210f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x1210f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x1210f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x1210f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x12110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP 0 0x12111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS 0 0x12111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0 0x12112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0 0x12112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0 0x12113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0 0x12113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0 0x12114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0 0x12114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0 0x12115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0 0x12115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0 0x12116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0 0x12116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0 0x12117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0 0x12117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0 0x12118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0 0x12118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0 0x12119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0 0x12119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0 0x1211a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0 0x1211a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0 0x1211b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0 0x1211b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0 0x1211c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0 0x1211c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0 0x1211d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0 0x1211d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0 0x1211e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0 0x1211e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0 0x1211f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0 0x1211f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0 0x12120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0 0x12120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0 0x12121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0 0x12121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF1_0_VENDOR_ID 0 0x12400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_EPF1_0_DEVICE_ID 0 0x12400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_EPF1_0_COMMAND 0 0x12401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_EPF1_0_STATUS 0 0x12401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_EPF1_0_REVISION_ID 0 0x12402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE 0 0x12402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_EPF1_0_SUB_CLASS 0 0x12402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_EPF1_0_BASE_CLASS 0 0x12402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_EPF1_0_CACHE_LINE 0 0x12403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_EPF1_0_LATENCY 0 0x12403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_EPF1_0_HEADER 0 0x12403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_EPF1_0_BIST 0 0x12403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 0 0x12404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 0 0x12405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 0 0x12406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 0 0x12407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 0 0x12408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 0 0x12409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR 0 0x1240a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID 0 0x1240b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR 0 0x1240c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_0_CAP_PTR 0 0x1240d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE 0 0x1240f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN 0 0x1240f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_EPF1_0_MIN_GRANT 0 0x1240f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV1_EPF1_0_MAX_LATENCY 0 0x1240f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST 0 0x12412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W 0 0x12413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST 0 0x12414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_0_PMI_CAP 0 0x12414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL 0 0x12415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_EPF1_0_SBRN 0 0x12418 1 0 5 SBRN 0 7 regBIF_CFG_DEV1_EPF1_0_FLADJ 0 0x12418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD 0 0x12418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST 0 0x12419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_CAP 0 0x12419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP 0 0x1241a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL 0 0x1241b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS 0 0x1241b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_EPF1_0_LINK_CAP 0 0x1241c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_EPF1_0_LINK_CNTL 0 0x1241d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_EPF1_0_LINK_STATUS 0 0x1241d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 0 0x12422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 0 0x12423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 0 0x12423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_EPF1_0_LINK_CAP2 0 0x12424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF1_0_LINK_CNTL2 0 0x12425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_EPF1_0_LINK_STATUS2 0 0x12425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST 0 0x12428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL 0 0x12428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO 0 0x12429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI 0 0x1242a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA 0 0x1242a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA 0 0x1242a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_EPF1_0_MSI_MASK 0 0x1242b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 0 0x1242b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64 0 0x1242b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_EPF1_0_MSI_MASK_64 0 0x1242c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV1_EPF1_0_MSI_PENDING 0 0x1242c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 0 0x1242d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST 0 0x12430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL 0 0x12430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV1_EPF1_0_MSIX_TABLE 0 0x12431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV1_EPF1_0_MSIX_PBA 0 0x12432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x12440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x12441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 0 0x12442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 0 0x12443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x12454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS 0 0x12455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK 0 0x12456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0 0x12457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS 0 0x12458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK 0 0x12459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1245a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 0 0x1245b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 0 0x1245c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 0 0x1245d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 0 0x1245e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 0 0x12462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 0 0x12463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 0 0x12464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 0 0x12465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0 0x12480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP 0 0x12481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL 0 0x12482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP 0 0x12483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL 0 0x12484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP 0 0x12485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL 0 0x12486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP 0 0x12487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL 0 0x12488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP 0 0x12489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL 0 0x1248a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP 0 0x1248b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL 0 0x1248c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x12490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x12491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA 0 0x12492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP 0 0x12493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0 0x12494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP 0 0x12495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0 0x12496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS 0 0x12497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL 0 0x12497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x12498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x12498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x12498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x12498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x12499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x12499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x12499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x12499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0 0x124a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP 0 0x124a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL 0 0x124a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0 0x124b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP 0 0x124b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL 0 0x124b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0 0x124ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP 0 0x124cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL 0 0x124cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x124dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP 0 0x124dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL 0 0x124de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0 0 0x124df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1 0 0x124df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2 0 0x124e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3 0 0x124e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4 0 0x124e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5 0 0x124e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6 0 0x124e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7 0 0x124e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8 0 0x124e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9 0 0x124e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10 0 0x124e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11 0 0x124e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12 0 0x124e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13 0 0x124e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14 0 0x124e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15 0 0x124e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16 0 0x124e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17 0 0x124e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18 0 0x124e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19 0 0x124e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20 0 0x124e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21 0 0x124e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22 0 0x124ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23 0 0x124ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24 0 0x124eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25 0 0x124eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26 0 0x124ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27 0 0x124ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28 0 0x124ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29 0 0x124ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30 0 0x124ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31 0 0x124ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32 0 0x124ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33 0 0x124ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34 0 0x124f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35 0 0x124f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36 0 0x124f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37 0 0x124f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38 0 0x124f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39 0 0x124f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40 0 0x124f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41 0 0x124f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42 0 0x124f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43 0 0x124f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44 0 0x124f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45 0 0x124f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46 0 0x124f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47 0 0x124f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48 0 0x124f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49 0 0x124f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50 0 0x124f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51 0 0x124f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52 0 0x124f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53 0 0x124f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54 0 0x124fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55 0 0x124fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56 0 0x124fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57 0 0x124fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58 0 0x124fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59 0 0x124fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60 0 0x124fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61 0 0x124fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62 0 0x124fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63 0 0x124fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_VENDOR_ID 0 0x14000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF0_0_DEVICE_ID 0 0x14000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF0_0_COMMAND 0 0x14001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF0_0_STATUS 0 0x14001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF0_0_REVISION_ID 0 0x14002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF0_0_PROG_INTERFACE 0 0x14002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF0_0_SUB_CLASS 0 0x14002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF0_0_BASE_CLASS 0 0x14002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF0_0_CACHE_LINE 0 0x14003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF0_0_LATENCY 0 0x14003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF0_0_HEADER 0 0x14003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF0_0_BIST 0 0x14003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_1 0 0x14004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_2 0 0x14005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_3 0 0x14006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_4 0 0x14007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_5 0 0x14008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_BASE_ADDR_6 0 0x14009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR 0 0x1400a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID 0 0x1400b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR 0 0x1400c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_0_CAP_PTR 0 0x1400d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE 0 0x1400f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN 0 0x1400f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF0_0_MIN_GRANT 0 0x1400f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF0_0_MAX_LATENCY 0 0x1400f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST 0 0x14012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W 0 0x14013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST 0 0x14014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_0_PMI_CAP 0 0x14014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL 0 0x14015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF0_0_SBRN 0 0x14018 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF0_0_FLADJ 0 0x14018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF0_0_DBESL_DBESLD 0 0x14018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST 0 0x14019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_CAP 0 0x14019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP 0 0x1401a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL 0 0x1401b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS 0 0x1401b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF0_0_LINK_CAP 0 0x1401c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF0_0_LINK_CNTL 0 0x1401d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF0_0_LINK_STATUS 0 0x1401d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF0_0_DEVICE_CAP2 0 0x14022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2 0 0x14023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2 0 0x14023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF0_0_LINK_CAP2 0 0x14024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF0_0_LINK_CNTL2 0 0x14025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF0_0_LINK_STATUS2 0 0x14025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST 0 0x14028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL 0 0x14028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO 0 0x14029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI 0 0x1402a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA 0 0x1402a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA 0 0x1402a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF0_0_MSI_MASK 0 0x1402b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64 0 0x1402b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64 0 0x1402b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF0_0_MSI_MASK_64 0 0x1402c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF0_0_MSI_PENDING 0 0x1402c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF0_0_MSI_PENDING_64 0 0x1402d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST 0 0x14030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL 0 0x14030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF0_0_MSIX_TABLE 0 0x14031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF0_0_MSIX_PBA 0 0x14032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x14040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x14041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1 0 0x14042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2 0 0x14043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST 0 0x14044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1 0 0x14045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2 0 0x14046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL 0 0x14047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS 0 0x14047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP 0 0x14048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0 0x14049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0 0x1404a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP 0 0x1404b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0 0x1404c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0 0x1404d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x14054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS 0 0x14055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK 0 0x14056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0 0x14057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS 0 0x14058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK 0 0x14059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1405a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0 0 0x1405b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1 0 0x1405c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2 0 0x1405d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3 0 0x1405e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0 0 0x14062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1 0 0x14063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2 0 0x14064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3 0 0x14065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0 0x14080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP 0 0x14081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL 0 0x14082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP 0 0x14083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL 0 0x14084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP 0 0x14085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL 0 0x14086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP 0 0x14087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL 0 0x14088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP 0 0x14089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL 0 0x1408a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP 0 0x1408b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL 0 0x1408c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x14090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x14091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA 0 0x14092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP 0 0x14093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0 0x14094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP 0 0x14095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0 0x14096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS 0 0x14097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL 0 0x14097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x14098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x14098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x14098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x14098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x14099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x14099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x14099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x14099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x1409c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3 0 0x1409d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS 0 0x1409e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x1409f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x1409f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x140a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x140a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x140a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x140a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x140a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x140a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x140a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x140a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x140a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x140a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x140a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x140a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x140a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x140a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0 0x140a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP 0 0x140a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL 0 0x140a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0 0x140b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP 0 0x140b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL 0 0x140b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0 0x140c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP 0 0x140c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0 0x140ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP 0 0x140cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL 0 0x140cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x140dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP 0 0x140dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL 0 0x140de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0 0 0x140df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1 0 0x140df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2 0 0x140e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3 0 0x140e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4 0 0x140e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5 0 0x140e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6 0 0x140e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7 0 0x140e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8 0 0x140e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9 0 0x140e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10 0 0x140e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11 0 0x140e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12 0 0x140e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13 0 0x140e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14 0 0x140e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15 0 0x140e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16 0 0x140e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17 0 0x140e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18 0 0x140e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19 0 0x140e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20 0 0x140e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21 0 0x140e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22 0 0x140ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23 0 0x140ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24 0 0x140eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25 0 0x140eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26 0 0x140ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27 0 0x140ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28 0 0x140ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29 0 0x140ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30 0 0x140ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31 0 0x140ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32 0 0x140ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33 0 0x140ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34 0 0x140f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35 0 0x140f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36 0 0x140f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37 0 0x140f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38 0 0x140f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39 0 0x140f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40 0 0x140f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41 0 0x140f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42 0 0x140f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43 0 0x140f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44 0 0x140f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45 0 0x140f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46 0 0x140f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47 0 0x140f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48 0 0x140f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49 0 0x140f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50 0 0x140f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51 0 0x140f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52 0 0x140f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53 0 0x140f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54 0 0x140fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55 0 0x140fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56 0 0x140fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57 0 0x140fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58 0 0x140fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59 0 0x140fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60 0 0x140fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61 0 0x140fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62 0 0x140fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63 0 0x140fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0 0x14100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP 0 0x14101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS 0 0x14102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x14104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT 0 0x14105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT 0 0x14106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT 0 0x14107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x14108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x14109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x1410a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x1410c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x1410c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x1410c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x1410c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x1410d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x1410d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x1410d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x1410d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x1410e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x1410e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x1410e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x1410e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x1410f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x1410f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x1410f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x1410f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x14110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP 0 0x14111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS 0 0x14111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0 0x14112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0 0x14112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0 0x14113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0 0x14113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0 0x14114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0 0x14114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0 0x14115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0 0x14115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0 0x14116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0 0x14116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0 0x14117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0 0x14117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0 0x14118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0 0x14118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0 0x14119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0 0x14119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0 0x1411a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0 0x1411a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0 0x1411b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0 0x1411b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0 0x1411c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0 0x1411c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0 0x1411d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0 0x1411d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0 0x1411e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0 0x1411e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0 0x1411f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0 0x1411f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0 0x14120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0 0x14120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0 0x14121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0 0x14121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF1_0_VENDOR_ID 0 0x14400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF1_0_DEVICE_ID 0 0x14400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF1_0_COMMAND 0 0x14401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF1_0_STATUS 0 0x14401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF1_0_REVISION_ID 0 0x14402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF1_0_PROG_INTERFACE 0 0x14402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF1_0_SUB_CLASS 0 0x14402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF1_0_BASE_CLASS 0 0x14402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF1_0_CACHE_LINE 0 0x14403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF1_0_LATENCY 0 0x14403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF1_0_HEADER 0 0x14403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF1_0_BIST 0 0x14403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_1 0 0x14404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_2 0 0x14405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_3 0 0x14406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_4 0 0x14407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_5 0 0x14408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_BASE_ADDR_6 0 0x14409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR 0 0x1440a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID 0 0x1440b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR 0 0x1440c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_0_CAP_PTR 0 0x1440d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE 0 0x1440f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN 0 0x1440f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF1_0_MIN_GRANT 0 0x1440f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF1_0_MAX_LATENCY 0 0x1440f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST 0 0x14412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W 0 0x14413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST 0 0x14414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_0_PMI_CAP 0 0x14414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL 0 0x14415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF1_0_SBRN 0 0x14418 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF1_0_FLADJ 0 0x14418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF1_0_DBESL_DBESLD 0 0x14418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST 0 0x14419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_CAP 0 0x14419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP 0 0x1441a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL 0 0x1441b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS 0 0x1441b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF1_0_LINK_CAP 0 0x1441c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF1_0_LINK_CNTL 0 0x1441d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF1_0_LINK_STATUS 0 0x1441d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF1_0_DEVICE_CAP2 0 0x14422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2 0 0x14423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2 0 0x14423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF1_0_LINK_CAP2 0 0x14424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF1_0_LINK_CNTL2 0 0x14425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF1_0_LINK_STATUS2 0 0x14425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST 0 0x14428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL 0 0x14428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO 0 0x14429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI 0 0x1442a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA 0 0x1442a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA 0 0x1442a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF1_0_MSI_MASK 0 0x1442b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64 0 0x1442b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64 0 0x1442b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF1_0_MSI_MASK_64 0 0x1442c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF1_0_MSI_PENDING 0 0x1442c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF1_0_MSI_PENDING_64 0 0x1442d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST 0 0x14430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL 0 0x14430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF1_0_MSIX_TABLE 0 0x14431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF1_0_MSIX_PBA 0 0x14432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x14440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x14441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1 0 0x14442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2 0 0x14443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x14454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS 0 0x14455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK 0 0x14456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0 0x14457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS 0 0x14458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK 0 0x14459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1445a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0 0 0x1445b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1 0 0x1445c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2 0 0x1445d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3 0 0x1445e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0 0 0x14462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1 0 0x14463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2 0 0x14464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3 0 0x14465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0 0x14480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP 0 0x14481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL 0 0x14482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP 0 0x14483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL 0 0x14484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP 0 0x14485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL 0 0x14486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP 0 0x14487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL 0 0x14488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP 0 0x14489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL 0 0x1448a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP 0 0x1448b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL 0 0x1448c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x14490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x14491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA 0 0x14492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP 0 0x14493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0 0x14494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP 0 0x14495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0 0x14496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS 0 0x14497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL 0 0x14497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x14498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x14498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x14498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x14498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x14499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x14499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x14499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x14499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0 0x144a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP 0 0x144a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL 0 0x144a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0 0x144b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP 0 0x144b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL 0 0x144b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0 0x144ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP 0 0x144cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL 0 0x144cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x144dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP 0 0x144dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL 0 0x144de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0 0 0x144df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1 0 0x144df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2 0 0x144e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3 0 0x144e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4 0 0x144e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5 0 0x144e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6 0 0x144e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7 0 0x144e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8 0 0x144e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9 0 0x144e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10 0 0x144e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11 0 0x144e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12 0 0x144e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13 0 0x144e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14 0 0x144e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15 0 0x144e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16 0 0x144e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17 0 0x144e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18 0 0x144e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19 0 0x144e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20 0 0x144e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21 0 0x144e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22 0 0x144ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23 0 0x144ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24 0 0x144eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25 0 0x144eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26 0 0x144ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27 0 0x144ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28 0 0x144ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29 0 0x144ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30 0 0x144ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31 0 0x144ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32 0 0x144ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33 0 0x144ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34 0 0x144f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35 0 0x144f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36 0 0x144f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37 0 0x144f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38 0 0x144f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39 0 0x144f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40 0 0x144f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41 0 0x144f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42 0 0x144f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43 0 0x144f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44 0 0x144f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45 0 0x144f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46 0 0x144f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47 0 0x144f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48 0 0x144f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49 0 0x144f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50 0 0x144f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51 0 0x144f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52 0 0x144f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53 0 0x144f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54 0 0x144fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55 0 0x144fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56 0 0x144fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57 0 0x144fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58 0 0x144fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59 0 0x144fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60 0 0x144fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61 0 0x144fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62 0 0x144fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63 0 0x144fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_VENDOR_ID 0 0x14800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF2_0_DEVICE_ID 0 0x14800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF2_0_COMMAND 0 0x14801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF2_0_STATUS 0 0x14801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF2_0_REVISION_ID 0 0x14802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF2_0_PROG_INTERFACE 0 0x14802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF2_0_SUB_CLASS 0 0x14802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF2_0_BASE_CLASS 0 0x14802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF2_0_CACHE_LINE 0 0x14803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF2_0_LATENCY 0 0x14803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF2_0_HEADER 0 0x14803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF2_0_BIST 0 0x14803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_1 0 0x14804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_2 0 0x14805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_3 0 0x14806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_4 0 0x14807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_5 0 0x14808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_BASE_ADDR_6 0 0x14809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR 0 0x1480a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID 0 0x1480b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR 0 0x1480c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_0_CAP_PTR 0 0x1480d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE 0 0x1480f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN 0 0x1480f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF2_0_MIN_GRANT 0 0x1480f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF2_0_MAX_LATENCY 0 0x1480f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST 0 0x14812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W 0 0x14813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST 0 0x14814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_0_PMI_CAP 0 0x14814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL 0 0x14815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF2_0_SBRN 0 0x14818 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF2_0_FLADJ 0 0x14818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF2_0_DBESL_DBESLD 0 0x14818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST 0 0x14819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_CAP 0 0x14819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP 0 0x1481a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL 0 0x1481b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS 0 0x1481b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF2_0_LINK_CAP 0 0x1481c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF2_0_LINK_CNTL 0 0x1481d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF2_0_LINK_STATUS 0 0x1481d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF2_0_DEVICE_CAP2 0 0x14822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2 0 0x14823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2 0 0x14823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF2_0_LINK_CAP2 0 0x14824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF2_0_LINK_CNTL2 0 0x14825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF2_0_LINK_STATUS2 0 0x14825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST 0 0x14828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL 0 0x14828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO 0 0x14829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI 0 0x1482a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA 0 0x1482a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA 0 0x1482a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF2_0_MSI_MASK 0 0x1482b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64 0 0x1482b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64 0 0x1482b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF2_0_MSI_MASK_64 0 0x1482c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF2_0_MSI_PENDING 0 0x1482c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF2_0_MSI_PENDING_64 0 0x1482d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST 0 0x14830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL 0 0x14830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF2_0_MSIX_TABLE 0 0x14831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF2_0_MSIX_PBA 0 0x14832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x14840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x14841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1 0 0x14842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2 0 0x14843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x14854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS 0 0x14855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK 0 0x14856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0 0x14857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS 0 0x14858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK 0 0x14859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0 0x1485a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0 0 0x1485b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1 0 0x1485c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2 0 0x1485d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3 0 0x1485e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0 0 0x14862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1 0 0x14863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2 0 0x14864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3 0 0x14865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0 0x14880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP 0 0x14881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL 0 0x14882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP 0 0x14883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL 0 0x14884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP 0 0x14885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL 0 0x14886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP 0 0x14887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL 0 0x14888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP 0 0x14889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL 0 0x1488a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP 0 0x1488b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL 0 0x1488c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x14890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0 0x14891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA 0 0x14892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP 0 0x14893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0 0x14894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP 0 0x14895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0 0x14896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS 0 0x14897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL 0 0x14897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x14898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x14898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x14898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x14898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x14899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x14899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x14899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x14899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0 0x148a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP 0 0x148a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL 0 0x148a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0 0x148b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP 0 0x148b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL 0 0x148b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0 0x148ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP 0 0x148cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL 0 0x148cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x148dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP 0 0x148dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL 0 0x148de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0 0 0x148df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1 0 0x148df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2 0 0x148e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3 0 0x148e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4 0 0x148e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5 0 0x148e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6 0 0x148e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7 0 0x148e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8 0 0x148e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9 0 0x148e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10 0 0x148e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11 0 0x148e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12 0 0x148e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13 0 0x148e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14 0 0x148e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15 0 0x148e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16 0 0x148e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17 0 0x148e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18 0 0x148e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19 0 0x148e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20 0 0x148e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21 0 0x148e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22 0 0x148ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23 0 0x148ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24 0 0x148eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25 0 0x148eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26 0 0x148ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27 0 0x148ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28 0 0x148ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29 0 0x148ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30 0 0x148ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31 0 0x148ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32 0 0x148ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33 0 0x148ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34 0 0x148f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35 0 0x148f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36 0 0x148f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37 0 0x148f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38 0 0x148f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39 0 0x148f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40 0 0x148f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41 0 0x148f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42 0 0x148f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43 0 0x148f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44 0 0x148f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45 0 0x148f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46 0 0x148f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47 0 0x148f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48 0 0x148f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49 0 0x148f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50 0 0x148f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51 0 0x148f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52 0 0x148f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53 0 0x148f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54 0 0x148fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55 0 0x148fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56 0 0x148fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57 0 0x148fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58 0 0x148fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59 0 0x148fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60 0 0x148fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61 0 0x148fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62 0 0x148fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63 0 0x148fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIFPLR0_0_VENDOR_ID 0 0x400000 1 0 5 VENDOR_ID 0 15 regBIFPLR0_0_DEVICE_ID 0 0x400000 1 0 5 DEVICE_ID 0 15 regBIFPLR0_0_COMMAND 0 0x400001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR0_0_STATUS 0 0x400001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR0_0_REVISION_ID 0 0x400002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR0_0_PROG_INTERFACE 0 0x400002 1 0 5 PROG_INTERFACE 0 7 regBIFPLR0_0_SUB_CLASS 0 0x400002 1 0 5 SUB_CLASS 0 7 regBIFPLR0_0_BASE_CLASS 0 0x400002 1 0 5 BASE_CLASS 0 7 regBIFPLR0_0_CACHE_LINE 0 0x400003 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR0_0_LATENCY 0 0x400003 1 0 5 LATENCY_TIMER 0 7 regBIFPLR0_0_HEADER 0 0x400003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR0_0_BIST 0 0x400003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR0_0_SUB_BUS_NUMBER_LATENCY 0 0x400006 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR0_0_IO_BASE_LIMIT 0 0x400007 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR0_0_SECONDARY_STATUS 0 0x400007 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR0_0_MEM_BASE_LIMIT 0 0x400008 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR0_0_PREF_BASE_LIMIT 0 0x400009 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR0_0_PREF_BASE_UPPER 0 0x40000a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR0_0_PREF_LIMIT_UPPER 0 0x40000b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR0_0_IO_BASE_LIMIT_HI 0 0x40000c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR0_0_CAP_PTR 0 0x40000d 1 0 5 CAP_PTR 0 7 regBIFPLR0_0_ROM_BASE_ADDR 0 0x40000e 1 0 5 BASE_ADDR 0 31 regBIFPLR0_0_INTERRUPT_LINE 0 0x40000f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR0_0_INTERRUPT_PIN 0 0x40000f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR0_0_IRQ_BRIDGE_CNTL 0 0x40000f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR0_0_EXT_BRIDGE_CNTL 0 0x400010 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR0_0_VENDOR_CAP_LIST 0 0x400012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR0_0_ADAPTER_ID_W 0 0x400013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR0_0_PMI_CAP_LIST 0 0x400014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_0_PMI_CAP 0 0x400014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR0_0_PMI_STATUS_CNTL 0 0x400015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR0_0_PCIE_CAP_LIST 0 0x400016 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_0_PCIE_CAP 0 0x400016 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR0_0_DEVICE_CAP 0 0x400017 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR0_0_DEVICE_CNTL 0 0x400018 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR0_0_DEVICE_STATUS 0 0x400018 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR0_0_LINK_CAP 0 0x400019 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR0_0_LINK_CNTL 0 0x40001a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR0_0_LINK_STATUS 0 0x40001a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR0_0_SLOT_CAP 0 0x40001b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR0_0_SLOT_CNTL 0 0x40001c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR0_0_SLOT_STATUS 0 0x40001c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR0_0_ROOT_CNTL 0 0x40001d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR0_0_ROOT_CAP 0 0x40001d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR0_0_ROOT_STATUS 0 0x40001e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR0_0_DEVICE_CAP2 0 0x40001f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR0_0_DEVICE_CNTL2 0 0x400020 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR0_0_DEVICE_STATUS2 0 0x400020 1 0 5 RESERVED 0 15 regBIFPLR0_0_LINK_CAP2 0 0x400021 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR0_0_LINK_CNTL2 0 0x400022 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR0_0_LINK_STATUS2 0 0x400022 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR0_0_SLOT_CAP2 0 0x400023 1 0 5 RESERVED 0 31 regBIFPLR0_0_SLOT_CNTL2 0 0x400024 1 0 5 RESERVED 0 15 regBIFPLR0_0_SLOT_STATUS2 0 0x400024 1 0 5 RESERVED 0 15 regBIFPLR0_0_MSI_CAP_LIST 0 0x400028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_0_MSI_MSG_CNTL 0 0x400028 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR0_0_MSI_MSG_ADDR_LO 0 0x400029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR0_0_MSI_MSG_ADDR_HI 0 0x40002a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR0_0_MSI_MSG_DATA 0 0x40002a 1 0 5 MSI_DATA 0 15 regBIFPLR0_0_MSI_MSG_DATA_64 0 0x40002b 1 0 5 MSI_DATA_64 0 15 regBIFPLR0_0_SSID_CAP_LIST 0 0x400030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_0_SSID_CAP 0 0x400031 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR0_0_MSI_MAP_CAP_LIST 0 0x400032 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_0_MSI_MAP_CAP 0 0x400032 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x400040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x400041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR0_0_PCIE_VENDOR_SPECIFIC1 0 0x400042 1 0 5 SCRATCH 0 31 regBIFPLR0_0_PCIE_VENDOR_SPECIFIC2 0 0x400043 1 0 5 SCRATCH 0 31 regBIFPLR0_0_PCIE_VC_ENH_CAP_LIST 0 0x400044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_PORT_VC_CAP_REG1 0 0x400045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR0_0_PCIE_PORT_VC_CAP_REG2 0 0x400046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR0_0_PCIE_PORT_VC_CNTL 0 0x400047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR0_0_PCIE_PORT_VC_STATUS 0 0x400047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR0_0_PCIE_VC0_RESOURCE_CAP 0 0x400048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL 0 0x400049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS 0 0x40004a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR0_0_PCIE_VC1_RESOURCE_CAP 0 0x40004b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL 0 0x40004c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS 0 0x40004d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x400050 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x400051 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x400052 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x400054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_UNCORR_ERR_STATUS 0 0x400055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR0_0_PCIE_UNCORR_ERR_MASK 0 0x400056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY 0 0x400057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR0_0_PCIE_CORR_ERR_STATUS 0 0x400058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR0_0_PCIE_CORR_ERR_MASK 0 0x400059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40005a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR0_0_PCIE_HDR_LOG0 0 0x40005b 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_HDR_LOG1 0 0x40005c 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_HDR_LOG2 0 0x40005d 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_HDR_LOG3 0 0x40005e 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_ROOT_ERR_CMD 0 0x40005f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR0_0_PCIE_ROOT_ERR_STATUS 0 0x400060 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR0_0_PCIE_ERR_SRC_ID 0 0x400061 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR0_0_PCIE_TLP_PREFIX_LOG0 0 0x400062 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_TLP_PREFIX_LOG1 0 0x400063 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_TLP_PREFIX_LOG2 0 0x400064 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_TLP_PREFIX_LOG3 0 0x400065 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40009c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_LINK_CNTL3 0 0x40009d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR0_0_PCIE_LANE_ERROR_STATUS 0 0x40009e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40009f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40009f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4000a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4000a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4000a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4000a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4000a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4000a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4000a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4000a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4000a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4000a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4000a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4000a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4000a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4000a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST 0 0x4000a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_ACS_CAP 0 0x4000a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR0_0_PCIE_ACS_CNTL 0 0x4000a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR0_0_PCIE_MC_ENH_CAP_LIST 0 0x4000bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_MC_CAP 0 0x4000bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR0_0_PCIE_MC_CNTL 0 0x4000bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR0_0_PCIE_MC_ADDR0 0 0x4000be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR0_0_PCIE_MC_ADDR1 0 0x4000bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR0_0_PCIE_MC_RCV0 0 0x4000c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR0_0_PCIE_MC_RCV1 0 0x4000c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR0_0_PCIE_MC_BLOCK_ALL0 0 0x4000c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR0_0_PCIE_MC_BLOCK_ALL1 0 0x4000c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4000c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4000c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR0_0_PCIE_MC_OVERLAY_BAR0 0 0x4000c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR0_0_PCIE_MC_OVERLAY_BAR1 0 0x4000c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4000dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_L1_PM_SUB_CAP 0 0x4000dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL 0 0x4000de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 0 0x4000df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST 0 0x4000e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_DPC_CAP_LIST 0 0x4000e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR0_0_PCIE_DPC_CNTL 0 0x4000e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR0_0_PCIE_DPC_STATUS 0 0x4000e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4000e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR0_0_PCIE_RP_PIO_STATUS 0 0x4000e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_0_PCIE_RP_PIO_MASK 0 0x4000e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_0_PCIE_RP_PIO_SEVERITY 0 0x4000e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_0_PCIE_RP_PIO_SYSERROR 0 0x4000e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_0_PCIE_RP_PIO_EXCEPTION 0 0x4000e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 0 0x4000e8 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 0 0x4000e9 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 0 0x4000ea 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 0 0x4000eb 1 0 5 TLP_HDR 0 31 regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4000ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4000ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4000ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4000f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_0_PCIE_ESM_CAP_LIST 0 0x4000f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_ESM_HEADER_1 0 0x4000f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR0_0_PCIE_ESM_HEADER_2 0 0x4000f3 1 0 5 CAP_ID 0 15 regBIFPLR0_0_PCIE_ESM_STATUS 0 0x4000f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR0_0_PCIE_ESM_CTRL 0 0x4000f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR0_0_PCIE_ESM_CAP_1 0 0x4000f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR0_0_PCIE_ESM_CAP_2 0 0x4000f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR0_0_PCIE_ESM_CAP_3 0 0x4000f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR0_0_PCIE_ESM_CAP_4 0 0x4000f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR0_0_PCIE_ESM_CAP_5 0 0x4000f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR0_0_PCIE_ESM_CAP_6 0 0x4000fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR0_0_PCIE_ESM_CAP_7 0 0x4000fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR0_0_PCIE_DLF_ENH_CAP_LIST 0 0x400100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_DATA_LINK_FEATURE_CAP 0 0x400101 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR0_0_DATA_LINK_FEATURE_STATUS 0 0x400102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x400104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_LINK_CAP_16GT 0 0x400105 1 0 5 RESERVED 0 31 regBIFPLR0_0_LINK_CNTL_16GT 0 0x400106 1 0 5 RESERVED 0 31 regBIFPLR0_0_LINK_STATUS_16GT 0 0x400107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x400108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x400109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40010a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40010c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40010c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40010c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40010c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40010d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40010d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40010d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40010d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40010e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40010e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40010e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40010e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40010f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40010f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40010f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40010f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x400110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_MARGINING_PORT_CAP 0 0x400111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR0_0_MARGINING_PORT_STATUS 0 0x400111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR0_0_LANE_0_MARGINING_LANE_CNTL 0 0x400112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_0_MARGINING_LANE_STATUS 0 0x400112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_1_MARGINING_LANE_CNTL 0 0x400113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_1_MARGINING_LANE_STATUS 0 0x400113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_2_MARGINING_LANE_CNTL 0 0x400114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_2_MARGINING_LANE_STATUS 0 0x400114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_3_MARGINING_LANE_CNTL 0 0x400115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_3_MARGINING_LANE_STATUS 0 0x400115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_4_MARGINING_LANE_CNTL 0 0x400116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_4_MARGINING_LANE_STATUS 0 0x400116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_5_MARGINING_LANE_CNTL 0 0x400117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_5_MARGINING_LANE_STATUS 0 0x400117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_6_MARGINING_LANE_CNTL 0 0x400118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_6_MARGINING_LANE_STATUS 0 0x400118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_7_MARGINING_LANE_CNTL 0 0x400119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_7_MARGINING_LANE_STATUS 0 0x400119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_8_MARGINING_LANE_CNTL 0 0x40011a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_8_MARGINING_LANE_STATUS 0 0x40011a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_9_MARGINING_LANE_CNTL 0 0x40011b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_9_MARGINING_LANE_STATUS 0 0x40011b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_10_MARGINING_LANE_CNTL 0 0x40011c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_10_MARGINING_LANE_STATUS 0 0x40011c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_11_MARGINING_LANE_CNTL 0 0x40011d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_11_MARGINING_LANE_STATUS 0 0x40011d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_12_MARGINING_LANE_CNTL 0 0x40011e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_12_MARGINING_LANE_STATUS 0 0x40011e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_13_MARGINING_LANE_CNTL 0 0x40011f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_13_MARGINING_LANE_STATUS 0 0x40011f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_14_MARGINING_LANE_CNTL 0 0x400120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_14_MARGINING_LANE_STATUS 0 0x400120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_LANE_15_MARGINING_LANE_CNTL 0 0x400121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR0_0_LANE_15_MARGINING_LANE_STATUS 0 0x400121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_0_PCIE_CCIX_CAP_LIST 0 0x400122 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_0_PCIE_CCIX_HEADER_1 0 0x400123 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR0_0_PCIE_CCIX_HEADER_2 0 0x400124 1 0 5 CAP_ID 0 15 regBIFPLR0_0_PCIE_CCIX_CAP 0 0x400124 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP 0 0x400125 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x400126 1 0 5 RESERVED 0 31 regBIFPLR0_0_PCIE_CCIX_ESM_STATUS 0 0x400127 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR0_0_PCIE_CCIX_ESM_CNTL 0 0x400128 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x400129 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x400129 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x400129 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x400129 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40012a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40012a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40012a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40012a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40012b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40012b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40012b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40012b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40012c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40012c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40012c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40012c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40012d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40012d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40012d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40012d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40012e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40012e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40012e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40012e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40012f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40012f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40012f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40012f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x400130 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x400130 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x400130 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x400130 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR0_0_PCIE_CCIX_TRANS_CAP 0 0x400131 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR0_0_PCIE_CCIX_TRANS_CNTL 0 0x400132 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR1_0_VENDOR_ID 0 0x400400 1 0 5 VENDOR_ID 0 15 regBIFPLR1_0_DEVICE_ID 0 0x400400 1 0 5 DEVICE_ID 0 15 regBIFPLR1_0_COMMAND 0 0x400401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR1_0_STATUS 0 0x400401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR1_0_REVISION_ID 0 0x400402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR1_0_PROG_INTERFACE 0 0x400402 1 0 5 PROG_INTERFACE 0 7 regBIFPLR1_0_SUB_CLASS 0 0x400402 1 0 5 SUB_CLASS 0 7 regBIFPLR1_0_BASE_CLASS 0 0x400402 1 0 5 BASE_CLASS 0 7 regBIFPLR1_0_CACHE_LINE 0 0x400403 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR1_0_LATENCY 0 0x400403 1 0 5 LATENCY_TIMER 0 7 regBIFPLR1_0_HEADER 0 0x400403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR1_0_BIST 0 0x400403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR1_0_SUB_BUS_NUMBER_LATENCY 0 0x400406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR1_0_IO_BASE_LIMIT 0 0x400407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR1_0_SECONDARY_STATUS 0 0x400407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR1_0_MEM_BASE_LIMIT 0 0x400408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR1_0_PREF_BASE_LIMIT 0 0x400409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR1_0_PREF_BASE_UPPER 0 0x40040a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR1_0_PREF_LIMIT_UPPER 0 0x40040b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR1_0_IO_BASE_LIMIT_HI 0 0x40040c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR1_0_CAP_PTR 0 0x40040d 1 0 5 CAP_PTR 0 7 regBIFPLR1_0_ROM_BASE_ADDR 0 0x40040e 1 0 5 BASE_ADDR 0 31 regBIFPLR1_0_INTERRUPT_LINE 0 0x40040f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR1_0_INTERRUPT_PIN 0 0x40040f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR1_0_IRQ_BRIDGE_CNTL 0 0x40040f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR1_0_EXT_BRIDGE_CNTL 0 0x400410 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR1_0_VENDOR_CAP_LIST 0 0x400412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR1_0_ADAPTER_ID_W 0 0x400413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR1_0_PMI_CAP_LIST 0 0x400414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_0_PMI_CAP 0 0x400414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR1_0_PMI_STATUS_CNTL 0 0x400415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR1_0_PCIE_CAP_LIST 0 0x400416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_0_PCIE_CAP 0 0x400416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR1_0_DEVICE_CAP 0 0x400417 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR1_0_DEVICE_CNTL 0 0x400418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR1_0_DEVICE_STATUS 0 0x400418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR1_0_LINK_CAP 0 0x400419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR1_0_LINK_CNTL 0 0x40041a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR1_0_LINK_STATUS 0 0x40041a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR1_0_SLOT_CAP 0 0x40041b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR1_0_SLOT_CNTL 0 0x40041c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR1_0_SLOT_STATUS 0 0x40041c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR1_0_ROOT_CNTL 0 0x40041d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR1_0_ROOT_CAP 0 0x40041d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR1_0_ROOT_STATUS 0 0x40041e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR1_0_DEVICE_CAP2 0 0x40041f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR1_0_DEVICE_CNTL2 0 0x400420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR1_0_DEVICE_STATUS2 0 0x400420 1 0 5 RESERVED 0 15 regBIFPLR1_0_LINK_CAP2 0 0x400421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR1_0_LINK_CNTL2 0 0x400422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR1_0_LINK_STATUS2 0 0x400422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR1_0_SLOT_CAP2 0 0x400423 1 0 5 RESERVED 0 31 regBIFPLR1_0_SLOT_CNTL2 0 0x400424 1 0 5 RESERVED 0 15 regBIFPLR1_0_SLOT_STATUS2 0 0x400424 1 0 5 RESERVED 0 15 regBIFPLR1_0_MSI_CAP_LIST 0 0x400428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_0_MSI_MSG_CNTL 0 0x400428 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR1_0_MSI_MSG_ADDR_LO 0 0x400429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR1_0_MSI_MSG_ADDR_HI 0 0x40042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR1_0_MSI_MSG_DATA 0 0x40042a 1 0 5 MSI_DATA 0 15 regBIFPLR1_0_MSI_MSG_DATA_64 0 0x40042b 1 0 5 MSI_DATA_64 0 15 regBIFPLR1_0_SSID_CAP_LIST 0 0x400430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_0_SSID_CAP 0 0x400431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR1_0_MSI_MAP_CAP_LIST 0 0x400432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_0_MSI_MAP_CAP 0 0x400432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x400440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x400441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR1_0_PCIE_VENDOR_SPECIFIC1 0 0x400442 1 0 5 SCRATCH 0 31 regBIFPLR1_0_PCIE_VENDOR_SPECIFIC2 0 0x400443 1 0 5 SCRATCH 0 31 regBIFPLR1_0_PCIE_VC_ENH_CAP_LIST 0 0x400444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_PORT_VC_CAP_REG1 0 0x400445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR1_0_PCIE_PORT_VC_CAP_REG2 0 0x400446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR1_0_PCIE_PORT_VC_CNTL 0 0x400447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR1_0_PCIE_PORT_VC_STATUS 0 0x400447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR1_0_PCIE_VC0_RESOURCE_CAP 0 0x400448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL 0 0x400449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS 0 0x40044a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR1_0_PCIE_VC1_RESOURCE_CAP 0 0x40044b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL 0 0x40044c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS 0 0x40044d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x400450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x400451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x400452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x400454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_UNCORR_ERR_STATUS 0 0x400455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR1_0_PCIE_UNCORR_ERR_MASK 0 0x400456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY 0 0x400457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR1_0_PCIE_CORR_ERR_STATUS 0 0x400458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR1_0_PCIE_CORR_ERR_MASK 0 0x400459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR1_0_PCIE_HDR_LOG0 0 0x40045b 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_HDR_LOG1 0 0x40045c 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_HDR_LOG2 0 0x40045d 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_HDR_LOG3 0 0x40045e 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_ROOT_ERR_CMD 0 0x40045f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR1_0_PCIE_ROOT_ERR_STATUS 0 0x400460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR1_0_PCIE_ERR_SRC_ID 0 0x400461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR1_0_PCIE_TLP_PREFIX_LOG0 0 0x400462 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_TLP_PREFIX_LOG1 0 0x400463 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_TLP_PREFIX_LOG2 0 0x400464 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_TLP_PREFIX_LOG3 0 0x400465 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40049c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_LINK_CNTL3 0 0x40049d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR1_0_PCIE_LANE_ERROR_STATUS 0 0x40049e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40049f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40049f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4004a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4004a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4004a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4004a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4004a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4004a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4004a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4004a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4004a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4004a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4004a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4004a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4004a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4004a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST 0 0x4004a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_ACS_CAP 0 0x4004a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR1_0_PCIE_ACS_CNTL 0 0x4004a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR1_0_PCIE_MC_ENH_CAP_LIST 0 0x4004bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_MC_CAP 0 0x4004bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR1_0_PCIE_MC_CNTL 0 0x4004bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR1_0_PCIE_MC_ADDR0 0 0x4004be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR1_0_PCIE_MC_ADDR1 0 0x4004bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR1_0_PCIE_MC_RCV0 0 0x4004c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR1_0_PCIE_MC_RCV1 0 0x4004c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR1_0_PCIE_MC_BLOCK_ALL0 0 0x4004c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR1_0_PCIE_MC_BLOCK_ALL1 0 0x4004c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4004c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4004c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR1_0_PCIE_MC_OVERLAY_BAR0 0 0x4004c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR1_0_PCIE_MC_OVERLAY_BAR1 0 0x4004c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4004dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_L1_PM_SUB_CAP 0 0x4004dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL 0 0x4004de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 0 0x4004df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST 0 0x4004e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_DPC_CAP_LIST 0 0x4004e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR1_0_PCIE_DPC_CNTL 0 0x4004e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR1_0_PCIE_DPC_STATUS 0 0x4004e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4004e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR1_0_PCIE_RP_PIO_STATUS 0 0x4004e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_0_PCIE_RP_PIO_MASK 0 0x4004e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_0_PCIE_RP_PIO_SEVERITY 0 0x4004e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_0_PCIE_RP_PIO_SYSERROR 0 0x4004e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_0_PCIE_RP_PIO_EXCEPTION 0 0x4004e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 0 0x4004e8 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 0 0x4004e9 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 0 0x4004ea 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 0 0x4004eb 1 0 5 TLP_HDR 0 31 regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4004ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4004ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4004ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4004f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_0_PCIE_ESM_CAP_LIST 0 0x4004f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_ESM_HEADER_1 0 0x4004f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR1_0_PCIE_ESM_HEADER_2 0 0x4004f3 1 0 5 CAP_ID 0 15 regBIFPLR1_0_PCIE_ESM_STATUS 0 0x4004f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR1_0_PCIE_ESM_CTRL 0 0x4004f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR1_0_PCIE_ESM_CAP_1 0 0x4004f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR1_0_PCIE_ESM_CAP_2 0 0x4004f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR1_0_PCIE_ESM_CAP_3 0 0x4004f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR1_0_PCIE_ESM_CAP_4 0 0x4004f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR1_0_PCIE_ESM_CAP_5 0 0x4004f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR1_0_PCIE_ESM_CAP_6 0 0x4004fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR1_0_PCIE_ESM_CAP_7 0 0x4004fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR1_0_PCIE_DLF_ENH_CAP_LIST 0 0x400500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_DATA_LINK_FEATURE_CAP 0 0x400501 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR1_0_DATA_LINK_FEATURE_STATUS 0 0x400502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x400504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_LINK_CAP_16GT 0 0x400505 1 0 5 RESERVED 0 31 regBIFPLR1_0_LINK_CNTL_16GT 0 0x400506 1 0 5 RESERVED 0 31 regBIFPLR1_0_LINK_STATUS_16GT 0 0x400507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x400508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x400509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40050a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40050c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40050c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40050c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40050c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40050d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40050d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40050d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40050d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40050e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40050e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40050e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40050e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40050f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40050f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40050f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40050f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x400510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_MARGINING_PORT_CAP 0 0x400511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR1_0_MARGINING_PORT_STATUS 0 0x400511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR1_0_LANE_0_MARGINING_LANE_CNTL 0 0x400512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_0_MARGINING_LANE_STATUS 0 0x400512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_1_MARGINING_LANE_CNTL 0 0x400513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_1_MARGINING_LANE_STATUS 0 0x400513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_2_MARGINING_LANE_CNTL 0 0x400514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_2_MARGINING_LANE_STATUS 0 0x400514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_3_MARGINING_LANE_CNTL 0 0x400515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_3_MARGINING_LANE_STATUS 0 0x400515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_4_MARGINING_LANE_CNTL 0 0x400516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_4_MARGINING_LANE_STATUS 0 0x400516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_5_MARGINING_LANE_CNTL 0 0x400517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_5_MARGINING_LANE_STATUS 0 0x400517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_6_MARGINING_LANE_CNTL 0 0x400518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_6_MARGINING_LANE_STATUS 0 0x400518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_7_MARGINING_LANE_CNTL 0 0x400519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_7_MARGINING_LANE_STATUS 0 0x400519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_8_MARGINING_LANE_CNTL 0 0x40051a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_8_MARGINING_LANE_STATUS 0 0x40051a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_9_MARGINING_LANE_CNTL 0 0x40051b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_9_MARGINING_LANE_STATUS 0 0x40051b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_10_MARGINING_LANE_CNTL 0 0x40051c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_10_MARGINING_LANE_STATUS 0 0x40051c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_11_MARGINING_LANE_CNTL 0 0x40051d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_11_MARGINING_LANE_STATUS 0 0x40051d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_12_MARGINING_LANE_CNTL 0 0x40051e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_12_MARGINING_LANE_STATUS 0 0x40051e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_13_MARGINING_LANE_CNTL 0 0x40051f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_13_MARGINING_LANE_STATUS 0 0x40051f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_14_MARGINING_LANE_CNTL 0 0x400520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_14_MARGINING_LANE_STATUS 0 0x400520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_LANE_15_MARGINING_LANE_CNTL 0 0x400521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR1_0_LANE_15_MARGINING_LANE_STATUS 0 0x400521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_0_PCIE_CCIX_CAP_LIST 0 0x400522 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_0_PCIE_CCIX_HEADER_1 0 0x400523 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR1_0_PCIE_CCIX_HEADER_2 0 0x400524 1 0 5 CAP_ID 0 15 regBIFPLR1_0_PCIE_CCIX_CAP 0 0x400524 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP 0 0x400525 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x400526 1 0 5 RESERVED 0 31 regBIFPLR1_0_PCIE_CCIX_ESM_STATUS 0 0x400527 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR1_0_PCIE_CCIX_ESM_CNTL 0 0x400528 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x400529 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x400529 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x400529 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x400529 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40052a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40052a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40052a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40052a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40052b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40052b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40052b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40052b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40052c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40052c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40052c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40052c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40052d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40052d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40052d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40052d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40052e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40052e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40052e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40052e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40052f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40052f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40052f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40052f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x400530 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x400530 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x400530 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x400530 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR1_0_PCIE_CCIX_TRANS_CAP 0 0x400531 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR1_0_PCIE_CCIX_TRANS_CNTL 0 0x400532 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR2_0_VENDOR_ID 0 0x400800 1 0 5 VENDOR_ID 0 15 regBIFPLR2_0_DEVICE_ID 0 0x400800 1 0 5 DEVICE_ID 0 15 regBIFPLR2_0_COMMAND 0 0x400801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR2_0_STATUS 0 0x400801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR2_0_REVISION_ID 0 0x400802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR2_0_PROG_INTERFACE 0 0x400802 1 0 5 PROG_INTERFACE 0 7 regBIFPLR2_0_SUB_CLASS 0 0x400802 1 0 5 SUB_CLASS 0 7 regBIFPLR2_0_BASE_CLASS 0 0x400802 1 0 5 BASE_CLASS 0 7 regBIFPLR2_0_CACHE_LINE 0 0x400803 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR2_0_LATENCY 0 0x400803 1 0 5 LATENCY_TIMER 0 7 regBIFPLR2_0_HEADER 0 0x400803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR2_0_BIST 0 0x400803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR2_0_SUB_BUS_NUMBER_LATENCY 0 0x400806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR2_0_IO_BASE_LIMIT 0 0x400807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR2_0_SECONDARY_STATUS 0 0x400807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR2_0_MEM_BASE_LIMIT 0 0x400808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR2_0_PREF_BASE_LIMIT 0 0x400809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR2_0_PREF_BASE_UPPER 0 0x40080a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR2_0_PREF_LIMIT_UPPER 0 0x40080b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR2_0_IO_BASE_LIMIT_HI 0 0x40080c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR2_0_CAP_PTR 0 0x40080d 1 0 5 CAP_PTR 0 7 regBIFPLR2_0_ROM_BASE_ADDR 0 0x40080e 1 0 5 BASE_ADDR 0 31 regBIFPLR2_0_INTERRUPT_LINE 0 0x40080f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR2_0_INTERRUPT_PIN 0 0x40080f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR2_0_IRQ_BRIDGE_CNTL 0 0x40080f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR2_0_EXT_BRIDGE_CNTL 0 0x400810 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR2_0_VENDOR_CAP_LIST 0 0x400812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR2_0_ADAPTER_ID_W 0 0x400813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR2_0_PMI_CAP_LIST 0 0x400814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_0_PMI_CAP 0 0x400814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR2_0_PMI_STATUS_CNTL 0 0x400815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR2_0_PCIE_CAP_LIST 0 0x400816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_0_PCIE_CAP 0 0x400816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR2_0_DEVICE_CAP 0 0x400817 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR2_0_DEVICE_CNTL 0 0x400818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR2_0_DEVICE_STATUS 0 0x400818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR2_0_LINK_CAP 0 0x400819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR2_0_LINK_CNTL 0 0x40081a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR2_0_LINK_STATUS 0 0x40081a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR2_0_SLOT_CAP 0 0x40081b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR2_0_SLOT_CNTL 0 0x40081c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR2_0_SLOT_STATUS 0 0x40081c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR2_0_ROOT_CNTL 0 0x40081d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR2_0_ROOT_CAP 0 0x40081d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR2_0_ROOT_STATUS 0 0x40081e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR2_0_DEVICE_CAP2 0 0x40081f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR2_0_DEVICE_CNTL2 0 0x400820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR2_0_DEVICE_STATUS2 0 0x400820 1 0 5 RESERVED 0 15 regBIFPLR2_0_LINK_CAP2 0 0x400821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR2_0_LINK_CNTL2 0 0x400822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR2_0_LINK_STATUS2 0 0x400822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR2_0_SLOT_CAP2 0 0x400823 1 0 5 RESERVED 0 31 regBIFPLR2_0_SLOT_CNTL2 0 0x400824 1 0 5 RESERVED 0 15 regBIFPLR2_0_SLOT_STATUS2 0 0x400824 1 0 5 RESERVED 0 15 regBIFPLR2_0_MSI_CAP_LIST 0 0x400828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_0_MSI_MSG_CNTL 0 0x400828 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR2_0_MSI_MSG_ADDR_LO 0 0x400829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR2_0_MSI_MSG_ADDR_HI 0 0x40082a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR2_0_MSI_MSG_DATA 0 0x40082a 1 0 5 MSI_DATA 0 15 regBIFPLR2_0_MSI_MSG_DATA_64 0 0x40082b 1 0 5 MSI_DATA_64 0 15 regBIFPLR2_0_SSID_CAP_LIST 0 0x400830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_0_SSID_CAP 0 0x400831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR2_0_MSI_MAP_CAP_LIST 0 0x400832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_0_MSI_MAP_CAP 0 0x400832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x400840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x400841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR2_0_PCIE_VENDOR_SPECIFIC1 0 0x400842 1 0 5 SCRATCH 0 31 regBIFPLR2_0_PCIE_VENDOR_SPECIFIC2 0 0x400843 1 0 5 SCRATCH 0 31 regBIFPLR2_0_PCIE_VC_ENH_CAP_LIST 0 0x400844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_PORT_VC_CAP_REG1 0 0x400845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR2_0_PCIE_PORT_VC_CAP_REG2 0 0x400846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR2_0_PCIE_PORT_VC_CNTL 0 0x400847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR2_0_PCIE_PORT_VC_STATUS 0 0x400847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR2_0_PCIE_VC0_RESOURCE_CAP 0 0x400848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL 0 0x400849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS 0 0x40084a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR2_0_PCIE_VC1_RESOURCE_CAP 0 0x40084b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL 0 0x40084c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS 0 0x40084d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x400850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x400851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x400852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x400854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_UNCORR_ERR_STATUS 0 0x400855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR2_0_PCIE_UNCORR_ERR_MASK 0 0x400856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY 0 0x400857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR2_0_PCIE_CORR_ERR_STATUS 0 0x400858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR2_0_PCIE_CORR_ERR_MASK 0 0x400859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40085a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR2_0_PCIE_HDR_LOG0 0 0x40085b 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_HDR_LOG1 0 0x40085c 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_HDR_LOG2 0 0x40085d 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_HDR_LOG3 0 0x40085e 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_ROOT_ERR_CMD 0 0x40085f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR2_0_PCIE_ROOT_ERR_STATUS 0 0x400860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR2_0_PCIE_ERR_SRC_ID 0 0x400861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR2_0_PCIE_TLP_PREFIX_LOG0 0 0x400862 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_TLP_PREFIX_LOG1 0 0x400863 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_TLP_PREFIX_LOG2 0 0x400864 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_TLP_PREFIX_LOG3 0 0x400865 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40089c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_LINK_CNTL3 0 0x40089d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR2_0_PCIE_LANE_ERROR_STATUS 0 0x40089e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40089f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40089f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4008a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4008a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4008a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4008a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4008a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4008a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4008a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4008a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4008a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4008a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4008a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4008a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4008a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4008a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST 0 0x4008a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_ACS_CAP 0 0x4008a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR2_0_PCIE_ACS_CNTL 0 0x4008a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR2_0_PCIE_MC_ENH_CAP_LIST 0 0x4008bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_MC_CAP 0 0x4008bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR2_0_PCIE_MC_CNTL 0 0x4008bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR2_0_PCIE_MC_ADDR0 0 0x4008be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR2_0_PCIE_MC_ADDR1 0 0x4008bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR2_0_PCIE_MC_RCV0 0 0x4008c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR2_0_PCIE_MC_RCV1 0 0x4008c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR2_0_PCIE_MC_BLOCK_ALL0 0 0x4008c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR2_0_PCIE_MC_BLOCK_ALL1 0 0x4008c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4008c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4008c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR2_0_PCIE_MC_OVERLAY_BAR0 0 0x4008c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR2_0_PCIE_MC_OVERLAY_BAR1 0 0x4008c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4008dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_L1_PM_SUB_CAP 0 0x4008dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0 0x4008de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 0 0x4008df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST 0 0x4008e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_DPC_CAP_LIST 0 0x4008e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR2_0_PCIE_DPC_CNTL 0 0x4008e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR2_0_PCIE_DPC_STATUS 0 0x4008e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4008e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR2_0_PCIE_RP_PIO_STATUS 0 0x4008e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_0_PCIE_RP_PIO_MASK 0 0x4008e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_0_PCIE_RP_PIO_SEVERITY 0 0x4008e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_0_PCIE_RP_PIO_SYSERROR 0 0x4008e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_0_PCIE_RP_PIO_EXCEPTION 0 0x4008e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 0 0x4008e8 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 0 0x4008e9 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 0 0x4008ea 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 0 0x4008eb 1 0 5 TLP_HDR 0 31 regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4008ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4008ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4008ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4008f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_0_PCIE_ESM_CAP_LIST 0 0x4008f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_ESM_HEADER_1 0 0x4008f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR2_0_PCIE_ESM_HEADER_2 0 0x4008f3 1 0 5 CAP_ID 0 15 regBIFPLR2_0_PCIE_ESM_STATUS 0 0x4008f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR2_0_PCIE_ESM_CTRL 0 0x4008f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR2_0_PCIE_ESM_CAP_1 0 0x4008f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR2_0_PCIE_ESM_CAP_2 0 0x4008f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR2_0_PCIE_ESM_CAP_3 0 0x4008f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR2_0_PCIE_ESM_CAP_4 0 0x4008f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR2_0_PCIE_ESM_CAP_5 0 0x4008f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR2_0_PCIE_ESM_CAP_6 0 0x4008fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR2_0_PCIE_ESM_CAP_7 0 0x4008fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR2_0_PCIE_DLF_ENH_CAP_LIST 0 0x400900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_DATA_LINK_FEATURE_CAP 0 0x400901 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR2_0_DATA_LINK_FEATURE_STATUS 0 0x400902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x400904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_LINK_CAP_16GT 0 0x400905 1 0 5 RESERVED 0 31 regBIFPLR2_0_LINK_CNTL_16GT 0 0x400906 1 0 5 RESERVED 0 31 regBIFPLR2_0_LINK_STATUS_16GT 0 0x400907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x400908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x400909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40090a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40090c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40090c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40090c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40090c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40090d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40090d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40090d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40090d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40090e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40090e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40090e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40090e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40090f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40090f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40090f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40090f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x400910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_MARGINING_PORT_CAP 0 0x400911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR2_0_MARGINING_PORT_STATUS 0 0x400911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR2_0_LANE_0_MARGINING_LANE_CNTL 0 0x400912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_0_MARGINING_LANE_STATUS 0 0x400912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_1_MARGINING_LANE_CNTL 0 0x400913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_1_MARGINING_LANE_STATUS 0 0x400913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_2_MARGINING_LANE_CNTL 0 0x400914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_2_MARGINING_LANE_STATUS 0 0x400914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_3_MARGINING_LANE_CNTL 0 0x400915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_3_MARGINING_LANE_STATUS 0 0x400915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_4_MARGINING_LANE_CNTL 0 0x400916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_4_MARGINING_LANE_STATUS 0 0x400916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_5_MARGINING_LANE_CNTL 0 0x400917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_5_MARGINING_LANE_STATUS 0 0x400917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_6_MARGINING_LANE_CNTL 0 0x400918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_6_MARGINING_LANE_STATUS 0 0x400918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_7_MARGINING_LANE_CNTL 0 0x400919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_7_MARGINING_LANE_STATUS 0 0x400919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_8_MARGINING_LANE_CNTL 0 0x40091a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_8_MARGINING_LANE_STATUS 0 0x40091a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_9_MARGINING_LANE_CNTL 0 0x40091b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_9_MARGINING_LANE_STATUS 0 0x40091b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_10_MARGINING_LANE_CNTL 0 0x40091c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_10_MARGINING_LANE_STATUS 0 0x40091c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_11_MARGINING_LANE_CNTL 0 0x40091d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_11_MARGINING_LANE_STATUS 0 0x40091d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_12_MARGINING_LANE_CNTL 0 0x40091e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_12_MARGINING_LANE_STATUS 0 0x40091e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_13_MARGINING_LANE_CNTL 0 0x40091f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_13_MARGINING_LANE_STATUS 0 0x40091f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_14_MARGINING_LANE_CNTL 0 0x400920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_14_MARGINING_LANE_STATUS 0 0x400920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_LANE_15_MARGINING_LANE_CNTL 0 0x400921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR2_0_LANE_15_MARGINING_LANE_STATUS 0 0x400921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_0_PCIE_CCIX_CAP_LIST 0 0x400922 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_0_PCIE_CCIX_HEADER_1 0 0x400923 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR2_0_PCIE_CCIX_HEADER_2 0 0x400924 1 0 5 CAP_ID 0 15 regBIFPLR2_0_PCIE_CCIX_CAP 0 0x400924 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP 0 0x400925 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x400926 1 0 5 RESERVED 0 31 regBIFPLR2_0_PCIE_CCIX_ESM_STATUS 0 0x400927 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR2_0_PCIE_CCIX_ESM_CNTL 0 0x400928 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x400929 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x400929 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x400929 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x400929 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40092a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40092a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40092a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40092a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40092b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40092b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40092b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40092b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40092c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40092c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40092c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40092c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40092d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40092d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40092d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40092d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40092e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40092e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40092e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40092e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40092f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40092f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40092f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40092f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x400930 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x400930 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x400930 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x400930 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR2_0_PCIE_CCIX_TRANS_CAP 0 0x400931 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR2_0_PCIE_CCIX_TRANS_CNTL 0 0x400932 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR3_0_VENDOR_ID 0 0x400c00 1 0 5 VENDOR_ID 0 15 regBIFPLR3_0_DEVICE_ID 0 0x400c00 1 0 5 DEVICE_ID 0 15 regBIFPLR3_0_COMMAND 0 0x400c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR3_0_STATUS 0 0x400c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR3_0_REVISION_ID 0 0x400c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR3_0_PROG_INTERFACE 0 0x400c02 1 0 5 PROG_INTERFACE 0 7 regBIFPLR3_0_SUB_CLASS 0 0x400c02 1 0 5 SUB_CLASS 0 7 regBIFPLR3_0_BASE_CLASS 0 0x400c02 1 0 5 BASE_CLASS 0 7 regBIFPLR3_0_CACHE_LINE 0 0x400c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR3_0_LATENCY 0 0x400c03 1 0 5 LATENCY_TIMER 0 7 regBIFPLR3_0_HEADER 0 0x400c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR3_0_BIST 0 0x400c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR3_0_SUB_BUS_NUMBER_LATENCY 0 0x400c06 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR3_0_IO_BASE_LIMIT 0 0x400c07 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR3_0_SECONDARY_STATUS 0 0x400c07 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR3_0_MEM_BASE_LIMIT 0 0x400c08 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR3_0_PREF_BASE_LIMIT 0 0x400c09 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR3_0_PREF_BASE_UPPER 0 0x400c0a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR3_0_PREF_LIMIT_UPPER 0 0x400c0b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR3_0_IO_BASE_LIMIT_HI 0 0x400c0c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR3_0_CAP_PTR 0 0x400c0d 1 0 5 CAP_PTR 0 7 regBIFPLR3_0_ROM_BASE_ADDR 0 0x400c0e 1 0 5 BASE_ADDR 0 31 regBIFPLR3_0_INTERRUPT_LINE 0 0x400c0f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR3_0_INTERRUPT_PIN 0 0x400c0f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR3_0_IRQ_BRIDGE_CNTL 0 0x400c0f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR3_0_EXT_BRIDGE_CNTL 0 0x400c10 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR3_0_VENDOR_CAP_LIST 0 0x400c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR3_0_ADAPTER_ID_W 0 0x400c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR3_0_PMI_CAP_LIST 0 0x400c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_0_PMI_CAP 0 0x400c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR3_0_PMI_STATUS_CNTL 0 0x400c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR3_0_PCIE_CAP_LIST 0 0x400c16 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_0_PCIE_CAP 0 0x400c16 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR3_0_DEVICE_CAP 0 0x400c17 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR3_0_DEVICE_CNTL 0 0x400c18 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR3_0_DEVICE_STATUS 0 0x400c18 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR3_0_LINK_CAP 0 0x400c19 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR3_0_LINK_CNTL 0 0x400c1a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR3_0_LINK_STATUS 0 0x400c1a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR3_0_SLOT_CAP 0 0x400c1b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR3_0_SLOT_CNTL 0 0x400c1c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR3_0_SLOT_STATUS 0 0x400c1c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR3_0_ROOT_CNTL 0 0x400c1d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR3_0_ROOT_CAP 0 0x400c1d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR3_0_ROOT_STATUS 0 0x400c1e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR3_0_DEVICE_CAP2 0 0x400c1f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR3_0_DEVICE_CNTL2 0 0x400c20 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR3_0_DEVICE_STATUS2 0 0x400c20 1 0 5 RESERVED 0 15 regBIFPLR3_0_LINK_CAP2 0 0x400c21 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR3_0_LINK_CNTL2 0 0x400c22 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR3_0_LINK_STATUS2 0 0x400c22 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR3_0_SLOT_CAP2 0 0x400c23 1 0 5 RESERVED 0 31 regBIFPLR3_0_SLOT_CNTL2 0 0x400c24 1 0 5 RESERVED 0 15 regBIFPLR3_0_SLOT_STATUS2 0 0x400c24 1 0 5 RESERVED 0 15 regBIFPLR3_0_MSI_CAP_LIST 0 0x400c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_0_MSI_MSG_CNTL 0 0x400c28 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR3_0_MSI_MSG_ADDR_LO 0 0x400c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR3_0_MSI_MSG_ADDR_HI 0 0x400c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR3_0_MSI_MSG_DATA 0 0x400c2a 1 0 5 MSI_DATA 0 15 regBIFPLR3_0_MSI_MSG_DATA_64 0 0x400c2b 1 0 5 MSI_DATA_64 0 15 regBIFPLR3_0_SSID_CAP_LIST 0 0x400c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_0_SSID_CAP 0 0x400c31 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR3_0_MSI_MAP_CAP_LIST 0 0x400c32 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_0_MSI_MAP_CAP 0 0x400c32 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x400c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x400c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR3_0_PCIE_VENDOR_SPECIFIC1 0 0x400c42 1 0 5 SCRATCH 0 31 regBIFPLR3_0_PCIE_VENDOR_SPECIFIC2 0 0x400c43 1 0 5 SCRATCH 0 31 regBIFPLR3_0_PCIE_VC_ENH_CAP_LIST 0 0x400c44 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0 0x400c45 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR3_0_PCIE_PORT_VC_CAP_REG2 0 0x400c46 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR3_0_PCIE_PORT_VC_CNTL 0 0x400c47 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR3_0_PCIE_PORT_VC_STATUS 0 0x400c47 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR3_0_PCIE_VC0_RESOURCE_CAP 0 0x400c48 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL 0 0x400c49 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS 0 0x400c4a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR3_0_PCIE_VC1_RESOURCE_CAP 0 0x400c4b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL 0 0x400c4c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS 0 0x400c4d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x400c50 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x400c51 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x400c52 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x400c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_UNCORR_ERR_STATUS 0 0x400c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR3_0_PCIE_UNCORR_ERR_MASK 0 0x400c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY 0 0x400c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR3_0_PCIE_CORR_ERR_STATUS 0 0x400c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR3_0_PCIE_CORR_ERR_MASK 0 0x400c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL 0 0x400c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR3_0_PCIE_HDR_LOG0 0 0x400c5b 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_HDR_LOG1 0 0x400c5c 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_HDR_LOG2 0 0x400c5d 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_HDR_LOG3 0 0x400c5e 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_ROOT_ERR_CMD 0 0x400c5f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR3_0_PCIE_ROOT_ERR_STATUS 0 0x400c60 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR3_0_PCIE_ERR_SRC_ID 0 0x400c61 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR3_0_PCIE_TLP_PREFIX_LOG0 0 0x400c62 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_TLP_PREFIX_LOG1 0 0x400c63 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_TLP_PREFIX_LOG2 0 0x400c64 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_TLP_PREFIX_LOG3 0 0x400c65 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x400c9c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_LINK_CNTL3 0 0x400c9d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR3_0_PCIE_LANE_ERROR_STATUS 0 0x400c9e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x400c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x400c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x400ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x400ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x400ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x400ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x400ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x400ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x400ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x400ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x400ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x400ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x400ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x400ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x400ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x400ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST 0 0x400ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_ACS_CAP 0 0x400ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR3_0_PCIE_ACS_CNTL 0 0x400ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR3_0_PCIE_MC_ENH_CAP_LIST 0 0x400cbc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_MC_CAP 0 0x400cbd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR3_0_PCIE_MC_CNTL 0 0x400cbd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR3_0_PCIE_MC_ADDR0 0 0x400cbe 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR3_0_PCIE_MC_ADDR1 0 0x400cbf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR3_0_PCIE_MC_RCV0 0 0x400cc0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR3_0_PCIE_MC_RCV1 0 0x400cc1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR3_0_PCIE_MC_BLOCK_ALL0 0 0x400cc2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR3_0_PCIE_MC_BLOCK_ALL1 0 0x400cc3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x400cc4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x400cc5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR3_0_PCIE_MC_OVERLAY_BAR0 0 0x400cc6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR3_0_PCIE_MC_OVERLAY_BAR1 0 0x400cc7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x400cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_L1_PM_SUB_CAP 0 0x400cdd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL 0 0x400cde 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 0 0x400cdf 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST 0 0x400ce0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_DPC_CAP_LIST 0 0x400ce1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR3_0_PCIE_DPC_CNTL 0 0x400ce1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR3_0_PCIE_DPC_STATUS 0 0x400ce2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x400ce2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR3_0_PCIE_RP_PIO_STATUS 0 0x400ce3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_0_PCIE_RP_PIO_MASK 0 0x400ce4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_0_PCIE_RP_PIO_SEVERITY 0 0x400ce5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_0_PCIE_RP_PIO_SYSERROR 0 0x400ce6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_0_PCIE_RP_PIO_EXCEPTION 0 0x400ce7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 0 0x400ce8 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 0 0x400ce9 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 0 0x400cea 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 0 0x400ceb 1 0 5 TLP_HDR 0 31 regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x400ced 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x400cee 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x400cef 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x400cf0 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_0_PCIE_ESM_CAP_LIST 0 0x400cf1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_ESM_HEADER_1 0 0x400cf2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR3_0_PCIE_ESM_HEADER_2 0 0x400cf3 1 0 5 CAP_ID 0 15 regBIFPLR3_0_PCIE_ESM_STATUS 0 0x400cf3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR3_0_PCIE_ESM_CTRL 0 0x400cf4 1 0 5 ESM_ENABLED 15 15 regBIFPLR3_0_PCIE_ESM_CAP_1 0 0x400cf5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR3_0_PCIE_ESM_CAP_2 0 0x400cf6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR3_0_PCIE_ESM_CAP_3 0 0x400cf7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR3_0_PCIE_ESM_CAP_4 0 0x400cf8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR3_0_PCIE_ESM_CAP_5 0 0x400cf9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR3_0_PCIE_ESM_CAP_6 0 0x400cfa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR3_0_PCIE_ESM_CAP_7 0 0x400cfb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR3_0_PCIE_DLF_ENH_CAP_LIST 0 0x400d00 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_DATA_LINK_FEATURE_CAP 0 0x400d01 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR3_0_DATA_LINK_FEATURE_STATUS 0 0x400d02 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x400d04 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_LINK_CAP_16GT 0 0x400d05 1 0 5 RESERVED 0 31 regBIFPLR3_0_LINK_CNTL_16GT 0 0x400d06 1 0 5 RESERVED 0 31 regBIFPLR3_0_LINK_STATUS_16GT 0 0x400d07 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x400d08 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x400d09 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x400d0a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x400d0c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x400d0c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x400d0c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x400d0c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x400d0d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x400d0d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x400d0d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x400d0d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x400d0e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x400d0e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x400d0e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x400d0e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x400d0f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x400d0f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x400d0f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x400d0f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x400d10 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_MARGINING_PORT_CAP 0 0x400d11 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR3_0_MARGINING_PORT_STATUS 0 0x400d11 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR3_0_LANE_0_MARGINING_LANE_CNTL 0 0x400d12 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_0_MARGINING_LANE_STATUS 0 0x400d12 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_1_MARGINING_LANE_CNTL 0 0x400d13 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_1_MARGINING_LANE_STATUS 0 0x400d13 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_2_MARGINING_LANE_CNTL 0 0x400d14 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_2_MARGINING_LANE_STATUS 0 0x400d14 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_3_MARGINING_LANE_CNTL 0 0x400d15 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_3_MARGINING_LANE_STATUS 0 0x400d15 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_4_MARGINING_LANE_CNTL 0 0x400d16 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_4_MARGINING_LANE_STATUS 0 0x400d16 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_5_MARGINING_LANE_CNTL 0 0x400d17 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_5_MARGINING_LANE_STATUS 0 0x400d17 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_6_MARGINING_LANE_CNTL 0 0x400d18 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_6_MARGINING_LANE_STATUS 0 0x400d18 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_7_MARGINING_LANE_CNTL 0 0x400d19 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_7_MARGINING_LANE_STATUS 0 0x400d19 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_8_MARGINING_LANE_CNTL 0 0x400d1a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_8_MARGINING_LANE_STATUS 0 0x400d1a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_9_MARGINING_LANE_CNTL 0 0x400d1b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_9_MARGINING_LANE_STATUS 0 0x400d1b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_10_MARGINING_LANE_CNTL 0 0x400d1c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_10_MARGINING_LANE_STATUS 0 0x400d1c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_11_MARGINING_LANE_CNTL 0 0x400d1d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_11_MARGINING_LANE_STATUS 0 0x400d1d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_12_MARGINING_LANE_CNTL 0 0x400d1e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_12_MARGINING_LANE_STATUS 0 0x400d1e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_13_MARGINING_LANE_CNTL 0 0x400d1f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_13_MARGINING_LANE_STATUS 0 0x400d1f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_14_MARGINING_LANE_CNTL 0 0x400d20 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_14_MARGINING_LANE_STATUS 0 0x400d20 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_LANE_15_MARGINING_LANE_CNTL 0 0x400d21 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR3_0_LANE_15_MARGINING_LANE_STATUS 0 0x400d21 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_0_PCIE_CCIX_CAP_LIST 0 0x400d22 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_0_PCIE_CCIX_HEADER_1 0 0x400d23 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR3_0_PCIE_CCIX_HEADER_2 0 0x400d24 1 0 5 CAP_ID 0 15 regBIFPLR3_0_PCIE_CCIX_CAP 0 0x400d24 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP 0 0x400d25 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x400d26 1 0 5 RESERVED 0 31 regBIFPLR3_0_PCIE_CCIX_ESM_STATUS 0 0x400d27 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR3_0_PCIE_CCIX_ESM_CNTL 0 0x400d28 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x400d29 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x400d29 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x400d29 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x400d29 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x400d2a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x400d2a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x400d2a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x400d2a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x400d2b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x400d2b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x400d2b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x400d2b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x400d2c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x400d2c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x400d2c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x400d2c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x400d2d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x400d2d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x400d2d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x400d2d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x400d2e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x400d2e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x400d2e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x400d2e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x400d2f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x400d2f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x400d2f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x400d2f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x400d30 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x400d30 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x400d30 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x400d30 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR3_0_PCIE_CCIX_TRANS_CAP 0 0x400d31 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR3_0_PCIE_CCIX_TRANS_CNTL 0 0x400d32 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR4_0_VENDOR_ID 0 0x401000 1 0 5 VENDOR_ID 0 15 regBIFPLR4_0_DEVICE_ID 0 0x401000 1 0 5 DEVICE_ID 0 15 regBIFPLR4_0_COMMAND 0 0x401001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR4_0_STATUS 0 0x401001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR4_0_REVISION_ID 0 0x401002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR4_0_PROG_INTERFACE 0 0x401002 1 0 5 PROG_INTERFACE 0 7 regBIFPLR4_0_SUB_CLASS 0 0x401002 1 0 5 SUB_CLASS 0 7 regBIFPLR4_0_BASE_CLASS 0 0x401002 1 0 5 BASE_CLASS 0 7 regBIFPLR4_0_CACHE_LINE 0 0x401003 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR4_0_LATENCY 0 0x401003 1 0 5 LATENCY_TIMER 0 7 regBIFPLR4_0_HEADER 0 0x401003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR4_0_BIST 0 0x401003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR4_0_SUB_BUS_NUMBER_LATENCY 0 0x401006 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR4_0_IO_BASE_LIMIT 0 0x401007 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR4_0_SECONDARY_STATUS 0 0x401007 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR4_0_MEM_BASE_LIMIT 0 0x401008 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR4_0_PREF_BASE_LIMIT 0 0x401009 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR4_0_PREF_BASE_UPPER 0 0x40100a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR4_0_PREF_LIMIT_UPPER 0 0x40100b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR4_0_IO_BASE_LIMIT_HI 0 0x40100c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR4_0_CAP_PTR 0 0x40100d 1 0 5 CAP_PTR 0 7 regBIFPLR4_0_ROM_BASE_ADDR 0 0x40100e 1 0 5 BASE_ADDR 0 31 regBIFPLR4_0_INTERRUPT_LINE 0 0x40100f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR4_0_INTERRUPT_PIN 0 0x40100f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR4_0_IRQ_BRIDGE_CNTL 0 0x40100f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR4_0_EXT_BRIDGE_CNTL 0 0x401010 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR4_0_VENDOR_CAP_LIST 0 0x401012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR4_0_ADAPTER_ID_W 0 0x401013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR4_0_PMI_CAP_LIST 0 0x401014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_0_PMI_CAP 0 0x401014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR4_0_PMI_STATUS_CNTL 0 0x401015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR4_0_PCIE_CAP_LIST 0 0x401016 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_0_PCIE_CAP 0 0x401016 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR4_0_DEVICE_CAP 0 0x401017 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR4_0_DEVICE_CNTL 0 0x401018 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR4_0_DEVICE_STATUS 0 0x401018 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR4_0_LINK_CAP 0 0x401019 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR4_0_LINK_CNTL 0 0x40101a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR4_0_LINK_STATUS 0 0x40101a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR4_0_SLOT_CAP 0 0x40101b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR4_0_SLOT_CNTL 0 0x40101c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR4_0_SLOT_STATUS 0 0x40101c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR4_0_ROOT_CNTL 0 0x40101d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR4_0_ROOT_CAP 0 0x40101d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR4_0_ROOT_STATUS 0 0x40101e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR4_0_DEVICE_CAP2 0 0x40101f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR4_0_DEVICE_CNTL2 0 0x401020 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR4_0_DEVICE_STATUS2 0 0x401020 1 0 5 RESERVED 0 15 regBIFPLR4_0_LINK_CAP2 0 0x401021 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR4_0_LINK_CNTL2 0 0x401022 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR4_0_LINK_STATUS2 0 0x401022 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR4_0_SLOT_CAP2 0 0x401023 1 0 5 RESERVED 0 31 regBIFPLR4_0_SLOT_CNTL2 0 0x401024 1 0 5 RESERVED 0 15 regBIFPLR4_0_SLOT_STATUS2 0 0x401024 1 0 5 RESERVED 0 15 regBIFPLR4_0_MSI_CAP_LIST 0 0x401028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_0_MSI_MSG_CNTL 0 0x401028 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR4_0_MSI_MSG_ADDR_LO 0 0x401029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR4_0_MSI_MSG_ADDR_HI 0 0x40102a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR4_0_MSI_MSG_DATA 0 0x40102a 1 0 5 MSI_DATA 0 15 regBIFPLR4_0_MSI_MSG_DATA_64 0 0x40102b 1 0 5 MSI_DATA_64 0 15 regBIFPLR4_0_SSID_CAP_LIST 0 0x401030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_0_SSID_CAP 0 0x401031 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR4_0_MSI_MAP_CAP_LIST 0 0x401032 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_0_MSI_MAP_CAP 0 0x401032 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x401040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x401041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR4_0_PCIE_VENDOR_SPECIFIC1 0 0x401042 1 0 5 SCRATCH 0 31 regBIFPLR4_0_PCIE_VENDOR_SPECIFIC2 0 0x401043 1 0 5 SCRATCH 0 31 regBIFPLR4_0_PCIE_VC_ENH_CAP_LIST 0 0x401044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_PORT_VC_CAP_REG1 0 0x401045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR4_0_PCIE_PORT_VC_CAP_REG2 0 0x401046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR4_0_PCIE_PORT_VC_CNTL 0 0x401047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR4_0_PCIE_PORT_VC_STATUS 0 0x401047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR4_0_PCIE_VC0_RESOURCE_CAP 0 0x401048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL 0 0x401049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS 0 0x40104a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR4_0_PCIE_VC1_RESOURCE_CAP 0 0x40104b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL 0 0x40104c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS 0 0x40104d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x401050 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x401051 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x401052 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x401054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_UNCORR_ERR_STATUS 0 0x401055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR4_0_PCIE_UNCORR_ERR_MASK 0 0x401056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY 0 0x401057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR4_0_PCIE_CORR_ERR_STATUS 0 0x401058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR4_0_PCIE_CORR_ERR_MASK 0 0x401059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40105a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR4_0_PCIE_HDR_LOG0 0 0x40105b 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_HDR_LOG1 0 0x40105c 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_HDR_LOG2 0 0x40105d 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_HDR_LOG3 0 0x40105e 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_ROOT_ERR_CMD 0 0x40105f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR4_0_PCIE_ROOT_ERR_STATUS 0 0x401060 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR4_0_PCIE_ERR_SRC_ID 0 0x401061 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR4_0_PCIE_TLP_PREFIX_LOG0 0 0x401062 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_TLP_PREFIX_LOG1 0 0x401063 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_TLP_PREFIX_LOG2 0 0x401064 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_TLP_PREFIX_LOG3 0 0x401065 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40109c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_LINK_CNTL3 0 0x40109d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR4_0_PCIE_LANE_ERROR_STATUS 0 0x40109e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40109f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40109f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4010a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4010a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4010a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4010a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4010a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4010a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4010a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4010a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4010a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4010a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4010a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4010a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4010a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4010a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST 0 0x4010a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_ACS_CAP 0 0x4010a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR4_0_PCIE_ACS_CNTL 0 0x4010a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR4_0_PCIE_MC_ENH_CAP_LIST 0 0x4010bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_MC_CAP 0 0x4010bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR4_0_PCIE_MC_CNTL 0 0x4010bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR4_0_PCIE_MC_ADDR0 0 0x4010be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR4_0_PCIE_MC_ADDR1 0 0x4010bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR4_0_PCIE_MC_RCV0 0 0x4010c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR4_0_PCIE_MC_RCV1 0 0x4010c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR4_0_PCIE_MC_BLOCK_ALL0 0 0x4010c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR4_0_PCIE_MC_BLOCK_ALL1 0 0x4010c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4010c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4010c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR4_0_PCIE_MC_OVERLAY_BAR0 0 0x4010c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR4_0_PCIE_MC_OVERLAY_BAR1 0 0x4010c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4010dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_L1_PM_SUB_CAP 0 0x4010dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL 0 0x4010de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 0 0x4010df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST 0 0x4010e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_DPC_CAP_LIST 0 0x4010e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR4_0_PCIE_DPC_CNTL 0 0x4010e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR4_0_PCIE_DPC_STATUS 0 0x4010e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4010e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR4_0_PCIE_RP_PIO_STATUS 0 0x4010e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_0_PCIE_RP_PIO_MASK 0 0x4010e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_0_PCIE_RP_PIO_SEVERITY 0 0x4010e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_0_PCIE_RP_PIO_SYSERROR 0 0x4010e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_0_PCIE_RP_PIO_EXCEPTION 0 0x4010e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 0 0x4010e8 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 0 0x4010e9 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 0 0x4010ea 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 0 0x4010eb 1 0 5 TLP_HDR 0 31 regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4010ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4010ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4010ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4010f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_0_PCIE_ESM_CAP_LIST 0 0x4010f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_ESM_HEADER_1 0 0x4010f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR4_0_PCIE_ESM_HEADER_2 0 0x4010f3 1 0 5 CAP_ID 0 15 regBIFPLR4_0_PCIE_ESM_STATUS 0 0x4010f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR4_0_PCIE_ESM_CTRL 0 0x4010f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR4_0_PCIE_ESM_CAP_1 0 0x4010f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR4_0_PCIE_ESM_CAP_2 0 0x4010f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR4_0_PCIE_ESM_CAP_3 0 0x4010f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR4_0_PCIE_ESM_CAP_4 0 0x4010f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR4_0_PCIE_ESM_CAP_5 0 0x4010f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR4_0_PCIE_ESM_CAP_6 0 0x4010fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR4_0_PCIE_ESM_CAP_7 0 0x4010fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR4_0_PCIE_DLF_ENH_CAP_LIST 0 0x401100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_DATA_LINK_FEATURE_CAP 0 0x401101 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR4_0_DATA_LINK_FEATURE_STATUS 0 0x401102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x401104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_LINK_CAP_16GT 0 0x401105 1 0 5 RESERVED 0 31 regBIFPLR4_0_LINK_CNTL_16GT 0 0x401106 1 0 5 RESERVED 0 31 regBIFPLR4_0_LINK_STATUS_16GT 0 0x401107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x401108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x401109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40110a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40110c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40110c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40110c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40110c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40110d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40110d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40110d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40110d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40110e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40110e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40110e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40110e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40110f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40110f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40110f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40110f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x401110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_MARGINING_PORT_CAP 0 0x401111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR4_0_MARGINING_PORT_STATUS 0 0x401111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR4_0_LANE_0_MARGINING_LANE_CNTL 0 0x401112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_0_MARGINING_LANE_STATUS 0 0x401112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_1_MARGINING_LANE_CNTL 0 0x401113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_1_MARGINING_LANE_STATUS 0 0x401113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_2_MARGINING_LANE_CNTL 0 0x401114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_2_MARGINING_LANE_STATUS 0 0x401114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_3_MARGINING_LANE_CNTL 0 0x401115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_3_MARGINING_LANE_STATUS 0 0x401115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_4_MARGINING_LANE_CNTL 0 0x401116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_4_MARGINING_LANE_STATUS 0 0x401116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_5_MARGINING_LANE_CNTL 0 0x401117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_5_MARGINING_LANE_STATUS 0 0x401117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_6_MARGINING_LANE_CNTL 0 0x401118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_6_MARGINING_LANE_STATUS 0 0x401118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_7_MARGINING_LANE_CNTL 0 0x401119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_7_MARGINING_LANE_STATUS 0 0x401119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_8_MARGINING_LANE_CNTL 0 0x40111a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_8_MARGINING_LANE_STATUS 0 0x40111a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_9_MARGINING_LANE_CNTL 0 0x40111b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_9_MARGINING_LANE_STATUS 0 0x40111b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_10_MARGINING_LANE_CNTL 0 0x40111c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_10_MARGINING_LANE_STATUS 0 0x40111c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_11_MARGINING_LANE_CNTL 0 0x40111d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_11_MARGINING_LANE_STATUS 0 0x40111d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_12_MARGINING_LANE_CNTL 0 0x40111e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_12_MARGINING_LANE_STATUS 0 0x40111e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_13_MARGINING_LANE_CNTL 0 0x40111f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_13_MARGINING_LANE_STATUS 0 0x40111f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_14_MARGINING_LANE_CNTL 0 0x401120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_14_MARGINING_LANE_STATUS 0 0x401120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_LANE_15_MARGINING_LANE_CNTL 0 0x401121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR4_0_LANE_15_MARGINING_LANE_STATUS 0 0x401121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_0_PCIE_CCIX_CAP_LIST 0 0x401122 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_0_PCIE_CCIX_HEADER_1 0 0x401123 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR4_0_PCIE_CCIX_HEADER_2 0 0x401124 1 0 5 CAP_ID 0 15 regBIFPLR4_0_PCIE_CCIX_CAP 0 0x401124 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP 0 0x401125 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x401126 1 0 5 RESERVED 0 31 regBIFPLR4_0_PCIE_CCIX_ESM_STATUS 0 0x401127 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR4_0_PCIE_CCIX_ESM_CNTL 0 0x401128 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x401129 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x401129 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x401129 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x401129 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40112a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40112a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40112a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40112a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40112b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40112b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40112b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40112b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40112c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40112c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40112c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40112c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40112d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40112d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40112d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40112d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40112e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40112e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40112e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40112e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40112f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40112f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40112f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40112f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x401130 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x401130 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x401130 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x401130 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR4_0_PCIE_CCIX_TRANS_CAP 0 0x401131 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR4_0_PCIE_CCIX_TRANS_CNTL 0 0x401132 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR5_0_VENDOR_ID 0 0x401400 1 0 5 VENDOR_ID 0 15 regBIFPLR5_0_DEVICE_ID 0 0x401400 1 0 5 DEVICE_ID 0 15 regBIFPLR5_0_COMMAND 0 0x401401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR5_0_STATUS 0 0x401401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR5_0_REVISION_ID 0 0x401402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR5_0_PROG_INTERFACE 0 0x401402 1 0 5 PROG_INTERFACE 0 7 regBIFPLR5_0_SUB_CLASS 0 0x401402 1 0 5 SUB_CLASS 0 7 regBIFPLR5_0_BASE_CLASS 0 0x401402 1 0 5 BASE_CLASS 0 7 regBIFPLR5_0_CACHE_LINE 0 0x401403 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR5_0_LATENCY 0 0x401403 1 0 5 LATENCY_TIMER 0 7 regBIFPLR5_0_HEADER 0 0x401403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR5_0_BIST 0 0x401403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR5_0_SUB_BUS_NUMBER_LATENCY 0 0x401406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR5_0_IO_BASE_LIMIT 0 0x401407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR5_0_SECONDARY_STATUS 0 0x401407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR5_0_MEM_BASE_LIMIT 0 0x401408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR5_0_PREF_BASE_LIMIT 0 0x401409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR5_0_PREF_BASE_UPPER 0 0x40140a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR5_0_PREF_LIMIT_UPPER 0 0x40140b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR5_0_IO_BASE_LIMIT_HI 0 0x40140c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR5_0_CAP_PTR 0 0x40140d 1 0 5 CAP_PTR 0 7 regBIFPLR5_0_ROM_BASE_ADDR 0 0x40140e 1 0 5 BASE_ADDR 0 31 regBIFPLR5_0_INTERRUPT_LINE 0 0x40140f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR5_0_INTERRUPT_PIN 0 0x40140f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR5_0_IRQ_BRIDGE_CNTL 0 0x40140f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR5_0_EXT_BRIDGE_CNTL 0 0x401410 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR5_0_VENDOR_CAP_LIST 0 0x401412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR5_0_ADAPTER_ID_W 0 0x401413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR5_0_PMI_CAP_LIST 0 0x401414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_0_PMI_CAP 0 0x401414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR5_0_PMI_STATUS_CNTL 0 0x401415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR5_0_PCIE_CAP_LIST 0 0x401416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_0_PCIE_CAP 0 0x401416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR5_0_DEVICE_CAP 0 0x401417 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR5_0_DEVICE_CNTL 0 0x401418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR5_0_DEVICE_STATUS 0 0x401418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR5_0_LINK_CAP 0 0x401419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR5_0_LINK_CNTL 0 0x40141a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR5_0_LINK_STATUS 0 0x40141a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR5_0_SLOT_CAP 0 0x40141b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR5_0_SLOT_CNTL 0 0x40141c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR5_0_SLOT_STATUS 0 0x40141c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR5_0_ROOT_CNTL 0 0x40141d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR5_0_ROOT_CAP 0 0x40141d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR5_0_ROOT_STATUS 0 0x40141e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR5_0_DEVICE_CAP2 0 0x40141f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR5_0_DEVICE_CNTL2 0 0x401420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR5_0_DEVICE_STATUS2 0 0x401420 1 0 5 RESERVED 0 15 regBIFPLR5_0_LINK_CAP2 0 0x401421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR5_0_LINK_CNTL2 0 0x401422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR5_0_LINK_STATUS2 0 0x401422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR5_0_SLOT_CAP2 0 0x401423 1 0 5 RESERVED 0 31 regBIFPLR5_0_SLOT_CNTL2 0 0x401424 1 0 5 RESERVED 0 15 regBIFPLR5_0_SLOT_STATUS2 0 0x401424 1 0 5 RESERVED 0 15 regBIFPLR5_0_MSI_CAP_LIST 0 0x401428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_0_MSI_MSG_CNTL 0 0x401428 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR5_0_MSI_MSG_ADDR_LO 0 0x401429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR5_0_MSI_MSG_ADDR_HI 0 0x40142a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR5_0_MSI_MSG_DATA 0 0x40142a 1 0 5 MSI_DATA 0 15 regBIFPLR5_0_MSI_MSG_DATA_64 0 0x40142b 1 0 5 MSI_DATA_64 0 15 regBIFPLR5_0_SSID_CAP_LIST 0 0x401430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_0_SSID_CAP 0 0x401431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR5_0_MSI_MAP_CAP_LIST 0 0x401432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_0_MSI_MAP_CAP 0 0x401432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x401440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x401441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR5_0_PCIE_VENDOR_SPECIFIC1 0 0x401442 1 0 5 SCRATCH 0 31 regBIFPLR5_0_PCIE_VENDOR_SPECIFIC2 0 0x401443 1 0 5 SCRATCH 0 31 regBIFPLR5_0_PCIE_VC_ENH_CAP_LIST 0 0x401444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_PORT_VC_CAP_REG1 0 0x401445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2 0 0x401446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR5_0_PCIE_PORT_VC_CNTL 0 0x401447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR5_0_PCIE_PORT_VC_STATUS 0 0x401447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR5_0_PCIE_VC0_RESOURCE_CAP 0 0x401448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL 0 0x401449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS 0 0x40144a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR5_0_PCIE_VC1_RESOURCE_CAP 0 0x40144b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL 0 0x40144c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS 0 0x40144d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x401450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x401451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x401452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x401454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_UNCORR_ERR_STATUS 0 0x401455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR5_0_PCIE_UNCORR_ERR_MASK 0 0x401456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY 0 0x401457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR5_0_PCIE_CORR_ERR_STATUS 0 0x401458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR5_0_PCIE_CORR_ERR_MASK 0 0x401459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40145a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR5_0_PCIE_HDR_LOG0 0 0x40145b 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_HDR_LOG1 0 0x40145c 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_HDR_LOG2 0 0x40145d 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_HDR_LOG3 0 0x40145e 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_ROOT_ERR_CMD 0 0x40145f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR5_0_PCIE_ROOT_ERR_STATUS 0 0x401460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR5_0_PCIE_ERR_SRC_ID 0 0x401461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR5_0_PCIE_TLP_PREFIX_LOG0 0 0x401462 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_TLP_PREFIX_LOG1 0 0x401463 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_TLP_PREFIX_LOG2 0 0x401464 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_TLP_PREFIX_LOG3 0 0x401465 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40149c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_LINK_CNTL3 0 0x40149d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR5_0_PCIE_LANE_ERROR_STATUS 0 0x40149e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40149f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40149f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4014a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4014a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4014a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4014a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4014a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4014a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4014a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4014a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4014a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4014a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4014a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4014a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4014a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4014a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST 0 0x4014a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_ACS_CAP 0 0x4014a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR5_0_PCIE_ACS_CNTL 0 0x4014a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR5_0_PCIE_MC_ENH_CAP_LIST 0 0x4014bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_MC_CAP 0 0x4014bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR5_0_PCIE_MC_CNTL 0 0x4014bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR5_0_PCIE_MC_ADDR0 0 0x4014be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR5_0_PCIE_MC_ADDR1 0 0x4014bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR5_0_PCIE_MC_RCV0 0 0x4014c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR5_0_PCIE_MC_RCV1 0 0x4014c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR5_0_PCIE_MC_BLOCK_ALL0 0 0x4014c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR5_0_PCIE_MC_BLOCK_ALL1 0 0x4014c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4014c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4014c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR5_0_PCIE_MC_OVERLAY_BAR0 0 0x4014c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR5_0_PCIE_MC_OVERLAY_BAR1 0 0x4014c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4014dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_L1_PM_SUB_CAP 0 0x4014dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL 0 0x4014de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 0 0x4014df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST 0 0x4014e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_DPC_CAP_LIST 0 0x4014e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR5_0_PCIE_DPC_CNTL 0 0x4014e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR5_0_PCIE_DPC_STATUS 0 0x4014e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4014e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR5_0_PCIE_RP_PIO_STATUS 0 0x4014e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_0_PCIE_RP_PIO_MASK 0 0x4014e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_0_PCIE_RP_PIO_SEVERITY 0 0x4014e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_0_PCIE_RP_PIO_SYSERROR 0 0x4014e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_0_PCIE_RP_PIO_EXCEPTION 0 0x4014e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 0 0x4014e8 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 0 0x4014e9 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 0 0x4014ea 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 0 0x4014eb 1 0 5 TLP_HDR 0 31 regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4014ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4014ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4014ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4014f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_0_PCIE_ESM_CAP_LIST 0 0x4014f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_ESM_HEADER_1 0 0x4014f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR5_0_PCIE_ESM_HEADER_2 0 0x4014f3 1 0 5 CAP_ID 0 15 regBIFPLR5_0_PCIE_ESM_STATUS 0 0x4014f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR5_0_PCIE_ESM_CTRL 0 0x4014f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR5_0_PCIE_ESM_CAP_1 0 0x4014f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR5_0_PCIE_ESM_CAP_2 0 0x4014f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR5_0_PCIE_ESM_CAP_3 0 0x4014f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR5_0_PCIE_ESM_CAP_4 0 0x4014f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR5_0_PCIE_ESM_CAP_5 0 0x4014f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR5_0_PCIE_ESM_CAP_6 0 0x4014fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR5_0_PCIE_ESM_CAP_7 0 0x4014fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR5_0_PCIE_DLF_ENH_CAP_LIST 0 0x401500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_DATA_LINK_FEATURE_CAP 0 0x401501 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR5_0_DATA_LINK_FEATURE_STATUS 0 0x401502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x401504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_LINK_CAP_16GT 0 0x401505 1 0 5 RESERVED 0 31 regBIFPLR5_0_LINK_CNTL_16GT 0 0x401506 1 0 5 RESERVED 0 31 regBIFPLR5_0_LINK_STATUS_16GT 0 0x401507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x401508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x401509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40150a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40150c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40150c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40150c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40150c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40150d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40150d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40150d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40150d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40150e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40150e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40150e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40150e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40150f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40150f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40150f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40150f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x401510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_MARGINING_PORT_CAP 0 0x401511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR5_0_MARGINING_PORT_STATUS 0 0x401511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR5_0_LANE_0_MARGINING_LANE_CNTL 0 0x401512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_0_MARGINING_LANE_STATUS 0 0x401512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_1_MARGINING_LANE_CNTL 0 0x401513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_1_MARGINING_LANE_STATUS 0 0x401513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_2_MARGINING_LANE_CNTL 0 0x401514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_2_MARGINING_LANE_STATUS 0 0x401514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_3_MARGINING_LANE_CNTL 0 0x401515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_3_MARGINING_LANE_STATUS 0 0x401515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_4_MARGINING_LANE_CNTL 0 0x401516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_4_MARGINING_LANE_STATUS 0 0x401516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_5_MARGINING_LANE_CNTL 0 0x401517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_5_MARGINING_LANE_STATUS 0 0x401517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_6_MARGINING_LANE_CNTL 0 0x401518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_6_MARGINING_LANE_STATUS 0 0x401518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_7_MARGINING_LANE_CNTL 0 0x401519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_7_MARGINING_LANE_STATUS 0 0x401519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_8_MARGINING_LANE_CNTL 0 0x40151a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_8_MARGINING_LANE_STATUS 0 0x40151a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_9_MARGINING_LANE_CNTL 0 0x40151b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_9_MARGINING_LANE_STATUS 0 0x40151b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_10_MARGINING_LANE_CNTL 0 0x40151c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_10_MARGINING_LANE_STATUS 0 0x40151c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_11_MARGINING_LANE_CNTL 0 0x40151d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_11_MARGINING_LANE_STATUS 0 0x40151d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_12_MARGINING_LANE_CNTL 0 0x40151e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_12_MARGINING_LANE_STATUS 0 0x40151e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_13_MARGINING_LANE_CNTL 0 0x40151f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_13_MARGINING_LANE_STATUS 0 0x40151f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_14_MARGINING_LANE_CNTL 0 0x401520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_14_MARGINING_LANE_STATUS 0 0x401520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_LANE_15_MARGINING_LANE_CNTL 0 0x401521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR5_0_LANE_15_MARGINING_LANE_STATUS 0 0x401521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_0_PCIE_CCIX_CAP_LIST 0 0x401522 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_0_PCIE_CCIX_HEADER_1 0 0x401523 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR5_0_PCIE_CCIX_HEADER_2 0 0x401524 1 0 5 CAP_ID 0 15 regBIFPLR5_0_PCIE_CCIX_CAP 0 0x401524 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP 0 0x401525 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x401526 1 0 5 RESERVED 0 31 regBIFPLR5_0_PCIE_CCIX_ESM_STATUS 0 0x401527 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR5_0_PCIE_CCIX_ESM_CNTL 0 0x401528 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x401529 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x401529 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x401529 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x401529 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40152a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40152a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40152a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40152a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40152b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40152b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40152b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40152b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40152c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40152c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40152c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40152c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40152d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40152d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40152d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40152d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40152e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40152e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40152e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40152e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40152f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40152f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40152f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40152f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x401530 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x401530 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x401530 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x401530 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR5_0_PCIE_CCIX_TRANS_CAP 0 0x401531 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR5_0_PCIE_CCIX_TRANS_CNTL 0 0x401532 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR6_0_VENDOR_ID 0 0x401800 1 0 5 VENDOR_ID 0 15 regBIFPLR6_0_DEVICE_ID 0 0x401800 1 0 5 DEVICE_ID 0 15 regBIFPLR6_0_COMMAND 0 0x401801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR6_0_STATUS 0 0x401801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR6_0_REVISION_ID 0 0x401802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR6_0_PROG_INTERFACE 0 0x401802 1 0 5 PROG_INTERFACE 0 7 regBIFPLR6_0_SUB_CLASS 0 0x401802 1 0 5 SUB_CLASS 0 7 regBIFPLR6_0_BASE_CLASS 0 0x401802 1 0 5 BASE_CLASS 0 7 regBIFPLR6_0_CACHE_LINE 0 0x401803 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR6_0_LATENCY 0 0x401803 1 0 5 LATENCY_TIMER 0 7 regBIFPLR6_0_HEADER 0 0x401803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR6_0_BIST 0 0x401803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR6_0_SUB_BUS_NUMBER_LATENCY 0 0x401806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR6_0_IO_BASE_LIMIT 0 0x401807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR6_0_SECONDARY_STATUS 0 0x401807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR6_0_MEM_BASE_LIMIT 0 0x401808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR6_0_PREF_BASE_LIMIT 0 0x401809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR6_0_PREF_BASE_UPPER 0 0x40180a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR6_0_PREF_LIMIT_UPPER 0 0x40180b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR6_0_IO_BASE_LIMIT_HI 0 0x40180c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR6_0_CAP_PTR 0 0x40180d 1 0 5 CAP_PTR 0 7 regBIFPLR6_0_ROM_BASE_ADDR 0 0x40180e 1 0 5 BASE_ADDR 0 31 regBIFPLR6_0_INTERRUPT_LINE 0 0x40180f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR6_0_INTERRUPT_PIN 0 0x40180f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR6_0_IRQ_BRIDGE_CNTL 0 0x40180f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR6_0_EXT_BRIDGE_CNTL 0 0x401810 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR6_0_VENDOR_CAP_LIST 0 0x401812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR6_0_ADAPTER_ID_W 0 0x401813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR6_0_PMI_CAP_LIST 0 0x401814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_0_PMI_CAP 0 0x401814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR6_0_PMI_STATUS_CNTL 0 0x401815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR6_0_PCIE_CAP_LIST 0 0x401816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_0_PCIE_CAP 0 0x401816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR6_0_DEVICE_CAP 0 0x401817 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR6_0_DEVICE_CNTL 0 0x401818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR6_0_DEVICE_STATUS 0 0x401818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR6_0_LINK_CAP 0 0x401819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR6_0_LINK_CNTL 0 0x40181a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR6_0_LINK_STATUS 0 0x40181a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR6_0_SLOT_CAP 0 0x40181b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR6_0_SLOT_CNTL 0 0x40181c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR6_0_SLOT_STATUS 0 0x40181c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR6_0_ROOT_CNTL 0 0x40181d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR6_0_ROOT_CAP 0 0x40181d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR6_0_ROOT_STATUS 0 0x40181e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR6_0_DEVICE_CAP2 0 0x40181f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR6_0_DEVICE_CNTL2 0 0x401820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR6_0_DEVICE_STATUS2 0 0x401820 1 0 5 RESERVED 0 15 regBIFPLR6_0_LINK_CAP2 0 0x401821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR6_0_LINK_CNTL2 0 0x401822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR6_0_LINK_STATUS2 0 0x401822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR6_0_SLOT_CAP2 0 0x401823 1 0 5 RESERVED 0 31 regBIFPLR6_0_SLOT_CNTL2 0 0x401824 1 0 5 RESERVED 0 15 regBIFPLR6_0_SLOT_STATUS2 0 0x401824 1 0 5 RESERVED 0 15 regBIFPLR6_0_MSI_CAP_LIST 0 0x401828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_0_MSI_MSG_CNTL 0 0x401828 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR6_0_MSI_MSG_ADDR_LO 0 0x401829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR6_0_MSI_MSG_ADDR_HI 0 0x40182a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR6_0_MSI_MSG_DATA 0 0x40182a 1 0 5 MSI_DATA 0 15 regBIFPLR6_0_MSI_MSG_DATA_64 0 0x40182b 1 0 5 MSI_DATA_64 0 15 regBIFPLR6_0_SSID_CAP_LIST 0 0x401830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_0_SSID_CAP 0 0x401831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR6_0_MSI_MAP_CAP_LIST 0 0x401832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_0_MSI_MAP_CAP 0 0x401832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x401840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR 0 0x401841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR6_0_PCIE_VENDOR_SPECIFIC1 0 0x401842 1 0 5 SCRATCH 0 31 regBIFPLR6_0_PCIE_VENDOR_SPECIFIC2 0 0x401843 1 0 5 SCRATCH 0 31 regBIFPLR6_0_PCIE_VC_ENH_CAP_LIST 0 0x401844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_PORT_VC_CAP_REG1 0 0x401845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR6_0_PCIE_PORT_VC_CAP_REG2 0 0x401846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR6_0_PCIE_PORT_VC_CNTL 0 0x401847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR6_0_PCIE_PORT_VC_STATUS 0 0x401847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR6_0_PCIE_VC0_RESOURCE_CAP 0 0x401848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL 0 0x401849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS 0 0x40184a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR6_0_PCIE_VC1_RESOURCE_CAP 0 0x40184b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL 0 0x40184c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS 0 0x40184d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x401850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 0 0x401851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 0 0x401852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x401854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_UNCORR_ERR_STATUS 0 0x401855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR6_0_PCIE_UNCORR_ERR_MASK 0 0x401856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY 0 0x401857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR6_0_PCIE_CORR_ERR_STATUS 0 0x401858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR6_0_PCIE_CORR_ERR_MASK 0 0x401859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL 0 0x40185a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR6_0_PCIE_HDR_LOG0 0 0x40185b 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_HDR_LOG1 0 0x40185c 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_HDR_LOG2 0 0x40185d 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_HDR_LOG3 0 0x40185e 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_ROOT_ERR_CMD 0 0x40185f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR6_0_PCIE_ROOT_ERR_STATUS 0 0x401860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR6_0_PCIE_ERR_SRC_ID 0 0x401861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR6_0_PCIE_TLP_PREFIX_LOG0 0 0x401862 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_TLP_PREFIX_LOG1 0 0x401863 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_TLP_PREFIX_LOG2 0 0x401864 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_TLP_PREFIX_LOG3 0 0x401865 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST 0 0x40189c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_LINK_CNTL3 0 0x40189d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR6_0_PCIE_LANE_ERROR_STATUS 0 0x40189e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x40189f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x40189f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x4018a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x4018a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x4018a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x4018a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x4018a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x4018a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x4018a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x4018a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x4018a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x4018a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x4018a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x4018a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x4018a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x4018a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST 0 0x4018a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_ACS_CAP 0 0x4018a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR6_0_PCIE_ACS_CNTL 0 0x4018a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR6_0_PCIE_MC_ENH_CAP_LIST 0 0x4018bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_MC_CAP 0 0x4018bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR6_0_PCIE_MC_CNTL 0 0x4018bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR6_0_PCIE_MC_ADDR0 0 0x4018be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR6_0_PCIE_MC_ADDR1 0 0x4018bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR6_0_PCIE_MC_RCV0 0 0x4018c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR6_0_PCIE_MC_RCV1 0 0x4018c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR6_0_PCIE_MC_BLOCK_ALL0 0 0x4018c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR6_0_PCIE_MC_BLOCK_ALL1 0 0x4018c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x4018c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x4018c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR6_0_PCIE_MC_OVERLAY_BAR0 0 0x4018c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR6_0_PCIE_MC_OVERLAY_BAR1 0 0x4018c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST 0 0x4018dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_L1_PM_SUB_CAP 0 0x4018dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL 0 0x4018de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 0 0x4018df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST 0 0x4018e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_DPC_CAP_LIST 0 0x4018e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR6_0_PCIE_DPC_CNTL 0 0x4018e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR6_0_PCIE_DPC_STATUS 0 0x4018e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID 0 0x4018e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR6_0_PCIE_RP_PIO_STATUS 0 0x4018e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_0_PCIE_RP_PIO_MASK 0 0x4018e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_0_PCIE_RP_PIO_SEVERITY 0 0x4018e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_0_PCIE_RP_PIO_SYSERROR 0 0x4018e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_0_PCIE_RP_PIO_EXCEPTION 0 0x4018e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 0 0x4018e8 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 0 0x4018e9 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 0 0x4018ea 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 0 0x4018eb 1 0 5 TLP_HDR 0 31 regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 0 0x4018ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 0 0x4018ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 0 0x4018ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 0 0x4018f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_0_PCIE_ESM_CAP_LIST 0 0x4018f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_ESM_HEADER_1 0 0x4018f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR6_0_PCIE_ESM_HEADER_2 0 0x4018f3 1 0 5 CAP_ID 0 15 regBIFPLR6_0_PCIE_ESM_STATUS 0 0x4018f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR6_0_PCIE_ESM_CTRL 0 0x4018f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR6_0_PCIE_ESM_CAP_1 0 0x4018f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR6_0_PCIE_ESM_CAP_2 0 0x4018f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR6_0_PCIE_ESM_CAP_3 0 0x4018f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR6_0_PCIE_ESM_CAP_4 0 0x4018f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR6_0_PCIE_ESM_CAP_5 0 0x4018f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR6_0_PCIE_ESM_CAP_6 0 0x4018fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR6_0_PCIE_ESM_CAP_7 0 0x4018fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR6_0_PCIE_DLF_ENH_CAP_LIST 0 0x401900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_DATA_LINK_FEATURE_CAP 0 0x401901 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR6_0_DATA_LINK_FEATURE_STATUS 0 0x401902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x401904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_LINK_CAP_16GT 0 0x401905 1 0 5 RESERVED 0 31 regBIFPLR6_0_LINK_CNTL_16GT 0 0x401906 1 0 5 RESERVED 0 31 regBIFPLR6_0_LINK_STATUS_16GT 0 0x401907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x401908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x401909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x40190a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT 0 0x40190c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT 0 0x40190c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT 0 0x40190c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT 0 0x40190c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT 0 0x40190d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT 0 0x40190d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT 0 0x40190d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT 0 0x40190d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT 0 0x40190e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT 0 0x40190e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT 0 0x40190e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT 0 0x40190e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT 0 0x40190f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT 0 0x40190f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT 0 0x40190f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT 0 0x40190f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST 0 0x401910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_MARGINING_PORT_CAP 0 0x401911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR6_0_MARGINING_PORT_STATUS 0 0x401911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR6_0_LANE_0_MARGINING_LANE_CNTL 0 0x401912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_0_MARGINING_LANE_STATUS 0 0x401912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_1_MARGINING_LANE_CNTL 0 0x401913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_1_MARGINING_LANE_STATUS 0 0x401913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_2_MARGINING_LANE_CNTL 0 0x401914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_2_MARGINING_LANE_STATUS 0 0x401914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_3_MARGINING_LANE_CNTL 0 0x401915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_3_MARGINING_LANE_STATUS 0 0x401915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_4_MARGINING_LANE_CNTL 0 0x401916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_4_MARGINING_LANE_STATUS 0 0x401916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_5_MARGINING_LANE_CNTL 0 0x401917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_5_MARGINING_LANE_STATUS 0 0x401917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_6_MARGINING_LANE_CNTL 0 0x401918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_6_MARGINING_LANE_STATUS 0 0x401918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_7_MARGINING_LANE_CNTL 0 0x401919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_7_MARGINING_LANE_STATUS 0 0x401919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_8_MARGINING_LANE_CNTL 0 0x40191a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_8_MARGINING_LANE_STATUS 0 0x40191a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_9_MARGINING_LANE_CNTL 0 0x40191b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_9_MARGINING_LANE_STATUS 0 0x40191b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_10_MARGINING_LANE_CNTL 0 0x40191c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_10_MARGINING_LANE_STATUS 0 0x40191c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_11_MARGINING_LANE_CNTL 0 0x40191d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_11_MARGINING_LANE_STATUS 0 0x40191d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_12_MARGINING_LANE_CNTL 0 0x40191e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_12_MARGINING_LANE_STATUS 0 0x40191e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_13_MARGINING_LANE_CNTL 0 0x40191f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_13_MARGINING_LANE_STATUS 0 0x40191f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_14_MARGINING_LANE_CNTL 0 0x401920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_14_MARGINING_LANE_STATUS 0 0x401920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_LANE_15_MARGINING_LANE_CNTL 0 0x401921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR6_0_LANE_15_MARGINING_LANE_STATUS 0 0x401921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_0_PCIE_CCIX_CAP_LIST 0 0x401922 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_0_PCIE_CCIX_HEADER_1 0 0x401923 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR6_0_PCIE_CCIX_HEADER_2 0 0x401924 1 0 5 CAP_ID 0 15 regBIFPLR6_0_PCIE_CCIX_CAP 0 0x401924 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP 0 0x401925 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP 0 0x401926 1 0 5 RESERVED 0 31 regBIFPLR6_0_PCIE_CCIX_ESM_STATUS 0 0x401927 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR6_0_PCIE_CCIX_ESM_CNTL 0 0x401928 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x401929 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x401929 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x401929 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x401929 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x40192a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x40192a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x40192a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x40192a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x40192b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x40192b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x40192b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x40192b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x40192c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x40192c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x40192c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x40192c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x40192d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x40192d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x40192d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x40192d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x40192e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x40192e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x40192e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x40192e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x40192f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x40192f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x40192f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x40192f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x401930 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x401930 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x401930 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x401930 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR6_0_PCIE_CCIX_TRANS_CAP 0 0x401931 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR6_0_PCIE_CCIX_TRANS_CNTL 0 0x401932 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFP0_PCIEP_RESERVED 0 0x410000 1 0 5 RESERVED 0 31 regBIFP0_PCIEP_SCRATCH 0 0x410001 1 0 5 PCIEP_SCRATCH 0 31 regBIFP0_PCIEP_PORT_CNTL 0 0x410010 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP0_PCIE_TX_CNTL 0 0x410020 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP0_PCIE_TX_REQUESTER_ID 0 0x410021 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP0_PCIE_TX_VENDOR_SPECIFIC 0 0x410022 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP0_PCIE_TX_REQUEST_NUM_CNTL 0 0x410023 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP0_PCIE_TX_SEQ 0 0x410024 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP0_PCIE_TX_REPLAY 0 0x410025 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP0_PCIE_TX_ACK_LATENCY_LIMIT 0 0x410026 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP0_PCIE_TX_NOP_DLLP 0 0x410027 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP0_PCIE_TX_CNTL_2 0 0x410028 0 0 5 regBIFP0_PCIE_TX_SKID_CTRL 0 0x41002f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP0_PCIE_TX_CREDITS_ADVT_P 0 0x410030 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP0_PCIE_TX_CREDITS_ADVT_NP 0 0x410031 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP0_PCIE_TX_CREDITS_ADVT_CPL 0 0x410032 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP0_PCIE_TX_CREDITS_INIT_P 0 0x410033 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP0_PCIE_TX_CREDITS_INIT_NP 0 0x410034 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP0_PCIE_TX_CREDITS_INIT_CPL 0 0x410035 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP0_PCIE_TX_CREDITS_STATUS 0 0x410036 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x410037 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP0_PCIE_TX_CCIX_PORT_CNTL0 0 0x410038 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP0_PCIE_TX_CCIX_PORT_CNTL1 0 0x410039 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP0_PCIE_CCIX_STACKED_BASE 0 0x41003a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP0_PCIE_CCIX_STACKED_LIMIT 0 0x41003b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP0_PCIE_CCIX_MISC_STATUS 0 0x410041 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP0_PCIE_P_PORT_LANE_STATUS 0 0x410050 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP0_PCIE_FC_P 0 0x410060 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP0_PCIE_FC_NP 0 0x410061 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP0_PCIE_FC_CPL 0 0x410062 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP0_PCIE_FC_P_VC1 0 0x410063 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP0_PCIE_FC_NP_VC1 0 0x410064 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP0_PCIE_FC_CPL_VC1 0 0x410065 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP0_PCIE_ERR_CNTL 0 0x41006a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP0_PCIE_RX_CNTL 0 0x410070 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP0_PCIE_RX_EXPECTED_SEQNUM 0 0x410071 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP0_PCIE_RX_VENDOR_SPECIFIC 0 0x410072 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP0_PCIE_RX_CNTL3 0 0x410074 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP0_PCIE_RX_CREDITS_ALLOCATED_P 0 0x410080 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP0_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x410081 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x410082 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP0_PCIEP_ERROR_INJECT_PHYSICAL 0 0x410083 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP0_PCIEP_ERROR_INJECT_TRANSACTION 0 0x410084 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP0_PCIEP_NAK_COUNTER 0 0x410086 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x410088 0 0 5 regBIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x410089 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41008c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP0_PCIE_AER_PRIV_TRIGGER 0 0x41008d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP0_PCIE_LC_CNTL 0 0x4100a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP0_PCIE_LC_TRAINING_CNTL 0 0x4100a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP0_PCIE_LC_LINK_WIDTH_CNTL 0 0x4100a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP0_PCIE_LC_N_FTS_CNTL 0 0x4100a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP0_PCIE_LC_SPEED_CNTL 0 0x4100a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP0_PCIE_LC_STATE0 0 0x4100a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP0_PCIE_LC_STATE1 0 0x4100a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP0_PCIE_LC_STATE2 0 0x4100a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP0_PCIE_LC_STATE3 0 0x4100a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP0_PCIE_LC_STATE4 0 0x4100a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP0_PCIE_LC_STATE5 0 0x4100aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP0_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4100ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP0_PCIE_LC_CNTL2 0 0x4100b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP0_PCIE_LC_BW_CHANGE_CNTL 0 0x4100b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP0_PCIE_LC_CDR_CNTL 0 0x4100b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP0_PCIE_LC_LANE_CNTL 0 0x4100b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP0_PCIE_LC_CNTL3 0 0x4100b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP0_PCIE_LC_CNTL4 0 0x4100b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP0_PCIE_LC_CNTL5 0 0x4100b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP0_PCIE_LC_FORCE_COEFF 0 0x4100b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP0_PCIE_LC_BEST_EQ_SETTINGS 0 0x4100b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4100ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP0_PCIE_LC_CNTL6 0 0x4100bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP0_PCIE_LC_CNTL7 0 0x4100bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP0_PCIE_LINK_MANAGEMENT_STATUS 0 0x4100bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP0_PCIE_LINK_MANAGEMENT_MASK 0 0x4100be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP0_PCIE_LINK_MANAGEMENT_CNTL 0 0x4100bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP0_PCIEP_STRAP_LC 0 0x4100c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP0_PCIEP_STRAP_MISC 0 0x4100c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP0_PCIEP_STRAP_LC2 0 0x4100c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP0_PCIE_LC_L1_PM_SUBSTATE 0 0x4100c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP0_PCIE_LC_L1_PM_SUBSTATE2 0 0x4100c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP0_PCIE_LC_PORT_ORDER 0 0x4100c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP0_PCIEP_BCH_ECC_CNTL 0 0x4100d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP0_PCIEP_HPGI_PRIVATE 0 0x4100d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP0_PCIEP_HPGI 0 0x4100da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP0_PCIEP_HCNT_DESCRIPTOR 0 0x4100db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4100dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP0_PCIE_LC_CNTL8 0 0x4100dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP0_PCIE_LC_CNTL9 0 0x4100de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP0_PCIE_LC_FORCE_COEFF2 0 0x4100df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4100e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4100e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4100e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP0_PCIE_LC_CNTL10 0 0x4100e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP0_PCIE_LC_CNTL11 0 0x4100e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP0_PCIE_LC_CNTL12 0 0x4100e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP0_PCIE_LC_SAVE_RESTORE_1 0 0x4100e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP0_PCIE_LC_SAVE_RESTORE_2 0 0x4100e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP0_PCIE_LC_SAVE_RESTORE_3 0 0x4100e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP1_PCIEP_RESERVED 0 0x410400 1 0 5 RESERVED 0 31 regBIFP1_PCIEP_SCRATCH 0 0x410401 1 0 5 PCIEP_SCRATCH 0 31 regBIFP1_PCIEP_PORT_CNTL 0 0x410410 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP1_PCIE_TX_CNTL 0 0x410420 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP1_PCIE_TX_REQUESTER_ID 0 0x410421 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP1_PCIE_TX_VENDOR_SPECIFIC 0 0x410422 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP1_PCIE_TX_REQUEST_NUM_CNTL 0 0x410423 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP1_PCIE_TX_SEQ 0 0x410424 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP1_PCIE_TX_REPLAY 0 0x410425 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP1_PCIE_TX_ACK_LATENCY_LIMIT 0 0x410426 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP1_PCIE_TX_NOP_DLLP 0 0x410427 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP1_PCIE_TX_CNTL_2 0 0x410428 0 0 5 regBIFP1_PCIE_TX_SKID_CTRL 0 0x41042f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP1_PCIE_TX_CREDITS_ADVT_P 0 0x410430 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP1_PCIE_TX_CREDITS_ADVT_NP 0 0x410431 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP1_PCIE_TX_CREDITS_ADVT_CPL 0 0x410432 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP1_PCIE_TX_CREDITS_INIT_P 0 0x410433 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP1_PCIE_TX_CREDITS_INIT_NP 0 0x410434 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP1_PCIE_TX_CREDITS_INIT_CPL 0 0x410435 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP1_PCIE_TX_CREDITS_STATUS 0 0x410436 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x410437 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP1_PCIE_TX_CCIX_PORT_CNTL0 0 0x410438 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP1_PCIE_TX_CCIX_PORT_CNTL1 0 0x410439 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP1_PCIE_CCIX_STACKED_BASE 0 0x41043a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP1_PCIE_CCIX_STACKED_LIMIT 0 0x41043b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP1_PCIE_CCIX_MISC_STATUS 0 0x410441 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP1_PCIE_P_PORT_LANE_STATUS 0 0x410450 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP1_PCIE_FC_P 0 0x410460 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP1_PCIE_FC_NP 0 0x410461 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP1_PCIE_FC_CPL 0 0x410462 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP1_PCIE_FC_P_VC1 0 0x410463 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP1_PCIE_FC_NP_VC1 0 0x410464 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP1_PCIE_FC_CPL_VC1 0 0x410465 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP1_PCIE_ERR_CNTL 0 0x41046a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP1_PCIE_RX_CNTL 0 0x410470 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP1_PCIE_RX_EXPECTED_SEQNUM 0 0x410471 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP1_PCIE_RX_VENDOR_SPECIFIC 0 0x410472 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP1_PCIE_RX_CNTL3 0 0x410474 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP1_PCIE_RX_CREDITS_ALLOCATED_P 0 0x410480 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP1_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x410481 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x410482 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP1_PCIEP_ERROR_INJECT_PHYSICAL 0 0x410483 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP1_PCIEP_ERROR_INJECT_TRANSACTION 0 0x410484 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP1_PCIEP_NAK_COUNTER 0 0x410486 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x410488 0 0 5 regBIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x410489 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41048c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP1_PCIE_AER_PRIV_TRIGGER 0 0x41048d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP1_PCIE_LC_CNTL 0 0x4104a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP1_PCIE_LC_TRAINING_CNTL 0 0x4104a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP1_PCIE_LC_LINK_WIDTH_CNTL 0 0x4104a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP1_PCIE_LC_N_FTS_CNTL 0 0x4104a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP1_PCIE_LC_SPEED_CNTL 0 0x4104a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP1_PCIE_LC_STATE0 0 0x4104a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP1_PCIE_LC_STATE1 0 0x4104a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP1_PCIE_LC_STATE2 0 0x4104a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP1_PCIE_LC_STATE3 0 0x4104a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP1_PCIE_LC_STATE4 0 0x4104a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP1_PCIE_LC_STATE5 0 0x4104aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP1_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4104ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP1_PCIE_LC_CNTL2 0 0x4104b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP1_PCIE_LC_BW_CHANGE_CNTL 0 0x4104b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP1_PCIE_LC_CDR_CNTL 0 0x4104b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP1_PCIE_LC_LANE_CNTL 0 0x4104b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP1_PCIE_LC_CNTL3 0 0x4104b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP1_PCIE_LC_CNTL4 0 0x4104b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP1_PCIE_LC_CNTL5 0 0x4104b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP1_PCIE_LC_FORCE_COEFF 0 0x4104b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP1_PCIE_LC_BEST_EQ_SETTINGS 0 0x4104b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4104ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP1_PCIE_LC_CNTL6 0 0x4104bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP1_PCIE_LC_CNTL7 0 0x4104bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP1_PCIE_LINK_MANAGEMENT_STATUS 0 0x4104bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP1_PCIE_LINK_MANAGEMENT_MASK 0 0x4104be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP1_PCIE_LINK_MANAGEMENT_CNTL 0 0x4104bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP1_PCIEP_STRAP_LC 0 0x4104c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP1_PCIEP_STRAP_MISC 0 0x4104c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP1_PCIEP_STRAP_LC2 0 0x4104c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP1_PCIE_LC_L1_PM_SUBSTATE 0 0x4104c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP1_PCIE_LC_L1_PM_SUBSTATE2 0 0x4104c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP1_PCIE_LC_PORT_ORDER 0 0x4104c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP1_PCIEP_BCH_ECC_CNTL 0 0x4104d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP1_PCIEP_HPGI_PRIVATE 0 0x4104d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP1_PCIEP_HPGI 0 0x4104da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP1_PCIEP_HCNT_DESCRIPTOR 0 0x4104db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4104dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP1_PCIE_LC_CNTL8 0 0x4104dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP1_PCIE_LC_CNTL9 0 0x4104de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP1_PCIE_LC_FORCE_COEFF2 0 0x4104df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4104e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4104e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4104e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP1_PCIE_LC_CNTL10 0 0x4104e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP1_PCIE_LC_CNTL11 0 0x4104e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP1_PCIE_LC_CNTL12 0 0x4104e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP1_PCIE_LC_SAVE_RESTORE_1 0 0x4104e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP1_PCIE_LC_SAVE_RESTORE_2 0 0x4104e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP1_PCIE_LC_SAVE_RESTORE_3 0 0x4104e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP2_PCIEP_RESERVED 0 0x410800 1 0 5 RESERVED 0 31 regBIFP2_PCIEP_SCRATCH 0 0x410801 1 0 5 PCIEP_SCRATCH 0 31 regBIFP2_PCIEP_PORT_CNTL 0 0x410810 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP2_PCIE_TX_CNTL 0 0x410820 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP2_PCIE_TX_REQUESTER_ID 0 0x410821 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP2_PCIE_TX_VENDOR_SPECIFIC 0 0x410822 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP2_PCIE_TX_REQUEST_NUM_CNTL 0 0x410823 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP2_PCIE_TX_SEQ 0 0x410824 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP2_PCIE_TX_REPLAY 0 0x410825 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP2_PCIE_TX_ACK_LATENCY_LIMIT 0 0x410826 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP2_PCIE_TX_NOP_DLLP 0 0x410827 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP2_PCIE_TX_CNTL_2 0 0x410828 0 0 5 regBIFP2_PCIE_TX_SKID_CTRL 0 0x41082f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP2_PCIE_TX_CREDITS_ADVT_P 0 0x410830 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP2_PCIE_TX_CREDITS_ADVT_NP 0 0x410831 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP2_PCIE_TX_CREDITS_ADVT_CPL 0 0x410832 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP2_PCIE_TX_CREDITS_INIT_P 0 0x410833 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP2_PCIE_TX_CREDITS_INIT_NP 0 0x410834 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP2_PCIE_TX_CREDITS_INIT_CPL 0 0x410835 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP2_PCIE_TX_CREDITS_STATUS 0 0x410836 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x410837 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP2_PCIE_TX_CCIX_PORT_CNTL0 0 0x410838 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP2_PCIE_TX_CCIX_PORT_CNTL1 0 0x410839 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP2_PCIE_CCIX_STACKED_BASE 0 0x41083a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP2_PCIE_CCIX_STACKED_LIMIT 0 0x41083b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP2_PCIE_CCIX_MISC_STATUS 0 0x410841 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP2_PCIE_P_PORT_LANE_STATUS 0 0x410850 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP2_PCIE_FC_P 0 0x410860 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP2_PCIE_FC_NP 0 0x410861 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP2_PCIE_FC_CPL 0 0x410862 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP2_PCIE_FC_P_VC1 0 0x410863 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP2_PCIE_FC_NP_VC1 0 0x410864 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP2_PCIE_FC_CPL_VC1 0 0x410865 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP2_PCIE_ERR_CNTL 0 0x41086a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP2_PCIE_RX_CNTL 0 0x410870 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP2_PCIE_RX_EXPECTED_SEQNUM 0 0x410871 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP2_PCIE_RX_VENDOR_SPECIFIC 0 0x410872 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP2_PCIE_RX_CNTL3 0 0x410874 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP2_PCIE_RX_CREDITS_ALLOCATED_P 0 0x410880 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP2_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x410881 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x410882 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP2_PCIEP_ERROR_INJECT_PHYSICAL 0 0x410883 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP2_PCIEP_ERROR_INJECT_TRANSACTION 0 0x410884 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP2_PCIEP_NAK_COUNTER 0 0x410886 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x410888 0 0 5 regBIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x410889 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41088c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP2_PCIE_AER_PRIV_TRIGGER 0 0x41088d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP2_PCIE_LC_CNTL 0 0x4108a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP2_PCIE_LC_TRAINING_CNTL 0 0x4108a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP2_PCIE_LC_LINK_WIDTH_CNTL 0 0x4108a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP2_PCIE_LC_N_FTS_CNTL 0 0x4108a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP2_PCIE_LC_SPEED_CNTL 0 0x4108a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP2_PCIE_LC_STATE0 0 0x4108a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP2_PCIE_LC_STATE1 0 0x4108a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP2_PCIE_LC_STATE2 0 0x4108a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP2_PCIE_LC_STATE3 0 0x4108a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP2_PCIE_LC_STATE4 0 0x4108a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP2_PCIE_LC_STATE5 0 0x4108aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP2_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4108ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP2_PCIE_LC_CNTL2 0 0x4108b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP2_PCIE_LC_BW_CHANGE_CNTL 0 0x4108b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP2_PCIE_LC_CDR_CNTL 0 0x4108b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP2_PCIE_LC_LANE_CNTL 0 0x4108b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP2_PCIE_LC_CNTL3 0 0x4108b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP2_PCIE_LC_CNTL4 0 0x4108b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP2_PCIE_LC_CNTL5 0 0x4108b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP2_PCIE_LC_FORCE_COEFF 0 0x4108b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP2_PCIE_LC_BEST_EQ_SETTINGS 0 0x4108b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4108ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP2_PCIE_LC_CNTL6 0 0x4108bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP2_PCIE_LC_CNTL7 0 0x4108bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP2_PCIE_LINK_MANAGEMENT_STATUS 0 0x4108bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP2_PCIE_LINK_MANAGEMENT_MASK 0 0x4108be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP2_PCIE_LINK_MANAGEMENT_CNTL 0 0x4108bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP2_PCIEP_STRAP_LC 0 0x4108c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP2_PCIEP_STRAP_MISC 0 0x4108c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP2_PCIEP_STRAP_LC2 0 0x4108c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP2_PCIE_LC_L1_PM_SUBSTATE 0 0x4108c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP2_PCIE_LC_L1_PM_SUBSTATE2 0 0x4108c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP2_PCIE_LC_PORT_ORDER 0 0x4108c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP2_PCIEP_BCH_ECC_CNTL 0 0x4108d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP2_PCIEP_HPGI_PRIVATE 0 0x4108d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP2_PCIEP_HPGI 0 0x4108da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP2_PCIEP_HCNT_DESCRIPTOR 0 0x4108db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4108dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP2_PCIE_LC_CNTL8 0 0x4108dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP2_PCIE_LC_CNTL9 0 0x4108de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP2_PCIE_LC_FORCE_COEFF2 0 0x4108df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4108e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4108e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4108e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP2_PCIE_LC_CNTL10 0 0x4108e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP2_PCIE_LC_CNTL11 0 0x4108e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP2_PCIE_LC_CNTL12 0 0x4108e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP2_PCIE_LC_SAVE_RESTORE_1 0 0x4108e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP2_PCIE_LC_SAVE_RESTORE_2 0 0x4108e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP2_PCIE_LC_SAVE_RESTORE_3 0 0x4108e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP3_PCIEP_RESERVED 0 0x410c00 1 0 5 RESERVED 0 31 regBIFP3_PCIEP_SCRATCH 0 0x410c01 1 0 5 PCIEP_SCRATCH 0 31 regBIFP3_PCIEP_PORT_CNTL 0 0x410c10 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP3_PCIE_TX_CNTL 0 0x410c20 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP3_PCIE_TX_REQUESTER_ID 0 0x410c21 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP3_PCIE_TX_VENDOR_SPECIFIC 0 0x410c22 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP3_PCIE_TX_REQUEST_NUM_CNTL 0 0x410c23 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP3_PCIE_TX_SEQ 0 0x410c24 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP3_PCIE_TX_REPLAY 0 0x410c25 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP3_PCIE_TX_ACK_LATENCY_LIMIT 0 0x410c26 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP3_PCIE_TX_NOP_DLLP 0 0x410c27 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP3_PCIE_TX_CNTL_2 0 0x410c28 0 0 5 regBIFP3_PCIE_TX_SKID_CTRL 0 0x410c2f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP3_PCIE_TX_CREDITS_ADVT_P 0 0x410c30 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP3_PCIE_TX_CREDITS_ADVT_NP 0 0x410c31 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP3_PCIE_TX_CREDITS_ADVT_CPL 0 0x410c32 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP3_PCIE_TX_CREDITS_INIT_P 0 0x410c33 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP3_PCIE_TX_CREDITS_INIT_NP 0 0x410c34 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP3_PCIE_TX_CREDITS_INIT_CPL 0 0x410c35 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP3_PCIE_TX_CREDITS_STATUS 0 0x410c36 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x410c37 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP3_PCIE_TX_CCIX_PORT_CNTL0 0 0x410c38 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP3_PCIE_TX_CCIX_PORT_CNTL1 0 0x410c39 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP3_PCIE_CCIX_STACKED_BASE 0 0x410c3a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP3_PCIE_CCIX_STACKED_LIMIT 0 0x410c3b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP3_PCIE_CCIX_MISC_STATUS 0 0x410c41 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP3_PCIE_P_PORT_LANE_STATUS 0 0x410c50 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP3_PCIE_FC_P 0 0x410c60 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP3_PCIE_FC_NP 0 0x410c61 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP3_PCIE_FC_CPL 0 0x410c62 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP3_PCIE_FC_P_VC1 0 0x410c63 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP3_PCIE_FC_NP_VC1 0 0x410c64 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP3_PCIE_FC_CPL_VC1 0 0x410c65 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP3_PCIE_ERR_CNTL 0 0x410c6a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP3_PCIE_RX_CNTL 0 0x410c70 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP3_PCIE_RX_EXPECTED_SEQNUM 0 0x410c71 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP3_PCIE_RX_VENDOR_SPECIFIC 0 0x410c72 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP3_PCIE_RX_CNTL3 0 0x410c74 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP3_PCIE_RX_CREDITS_ALLOCATED_P 0 0x410c80 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP3_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x410c81 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x410c82 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP3_PCIEP_ERROR_INJECT_PHYSICAL 0 0x410c83 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP3_PCIEP_ERROR_INJECT_TRANSACTION 0 0x410c84 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP3_PCIEP_NAK_COUNTER 0 0x410c86 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x410c88 0 0 5 regBIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x410c89 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x410c8c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP3_PCIE_AER_PRIV_TRIGGER 0 0x410c8d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP3_PCIE_LC_CNTL 0 0x410ca0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP3_PCIE_LC_TRAINING_CNTL 0 0x410ca1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP3_PCIE_LC_LINK_WIDTH_CNTL 0 0x410ca2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP3_PCIE_LC_N_FTS_CNTL 0 0x410ca3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP3_PCIE_LC_SPEED_CNTL 0 0x410ca4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP3_PCIE_LC_STATE0 0 0x410ca5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP3_PCIE_LC_STATE1 0 0x410ca6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP3_PCIE_LC_STATE2 0 0x410ca7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP3_PCIE_LC_STATE3 0 0x410ca8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP3_PCIE_LC_STATE4 0 0x410ca9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP3_PCIE_LC_STATE5 0 0x410caa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP3_PCIE_LINK_MANAGEMENT_CNTL2 0 0x410cab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP3_PCIE_LC_CNTL2 0 0x410cb1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP3_PCIE_LC_BW_CHANGE_CNTL 0 0x410cb2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP3_PCIE_LC_CDR_CNTL 0 0x410cb3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP3_PCIE_LC_LANE_CNTL 0 0x410cb4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP3_PCIE_LC_CNTL3 0 0x410cb5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP3_PCIE_LC_CNTL4 0 0x410cb6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP3_PCIE_LC_CNTL5 0 0x410cb7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP3_PCIE_LC_FORCE_COEFF 0 0x410cb8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP3_PCIE_LC_BEST_EQ_SETTINGS 0 0x410cb9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x410cba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP3_PCIE_LC_CNTL6 0 0x410cbb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP3_PCIE_LC_CNTL7 0 0x410cbc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP3_PCIE_LINK_MANAGEMENT_STATUS 0 0x410cbd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP3_PCIE_LINK_MANAGEMENT_MASK 0 0x410cbe 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP3_PCIE_LINK_MANAGEMENT_CNTL 0 0x410cbf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP3_PCIEP_STRAP_LC 0 0x410cc0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP3_PCIEP_STRAP_MISC 0 0x410cc1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP3_PCIEP_STRAP_LC2 0 0x410cc2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP3_PCIE_LC_L1_PM_SUBSTATE 0 0x410cc6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP3_PCIE_LC_L1_PM_SUBSTATE2 0 0x410cc7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP3_PCIE_LC_PORT_ORDER 0 0x410cc8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP3_PCIEP_BCH_ECC_CNTL 0 0x410cd0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP3_PCIEP_HPGI_PRIVATE 0 0x410cd2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP3_PCIEP_HPGI 0 0x410cda 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP3_PCIEP_HCNT_DESCRIPTOR 0 0x410cdb 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x410cdc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP3_PCIE_LC_CNTL8 0 0x410cdd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP3_PCIE_LC_CNTL9 0 0x410cde 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP3_PCIE_LC_FORCE_COEFF2 0 0x410cdf 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x410ce0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x410ce1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x410ce2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP3_PCIE_LC_CNTL10 0 0x410ce3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP3_PCIE_LC_CNTL11 0 0x410ce4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP3_PCIE_LC_CNTL12 0 0x410ce5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP3_PCIE_LC_SAVE_RESTORE_1 0 0x410ce6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP3_PCIE_LC_SAVE_RESTORE_2 0 0x410ce7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP3_PCIE_LC_SAVE_RESTORE_3 0 0x410ce8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP4_PCIEP_RESERVED 0 0x411000 1 0 5 RESERVED 0 31 regBIFP4_PCIEP_SCRATCH 0 0x411001 1 0 5 PCIEP_SCRATCH 0 31 regBIFP4_PCIEP_PORT_CNTL 0 0x411010 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP4_PCIE_TX_CNTL 0 0x411020 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP4_PCIE_TX_REQUESTER_ID 0 0x411021 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP4_PCIE_TX_VENDOR_SPECIFIC 0 0x411022 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP4_PCIE_TX_REQUEST_NUM_CNTL 0 0x411023 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP4_PCIE_TX_SEQ 0 0x411024 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP4_PCIE_TX_REPLAY 0 0x411025 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP4_PCIE_TX_ACK_LATENCY_LIMIT 0 0x411026 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP4_PCIE_TX_NOP_DLLP 0 0x411027 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP4_PCIE_TX_CNTL_2 0 0x411028 0 0 5 regBIFP4_PCIE_TX_SKID_CTRL 0 0x41102f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP4_PCIE_TX_CREDITS_ADVT_P 0 0x411030 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP4_PCIE_TX_CREDITS_ADVT_NP 0 0x411031 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP4_PCIE_TX_CREDITS_ADVT_CPL 0 0x411032 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP4_PCIE_TX_CREDITS_INIT_P 0 0x411033 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP4_PCIE_TX_CREDITS_INIT_NP 0 0x411034 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP4_PCIE_TX_CREDITS_INIT_CPL 0 0x411035 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP4_PCIE_TX_CREDITS_STATUS 0 0x411036 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x411037 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP4_PCIE_TX_CCIX_PORT_CNTL0 0 0x411038 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP4_PCIE_TX_CCIX_PORT_CNTL1 0 0x411039 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP4_PCIE_CCIX_STACKED_BASE 0 0x41103a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP4_PCIE_CCIX_STACKED_LIMIT 0 0x41103b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP4_PCIE_CCIX_MISC_STATUS 0 0x411041 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP4_PCIE_P_PORT_LANE_STATUS 0 0x411050 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP4_PCIE_FC_P 0 0x411060 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP4_PCIE_FC_NP 0 0x411061 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP4_PCIE_FC_CPL 0 0x411062 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP4_PCIE_FC_P_VC1 0 0x411063 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP4_PCIE_FC_NP_VC1 0 0x411064 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP4_PCIE_FC_CPL_VC1 0 0x411065 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP4_PCIE_ERR_CNTL 0 0x41106a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP4_PCIE_RX_CNTL 0 0x411070 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP4_PCIE_RX_EXPECTED_SEQNUM 0 0x411071 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP4_PCIE_RX_VENDOR_SPECIFIC 0 0x411072 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP4_PCIE_RX_CNTL3 0 0x411074 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP4_PCIE_RX_CREDITS_ALLOCATED_P 0 0x411080 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP4_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x411081 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x411082 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP4_PCIEP_ERROR_INJECT_PHYSICAL 0 0x411083 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP4_PCIEP_ERROR_INJECT_TRANSACTION 0 0x411084 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP4_PCIEP_NAK_COUNTER 0 0x411086 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x411088 0 0 5 regBIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x411089 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41108c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP4_PCIE_AER_PRIV_TRIGGER 0 0x41108d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP4_PCIE_LC_CNTL 0 0x4110a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP4_PCIE_LC_TRAINING_CNTL 0 0x4110a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP4_PCIE_LC_LINK_WIDTH_CNTL 0 0x4110a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP4_PCIE_LC_N_FTS_CNTL 0 0x4110a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP4_PCIE_LC_SPEED_CNTL 0 0x4110a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP4_PCIE_LC_STATE0 0 0x4110a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP4_PCIE_LC_STATE1 0 0x4110a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP4_PCIE_LC_STATE2 0 0x4110a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP4_PCIE_LC_STATE3 0 0x4110a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP4_PCIE_LC_STATE4 0 0x4110a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP4_PCIE_LC_STATE5 0 0x4110aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP4_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4110ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP4_PCIE_LC_CNTL2 0 0x4110b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP4_PCIE_LC_BW_CHANGE_CNTL 0 0x4110b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP4_PCIE_LC_CDR_CNTL 0 0x4110b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP4_PCIE_LC_LANE_CNTL 0 0x4110b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP4_PCIE_LC_CNTL3 0 0x4110b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP4_PCIE_LC_CNTL4 0 0x4110b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP4_PCIE_LC_CNTL5 0 0x4110b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP4_PCIE_LC_FORCE_COEFF 0 0x4110b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP4_PCIE_LC_BEST_EQ_SETTINGS 0 0x4110b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4110ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP4_PCIE_LC_CNTL6 0 0x4110bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP4_PCIE_LC_CNTL7 0 0x4110bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP4_PCIE_LINK_MANAGEMENT_STATUS 0 0x4110bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP4_PCIE_LINK_MANAGEMENT_MASK 0 0x4110be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP4_PCIE_LINK_MANAGEMENT_CNTL 0 0x4110bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP4_PCIEP_STRAP_LC 0 0x4110c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP4_PCIEP_STRAP_MISC 0 0x4110c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP4_PCIEP_STRAP_LC2 0 0x4110c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP4_PCIE_LC_L1_PM_SUBSTATE 0 0x4110c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP4_PCIE_LC_L1_PM_SUBSTATE2 0 0x4110c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP4_PCIE_LC_PORT_ORDER 0 0x4110c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP4_PCIEP_BCH_ECC_CNTL 0 0x4110d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP4_PCIEP_HPGI_PRIVATE 0 0x4110d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP4_PCIEP_HPGI 0 0x4110da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP4_PCIEP_HCNT_DESCRIPTOR 0 0x4110db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4110dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP4_PCIE_LC_CNTL8 0 0x4110dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP4_PCIE_LC_CNTL9 0 0x4110de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP4_PCIE_LC_FORCE_COEFF2 0 0x4110df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4110e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4110e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4110e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP4_PCIE_LC_CNTL10 0 0x4110e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP4_PCIE_LC_CNTL11 0 0x4110e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP4_PCIE_LC_CNTL12 0 0x4110e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP4_PCIE_LC_SAVE_RESTORE_1 0 0x4110e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP4_PCIE_LC_SAVE_RESTORE_2 0 0x4110e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP4_PCIE_LC_SAVE_RESTORE_3 0 0x4110e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP5_PCIEP_RESERVED 0 0x411400 1 0 5 RESERVED 0 31 regBIFP5_PCIEP_SCRATCH 0 0x411401 1 0 5 PCIEP_SCRATCH 0 31 regBIFP5_PCIEP_PORT_CNTL 0 0x411410 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP5_PCIE_TX_CNTL 0 0x411420 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP5_PCIE_TX_REQUESTER_ID 0 0x411421 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP5_PCIE_TX_VENDOR_SPECIFIC 0 0x411422 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP5_PCIE_TX_REQUEST_NUM_CNTL 0 0x411423 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP5_PCIE_TX_SEQ 0 0x411424 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP5_PCIE_TX_REPLAY 0 0x411425 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP5_PCIE_TX_ACK_LATENCY_LIMIT 0 0x411426 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP5_PCIE_TX_NOP_DLLP 0 0x411427 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP5_PCIE_TX_CNTL_2 0 0x411428 0 0 5 regBIFP5_PCIE_TX_SKID_CTRL 0 0x41142f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP5_PCIE_TX_CREDITS_ADVT_P 0 0x411430 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP5_PCIE_TX_CREDITS_ADVT_NP 0 0x411431 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP5_PCIE_TX_CREDITS_ADVT_CPL 0 0x411432 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP5_PCIE_TX_CREDITS_INIT_P 0 0x411433 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP5_PCIE_TX_CREDITS_INIT_NP 0 0x411434 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP5_PCIE_TX_CREDITS_INIT_CPL 0 0x411435 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP5_PCIE_TX_CREDITS_STATUS 0 0x411436 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x411437 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP5_PCIE_TX_CCIX_PORT_CNTL0 0 0x411438 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP5_PCIE_TX_CCIX_PORT_CNTL1 0 0x411439 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP5_PCIE_CCIX_STACKED_BASE 0 0x41143a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP5_PCIE_CCIX_STACKED_LIMIT 0 0x41143b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP5_PCIE_CCIX_MISC_STATUS 0 0x411441 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP5_PCIE_P_PORT_LANE_STATUS 0 0x411450 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP5_PCIE_FC_P 0 0x411460 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP5_PCIE_FC_NP 0 0x411461 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP5_PCIE_FC_CPL 0 0x411462 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP5_PCIE_FC_P_VC1 0 0x411463 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP5_PCIE_FC_NP_VC1 0 0x411464 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP5_PCIE_FC_CPL_VC1 0 0x411465 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP5_PCIE_ERR_CNTL 0 0x41146a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP5_PCIE_RX_CNTL 0 0x411470 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP5_PCIE_RX_EXPECTED_SEQNUM 0 0x411471 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP5_PCIE_RX_VENDOR_SPECIFIC 0 0x411472 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP5_PCIE_RX_CNTL3 0 0x411474 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP5_PCIE_RX_CREDITS_ALLOCATED_P 0 0x411480 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x411481 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x411482 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP5_PCIEP_ERROR_INJECT_PHYSICAL 0 0x411483 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP5_PCIEP_ERROR_INJECT_TRANSACTION 0 0x411484 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP5_PCIEP_NAK_COUNTER 0 0x411486 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x411488 0 0 5 regBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x411489 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41148c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP5_PCIE_AER_PRIV_TRIGGER 0 0x41148d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP5_PCIE_LC_CNTL 0 0x4114a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP5_PCIE_LC_TRAINING_CNTL 0 0x4114a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP5_PCIE_LC_LINK_WIDTH_CNTL 0 0x4114a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP5_PCIE_LC_N_FTS_CNTL 0 0x4114a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP5_PCIE_LC_SPEED_CNTL 0 0x4114a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP5_PCIE_LC_STATE0 0 0x4114a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP5_PCIE_LC_STATE1 0 0x4114a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP5_PCIE_LC_STATE2 0 0x4114a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP5_PCIE_LC_STATE3 0 0x4114a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP5_PCIE_LC_STATE4 0 0x4114a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP5_PCIE_LC_STATE5 0 0x4114aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP5_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4114ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP5_PCIE_LC_CNTL2 0 0x4114b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP5_PCIE_LC_BW_CHANGE_CNTL 0 0x4114b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP5_PCIE_LC_CDR_CNTL 0 0x4114b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP5_PCIE_LC_LANE_CNTL 0 0x4114b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP5_PCIE_LC_CNTL3 0 0x4114b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP5_PCIE_LC_CNTL4 0 0x4114b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP5_PCIE_LC_CNTL5 0 0x4114b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP5_PCIE_LC_FORCE_COEFF 0 0x4114b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP5_PCIE_LC_BEST_EQ_SETTINGS 0 0x4114b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4114ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP5_PCIE_LC_CNTL6 0 0x4114bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP5_PCIE_LC_CNTL7 0 0x4114bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP5_PCIE_LINK_MANAGEMENT_STATUS 0 0x4114bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP5_PCIE_LINK_MANAGEMENT_MASK 0 0x4114be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP5_PCIE_LINK_MANAGEMENT_CNTL 0 0x4114bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP5_PCIEP_STRAP_LC 0 0x4114c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP5_PCIEP_STRAP_MISC 0 0x4114c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP5_PCIEP_STRAP_LC2 0 0x4114c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP5_PCIE_LC_L1_PM_SUBSTATE 0 0x4114c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP5_PCIE_LC_L1_PM_SUBSTATE2 0 0x4114c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP5_PCIE_LC_PORT_ORDER 0 0x4114c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP5_PCIEP_BCH_ECC_CNTL 0 0x4114d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP5_PCIEP_HPGI_PRIVATE 0 0x4114d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP5_PCIEP_HPGI 0 0x4114da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP5_PCIEP_HCNT_DESCRIPTOR 0 0x4114db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4114dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP5_PCIE_LC_CNTL8 0 0x4114dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP5_PCIE_LC_CNTL9 0 0x4114de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP5_PCIE_LC_FORCE_COEFF2 0 0x4114df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4114e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4114e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4114e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP5_PCIE_LC_CNTL10 0 0x4114e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP5_PCIE_LC_CNTL11 0 0x4114e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP5_PCIE_LC_CNTL12 0 0x4114e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP5_PCIE_LC_SAVE_RESTORE_1 0 0x4114e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP5_PCIE_LC_SAVE_RESTORE_2 0 0x4114e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP5_PCIE_LC_SAVE_RESTORE_3 0 0x4114e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regBIFP6_PCIEP_RESERVED 0 0x411800 1 0 5 RESERVED 0 31 regBIFP6_PCIEP_SCRATCH 0 0x411801 1 0 5 PCIEP_SCRATCH 0 31 regBIFP6_PCIEP_PORT_CNTL 0 0x411810 10 0 5 SLV_PORT_REQ_EN 0 0 CI_SNOOP_OVERRIDE 1 1 HOTPLUG_MSG_EN 2 2 NATIVE_PME_EN 3 3 PWR_FAULT_EN 4 4 PMI_BM_DIS 5 5 CI_SLV_CPL_STATIC_ALLOC_LIMIT_S 8 17 CI_PRIV_MAX_CPL_PAYLOAD_SIZE 18 20 CI_SLV_RSP_POISONED_UR_MODE 24 25 CI_MAX_CPL_PAYLOAD_SIZE_MODE 26 27 regBIFP6_PCIE_TX_CNTL 0 0x411820 9 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_PACK_PACKET_DIS 14 14 TX_FLUSH_TLP_DIS 15 15 TX_CPL_PASS_P 20 20 TX_NP_PASS_P 21 21 TX_CLEAR_EXTRA_PM_REQS 22 22 TX_FC_UPDATE_TIMEOUT_DIS 23 23 TX_SWAP_RTRC_WITH_BFRC_ENABLE 27 27 regBIFP6_PCIE_TX_REQUESTER_ID 0 0x411821 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regBIFP6_PCIE_TX_VENDOR_SPECIFIC 0 0x411822 2 0 5 TX_VENDOR_DATA 0 23 TX_VENDOR_SEND 24 24 regBIFP6_PCIE_TX_REQUEST_NUM_CNTL 0 0x411823 3 0 5 TX_NUM_OUTSTANDING_NP 24 29 TX_NUM_OUTSTANDING_NP_VC1_EN 30 30 TX_NUM_OUTSTANDING_NP_EN 31 31 regBIFP6_PCIE_TX_SEQ 0 0x411824 2 0 5 TX_NEXT_TRANSMIT_SEQ 0 11 TX_ACKD_SEQ 16 27 regBIFP6_PCIE_TX_REPLAY 0 0x411825 4 0 5 TX_REPLAY_NUM 0 2 TX_REPLAY_TIMER_DIS 14 14 TX_REPLAY_TIMER_OVERWRITE 15 15 TX_REPLAY_TIMER 16 31 regBIFP6_PCIE_TX_ACK_LATENCY_LIMIT 0 0x411826 2 0 5 TX_ACK_LATENCY_LIMIT 0 11 TX_ACK_LATENCY_LIMIT_OVERWRITE 12 12 regBIFP6_PCIE_TX_NOP_DLLP 0 0x411827 2 0 5 TX_NOP_DATA 0 23 TX_NOP_SEND 24 24 regBIFP6_PCIE_TX_CNTL_2 0 0x411828 0 0 5 regBIFP6_PCIE_TX_SKID_CTRL 0 0x41182f 2 0 5 TX_SKID_CREDIT_LIMIT 0 3 TX_SKID_CREDIT_OVERRIDE_EN 4 4 regBIFP6_PCIE_TX_CREDITS_ADVT_P 0 0x411830 2 0 5 TX_CREDITS_ADVT_PD 0 13 TX_CREDITS_ADVT_PH 16 25 regBIFP6_PCIE_TX_CREDITS_ADVT_NP 0 0x411831 2 0 5 TX_CREDITS_ADVT_NPD 0 13 TX_CREDITS_ADVT_NPH 16 25 regBIFP6_PCIE_TX_CREDITS_ADVT_CPL 0 0x411832 2 0 5 TX_CREDITS_ADVT_CPLD 0 13 TX_CREDITS_ADVT_CPLH 16 25 regBIFP6_PCIE_TX_CREDITS_INIT_P 0 0x411833 2 0 5 TX_CREDITS_INIT_PD 0 11 TX_CREDITS_INIT_PH 16 23 regBIFP6_PCIE_TX_CREDITS_INIT_NP 0 0x411834 2 0 5 TX_CREDITS_INIT_NPD 0 11 TX_CREDITS_INIT_NPH 16 23 regBIFP6_PCIE_TX_CREDITS_INIT_CPL 0 0x411835 2 0 5 TX_CREDITS_INIT_CPLD 0 11 TX_CREDITS_INIT_CPLH 16 23 regBIFP6_PCIE_TX_CREDITS_STATUS 0 0x411836 12 0 5 TX_CREDITS_ERR_PD 0 0 TX_CREDITS_ERR_PH 1 1 TX_CREDITS_ERR_NPD 2 2 TX_CREDITS_ERR_NPH 3 3 TX_CREDITS_ERR_CPLD 4 4 TX_CREDITS_ERR_CPLH 5 5 TX_CREDITS_CUR_STATUS_PD 16 16 TX_CREDITS_CUR_STATUS_PH 17 17 TX_CREDITS_CUR_STATUS_NPD 18 18 TX_CREDITS_CUR_STATUS_NPH 19 19 TX_CREDITS_CUR_STATUS_CPLD 20 20 TX_CREDITS_CUR_STATUS_CPLH 21 21 regBIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD 0 0x411837 6 0 5 TX_FCU_THRESHOLD_P_VC0 0 2 TX_FCU_THRESHOLD_NP_VC0 4 6 TX_FCU_THRESHOLD_CPL_VC0 8 10 TX_FCU_THRESHOLD_P_VC1 16 18 TX_FCU_THRESHOLD_NP_VC1 20 22 TX_FCU_THRESHOLD_CPL_VC1 24 26 regBIFP6_PCIE_TX_CCIX_PORT_CNTL0 0 0x411838 7 0 5 TXCCIX_REQATTR_MEMTYPE 0 2 TXCCIX_CCIX_TC 3 5 TXCCIX_MSG_REQ_NONSEC 6 6 TXCCIX_TGT_ID 8 13 TXCCIX_SRC_ID 16 21 RXCCIX_RECEIVE_OPT_HDR_EN 25 25 TXCCIX_MSG_REQ_QOS 28 31 regBIFP6_PCIE_TX_CCIX_PORT_CNTL1 0 0x411839 1 0 5 TXCCIX_PCIE_TGT_ROUTING_ID 0 15 regBIFP6_PCIE_CCIX_STACKED_BASE 0 0x41183a 1 0 5 CCIX_STACKED_ADDR_BASE 4 31 regBIFP6_PCIE_CCIX_STACKED_LIMIT 0 0x41183b 1 0 5 CCIX_STACKED_ADDR_LIMIT 4 31 regBIFP6_PCIE_CCIX_MISC_STATUS 0 0x411841 2 0 5 RXCCIX_ERR_POSTED_UR 0 0 RXCCIX_ERR_NON_POSTED_UR 1 1 regBIFP6_PCIE_P_PORT_LANE_STATUS 0 0x411850 2 0 5 PORT_LANE_REVERSAL 0 0 PHY_LINK_WIDTH 1 6 regBIFP6_PCIE_FC_P 0 0x411860 2 0 5 PD_CREDITS 0 15 PH_CREDITS 16 27 regBIFP6_PCIE_FC_NP 0 0x411861 2 0 5 NPD_CREDITS 0 15 NPH_CREDITS 16 27 regBIFP6_PCIE_FC_CPL 0 0x411862 2 0 5 CPLD_CREDITS 0 15 CPLH_CREDITS 16 27 regBIFP6_PCIE_FC_P_VC1 0 0x411863 2 0 5 ADVT_FC_VC1_PD_CREDITS 0 15 ADVT_FC_VC1_PH_CREDITS 16 27 regBIFP6_PCIE_FC_NP_VC1 0 0x411864 2 0 5 ADVT_FC_VC1_NPD_CREDITS 0 15 ADVT_FC_VC1_NPH_CREDITS 16 27 regBIFP6_PCIE_FC_CPL_VC1 0 0x411865 2 0 5 ADVT_FC_VC1_CPLD_CREDITS 0 15 ADVT_FC_VC1_CPLH_CREDITS 16 27 regBIFP6_PCIE_ERR_CNTL 0 0x41186a 16 0 5 ERR_REPORTING_DIS 0 0 STRAP_FIRST_RCVD_ERR_LOG 1 1 RX_DROP_ECRC_FAILURES 2 2 TX_GENERATE_LCRC_ERR 4 4 RX_GENERATE_LCRC_ERR 5 5 TX_GENERATE_ECRC_ERR 6 6 RX_GENERATE_ECRC_ERR 7 7 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 CI_P_SLV_BUF_RD_HALT_STATUS 14 14 CI_NP_SLV_BUF_RD_HALT_STATUS 15 15 CI_SLV_BUF_HALT_RESET 16 16 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_PRIV_MASK_BAD_DLLP 19 19 AER_PRIV_MASK_BAD_TLP 20 20 regBIFP6_PCIE_RX_CNTL 0 0x411870 27 0 5 RX_IGNORE_IO_ERR 0 0 RX_IGNORE_BE_ERR 1 1 RX_IGNORE_MSG_ERR 2 2 RX_IGNORE_CRC_ERR 3 3 RX_IGNORE_CFG_ERR 4 4 RX_IGNORE_CPL_ERR 5 5 RX_IGNORE_EP_ERR 6 6 RX_IGNORE_LEN_MISMATCH_ERR 7 7 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_IGNORE_CFG_UR 10 10 RX_IGNORE_IO_UR 11 11 RX_IGNORE_AT_ERR 12 12 RX_NAK_IF_FIFO_FULL 13 13 RX_FC_INIT_FROM_REG 15 15 RX_RCB_CPL_TIMEOUT 16 18 RX_RCB_CPL_TIMEOUT_MODE 19 19 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_CPLPREFIX_ERR 23 23 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 RX_RCB_FLR_TIMEOUT_DIS 27 27 CTO_MASK_PRIV 28 28 RX_SWAP_RTRC_TO_BFRC_ENABLE 29 29 regBIFP6_PCIE_RX_EXPECTED_SEQNUM 0 0x411871 1 0 5 RX_EXPECTED_SEQNUM 0 11 regBIFP6_PCIE_RX_VENDOR_SPECIFIC 0 0x411872 2 0 5 RX_VENDOR_DATA 0 23 RX_VENDOR_STATUS 24 24 regBIFP6_PCIE_RX_CNTL3 0 0x411874 5 0 5 RX_IGNORE_RC_TRANSMRDPASID_UR 0 0 RX_IGNORE_RC_TRANSMWRPASID_UR 1 1 RX_IGNORE_RC_PRGRESPMSG_UR 2 2 RX_IGNORE_RC_INVREQ_UR 3 3 RX_IGNORE_RC_INVCPLPASID_UR 4 4 regBIFP6_PCIE_RX_CREDITS_ALLOCATED_P 0 0x411880 2 0 5 RX_CREDITS_ALLOCATED_PD 0 11 RX_CREDITS_ALLOCATED_PH 16 23 regBIFP6_PCIE_RX_CREDITS_ALLOCATED_NP 0 0x411881 2 0 5 RX_CREDITS_ALLOCATED_NPD 0 11 RX_CREDITS_ALLOCATED_NPH 16 23 regBIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL 0 0x411882 2 0 5 RX_CREDITS_ALLOCATED_CPLD 0 11 RX_CREDITS_ALLOCATED_CPLH 16 23 regBIFP6_PCIEP_ERROR_INJECT_PHYSICAL 0 0x411883 12 0 5 ERROR_INJECT_PL_LANE_ERR 0 1 ERROR_INJECT_PL_FRAMING_ERR 2 3 ERROR_INJECT_PL_BAD_PARITY_IN_SKP 4 5 ERROR_INJECT_PL_BAD_LFSR_IN_SKP 6 7 ERROR_INJECT_PL_LOOPBACK_UFLOW 8 9 ERROR_INJECT_PL_LOOPBACK_OFLOW 10 11 ERROR_INJECT_PL_DESKEW_ERR 12 13 ERROR_INJECT_PL_8B10B_DISPARITY_ERR 14 15 ERROR_INJECT_PL_8B10B_DECODE_ERR 16 17 ERROR_INJECT_PL_SKP_OS_ERROR 18 19 ERROR_INJECT_PL_INV_OS_IDENTIFIER 20 21 ERROR_INJECT_PL_BAD_SYNC_HEADER 22 23 regBIFP6_PCIEP_ERROR_INJECT_TRANSACTION 0 0x411884 10 0 5 ERROR_INJECT_TL_FLOW_CTL_ERR 0 1 ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER 2 3 ERROR_INJECT_TL_BAD_DLLP 4 5 ERROR_INJECT_TL_BAD_TLP 6 7 ERROR_INJECT_TL_UNSUPPORTED_REQ 8 9 ERROR_INJECT_TL_ECRC_ERROR 10 11 ERROR_INJECT_TL_MALFORMED_TLP 12 13 ERROR_INJECT_TL_UNEXPECTED_CMPLT 14 15 ERROR_INJECT_TL_COMPLETER_ABORT 16 17 ERROR_INJECT_TL_COMPLETION_TIMEOUT 18 19 regBIFP6_PCIEP_NAK_COUNTER 0 0x411886 2 0 5 RX_NUM_NAK_RECEIVED_PORT 0 15 RX_NUM_NAK_GENERATED_PORT 16 31 regBIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS 0 0x411888 0 0 5 regBIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES 0 0x411889 6 0 5 RX_LTR_SNOOP_THRESHOLD_VALUE 0 9 RX_LTR_SNOOP_THRESHOLD_SCALE 10 12 RX_LTR_SNOOP_THRESHOLD_REQR 15 15 RX_LTR_NONSNOOP_THRESHOLD_VALUE 16 25 RX_LTR_NONSNOOP_THRESHOLD_SCALE 26 28 RX_LTR_NONSNOOP_THRESHOLD_REQR 31 31 regBIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK 0 0x41188c 1 0 5 PRIV_SURP_DOWN_MASK 5 5 regBIFP6_PCIE_AER_PRIV_TRIGGER 0 0x41188d 3 0 5 PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION 0 0 PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE 1 1 PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES 2 2 regBIFP6_PCIE_LC_CNTL 0 0x4118a0 20 0 5 LC_DONT_ENTER_L23_IN_D0 1 1 LC_RESET_L_IDLE_COUNT_EN 2 2 LC_RESET_LINK 3 3 LC_16X_CLEAR_TX_PIPE 4 7 LC_L0S_INACTIVITY 8 11 LC_L1_INACTIVITY 12 15 LC_PMI_TO_L1_DIS 16 16 LC_INC_N_FTS_EN 17 17 LC_LOOK_FOR_IDLE_IN_L1L23 18 19 LC_FACTOR_IN_EXT_SYNC 20 20 LC_WAIT_FOR_PM_ACK_DIS 21 21 LC_WAKE_FROM_L23 22 22 LC_L1_IMMEDIATE_ACK 23 23 LC_ASPM_TO_L1_DIS 24 24 LC_DELAY_COUNT 25 26 LC_DELAY_L0S_EXIT 27 27 LC_DELAY_L1_EXIT 28 28 LC_EXTEND_WAIT_FOR_EL_IDLE 29 29 LC_ESCAPE_L1L23_EN 30 30 LC_GATE_RCVR_IDLE 31 31 regBIFP6_PCIE_LC_TRAINING_CNTL 0 0x4118a1 25 0 5 LC_TRAINING_CNTL 0 3 LC_COMPLIANCE_RECEIVE 4 4 LC_LOOK_FOR_MORE_NON_MATCHING_TS1 5 5 LC_L0S_L1_TRAINING_CNTL_EN 6 6 LC_L1_LONG_WAKE_FIX_EN 7 7 LC_POWER_STATE 8 10 LC_DONT_GO_TO_L0S_IF_L1_ARMED 11 11 LC_INIT_SPD_CHG_WITH_CSR_EN 12 12 LC_DISABLE_TRAINING_BIT_ARCH 13 13 LC_WAIT_FOR_SETS_IN_RCFG 14 14 LC_HOT_RESET_QUICK_EXIT_EN 15 15 LC_EXTEND_WAIT_FOR_SKP 16 16 LC_AUTONOMOUS_CHANGE_OFF 17 17 LC_UPCONFIGURE_CAP_OFF 18 18 LC_HW_LINK_DIS_EN 19 19 LC_LINK_DIS_BY_HW 20 20 LC_STATIC_TX_PIPE_COUNT_EN 21 21 LC_ASPM_L1_NAK_TIMER_SEL 22 23 LC_DONT_DEASSERT_RX_EN_IN_R_SPEED 24 24 LC_DONT_DEASSERT_RX_EN_IN_TEST 25 25 LC_RESET_ASPM_L1_NAK_TIMER 26 26 LC_SHORT_RCFG_TIMEOUT 27 27 LC_ALLOW_TX_L1_CONTROL 28 28 LC_WAIT_FOR_FOM_VALID_AFTER_TRACK 29 29 LC_EXTEND_EQ_REQ_TIME 30 31 regBIFP6_PCIE_LC_LINK_WIDTH_CNTL 0 0x4118a2 25 0 5 LC_LINK_WIDTH 0 2 LC_LINK_WIDTH_RD 4 6 LC_RECONFIG_ARC_MISSING_ESCAPE 7 7 LC_RECONFIG_NOW 8 8 LC_RENEGOTIATION_SUPPORT 9 9 LC_RENEGOTIATE_EN 10 10 LC_SHORT_RECONFIG_EN 11 11 LC_UPCONFIGURE_SUPPORT 12 12 LC_UPCONFIGURE_DIS 13 13 LC_UPCFG_WAIT_FOR_RCVR_DIS 14 14 LC_UPCFG_TIMER_SEL 15 15 LC_L1_RECONFIG_EN 17 17 LC_DYNLINK_MST_EN 18 18 LC_DUAL_END_RECONFIG_EN 19 19 LC_UPCONFIGURE_CAPABLE 20 20 LC_DYN_LANES_PWR_STATE 21 22 LC_EQ_REVERSAL_LOGIC_EN 23 23 LC_MULT_REVERSE_ATTEMP_EN 24 24 LC_RESET_TSX_CNT_IN_RCONFIG_EN 25 25 LC_WAIT_FOR_L_IDLE_IN_R_IDLE 26 26 LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT 27 27 LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE 28 28 LC_BYPASS_RXL0S_ON_SHORT_EI 29 29 LC_TURN_OFF_UNUSED_LANES 30 30 LC_BYPASS_RXSTANDBY_STATUS 31 31 regBIFP6_PCIE_LC_N_FTS_CNTL 0 0x4118a3 8 0 5 LC_XMIT_N_FTS 0 7 LC_XMIT_N_FTS_OVERRIDE_EN 8 8 LC_XMIT_FTS_BEFORE_RECOVERY 9 9 LC_N_EIE_SEL 10 10 LC_XMIT_N_FTS_8GT_CNTL 14 14 LC_XMIT_N_FTS_16GT_CNTL 15 15 LC_XMIT_N_FTS_LIMIT 16 23 LC_N_FTS 24 31 regBIFP6_PCIE_LC_SPEED_CNTL 0 0x4118a4 28 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 LC_TARGET_LINK_SPEED_OVERRIDE_EN 3 3 LC_TARGET_LINK_SPEED_OVERRIDE 4 5 LC_FORCE_EN_SW_SPEED_CHANGE 6 6 LC_FORCE_DIS_SW_SPEED_CHANGE 7 7 LC_FORCE_EN_HW_SPEED_CHANGE 8 8 LC_FORCE_DIS_HW_SPEED_CHANGE 9 9 LC_INITIATE_LINK_SPEED_CHANGE 10 10 LC_SPEED_CHANGE_ATTEMPTS_ALLOWED 11 12 LC_SPEED_CHANGE_ATTEMPT_FAILED 13 13 LC_CURRENT_DATA_RATE 14 15 LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS 16 16 LC_CLR_FAILED_SPD_CHANGE_CNT 17 17 LC_1_OR_MORE_TS2_SPEED_ARC_EN 18 18 LC_OTHER_SIDE_EVER_SENT_GEN2 19 19 LC_OTHER_SIDE_SUPPORTS_GEN2 20 20 LC_OTHER_SIDE_EVER_SENT_GEN3 21 21 LC_OTHER_SIDE_SUPPORTS_GEN3 22 22 LC_OTHER_SIDE_EVER_SENT_GEN4 23 23 LC_OTHER_SIDE_SUPPORTS_GEN4 24 24 LC_SPEED_CHANGE_STATUS 25 25 LC_DATA_RATE_ADVERTISED 26 27 LC_CHECK_DATA_RATE 28 28 LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN 29 29 LC_INIT_SPEED_NEG_IN_L0s_EN 30 30 LC_INIT_SPEED_NEG_IN_L1_EN 31 31 regBIFP6_PCIE_LC_STATE0 0 0x4118a5 4 0 5 LC_CURRENT_STATE 0 5 LC_PREV_STATE1 8 13 LC_PREV_STATE2 16 21 LC_PREV_STATE3 24 29 regBIFP6_PCIE_LC_STATE1 0 0x4118a6 4 0 5 LC_PREV_STATE4 0 5 LC_PREV_STATE5 8 13 LC_PREV_STATE6 16 21 LC_PREV_STATE7 24 29 regBIFP6_PCIE_LC_STATE2 0 0x4118a7 4 0 5 LC_PREV_STATE8 0 5 LC_PREV_STATE9 8 13 LC_PREV_STATE10 16 21 LC_PREV_STATE11 24 29 regBIFP6_PCIE_LC_STATE3 0 0x4118a8 4 0 5 LC_PREV_STATE12 0 5 LC_PREV_STATE13 8 13 LC_PREV_STATE14 16 21 LC_PREV_STATE15 24 29 regBIFP6_PCIE_LC_STATE4 0 0x4118a9 4 0 5 LC_PREV_STATE16 0 5 LC_PREV_STATE17 8 13 LC_PREV_STATE18 16 21 LC_PREV_STATE19 24 29 regBIFP6_PCIE_LC_STATE5 0 0x4118aa 4 0 5 LC_PREV_STATE20 0 5 LC_PREV_STATE21 8 13 LC_PREV_STATE22 16 21 LC_PREV_STATE23 24 29 regBIFP6_PCIE_LINK_MANAGEMENT_CNTL2 0 0x4118ab 13 0 5 QUIESCE_RCVD 0 0 QUIESCE_SENT 1 1 REQ_EQ_RCVD 2 2 REQ_EQ_SENT 3 3 BW_HINT_MODE 4 4 BW_HINT_TX_EN 5 5 BW_HINT_RX_EN 6 6 LOW_BW_THRESHOLD_G2 7 10 HIGH_BW_THRESHOLD_G2 11 14 LOW_BW_THRESHOLD_G3 15 18 HIGH_BW_THRESHOLD_G3 19 22 LOW_BW_THRESHOLD_G4 23 26 HIGH_BW_THRESHOLD_G4 27 30 regBIFP6_PCIE_LC_CNTL2 0 0x4118b1 24 0 5 LC_TIMED_OUT_STATE 0 5 LC_STATE_TIMED_OUT 6 6 LC_LOOK_FOR_BW_REDUCTION 7 7 LC_MORE_TS2_EN 8 8 LC_X12_NEGOTIATION_DIS 9 9 LC_LINK_UP_REVERSAL_EN 10 10 LC_ILLEGAL_STATE 11 11 LC_ILLEGAL_STATE_RESTART_EN 12 12 LC_WAIT_FOR_OTHER_LANES_MODE 13 13 LC_ELEC_IDLE_MODE 14 15 LC_DISABLE_INFERRED_ELEC_IDLE_DET 16 16 LC_ALLOW_PDWN_IN_L1 17 17 LC_ALLOW_PDWN_IN_L23 18 18 LC_CONSECUTIVE_EIOS_RESET_EN 19 19 LC_BLOCK_EL_IDLE_IN_L0 20 20 LC_RCV_L0_TO_RCV_L0S_DIS 21 21 LC_ASSERT_INACTIVE_DURING_HOLD 22 22 LC_WAIT_FOR_LANES_IN_LW_NEG 23 24 LC_PWR_DOWN_NEG_OFF_LANES 25 25 LC_DISABLE_LOST_SYM_LOCK_ARCS 26 26 LC_LINK_BW_NOTIFICATION_DIS 27 27 LC_PMI_L1_WAIT_FOR_SLV_IDLE 28 28 LC_TEST_TIMER_SEL 29 30 LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI 31 31 regBIFP6_PCIE_LC_BW_CHANGE_CNTL 0 0x4118b2 12 0 5 LC_BW_CHANGE_INT_EN 0 0 LC_HW_INIT_SPEED_CHANGE 1 1 LC_SW_INIT_SPEED_CHANGE 2 2 LC_OTHER_INIT_SPEED_CHANGE 3 3 LC_RELIABILITY_SPEED_CHANGE 4 4 LC_FAILED_SPEED_NEG 5 5 LC_LONG_LW_CHANGE 6 6 LC_SHORT_LW_CHANGE 7 7 LC_LW_CHANGE_OTHER 8 8 LC_LW_CHANGE_FAILED 9 9 LC_LINK_BW_NOTIFICATION_DETECT_MODE 10 10 LC_SPEED_NEG_UNSUCCESSFUL 11 11 regBIFP6_PCIE_LC_CDR_CNTL 0 0x4118b3 3 0 5 LC_CDR_TEST_OFF 0 11 LC_CDR_TEST_SETS 12 23 LC_CDR_SET_TYPE 24 25 regBIFP6_PCIE_LC_LANE_CNTL 0 0x4118b4 1 0 5 LC_CORRUPTED_LANES 0 15 regBIFP6_PCIE_LC_CNTL3 0 0x4118b5 24 0 5 LC_SELECT_DEEMPHASIS 0 0 LC_SELECT_DEEMPHASIS_CNTL 1 2 LC_RCVD_DEEMPHASIS 3 3 LC_COMP_TO_DETECT 4 4 LC_RESET_TSX_CNT_IN_RLOCK_EN 5 5 LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED 6 7 LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED 8 8 LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT 9 9 LC_ENHANCED_HOT_PLUG_EN 10 10 LC_RCVR_DET_EN_OVERRIDE 11 11 LC_LINK_DOWN_SPD_CHG_EN 12 12 LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ 13 13 LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE 14 14 LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY 15 15 LC_L1_BLOCK_RECONFIG_EN 17 17 LC_AUTO_DISABLE_SPEED_SUPPORT_EN 18 18 LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL 19 20 LC_FAST_L1_ENTRY_EXIT_EN 21 21 LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT 22 22 LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK 23 23 LC_HW_VOLTAGE_IF_CONTROL 24 25 LC_VOLTAGE_TIMER_SEL 26 29 LC_GO_TO_RECOVERY 30 30 LC_AUTO_RECOVERY_DIS 31 31 regBIFP6_PCIE_LC_CNTL4 0 0x4118b6 22 0 5 LC_TX_ENABLE_BEHAVIOUR 0 1 LC_DIS_CONTIG_END_SET_CHECK 2 2 LC_DIS_ASPM_L1_IN_SPEED_CHANGE 3 3 LC_BYPASS_EQ_8GT 4 4 LC_REDO_EQ_8GT 5 5 LC_EXTEND_EIEOS 6 6 LC_IGNORE_PARITY 7 7 LC_EQ_SEARCH_MODE_8GT 8 9 LC_DSC_CHECK_COEFFS_IN_RLOCK 10 10 LC_USC_EQ_NOT_REQD_8GT 11 11 LC_USC_GO_TO_EQ_8GT 12 12 LC_SET_QUIESCE 13 13 LC_QUIESCE_RCVD 14 14 LC_UNEXPECTED_COEFFS_RCVD_8GT 15 15 LC_BYPASS_EQ_REQ_PHASE_8GT 16 16 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT 17 17 LC_FORCE_PRESET_VALUE_8GT 18 21 LC_USC_DELAY_DLLPS 22 22 LC_TX_SWING 23 23 LC_EQ_WAIT_FOR_EVAL_DONE 24 24 LC_8GT_SKIP_ORDER_EN 25 25 LC_WAIT_FOR_MORE_TS_IN_RLOCK 26 31 regBIFP6_PCIE_LC_CNTL5 0 0x4118b7 13 0 5 LC_LOCAL_EQ_SETTINGS_RATE 0 1 LC_LOCAL_PRESET 2 5 LC_LOCAL_PRE_CURSOR 6 9 LC_LOCAL_CURSOR 10 15 LC_LOCAL_POST_CURSOR 16 20 LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN 21 21 LC_SAFE_RECOVER_CNTL 22 23 LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS 24 24 LC_TX_SWING_OVERRIDE 25 25 LC_ACCEPT_ALL_PRESETS 26 26 LC_ACCEPT_ALL_PRESETS_TEST 27 27 LC_WAIT_IN_DETECT 28 28 LC_HOLD_TRAINING_MODE 29 31 regBIFP6_PCIE_LC_FORCE_COEFF 0 0x4118b8 6 0 5 LC_FORCE_COEFF_8GT 0 0 LC_FORCE_PRE_CURSOR_8GT 1 6 LC_FORCE_CURSOR_8GT 7 12 LC_FORCE_POST_CURSOR_8GT 13 18 LC_3X3_COEFF_SEARCH_EN_8GT 19 19 LC_PRESET_10_EN 20 20 regBIFP6_PCIE_LC_BEST_EQ_SETTINGS 0 0x4118b9 6 0 5 LC_BEST_PRESET 0 3 LC_BEST_PRECURSOR 4 9 LC_BEST_CURSOR 10 15 LC_BEST_POSTCURSOR 16 21 LC_BEST_FOM 22 29 LC_BEST_SETTINGS_RATE 30 30 regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF 0 0x4118ba 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT 0 0 LC_FORCE_PRE_CURSOR_REQ_8GT 1 6 LC_FORCE_CURSOR_REQ_8GT 7 12 LC_FORCE_POST_CURSOR_REQ_8GT 13 18 LC_FS_OTHER_END_8GT 19 24 LC_LF_OTHER_END_8GT 25 30 regBIFP6_PCIE_LC_CNTL6 0 0x4118bb 17 0 5 LC_SPC_MODE_2P5GT 0 1 LC_SPC_MODE_5GT 2 3 LC_SPC_MODE_8GT 4 5 LC_SPC_MODE_16GT 6 7 LC_SRIS_EN 8 8 LC_SRNS_SKIP_IN_SRIS 9 12 LC_SRIS_AUTODETECT_EN 13 13 LC_SRIS_AUTODETECT_FACTOR 14 15 LC_SRIS_AUTODETECT_MODE 16 17 LC_SRIS_AUTODETECT_OUT_OF_RANGE 18 18 LC_DEFER_SKIP_FOR_EIEOS_EN 19 19 LC_SEND_EIEOS_IN_RCFG 20 20 LC_L1_POWERDOWN 21 21 LC_P2_ENTRY 22 22 LC_RXRECOVER_EN 23 23 LC_RXRECOVER_TIMEOUT 24 30 LC_RX_L0S_STANDBY_EN 31 31 regBIFP6_PCIE_LC_CNTL7 0 0x4118bc 24 0 5 LC_EXPECTED_TS2_CFG_COMPLETE 0 0 LC_IGNORE_NON_CONTIG_SETS_IN_RCFG 1 1 LC_ROBUST_TRAINING_BIT_CHK_EN 2 2 LC_RESET_TS_COUNT_ON_EI 3 3 LC_NBIF_ASPM_INPUT_EN 4 4 LC_CLEAR_REVERSE_ATTEMPT_IN_L0 5 5 LC_LOCK_REVERSAL 6 6 LC_FORCE_RX_EQ_IN_PROGRESS 7 7 LC_EVER_IDLE_TO_RLOCK 8 8 LC_RXEQEVAL_AFTER_TIMEOUT_EN 9 9 LC_WAIT_FOR_LANES_IN_CONFIG 10 10 LC_REQ_COEFFS_FOR_TXMARGIN_EN 11 11 LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1 12 12 LC_SCHEDULED_RXEQEVAL_INTERVAL 13 20 LC_SCHEDULED_RXEQEVAL_MODE 21 21 LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN 22 22 LC_LINK_MANAGEMENT_EN 23 23 LC_AUTO_REJECT_AFTER_TIMEOUT 24 24 LC_ESM_RATES 25 26 LC_ESM_PLL_INIT_STATE 27 27 LC_ESM_PLL_INIT_DONE 28 28 LC_ESM_REDO_INIT 29 29 LC_MULTIPORT_ESM 30 30 LC_ESM_ENTRY_MODE 31 31 regBIFP6_PCIE_LINK_MANAGEMENT_STATUS 0 0x4118bd 14 0 5 LINK_SPEED_UPDATE 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE 2 2 LINK_WIDTH_UPDATE 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE 5 5 POWER_DOWN_COMMAND_COMPLETE 6 6 BANDWIDTH_UPDATE 7 7 LINK_POWER_STATE_CHANGE 8 8 BW_REQUIREMENT_HINT 9 9 EQUALIZATION_REQUEST 10 10 LINK_PARTNER_ESM_REQUEST 11 11 LOW_SPEED_REQD_IMMEDIATE 12 12 ESTABLISH_ESM_PLL_SETTINGS 13 13 regBIFP6_PCIE_LINK_MANAGEMENT_MASK 0 0x4118be 14 0 5 LINK_SPEED_UPDATE_MASK 0 0 LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 1 1 LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 2 2 LINK_WIDTH_UPDATE_MASK 3 3 LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 4 4 LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 5 5 POWER_DOWN_COMMAND_COMPLETE_MASK 6 6 BANDWIDTH_UPDATE_MASK 7 7 LINK_POWER_STATE_CHANGE_MASK 8 8 BW_REQUIREMENT_HINT_MASK 9 9 EQUALIZATION_REQUEST_MASK 10 10 LINK_PARTNER_ESM_REQUEST_MASK 11 11 LOW_SPEED_REQD_IMMEDIATE_MASK 12 12 ESTABLISH_ESM_PLL_SETTINGS_MASK 13 13 regBIFP6_PCIE_LINK_MANAGEMENT_CNTL 0 0x4118bf 14 0 5 FAR_END_WIDTH_SUPPORT 0 2 LINK_POWER_STATE 3 6 LINK_POWER_STATE_MASK 7 10 LINK_UP 11 11 PORT_POWERED_DOWN 12 12 SPC_MODE 13 14 CLOCK_RATE 15 16 LOW_BW_HINT 17 17 HIGH_BW_HINT 18 18 LOW_BW_THRESHOLD 19 22 HIGH_BW_THRESHOLD 23 26 BW_HINT_COUNT 27 29 EQ_REQ_RCVD_8GT 30 30 EQ_REQ_RCVD_16GT 31 31 regBIFP6_PCIEP_STRAP_LC 0 0x4118c0 14 0 5 STRAP_FTS_yTSx_COUNT 0 1 STRAP_LONG_yTSx_COUNT 2 3 STRAP_MED_yTSx_COUNT 4 5 STRAP_SHORT_yTSx_COUNT 6 7 STRAP_SKIP_INTERVAL 8 10 STRAP_BYPASS_RCVR_DET 11 11 STRAP_COMPLIANCE_DIS 12 12 STRAP_FORCE_COMPLIANCE 13 13 STRAP_REVERSE_LC_LANES 14 14 STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS 15 15 STRAP_LANE_NEGOTIATION 16 18 STRAP_MARGINING_USES_SOFTWARE 19 19 STRAP_RTM1_PRESENCE_DET_SUPP 20 20 STRAP_RTM2_PRESENCE_DET_SUPP 21 21 regBIFP6_PCIEP_STRAP_MISC 0 0x4118c1 7 0 5 STRAP_REVERSE_LANES 0 0 STRAP_E2E_PREFIX_EN 1 1 STRAP_EXTENDED_FMT_SUPPORTED 2 2 STRAP_OBFF_SUPPORTED 3 4 STRAP_LTR_SUPPORTED 5 5 STRAP_CCIX_EN 6 6 STRAP_CCIX_OPT_TLP_FMT_SUPPORT 7 7 regBIFP6_PCIEP_STRAP_LC2 0 0x4118c2 5 0 5 STRAP_ESM_MODE_SUPPORTED 0 0 STRAP_ESM_PHY_REACH_LEN_CAP 1 2 STRAP_ESM_RECAL_NEEDED 3 3 STRAP_ESM_CALIB_TIME 4 6 STRAP_ESM_QUICK_EQ_TIMEOUT 7 9 regBIFP6_PCIE_LC_L1_PM_SUBSTATE 0 0x4118c6 14 0 5 LC_L1_SUBSTATES_OVERRIDE_EN 0 0 LC_PCI_PM_L1_2_OVERRIDE 1 1 LC_PCI_PM_L1_1_OVERRIDE 2 2 LC_ASPM_L1_2_OVERRIDE 3 3 LC_ASPM_L1_1_OVERRIDE 4 4 LC_CLKREQ_FILTER_EN 5 5 LC_T_POWER_ON_SCALE 6 7 LC_T_POWER_ON_VALUE 8 12 LC_L1_1_POWERDOWN 16 18 LC_L1_2_POWERDOWN 20 22 LC_DEFER_L1_2_EXIT 23 25 LC_AUX_COUNT_REFCLK_INCREMENT_EN 26 26 LC_IGNORE_RX_ELEC_IDLE_IN_L1_2 27 27 LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY 28 28 regBIFP6_PCIE_LC_L1_PM_SUBSTATE2 0 0x4118c7 3 0 5 LC_CM_RESTORE_TIME 0 7 LC_LTR_THRESHOLD_SCALE 8 10 LC_LTR_THRESHOLD_VALUE 16 25 regBIFP6_PCIE_LC_PORT_ORDER 0 0x4118c8 1 0 5 LC_PORT_OFFSET 0 3 regBIFP6_PCIEP_BCH_ECC_CNTL 0 0x4118d0 3 0 5 STRAP_BCH_ECC_EN 0 0 BCH_ECC_ERROR_THRESHOLD 8 15 BCH_ECC_ERROR_STATUS 16 31 regBIFP6_PCIEP_HPGI_PRIVATE 0 0x4118d2 2 0 5 PRESENCE_DETECT_CHANGED_PRIVATE 3 3 PRESENCE_DETECT_STATE_PRIVATE 6 6 regBIFP6_PCIEP_HPGI 0 0x4118da 11 0 5 REG_HPGI_ASSERT_TO_SMI_EN 0 0 REG_HPGI_ASSERT_TO_SCI_EN 1 1 REG_HPGI_DEASSERT_TO_SMI_EN 2 2 REG_HPGI_DEASSERT_TO_SCI_EN 3 3 REG_HPGI_HOOK 7 7 HPGI_REG_ASSERT_TO_SMI_STATUS 8 8 HPGI_REG_ASSERT_TO_SCI_STATUS 9 9 HPGI_REG_DEASSERT_TO_SMI_STATUS 10 10 HPGI_REG_DEASSERT_TO_SCI_STATUS 11 11 HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS 15 15 REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN 16 16 regBIFP6_PCIEP_HCNT_DESCRIPTOR 0 0x4118db 2 0 5 HTPLG_CNTL_DESCRIPTOR_SLOT_NUM 0 12 HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE 31 31 regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK 0 0x4118dc 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP6_PCIE_LC_CNTL8 0 0x4118dd 20 0 5 LC_EQ_SEARCH_MODE_16GT 0 1 LC_BYPASS_EQ_16GT 2 2 LC_BYPASS_EQ_PRESET_16GT 3 6 LC_REDO_EQ_16GT 7 7 LC_USC_EQ_NOT_REQD_16GT 8 8 LC_USC_GO_TO_EQ_16GT 9 9 LC_UNEXPECTED_COEFFS_RCVD_16GT 10 10 LC_BYPASS_EQ_REQ_PHASE_16GT 11 11 LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT 12 12 LC_FORCE_PRESET_VALUE_16GT 13 16 LC_EQTS2_PRESET_EN 17 17 LC_EQTS2_PRESET 18 21 LC_USE_EQTS2_PRESET 22 22 LC_FOM_TIME 23 24 LC_SAFE_EQ_SEARCH 25 25 LC_DONT_CHECK_EQTS_IN_RCFG 26 26 LC_DELAY_COEFF_UPDATE_DIS 27 27 LC_8GT_EQ_REDO_EN 28 28 LC_WAIT_FOR_EIEOS_IN_RLOCK 29 29 LC_DYNAMIC_INACTIVE_TS_SELECT 30 31 regBIFP6_PCIE_LC_CNTL9 0 0x4118de 19 0 5 LC_OVERRIDE_RETIMER_PRESENCE_EN 0 0 LC_OVERRIDE_RETIMER_PRESENCE 1 2 LC_IGNORE_RETIMER_PRESENCE 3 3 LC_RETIMER_PRESENCE 4 5 LC_ESM_RATE0_TIMER_FACTOR 6 7 LC_ESM_RATE1_TIMER_FACTOR 8 9 LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG 10 10 LC_LOOPBACK_RXEQEVAL_EN 11 11 LC_EX_SEARCH_TRAVERSAL_MODE 12 12 LC_LOCK_IN_EQ_RESPONSE 13 13 LC_USC_ACCEPTABLE_PRESETS 14 23 LC_DSC_ACCEPT_8GT_EQ_REDO 24 24 LC_DSC_ACCEPT_16GT_EQ_REDO 25 25 LC_USC_HW_8GT_EQ_REDO_EN 26 26 LC_USC_HW_16GT_EQ_REDO_EN 27 27 LC_DELAY_DETECTED_TSX_RCV_EN 28 28 LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN 29 29 LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN 30 30 LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN 31 31 regBIFP6_PCIE_LC_FORCE_COEFF2 0 0x4118df 5 0 5 LC_FORCE_COEFF_16GT 0 0 LC_FORCE_PRE_CURSOR_16GT 1 6 LC_FORCE_CURSOR_16GT 7 12 LC_FORCE_POST_CURSOR_16GT 13 18 LC_3X3_COEFF_SEARCH_EN_16GT 19 19 regBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2 0 0x4118e0 6 0 5 LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT 0 0 LC_FORCE_PRE_CURSOR_REQ_16GT 1 6 LC_FORCE_CURSOR_REQ_16GT 7 12 LC_FORCE_POST_CURSOR_REQ_16GT 13 18 LC_FS_OTHER_END_16GT 19 24 LC_LF_OTHER_END_16GT 25 30 regBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC 0 0x4118e1 2 0 5 PERF_TXCLK_COUNTER 0 15 PERF_TXCLK_EVENT_SEL 16 23 regBIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES 0 0x4118e2 2 0 5 LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING 0 0 LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING 1 1 regBIFP6_PCIE_LC_CNTL10 0 0x4118e3 11 0 5 LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN 0 0 LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN 1 1 LC_ENH_PRESET_SEARCH_SEL_8GT 2 3 LC_ENH_PRESET_SEARCH_SEL_16GT 4 5 LC_PRESET_MASK_8GT 6 15 LC_PRESET_MASK_16GT 16 25 LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS 26 26 LC_TRAINING_BITS_REQUIRED 27 28 LC_REFCLK_OFF_NO_RCVR_LANES 29 29 LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION 30 30 LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION 31 31 regBIFP6_PCIE_LC_CNTL11 0 0x4118e4 22 0 5 LC_DEFAULT_PRESET_OVERRIDE_EN 0 0 LC_DEFAULT_PRESET_OVERRIDE_MODE 1 1 LC_DEFAULT_PRESET_OVERRIDE_PORT 2 2 LC_DEFAULT_PRESET_OVERRIDE_RATE 3 4 LC_DEFAULT_PRESET_OVERRIDE_VALUE 5 8 LC_DEFAULT_PRESET_OVERRIDE_LANE 9 12 LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES 13 13 LC_USE_SEPARATE_RXRECOVER_TIMER 14 14 LC_RXRECOVER_IN_POLL_ACTIVE_EN 15 15 LC_RXRECOVER_IN_CONFIG_EN 16 16 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK 17 17 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE 18 18 LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG 19 19 LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN 20 20 LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN 21 21 LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE 22 22 LC_LSLD_EN 23 23 LC_LSLD_RATE_REQD 24 25 LC_LSLD_MODE 26 26 LC_LSLD_DONE 27 27 LC_LSLD_TLS_ADVERTISED 28 29 LC_LSLD_CURRENT_RATE 30 31 regBIFP6_PCIE_LC_CNTL12 0 0x4118e5 25 0 5 LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE 0 0 LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN 1 1 LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0 2 2 LC_SKIP_LOCALPRESET_OFF_LANES 3 3 LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT 4 4 LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE 5 5 LC_FORCE_L1_PG_EXIT_ON_REG_WRITE 6 6 LC_EXTEND_EIEOS_MODE 7 7 LC_RXEQEVAL_WAIT_FOR_RXSTANDBY 8 8 LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1 9 9 LC_ALT_RX_EQ_IN_PROGRESS_EN 10 10 LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED 11 11 LC_QUICK_L1_1_ABORT_IN_L1 12 12 LC_DYN_LANES_L1_SS_POWERDOWN 13 13 LC_CLKGATE_WAIT_FOR_REFCLKACK 14 14 LC_QUICK_L1_2_ABORT_IN_L1 15 15 LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES 16 16 LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON 17 17 LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG 18 18 LC_ENSURE_TURN_OFF_DONE_LINKDIS 19 19 LC_CONFIG_WAIT_FOR_EIEOS 20 20 LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1 21 21 LC_BLOCK_NEAREND_L1_2_WAKEUP 22 22 LC_RECOVERY_WAIT_FOR_ASPM_NAK 23 23 LC_REFCLKREQ_IN_HOLD_TRAINING 31 31 regBIFP6_PCIE_LC_SAVE_RESTORE_1 0 0x4118e6 9 0 5 LC_SAVE_RESTORE_EN 0 0 LC_SAVE_RESTORE_DIRECTION 1 1 LC_SAVE_RESTORE_INDEX 2 9 LC_SAVE_RESTORE_ACKNOWLEDGE 10 10 LC_SAVE_RESTORE_DONE 11 11 LC_SAVE_RESTORE_FAST_RESTORE_EN 12 12 LC_SAVE_RESTORE_BYPASS_P2C_EN 13 13 LC_SAVE_RESTORE_SPEEDS 14 15 LC_SAVE_RESTORE_DATA_LO 16 31 regBIFP6_PCIE_LC_SAVE_RESTORE_2 0 0x4118e7 1 0 5 LC_SAVE_RESTORE_DATA_HI 0 31 regBIFP6_PCIE_LC_SAVE_RESTORE_3 0 0x4118e8 1 0 5 LC_SAVE_RESTORE_FORCE_NEAR_END_EN 0 0 regPCIE_RESERVED 0 0x420000 1 0 5 RESERVED 0 31 regPCIE_SCRATCH 0 0x420001 1 0 5 PCIE_SCRATCH 0 31 regPCIE_RX_NUM_NAK 0 0x42000e 1 0 5 RX_NUM_NAK 0 31 regPCIE_RX_NUM_NAK_GENERATED 0 0x42000f 1 0 5 RX_NUM_NAK_GENERATED 0 31 regPCIE_CNTL 0 0x420010 17 0 5 HWINIT_WR_LOCK 0 0 LC_HOT_PLUG_DELAY_SEL 1 3 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 PCIE_HT_NP_MEM_WRITE 9 9 RX_SB_ADJ_PAYLOAD_SIZE 10 12 RX_RCB_ATS_UC_DIS 15 15 RX_RCB_REORDER_EN 16 16 RX_RCB_INVALID_SIZE_DIS 17 17 RX_RCB_UNEXP_CPL_DIS 18 18 RX_RCB_CPL_TIMEOUT_TEST_MODE 19 19 RX_RCB_WRONG_PREFIX_DIS 20 20 RX_RCB_WRONG_ATTR_DIS 21 21 RX_RCB_WRONG_FUNCNUM_DIS 22 22 RX_ATS_TRAN_CPL_SPLIT_DIS 23 23 RX_IGNORE_LTR_MSG_UR 30 30 RX_CPL_POSTED_REQ_ORD_EN 31 31 regPCIE_CONFIG_CNTL 0 0x420011 14 0 5 DYN_CLK_LATENCY 0 3 CI_SWUS_MAX_PAYLOAD_SIZE_MODE 8 8 CI_SWUS_PRIV_MAX_PAYLOAD_SIZE 9 10 CI_10BIT_TAG_EN_OVERRIDE 11 12 CI_SWUS_10BIT_TAG_EN_OVERRIDE 13 14 CI_MAX_PAYLOAD_SIZE_MODE 16 16 CI_PRIV_MAX_PAYLOAD_SIZE 17 19 CI_MAX_READ_REQUEST_SIZE_MODE 20 20 CI_PRIV_MAX_READ_REQUEST_SIZE 21 23 CI_MAX_READ_SAFE_MODE 24 24 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE 27 27 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV 28 29 CI_SWUS_EXTENDED_TAG_EN_OVERRIDE 30 31 regPCIE_TX_TRACKING_ADDR_LO 0 0x420013 1 0 5 TX_TRACKING_ADDR_LO 2 31 regPCIE_TX_TRACKING_ADDR_HI 0 0x420014 1 0 5 TX_TRACKING_ADDR_HI 0 31 regPCIE_TX_TRACKING_CTRL_STATUS 0 0x420015 4 0 5 TX_TRACKING_ENABLE 0 0 TX_TRACKING_PORT 1 3 TX_TRACKING_UNIT_ID 8 14 TX_TRACKING_STATUS_VALID 15 15 regPCIE_TX_CTRL_4 0 0x420017 3 0 5 TX_ARB_VC_ROUND_ROBIN_EN 0 0 TX_ARB_VC0_LIMIT 1 5 TX_ARB_VC1_LIMIT 6 10 regPCIE_MST_CTRL_1 0 0x420018 7 0 5 MST_PDAT_CREDITS_ADVT 0 7 MST_PDAT_CREDITS_OVERRIDE_EN 8 8 MST_PHDR_CREDITS_PENDING_RESET_DIS 9 9 CI_MSTSDP_ORIG_DISC_FIX_DIS 10 10 MST_PHDR_CREDITS_OVERRIDE_EN 15 15 MST_PHDR_CREDITS_ADVT 16 23 MST_IDLE_HYSTERESIS 24 31 regPCIE_COMMON_AER_MASK 0 0x42001a 1 0 5 PRIV_SURP_DIS_VEC 0 7 regPCIE_CNTL2 0 0x42001c 19 0 5 TX_ARB_ROUND_ROBIN_EN 0 0 TX_ARB_SLV_LIMIT 1 5 TX_ARB_MST_LIMIT 6 10 TX_BLOCK_TLP_ON_PM_DIS 11 11 TX_NP_MEM_WRITE_SWP_ENCODING 12 12 TX_ATOMIC_OPS_DISABLE 13 13 TX_ATOMIC_ORDERING_DIS 14 14 SLV_MEM_LS_EN 16 16 SLV_MEM_AGGRESSIVE_LS_EN 17 17 MST_MEM_LS_EN 18 18 REPLAY_MEM_LS_EN 19 19 SLV_MEM_SD_EN 20 20 SLV_MEM_AGGRESSIVE_SD_EN 21 21 MST_MEM_SD_EN 22 22 REPLAY_MEM_SD_EN 23 23 RX_NP_MEM_WRITE_ENCODING 24 28 SLV_MEM_DS_EN 29 29 MST_MEM_DS_EN 30 30 REPLAY_MEM_DS_EN 31 31 regPCIE_RX_CNTL2 0 0x42001d 14 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 RX_IGNORE_EP_TRANSMRD_UR 1 1 RX_IGNORE_EP_TRANSMWR_UR 2 2 RX_IGNORE_EP_ATSTRANSREQ_UR 3 3 RX_IGNORE_EP_PAGEREQMSG_UR 4 4 RX_IGNORE_EP_INVCPL_UR 5 5 RX_RCB_LATENCY_EN 8 8 RX_RCB_LATENCY_SCALE 9 11 SLVCPL_MEM_LS_EN 12 12 SLVCPL_MEM_SD_EN 13 13 SLVCPL_MEM_DS_EN 14 14 RX_RCB_LATENCY_MAX_COUNT 16 25 FLR_EXTEND_MODE 28 30 RX_PD_OVERFLOW_FIX_DISABLE 31 31 regPCIE_TX_F0_ATTR_CNTL 0 0x42001e 7 0 5 TX_F0_IDO_OVERRIDE_P 0 1 TX_F0_IDO_OVERRIDE_NP 2 3 TX_F0_IDO_OVERRIDE_CPL 4 5 TX_F0_RO_OVERRIDE_P 6 7 TX_F0_RO_OVERRIDE_NP 8 9 TX_F0_SNR_OVERRIDE_P 10 11 TX_F0_SNR_OVERRIDE_NP 12 13 regPCIE_TX_SWUS_ATTR_CNTL 0 0x42001f 7 0 5 TX_SWUS_IDO_OVERRIDE_P 0 1 TX_SWUS_IDO_OVERRIDE_NP 2 3 TX_SWUS_IDO_OVERRIDE_CPL 4 5 TX_SWUS_RO_OVERRIDE_P 6 7 TX_SWUS_RO_OVERRIDE_NP 8 9 TX_SWUS_SNR_OVERRIDE_P 10 11 TX_SWUS_SNR_OVERRIDE_NP 12 13 regPCIE_CI_CNTL 0 0x420020 24 0 5 CI_SLAVE_SPLIT_MODE 2 2 CI_MST_CMPL_DUMMY_DATA 4 4 CI_SLV_RC_RD_REQ_SIZE 6 7 CI_SLV_ORDERING_DIS 8 8 CI_RC_ORDERING_DIS 9 9 CI_SLV_CPL_ALLOC_DIS 10 10 CI_SLV_CPL_ALLOC_MODE 11 11 CI_SLV_CPL_ALLOC_SOR 12 12 CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS 16 16 TX_PRIV_TLP_PREFIX_BLOCKING_DIS 17 17 TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS 18 18 TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS 19 19 PRIV_AUTO_SLOT_PWR_LIMIT_DIS 20 20 TX_DISABLE_SLOT_PWR_LIMIT_MSG 21 21 RX_RCB_RC_CTO_TO_UR_EN 22 22 RX_RCB_RC_DPC_EXCEPTION_EN 23 23 RX_RCB_RC_DPC_CPL_CTL_EN 24 24 CI_MSTSPLIT_DIS 25 25 CI_MSTSPLIT_REQ_CHAIN_DIS 26 26 TX_MWR_SPLIT_QW_PKT_SAFE_MODE 27 27 CI_MST_TAG_BORROWING_DIS 28 28 RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN 29 29 SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN 30 30 RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN 31 31 regPCIE_BUS_CNTL 0 0x420021 3 0 5 PMI_INT_DIS 6 6 IMMEDIATE_PMI_DIS 7 7 TRUE_PM_STATUS_EN 12 12 regPCIE_LC_STATE6 0 0x420022 4 0 5 LC_PREV_STATE24 0 5 LC_PREV_STATE25 8 13 LC_PREV_STATE26 16 21 LC_PREV_STATE27 24 29 regPCIE_LC_STATE7 0 0x420023 4 0 5 LC_PREV_STATE28 0 5 LC_PREV_STATE29 8 13 LC_PREV_STATE30 16 21 LC_PREV_STATE31 24 29 regPCIE_LC_STATE8 0 0x420024 4 0 5 LC_PREV_STATE32 0 5 LC_PREV_STATE33 8 13 LC_PREV_STATE34 16 21 LC_PREV_STATE35 24 29 regPCIE_LC_STATE9 0 0x420025 4 0 5 LC_PREV_STATE36 0 5 LC_PREV_STATE37 8 13 LC_PREV_STATE38 16 21 LC_PREV_STATE39 24 29 regPCIE_LC_STATE10 0 0x420026 4 0 5 LC_PREV_STATE40 0 5 LC_PREV_STATE41 8 13 LC_PREV_STATE42 16 21 LC_PREV_STATE43 24 29 regPCIE_LC_STATE11 0 0x420027 4 0 5 LC_PREV_STATE44 0 5 LC_PREV_STATE45 8 13 LC_PREV_STATE46 16 21 LC_PREV_STATE47 24 29 regPCIE_LC_STATUS1 0 0x420028 4 0 5 LC_REVERSE_RCVR 0 0 LC_REVERSE_XMIT 1 1 LC_OPERATING_LINK_WIDTH 2 4 LC_DETECTED_LINK_WIDTH 5 7 regPCIE_LC_STATUS2 0 0x420029 2 0 5 LC_TOTAL_INACTIVE_LANES 0 15 LC_TURN_ON_LANE 16 31 regPCIE_TX_CNTL3 0 0x42002a 20 0 5 TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS 0 0 CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE 1 3 TX_STOP_TLP2_IN_REPLAY_DIS 4 4 TX_PDAT_CREDIT_RELEASE_FIX_DIS 5 5 TX_ARB_P_AFTER_NP_EN 6 6 TX_RBUF_DELAY_2HDR_MWR_EN 7 7 TX_RBUF_DELAY_MWR_SIZE 8 15 TX_ENCMSG_HDR_FROM_SDP_REQ_EN 19 19 TX_DROP_REQ_TARGETING_BAD_PORT_EN 20 20 MCA_CLKGATE_DIS 21 21 TX_PMFSM_OLD_MODE 22 22 TX_MPDAT_EVICT_TAIL_FIX_DIS 23 23 TX_CHK_FC_FOR_L1_DIS 24 24 TX_8B_CPL_AND_WRITE_EN 25 25 TX_B2B_ACK_FIX_DIS 26 26 TXDLLP_B2B_DIS 27 27 TXDL_TLP_AFTER_DLLP_EN 28 28 TXDL_STP_SDP_AT_DW3_EN 29 29 TX_SILENT_DROP_P_IN_L1SS_DIS 30 30 TX_SILENT_DROP_NP_IN_L1SS_DIS 31 31 regPCIE_TX_STATUS 0 0x42002b 16 0 5 TX_MST_MEM_READY 0 0 CI_MST_REQ_IDLE 1 1 CI_NO_PENDING_MST_MRD 2 2 CI_MST_WRRSP_IDLE 3 3 CI_SLV_RDRSP_IDLE 4 4 CI_MST_TX_IDLE 5 5 CI_SLV_CLKREQ_IDLE 6 6 CI_MST_CLKREQ_IDLE 7 7 TX_P_HDR_EMPTY 8 8 TX_NP_HDR_EMPTY 9 9 TX_P_DAT_EMPTY 10 10 TX_NP_DAT_EMPTY 11 11 CI_P_HDR_NO_FREE_CREDITS 12 12 CI_NP_HDR_NO_FREE_CREDITS 13 13 CI_P_DAT_NO_FREE_CREDITS 14 14 CI_NP_DAT_NO_FREE_CREDITS 15 15 regPCIE_WPR_CNTL 0 0x420030 7 0 5 WPR_RESET_HOT_RST_EN 0 0 WPR_RESET_LNK_DWN_EN 1 1 WPR_RESET_LNK_DIS_EN 2 2 WPR_RESET_COR_EN 3 3 WPR_RESET_REG_EN 4 4 WPR_RESET_STY_EN 5 5 WPR_RESET_PHY_EN 6 6 regPCIE_RX_LAST_TLP0 0 0x420031 1 0 5 RX_LAST_TLP0 0 31 regPCIE_RX_LAST_TLP1 0 0x420032 1 0 5 RX_LAST_TLP1 0 31 regPCIE_RX_LAST_TLP2 0 0x420033 1 0 5 RX_LAST_TLP2 0 31 regPCIE_RX_LAST_TLP3 0 0x420034 1 0 5 RX_LAST_TLP3 0 31 regPCIE_TX_LAST_TLP0 0 0x420035 1 0 5 TX_LAST_TLP0 0 31 regPCIE_TX_LAST_TLP1 0 0x420036 1 0 5 TX_LAST_TLP1 0 31 regPCIE_TX_LAST_TLP2 0 0x420037 1 0 5 TX_LAST_TLP2 0 31 regPCIE_TX_LAST_TLP3 0 0x420038 1 0 5 TX_LAST_TLP3 0 31 regPCIE_I2C_REG_ADDR_EXPAND 0 0x42003a 1 0 5 I2C_REG_ADDR 0 16 regPCIE_I2C_REG_DATA 0 0x42003b 1 0 5 I2C_REG_DATA 0 31 regPCIE_CFG_CNTL 0 0x42003c 3 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 regPCIE_LC_PM_CNTL 0 0x42003d 8 0 5 LC_PORT_0_CLKREQB_MAP 0 3 LC_PORT_1_CLKREQB_MAP 4 7 LC_PORT_2_CLKREQB_MAP 8 11 LC_PORT_3_CLKREQB_MAP 12 15 LC_PORT_4_CLKREQB_MAP 16 19 LC_PORT_5_CLKREQB_MAP 20 23 LC_PORT_6_CLKREQB_MAP 24 27 LC_PORT_7_CLKREQB_MAP 28 31 regPCIE_LC_PORT_ORDER_CNTL 0 0x42003e 1 0 5 LC_PORT_ORDER_EN 0 0 regPCIE_P_CNTL 0 0x420040 16 0 5 P_PWRDN_EN 0 0 P_SYMALIGN_MODE 1 1 P_IGNORE_CRC_ERR 4 4 P_IGNORE_LEN_ERR 5 5 P_IGNORE_EDB_ERR 6 6 P_IGNORE_IDL_ERR 7 7 P_IGNORE_TOK_ERR 8 8 P_BLK_LOCK_MODE 12 12 P_ALWAYS_USE_FAST_TXCLK 13 13 P_ELEC_IDLE_MODE 14 15 DLP_IGNORE_IN_L1_EN 16 16 ASSERT_DVALID_ON_EI_TRANS 17 17 LC_PCLK_USE_OLD_CLOCK_CIRCUIT 18 18 MASTER_PLL_LANE_NUM 19 22 MASTER_PLL_LANE_REFCLKREQ_EN 23 23 REFCLKREQ_WAIT_FOR_MASTER_PLL 24 24 regPCIE_P_BUF_STATUS 0 0x420041 2 0 5 P_OVERFLOW_ERR 0 15 P_UNDERFLOW_ERR 16 31 regPCIE_P_DECODER_STATUS 0 0x420042 1 0 5 P_DECODE_ERR 0 15 regPCIE_P_MISC_STATUS 0 0x420043 2 0 5 P_DESKEW_ERR 0 7 P_SYMUNLOCK_ERR 16 31 regPCIE_P_RCV_L0S_FTS_DET 0 0x420050 2 0 5 P_RCV_L0S_FTS_DET_MIN 0 7 P_RCV_L0S_FTS_DET_MAX 8 15 regPCIE_TX_CCIX_CNTL0 0 0x420054 4 0 5 TXCCIX_SDP_ENABLE 0 0 TXCCIX_L1_ON_SDP_DISCONNECT_EN 1 1 CCIX_SYNCFLOOD_DIS 2 2 TXCCIX_FLUSH_DIS 3 3 regPCIE_TX_CCIX_CNTL1 0 0x420055 1 0 5 TXCCIX_VENDOR_ID 0 15 regPCIE_TX_CCIX_PORT_MAP 0 0x420056 8 0 5 CCIX_SDP_PORT_NUM_INSERT_EN 0 0 CCIX_SDP_PORT_NUM_INSERT_SEL 1 3 CCIX_INTERLEAVED_MODE_EN 4 4 CCIX_PORT_NUMBER 5 7 CCIX_FIRST_CCIX_PORT_NUM 8 9 CCIX_INTERLEAVED_ADDR_SEL 10 13 CCIX_INTERLEAVED_ADDR_REMOVE0 14 14 CCIX_INTERLEAVED_ADDR_REMOVE1 15 15 regPCIE_TX_CCIX_ERR_CTL 0 0x420057 4 0 5 RX_CCIX_WRRSP_NONDATAERR_MODE 0 1 RX_CCIX_RDRSP_NONDATAERR_MODE 2 4 RX_CCIX_RDRSP_DATAERR_MODE 5 7 TXCCIX_MASK_POISON_EN 8 8 regPCIE_RX_CCIX_CTL0 0 0x420058 4 0 5 RXCCIX_CTO_VALUE 0 2 RXCCIX_CTO_STATUS 3 5 TXCCIX_REQMUX_MODE 14 14 TXCCIX_REQ_MUXTIME_LIMIT 16 23 regPCIE_RX_AD 0 0x420062 16 0 5 RX_SWUS_DROP_PME_TO 0 0 RX_SWUS_DROP_UNLOCK 1 1 RX_SWUS_UR_VDM0 2 2 RX_SWUS_DROP_VDM0 3 3 RX_SWUS_DROP_VDM1 4 4 RX_SWUS_UR_MSG_PREFIX_DIS 5 5 RX_RC_DROP_VDM0 8 8 RX_RC_UR_VDM0 9 9 RX_RC_DROP_VDM1 10 10 RX_RC_UR_SSPL_MSG 11 11 RX_RC_UR_BFRC_MSG 12 12 RX_RC_DROP_PME_TO_ACK 13 13 RX_RC_UR_ECRC_DIS 14 14 RX_RC_DROP_CPL_ECRC_FAILURE 15 15 RX_SB_DROP_LTAR_VDM_EN 16 16 RX_RC_UR_POIS_ATOP 17 17 regPCIE_SDP_CTRL 0 0x420063 26 0 5 SDP_UNIT_ID 0 3 CI_SLV_REQR_FULL_DISCONNECT_EN 4 4 CI_SLV_REQR_PART_DISCONNECT_EN 5 5 CI_MSTSDP_CLKGATE_ONESIDED_ENABLE 6 6 TX_RC_TPH_PRIV_DIS 7 7 TX_SWUS_TPH_PRIV_DIS 8 8 CI_SLAVE_TAG_STEALING_DIS 9 9 SLAVE_PREFIX_PRELOAD_DIS 10 10 CI_DISABLE_LTR_DROPPING 11 11 RX_SWUS_SIDEBAND_CPLHDR_DIS 12 12 CI_MST_MEMR_RD_NONCONT_BE_EN 13 13 CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL 14 14 CI_SWUS_RCVD_ERR_HANDLING_DIS 15 15 EARLY_HW_WAKE_UP_EN 16 16 SLV_SDP_DISCONNECT_WHEN_IN_L1_EN 17 17 BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN 18 18 TX_ENCMSG_USE_SDP_EP_DIS 19 19 TX_IGNORE_POISON_BIT_EN 20 20 TX_RBUF_WRITE_2HDR_DIS 21 21 TX_RBUF_READ_2HDR_DIS 22 22 TX_RBUF_END_TLP2_DIS 23 23 TX_MULTICYCLE_DLLP_DIS 24 24 CI_VIRTUAL_WIRE_MODE 25 25 SDP_UNIT_ID_LOWER 26 28 CI_SDP_RECONFIG_EN 29 29 TX_ENCMSG_REQID_FROM_REQSTREAMID_EN 30 30 regNBIO_CLKREQb_MAP_CNTL 0 0x420064 8 0 5 PCIE_CLKREQB_0_MAP 0 3 PCIE_CLKREQB_1_MAP 4 7 PCIE_CLKREQB_2_MAP 8 11 PCIE_CLKREQB_3_MAP 12 15 PCIE_CLKREQB_4_MAP 16 19 PCIE_CLKREQB_5_MAP 20 23 PCIE_CLKREQB_6_MAP 24 27 PCIE_CLKREQB_CNTL_MASK 28 28 regPCIE_SDP_SWUS_SLV_ATTR_CTRL 0 0x420065 9 0 5 CI_SWUS_SLV_RO_OVERRIDE_MEMWR 0 1 CI_SWUS_SLV_RO_OVERRIDE_MEMRD 2 3 CI_SWUS_SLV_RO_OVERRIDE_ATOMIC 4 5 CI_SWUS_SLV_SNR_OVERRIDE_MEMWR 6 7 CI_SWUS_SLV_SNR_OVERRIDE_MEMRD 8 9 CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC 10 11 CI_SWUS_SLV_IDO_OVERRIDE_MEMWR 12 13 CI_SWUS_SLV_IDO_OVERRIDE_MEMRD 14 15 CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC 16 17 regPCIE_SDP_RC_SLV_ATTR_CTRL 0 0x420066 9 0 5 CI_RC_SLV_RO_OVERRIDE_MEMWR 0 1 CI_RC_SLV_RO_OVERRIDE_MEMRD 2 3 CI_RC_SLV_RO_OVERRIDE_ATOMIC 4 5 CI_RC_SLV_SNR_OVERRIDE_MEMWR 6 7 CI_RC_SLV_SNR_OVERRIDE_MEMRD 8 9 CI_RC_SLV_SNR_OVERRIDE_ATOMIC 10 11 CI_RC_SLV_IDO_OVERRIDE_MEMWR 12 13 CI_RC_SLV_IDO_OVERRIDE_MEMRD 14 15 CI_RC_SLV_IDO_OVERRIDE_ATOMIC 16 17 regPCIE_PERF_COUNT_CNTL 0 0x420080 4 0 5 GLOBAL_COUNT_EN 0 0 GLOBAL_SHADOW_WR 1 1 GLOBAL_COUNT_RESET 2 2 GLOBAL_SHADOW_WR_SCLK_STATUS 31 31 regPCIE_PERF_CNTL_TXCLK1 0 0x420081 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_TXCLK1 0 0x420082 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_TXCLK1 0 0x420083 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_TXCLK2 0 0x420084 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_TXCLK2 0 0x420085 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_TXCLK2 0 0x420086 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_TXCLK3 0 0x420087 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_TXCLK3 0 0x420088 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_TXCLK3 0 0x420089 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_TXCLK4 0 0x42008a 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_TXCLK4 0 0x42008b 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_TXCLK4 0 0x42008c 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_SCLK1 0 0x42008d 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_SCLK1 0 0x42008e 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_SCLK1 0 0x42008f 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_SCLK2 0 0x420090 4 0 5 EVENT0_SEL 0 7 EVENT1_SEL 8 15 COUNTER0_UPPER 16 23 COUNTER1_UPPER 24 31 regPCIE_PERF_COUNT0_SCLK2 0 0x420091 1 0 5 COUNTER0 0 31 regPCIE_PERF_COUNT1_SCLK2 0 0x420092 1 0 5 COUNTER1 0 31 regPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0 0x420093 4 0 5 PERF0_PORT_SEL_TXCLK1 0 3 PERF1_PORT_SEL_TXCLK1 4 7 PERF0_PORT_SEL_TXCLK2 8 11 PERF1_PORT_SEL_TXCLK2 12 15 regPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0 0x420094 8 0 5 PERF0_PORT_SEL_TXCLK3 0 3 PERF1_PORT_SEL_TXCLK3 4 7 PERF0_PORT_SEL_TXCLK4 8 11 PERF1_PORT_SEL_TXCLK4 12 15 PERF0_PORT_SEL_SCLK1 16 19 PERF1_PORT_SEL_SCLK1 20 23 PERF0_PORT_SEL_SCLK2 24 27 PERF1_PORT_SEL_SCLK2 28 31 regPCIE_STRAP_F0 0 0x4200b0 27 0 5 STRAP_F0_EN 0 0 STRAP_F0_LEGACY_DEVICE_TYPE_EN 1 1 STRAP_F0_MSI_EN 2 2 STRAP_F0_VC_EN 3 3 STRAP_F0_DSN_EN 4 4 STRAP_F0_AER_EN 5 5 STRAP_F0_ACS_EN 6 6 STRAP_F0_BAR_EN 7 7 STRAP_F0_PWR_EN 8 8 STRAP_F0_DPA_EN 9 9 STRAP_F0_ATS_EN 10 10 STRAP_F0_PAGE_REQ_EN 11 11 STRAP_F0_PASID_EN 12 12 STRAP_F0_ECRC_CHECK_EN 13 13 STRAP_F0_CPL_ABORT_ERR_EN 15 15 STRAP_F0_POISONED_ADVISORY_NONFATAL 16 16 STRAP_F0_MC_EN 17 17 STRAP_F0_ATOMIC_EN 18 18 STRAP_F0_ATOMIC_64BIT_EN 19 19 STRAP_F0_ATOMIC_ROUTING_EN 20 20 STRAP_F0_MSI_MULTI_CAP 21 23 STRAP_F0_VFn_MSI_MULTI_CAP 24 26 STRAP_F0_MSI_PERVECTOR_MASK_CAP 27 27 STRAP_F0_NO_RO_ENABLED_P2P_PASSING 28 28 STRAP_SWUS_ARI_EN 29 29 STRAP_F0_SRIOV_EN 30 30 STRAP_F0_MSI_MAP_EN 31 31 regPCIE_STRAP_NTB 0 0x4200b1 11 0 5 STRAP_NTB_MSI_EN 2 2 STRAP_NTB_VC_EN 3 3 STRAP_NTB_DSN_EN 4 4 STRAP_NTB_AER_EN 5 5 STRAP_NTB_ECRC_CHECK_EN 13 13 STRAP_NTB_CPL_ABORT_ERR_EN 15 15 STRAP_NTB_ATOMIC_EN 18 18 STRAP_NTB_ATOMIC_64BIT_EN 19 19 STRAP_NTB_ATOMIC_ROUTING_EN 20 20 STRAP_NTB_LTR_SUPPORTED 21 21 STRAP_NTB_OBFF_SUPPORTED 22 23 regPCIE_STRAP_MISC 0 0x4200c0 9 0 5 STRAP_DLF_EN 0 0 STRAP_16GT_EN 1 1 STRAP_MARGINING_EN 2 2 STRAP_TL_ALT_BUF_EN 4 4 STRAP_BYPASS_SCRAMBLER 6 6 STRAP_CLK_PM_EN 24 24 STRAP_EXT_VC_COUNT 26 26 STRAP_REVERSE_ALL 28 28 STRAP_MST_ADR64_EN 29 29 regPCIE_STRAP_MISC2 0 0x4200c1 7 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_EN 0 0 STRAP_GEN2_COMPLIANCE 1 1 STRAP_MSTCPL_TIMEOUT_EN 2 2 STRAP_GEN3_COMPLIANCE 3 3 STRAP_TPH_SUPPORTED 4 4 STRAP_GEN4_COMPLIANCE 5 5 STRAP_F0_CTO_LOG_CAPABLE 6 6 regPCIE_STRAP_PI 0 0x4200c2 3 0 5 STRAP_QUICKSIM_START 0 0 STRAP_TEST_TOGGLE_PATTERN 28 28 STRAP_TEST_TOGGLE_MODE 29 29 regPCIE_STRAP_I2C_BD 0 0x4200c4 1 0 5 STRAP_BIF_I2C_SLV_ADR 0 6 regPCIE_PRBS_CLR 0 0x4200c8 2 0 5 PRBS_CLR 0 15 PRBS_POLARITY_EN 24 24 regPCIE_PRBS_STATUS1 0 0x4200c9 2 0 5 PRBS_ERRSTAT 0 15 PRBS_LOCKED 16 31 regPCIE_PRBS_STATUS2 0 0x4200ca 1 0 5 PRBS_BITCNT_DONE 0 15 regPCIE_PRBS_FREERUN 0 0x4200cb 1 0 5 PRBS_FREERUN 0 15 regPCIE_PRBS_MISC 0 0x4200cc 8 0 5 PRBS_EN 0 0 PRBS_TEST_MODE 1 3 PRBS_USER_PATTERN_TOGGLE 4 4 PRBS_8BIT_SEL 5 5 PRBS_COMMA_NUM 6 7 PRBS_LOCK_CNT 8 12 PRBS_DATA_RATE 14 15 PRBS_CHK_ERR_MASK 16 31 regPCIE_PRBS_USER_PATTERN 0 0x4200cd 1 0 5 PRBS_USER_PATTERN 0 29 regPCIE_PRBS_LO_BITCNT 0 0x4200ce 1 0 5 PRBS_LO_BITCNT 0 31 regPCIE_PRBS_HI_BITCNT 0 0x4200cf 1 0 5 PRBS_HI_BITCNT 0 7 regPCIE_PRBS_ERRCNT_0 0 0x4200d0 1 0 5 PRBS_ERRCNT_0 0 31 regPCIE_PRBS_ERRCNT_1 0 0x4200d1 1 0 5 PRBS_ERRCNT_1 0 31 regPCIE_PRBS_ERRCNT_2 0 0x4200d2 1 0 5 PRBS_ERRCNT_2 0 31 regPCIE_PRBS_ERRCNT_3 0 0x4200d3 1 0 5 PRBS_ERRCNT_3 0 31 regPCIE_PRBS_ERRCNT_4 0 0x4200d4 1 0 5 PRBS_ERRCNT_4 0 31 regPCIE_PRBS_ERRCNT_5 0 0x4200d5 1 0 5 PRBS_ERRCNT_5 0 31 regPCIE_PRBS_ERRCNT_6 0 0x4200d6 1 0 5 PRBS_ERRCNT_6 0 31 regPCIE_PRBS_ERRCNT_7 0 0x4200d7 1 0 5 PRBS_ERRCNT_7 0 31 regPCIE_PRBS_ERRCNT_8 0 0x4200d8 1 0 5 PRBS_ERRCNT_8 0 31 regPCIE_PRBS_ERRCNT_9 0 0x4200d9 1 0 5 PRBS_ERRCNT_9 0 31 regPCIE_PRBS_ERRCNT_10 0 0x4200da 1 0 5 PRBS_ERRCNT_10 0 31 regPCIE_PRBS_ERRCNT_11 0 0x4200db 1 0 5 PRBS_ERRCNT_11 0 31 regPCIE_PRBS_ERRCNT_12 0 0x4200dc 1 0 5 PRBS_ERRCNT_12 0 31 regPCIE_PRBS_ERRCNT_13 0 0x4200dd 1 0 5 PRBS_ERRCNT_13 0 31 regPCIE_PRBS_ERRCNT_14 0 0x4200de 1 0 5 PRBS_ERRCNT_14 0 31 regPCIE_PRBS_ERRCNT_15 0 0x4200df 1 0 5 PRBS_ERRCNT_15 0 31 regSWRST_COMMAND_STATUS 0 0x420100 12 0 5 RECONFIGURE 0 0 ATOMIC_RESET 1 1 RESET_COMPLETE 16 16 WAIT_STATE 17 17 SWUS_LINK_RESET 24 24 SWUS_LINK_RESET_CFG_ONLY 25 25 SWUS_LINK_RESET_PHY_CALIB 26 26 SWDS_LINK_RESET 27 27 SWDS_LINK_RESET_CFG_ONLY 28 28 LINK_RESET_TYPE_HOT_RESET 29 29 LINK_RESET_TYPE_LINK_DISABLE 30 30 LINK_RESET_TYPE_LINK_DOWN 31 31 regSWRST_GENERAL_CONTROL 0 0x420101 11 0 5 RECONFIGURE_EN 0 0 ATOMIC_RESET_EN 1 1 RESET_PERIOD 2 4 WAIT_LINKUP 8 8 FORCE_REGIDLE 9 9 BLOCK_ON_IDLE 10 10 CONFIG_XFER_MODE 12 12 BYPASS_PCS_HOLD 17 17 MP1_PCIE_CROSSFIRE_LOCKDOWN_EN 24 24 IGNORE_SDP_RESET 25 25 WAIT_FOR_SDP_CREDITS 26 26 regSWRST_COMMAND_0 0 0x420102 17 0 5 PORT0_COR_RESET 0 0 PORT0_CFG_RESET 8 8 PORT1_CFG_RESET 9 9 PORT2_CFG_RESET 10 10 PORT3_CFG_RESET 11 11 PORT4_CFG_RESET 12 12 PORT5_CFG_RESET 13 13 PORT6_CFG_RESET 14 14 PORT7_CFG_RESET 15 15 BIF0_GLOBAL_RESET 24 24 BIF0_CALIB_RESET 25 25 BIF0_CORE_RESET 26 26 BIF0_REGISTER_RESET 27 27 BIF0_PHY_RESET 28 28 BIF0_STICKY_RESET 29 29 BIF0_CONFIG_RESET 30 30 BIF0_SDP_CREDIT_RESET 31 31 regSWRST_COMMAND_1 0 0x420103 24 0 5 RESETPCS0 0 0 RESETPCS1 1 1 RESETPCS2 2 2 RESETPCS3 3 3 RESETPCS4 4 4 RESETPCS5 5 5 RESETPCS6 6 6 RESETPCS7 7 7 RESETPCS8 8 8 RESETPCS9 9 9 RESETPCS10 10 10 RESETPCS11 11 11 RESETPCS12 12 12 RESETPCS13 13 13 RESETPCS14 14 14 RESETPCS15 15 15 SWITCHCLK 21 21 RESETPCFG 25 25 RESETLNCT 26 26 RESETMNTR 27 27 RESETHLTR 28 28 RESETCPM 29 29 RESETPHY0 30 30 TOGGLESTRAP 31 31 regSWRST_CONTROL_0 0 0x420104 17 0 5 PORT0_COR_RCEN 0 0 PORT0_CFG_RCEN 8 8 PORT1_CFG_RCEN 9 9 PORT2_CFG_RCEN 10 10 PORT3_CFG_RCEN 11 11 PORT4_CFG_RCEN 12 12 PORT5_CFG_RCEN 13 13 PORT6_CFG_RCEN 14 14 PORT7_CFG_RCEN 15 15 BIF0_GLOBAL_RESETRCEN 24 24 BIF0_CALIB_RESETRCEN 25 25 BIF0_CORE_RESETRCEN 26 26 BIF0_REGISTER_RESETRCEN 27 27 BIF0_PHY_RESETRCEN 28 28 BIF0_STICKY_RESETRCEN 29 29 BIF0_CONFIG_RESETRCEN 30 30 BIF0_SDP_CREDIT_RESETRCEN 31 31 regSWRST_CONTROL_1 0 0x420105 24 0 5 PCSRESET0_RCEN 0 0 PCSRESET1_RCEN 1 1 PCSRESET2_RCEN 2 2 PCSRESET3_RCEN 3 3 PCSRESET4_RCEN 4 4 PCSRESET5_RCEN 5 5 PCSRESET6_RCEN 6 6 PCSRESET7_RCEN 7 7 PCSRESET8_RCEN 8 8 PCSRESET9_RCEN 9 9 PCSRESET10_RCEN 10 10 PCSRESET11_RCEN 11 11 PCSRESET12_RCEN 12 12 PCSRESET13_RCEN 13 13 PCSRESET14_RCEN 14 14 PCSRESET15_RCEN 15 15 SWITCHCLK_RCEN 21 21 RESETPCFG_RCEN 25 25 RESETLNCT_RCEN 26 26 RESETMNTR_RCEN 27 27 RESETHLTR_RCEN 28 28 RESETCPM_RCEN 29 29 RESETPHY0_RCEN 30 30 STRAPVLD_RCEN 31 31 regSWRST_CONTROL_2 0 0x420106 17 0 5 PORT0_COR_ATEN 0 0 PORT0_CFG_ATEN 8 8 PORT1_CFG_ATEN 9 9 PORT2_CFG_ATEN 10 10 PORT3_CFG_ATEN 11 11 PORT4_CFG_ATEN 12 12 PORT5_CFG_ATEN 13 13 PORT6_CFG_ATEN 14 14 PORT7_CFG_ATEN 15 15 BIF0_GLOBAL_RESETATEN 24 24 BIF0_CALIB_RESETATEN 25 25 BIF0_CORE_RESETATEN 26 26 BIF0_REGISTER_RESETATEN 27 27 BIF0_PHY_RESETATEN 28 28 BIF0_STICKY_RESETATEN 29 29 BIF0_CONFIG_RESETATEN 30 30 BIF0_SDP_CREDIT_RESETATEN 31 31 regSWRST_CONTROL_3 0 0x420107 24 0 5 PCSRESET0_ATEN 0 0 PCSRESET1_ATEN 1 1 PCSRESET2_ATEN 2 2 PCSRESET3_ATEN 3 3 PCSRESET4_ATEN 4 4 PCSRESET5_ATEN 5 5 PCSRESET6_ATEN 6 6 PCSRESET7_ATEN 7 7 PCSRESET8_ATEN 8 8 PCSRESET9_ATEN 9 9 PCSRESET10_ATEN 10 10 PCSRESET11_ATEN 11 11 PCSRESET12_ATEN 12 12 PCSRESET13_ATEN 13 13 PCSRESET14_ATEN 14 14 PCSRESET15_ATEN 15 15 SWITCHCLK_ATEN 21 21 RESETPCFG_ATEN 25 25 RESETLNCT_ATEN 26 26 RESETMNTR_ATEN 27 27 RESETHLTR_ATEN 28 28 RESETCPM_ATEN 29 29 RESETPHY0_ATEN 30 30 STRAPVLD_ATEN 31 31 regSWRST_CONTROL_4 0 0x420108 17 0 5 PORT0_COR_WREN 0 0 PORT0_CFG_WREN 8 8 PORT1_CFG_WREN 9 9 PORT2_CFG_WREN 10 10 PORT3_CFG_WREN 11 11 PORT4_CFG_WREN 12 12 PORT5_CFG_WREN 13 13 PORT6_CFG_WREN 14 14 PORT7_CFG_WREN 15 15 BIF0_GLOBAL_WRRESETEN 24 24 BIF0_CALIB_WRRESETEN 25 25 BIF0_CORE_WRRESETEN 26 26 BIF0_REGISTER_WRRESETEN 27 27 BIF0_PHY_WRRESETEN 28 28 BIF0_STICKY_WRRESETEN 29 29 BIF0_CONFIG_WRRESETEN 30 30 BIF0_SDP_CREDIT_WRRESETEN 31 31 regSWRST_CONTROL_5 0 0x420109 24 0 5 PCSRESET0_WREN 0 0 PCSRESET1_WREN 1 1 PCSRESET2_WREN 2 2 PCSRESET3_WREN 3 3 PCSRESET4_WREN 4 4 PCSRESET5_WREN 5 5 PCSRESET6_WREN 6 6 PCSRESET7_WREN 7 7 PCSRESET8_WREN 8 8 PCSRESET9_WREN 9 9 PCSRESET10_WREN 10 10 PCSRESET11_WREN 11 11 PCSRESET12_WREN 12 12 PCSRESET13_WREN 13 13 PCSRESET14_WREN 14 14 PCSRESET15_WREN 15 15 WRSWITCHCLK_EN 21 21 WRRESETPCFG_EN 25 25 WRRESETLNCT_EN 26 26 WRRESETMNTR_EN 27 27 WRRESETHLTR_EN 28 28 WRRESETCPM_EN 29 29 WRRESETPHY0_EN 30 30 WRSTRAPVLD_EN 31 31 regSWRST_CONTROL_6 0 0x42010a 11 0 5 HOLD_TRAINING_A 0 0 HOLD_TRAINING_B 1 1 HOLD_TRAINING_C 2 2 HOLD_TRAINING_D 3 3 HOLD_TRAINING_E 4 4 HOLD_TRAINING_F 5 5 HOLD_TRAINING_G 6 6 HOLD_TRAINING_H 7 7 HOLD_TRAINING_I 8 8 HOLD_TRAINING_J 9 9 HOLD_TRAINING_K 10 10 regSWRST_EP_COMMAND_0 0 0x42010b 4 0 5 EP_CFG_RESET_ONLY 0 0 EP_HOT_RESET 8 8 EP_LNKDWN_RESET 9 9 EP_LNKDIS_RESET 10 10 regSWRST_EP_CONTROL_0 0 0x42010c 6 0 5 EP_CFG_RESET_ONLY_EN 0 0 EP_HOT_RESET_EN 8 8 EP_LNKDWN_RESET_EN 9 9 EP_LNKDIS_RESET_EN 10 10 EP_PORT_IGNORE_CHIP_MODE 22 22 EP_PORT_CONTROL 23 31 regCPM_CONTROL 0 0x420118 27 0 5 LCLK_DYN_GATE_ENABLE 0 0 TXCLK_DYN_GATE_ENABLE 1 1 L1_PWR_GATE_ENABLE 2 2 L1_1_PWR_GATE_ENABLE 3 3 L1_2_PWR_GATE_ENABLE 4 4 TXCLK_LCNT_GATE_ENABLE 5 5 TXCLK_REGS_GATE_ENABLE 6 6 TXCLK_PRBS_GATE_ENABLE 7 7 REFCLK_REGS_GATE_ENABLE 8 8 LCLK_DYN_GATE_LATENCY 9 10 TXCLK_DYN_GATE_LATENCY 11 12 REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE 13 13 TXCLK_REGS_GATE_LATENCY 14 14 REFCLK_REGS_GATE_LATENCY 15 15 LCLK_GATE_TXCLK_FREE 16 16 RCVR_DET_CLK_ENABLE 17 17 FAST_TXCLK_LATENCY 18 20 IGNORE_REGS_IDLE_IN_PG 21 21 REFCLK_XSTCLK_ENABLE 22 22 REFCLK_XSTCLK_LATENCY 23 23 CLKREQb_UNGATE_TXCLK_ENABLE 24 24 LCLK_GATE_ALLOW_IN_L1 25 25 PG_EARLY_WAKE_ENABLE 26 26 PCIE_CORE_IDLE 27 27 PCIE_LINK_IDLE 28 28 PCIE_BUFFER_EMPTY 29 29 REGS_IDLE_TO_PG_LATENCY 30 31 regCPM_SPLIT_CONTROL 0 0x420119 1 0 5 TXCLK_CCIX_DYN_GATE_ENABLE 0 0 regCPM_CONTROL_EXT 0 0x42011a 5 0 5 PWRDOWN_EI_MASK_DISABLE 0 0 DELAY_HOLD_TRAINING_ENABLE 1 1 LCLK_DS_MODE 2 2 LCLK_DS_ENABLE 3 3 PG_STATE 4 6 regSMN_APERTURE_ID_A 0 0x42011d 1 0 5 PCS_APERTURE_ID 12 23 regSMN_APERTURE_ID_B 0 0x42011e 2 0 5 IOHUB_APERTURE_ID 0 11 NBIF_APERTURE_ID 12 23 regLNCNT_CONTROL 0 0x420125 5 0 5 CFG_LNC_WINDOW_EN 0 0 CFG_LNC_BW_CNT_EN 1 1 CFG_LNC_CMN_CNT_EN 2 2 CFG_LNC_OVRD_EN 3 3 CFG_LNC_OVRD_VAL 4 4 regLNCNT_QUAN_THRD 0 0x420127 2 0 5 CFG_LNC_BW_QUAN_THRD 0 2 CFG_LNC_CMN_QUAN_THRD 4 6 regLNCNT_WEIGHT 0 0x420128 2 0 5 CFG_LNC_BW_WEIGHT 0 15 CFG_LNC_CMN_WEIGHT 16 31 regPCIE_PGMST_CNTL 0 0x420130 5 0 5 CFG_PG_HYSTERESIS 0 7 CFG_PG_EN 8 8 CFG_IDLENESS_COUNT_EN 10 13 CFG_FW_PG_EXIT_CNTL 14 15 PG_EXIT_TIMER 16 23 regPCIE_PGSLV_CNTL 0 0x420131 1 0 5 CFG_IDLE_HYSTERESIS 0 4 regLC_CPM_CONTROL_0 0 0x420133 32 0 5 TXCLK_DYN_PORT_A_GATE_ENABLE 0 0 TXCLK_DYN_PORT_B_GATE_ENABLE 1 1 TXCLK_DYN_PORT_C_GATE_ENABLE 2 2 TXCLK_DYN_PORT_D_GATE_ENABLE 3 3 TXCLK_DYN_PORT_E_GATE_ENABLE 4 4 TXCLK_DYN_PORT_F_GATE_ENABLE 5 5 TXCLK_DYN_PORT_G_GATE_ENABLE 6 6 TXCLK_DYN_PORT_H_GATE_ENABLE 7 7 TXCLK_DYN_PORT_I_GATE_ENABLE 8 8 TXCLK_DYN_PORT_J_GATE_ENABLE 9 9 TXCLK_DYN_PORT_K_GATE_ENABLE 10 10 TXCLK_DYN_PORT_L_GATE_ENABLE 11 11 TXCLK_DYN_PORT_M_GATE_ENABLE 12 12 TXCLK_DYN_PORT_N_GATE_ENABLE 13 13 TXCLK_DYN_PORT_O_GATE_ENABLE 14 14 TXCLK_DYN_PORT_P_GATE_ENABLE 15 15 TXCLK_DYN_TR_PORT_A_GATE_ENABLE 16 16 TXCLK_DYN_TR_PORT_B_GATE_ENABLE 17 17 TXCLK_DYN_TR_PORT_C_GATE_ENABLE 18 18 TXCLK_DYN_TR_PORT_D_GATE_ENABLE 19 19 TXCLK_DYN_TR_PORT_E_GATE_ENABLE 20 20 TXCLK_DYN_TR_PORT_F_GATE_ENABLE 21 21 TXCLK_DYN_TR_PORT_G_GATE_ENABLE 22 22 TXCLK_DYN_TR_PORT_H_GATE_ENABLE 23 23 TXCLK_DYN_TR_PORT_I_GATE_ENABLE 24 24 TXCLK_DYN_TR_PORT_J_GATE_ENABLE 25 25 TXCLK_DYN_TR_PORT_K_GATE_ENABLE 26 26 TXCLK_DYN_TR_PORT_L_GATE_ENABLE 27 27 TXCLK_DYN_TR_PORT_M_GATE_ENABLE 28 28 TXCLK_DYN_TR_PORT_N_GATE_ENABLE 29 29 TXCLK_DYN_TR_PORT_O_GATE_ENABLE 30 30 TXCLK_DYN_TR_PORT_P_GATE_ENABLE 31 31 regLC_CPM_CONTROL_1 0 0x420134 18 0 5 TXCLK_DYN_PORT_GATE_LATENCY 0 2 TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE 15 15 TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE 16 16 TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE 17 17 TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE 18 18 TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE 19 19 TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE 20 20 TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE 21 21 TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE 22 22 TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE 23 23 TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE 24 24 TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE 25 25 TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE 26 26 TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE 27 27 TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE 28 28 TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE 29 29 TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE 30 30 TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE 31 31 regPCIE_RXMARGIN_CONTROL_CAPABILITIES 0 0x420135 5 0 5 M_VOLTAGESUPPORTED 0 0 M_INDUPDOWNVOLTAGE 1 1 M_INDLEFTRIGHTTIMING 2 2 M_SAMPLEREPORTINGMETHOD 3 3 M_INDERRORSAMPLER 4 4 regPCIE_RXMARGIN_1_SETTINGS 0 0x420136 4 0 5 M_NUMVOLTAGESTEPS 0 6 M_NUMTIMINGSTEPS 7 12 M_MAXTIMINGOFFSET 13 19 M_MAXVOLTAGEOFFSET 20 26 regPCIE_RXMARGIN_2_SETTINGS 0 0x420137 5 0 5 M_SAMPLINGRATEVOLTAGE 0 5 M_SAMPLINGRATETIMING 6 11 M_SAMPLECOUNT 12 18 M_MAXLANES 19 23 M_ERROR_COUNT_LIMIT 24 29 regPCIE_PRESENCE_DETECT_SELECT 0 0x420138 4 0 5 HPGI_BLOCK_DL_ACTIVE_INT 0 7 HPGI_DL_ACTIVE_STATE_PRIVATE 8 15 DL_ACTIVE_INT_STATUS 16 23 PRESENCE_DETECT_SELECT 24 24 regFASTREG_APERTURE 0 0xe81c00 3 0 5 FASTREG_APERTURE_ID 0 11 FASTREG_NODE_ID 16 19 FASTREG_TRAN_POSTED 31 31 regNBIO_LCLK_DS_MASK 0 0xe84009 1 0 5 LCLK_DS_MASK 0 31 regSB_LOCATION 0 0xe8401f 2 0 5 SBlocated_Port 0 15 SBlocated_Core 16 31 regSW_US_LOCATION 0 0xe84020 2 0 5 SW_USlocated_Port 0 15 SW_USlocated_Core 16 31 regSW_NMI_CNTL 0 0xe84042 1 0 5 SW_NMI_Status 0 31 regSW_SMI_CNTL 0 0xe84043 1 0 5 SW_SMI_Status 0 31 regSW_SCI_CNTL 0 0xe84044 1 0 5 SW_SCI_Status 0 31 regAPML_SW_STATUS 0 0xe84045 1 0 5 APML_NMI_STATUS 0 0 regSW_GIC_SPI_CNTL 0 0xe84047 3 0 5 SW_NMI_GIC_SPI_Vector 0 7 SW_SMI_GIC_SPI_Vector 8 15 SW_SCI_GIC_SPI_Vector 16 23 regSW_SYNCFLOOD_CNTL 0 0xe84049 2 0 5 SW_SYNCFLOOD_PRIVATE 0 0 SW_SYNCFLOOD_APML 1 1 regCAM_CONTROL 0 0xe84052 6 0 5 CAM_En 0 0 Op 1 1 AccessType 2 2 DataMatchEn 3 3 VC 4 6 CrossTrigger 8 11 regCAM_TARGET_INDEX_ADDR_BOTTOM 0 0xe84053 1 0 5 IndexAddrBottom 0 31 regCAM_TARGET_INDEX_ADDR_TOP 0 0xe84054 1 0 5 IndexAddrTop 0 31 regCAM_TARGET_INDEX_DATA 0 0xe84055 1 0 5 IndexData 0 31 regCAM_TARGET_INDEX_DATA_MASK 0 0xe84056 1 0 5 IndexDataMask 0 31 regCAM_TARGET_DATA_ADDR_BOTTOM 0 0xe84057 1 0 5 DataAddrBottom 0 31 regCAM_TARGET_DATA_ADDR_TOP 0 0xe84059 1 0 5 DataAddrTop 0 31 regCAM_TARGET_DATA 0 0xe8405a 1 0 5 Data 0 31 regCAM_TARGET_DATA_MASK 0 0xe8405b 1 0 5 DataMask 0 31 regP_DMA_DROPPED_LOG_LOWER 0 0xe84060 32 0 5 P_DMA_DROPPED_LOG_LOWER_0 0 0 P_DMA_DROPPED_LOG_LOWER_1 1 1 P_DMA_DROPPED_LOG_LOWER_2 2 2 P_DMA_DROPPED_LOG_LOWER_3 3 3 P_DMA_DROPPED_LOG_LOWER_4 4 4 P_DMA_DROPPED_LOG_LOWER_5 5 5 P_DMA_DROPPED_LOG_LOWER_6 6 6 P_DMA_DROPPED_LOG_LOWER_7 7 7 P_DMA_DROPPED_LOG_LOWER_8 8 8 P_DMA_DROPPED_LOG_LOWER_9 9 9 P_DMA_DROPPED_LOG_LOWER_10 10 10 P_DMA_DROPPED_LOG_LOWER_11 11 11 P_DMA_DROPPED_LOG_LOWER_12 12 12 P_DMA_DROPPED_LOG_LOWER_13 13 13 P_DMA_DROPPED_LOG_LOWER_14 14 14 P_DMA_DROPPED_LOG_LOWER_15 15 15 P_DMA_DROPPED_LOG_LOWER_16 16 16 P_DMA_DROPPED_LOG_LOWER_17 17 17 P_DMA_DROPPED_LOG_LOWER_18 18 18 P_DMA_DROPPED_LOG_LOWER_19 19 19 P_DMA_DROPPED_LOG_LOWER_20 20 20 P_DMA_DROPPED_LOG_LOWER_21 21 21 P_DMA_DROPPED_LOG_LOWER_22 22 22 P_DMA_DROPPED_LOG_LOWER_23 23 23 P_DMA_DROPPED_LOG_LOWER_24 24 24 P_DMA_DROPPED_LOG_LOWER_25 25 25 P_DMA_DROPPED_LOG_LOWER_26 26 26 P_DMA_DROPPED_LOG_LOWER_27 27 27 P_DMA_DROPPED_LOG_LOWER_28 28 28 P_DMA_DROPPED_LOG_LOWER_29 29 29 P_DMA_DROPPED_LOG_LOWER_30 30 30 P_DMA_DROPPED_LOG_LOWER_31 31 31 regP_DMA_DROPPED_LOG_UPPER 0 0xe84061 32 0 5 P_DMA_DROPPED_LOG_UPPER_0 0 0 P_DMA_DROPPED_LOG_UPPER_1 1 1 P_DMA_DROPPED_LOG_UPPER_2 2 2 P_DMA_DROPPED_LOG_UPPER_3 3 3 P_DMA_DROPPED_LOG_UPPER_4 4 4 P_DMA_DROPPED_LOG_UPPER_5 5 5 P_DMA_DROPPED_LOG_UPPER_6 6 6 P_DMA_DROPPED_LOG_UPPER_7 7 7 P_DMA_DROPPED_LOG_UPPER_8 8 8 P_DMA_DROPPED_LOG_UPPER_9 9 9 P_DMA_DROPPED_LOG_UPPER_10 10 10 P_DMA_DROPPED_LOG_UPPER_11 11 11 P_DMA_DROPPED_LOG_UPPER_12 12 12 P_DMA_DROPPED_LOG_UPPER_13 13 13 P_DMA_DROPPED_LOG_UPPER_14 14 14 P_DMA_DROPPED_LOG_UPPER_15 15 15 P_DMA_DROPPED_LOG_UPPER_16 16 16 P_DMA_DROPPED_LOG_UPPER_17 17 17 P_DMA_DROPPED_LOG_UPPER_18 18 18 P_DMA_DROPPED_LOG_UPPER_19 19 19 P_DMA_DROPPED_LOG_UPPER_20 20 20 P_DMA_DROPPED_LOG_UPPER_21 21 21 P_DMA_DROPPED_LOG_UPPER_22 22 22 P_DMA_DROPPED_LOG_UPPER_23 23 23 P_DMA_DROPPED_LOG_UPPER_24 24 24 P_DMA_DROPPED_LOG_UPPER_25 25 25 P_DMA_DROPPED_LOG_UPPER_26 26 26 P_DMA_DROPPED_LOG_UPPER_27 27 27 P_DMA_DROPPED_LOG_UPPER_28 28 28 P_DMA_DROPPED_LOG_UPPER_29 29 29 P_DMA_DROPPED_LOG_UPPER_30 30 30 P_DMA_DROPPED_LOG_UPPER_31 31 31 regNP_DMA_DROPPED_LOG_LOWER 0 0xe84062 32 0 5 NP_DMA_DROPPED_LOG_LOWER_0 0 0 NP_DMA_DROPPED_LOG_LOWER_1 1 1 NP_DMA_DROPPED_LOG_LOWER_2 2 2 NP_DMA_DROPPED_LOG_LOWER_3 3 3 NP_DMA_DROPPED_LOG_LOWER_4 4 4 NP_DMA_DROPPED_LOG_LOWER_5 5 5 NP_DMA_DROPPED_LOG_LOWER_6 6 6 NP_DMA_DROPPED_LOG_LOWER_7 7 7 NP_DMA_DROPPED_LOG_LOWER_8 8 8 NP_DMA_DROPPED_LOG_LOWER_9 9 9 NP_DMA_DROPPED_LOG_LOWER_10 10 10 NP_DMA_DROPPED_LOG_LOWER_11 11 11 NP_DMA_DROPPED_LOG_LOWER_12 12 12 NP_DMA_DROPPED_LOG_LOWER_13 13 13 NP_DMA_DROPPED_LOG_LOWER_14 14 14 NP_DMA_DROPPED_LOG_LOWER_15 15 15 NP_DMA_DROPPED_LOG_LOWER_16 16 16 NP_DMA_DROPPED_LOG_LOWER_17 17 17 NP_DMA_DROPPED_LOG_LOWER_18 18 18 NP_DMA_DROPPED_LOG_LOWER_19 19 19 NP_DMA_DROPPED_LOG_LOWER_20 20 20 NP_DMA_DROPPED_LOG_LOWER_21 21 21 NP_DMA_DROPPED_LOG_LOWER_22 22 22 NP_DMA_DROPPED_LOG_LOWER_23 23 23 NP_DMA_DROPPED_LOG_LOWER_24 24 24 NP_DMA_DROPPED_LOG_LOWER_25 25 25 NP_DMA_DROPPED_LOG_LOWER_26 26 26 NP_DMA_DROPPED_LOG_LOWER_27 27 27 NP_DMA_DROPPED_LOG_LOWER_28 28 28 NP_DMA_DROPPED_LOG_LOWER_29 29 29 NP_DMA_DROPPED_LOG_LOWER_30 30 30 NP_DMA_DROPPED_LOG_LOWER_31 31 31 regNP_DMA_DROPPED_LOG_UPPER 0 0xe84063 32 0 5 NP_DMA_DROPPED_LOG_UPPER_0 0 0 NP_DMA_DROPPED_LOG_UPPER_1 1 1 NP_DMA_DROPPED_LOG_UPPER_2 2 2 NP_DMA_DROPPED_LOG_UPPER_3 3 3 NP_DMA_DROPPED_LOG_UPPER_4 4 4 NP_DMA_DROPPED_LOG_UPPER_5 5 5 NP_DMA_DROPPED_LOG_UPPER_6 6 6 NP_DMA_DROPPED_LOG_UPPER_7 7 7 NP_DMA_DROPPED_LOG_UPPER_8 8 8 NP_DMA_DROPPED_LOG_UPPER_9 9 9 NP_DMA_DROPPED_LOG_UPPER_10 10 10 NP_DMA_DROPPED_LOG_UPPER_11 11 11 NP_DMA_DROPPED_LOG_UPPER_12 12 12 NP_DMA_DROPPED_LOG_UPPER_13 13 13 NP_DMA_DROPPED_LOG_UPPER_14 14 14 NP_DMA_DROPPED_LOG_UPPER_15 15 15 NP_DMA_DROPPED_LOG_UPPER_16 16 16 NP_DMA_DROPPED_LOG_UPPER_17 17 17 NP_DMA_DROPPED_LOG_UPPER_18 18 18 NP_DMA_DROPPED_LOG_UPPER_19 19 19 NP_DMA_DROPPED_LOG_UPPER_20 20 20 NP_DMA_DROPPED_LOG_UPPER_21 21 21 NP_DMA_DROPPED_LOG_UPPER_22 22 22 NP_DMA_DROPPED_LOG_UPPER_23 23 23 NP_DMA_DROPPED_LOG_UPPER_24 24 24 NP_DMA_DROPPED_LOG_UPPER_25 25 25 NP_DMA_DROPPED_LOG_UPPER_26 26 26 NP_DMA_DROPPED_LOG_UPPER_27 27 27 NP_DMA_DROPPED_LOG_UPPER_28 28 28 NP_DMA_DROPPED_LOG_UPPER_29 29 29 NP_DMA_DROPPED_LOG_UPPER_30 30 30 NP_DMA_DROPPED_LOG_UPPER_31 31 31 regPCIE_VDM_NODE0_CTRL4 0 0xe84064 3 0 5 BUS_RANGE_BASE 0 7 BUS_RANGE_LIMIT 8 15 NODE0_PRESENT 31 31 regPCIE_VDM_CNTL2 0 0xe8408c 3 0 5 VdmP2pMode 0 1 MCTPMasterValid 15 15 MCTPMasterID 16 31 regPCIE_VDM_CNTL3 0 0xe8408d 2 0 5 APMTPMasterValid 15 15 APMTPMasterID 16 31 regSTALL_CONTROL_XBARPORT0_0 0 0xe84090 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT0_1 0 0xe84091 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT1_0 0 0xe84093 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT1_1 0 0xe84094 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT2_0 0 0xe84096 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT2_1 0 0xe84097 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT3_0 0 0xe84099 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT3_1 0 0xe8409a 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT4_0 0 0xe8409c 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT4_1 0 0xe8409d 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT5_0 0 0xe8409f 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT5_1 0 0xe840a0 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regSTALL_CONTROL_XBARPORT6_0 0 0xe840a2 7 0 5 StallVC0ReqEn 0 1 StallVC1ReqEn 4 5 StallVC2ReqEn 8 9 StallVC3ReqEn 12 13 StallVC4ReqEn 16 17 StallVC5ReqEn 20 21 StallVC7ReqEn 28 29 regSTALL_CONTROL_XBARPORT6_1 0 0xe840a3 7 0 5 StallVC0RspEn 0 1 StallVC1RspEn 4 5 StallVC2RspEn 8 9 StallVC3RspEn 12 13 StallVC4RspEn 16 17 StallVC5RspEn 20 21 StallVC7RspEn 28 29 regFASTREG_BASE_ADDR_LO 0 0xe840c0 3 0 5 FASTREG_MMIO_EN 0 0 FASTREG_MMIO_LOCK 1 1 FASTREG_BASE_ADDR_LO 20 31 regFASTREG_BASE_ADDR_HI 0 0xe840c1 1 0 5 FASTREG_BASE_ADDR_HI 0 15 regFASTREGCNTL_BASE_ADDR_LO 0 0xe840c2 3 0 5 FASTREGCNTL_MMIO_EN 0 0 FASTREGCNTL_MMIO_LOCK 1 1 FASTREGCNTL_BASE_ADDR_LO 12 31 regFASTREGCNTL_BASE_ADDR_HI 0 0xe840c3 1 0 5 FASTREGCNTL_BASE_ADDR_HI 0 15 regSCRATCH_4 0 0xe840fc 1 0 5 SCRATCH_4 0 31 regSCRATCH_5 0 0xe840fd 1 0 5 SCRATCH_5 0 31 regTRAP_STATUS 0 0xe84100 2 0 5 TrapReqValid 0 0 TrapNumber 8 11 regTRAP_REQUEST0 0 0xe84101 1 0 5 TrapReqAddrLo 2 31 regTRAP_REQUEST1 0 0xe84102 1 0 5 TrapReqAddrHi 0 31 regTRAP_REQUEST2 0 0xe84103 3 0 5 TrapReqCmd 0 5 TrapAttr 8 15 TrapReqLen 16 21 regTRAP_REQUEST3 0 0xe84104 7 0 5 TrapReqVC 0 2 TrapReqBlockLevel 4 5 TrapReqChain 6 6 TrapReqIO 7 7 TrapReqPassPW 8 8 TrapReqRspPassPW 9 9 TrapReqUnitID 16 21 regTRAP_REQUEST4 0 0xe84105 1 0 5 TrapReqSecLevel 0 3 regTRAP_REQUEST5 0 0xe84106 3 0 5 TrapReqDataVC 0 2 TrapReqDataErr 4 4 TrapReqDataParity 8 15 regTRAP_REQUEST_DATASTRB0 0 0xe84108 1 0 5 TrapReqDataBytEn0 0 31 regTRAP_REQUEST_DATASTRB1 0 0xe84109 1 0 5 TrapReqDataBytEn1 0 31 regTRAP_REQUEST_DATA0 0 0xe84110 1 0 5 TrapReqData0 0 31 regTRAP_REQUEST_DATA1 0 0xe84111 1 0 5 TrapReqData1 0 31 regTRAP_REQUEST_DATA2 0 0xe84112 1 0 5 TrapReqData2 0 31 regTRAP_REQUEST_DATA3 0 0xe84113 1 0 5 TrapReqData3 0 31 regTRAP_REQUEST_DATA4 0 0xe84114 1 0 5 TrapReqData4 0 31 regTRAP_REQUEST_DATA5 0 0xe84115 1 0 5 TrapReqData5 0 31 regTRAP_REQUEST_DATA6 0 0xe84116 1 0 5 TrapReqData6 0 31 regTRAP_REQUEST_DATA7 0 0xe84117 1 0 5 TrapReqData7 0 31 regTRAP_REQUEST_DATA8 0 0xe84118 1 0 5 TrapReqData8 0 31 regTRAP_REQUEST_DATA9 0 0xe84119 1 0 5 TrapReqData9 0 31 regTRAP_REQUEST_DATA10 0 0xe8411a 1 0 5 TrapReqData10 0 31 regTRAP_REQUEST_DATA11 0 0xe8411b 1 0 5 TrapReqData11 0 31 regTRAP_REQUEST_DATA12 0 0xe8411c 1 0 5 TrapReqData12 0 31 regTRAP_REQUEST_DATA13 0 0xe8411d 1 0 5 TrapReqData13 0 31 regTRAP_REQUEST_DATA14 0 0xe8411e 1 0 5 TrapReqData14 0 31 regTRAP_REQUEST_DATA15 0 0xe8411f 1 0 5 TrapReqData15 0 31 regTRAP_RESPONSE_CONTROL 0 0xe84130 2 0 5 TrapRspTrigger 0 0 TrapRspReqPassthru 1 1 regTRAP_RESPONSE0 0 0xe84131 3 0 5 TrapRspPassPW 0 0 TrapRspStatus 4 7 TrapRspDataStatus 16 23 regTRAP_RESPONSE_DATA0 0 0xe84140 1 0 5 TrapRdRspData0 0 31 regTRAP_RESPONSE_DATA1 0 0xe84141 1 0 5 TrapRdRspData1 0 31 regTRAP_RESPONSE_DATA2 0 0xe84142 1 0 5 TrapRdRspData2 0 31 regTRAP_RESPONSE_DATA3 0 0xe84143 1 0 5 TrapRdRspData3 0 31 regTRAP_RESPONSE_DATA4 0 0xe84144 1 0 5 TrapRdRspData4 0 31 regTRAP_RESPONSE_DATA5 0 0xe84145 1 0 5 TrapRdRspData5 0 31 regTRAP_RESPONSE_DATA6 0 0xe84146 1 0 5 TrapRdRspData6 0 31 regTRAP_RESPONSE_DATA7 0 0xe84147 1 0 5 TrapRdRspData7 0 31 regTRAP_RESPONSE_DATA8 0 0xe84148 1 0 5 TrapRdRspData8 0 31 regTRAP_RESPONSE_DATA9 0 0xe84149 1 0 5 TrapRdRspData9 0 31 regTRAP_RESPONSE_DATA10 0 0xe8414a 1 0 5 TrapRdRspData10 0 31 regTRAP_RESPONSE_DATA11 0 0xe8414b 1 0 5 TrapRdRspData11 0 31 regTRAP_RESPONSE_DATA12 0 0xe8414c 1 0 5 TrapRdRspData12 0 31 regTRAP_RESPONSE_DATA13 0 0xe8414d 1 0 5 TrapRdRspData13 0 31 regTRAP_RESPONSE_DATA14 0 0xe8414e 1 0 5 TrapRdRspData14 0 31 regTRAP_RESPONSE_DATA15 0 0xe8414f 1 0 5 TrapRdRspData15 0 31 regTRAP0_CONTROL0 0 0xe84200 2 0 5 Trap0En 0 0 Trap0CrossTrigger 24 27 regTRAP0_ADDRESS_LO 0 0xe84202 1 0 5 Trap0AddrLo 2 31 regTRAP0_ADDRESS_HI 0 0xe84203 1 0 5 Trap0AddrHi 0 31 regTRAP0_COMMAND 0 0xe84204 2 0 5 Trap0Cmd0 0 5 Trap0Cmd1 8 13 regTRAP0_ADDRESS_LO_MASK 0 0xe84206 1 0 5 Trap0AddrLoMask 2 31 regTRAP0_ADDRESS_HI_MASK 0 0xe84207 1 0 5 Trap0AddrHiMask 0 31 regTRAP0_COMMAND_MASK 0 0xe84208 2 0 5 Trap0Cmd0Mask 0 5 Trap0Cmd1Mask 8 13 regTRAP1_CONTROL0 0 0xe84210 2 0 5 Trap1En 0 0 Trap1CrossTrigger 24 27 regTRAP1_ADDRESS_LO 0 0xe84212 1 0 5 Trap1AddrLo 2 31 regTRAP1_ADDRESS_HI 0 0xe84213 1 0 5 Trap1AddrHi 0 31 regTRAP1_COMMAND 0 0xe84214 2 0 5 Trap1Cmd0 0 5 Trap1Cmd1 8 13 regTRAP1_ADDRESS_LO_MASK 0 0xe84216 1 0 5 Trap1AddrLoMask 2 31 regTRAP1_ADDRESS_HI_MASK 0 0xe84217 1 0 5 Trap1AddrHiMask 0 31 regTRAP1_COMMAND_MASK 0 0xe84218 2 0 5 Trap1Cmd0Mask 0 5 Trap1Cmd1Mask 8 13 regTRAP2_CONTROL0 0 0xe84220 2 0 5 Trap2En 0 0 Trap2CrossTrigger 24 27 regTRAP2_ADDRESS_LO 0 0xe84222 1 0 5 Trap2AddrLo 2 31 regTRAP2_ADDRESS_HI 0 0xe84223 1 0 5 Trap2AddrHi 0 31 regTRAP2_COMMAND 0 0xe84224 2 0 5 Trap2Cmd0 0 5 Trap2Cmd1 8 13 regTRAP2_ADDRESS_LO_MASK 0 0xe84226 1 0 5 Trap2AddrLoMask 2 31 regTRAP2_ADDRESS_HI_MASK 0 0xe84227 1 0 5 Trap2AddrHiMask 0 31 regTRAP2_COMMAND_MASK 0 0xe84228 2 0 5 Trap2Cmd0Mask 0 5 Trap2Cmd1Mask 8 13 regTRAP3_CONTROL0 0 0xe84230 2 0 5 Trap3En 0 0 Trap3CrossTrigger 24 27 regTRAP3_ADDRESS_LO 0 0xe84232 1 0 5 Trap3AddrLo 2 31 regTRAP3_ADDRESS_HI 0 0xe84233 1 0 5 Trap3AddrHi 0 31 regTRAP3_COMMAND 0 0xe84234 2 0 5 Trap3Cmd0 0 5 Trap3Cmd1 8 13 regTRAP3_ADDRESS_LO_MASK 0 0xe84236 1 0 5 Trap3AddrLoMask 2 31 regTRAP3_ADDRESS_HI_MASK 0 0xe84237 1 0 5 Trap3AddrHiMask 0 31 regTRAP3_COMMAND_MASK 0 0xe84238 2 0 5 Trap3Cmd0Mask 0 5 Trap3Cmd1Mask 8 13 regTRAP4_CONTROL0 0 0xe84240 2 0 5 Trap4En 0 0 Trap4CrossTrigger 24 27 regTRAP4_ADDRESS_LO 0 0xe84242 1 0 5 Trap4AddrLo 2 31 regTRAP4_ADDRESS_HI 0 0xe84243 1 0 5 Trap4AddrHi 0 31 regTRAP4_COMMAND 0 0xe84244 2 0 5 Trap4Cmd0 0 5 Trap4Cmd1 8 13 regTRAP4_ADDRESS_LO_MASK 0 0xe84246 1 0 5 Trap4AddrLoMask 2 31 regTRAP4_ADDRESS_HI_MASK 0 0xe84247 1 0 5 Trap4AddrHiMask 0 31 regTRAP4_COMMAND_MASK 0 0xe84248 2 0 5 Trap4Cmd0Mask 0 5 Trap4Cmd1Mask 8 13 regTRAP5_CONTROL0 0 0xe84250 2 0 5 Trap5En 0 0 Trap5CrossTrigger 24 27 regTRAP5_ADDRESS_LO 0 0xe84252 1 0 5 Trap5AddrLo 2 31 regTRAP5_ADDRESS_HI 0 0xe84253 1 0 5 Trap5AddrHi 0 31 regTRAP5_COMMAND 0 0xe84254 2 0 5 Trap5Cmd0 0 5 Trap5Cmd1 8 13 regTRAP5_ADDRESS_LO_MASK 0 0xe84256 1 0 5 Trap5AddrLoMask 2 31 regTRAP5_ADDRESS_HI_MASK 0 0xe84257 1 0 5 Trap5AddrHiMask 0 31 regTRAP5_COMMAND_MASK 0 0xe84258 2 0 5 Trap5Cmd0Mask 0 5 Trap5Cmd1Mask 8 13 regTRAP6_CONTROL0 0 0xe84260 2 0 5 Trap6En 0 0 Trap6CrossTrigger 24 27 regTRAP6_ADDRESS_LO 0 0xe84262 1 0 5 Trap6AddrLo 2 31 regTRAP6_ADDRESS_HI 0 0xe84263 1 0 5 Trap6AddrHi 0 31 regTRAP6_COMMAND 0 0xe84264 2 0 5 Trap6Cmd0 0 5 Trap6Cmd1 8 13 regTRAP6_ADDRESS_LO_MASK 0 0xe84266 1 0 5 Trap6AddrLoMask 2 31 regTRAP6_ADDRESS_HI_MASK 0 0xe84267 1 0 5 Trap6AddrHiMask 0 31 regTRAP6_COMMAND_MASK 0 0xe84268 2 0 5 Trap6Cmd0Mask 0 5 Trap6Cmd1Mask 8 13 regTRAP7_CONTROL0 0 0xe84270 2 0 5 Trap7En 0 0 Trap7CrossTrigger 24 27 regTRAP7_ADDRESS_LO 0 0xe84272 1 0 5 Trap7AddrLo 2 31 regTRAP7_ADDRESS_HI 0 0xe84273 1 0 5 Trap7AddrHi 0 31 regTRAP7_COMMAND 0 0xe84274 2 0 5 Trap7Cmd0 0 5 Trap7Cmd1 8 13 regTRAP7_ADDRESS_LO_MASK 0 0xe84276 1 0 5 Trap7AddrLoMask 2 31 regTRAP7_ADDRESS_HI_MASK 0 0xe84277 1 0 5 Trap7AddrHiMask 0 31 regTRAP7_COMMAND_MASK 0 0xe84278 2 0 5 Trap7Cmd0Mask 0 5 Trap7Cmd1Mask 8 13 regTRAP8_CONTROL0 0 0xe84280 2 0 5 Trap8En 0 0 Trap8CrossTrigger 24 27 regTRAP8_ADDRESS_LO 0 0xe84282 1 0 5 Trap8AddrLo 2 31 regTRAP8_ADDRESS_HI 0 0xe84283 1 0 5 Trap8AddrHi 0 31 regTRAP8_COMMAND 0 0xe84284 2 0 5 Trap8Cmd0 0 5 Trap8Cmd1 8 13 regTRAP8_ADDRESS_LO_MASK 0 0xe84286 1 0 5 Trap8AddrLoMask 2 31 regTRAP8_ADDRESS_HI_MASK 0 0xe84287 1 0 5 Trap8AddrHiMask 0 31 regTRAP8_COMMAND_MASK 0 0xe84288 2 0 5 Trap8Cmd0Mask 0 5 Trap8Cmd1Mask 8 13 regTRAP9_CONTROL0 0 0xe84290 2 0 5 Trap9En 0 0 Trap9CrossTrigger 24 27 regTRAP9_ADDRESS_LO 0 0xe84292 1 0 5 Trap9AddrLo 2 31 regTRAP9_ADDRESS_HI 0 0xe84293 1 0 5 Trap9AddrHi 0 31 regTRAP9_COMMAND 0 0xe84294 2 0 5 Trap9Cmd0 0 5 Trap9Cmd1 8 13 regTRAP9_ADDRESS_LO_MASK 0 0xe84296 1 0 5 Trap9AddrLoMask 2 31 regTRAP9_ADDRESS_HI_MASK 0 0xe84297 1 0 5 Trap9AddrHiMask 0 31 regTRAP9_COMMAND_MASK 0 0xe84298 2 0 5 Trap9Cmd0Mask 0 5 Trap9Cmd1Mask 8 13 regTRAP10_CONTROL0 0 0xe842a0 2 0 5 Trap10En 0 0 Trap10CrossTrigger 24 27 regTRAP10_ADDRESS_LO 0 0xe842a2 1 0 5 Trap10AddrLo 2 31 regTRAP10_ADDRESS_HI 0 0xe842a3 1 0 5 Trap10AddrHi 0 31 regTRAP10_COMMAND 0 0xe842a4 2 0 5 Trap10Cmd0 0 5 Trap10Cmd1 8 13 regTRAP10_ADDRESS_LO_MASK 0 0xe842a6 1 0 5 Trap10AddrLoMask 2 31 regTRAP10_ADDRESS_HI_MASK 0 0xe842a7 1 0 5 Trap10AddrHiMask 0 31 regTRAP10_COMMAND_MASK 0 0xe842a8 2 0 5 Trap10Cmd0Mask 0 5 Trap10Cmd1Mask 8 13 regTRAP11_CONTROL0 0 0xe842b0 2 0 5 Trap11En 0 0 Trap11CrossTrigger 24 27 regTRAP11_ADDRESS_LO 0 0xe842b2 1 0 5 Trap11AddrLo 2 31 regTRAP11_ADDRESS_HI 0 0xe842b3 1 0 5 Trap11AddrHi 0 31 regTRAP11_COMMAND 0 0xe842b4 2 0 5 Trap11Cmd0 0 5 Trap11Cmd1 8 13 regTRAP11_ADDRESS_LO_MASK 0 0xe842b6 1 0 5 Trap11AddrLoMask 2 31 regTRAP11_ADDRESS_HI_MASK 0 0xe842b7 1 0 5 Trap11AddrHiMask 0 31 regTRAP11_COMMAND_MASK 0 0xe842b8 2 0 5 Trap11Cmd0Mask 0 5 Trap11Cmd1Mask 8 13 regTRAP12_CONTROL0 0 0xe842c0 2 0 5 Trap12En 0 0 Trap12CrossTrigger 24 27 regTRAP12_ADDRESS_LO 0 0xe842c2 1 0 5 Trap12AddrLo 2 31 regTRAP12_ADDRESS_HI 0 0xe842c3 1 0 5 Trap12AddrHi 0 31 regTRAP12_COMMAND 0 0xe842c4 2 0 5 Trap12Cmd0 0 5 Trap12Cmd1 8 13 regTRAP12_ADDRESS_LO_MASK 0 0xe842c6 1 0 5 Trap12AddrLoMask 2 31 regTRAP12_ADDRESS_HI_MASK 0 0xe842c7 1 0 5 Trap12AddrHiMask 0 31 regTRAP12_COMMAND_MASK 0 0xe842c8 2 0 5 Trap12Cmd0Mask 0 5 Trap12Cmd1Mask 8 13 regTRAP13_CONTROL0 0 0xe842d0 2 0 5 Trap13En 0 0 Trap13CrossTrigger 24 27 regTRAP13_ADDRESS_LO 0 0xe842d2 1 0 5 Trap13AddrLo 2 31 regTRAP13_ADDRESS_HI 0 0xe842d3 1 0 5 Trap13AddrHi 0 31 regTRAP13_COMMAND 0 0xe842d4 2 0 5 Trap13Cmd0 0 5 Trap13Cmd1 8 13 regTRAP13_ADDRESS_LO_MASK 0 0xe842d6 1 0 5 Trap13AddrLoMask 2 31 regTRAP13_ADDRESS_HI_MASK 0 0xe842d7 1 0 5 Trap13AddrHiMask 0 31 regTRAP13_COMMAND_MASK 0 0xe842d8 2 0 5 Trap13Cmd0Mask 0 5 Trap13Cmd1Mask 8 13 regTRAP14_CONTROL0 0 0xe842e0 2 0 5 Trap14En 0 0 Trap14CrossTrigger 24 27 regTRAP14_ADDRESS_LO 0 0xe842e2 1 0 5 Trap14AddrLo 2 31 regTRAP14_ADDRESS_HI 0 0xe842e3 1 0 5 Trap14AddrHi 0 31 regTRAP14_COMMAND 0 0xe842e4 2 0 5 Trap14Cmd0 0 5 Trap14Cmd1 8 13 regTRAP14_ADDRESS_LO_MASK 0 0xe842e6 1 0 5 Trap14AddrLoMask 2 31 regTRAP14_ADDRESS_HI_MASK 0 0xe842e7 1 0 5 Trap14AddrHiMask 0 31 regTRAP14_COMMAND_MASK 0 0xe842e8 2 0 5 Trap14Cmd0Mask 0 5 Trap14Cmd1Mask 8 13 regTRAP15_CONTROL0 0 0xe842f0 2 0 5 Trap15En 0 0 Trap15CrossTrigger 24 27 regTRAP15_ADDRESS_LO 0 0xe842f2 1 0 5 Trap15AddrLo 2 31 regTRAP15_ADDRESS_HI 0 0xe842f3 1 0 5 Trap15AddrHi 0 31 regTRAP15_COMMAND 0 0xe842f4 2 0 5 Trap15Cmd0 0 5 Trap15Cmd1 8 13 regTRAP15_ADDRESS_LO_MASK 0 0xe842f6 1 0 5 Trap15AddrLoMask 2 31 regTRAP15_ADDRESS_HI_MASK 0 0xe842f7 1 0 5 Trap15AddrHiMask 0 31 regTRAP15_COMMAND_MASK 0 0xe842f8 2 0 5 Trap15Cmd0Mask 0 5 Trap15Cmd1Mask 8 13 regSB_COMMAND 0 0xe85000 3 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 regSB_SUB_BUS_NUMBER_LATENCY 0 0xe85001 2 0 5 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 regSB_IO_BASE_LIMIT 0 0xe85002 2 0 5 IO_BASE 4 7 IO_LIMIT 12 15 regSB_MEM_BASE_LIMIT 0 0xe85003 2 0 5 MEM_BASE_31_20 4 15 MEM_LIMIT_31_20 20 31 regSB_PREF_BASE_LIMIT 0 0xe85004 2 0 5 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_31_20 20 31 regSB_PREF_BASE_UPPER 0 0xe85005 1 0 5 PREF_BASE_UPPER 0 31 regSB_PREF_LIMIT_UPPER 0 0xe85006 1 0 5 PREF_LIMIT_UPPER 0 31 regSB_IO_BASE_LIMIT_HI 0 0xe85007 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regSB_IRQ_BRIDGE_CNTL 0 0xe85008 3 0 5 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 regSB_EXT_BRIDGE_CNTL 0 0xe85009 1 0 5 IO_PORT_80_EN 0 0 regSB_PMI_STATUS_CNTL 0 0xe8500a 1 0 5 POWER_STATE 0 1 regSB_SLOT_CAP 0 0xe8500b 2 0 5 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 regSB_ROOT_CNTL 0 0xe8500c 1 0 5 CRS_SOFTWARE_VISIBILITY_EN 4 4 regSB_DEVICE_CNTL2 0 0xe8500d 1 0 5 ARI_FORWARDING_EN 5 5 regMCA_SMN_INT_REQ_ADDR 0 0xe85020 1 0 5 SMN_INT_REQ_ADDR 0 19 regMCA_SMN_INT_MCM_ADDR 0 0xe85021 1 0 5 SMN_INT_MCM_ADDR 0 3 regMCA_SMN_INT_APERTUREID 0 0xe85022 1 0 5 SMN_INT_APERTUREID 0 11 regMCA_SMN_INT_CONTROL 0 0xe85023 1 0 5 MCACrossTrigger 0 3 regPARITY_CONTROL_0 0 0xe88000 2 0 5 ParityCorrThreshold 0 15 ParityUCPThreshold 16 31 regPARITY_CONTROL_1 0 0xe88001 6 0 5 ParityErrGenGroupSel 0 7 ParityErrGenGroupTypeSel 8 8 ParityErrGenIdSel 11 15 ParityErrGenCmd 16 19 ParityErrGenTrigger 30 30 ParityErrGenInjectAllow 31 31 regPARITY_SEVERITY_CONTROL_UNCORR_0 0 0xe88002 8 0 5 ParityErrSevUnCorrGrp0 0 1 ParityErrSevUnCorrGrp1 2 3 ParityErrSevUnCorrGrp2 4 5 ParityErrSevUnCorrGrp3 6 7 ParityErrSevUnCorrGrp4 8 9 ParityErrSevUnCorrGrp5 10 11 ParityErrSevUnCorrGrp6 12 13 ParityErrSevUnCorrGrp7 14 15 regPARITY_SEVERITY_CONTROL_CORR_0 0 0xe88004 8 0 5 ParityErrSevCorrGrp0 0 1 ParityErrSevCorrGrp1 2 3 ParityErrSevCorrGrp2 4 5 ParityErrSevCorrGrp3 6 7 ParityErrSevCorrGrp4 8 9 ParityErrSevCorrGrp5 10 11 ParityErrSevCorrGrp6 12 13 ParityErrSevCorrGrp7 14 15 regPARITY_SEVERITY_CONTROL_UCP_0 0 0xe88006 8 0 5 ParityErrSevUCPGrp0 0 1 ParityErrSevUCPGrp1 2 3 ParityErrSevUCPGrp2 4 5 ParityErrSevUCPGrp3 6 7 ParityErrSevUCPGrp4 8 9 ParityErrSevUCPGrp5 10 11 ParityErrSevUCPGrp6 12 13 ParityErrSevUCPGrp7 14 15 regRAS_GLOBAL_STATUS_LO 0 0xe88008 14 0 5 ParityErrCorr 0 0 ParityErrNonFatal 1 1 ParityErrFatal 2 2 ParityErrSerr 3 3 HPLGWA_NMI 6 6 HPLGWA_SCI 7 7 HPLGWA_SMI 8 8 SW_SMI 9 9 SW_SCI 10 10 SW_NMI 11 11 APML_NMI 12 12 APML_SyncFld 13 13 PIN_SyncFld_NMI 14 14 APML_SyncFld_Private 15 15 regRAS_GLOBAL_STATUS_HI 0 0xe88009 10 0 5 PCIE0PortAErr 0 0 PCIE0PortBErr 1 1 PCIE0PortCErr 2 2 PCIE0PortDErr 3 3 PCIE0PortEErr 4 4 PCIE0PortFErr 5 5 PCIE0PortGErr 6 6 NBIF1PortAErr 7 7 NBIF1PortBErr 8 8 NBIF1PortCErr 9 9 regPARITY_ERROR_STATUS_UNCORR_GRP0 0 0xe8800a 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP1 0 0xe8800b 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP2 0 0xe8800c 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP3 0 0xe8800d 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP4 0 0xe8800e 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP5 0 0xe8800f 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP6 0 0xe88010 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UNCORR_GRP7 0 0xe88011 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP0 0 0xe88012 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP1 0 0xe88013 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP2 0 0xe88014 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP3 0 0xe88015 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP4 0 0xe88016 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP5 0 0xe88017 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP6 0 0xe88018 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_CORR_GRP7 0 0xe88019 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_COUNTER_CORR_GRP0 0 0xe8801a 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP1 0 0xe8801b 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP2 0 0xe8801c 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP3 0 0xe8801d 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP4 0 0xe8801e 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP5 0 0xe8801f 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP6 0 0xe88020 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_CORR_GRP7 0 0xe88021 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_ERROR_STATUS_UCP_GRP0 0 0xe88022 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP1 0 0xe88023 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP2 0 0xe88024 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP3 0 0xe88025 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP4 0 0xe88026 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP5 0 0xe88027 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP6 0 0xe88028 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_ERROR_STATUS_UCP_GRP7 0 0xe88029 32 0 5 ParityErrDetected_Id0 0 0 ParityErrDetected_Id1 1 1 ParityErrDetected_Id2 2 2 ParityErrDetected_Id3 3 3 ParityErrDetected_Id4 4 4 ParityErrDetected_Id5 5 5 ParityErrDetected_Id6 6 6 ParityErrDetected_Id7 7 7 ParityErrDetected_Id8 8 8 ParityErrDetected_Id9 9 9 ParityErrDetected_Id10 10 10 ParityErrDetected_Id11 11 11 ParityErrDetected_Id12 12 12 ParityErrDetected_Id13 13 13 ParityErrDetected_Id14 14 14 ParityErrDetected_Id15 15 15 ParityErrDetected_Id16 16 16 ParityErrDetected_Id17 17 17 ParityErrDetected_Id18 18 18 ParityErrDetected_Id19 19 19 ParityErrDetected_Id20 20 20 ParityErrDetected_Id21 21 21 ParityErrDetected_Id22 22 22 ParityErrDetected_Id23 23 23 ParityErrDetected_Id24 24 24 ParityErrDetected_Id25 25 25 ParityErrDetected_Id26 26 26 ParityErrDetected_Id27 27 27 ParityErrDetected_Id28 28 28 ParityErrDetected_Id29 29 29 ParityErrDetected_Id30 30 30 ParityErrDetected_Id31 31 31 regPARITY_COUNTER_UCP_GRP0 0 0xe8802a 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP1 0 0xe8802b 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP2 0 0xe8802c 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP3 0 0xe8802d 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP4 0 0xe8802e 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP5 0 0xe8802f 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP6 0 0xe88030 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regPARITY_COUNTER_UCP_GRP7 0 0xe88031 2 0 5 ThresholdCounter 0 15 ResetEn 31 31 regMISC_SEVERITY_CONTROL 0 0xe88032 2 0 5 ErrEventErrSev 4 5 PcieParityErrSev 6 7 regMISC_RAS_CONTROL 0 0xe88033 10 0 5 PIN_NMI_SyncFlood_En 2 2 InterruptOutputDis 9 9 LinkDisOutputDis 10 10 SyncFldOutputDis 11 11 PCIe_NMI_En 12 12 PCIe_SCI_En 13 13 PCIe_SMI_En 14 14 SW_SCI_En 15 15 SW_SMI_En 16 16 SW_NMI_En 17 17 regRAS_SCRATCH_0 0 0xe88034 1 0 5 SCRATCH_0 0 31 regRAS_SCRATCH_1 0 0xe88035 1 0 5 SCRATCH_1 0 31 regErrEvent_ACTION_CONTROL 0 0xe88036 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regParitySerr_ACTION_CONTROL 0 0xe88037 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regParityFatal_ACTION_CONTROL 0 0xe88038 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regParityNonFatal_ACTION_CONTROL 0 0xe88039 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regParityCorr_ACTION_CONTROL 0 0xe8803a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortASerr_ACTION_CONTROL 0 0xe8803b 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAIntFatal_ACTION_CONTROL 0 0xe8803c 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAIntNonFatal_ACTION_CONTROL 0 0xe8803d 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAIntCorr_ACTION_CONTROL 0 0xe8803e 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAExtFatal_ACTION_CONTROL 0 0xe8803f 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAExtNonFatal_ACTION_CONTROL 0 0xe88040 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAExtCorr_ACTION_CONTROL 0 0xe88041 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortAParityErr_ACTION_CONTROL 0 0xe88042 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBSerr_ACTION_CONTROL 0 0xe88043 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBIntFatal_ACTION_CONTROL 0 0xe88044 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBIntNonFatal_ACTION_CONTROL 0 0xe88045 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBIntCorr_ACTION_CONTROL 0 0xe88046 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBExtFatal_ACTION_CONTROL 0 0xe88047 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBExtNonFatal_ACTION_CONTROL 0 0xe88048 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBExtCorr_ACTION_CONTROL 0 0xe88049 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortBParityErr_ACTION_CONTROL 0 0xe8804a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCSerr_ACTION_CONTROL 0 0xe8804b 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCIntFatal_ACTION_CONTROL 0 0xe8804c 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCIntNonFatal_ACTION_CONTROL 0 0xe8804d 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCIntCorr_ACTION_CONTROL 0 0xe8804e 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCExtFatal_ACTION_CONTROL 0 0xe8804f 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCExtNonFatal_ACTION_CONTROL 0 0xe88050 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCExtCorr_ACTION_CONTROL 0 0xe88051 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortCParityErr_ACTION_CONTROL 0 0xe88052 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDSerr_ACTION_CONTROL 0 0xe88053 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDIntFatal_ACTION_CONTROL 0 0xe88054 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDIntNonFatal_ACTION_CONTROL 0 0xe88055 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDIntCorr_ACTION_CONTROL 0 0xe88056 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDExtFatal_ACTION_CONTROL 0 0xe88057 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDExtNonFatal_ACTION_CONTROL 0 0xe88058 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDExtCorr_ACTION_CONTROL 0 0xe88059 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortDParityErr_ACTION_CONTROL 0 0xe8805a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortESerr_ACTION_CONTROL 0 0xe8805b 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEIntFatal_ACTION_CONTROL 0 0xe8805c 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEIntNonFatal_ACTION_CONTROL 0 0xe8805d 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEIntCorr_ACTION_CONTROL 0 0xe8805e 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEExtFatal_ACTION_CONTROL 0 0xe8805f 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEExtNonFatal_ACTION_CONTROL 0 0xe88060 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEExtCorr_ACTION_CONTROL 0 0xe88061 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortEParityErr_ACTION_CONTROL 0 0xe88062 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFSerr_ACTION_CONTROL 0 0xe88063 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFIntFatal_ACTION_CONTROL 0 0xe88064 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFIntNonFatal_ACTION_CONTROL 0 0xe88065 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFIntCorr_ACTION_CONTROL 0 0xe88066 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFExtFatal_ACTION_CONTROL 0 0xe88067 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFExtNonFatal_ACTION_CONTROL 0 0xe88068 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFExtCorr_ACTION_CONTROL 0 0xe88069 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortFParityErr_ACTION_CONTROL 0 0xe8806a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGSerr_ACTION_CONTROL 0 0xe8806b 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGIntFatal_ACTION_CONTROL 0 0xe8806c 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGIntNonFatal_ACTION_CONTROL 0 0xe8806d 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGIntCorr_ACTION_CONTROL 0 0xe8806e 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGExtFatal_ACTION_CONTROL 0 0xe8806f 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGExtNonFatal_ACTION_CONTROL 0 0xe88070 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGExtCorr_ACTION_CONTROL 0 0xe88071 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regPCIE0PortGParityErr_ACTION_CONTROL 0 0xe88072 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortASerr_ACTION_CONTROL 0 0xe88073 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAIntFatal_ACTION_CONTROL 0 0xe88074 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAIntNonFatal_ACTION_CONTROL 0 0xe88075 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAIntCorr_ACTION_CONTROL 0 0xe88076 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAExtFatal_ACTION_CONTROL 0 0xe88077 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAExtNonFatal_ACTION_CONTROL 0 0xe88078 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAExtCorr_ACTION_CONTROL 0 0xe88079 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortAParityErr_ACTION_CONTROL 0 0xe8807a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBSerr_ACTION_CONTROL 0 0xe8807b 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBIntFatal_ACTION_CONTROL 0 0xe8807c 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBIntNonFatal_ACTION_CONTROL 0 0xe8807d 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBIntCorr_ACTION_CONTROL 0 0xe8807e 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBExtFatal_ACTION_CONTROL 0 0xe8807f 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBExtNonFatal_ACTION_CONTROL 0 0xe88080 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBExtCorr_ACTION_CONTROL 0 0xe88081 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortBParityErr_ACTION_CONTROL 0 0xe88082 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCSerr_ACTION_CONTROL 0 0xe88083 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCIntFatal_ACTION_CONTROL 0 0xe88084 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCIntNonFatal_ACTION_CONTROL 0 0xe88085 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCIntCorr_ACTION_CONTROL 0 0xe88086 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCExtFatal_ACTION_CONTROL 0 0xe88087 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCExtNonFatal_ACTION_CONTROL 0 0xe88088 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCExtCorr_ACTION_CONTROL 0 0xe88089 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regNBIF1PortCParityErr_ACTION_CONTROL 0 0xe8808a 4 0 5 APML_ERR_En 0 0 IntrGenSel 1 2 LinkDis_En 3 3 SyncFlood_En 4 4 regSYNCFLOOD_STATUS 0 0xe88200 29 0 5 SyncfloodFromRASCntl 0 0 SyncfloodFromAPML 1 1 SyncfloodFromPin 2 2 SyncfloodFromPrivate 4 4 SyncfloodFromMCA 5 5 SyncfloodFromIOHCPortN_8 8 8 SyncfloodFromIOHCPortN_9 9 9 SyncfloodFromIOHCPortN_10 10 10 SyncfloodFromIOHCPortN_11 11 11 SyncfloodFromIOHCPortN_12 12 12 SyncfloodFromIOHCPortN_13 13 13 SyncfloodFromIOHCPortN_14 14 14 SyncfloodFromIOHCPortN_15 15 15 SyncfloodFromIOHCPortN_16 16 16 SyncfloodFromIOHCPortN_17 17 17 SyncfloodFromIOHCPortN_18 18 18 SyncfloodFromIOHCPortN_19 19 19 SyncfloodFromIOHCPortN_20 20 20 SyncfloodFromIOHCPortN_21 21 21 SyncfloodFromIOHCPortN_22 22 22 SyncfloodFromIOHCPortN_23 23 23 SyncfloodFromIOHCPortN_24 24 24 SyncfloodFromIOHCPortN_25 25 25 SyncfloodFromIOHCPortN_26 26 26 SyncfloodFromIOHCPortN_27 27 27 SyncfloodFromIOHCPortN_28 28 28 SyncfloodFromIOHCPortN_29 29 29 SyncfloodFromIOHCPortN_30 30 30 SyncfloodFromIOHCPortN_31 31 31 regNMI_STATUS 0 0xe88201 1 0 5 NMIFromPin 0 0 regPOISON_ACTION_CONTROL 0 0xe88205 12 0 5 IntPoisonAPMLErrEn 0 0 IntPoisonIntrGenSel 1 2 IntPoisonLinkDisEn 3 3 IntPoisonSyncFloodEn 4 4 EgressPoisonLSAPMLErrEn 8 8 EgressPoisonLSIntrGenSel 9 10 EgressPoisonLSLinkDisEn 11 11 EgressPoisonLSSyncFloodEn 12 12 EgressPoisonHSAPMLErrEn 16 16 EgressPoisonHSIntrGenSel 17 18 EgressPoisonHSLinkDisEn 19 19 EgressPoisonHSSyncFloodEn 20 20 regEGRESS_POISON_STATUS_LO 0 0xe88208 32 0 5 EgressPoisonStatusLo_0 0 0 EgressPoisonStatusLo_1 1 1 EgressPoisonStatusLo_2 2 2 EgressPoisonStatusLo_3 3 3 EgressPoisonStatusLo_4 4 4 EgressPoisonStatusLo_5 5 5 EgressPoisonStatusLo_6 6 6 EgressPoisonStatusLo_7 7 7 EgressPoisonStatusLo_8 8 8 EgressPoisonStatusLo_9 9 9 EgressPoisonStatusLo_10 10 10 EgressPoisonStatusLo_11 11 11 EgressPoisonStatusLo_12 12 12 EgressPoisonStatusLo_13 13 13 EgressPoisonStatusLo_14 14 14 EgressPoisonStatusLo_15 15 15 EgressPoisonStatusLo_16 16 16 EgressPoisonStatusLo_17 17 17 EgressPoisonStatusLo_18 18 18 EgressPoisonStatusLo_19 19 19 EgressPoisonStatusLo_20 20 20 EgressPoisonStatusLo_21 21 21 EgressPoisonStatusLo_22 22 22 EgressPoisonStatusLo_23 23 23 EgressPoisonStatusLo_24 24 24 EgressPoisonStatusLo_25 25 25 EgressPoisonStatusLo_26 26 26 EgressPoisonStatusLo_27 27 27 EgressPoisonStatusLo_28 28 28 EgressPoisonStatusLo_29 29 29 EgressPoisonStatusLo_30 30 30 EgressPoisonStatusLo_31 31 31 regEGRESS_POISON_STATUS_HI 0 0xe88209 32 0 5 EgressPoisonStatusHi_0 0 0 EgressPoisonStatusHi_1 1 1 EgressPoisonStatusHi_2 2 2 EgressPoisonStatusHi_3 3 3 EgressPoisonStatusHi_4 4 4 EgressPoisonStatusHi_5 5 5 EgressPoisonStatusHi_6 6 6 EgressPoisonStatusHi_7 7 7 EgressPoisonStatusHi_8 8 8 EgressPoisonStatusHi_9 9 9 EgressPoisonStatusHi_10 10 10 EgressPoisonStatusHi_11 11 11 EgressPoisonStatusHi_12 12 12 EgressPoisonStatusHi_13 13 13 EgressPoisonStatusHi_14 14 14 EgressPoisonStatusHi_15 15 15 EgressPoisonStatusHi_16 16 16 EgressPoisonStatusHi_17 17 17 EgressPoisonStatusHi_18 18 18 EgressPoisonStatusHi_19 19 19 EgressPoisonStatusHi_20 20 20 EgressPoisonStatusHi_21 21 21 EgressPoisonStatusHi_22 22 22 EgressPoisonStatusHi_23 23 23 EgressPoisonStatusHi_24 24 24 EgressPoisonStatusHi_25 25 25 EgressPoisonStatusHi_26 26 26 EgressPoisonStatusHi_27 27 27 EgressPoisonStatusHi_28 28 28 EgressPoisonStatusHi_29 29 29 EgressPoisonStatusHi_30 30 30 EgressPoisonStatusHi_31 31 31 regEGRESS_POISON_MASK_LO 0 0xe8820a 1 0 5 EgressPoisonMaskLo 0 31 regEGRESS_POISON_MASK_HI 0 0xe8820b 1 0 5 EgressPoisonMaskHi 0 31 regEGRESS_POISON_SEVERITY_DOWN 0 0xe8820c 1 0 5 EgressPoisonSeverityDown 0 31 regEGRESS_POISON_SEVERITY_UPPER 0 0xe8820d 1 0 5 EgressPoisonSeverityUpper 0 31 regAPML_STATUS 0 0xe88370 7 0 5 APML_Corr 0 0 APML_NonFatal 1 1 APML_Fatal 2 2 APML_Serr 3 3 APML_IntPoisonErr 4 4 APML_EgressPoisonErrLo 5 5 APML_EgressPoisonErrHi 6 6 regAPML_CONTROL 0 0xe88371 3 0 5 APML_NMI_En 0 0 APML_SyncFlood_En 1 1 APML_OutputDis 8 8 regAPML_TRIGGER 0 0xe88372 1 0 5 APML_NMI_TRIGGER 0 0 regBIF_BX_PF2_MM_INDEX 0 0x2ffc0000 2 0 5 MM_OFFSET 0 30 MM_APER 31 31 regBIF_BX_PF2_MM_DATA 0 0x2ffc0001 1 0 5 MM_DATA 0 31 regBIF_BX_PF2_MM_INDEX_HI 0 0x2ffc0006 1 0 5 MM_OFFSET_HI 0 31 regBIF_BX2_PCIE_INDEX 0 0x2ffc000c 1 0 5 PCIE_INDEX 0 31 regBIF_BX2_PCIE_DATA 0 0x2ffc000d 1 0 5 PCIE_DATA 0 31 regBIF_BX2_PCIE_INDEX2 0 0x2ffc000e 1 0 5 PCIE_INDEX2 0 31 regBIF_BX2_PCIE_DATA2 0 0x2ffc000f 1 0 5 PCIE_DATA2 0 31 regBIF_BX2_SBIOS_SCRATCH_0 0 0x2ffc0048 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX2_SBIOS_SCRATCH_1 0 0x2ffc0049 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX2_SBIOS_SCRATCH_2 0 0x2ffc004a 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX2_SBIOS_SCRATCH_3 0 0x2ffc004b 1 0 5 SBIOS_SCRATCH_DW 0 31 regBIF_BX2_BIOS_SCRATCH_0 0 0x2ffc004c 1 0 5 BIOS_SCRATCH_0 0 31 regBIF_BX2_BIOS_SCRATCH_1 0 0x2ffc004d 1 0 5 BIOS_SCRATCH_1 0 31 regBIF_BX2_BIOS_SCRATCH_2 0 0x2ffc004e 1 0 5 BIOS_SCRATCH_2 0 31 regBIF_BX2_BIOS_SCRATCH_3 0 0x2ffc004f 1 0 5 BIOS_SCRATCH_3 0 31 regBIF_BX2_BIOS_SCRATCH_4 0 0x2ffc0050 1 0 5 BIOS_SCRATCH_4 0 31 regBIF_BX2_BIOS_SCRATCH_5 0 0x2ffc0051 1 0 5 BIOS_SCRATCH_5 0 31 regBIF_BX2_BIOS_SCRATCH_6 0 0x2ffc0052 1 0 5 BIOS_SCRATCH_6 0 31 regBIF_BX2_BIOS_SCRATCH_7 0 0x2ffc0053 1 0 5 BIOS_SCRATCH_7 0 31 regBIF_BX2_BIOS_SCRATCH_8 0 0x2ffc0054 1 0 5 BIOS_SCRATCH_8 0 31 regBIF_BX2_BIOS_SCRATCH_9 0 0x2ffc0055 1 0 5 BIOS_SCRATCH_9 0 31 regBIF_BX2_BIOS_SCRATCH_10 0 0x2ffc0056 1 0 5 BIOS_SCRATCH_10 0 31 regBIF_BX2_BIOS_SCRATCH_11 0 0x2ffc0057 1 0 5 BIOS_SCRATCH_11 0 31 regBIF_BX2_BIOS_SCRATCH_12 0 0x2ffc0058 1 0 5 BIOS_SCRATCH_12 0 31 regBIF_BX2_BIOS_SCRATCH_13 0 0x2ffc0059 1 0 5 BIOS_SCRATCH_13 0 31 regBIF_BX2_BIOS_SCRATCH_14 0 0x2ffc005a 1 0 5 BIOS_SCRATCH_14 0 31 regBIF_BX2_BIOS_SCRATCH_15 0 0x2ffc005b 1 0 5 BIOS_SCRATCH_15 0 31 regBIF_BX2_BIF_RLC_INTR_CNTL 0 0x2ffc0060 4 0 5 RLC_CMD_COMPLETE 0 0 RLC_HANG_SELF_RECOVERED 1 1 RLC_HANG_NEED_FLR 2 2 RLC_VM_BUSY_TRANSITION 3 3 regBIF_BX2_BIF_VCE_INTR_CNTL 0 0x2ffc0061 4 0 5 VCE_CMD_COMPLETE 0 0 VCE_HANG_SELF_RECOVERED 1 1 VCE_HANG_NEED_FLR 2 2 VCE_VM_BUSY_TRANSITION 3 3 regBIF_BX2_BIF_UVD_INTR_CNTL 0 0x2ffc0062 5 0 5 UVD_CMD_COMPLETE 0 0 UVD_HANG_SELF_RECOVERED 1 1 UVD_HANG_NEED_FLR 2 2 UVD_VM_BUSY_TRANSITION 3 3 UVD_INST_SEL 28 31 regBIF_BX2_GFX_MMIOREG_CAM_ADDR0 0 0x2ffc0080 1 0 5 CAM_ADDR0 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0 0 0x2ffc0081 1 0 5 CAM_REMAP_ADDR0 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR1 0 0x2ffc0082 1 0 5 CAM_ADDR1 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1 0 0x2ffc0083 1 0 5 CAM_REMAP_ADDR1 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR2 0 0x2ffc0084 1 0 5 CAM_ADDR2 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2 0 0x2ffc0085 1 0 5 CAM_REMAP_ADDR2 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR3 0 0x2ffc0086 1 0 5 CAM_ADDR3 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3 0 0x2ffc0087 1 0 5 CAM_REMAP_ADDR3 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR4 0 0x2ffc0088 1 0 5 CAM_ADDR4 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4 0 0x2ffc0089 1 0 5 CAM_REMAP_ADDR4 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR5 0 0x2ffc008a 1 0 5 CAM_ADDR5 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5 0 0x2ffc008b 1 0 5 CAM_REMAP_ADDR5 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR6 0 0x2ffc008c 1 0 5 CAM_ADDR6 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6 0 0x2ffc008d 1 0 5 CAM_REMAP_ADDR6 0 19 regBIF_BX2_GFX_MMIOREG_CAM_ADDR7 0 0x2ffc008e 1 0 5 CAM_ADDR7 0 19 regBIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7 0 0x2ffc008f 1 0 5 CAM_REMAP_ADDR7 0 19 regBIF_BX2_GFX_MMIOREG_CAM_CNTL 0 0x2ffc0090 1 0 5 CAM_ENABLE 0 7 regBIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL 0 0x2ffc0091 1 0 5 CAM_ZERO_CPL 0 31 regBIF_BX2_GFX_MMIOREG_CAM_ONE_CPL 0 0x2ffc0092 1 0 5 CAM_ONE_CPL 0 31 regBIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0 0x2ffc0093 1 0 5 CAM_PROGRAMMABLE_CPL 0 31 regRCC_STRAP3_RCC_BIF_STRAP0 0 0x2ffc0d20 22 0 5 STRAP_GEN4_DIS_PIN 0 0 STRAP_VGA_DIS_PIN 2 2 STRAP_MEM_AP_SIZE_PIN 3 5 STRAP_BIOS_ROM_EN_PIN 6 6 STRAP_PX_CAPABLE 7 7 STRAP_BIF_KILL_GEN3 8 8 STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN 9 9 STRAP_NBIF_IGNORE_ERR_INFLR 10 10 STRAP_PME_SUPPORT_COMPLIANCE_EN 11 11 STRAP_RX_IGNORE_EP_ERR 12 12 STRAP_RX_IGNORE_MSG_ERR 13 13 STRAP_RX_IGNORE_MAX_PAYLOAD_ERR 14 14 STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN 15 15 STRAP_RX_IGNORE_TC_ERR 16 16 STRAP_RX_IGNORE_TC_ERR_DN 17 17 STRAP_GEN3_DIS 24 24 STRAP_BIF_KILL_GEN4 25 25 STRAP_QUICKSIM_START 26 26 STRAP_NO_RO_ENABLED_P2P_PASSING 27 27 STRAP_CFG0_RD_VF_BUSNUM_CHK_EN 29 29 STRAP_BIGAPU_MODE 30 30 STRAP_LINK_DOWN_RESET_EN 31 31 regRCC_STRAP3_RCC_BIF_STRAP1 0 0x2ffc0d21 21 0 5 ROMSTRAP_VALID 1 1 STRAP_ECRC_INTERMEDIATE_CHK_EN 3 3 STRAP_IGNORE_E2E_PREFIX_UR_SWUS 5 5 STRAP_MARGINING_USES_SOFTWARE 6 6 STRAP_MARGINING_READY 7 7 STRAP_SWUS_APER_EN 8 8 STRAP_SWUS_64BAR_EN 9 9 STRAP_SWUS_AP_SIZE 10 11 STRAP_SWUS_APER_PREFETCHABLE 12 12 STRAP_HWREV_LSB2 13 14 STRAP_SWREV_LSB2 15 16 STRAP_LINK_RST_CFG_ONLY 17 17 STRAP_BIF_IOV_LKRST_DIS 18 18 STRAP_DLF_EN 19 19 STRAP_PHY_16GT_EN 20 20 STRAP_MARGIN_EN 21 21 STRAP_BIF_PSN_UR_RPT_EN 22 22 STRAP_BIF_SLOT_POWER_SUPPORT_EN 23 23 STRAP_GFX_FUNC_LTR_MODE 26 26 STRAP_GSI_SMN_POSTWR_MULTI_EN 27 28 STRAP_DLF_EN_EP 29 29 regRCC_STRAP3_RCC_BIF_STRAP2 0 0x2ffc0d22 14 0 5 STRAP_PCIESWUS_INDEX_APER_RANGE 0 0 STRAP_SUC_IND_ACCESS_DIS 3 3 STRAP_SUM_IND_ACCESS_DIS 4 4 STRAP_ENDP_LINKDOWN_DROP_DMA 5 5 STRAP_SWITCH_LINKDOWN_DROP_DMA 6 6 STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS 8 8 STRAP_ACS_MSKSEV_EP_HIDE_DIS 9 9 STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN 10 11 RESERVED_BIF_STRAP2 13 13 STRAP_LTR_IN_ASPML1_DIS 14 14 STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN 15 15 STRAP_PWRBRK_DEGLITCH_CYCLE 16 23 STRAP_PWRBRK_DEGLITCH_BYPASS 24 24 STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS 31 31 regRCC_STRAP3_RCC_BIF_STRAP3 0 0x2ffc0d23 2 0 5 STRAP_VLINK_ASPM_IDLE_TIMER 0 15 STRAP_VLINK_PM_L1_ENTRY_TIMER 16 31 regRCC_STRAP3_RCC_BIF_STRAP4 0 0x2ffc0d24 2 0 5 STRAP_VLINK_L0S_EXIT_TIMER 0 15 STRAP_VLINK_L1_EXIT_TIMER 16 31 regRCC_STRAP3_RCC_BIF_STRAP5 0 0x2ffc0d25 11 0 5 STRAP_VLINK_LDN_ENTRY_TIMER 0 15 STRAP_VLINK_LDN_ON_SWUS_LDN_EN 16 16 STRAP_VLINK_LDN_ON_SWUS_SECRST_EN 17 17 STRAP_VLINK_ENTER_COMPLIANCE_DIS 18 18 STRAP_IGNORE_PSN_ON_VDM1_DIS 19 19 STRAP_SMN_ERR_STATUS_MASK_EN_UPS 20 20 STRAP_SMN_ERRRSP_DATA_FORCE 22 23 STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE 24 24 STRAP_EMER_POWER_REDUCTION_SUPPORTED 25 26 STRAP_EMER_POWER_REDUCTION_INIT_REQ 27 27 STRAP_PWRBRK_STATUS_TIMER 28 30 regRCC_STRAP3_RCC_BIF_STRAP6 0 0x2ffc0d26 0 0 5 regRCC_STRAP3_RCC_DEV0_PORT_STRAP0 0 0x2ffc0d27 10 0 5 STRAP_ARI_EN_DN_DEV0 1 1 STRAP_ACS_EN_DN_DEV0 2 2 STRAP_AER_EN_DN_DEV0 3 3 STRAP_CPL_ABORT_ERR_EN_DN_DEV0 4 4 STRAP_DEVICE_ID_DN_DEV0 5 20 STRAP_INTERRUPT_PIN_DN_DEV0 21 23 STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0 24 24 STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0 25 27 STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0 28 30 STRAP_EPF0_DUMMY_EN_DEV0 31 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP1 0 0x2ffc0d28 2 0 5 STRAP_SUBSYS_ID_DN_DEV0 0 15 STRAP_SUBSYS_VEN_ID_DN_DEV0 16 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP2 0 0x2ffc0d29 20 0 5 STRAP_DE_EMPHASIS_SEL_DN_DEV0 0 0 STRAP_DSN_EN_DN_DEV0 1 1 STRAP_E2E_PREFIX_EN_DEV0 2 2 STRAP_ECN1P1_EN_DEV0 3 3 STRAP_ECRC_CHECK_EN_DEV0 4 4 STRAP_ERR_REPORTING_DIS_DEV0 6 6 STRAP_EXTENDED_FMT_SUPPORTED_DEV0 7 7 STRAP_EXTENDED_TAG_ECN_EN_DEV0 8 8 STRAP_EXT_VC_COUNT_DN_DEV0 9 11 STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0 12 12 STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0 13 13 STRAP_GEN2_COMPLIANCE_DEV0 14 14 STRAP_GEN2_EN_DEV0 15 15 STRAP_GEN3_COMPLIANCE_DEV0 16 16 STRAP_GEN4_COMPLIANCE_DEV0 17 17 STRAP_TARGET_LINK_SPEED_DEV0 18 19 STRAP_L0S_ACCEPTABLE_LATENCY_DEV0 20 22 STRAP_L0S_EXIT_LATENCY_DEV0 23 25 STRAP_L1_ACCEPTABLE_LATENCY_DEV0 26 28 STRAP_L1_EXIT_LATENCY_DEV0 29 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP3 0 0x2ffc0d2a 16 0 5 STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0 0 0 STRAP_LTR_EN_DEV0 1 1 STRAP_LTR_EN_DN_DEV0 2 2 STRAP_MAX_PAYLOAD_SUPPORT_DEV0 3 5 STRAP_MSI_EN_DN_DEV0 6 6 STRAP_MSTCPL_TIMEOUT_EN_DEV0 7 7 STRAP_NO_SOFT_RESET_DN_DEV0 8 8 STRAP_OBFF_SUPPORTED_DEV0 9 10 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0 11 13 STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0 14 17 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0 18 20 STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0 21 24 STRAP_PM_SUPPORT_DEV0 25 26 STRAP_PM_SUPPORT_DN_DEV0 27 28 STRAP_ATOMIC_EN_DN_DEV0 29 29 STRAP_PMC_DSI_DN_DEV0 31 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP4 0 0x2ffc0d2b 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_0_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_1_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_2_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_3_DEV0 24 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP5 0 0x2ffc0d2c 18 0 5 STRAP_PWR_BUDGET_DATA_8T0_4_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_5_DEV0 8 15 STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0 16 16 STRAP_ATOMIC_64BIT_EN_DN_DEV0 17 17 STRAP_ATOMIC_ROUTING_EN_DEV0 18 18 STRAP_VC_EN_DN_DEV0 19 19 STRAP_TwoVC_EN_DEV0 20 20 STRAP_TwoVC_EN_DN_DEV0 21 21 STRAP_LOCAL_DLF_SUPPORTED_DEV0 22 22 STRAP_ACS_SOURCE_VALIDATION_DN_DEV0 23 23 STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0 24 24 STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0 25 25 STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0 26 26 STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0 27 27 STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0 28 28 STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0 29 29 STRAP_MSI_MAP_EN_DEV0 30 30 STRAP_SSID_EN_DEV0 31 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP6 0 0x2ffc0d2d 12 0 5 STRAP_CFG_CRS_EN_DEV0 0 0 STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0 1 1 STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0 3 3 STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0 4 4 STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0 5 5 STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 6 6 STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0 7 7 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0 8 11 STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0 12 15 STRAP_TPH_CPLR_SUPPORTED_DN_DEV0 16 17 STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0 18 18 STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0 19 19 regRCC_STRAP3_RCC_DEV0_PORT_STRAP7 0 0x2ffc0d2e 6 0 5 STRAP_PORT_NUMBER_DEV0 0 7 STRAP_MAJOR_REV_ID_DN_DEV0 8 11 STRAP_MINOR_REV_ID_DN_DEV0 12 15 STRAP_RP_BUSNUM_DEV0 16 23 STRAP_DN_DEVNUM_DEV0 24 28 STRAP_DN_FUNCID_DEV0 29 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP8 0 0x2ffc0d2f 4 0 5 STRAP_PWR_BUDGET_DATA_8T0_6_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_7_DEV0 8 15 STRAP_PWR_BUDGET_DATA_8T0_8_DEV0 16 23 STRAP_PWR_BUDGET_DATA_8T0_9_DEV0 24 31 regRCC_STRAP3_RCC_DEV0_PORT_STRAP9 0 0x2ffc0d30 3 0 5 STRAP_PWR_BUDGET_DATA_8T0_a_DEV0 0 7 STRAP_PWR_BUDGET_DATA_8T0_b_DEV0 8 15 STRAP_VENDOR_ID_DN_DEV0 16 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP0 0 0x2ffc0d31 8 0 5 STRAP_DEVICE_ID_DEV0_F0 0 15 STRAP_MAJOR_REV_ID_DEV0_F0 16 19 STRAP_MINOR_REV_ID_DEV0_F0 20 23 STRAP_ATI_REV_ID_DEV0_F0 24 27 STRAP_FUNC_EN_DEV0_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 29 29 STRAP_D1_SUPPORT_DEV0_F0 30 30 STRAP_D2_SUPPORT_DEV0_F0 31 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP1 0 0x2ffc0d32 2 0 5 STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0 0 15 STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0 16 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP13 0 0x2ffc0d33 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F0 0 7 STRAP_CLASS_CODE_SUB_DEV0_F0 8 15 STRAP_CLASS_CODE_BASE_DEV0_F0 16 23 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP14 0 0x2ffc0d34 1 0 5 STRAP_VENDOR_ID_DEV0_F0 0 15 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP2 0 0x2ffc0d35 21 0 5 STRAP_SRIOV_EN_DEV0_F0 0 0 STRAP_SRIOV_TOTAL_VFS_DEV0_F0 1 5 STRAP_64BAR_DIS_DEV0_F0 6 6 STRAP_NO_SOFT_RESET_DEV0_F0 7 7 STRAP_RESIZE_BAR_EN_DEV0_F0 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F0 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0 14 14 STRAP_ARI_EN_DEV0_F0 15 15 STRAP_AER_EN_DEV0_F0 16 16 STRAP_ACS_EN_DEV0_F0 17 17 STRAP_ATS_EN_DEV0_F0 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F0 20 20 STRAP_DPA_EN_DEV0_F0 21 21 STRAP_DSN_EN_DEV0_F0 22 22 STRAP_VC_EN_DEV0_F0 23 23 STRAP_MSI_MULTI_CAP_DEV0_F0 24 26 STRAP_PAGE_REQ_EN_DEV0_F0 27 27 STRAP_PASID_EN_DEV0_F0 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0 31 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP3 0 0x2ffc0d36 13 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0 0 0 STRAP_PWR_EN_DEV0_F0 1 1 STRAP_SUBSYS_ID_DEV0_F0 2 17 STRAP_MSI_EN_DEV0_F0 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F0 19 19 STRAP_MSIX_EN_DEV0_F0 20 20 STRAP_MSIX_TABLE_BIR_DEV0_F0 21 23 STRAP_PMC_DSI_DEV0_F0 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0 27 27 STRAP_VF_RESIZE_BAR_EN_DEV0_F0 28 28 STRAP_CLK_PM_EN_DEV0_F0 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F0 30 30 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP4 0 0x2ffc0d37 7 0 5 STRAP_RESERVED_STRAP4_DEV0_F0 0 9 STRAP_ATOMIC_64BIT_EN_DEV0_F0 20 20 STRAP_ATOMIC_EN_DEV0_F0 21 21 STRAP_FLR_EN_DEV0_F0 22 22 STRAP_PME_SUPPORT_DEV0_F0 23 27 STRAP_INTERRUPT_PIN_DEV0_F0 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F0 31 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP5 0 0x2ffc0d38 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F0 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0 30 30 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP8 0 0x2ffc0d39 13 0 5 STRAP_DOORBELL_APER_SIZE_DEV0_F0 0 2 STRAP_DOORBELL_BAR_DIS_DEV0_F0 3 3 STRAP_ROM_AP_SIZE_DEV0_F0 4 6 STRAP_IO_BAR_DIS_DEV0_F0 7 7 STRAP_LFB_ERRMSG_EN_DEV0_F0 8 8 STRAP_MEM_AP_SIZE_DEV0_F0 9 12 STRAP_REG_AP_SIZE_DEV0_F0 13 15 STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0 16 18 STRAP_VF_MEM_AP_SIZE_DEV0_F0 19 22 STRAP_VF_REG_AP_SIZE_DEV0_F0 23 25 STRAP_VGA_DIS_DEV0_F0 26 26 STRAP_VF_MSI_MULTI_CAP_DEV0_F0 27 29 STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0 30 31 regRCC_STRAP3_RCC_DEV0_EPF0_STRAP9 0 0x2ffc0d3a 7 0 5 STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0 0 15 STRAP_BAR_COMPLIANCE_EN_DEV0_F0 18 18 STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0 19 19 STRAP_VF_REG_PROT_DIS_DEV0_F0 20 20 STRAP_FB_ALWAYS_ON_DEV0_F0 21 21 STRAP_FB_CPL_TYPE_SEL_DEV0_F0 22 23 STRAP_GPUIOV_VSEC_REV_DEV0_F0 24 27 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP0 0 0x2ffc0d3b 7 0 5 STRAP_DEVICE_ID_DEV0_F1 0 15 STRAP_MAJOR_REV_ID_DEV0_F1 16 19 STRAP_MINOR_REV_ID_DEV0_F1 20 23 STRAP_FUNC_EN_DEV0_F1 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1 29 29 STRAP_D1_SUPPORT_DEV0_F1 30 30 STRAP_D2_SUPPORT_DEV0_F1 31 31 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP10 0 0x2ffc0d3c 0 0 5 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP11 0 0x2ffc0d3d 0 0 5 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP12 0 0x2ffc0d3e 0 0 5 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP13 0 0x2ffc0d3f 3 0 5 STRAP_CLASS_CODE_PIF_DEV0_F1 0 7 STRAP_CLASS_CODE_SUB_DEV0_F1 8 15 STRAP_CLASS_CODE_BASE_DEV0_F1 16 23 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP14 0 0x2ffc0d40 1 0 5 STRAP_VENDOR_ID_DEV0_F1 0 15 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP2 0 0x2ffc0d41 16 0 5 STRAP_NO_SOFT_RESET_DEV0_F1 7 7 STRAP_RESIZE_BAR_EN_DEV0_F1 8 8 STRAP_MAX_PASID_WIDTH_DEV0_F1 9 13 STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1 14 14 STRAP_AER_EN_DEV0_F1 16 16 STRAP_ACS_EN_DEV0_F1 17 17 STRAP_ATS_EN_DEV0_F1 18 18 STRAP_CPL_ABORT_ERR_EN_DEV0_F1 20 20 STRAP_DPA_EN_DEV0_F1 21 21 STRAP_DSN_EN_DEV0_F1 22 22 STRAP_VC_EN_DEV0_F1 23 23 STRAP_MSI_MULTI_CAP_DEV0_F1 24 26 STRAP_PASID_EN_DEV0_F1 28 28 STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1 29 29 STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1 30 30 STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1 31 31 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP3 0 0x2ffc0d42 11 0 5 STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1 0 0 STRAP_PWR_EN_DEV0_F1 1 1 STRAP_SUBSYS_ID_DEV0_F1 2 17 STRAP_MSI_EN_DEV0_F1 18 18 STRAP_MSI_CLR_PENDING_EN_DEV0_F1 19 19 STRAP_MSIX_EN_DEV0_F1 20 20 STRAP_PMC_DSI_DEV0_F1 24 24 STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1 26 26 STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1 27 27 STRAP_CLK_PM_EN_DEV0_F1 29 29 STRAP_TRUE_PM_STATUS_EN_DEV0_F1 30 30 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP4 0 0x2ffc0d43 6 0 5 STRAP_ATOMIC_64BIT_EN_DEV0_F1 20 20 STRAP_ATOMIC_EN_DEV0_F1 21 21 STRAP_FLR_EN_DEV0_F1 22 22 STRAP_PME_SUPPORT_DEV0_F1 23 27 STRAP_INTERRUPT_PIN_DEV0_F1 28 30 STRAP_AUXPWR_SUPPORT_DEV0_F1 31 31 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP5 0 0x2ffc0d44 2 0 5 STRAP_SUBSYS_VEN_ID_DEV0_F1 0 15 STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1 30 30 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP6 0 0x2ffc0d45 3 0 5 STRAP_APER0_EN_DEV0_F1 0 0 STRAP_APER0_PREFETCHABLE_EN_DEV0_F1 1 1 STRAP_APER0_64BAR_EN_DEV0_F1 2 2 regRCC_STRAP3_RCC_DEV0_EPF1_STRAP7 0 0x2ffc0d46 0 0 5 regRCC_EP_DEV0_3_EP_PCIE_SCRATCH 0 0x2ffc0d47 1 0 5 PCIE_SCRATCH 0 31 regRCC_EP_DEV0_3_EP_PCIE_CNTL 0 0x2ffc0d49 3 0 5 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_EP_DEV0_3_EP_PCIE_INT_CNTL 0 0x2ffc0d4a 6 0 5 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 regRCC_EP_DEV0_3_EP_PCIE_INT_STATUS 0 0x2ffc0d4b 6 0 5 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL2 0 0x2ffc0d4c 1 0 5 RX_IGNORE_EP_INVALIDPASID_UR 0 0 regRCC_EP_DEV0_3_EP_PCIE_BUS_CNTL 0 0x2ffc0d4d 1 0 5 IMMEDIATE_PMI_DIS 7 7 regRCC_EP_DEV0_3_EP_PCIE_CFG_CNTL 0 0x2ffc0d4e 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL 0 0x2ffc0d50 10 0 5 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0 0x2ffc0d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0 0x2ffc0d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0 0x2ffc0d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0 0x2ffc0d51 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0 0x2ffc0d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0 0x2ffc0d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0 0x2ffc0d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0 0x2ffc0d52 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC 0 0x2ffc0d53 1 0 5 STRAP_MST_ADR64_EN 29 29 regRCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2 0 0x2ffc0d54 1 0 5 STRAP_TPH_SUPPORTED 4 4 regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP 0 0x2ffc0d56 4 0 5 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0x2ffc0d57 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regRCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL 0 0x2ffc0d57 2 0 5 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0x2ffc0d57 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0x2ffc0d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0x2ffc0d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0x2ffc0d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0x2ffc0d58 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0x2ffc0d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0x2ffc0d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0x2ffc0d59 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regRCC_EP_DEV0_3_EP_PCIE_PME_CONTROL 0 0x2ffc0d59 1 0 5 PME_SERVICE_TIMER 0 4 regRCC_EP_DEV0_3_EP_PCIEP_RESERVED 0 0x2ffc0d5a 1 0 5 PCIEP_RESERVED 0 31 regRCC_EP_DEV0_3_EP_PCIE_TX_CNTL 0 0x2ffc0d5c 5 0 5 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 regRCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID 0 0x2ffc0d5d 3 0 5 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 regRCC_EP_DEV0_3_EP_PCIE_ERR_CNTL 0 0x2ffc0d5e 12 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 regRCC_EP_DEV0_3_EP_PCIE_RX_CNTL 0 0x2ffc0d5f 8 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 regRCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL 0 0x2ffc0d60 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWN_DEV0_3_DN_PCIE_RESERVED 0 0x2ffc0d62 1 0 5 PCIE_RESERVED 0 31 regRCC_DWN_DEV0_3_DN_PCIE_SCRATCH 0 0x2ffc0d63 1 0 5 PCIE_SCRATCH 0 31 regRCC_DWN_DEV0_3_DN_PCIE_CNTL 0 0x2ffc0d65 3 0 5 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 regRCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL 0 0x2ffc0d66 1 0 5 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 regRCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2 0 0x2ffc0d67 1 0 5 FLR_EXTEND_MODE 28 30 regRCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL 0 0x2ffc0d68 2 0 5 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 regRCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL 0 0x2ffc0d69 4 0 5 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 regRCC_DWN_DEV0_3_DN_PCIE_STRAP_F0 0 0x2ffc0d6a 3 0 5 STRAP_F0_EN 0 0 STRAP_F0_MC_EN 17 17 STRAP_F0_MSI_MULTI_CAP 21 23 regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC 0 0x2ffc0d6b 2 0 5 STRAP_CLK_PM_EN 24 24 STRAP_MST_ADR64_EN 29 29 regRCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2 0 0x2ffc0d6c 1 0 5 STRAP_MSTCPL_TIMEOUT_EN 2 2 regRCC_DWNP_DEV0_3_PCIE_ERR_CNTL 0 0x2ffc0d6f 4 0 5 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 AER_HDR_LOG_F0_TIMER_EXPIRED 11 11 SEND_ERR_MSG_IMMEDIATELY 17 17 regRCC_DWNP_DEV0_3_PCIE_RX_CNTL 0 0x2ffc0d70 5 0 5 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 regRCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL 0 0x2ffc0d71 3 0 5 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 regRCC_DWNP_DEV0_3_PCIE_LC_CNTL2 0 0x2ffc0d72 2 0 5 DL_STATE_CHANGED_NOTIFICATION_DIS 0 0 LC_LINK_BW_NOTIFICATION_DIS 27 27 regRCC_DWNP_DEV0_3_PCIEP_STRAP_MISC 0 0x2ffc0d73 1 0 5 STRAP_MULTI_FUNC_EN 10 10 regRCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP 0 0x2ffc0d74 1 0 5 LTR_MSG_INFO_FROM_EP 0 31 regRCC_DEV0_EPF0_1_RCC_ERR_LOG 0 0x2ffc0da5 2 0 5 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_1_RCC_ERR_LOG_1 0 0x2ffc0da5 2 0 5 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_1_RCC_ERR_LOG_2 0 0x2ffc0da5 2 0 5 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN 0 0x2ffc0de0 1 0 5 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1 0 0x2ffc0de0 1 0 5 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2 0 0x2ffc0de0 1 0 5 BIF_DOORBELL_APER_EN 0 0 regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE 0 0x2ffc0de3 1 0 5 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1 0 0x2ffc0de3 1 0 5 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2 0 0x2ffc0de3 1 0 5 CONFIG_MEMSIZE 0 31 regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED 0 0x2ffc0de4 1 0 5 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1 0 0x2ffc0de4 1 0 5 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2 0 0x2ffc0de4 1 0 5 CONFIG_RESERVED 0 31 regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER 0 0x2ffc0de5 2 0 5 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1 0 0x2ffc0de5 2 0 5 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2 0 0x2ffc0de5 2 0 5 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 regRCC_DEV0_2_RCC_ERR_INT_CNTL 0 0x2ffc0da6 1 0 5 INVALID_REG_ACCESS_IN_SRIOV_INT_EN 0 0 regRCC_DEV0_2_RCC_BACO_CNTL_MISC 0 0x2ffc0da7 2 0 5 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 regRCC_DEV0_2_RCC_RESET_EN 0 0x2ffc0da8 1 0 5 DB_APER_RESET_EN 15 15 regRCC_DEV0_3_RCC_VDM_SUPPORT 0 0x2ffc0da9 5 0 5 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0 0 0x2ffc0daa 9 0 5 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 regRCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1 0 0x2ffc0dab 4 0 5 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 regRCC_DEV0_2_RCC_GPUIOV_REGION 0 0x2ffc0dac 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regRCC_DEV0_2_RCC_GPU_HOSTVM_EN 0 0x2ffc0dad 1 0 5 GPU_HOSTVM_EN 0 0 regRCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL 0 0x2ffc0dae 2 0 5 RCC_CONSOLE_IOV_MODE_ENABLE 0 0 MULTIOS_IH_SUPPORT_EN 1 1 regRCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0 0x2ffc0daf 1 0 5 CONSOLE_IOV_FIRST_VF_OFFSET 0 15 regRCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE 0 0x2ffc0daf 1 0 5 CONSOLE_IOV_VF_STRIDE 0 15 regRCC_DEV0_2_RCC_PEER_REG_RANGE0 0 0x2ffc0dde 2 0 5 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_2_RCC_PEER_REG_RANGE1 0 0x2ffc0ddf 2 0 5 START_ADDR 0 15 END_ADDR 16 31 regRCC_DEV0_3_RCC_BUS_CNTL 0 0x2ffc0de1 19 0 5 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 ROOT_ERR_LOG_ON_EVENT 12 12 HOST_CPL_POISONED_LOG_IN_RC 13 13 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 regRCC_DEV0_2_RCC_CONFIG_CNTL 0 0x2ffc0de2 3 0 5 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 regRCC_DEV0_2_RCC_CONFIG_F0_BASE 0 0x2ffc0de6 1 0 5 F0_BASE 0 31 regRCC_DEV0_2_RCC_CONFIG_APER_SIZE 0 0x2ffc0de7 1 0 5 APER_SIZE 0 31 regRCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE 0 0x2ffc0de8 1 0 5 REG_APER_SIZE 0 26 regRCC_DEV0_2_RCC_XDMA_LO 0 0x2ffc0de9 2 0 5 BIF_XDMA_LOWER_BOUND 0 30 BIF_XDMA_APER_EN 31 31 regRCC_DEV0_2_RCC_XDMA_HI 0 0x2ffc0dea 1 0 5 BIF_XDMA_UPPER_BOUND 0 30 regRCC_DEV0_3_RCC_FEATURES_CONTROL_MISC 0 0x2ffc0deb 12 0 5 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 regRCC_DEV0_2_RCC_BUSNUM_CNTL1 0 0x2ffc0dec 1 0 5 ID_MASK 0 7 regRCC_DEV0_2_RCC_BUSNUM_LIST0 0 0x2ffc0ded 4 0 5 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 regRCC_DEV0_2_RCC_BUSNUM_LIST1 0 0x2ffc0dee 4 0 5 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 regRCC_DEV0_2_RCC_BUSNUM_CNTL2 0 0x2ffc0def 4 0 5 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 regRCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM 0 0x2ffc0df0 1 0 5 CHECK_EN 0 0 regRCC_DEV0_2_RCC_HOST_BUSNUM 0 0x2ffc0df1 1 0 5 HOST_ID 0 15 regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI 0 0x2ffc0df2 1 0 5 PEER0_FB_OFFSET_HI 0 19 regRCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO 0 0x2ffc0df3 2 0 5 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI 0 0x2ffc0df4 1 0 5 PEER1_FB_OFFSET_HI 0 19 regRCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO 0 0x2ffc0df5 2 0 5 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI 0 0x2ffc0df6 1 0 5 PEER2_FB_OFFSET_HI 0 19 regRCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO 0 0x2ffc0df7 2 0 5 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI 0 0x2ffc0df8 1 0 5 PEER3_FB_OFFSET_HI 0 19 regRCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO 0 0x2ffc0df9 2 0 5 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST0 0 0x2ffc0dfa 4 0 5 DEVFUNC_ID0 0 7 DEVFUNC_ID1 8 15 DEVFUNC_ID2 16 23 DEVFUNC_ID3 24 31 regRCC_DEV0_2_RCC_DEVFUNCNUM_LIST1 0 0x2ffc0dfb 4 0 5 DEVFUNC_ID4 0 7 DEVFUNC_ID5 8 15 DEVFUNC_ID6 16 23 DEVFUNC_ID7 24 31 regRCC_DEV0_3_RCC_DEV0_LINK_CNTL 0 0x2ffc0dfd 2 0 5 LINK_DOWN_EXIT 0 0 LINK_DOWN_ENTRY 8 8 regRCC_DEV0_3_RCC_CMN_LINK_CNTL 0 0x2ffc0dfe 5 0 5 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 regRCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE 0 0x2ffc0dff 2 0 5 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 regRCC_DEV0_3_RCC_LTR_LSWITCH_CNTL 0 0x2ffc0e00 1 0 5 LSWITCH_LATENCY_VALUE 0 9 regRCC_DEV0_3_RCC_MH_ARB_CNTL 0 0x2ffc0e01 2 0 5 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 regBIF_BX2_CC_BIF_BX_STRAP0 0 0x2ffc0e02 1 0 5 STRAP_RESERVED 25 31 regBIF_BX2_CC_BIF_BX_PINSTRAP0 0 0x2ffc0e04 0 0 5 regBIF_BX2_BIF_MM_INDACCESS_CNTL 0 0x2ffc0e06 1 0 5 MM_INDACCESS_DIS 1 1 regBIF_BX2_BUS_CNTL 0 0x2ffc0e07 15 0 5 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 HDP_FB_FLUSH_STALL_DOORBELL_DIS 24 24 PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS 25 25 PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS 26 26 MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS 27 27 HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS 28 28 HDP_REG_FLUSH_VF_MASK_EN 29 29 VGAFB_ZERO_BE_WR_EN 30 30 VGAFB_ZERO_BE_RD_EN 31 31 regBIF_BX2_BIF_SCRATCH0 0 0x2ffc0e08 1 0 5 BIF_SCRATCH0 0 31 regBIF_BX2_BIF_SCRATCH1 0 0x2ffc0e09 1 0 5 BIF_SCRATCH1 0 31 regBIF_BX2_BX_RESET_EN 0 0x2ffc0e0d 1 0 5 RESET_ON_VFENABLE_LOW_EN 16 16 regBIF_BX2_MM_CFGREGS_CNTL 0 0x2ffc0e0e 3 0 5 MM_CFG_FUNC_SEL 0 2 MM_CFG_DEV_SEL 6 7 MM_WR_TO_CFG_EN 31 31 regBIF_BX2_BX_RESET_CNTL 0 0x2ffc0e10 1 0 5 LINK_TRAIN_EN 0 0 regBIF_BX2_INTERRUPT_CNTL 0 0x2ffc0e11 8 0 5 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 BIF_RB_REQ_NONSNOOP_EN 15 15 DUMMYRD_BYPASS_IN_MSI_EN 16 16 ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS 17 17 BIF_RB_REQ_RELAX_ORDER_EN 18 18 regBIF_BX2_INTERRUPT_CNTL2 0 0x2ffc0e12 1 0 5 IH_DUMMY_RD_ADDR 0 31 regBIF_BX2_CLKREQB_PAD_CNTL 0 0x2ffc0e18 13 0 5 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_Y 13 13 regBIF_BX2_BIF_FEATURES_CONTROL_MISC 0 0x2ffc0e1b 10 0 5 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 BIF_RB_MSI_VEC_NOT_ENABLED_MODE 11 11 BIF_RB_SET_OVERFLOW_EN 12 12 ATOMIC_ERR_INT_DIS 13 13 BME_HDL_NONVIR_EN 15 15 HDP_NP_OSTD_LIMIT 16 23 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR 24 24 regBIF_BX2_BIF_DOORBELL_CNTL 0 0x2ffc0e1c 9 0 5 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 DOORBELL_MONITOR_EN 4 4 DB_MNTR_INTGEN_DIS 24 24 DB_MNTR_INTGEN_MODE_0 25 25 DB_MNTR_INTGEN_MODE_1 26 26 DB_MNTR_INTGEN_MODE_2 27 27 regBIF_BX2_BIF_DOORBELL_INT_CNTL 0 0x2ffc0e1d 12 0 5 DOORBELL_INTERRUPT_STATUS 0 0 RAS_CNTLR_INTERRUPT_STATUS 1 1 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS 2 2 DOORBELL_INTERRUPT_CLEAR 16 16 RAS_CNTLR_INTERRUPT_CLEAR 17 17 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR 18 18 DOORBELL_INTERRUPT_DISABLE 24 24 RAS_CNTLR_INTERRUPT_DISABLE 25 25 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE 26 26 SET_DB_INTR_STATUS_WHEN_RB_ENABLE 28 28 SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE 29 29 SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE 30 30 regBIF_BX2_BIF_FB_EN 0 0x2ffc0e1f 2 0 5 FB_READ_EN 0 0 FB_WRITE_EN 1 1 regBIF_BX2_BIF_INTR_CNTL 0 0x2ffc0e20 1 0 5 RAS_INTR_VEC_SEL 0 0 regBIF_BX2_BIF_MST_TRANS_PENDING_VF 0 0x2ffc0e29 1 0 5 BIF_MST_TRANS_PENDING 0 30 regBIF_BX2_BIF_SLV_TRANS_PENDING_VF 0 0x2ffc0e2a 1 0 5 BIF_SLV_TRANS_PENDING 0 30 regBIF_BX2_BACO_CNTL 0 0x2ffc0e2b 9 0 5 BACO_EN 0 0 BACO_BIF_LCLK_SWITCH 1 1 BACO_DUMMY_EN 2 2 BACO_POWER_OFF 3 3 BACO_DSTATE_BYPASS 5 5 BACO_RST_INTR_MASK 6 6 BACO_MODE 8 8 RCU_BIF_CONFIG_DONE 9 9 BACO_AUTO_EXIT 31 31 regBIF_BX2_BIF_BACO_EXIT_TIME0 0 0x2ffc0e2c 1 0 5 BACO_EXIT_PXEN_CLR_TIMER 0 19 regBIF_BX2_BIF_BACO_EXIT_TIMER1 0 0x2ffc0e2d 7 0 5 BACO_EXIT_SIDEBAND_TIMER 0 19 BACO_HW_AUTO_FLUSH_EN 24 24 BACO_HW_EXIT_DIS 26 26 PX_EN_OE_IN_PX_EN_HIGH 27 27 PX_EN_OE_IN_PX_EN_LOW 28 28 BACO_MODE_SEL 29 30 AUTO_BACO_EXIT_CLR_BY_HW_DIS 31 31 regBIF_BX2_BIF_BACO_EXIT_TIMER2 0 0x2ffc0e2e 1 0 5 BACO_EXIT_LCLK_BAK_TIMER 0 19 regBIF_BX2_BIF_BACO_EXIT_TIMER3 0 0x2ffc0e2f 1 0 5 BACO_EXIT_DUMMY_EN_CLR_TIMER 0 19 regBIF_BX2_BIF_BACO_EXIT_TIMER4 0 0x2ffc0e30 1 0 5 BACO_EXIT_BACO_EN_CLR_TIMER 0 19 regBIF_BX2_MEM_TYPE_CNTL 0 0x2ffc0e31 1 0 5 BF_MEM_PHY_G5_G3 0 0 regBIF_BX2_NBIF_GFX_ADDR_LUT_CNTL 0 0x2ffc0e33 3 0 5 LUT_ENABLE 0 0 MSI_ADDR_MODE 1 1 LUT_BC_MODE 8 8 regBIF_BX2_NBIF_GFX_ADDR_LUT_0 0 0x2ffc0e34 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_1 0 0x2ffc0e35 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_2 0 0x2ffc0e36 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_3 0 0x2ffc0e37 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_4 0 0x2ffc0e38 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_5 0 0x2ffc0e39 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_6 0 0x2ffc0e3a 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_7 0 0x2ffc0e3b 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_8 0 0x2ffc0e3c 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_9 0 0x2ffc0e3d 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_10 0 0x2ffc0e3e 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_11 0 0x2ffc0e3f 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_12 0 0x2ffc0e40 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_13 0 0x2ffc0e41 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_14 0 0x2ffc0e42 1 0 5 ADDR 0 23 regBIF_BX2_NBIF_GFX_ADDR_LUT_15 0 0x2ffc0e43 1 0 5 ADDR 0 23 regBIF_BX2_VF_REGWR_EN 0 0x2ffc0e44 31 0 5 VF_REGWR_EN_VF0 0 0 VF_REGWR_EN_VF1 1 1 VF_REGWR_EN_VF2 2 2 VF_REGWR_EN_VF3 3 3 VF_REGWR_EN_VF4 4 4 VF_REGWR_EN_VF5 5 5 VF_REGWR_EN_VF6 6 6 VF_REGWR_EN_VF7 7 7 VF_REGWR_EN_VF8 8 8 VF_REGWR_EN_VF9 9 9 VF_REGWR_EN_VF10 10 10 VF_REGWR_EN_VF11 11 11 VF_REGWR_EN_VF12 12 12 VF_REGWR_EN_VF13 13 13 VF_REGWR_EN_VF14 14 14 VF_REGWR_EN_VF15 15 15 VF_REGWR_EN_VF16 16 16 VF_REGWR_EN_VF17 17 17 VF_REGWR_EN_VF18 18 18 VF_REGWR_EN_VF19 19 19 VF_REGWR_EN_VF20 20 20 VF_REGWR_EN_VF21 21 21 VF_REGWR_EN_VF22 22 22 VF_REGWR_EN_VF23 23 23 VF_REGWR_EN_VF24 24 24 VF_REGWR_EN_VF25 25 25 VF_REGWR_EN_VF26 26 26 VF_REGWR_EN_VF27 27 27 VF_REGWR_EN_VF28 28 28 VF_REGWR_EN_VF29 29 29 VF_REGWR_EN_VF30 30 30 regBIF_BX2_VF_DOORBELL_EN 0 0x2ffc0e45 32 0 5 VF_DOORBELL_EN_VF0 0 0 VF_DOORBELL_EN_VF1 1 1 VF_DOORBELL_EN_VF2 2 2 VF_DOORBELL_EN_VF3 3 3 VF_DOORBELL_EN_VF4 4 4 VF_DOORBELL_EN_VF5 5 5 VF_DOORBELL_EN_VF6 6 6 VF_DOORBELL_EN_VF7 7 7 VF_DOORBELL_EN_VF8 8 8 VF_DOORBELL_EN_VF9 9 9 VF_DOORBELL_EN_VF10 10 10 VF_DOORBELL_EN_VF11 11 11 VF_DOORBELL_EN_VF12 12 12 VF_DOORBELL_EN_VF13 13 13 VF_DOORBELL_EN_VF14 14 14 VF_DOORBELL_EN_VF15 15 15 VF_DOORBELL_EN_VF16 16 16 VF_DOORBELL_EN_VF17 17 17 VF_DOORBELL_EN_VF18 18 18 VF_DOORBELL_EN_VF19 19 19 VF_DOORBELL_EN_VF20 20 20 VF_DOORBELL_EN_VF21 21 21 VF_DOORBELL_EN_VF22 22 22 VF_DOORBELL_EN_VF23 23 23 VF_DOORBELL_EN_VF24 24 24 VF_DOORBELL_EN_VF25 25 25 VF_DOORBELL_EN_VF26 26 26 VF_DOORBELL_EN_VF27 27 27 VF_DOORBELL_EN_VF28 28 28 VF_DOORBELL_EN_VF29 29 29 VF_DOORBELL_EN_VF30 30 30 VF_DOORBELL_RD_LOG_DIS 31 31 regBIF_BX2_VF_FB_EN 0 0x2ffc0e46 31 0 5 VF_FB_EN_VF0 0 0 VF_FB_EN_VF1 1 1 VF_FB_EN_VF2 2 2 VF_FB_EN_VF3 3 3 VF_FB_EN_VF4 4 4 VF_FB_EN_VF5 5 5 VF_FB_EN_VF6 6 6 VF_FB_EN_VF7 7 7 VF_FB_EN_VF8 8 8 VF_FB_EN_VF9 9 9 VF_FB_EN_VF10 10 10 VF_FB_EN_VF11 11 11 VF_FB_EN_VF12 12 12 VF_FB_EN_VF13 13 13 VF_FB_EN_VF14 14 14 VF_FB_EN_VF15 15 15 VF_FB_EN_VF16 16 16 VF_FB_EN_VF17 17 17 VF_FB_EN_VF18 18 18 VF_FB_EN_VF19 19 19 VF_FB_EN_VF20 20 20 VF_FB_EN_VF21 21 21 VF_FB_EN_VF22 22 22 VF_FB_EN_VF23 23 23 VF_FB_EN_VF24 24 24 VF_FB_EN_VF25 25 25 VF_FB_EN_VF26 26 26 VF_FB_EN_VF27 27 27 VF_FB_EN_VF28 28 28 VF_FB_EN_VF29 29 29 VF_FB_EN_VF30 30 30 regBIF_BX2_VF_REGWR_STATUS 0 0x2ffc0e47 31 0 5 VF_REGWR_STATUS_VF0 0 0 VF_REGWR_STATUS_VF1 1 1 VF_REGWR_STATUS_VF2 2 2 VF_REGWR_STATUS_VF3 3 3 VF_REGWR_STATUS_VF4 4 4 VF_REGWR_STATUS_VF5 5 5 VF_REGWR_STATUS_VF6 6 6 VF_REGWR_STATUS_VF7 7 7 VF_REGWR_STATUS_VF8 8 8 VF_REGWR_STATUS_VF9 9 9 VF_REGWR_STATUS_VF10 10 10 VF_REGWR_STATUS_VF11 11 11 VF_REGWR_STATUS_VF12 12 12 VF_REGWR_STATUS_VF13 13 13 VF_REGWR_STATUS_VF14 14 14 VF_REGWR_STATUS_VF15 15 15 VF_REGWR_STATUS_VF16 16 16 VF_REGWR_STATUS_VF17 17 17 VF_REGWR_STATUS_VF18 18 18 VF_REGWR_STATUS_VF19 19 19 VF_REGWR_STATUS_VF20 20 20 VF_REGWR_STATUS_VF21 21 21 VF_REGWR_STATUS_VF22 22 22 VF_REGWR_STATUS_VF23 23 23 VF_REGWR_STATUS_VF24 24 24 VF_REGWR_STATUS_VF25 25 25 VF_REGWR_STATUS_VF26 26 26 VF_REGWR_STATUS_VF27 27 27 VF_REGWR_STATUS_VF28 28 28 VF_REGWR_STATUS_VF29 29 29 VF_REGWR_STATUS_VF30 30 30 regBIF_BX2_VF_DOORBELL_STATUS 0 0x2ffc0e48 31 0 5 VF_DOORBELL_STATUS_VF0 0 0 VF_DOORBELL_STATUS_VF1 1 1 VF_DOORBELL_STATUS_VF2 2 2 VF_DOORBELL_STATUS_VF3 3 3 VF_DOORBELL_STATUS_VF4 4 4 VF_DOORBELL_STATUS_VF5 5 5 VF_DOORBELL_STATUS_VF6 6 6 VF_DOORBELL_STATUS_VF7 7 7 VF_DOORBELL_STATUS_VF8 8 8 VF_DOORBELL_STATUS_VF9 9 9 VF_DOORBELL_STATUS_VF10 10 10 VF_DOORBELL_STATUS_VF11 11 11 VF_DOORBELL_STATUS_VF12 12 12 VF_DOORBELL_STATUS_VF13 13 13 VF_DOORBELL_STATUS_VF14 14 14 VF_DOORBELL_STATUS_VF15 15 15 VF_DOORBELL_STATUS_VF16 16 16 VF_DOORBELL_STATUS_VF17 17 17 VF_DOORBELL_STATUS_VF18 18 18 VF_DOORBELL_STATUS_VF19 19 19 VF_DOORBELL_STATUS_VF20 20 20 VF_DOORBELL_STATUS_VF21 21 21 VF_DOORBELL_STATUS_VF22 22 22 VF_DOORBELL_STATUS_VF23 23 23 VF_DOORBELL_STATUS_VF24 24 24 VF_DOORBELL_STATUS_VF25 25 25 VF_DOORBELL_STATUS_VF26 26 26 VF_DOORBELL_STATUS_VF27 27 27 VF_DOORBELL_STATUS_VF28 28 28 VF_DOORBELL_STATUS_VF29 29 29 VF_DOORBELL_STATUS_VF30 30 30 regBIF_BX2_VF_FB_STATUS 0 0x2ffc0e49 31 0 5 VF_FB_STATUS_VF0 0 0 VF_FB_STATUS_VF1 1 1 VF_FB_STATUS_VF2 2 2 VF_FB_STATUS_VF3 3 3 VF_FB_STATUS_VF4 4 4 VF_FB_STATUS_VF5 5 5 VF_FB_STATUS_VF6 6 6 VF_FB_STATUS_VF7 7 7 VF_FB_STATUS_VF8 8 8 VF_FB_STATUS_VF9 9 9 VF_FB_STATUS_VF10 10 10 VF_FB_STATUS_VF11 11 11 VF_FB_STATUS_VF12 12 12 VF_FB_STATUS_VF13 13 13 VF_FB_STATUS_VF14 14 14 VF_FB_STATUS_VF15 15 15 VF_FB_STATUS_VF16 16 16 VF_FB_STATUS_VF17 17 17 VF_FB_STATUS_VF18 18 18 VF_FB_STATUS_VF19 19 19 VF_FB_STATUS_VF20 20 20 VF_FB_STATUS_VF21 21 21 VF_FB_STATUS_VF22 22 22 VF_FB_STATUS_VF23 23 23 VF_FB_STATUS_VF24 24 24 VF_FB_STATUS_VF25 25 25 VF_FB_STATUS_VF26 26 26 VF_FB_STATUS_VF27 27 27 VF_FB_STATUS_VF28 28 28 VF_FB_STATUS_VF29 29 29 VF_FB_STATUS_VF30 30 30 regBIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL 0 0x2ffc0e4d 1 0 5 ADDRESS 2 18 regBIF_BX2_REMAP_HDP_REG_FLUSH_CNTL 0 0x2ffc0e4e 1 0 5 ADDRESS 2 18 regBIF_BX2_BIF_RB_CNTL 0 0x2ffc0e4f 9 0 5 RB_ENABLE 0 0 RB_SIZE 1 5 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 BIF_RB_TRAN 17 17 RB_INTR_FIX_PRIORITY 26 28 RB_INTR_ARB_MODE 29 29 RB_RST_BY_FLR_DISABLE 30 30 WPTR_OVERFLOW_CLEAR 31 31 regBIF_BX2_BIF_RB_BASE 0 0x2ffc0e50 1 0 5 ADDR 0 31 regBIF_BX2_BIF_RB_RPTR 0 0x2ffc0e51 1 0 5 OFFSET 2 17 regBIF_BX2_BIF_RB_WPTR 0 0x2ffc0e52 2 0 5 BIF_RB_OVERFLOW 0 0 OFFSET 2 17 regBIF_BX2_BIF_RB_WPTR_ADDR_HI 0 0x2ffc0e53 1 0 5 ADDR 0 7 regBIF_BX2_BIF_RB_WPTR_ADDR_LO 0 0x2ffc0e54 1 0 5 ADDR 2 31 regBIF_BX2_MAILBOX_INDEX 0 0x2ffc0e55 1 0 5 MAILBOX_INDEX 0 4 regBIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE 0 0x2ffc0e63 1 0 5 VCN0_GPUIOV_CFG_SIZE 0 3 regBIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE 0 0x2ffc0e64 1 0 5 VCN1_GPUIOV_CFG_SIZE 0 3 regBIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE 0 0x2ffc0e65 1 0 5 GFX_SDMA_GPUIOV_CFG_SIZE 0 3 regBIF_BX2_BIF_PERSTB_PAD_CNTL 0 0x2ffc0e68 1 0 5 PERSTB_PAD_CNTL 0 15 regBIF_BX2_BIF_PX_EN_PAD_CNTL 0 0x2ffc0e69 1 0 5 PX_EN_PAD_CNTL 0 7 regBIF_BX2_BIF_REFPADKIN_PAD_CNTL 0 0x2ffc0e6a 1 0 5 REFPADKIN_PAD_CNTL 0 7 regBIF_BX2_BIF_CLKREQB_PAD_CNTL 0 0x2ffc0e6b 1 0 5 CLKREQB_PAD_CNTL 0 23 regBIF_BX2_BIF_PWRBRK_PAD_CNTL 0 0x2ffc0e6c 1 0 5 PWRBRK_PAD_CNTL 0 7 regBIF_BX2_BIF_WAKEB_PAD_CNTL 0 0x2ffc0e6d 8 0 5 GPIO33_ITXIMPSEL 0 0 GPIO33_ICTFEN 1 1 GPIO33_IPD 2 2 GPIO33_IPU 3 3 GPIO33_IRXEN 4 4 GPIO33_IRXSEL0 5 5 GPIO33_IRXSEL1 6 6 GPIO33_RESERVED 7 7 regBIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL 0 0x2ffc0e6e 6 0 5 GPIO_IPD 0 0 GPIO_IPU 1 1 GPIO_IRXEN 2 2 GPIO_IRXSEL0 3 3 GPIO_IRXSEL1 4 4 GPIO_ITXIMPSEL 5 5 regBIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL 0 0x2ffc0e70 2 0 5 PCIE_PAR_SAVE_VALID 0 0 PCIE_PAR_SAVE_SCRATCH 1 31 regBIF_BX2_BIF_S5_MEM_POWER_CTRL0 0 0x2ffc0e71 1 0 5 MEM_POWER_CTRL_S5_31_0 0 31 regBIF_BX2_BIF_S5_MEM_POWER_CTRL1 0 0x2ffc0e72 2 0 5 MEM_POWER_CTRL_S5_41_32 0 9 MEM_POWER_CTRL_SEL 10 10 regBIF_BX2_BIF_S5_DUMMY_REGS 0 0x2ffc0e73 1 0 5 BIF_S5_DUMMY_REGS 0 31 regBIF_BX_PF2_BIF_BME_STATUS 0 0x2ffc0e0b 2 0 5 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 regBIF_BX_PF2_BIF_ATOMIC_ERR_LOG 0 0x2ffc0e0c 8 0 5 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0x2ffc0e13 1 0 5 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0x2ffc0e14 1 0 5 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 regBIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL 0 0x2ffc0e15 3 0 5 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 regBIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL 0 0x2ffc0e16 1 0 5 HDP_REG_FLUSH_ADDR 0 0 regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0x2ffc0e17 1 0 5 HDP_MEM_FLUSH_ADDR 0 0 regBIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0 0x2ffc0e19 1 0 5 HDP_MEM_FLUSH_ONLY_ADDR 0 0 regBIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0 0x2ffc0e1a 1 0 5 HDP_MEM_INVALIDATE_ONLY_ADDR 0 0 regBIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ 0 0x2ffc0e24 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ 0 0x2ffc0e25 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF2_GPU_HDP_FLUSH_REQ 0 0x2ffc0e26 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF2_GPU_HDP_FLUSH_DONE 0 0x2ffc0e27 32 0 5 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 RSVD_ENG0 12 12 RSVD_ENG1 13 13 RSVD_ENG2 14 14 RSVD_ENG3 15 15 RSVD_ENG4 16 16 RSVD_ENG5 17 17 RSVD_ENG6 18 18 RSVD_ENG7 19 19 RSVD_ENG8 20 20 RSVD_ENG9 21 21 RSVD_ENG10 22 22 RSVD_ENG11 23 23 RSVD_ENG12 24 24 RSVD_ENG13 25 25 RSVD_ENG14 26 26 RSVD_ENG15 27 27 RSVD_ENG16 28 28 RSVD_ENG17 29 29 RSVD_ENG18 30 30 RSVD_ENG19 31 31 regBIF_BX_PF2_BIF_TRANS_PENDING 0 0x2ffc0e28 2 0 5 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 regBIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS 0 0x2ffc0e32 1 0 5 LUT_BYPASS 0 0 regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0 0 0x2ffc0e56 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1 0 0x2ffc0e57 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2 0 0x2ffc0e58 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3 0 0x2ffc0e59 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0 0 0x2ffc0e5a 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1 0 0x2ffc0e5b 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2 0 0x2ffc0e5c 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3 0 0x2ffc0e5d 1 0 5 MSGBUF_DATA 0 31 regBIF_BX_PF2_MAILBOX_CONTROL 0 0x2ffc0e5e 4 0 5 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 regBIF_BX_PF2_MAILBOX_INT_CNTL 0 0x2ffc0e5f 2 0 5 VALID_INT_EN 0 0 ACK_INT_EN 1 1 regBIF_BX_PF2_BIF_VMHV_MAILBOX 0 0x2ffc0e60 8 0 5 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 regGDC1_NGDC_SDP_PORT_CTRL 0 0x2ffc0ee2 3 0 5 SDP_DISCON_HYSTERESIS 0 7 NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN 15 15 SDP_DISCON_HYSTERESIS_H 16 19 regGDC1_SHUB_REGS_IF_CTL 0 0x2ffc0ee3 1 0 5 SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS 0 0 regGDC1_NGDC_MP4SDP_CTRL 0 0x2ffc0ee4 6 0 5 MP4SDP_BLKLVL_VC0_OVERRIDE_EN 0 0 MP4SDP_BLKLVL_VC0_OVERRIDE_VAL 1 2 MP4SDP_BLKLVL_VC1_OVERRIDE_EN 4 4 MP4SDP_BLKLVL_VC1_OVERRIDE_VAL 5 6 MP4SDP_BLKLVL_VC4_OVERRIDE_EN 8 8 MP4SDP_BLKLVL_VC4_OVERRIDE_VAL 9 10 regGDC1_NGDC_MGCG_CTRL 0 0x2ffc0eea 7 0 5 NGDC_MGCG_EN 0 0 NGDC_MGCG_MODE 1 1 NGDC_MGCG_HYSTERESIS 2 9 NGDC_MGCG_HST_DIS 10 10 NGDC_MGCG_DMA_DIS 11 11 NGDC_MGCG_REG_DIS 12 12 NGDC_MGCG_AER_DIS 13 13 regGDC1_NGDC_RESERVED_0 0 0x2ffc0eeb 1 0 5 RESERVED 0 31 regGDC1_NGDC_RESERVED_1 0 0x2ffc0eec 1 0 5 RESERVED 0 31 regGDC1_NGDC_SDP_PORT_CTRL_SOCCLK 0 0x2ffc0eed 6 0 5 SDP_DISCON_HYSTERESIS_SOCCLK 0 7 ATDMA_RDRSP_POOL_NUM_SOCCLK 8 15 ATDMA_RDRSP_CRDT_VC0_RSV 16 19 ATDMA_RDRSP_CRDT_VC5_RSV 20 23 ATDMA_RDRSP_CRDT_VC6_RSV 24 27 SDP_DISCON_HYSTERESIS_SOCCLK_H 28 31 regGDC1_NGDC_SDP_PORT_CTRL1_SOCCLK 0 0x2ffc0eee 6 0 5 ATDMA_REQ_CRDT_VC0_RSV 0 3 ATDMA_REQ_CRDT_VC1_RSV 4 7 ATDMA_REQ_CRDT_VC5_RSV 8 11 ATDMA_REQ_CRDT_VC6_RSV 12 15 ATDMA_ORIGDATA_CRDT_VC0_RSV 16 19 ATDMA_ORIGDATA_CRDT_VC1_RSV 20 23 regGDC1_NBIF_GFX_DOORBELL_STATUS 0 0x2ffc0eef 1 0 5 NBIF_GFX_DOORBELL_SENT 0 0 regGDC1_BIF_SDMA0_DOORBELL_RANGE 0 0x2ffc0ef0 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_SDMA1_DOORBELL_RANGE 0 0x2ffc0ef1 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_IH_DOORBELL_RANGE 0 0x2ffc0ef2 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_VCN0_DOORBELL_RANGE 0 0x2ffc0ef3 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_RLC_DOORBELL_RANGE 0 0x2ffc0ef5 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_SDMA2_DOORBELL_RANGE 0 0x2ffc0ef6 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_SDMA3_DOORBELL_RANGE 0 0x2ffc0ef7 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_VCN1_DOORBELL_RANGE 0 0x2ffc0ef8 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_SDMA4_DOORBELL_RANGE 0 0x2ffc0ef9 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_BIF_SDMA5_DOORBELL_RANGE 0 0x2ffc0efa 2 0 5 OFFSET 2 11 SIZE 16 20 regGDC1_ATDMA_MISC_CNTL 0 0x2ffc0efd 6 0 5 WRR_ARB_MODE 0 0 INSERT_RD_ON_2ND_WDAT_EN 1 1 RDRSP_ARB_MODE 2 3 WRR_VC6_WEIGHT 8 15 WRR_VC0_WEIGHT 16 23 WRR_VC1_WEIGHT 24 31 regGDC1_BIF_DOORBELL_FENCE_CNTL 0 0x2ffc0efe 9 0 5 DOORBELL_FENCE_CP_ENABLE 0 0 DOORBELL_FENCE_SDMA0_ENABLE 1 1 DOORBELL_FENCE_SDMA1_ENABLE 2 2 DOORBELL_FENCE_RLC_ENABLE 4 4 DOORBELL_FENCE_SDMA2_ENABLE 5 5 DOORBELL_FENCE_SDMA3_ENABLE 6 6 DOORBELL_FENCE_SDMA4_ENABLE 7 7 DOORBELL_FENCE_SDMA5_ENABLE 8 8 DOORBELL_FENCE_ONCE_TRIGGER_DIS 16 16 regGDC1_S2A_MISC_CNTL 0 0x2ffc0eff 12 0 5 DOORBELL_64BIT_SUPPORT_SDMA0_DIS 0 0 DOORBELL_64BIT_SUPPORT_SDMA1_DIS 1 1 DOORBELL_64BIT_SUPPORT_CP_DIS 2 2 DOORBELL_64BIT_SUPPORT_RLC_DIS 5 5 ATM_ARB_MODE 8 9 RB_ARB_MODE 10 11 HSTR_ARB_MODE 12 13 WRSP_ARB_MODE 16 19 DOORBELL_64BIT_SUPPORT_SDMA2_DIS 24 24 DOORBELL_64BIT_SUPPORT_SDMA3_DIS 25 25 DOORBELL_64BIT_SUPPORT_SDMA4_DIS 26 26 DOORBELL_64BIT_SUPPORT_SDMA5_DIS 27 27 regGDC1_NGDC_EARLY_WAKEUP_CTRL 0 0x2ffc0f01 3 0 5 NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE 0 0 NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT 1 1 NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE 2 2 regGDC1_NGDC_PG_MISC_CTRL 0 0x2ffc0f18 6 0 5 NGDC_PG_ENDP_D3_ONLY 10 10 NGDC_PG_CLK_PERM1 13 13 NGDC_PG_DS_ALLOW_DIS 14 14 NGDC_PG_CLK_PERM2 16 16 NGDC_CFG_REFCLK_CYCLE_FOR_200NS 24 29 NGDC_CFG_PG_EXIT_OVERRIDE 31 31 regGDC1_NGDC_PGMST_CTRL 0 0x2ffc0f19 4 0 5 NGDC_CFG_PG_HYSTERESIS 0 7 NGDC_CFG_PG_EN 8 8 NGDC_CFG_IDLENESS_COUNT_EN 10 13 NGDC_CFG_FW_PG_EXIT_EN 14 15 regGDC1_NGDC_PGSLV_CTRL 0 0x2ffc0f1a 5 0 5 NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS 0 4 NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS 5 9 NGDC_CFG_GDCCLK_IDLE_HYSTERESIS 10 14 NGDC_CFG_SHUBCLK_2_IDLE_HYSTERESIS 15 19 NGDC_CFG_SHUBCLK_3_IDLE_HYSTERESIS 20 24 regGDC1_SHUBCLK_DPM_CTRL 0 0x2ffc0f1b 5 0 5 SHUBCLK_DPM_MODE 0 0 SHUBCLK_DPM_ENABLE 1 1 SHUBCLK_DPM_DMAWR_QUANT 2 9 SHUBCLK_DPM_DMARD_QUANT 10 17 SHUBCLK_DPM_CLEAR 18 18 regGDC1_SHUBCLK_DPM_WR_WEIGHT 0 0x2ffc0f1c 5 0 5 SHUBCLK_DPM_WR_WEIGHT_4B 0 4 SHUBCLK_DPM_WR_WEIGHT_8B 5 9 SHUBCLK_DPM_WR_WEIGHT_16B 10 14 SHUBCLK_DPM_WR_WEIGHT_32B 15 19 SHUBCLK_DPM_WR_WEIGHT_64B 20 24 regGDC1_SHUBCLK_DPM_RD_WEIGHT 0 0x2ffc0f1d 5 0 5 SHUBCLK_DPM_RD_WEIGHT_4B 0 4 SHUBCLK_DPM_RD_WEIGHT_8B 5 9 SHUBCLK_DPM_RD_WEIGHT_16B 10 14 SHUBCLK_DPM_RD_WEIGHT_32B 15 19 SHUBCLK_DPM_RD_WEIGHT_64B 20 24 regGDC1_SHUBCLK_DPM_WR_CNT 0 0x2ffc0f1e 1 0 5 SHUBCLK_DPM_WR_COUNTER 0 31 regGDC1_SHUBCLK_DPM_RD_CNT 0 0x2ffc0f1f 1 0 5 SHUBCLK_DPM_RD_COUNTER 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO 0 0x2ffd0800 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1 0 0x2ffd0800 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2 0 0x2ffd0800 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI 0 0x2ffd0801 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1 0 0x2ffd0801 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2 0 0x2ffd0801 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA 0 0x2ffd0802 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1 0 0x2ffd0802 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2 0 0x2ffd0802 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL 0 0x2ffd0803 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1 0 0x2ffd0803 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2 0 0x2ffd0803 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO 0 0x2ffd0804 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1 0 0x2ffd0804 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2 0 0x2ffd0804 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI 0 0x2ffd0805 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1 0 0x2ffd0805 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2 0 0x2ffd0805 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA 0 0x2ffd0806 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1 0 0x2ffd0806 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2 0 0x2ffd0806 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL 0 0x2ffd0807 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1 0 0x2ffd0807 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2 0 0x2ffd0807 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO 0 0x2ffd0808 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1 0 0x2ffd0808 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2 0 0x2ffd0808 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI 0 0x2ffd0809 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1 0 0x2ffd0809 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2 0 0x2ffd0809 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA 0 0x2ffd080a 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1 0 0x2ffd080a 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2 0 0x2ffd080a 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL 0 0x2ffd080b 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1 0 0x2ffd080b 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2 0 0x2ffd080b 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO 0 0x2ffd080c 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1 0 0x2ffd080c 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2 0 0x2ffd080c 1 0 5 MSG_ADDR_LO 2 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI 0 0x2ffd080d 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1 0 0x2ffd080d 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2 0 0x2ffd080d 1 0 5 MSG_ADDR_HI 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA 0 0x2ffd080e 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1 0 0x2ffd080e 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2 0 0x2ffd080e 1 0 5 MSG_DATA 0 31 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL 0 0x2ffd080f 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1 0 0x2ffd080f 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2 0 0x2ffd080f 1 0 5 MASK_BIT 0 0 regRCC_DEV0_EPF0_1_GFXMSIX_PBA 0 0x2ffd0c00 4 0 5 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regRCC_DEV0_EPF0_1_GFXMSIX_PBA_1 0 0x2ffd0c00 4 0 5 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regRCC_DEV0_EPF0_1_GFXMSIX_PBA_2 0 0x2ffd0c00 4 0 5 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 MSIX_PENDING_BITS_3 3 3 regBIFPLR0_1_VENDOR_ID 0 0x3fff7bfc2400 1 0 5 VENDOR_ID 0 15 regBIFPLR0_1_DEVICE_ID 0 0x3fff7bfc2400 1 0 5 DEVICE_ID 0 15 regBIFPLR0_1_COMMAND 0 0x3fff7bfc2401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR0_1_STATUS 0 0x3fff7bfc2401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR0_1_REVISION_ID 0 0x3fff7bfc2402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR0_1_PROG_INTERFACE 0 0x3fff7bfc2402 1 0 5 PROG_INTERFACE 0 7 regBIFPLR0_1_SUB_CLASS 0 0x3fff7bfc2402 1 0 5 SUB_CLASS 0 7 regBIFPLR0_1_BASE_CLASS 0 0x3fff7bfc2402 1 0 5 BASE_CLASS 0 7 regBIFPLR0_1_CACHE_LINE 0 0x3fff7bfc2403 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR0_1_LATENCY 0 0x3fff7bfc2403 1 0 5 LATENCY_TIMER 0 7 regBIFPLR0_1_HEADER 0 0x3fff7bfc2403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR0_1_BIST 0 0x3fff7bfc2403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR0_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc2406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR0_1_IO_BASE_LIMIT 0 0x3fff7bfc2407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR0_1_SECONDARY_STATUS 0 0x3fff7bfc2407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR0_1_MEM_BASE_LIMIT 0 0x3fff7bfc2408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR0_1_PREF_BASE_LIMIT 0 0x3fff7bfc2409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR0_1_PREF_BASE_UPPER 0 0x3fff7bfc240a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR0_1_PREF_LIMIT_UPPER 0 0x3fff7bfc240b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR0_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc240c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR0_1_CAP_PTR 0 0x3fff7bfc240d 1 0 5 CAP_PTR 0 7 regBIFPLR0_1_ROM_BASE_ADDR 0 0x3fff7bfc240e 1 0 5 BASE_ADDR 0 31 regBIFPLR0_1_INTERRUPT_LINE 0 0x3fff7bfc240f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR0_1_INTERRUPT_PIN 0 0x3fff7bfc240f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR0_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc240f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR0_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc2410 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR0_1_VENDOR_CAP_LIST 0 0x3fff7bfc2412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR0_1_ADAPTER_ID_W 0 0x3fff7bfc2413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR0_1_PMI_CAP_LIST 0 0x3fff7bfc2414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_1_PMI_CAP 0 0x3fff7bfc2414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR0_1_PMI_STATUS_CNTL 0 0x3fff7bfc2415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR0_1_PCIE_CAP_LIST 0 0x3fff7bfc2416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_1_PCIE_CAP 0 0x3fff7bfc2416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR0_1_DEVICE_CAP 0 0x3fff7bfc2417 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR0_1_DEVICE_CNTL 0 0x3fff7bfc2418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR0_1_DEVICE_STATUS 0 0x3fff7bfc2418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR0_1_LINK_CAP 0 0x3fff7bfc2419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR0_1_LINK_CNTL 0 0x3fff7bfc241a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR0_1_LINK_STATUS 0 0x3fff7bfc241a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR0_1_SLOT_CAP 0 0x3fff7bfc241b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR0_1_SLOT_CNTL 0 0x3fff7bfc241c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR0_1_SLOT_STATUS 0 0x3fff7bfc241c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR0_1_ROOT_CNTL 0 0x3fff7bfc241d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR0_1_ROOT_CAP 0 0x3fff7bfc241d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR0_1_ROOT_STATUS 0 0x3fff7bfc241e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR0_1_DEVICE_CAP2 0 0x3fff7bfc241f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR0_1_DEVICE_CNTL2 0 0x3fff7bfc2420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR0_1_DEVICE_STATUS2 0 0x3fff7bfc2420 1 0 5 RESERVED 0 15 regBIFPLR0_1_LINK_CAP2 0 0x3fff7bfc2421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR0_1_LINK_CNTL2 0 0x3fff7bfc2422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR0_1_LINK_STATUS2 0 0x3fff7bfc2422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR0_1_SLOT_CAP2 0 0x3fff7bfc2423 1 0 5 RESERVED 0 31 regBIFPLR0_1_SLOT_CNTL2 0 0x3fff7bfc2424 1 0 5 RESERVED 0 15 regBIFPLR0_1_SLOT_STATUS2 0 0x3fff7bfc2424 1 0 5 RESERVED 0 15 regBIFPLR0_1_MSI_CAP_LIST 0 0x3fff7bfc2428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_1_MSI_MSG_CNTL 0 0x3fff7bfc2428 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR0_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc2429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR0_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc242a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR0_1_MSI_MSG_DATA 0 0x3fff7bfc242a 1 0 5 MSI_DATA 0 15 regBIFPLR0_1_MSI_MSG_DATA_64 0 0x3fff7bfc242b 1 0 5 MSI_DATA_64 0 15 regBIFPLR0_1_SSID_CAP_LIST 0 0x3fff7bfc2430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_1_SSID_CAP 0 0x3fff7bfc2431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR0_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc2432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR0_1_MSI_MAP_CAP 0 0x3fff7bfc2432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc2440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc2441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR0_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc2442 1 0 5 SCRATCH 0 31 regBIFPLR0_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc2443 1 0 5 SCRATCH 0 31 regBIFPLR0_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc2444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc2445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR0_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc2446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR0_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc2447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR0_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc2447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR0_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc2448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc2449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc244a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR0_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc244b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc244c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc244d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc2450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc2451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc2452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc2454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc2455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR0_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc2456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc2457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR0_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc2458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR0_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc2459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc245a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR0_1_PCIE_HDR_LOG0 0 0x3fff7bfc245b 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_HDR_LOG1 0 0x3fff7bfc245c 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_HDR_LOG2 0 0x3fff7bfc245d 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_HDR_LOG3 0 0x3fff7bfc245e 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc245f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR0_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc2460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR0_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc2461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR0_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc2462 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc2463 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc2464 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc2465 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc249c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_LINK_CNTL3 0 0x3fff7bfc249d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR0_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc249e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc249f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc249f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc24a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc24a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc24a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc24a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc24a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc24a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc24a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc24a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc24a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc24a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc24a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc24a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc24a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc24a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc24a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_ACS_CAP 0 0x3fff7bfc24a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR0_1_PCIE_ACS_CNTL 0 0x3fff7bfc24a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR0_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc24bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_MC_CAP 0 0x3fff7bfc24bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR0_1_PCIE_MC_CNTL 0 0x3fff7bfc24bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR0_1_PCIE_MC_ADDR0 0 0x3fff7bfc24be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR0_1_PCIE_MC_ADDR1 0 0x3fff7bfc24bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR0_1_PCIE_MC_RCV0 0 0x3fff7bfc24c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR0_1_PCIE_MC_RCV1 0 0x3fff7bfc24c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR0_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc24c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR0_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc24c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc24c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc24c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR0_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc24c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR0_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc24c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc24dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc24dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc24de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc24df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc24e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc24e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR0_1_PCIE_DPC_CNTL 0 0x3fff7bfc24e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR0_1_PCIE_DPC_STATUS 0 0x3fff7bfc24e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc24e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR0_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc24e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc24e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc24e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc24e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc24e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc24e8 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc24e9 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc24ea 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc24eb 1 0 5 TLP_HDR 0 31 regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc24ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc24ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc24ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc24f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR0_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc24f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc24f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR0_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc24f3 1 0 5 CAP_ID 0 15 regBIFPLR0_1_PCIE_ESM_STATUS 0 0x3fff7bfc24f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR0_1_PCIE_ESM_CTRL 0 0x3fff7bfc24f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR0_1_PCIE_ESM_CAP_1 0 0x3fff7bfc24f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR0_1_PCIE_ESM_CAP_2 0 0x3fff7bfc24f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR0_1_PCIE_ESM_CAP_3 0 0x3fff7bfc24f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR0_1_PCIE_ESM_CAP_4 0 0x3fff7bfc24f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR0_1_PCIE_ESM_CAP_5 0 0x3fff7bfc24f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR0_1_PCIE_ESM_CAP_6 0 0x3fff7bfc24fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR0_1_PCIE_ESM_CAP_7 0 0x3fff7bfc24fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR0_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc2500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc2501 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR0_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc2502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc2504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_LINK_CAP_16GT 0 0x3fff7bfc2505 1 0 5 RESERVED 0 31 regBIFPLR0_1_LINK_CNTL_16GT 0 0x3fff7bfc2506 1 0 5 RESERVED 0 31 regBIFPLR0_1_LINK_STATUS_16GT 0 0x3fff7bfc2507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc250a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc250f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc2510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_MARGINING_PORT_CAP 0 0x3fff7bfc2511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR0_1_MARGINING_PORT_STATUS 0 0x3fff7bfc2511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR0_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc2512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc2512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc2513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc2513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc2514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc2514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc2515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc2515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc2516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc2516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc2517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc2517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc2518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc2518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc2519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc2519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc251a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc251a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc251b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc251b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc251c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc251c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc251d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc251d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc251e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc251e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc251f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc251f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc2520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc2520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc2521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR0_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc2521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR0_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc2522 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR0_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc2523 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR0_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc2524 1 0 5 CAP_ID 0 15 regBIFPLR0_1_PCIE_CCIX_CAP 0 0x3fff7bfc2524 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc2525 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc2526 1 0 5 RESERVED 0 31 regBIFPLR0_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc2527 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR0_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc2528 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2529 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2529 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2529 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2529 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc252c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc252f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2530 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2530 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2530 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2530 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR0_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc2531 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR0_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc2532 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR1_1_VENDOR_ID 0 0x3fff7bfc2800 1 0 5 VENDOR_ID 0 15 regBIFPLR1_1_DEVICE_ID 0 0x3fff7bfc2800 1 0 5 DEVICE_ID 0 15 regBIFPLR1_1_COMMAND 0 0x3fff7bfc2801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR1_1_STATUS 0 0x3fff7bfc2801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR1_1_REVISION_ID 0 0x3fff7bfc2802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR1_1_PROG_INTERFACE 0 0x3fff7bfc2802 1 0 5 PROG_INTERFACE 0 7 regBIFPLR1_1_SUB_CLASS 0 0x3fff7bfc2802 1 0 5 SUB_CLASS 0 7 regBIFPLR1_1_BASE_CLASS 0 0x3fff7bfc2802 1 0 5 BASE_CLASS 0 7 regBIFPLR1_1_CACHE_LINE 0 0x3fff7bfc2803 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR1_1_LATENCY 0 0x3fff7bfc2803 1 0 5 LATENCY_TIMER 0 7 regBIFPLR1_1_HEADER 0 0x3fff7bfc2803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR1_1_BIST 0 0x3fff7bfc2803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR1_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc2806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR1_1_IO_BASE_LIMIT 0 0x3fff7bfc2807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR1_1_SECONDARY_STATUS 0 0x3fff7bfc2807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR1_1_MEM_BASE_LIMIT 0 0x3fff7bfc2808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR1_1_PREF_BASE_LIMIT 0 0x3fff7bfc2809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR1_1_PREF_BASE_UPPER 0 0x3fff7bfc280a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR1_1_PREF_LIMIT_UPPER 0 0x3fff7bfc280b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR1_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc280c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR1_1_CAP_PTR 0 0x3fff7bfc280d 1 0 5 CAP_PTR 0 7 regBIFPLR1_1_ROM_BASE_ADDR 0 0x3fff7bfc280e 1 0 5 BASE_ADDR 0 31 regBIFPLR1_1_INTERRUPT_LINE 0 0x3fff7bfc280f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR1_1_INTERRUPT_PIN 0 0x3fff7bfc280f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR1_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc280f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR1_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc2810 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR1_1_VENDOR_CAP_LIST 0 0x3fff7bfc2812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR1_1_ADAPTER_ID_W 0 0x3fff7bfc2813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR1_1_PMI_CAP_LIST 0 0x3fff7bfc2814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_1_PMI_CAP 0 0x3fff7bfc2814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR1_1_PMI_STATUS_CNTL 0 0x3fff7bfc2815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR1_1_PCIE_CAP_LIST 0 0x3fff7bfc2816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_1_PCIE_CAP 0 0x3fff7bfc2816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR1_1_DEVICE_CAP 0 0x3fff7bfc2817 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR1_1_DEVICE_CNTL 0 0x3fff7bfc2818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR1_1_DEVICE_STATUS 0 0x3fff7bfc2818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR1_1_LINK_CAP 0 0x3fff7bfc2819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR1_1_LINK_CNTL 0 0x3fff7bfc281a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR1_1_LINK_STATUS 0 0x3fff7bfc281a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR1_1_SLOT_CAP 0 0x3fff7bfc281b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR1_1_SLOT_CNTL 0 0x3fff7bfc281c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR1_1_SLOT_STATUS 0 0x3fff7bfc281c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR1_1_ROOT_CNTL 0 0x3fff7bfc281d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR1_1_ROOT_CAP 0 0x3fff7bfc281d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR1_1_ROOT_STATUS 0 0x3fff7bfc281e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR1_1_DEVICE_CAP2 0 0x3fff7bfc281f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR1_1_DEVICE_CNTL2 0 0x3fff7bfc2820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR1_1_DEVICE_STATUS2 0 0x3fff7bfc2820 1 0 5 RESERVED 0 15 regBIFPLR1_1_LINK_CAP2 0 0x3fff7bfc2821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR1_1_LINK_CNTL2 0 0x3fff7bfc2822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR1_1_LINK_STATUS2 0 0x3fff7bfc2822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR1_1_SLOT_CAP2 0 0x3fff7bfc2823 1 0 5 RESERVED 0 31 regBIFPLR1_1_SLOT_CNTL2 0 0x3fff7bfc2824 1 0 5 RESERVED 0 15 regBIFPLR1_1_SLOT_STATUS2 0 0x3fff7bfc2824 1 0 5 RESERVED 0 15 regBIFPLR1_1_MSI_CAP_LIST 0 0x3fff7bfc2828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_1_MSI_MSG_CNTL 0 0x3fff7bfc2828 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR1_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc2829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR1_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc282a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR1_1_MSI_MSG_DATA 0 0x3fff7bfc282a 1 0 5 MSI_DATA 0 15 regBIFPLR1_1_MSI_MSG_DATA_64 0 0x3fff7bfc282b 1 0 5 MSI_DATA_64 0 15 regBIFPLR1_1_SSID_CAP_LIST 0 0x3fff7bfc2830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_1_SSID_CAP 0 0x3fff7bfc2831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR1_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc2832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR1_1_MSI_MAP_CAP 0 0x3fff7bfc2832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc2840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc2841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR1_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc2842 1 0 5 SCRATCH 0 31 regBIFPLR1_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc2843 1 0 5 SCRATCH 0 31 regBIFPLR1_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc2844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc2845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR1_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc2846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR1_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc2847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR1_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc2847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR1_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc2848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc2849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc284a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR1_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc284b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc284c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc284d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc2850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc2851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc2852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc2854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc2855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR1_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc2856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc2857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR1_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc2858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR1_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc2859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc285a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR1_1_PCIE_HDR_LOG0 0 0x3fff7bfc285b 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_HDR_LOG1 0 0x3fff7bfc285c 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_HDR_LOG2 0 0x3fff7bfc285d 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_HDR_LOG3 0 0x3fff7bfc285e 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc285f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR1_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc2860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR1_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc2861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR1_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc2862 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc2863 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc2864 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc2865 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc289c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_LINK_CNTL3 0 0x3fff7bfc289d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR1_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc289e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc289f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc289f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc28a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc28a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc28a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc28a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc28a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc28a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc28a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc28a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc28a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc28a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc28a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc28a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc28a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc28a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc28a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_ACS_CAP 0 0x3fff7bfc28a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR1_1_PCIE_ACS_CNTL 0 0x3fff7bfc28a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR1_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc28bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_MC_CAP 0 0x3fff7bfc28bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR1_1_PCIE_MC_CNTL 0 0x3fff7bfc28bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR1_1_PCIE_MC_ADDR0 0 0x3fff7bfc28be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR1_1_PCIE_MC_ADDR1 0 0x3fff7bfc28bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR1_1_PCIE_MC_RCV0 0 0x3fff7bfc28c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR1_1_PCIE_MC_RCV1 0 0x3fff7bfc28c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR1_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc28c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR1_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc28c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc28c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc28c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR1_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc28c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR1_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc28c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc28dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc28dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc28de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc28df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc28e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc28e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR1_1_PCIE_DPC_CNTL 0 0x3fff7bfc28e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR1_1_PCIE_DPC_STATUS 0 0x3fff7bfc28e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc28e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR1_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc28e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc28e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc28e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc28e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc28e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc28e8 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc28e9 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc28ea 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc28eb 1 0 5 TLP_HDR 0 31 regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc28ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc28ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc28ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc28f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR1_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc28f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc28f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR1_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc28f3 1 0 5 CAP_ID 0 15 regBIFPLR1_1_PCIE_ESM_STATUS 0 0x3fff7bfc28f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR1_1_PCIE_ESM_CTRL 0 0x3fff7bfc28f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR1_1_PCIE_ESM_CAP_1 0 0x3fff7bfc28f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR1_1_PCIE_ESM_CAP_2 0 0x3fff7bfc28f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR1_1_PCIE_ESM_CAP_3 0 0x3fff7bfc28f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR1_1_PCIE_ESM_CAP_4 0 0x3fff7bfc28f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR1_1_PCIE_ESM_CAP_5 0 0x3fff7bfc28f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR1_1_PCIE_ESM_CAP_6 0 0x3fff7bfc28fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR1_1_PCIE_ESM_CAP_7 0 0x3fff7bfc28fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR1_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc2900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc2901 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR1_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc2902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc2904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_LINK_CAP_16GT 0 0x3fff7bfc2905 1 0 5 RESERVED 0 31 regBIFPLR1_1_LINK_CNTL_16GT 0 0x3fff7bfc2906 1 0 5 RESERVED 0 31 regBIFPLR1_1_LINK_STATUS_16GT 0 0x3fff7bfc2907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc290a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc290f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc2910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_MARGINING_PORT_CAP 0 0x3fff7bfc2911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR1_1_MARGINING_PORT_STATUS 0 0x3fff7bfc2911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR1_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc2912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc2912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc2913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc2913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc2914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc2914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc2915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc2915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc2916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc2916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc2917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc2917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc2918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc2918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc2919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc2919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc291a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc291a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc291b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc291b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc291c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc291c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc291d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc291d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc291e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc291e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc291f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc291f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc2920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc2920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc2921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR1_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc2921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR1_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc2922 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR1_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc2923 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR1_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc2924 1 0 5 CAP_ID 0 15 regBIFPLR1_1_PCIE_CCIX_CAP 0 0x3fff7bfc2924 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc2925 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc2926 1 0 5 RESERVED 0 31 regBIFPLR1_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc2927 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR1_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc2928 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2929 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2929 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2929 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2929 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc292c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc292f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2930 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2930 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2930 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2930 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR1_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc2931 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR1_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc2932 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR2_1_VENDOR_ID 0 0x3fff7bfc2c00 1 0 5 VENDOR_ID 0 15 regBIFPLR2_1_DEVICE_ID 0 0x3fff7bfc2c00 1 0 5 DEVICE_ID 0 15 regBIFPLR2_1_COMMAND 0 0x3fff7bfc2c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR2_1_STATUS 0 0x3fff7bfc2c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR2_1_REVISION_ID 0 0x3fff7bfc2c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR2_1_PROG_INTERFACE 0 0x3fff7bfc2c02 1 0 5 PROG_INTERFACE 0 7 regBIFPLR2_1_SUB_CLASS 0 0x3fff7bfc2c02 1 0 5 SUB_CLASS 0 7 regBIFPLR2_1_BASE_CLASS 0 0x3fff7bfc2c02 1 0 5 BASE_CLASS 0 7 regBIFPLR2_1_CACHE_LINE 0 0x3fff7bfc2c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR2_1_LATENCY 0 0x3fff7bfc2c03 1 0 5 LATENCY_TIMER 0 7 regBIFPLR2_1_HEADER 0 0x3fff7bfc2c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR2_1_BIST 0 0x3fff7bfc2c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR2_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc2c06 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR2_1_IO_BASE_LIMIT 0 0x3fff7bfc2c07 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR2_1_SECONDARY_STATUS 0 0x3fff7bfc2c07 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR2_1_MEM_BASE_LIMIT 0 0x3fff7bfc2c08 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR2_1_PREF_BASE_LIMIT 0 0x3fff7bfc2c09 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR2_1_PREF_BASE_UPPER 0 0x3fff7bfc2c0a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR2_1_PREF_LIMIT_UPPER 0 0x3fff7bfc2c0b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR2_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc2c0c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR2_1_CAP_PTR 0 0x3fff7bfc2c0d 1 0 5 CAP_PTR 0 7 regBIFPLR2_1_ROM_BASE_ADDR 0 0x3fff7bfc2c0e 1 0 5 BASE_ADDR 0 31 regBIFPLR2_1_INTERRUPT_LINE 0 0x3fff7bfc2c0f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR2_1_INTERRUPT_PIN 0 0x3fff7bfc2c0f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR2_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc2c0f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR2_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc2c10 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR2_1_VENDOR_CAP_LIST 0 0x3fff7bfc2c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR2_1_ADAPTER_ID_W 0 0x3fff7bfc2c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR2_1_PMI_CAP_LIST 0 0x3fff7bfc2c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_1_PMI_CAP 0 0x3fff7bfc2c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR2_1_PMI_STATUS_CNTL 0 0x3fff7bfc2c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR2_1_PCIE_CAP_LIST 0 0x3fff7bfc2c16 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_1_PCIE_CAP 0 0x3fff7bfc2c16 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR2_1_DEVICE_CAP 0 0x3fff7bfc2c17 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR2_1_DEVICE_CNTL 0 0x3fff7bfc2c18 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR2_1_DEVICE_STATUS 0 0x3fff7bfc2c18 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR2_1_LINK_CAP 0 0x3fff7bfc2c19 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR2_1_LINK_CNTL 0 0x3fff7bfc2c1a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR2_1_LINK_STATUS 0 0x3fff7bfc2c1a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR2_1_SLOT_CAP 0 0x3fff7bfc2c1b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR2_1_SLOT_CNTL 0 0x3fff7bfc2c1c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR2_1_SLOT_STATUS 0 0x3fff7bfc2c1c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR2_1_ROOT_CNTL 0 0x3fff7bfc2c1d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR2_1_ROOT_CAP 0 0x3fff7bfc2c1d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR2_1_ROOT_STATUS 0 0x3fff7bfc2c1e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR2_1_DEVICE_CAP2 0 0x3fff7bfc2c1f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR2_1_DEVICE_CNTL2 0 0x3fff7bfc2c20 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR2_1_DEVICE_STATUS2 0 0x3fff7bfc2c20 1 0 5 RESERVED 0 15 regBIFPLR2_1_LINK_CAP2 0 0x3fff7bfc2c21 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR2_1_LINK_CNTL2 0 0x3fff7bfc2c22 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR2_1_LINK_STATUS2 0 0x3fff7bfc2c22 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR2_1_SLOT_CAP2 0 0x3fff7bfc2c23 1 0 5 RESERVED 0 31 regBIFPLR2_1_SLOT_CNTL2 0 0x3fff7bfc2c24 1 0 5 RESERVED 0 15 regBIFPLR2_1_SLOT_STATUS2 0 0x3fff7bfc2c24 1 0 5 RESERVED 0 15 regBIFPLR2_1_MSI_CAP_LIST 0 0x3fff7bfc2c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_1_MSI_MSG_CNTL 0 0x3fff7bfc2c28 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR2_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc2c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR2_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc2c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR2_1_MSI_MSG_DATA 0 0x3fff7bfc2c2a 1 0 5 MSI_DATA 0 15 regBIFPLR2_1_MSI_MSG_DATA_64 0 0x3fff7bfc2c2b 1 0 5 MSI_DATA_64 0 15 regBIFPLR2_1_SSID_CAP_LIST 0 0x3fff7bfc2c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_1_SSID_CAP 0 0x3fff7bfc2c31 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR2_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc2c32 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR2_1_MSI_MAP_CAP 0 0x3fff7bfc2c32 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc2c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc2c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR2_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc2c42 1 0 5 SCRATCH 0 31 regBIFPLR2_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc2c43 1 0 5 SCRATCH 0 31 regBIFPLR2_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc2c44 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc2c45 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR2_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc2c46 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR2_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc2c47 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR2_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc2c47 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR2_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc2c48 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc2c49 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc2c4a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR2_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc2c4b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc2c4c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc2c4d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc2c50 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc2c51 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc2c52 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc2c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc2c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR2_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc2c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc2c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR2_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc2c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR2_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc2c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc2c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR2_1_PCIE_HDR_LOG0 0 0x3fff7bfc2c5b 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_HDR_LOG1 0 0x3fff7bfc2c5c 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_HDR_LOG2 0 0x3fff7bfc2c5d 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_HDR_LOG3 0 0x3fff7bfc2c5e 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc2c5f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR2_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc2c60 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR2_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc2c61 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR2_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc2c62 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc2c63 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc2c64 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc2c65 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc2c9c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_LINK_CNTL3 0 0x3fff7bfc2c9d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR2_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc2c9e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc2c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc2c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc2ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc2ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc2ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc2ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc2ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc2ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc2ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc2ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc2ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc2ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc2ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc2ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc2ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc2ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc2ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_ACS_CAP 0 0x3fff7bfc2ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR2_1_PCIE_ACS_CNTL 0 0x3fff7bfc2ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR2_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc2cbc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_MC_CAP 0 0x3fff7bfc2cbd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR2_1_PCIE_MC_CNTL 0 0x3fff7bfc2cbd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR2_1_PCIE_MC_ADDR0 0 0x3fff7bfc2cbe 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR2_1_PCIE_MC_ADDR1 0 0x3fff7bfc2cbf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR2_1_PCIE_MC_RCV0 0 0x3fff7bfc2cc0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR2_1_PCIE_MC_RCV1 0 0x3fff7bfc2cc1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR2_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc2cc2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR2_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc2cc3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc2cc4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc2cc5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR2_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc2cc6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR2_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc2cc7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc2cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc2cdd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc2cde 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc2cdf 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc2ce0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc2ce1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR2_1_PCIE_DPC_CNTL 0 0x3fff7bfc2ce1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR2_1_PCIE_DPC_STATUS 0 0x3fff7bfc2ce2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc2ce2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR2_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc2ce3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc2ce4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc2ce5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc2ce6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc2ce7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc2ce8 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc2ce9 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc2cea 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc2ceb 1 0 5 TLP_HDR 0 31 regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc2ced 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc2cee 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc2cef 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc2cf0 1 0 5 TLP_PREFIX 0 31 regBIFPLR2_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc2cf1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc2cf2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR2_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc2cf3 1 0 5 CAP_ID 0 15 regBIFPLR2_1_PCIE_ESM_STATUS 0 0x3fff7bfc2cf3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR2_1_PCIE_ESM_CTRL 0 0x3fff7bfc2cf4 1 0 5 ESM_ENABLED 15 15 regBIFPLR2_1_PCIE_ESM_CAP_1 0 0x3fff7bfc2cf5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR2_1_PCIE_ESM_CAP_2 0 0x3fff7bfc2cf6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR2_1_PCIE_ESM_CAP_3 0 0x3fff7bfc2cf7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR2_1_PCIE_ESM_CAP_4 0 0x3fff7bfc2cf8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR2_1_PCIE_ESM_CAP_5 0 0x3fff7bfc2cf9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR2_1_PCIE_ESM_CAP_6 0 0x3fff7bfc2cfa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR2_1_PCIE_ESM_CAP_7 0 0x3fff7bfc2cfb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR2_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc2d00 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc2d01 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR2_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc2d02 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc2d04 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_LINK_CAP_16GT 0 0x3fff7bfc2d05 1 0 5 RESERVED 0 31 regBIFPLR2_1_LINK_CNTL_16GT 0 0x3fff7bfc2d06 1 0 5 RESERVED 0 31 regBIFPLR2_1_LINK_STATUS_16GT 0 0x3fff7bfc2d07 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2d08 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2d09 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc2d0a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc2d0f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc2d10 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_MARGINING_PORT_CAP 0 0x3fff7bfc2d11 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR2_1_MARGINING_PORT_STATUS 0 0x3fff7bfc2d11 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR2_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc2d12 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc2d12 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc2d13 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc2d13 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc2d14 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc2d14 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc2d15 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc2d15 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc2d16 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc2d16 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc2d17 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc2d17 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc2d18 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc2d18 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc2d19 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc2d19 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc2d1f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc2d1f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc2d20 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc2d20 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc2d21 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR2_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc2d21 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR2_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc2d22 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR2_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc2d23 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR2_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc2d24 1 0 5 CAP_ID 0 15 regBIFPLR2_1_PCIE_CCIX_CAP 0 0x3fff7bfc2d24 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc2d25 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc2d26 1 0 5 RESERVED 0 31 regBIFPLR2_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc2d27 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR2_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc2d28 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d29 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d29 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d29 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d29 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc2d2c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d2f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d30 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d30 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d30 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc2d30 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR2_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc2d31 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR2_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc2d32 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR3_1_VENDOR_ID 0 0x3fff7bfc3000 1 0 5 VENDOR_ID 0 15 regBIFPLR3_1_DEVICE_ID 0 0x3fff7bfc3000 1 0 5 DEVICE_ID 0 15 regBIFPLR3_1_COMMAND 0 0x3fff7bfc3001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR3_1_STATUS 0 0x3fff7bfc3001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR3_1_REVISION_ID 0 0x3fff7bfc3002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR3_1_PROG_INTERFACE 0 0x3fff7bfc3002 1 0 5 PROG_INTERFACE 0 7 regBIFPLR3_1_SUB_CLASS 0 0x3fff7bfc3002 1 0 5 SUB_CLASS 0 7 regBIFPLR3_1_BASE_CLASS 0 0x3fff7bfc3002 1 0 5 BASE_CLASS 0 7 regBIFPLR3_1_CACHE_LINE 0 0x3fff7bfc3003 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR3_1_LATENCY 0 0x3fff7bfc3003 1 0 5 LATENCY_TIMER 0 7 regBIFPLR3_1_HEADER 0 0x3fff7bfc3003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR3_1_BIST 0 0x3fff7bfc3003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR3_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc3006 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR3_1_IO_BASE_LIMIT 0 0x3fff7bfc3007 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR3_1_SECONDARY_STATUS 0 0x3fff7bfc3007 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR3_1_MEM_BASE_LIMIT 0 0x3fff7bfc3008 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR3_1_PREF_BASE_LIMIT 0 0x3fff7bfc3009 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR3_1_PREF_BASE_UPPER 0 0x3fff7bfc300a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR3_1_PREF_LIMIT_UPPER 0 0x3fff7bfc300b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR3_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc300c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR3_1_CAP_PTR 0 0x3fff7bfc300d 1 0 5 CAP_PTR 0 7 regBIFPLR3_1_ROM_BASE_ADDR 0 0x3fff7bfc300e 1 0 5 BASE_ADDR 0 31 regBIFPLR3_1_INTERRUPT_LINE 0 0x3fff7bfc300f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR3_1_INTERRUPT_PIN 0 0x3fff7bfc300f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR3_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc300f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR3_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc3010 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR3_1_VENDOR_CAP_LIST 0 0x3fff7bfc3012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR3_1_ADAPTER_ID_W 0 0x3fff7bfc3013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR3_1_PMI_CAP_LIST 0 0x3fff7bfc3014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_1_PMI_CAP 0 0x3fff7bfc3014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR3_1_PMI_STATUS_CNTL 0 0x3fff7bfc3015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR3_1_PCIE_CAP_LIST 0 0x3fff7bfc3016 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_1_PCIE_CAP 0 0x3fff7bfc3016 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR3_1_DEVICE_CAP 0 0x3fff7bfc3017 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR3_1_DEVICE_CNTL 0 0x3fff7bfc3018 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR3_1_DEVICE_STATUS 0 0x3fff7bfc3018 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR3_1_LINK_CAP 0 0x3fff7bfc3019 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR3_1_LINK_CNTL 0 0x3fff7bfc301a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR3_1_LINK_STATUS 0 0x3fff7bfc301a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR3_1_SLOT_CAP 0 0x3fff7bfc301b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR3_1_SLOT_CNTL 0 0x3fff7bfc301c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR3_1_SLOT_STATUS 0 0x3fff7bfc301c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR3_1_ROOT_CNTL 0 0x3fff7bfc301d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR3_1_ROOT_CAP 0 0x3fff7bfc301d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR3_1_ROOT_STATUS 0 0x3fff7bfc301e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR3_1_DEVICE_CAP2 0 0x3fff7bfc301f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR3_1_DEVICE_CNTL2 0 0x3fff7bfc3020 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR3_1_DEVICE_STATUS2 0 0x3fff7bfc3020 1 0 5 RESERVED 0 15 regBIFPLR3_1_LINK_CAP2 0 0x3fff7bfc3021 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR3_1_LINK_CNTL2 0 0x3fff7bfc3022 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR3_1_LINK_STATUS2 0 0x3fff7bfc3022 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR3_1_SLOT_CAP2 0 0x3fff7bfc3023 1 0 5 RESERVED 0 31 regBIFPLR3_1_SLOT_CNTL2 0 0x3fff7bfc3024 1 0 5 RESERVED 0 15 regBIFPLR3_1_SLOT_STATUS2 0 0x3fff7bfc3024 1 0 5 RESERVED 0 15 regBIFPLR3_1_MSI_CAP_LIST 0 0x3fff7bfc3028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_1_MSI_MSG_CNTL 0 0x3fff7bfc3028 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR3_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc3029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR3_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc302a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR3_1_MSI_MSG_DATA 0 0x3fff7bfc302a 1 0 5 MSI_DATA 0 15 regBIFPLR3_1_MSI_MSG_DATA_64 0 0x3fff7bfc302b 1 0 5 MSI_DATA_64 0 15 regBIFPLR3_1_SSID_CAP_LIST 0 0x3fff7bfc3030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_1_SSID_CAP 0 0x3fff7bfc3031 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR3_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc3032 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR3_1_MSI_MAP_CAP 0 0x3fff7bfc3032 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc3040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc3041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR3_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc3042 1 0 5 SCRATCH 0 31 regBIFPLR3_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc3043 1 0 5 SCRATCH 0 31 regBIFPLR3_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc3044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc3045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR3_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc3046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR3_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc3047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR3_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc3047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR3_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc3048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc3049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc304a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR3_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc304b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc304c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc304d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc3050 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc3051 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc3052 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc3054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc3055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR3_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc3056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc3057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR3_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc3058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR3_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc3059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc305a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR3_1_PCIE_HDR_LOG0 0 0x3fff7bfc305b 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_HDR_LOG1 0 0x3fff7bfc305c 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_HDR_LOG2 0 0x3fff7bfc305d 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_HDR_LOG3 0 0x3fff7bfc305e 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc305f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR3_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc3060 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR3_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc3061 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR3_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc3062 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc3063 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc3064 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc3065 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc309c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_LINK_CNTL3 0 0x3fff7bfc309d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR3_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc309e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc309f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc309f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc30a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc30a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc30a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc30a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc30a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc30a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc30a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc30a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc30a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc30a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc30a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc30a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc30a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc30a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc30a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_ACS_CAP 0 0x3fff7bfc30a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR3_1_PCIE_ACS_CNTL 0 0x3fff7bfc30a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR3_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc30bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_MC_CAP 0 0x3fff7bfc30bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR3_1_PCIE_MC_CNTL 0 0x3fff7bfc30bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR3_1_PCIE_MC_ADDR0 0 0x3fff7bfc30be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR3_1_PCIE_MC_ADDR1 0 0x3fff7bfc30bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR3_1_PCIE_MC_RCV0 0 0x3fff7bfc30c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR3_1_PCIE_MC_RCV1 0 0x3fff7bfc30c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR3_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc30c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR3_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc30c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc30c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc30c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR3_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc30c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR3_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc30c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc30dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc30dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc30de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc30df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc30e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc30e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR3_1_PCIE_DPC_CNTL 0 0x3fff7bfc30e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR3_1_PCIE_DPC_STATUS 0 0x3fff7bfc30e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc30e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR3_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc30e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc30e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc30e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc30e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc30e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc30e8 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc30e9 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc30ea 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc30eb 1 0 5 TLP_HDR 0 31 regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc30ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc30ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc30ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc30f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR3_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc30f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc30f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR3_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc30f3 1 0 5 CAP_ID 0 15 regBIFPLR3_1_PCIE_ESM_STATUS 0 0x3fff7bfc30f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR3_1_PCIE_ESM_CTRL 0 0x3fff7bfc30f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR3_1_PCIE_ESM_CAP_1 0 0x3fff7bfc30f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR3_1_PCIE_ESM_CAP_2 0 0x3fff7bfc30f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR3_1_PCIE_ESM_CAP_3 0 0x3fff7bfc30f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR3_1_PCIE_ESM_CAP_4 0 0x3fff7bfc30f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR3_1_PCIE_ESM_CAP_5 0 0x3fff7bfc30f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR3_1_PCIE_ESM_CAP_6 0 0x3fff7bfc30fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR3_1_PCIE_ESM_CAP_7 0 0x3fff7bfc30fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR3_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc3100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc3101 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR3_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc3102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc3104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_LINK_CAP_16GT 0 0x3fff7bfc3105 1 0 5 RESERVED 0 31 regBIFPLR3_1_LINK_CNTL_16GT 0 0x3fff7bfc3106 1 0 5 RESERVED 0 31 regBIFPLR3_1_LINK_STATUS_16GT 0 0x3fff7bfc3107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc310a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc310f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc3110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_MARGINING_PORT_CAP 0 0x3fff7bfc3111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR3_1_MARGINING_PORT_STATUS 0 0x3fff7bfc3111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR3_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc3112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc3112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc3113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc3113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc3114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc3114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc3115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc3115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc3116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc3116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc3117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc3117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc3118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc3118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc3119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc3119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc311a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc311a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc311b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc311b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc311c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc311c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc311d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc311d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc311e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc311e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc311f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc311f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc3120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc3120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc3121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR3_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc3121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR3_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc3122 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR3_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc3123 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR3_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc3124 1 0 5 CAP_ID 0 15 regBIFPLR3_1_PCIE_CCIX_CAP 0 0x3fff7bfc3124 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc3125 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc3126 1 0 5 RESERVED 0 31 regBIFPLR3_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc3127 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR3_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc3128 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3129 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3129 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3129 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3129 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc312c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc312f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3130 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3130 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3130 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3130 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR3_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc3131 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR3_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc3132 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR4_1_VENDOR_ID 0 0x3fff7bfc3400 1 0 5 VENDOR_ID 0 15 regBIFPLR4_1_DEVICE_ID 0 0x3fff7bfc3400 1 0 5 DEVICE_ID 0 15 regBIFPLR4_1_COMMAND 0 0x3fff7bfc3401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR4_1_STATUS 0 0x3fff7bfc3401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR4_1_REVISION_ID 0 0x3fff7bfc3402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR4_1_PROG_INTERFACE 0 0x3fff7bfc3402 1 0 5 PROG_INTERFACE 0 7 regBIFPLR4_1_SUB_CLASS 0 0x3fff7bfc3402 1 0 5 SUB_CLASS 0 7 regBIFPLR4_1_BASE_CLASS 0 0x3fff7bfc3402 1 0 5 BASE_CLASS 0 7 regBIFPLR4_1_CACHE_LINE 0 0x3fff7bfc3403 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR4_1_LATENCY 0 0x3fff7bfc3403 1 0 5 LATENCY_TIMER 0 7 regBIFPLR4_1_HEADER 0 0x3fff7bfc3403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR4_1_BIST 0 0x3fff7bfc3403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR4_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc3406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR4_1_IO_BASE_LIMIT 0 0x3fff7bfc3407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR4_1_SECONDARY_STATUS 0 0x3fff7bfc3407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR4_1_MEM_BASE_LIMIT 0 0x3fff7bfc3408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR4_1_PREF_BASE_LIMIT 0 0x3fff7bfc3409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR4_1_PREF_BASE_UPPER 0 0x3fff7bfc340a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR4_1_PREF_LIMIT_UPPER 0 0x3fff7bfc340b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR4_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc340c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR4_1_CAP_PTR 0 0x3fff7bfc340d 1 0 5 CAP_PTR 0 7 regBIFPLR4_1_ROM_BASE_ADDR 0 0x3fff7bfc340e 1 0 5 BASE_ADDR 0 31 regBIFPLR4_1_INTERRUPT_LINE 0 0x3fff7bfc340f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR4_1_INTERRUPT_PIN 0 0x3fff7bfc340f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR4_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc340f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR4_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc3410 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR4_1_VENDOR_CAP_LIST 0 0x3fff7bfc3412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR4_1_ADAPTER_ID_W 0 0x3fff7bfc3413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR4_1_PMI_CAP_LIST 0 0x3fff7bfc3414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_1_PMI_CAP 0 0x3fff7bfc3414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR4_1_PMI_STATUS_CNTL 0 0x3fff7bfc3415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR4_1_PCIE_CAP_LIST 0 0x3fff7bfc3416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_1_PCIE_CAP 0 0x3fff7bfc3416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR4_1_DEVICE_CAP 0 0x3fff7bfc3417 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR4_1_DEVICE_CNTL 0 0x3fff7bfc3418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR4_1_DEVICE_STATUS 0 0x3fff7bfc3418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR4_1_LINK_CAP 0 0x3fff7bfc3419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR4_1_LINK_CNTL 0 0x3fff7bfc341a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR4_1_LINK_STATUS 0 0x3fff7bfc341a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR4_1_SLOT_CAP 0 0x3fff7bfc341b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR4_1_SLOT_CNTL 0 0x3fff7bfc341c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR4_1_SLOT_STATUS 0 0x3fff7bfc341c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR4_1_ROOT_CNTL 0 0x3fff7bfc341d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR4_1_ROOT_CAP 0 0x3fff7bfc341d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR4_1_ROOT_STATUS 0 0x3fff7bfc341e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR4_1_DEVICE_CAP2 0 0x3fff7bfc341f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR4_1_DEVICE_CNTL2 0 0x3fff7bfc3420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR4_1_DEVICE_STATUS2 0 0x3fff7bfc3420 1 0 5 RESERVED 0 15 regBIFPLR4_1_LINK_CAP2 0 0x3fff7bfc3421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR4_1_LINK_CNTL2 0 0x3fff7bfc3422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR4_1_LINK_STATUS2 0 0x3fff7bfc3422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR4_1_SLOT_CAP2 0 0x3fff7bfc3423 1 0 5 RESERVED 0 31 regBIFPLR4_1_SLOT_CNTL2 0 0x3fff7bfc3424 1 0 5 RESERVED 0 15 regBIFPLR4_1_SLOT_STATUS2 0 0x3fff7bfc3424 1 0 5 RESERVED 0 15 regBIFPLR4_1_MSI_CAP_LIST 0 0x3fff7bfc3428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_1_MSI_MSG_CNTL 0 0x3fff7bfc3428 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR4_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc3429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR4_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc342a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR4_1_MSI_MSG_DATA 0 0x3fff7bfc342a 1 0 5 MSI_DATA 0 15 regBIFPLR4_1_MSI_MSG_DATA_64 0 0x3fff7bfc342b 1 0 5 MSI_DATA_64 0 15 regBIFPLR4_1_SSID_CAP_LIST 0 0x3fff7bfc3430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_1_SSID_CAP 0 0x3fff7bfc3431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR4_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc3432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR4_1_MSI_MAP_CAP 0 0x3fff7bfc3432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc3440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc3441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR4_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc3442 1 0 5 SCRATCH 0 31 regBIFPLR4_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc3443 1 0 5 SCRATCH 0 31 regBIFPLR4_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc3444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc3445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR4_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc3446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR4_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc3447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR4_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc3447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR4_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc3448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc3449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc344a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR4_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc344b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc344c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc344d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc3450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc3451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc3452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc3454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc3455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR4_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc3456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc3457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR4_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc3458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR4_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc3459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc345a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR4_1_PCIE_HDR_LOG0 0 0x3fff7bfc345b 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_HDR_LOG1 0 0x3fff7bfc345c 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_HDR_LOG2 0 0x3fff7bfc345d 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_HDR_LOG3 0 0x3fff7bfc345e 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc345f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR4_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc3460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR4_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc3461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR4_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc3462 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc3463 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc3464 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc3465 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc349c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_LINK_CNTL3 0 0x3fff7bfc349d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR4_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc349e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc349f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc349f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc34a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc34a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc34a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc34a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc34a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc34a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc34a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc34a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc34a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc34a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc34a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc34a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc34a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc34a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc34a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_ACS_CAP 0 0x3fff7bfc34a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR4_1_PCIE_ACS_CNTL 0 0x3fff7bfc34a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR4_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc34bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_MC_CAP 0 0x3fff7bfc34bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR4_1_PCIE_MC_CNTL 0 0x3fff7bfc34bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR4_1_PCIE_MC_ADDR0 0 0x3fff7bfc34be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR4_1_PCIE_MC_ADDR1 0 0x3fff7bfc34bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR4_1_PCIE_MC_RCV0 0 0x3fff7bfc34c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR4_1_PCIE_MC_RCV1 0 0x3fff7bfc34c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR4_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc34c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR4_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc34c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc34c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc34c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR4_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc34c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR4_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc34c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc34dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc34dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc34de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc34df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc34e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc34e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR4_1_PCIE_DPC_CNTL 0 0x3fff7bfc34e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR4_1_PCIE_DPC_STATUS 0 0x3fff7bfc34e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc34e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR4_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc34e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc34e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc34e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc34e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc34e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc34e8 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc34e9 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc34ea 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc34eb 1 0 5 TLP_HDR 0 31 regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc34ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc34ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc34ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc34f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR4_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc34f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc34f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR4_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc34f3 1 0 5 CAP_ID 0 15 regBIFPLR4_1_PCIE_ESM_STATUS 0 0x3fff7bfc34f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR4_1_PCIE_ESM_CTRL 0 0x3fff7bfc34f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR4_1_PCIE_ESM_CAP_1 0 0x3fff7bfc34f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR4_1_PCIE_ESM_CAP_2 0 0x3fff7bfc34f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR4_1_PCIE_ESM_CAP_3 0 0x3fff7bfc34f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR4_1_PCIE_ESM_CAP_4 0 0x3fff7bfc34f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR4_1_PCIE_ESM_CAP_5 0 0x3fff7bfc34f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR4_1_PCIE_ESM_CAP_6 0 0x3fff7bfc34fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR4_1_PCIE_ESM_CAP_7 0 0x3fff7bfc34fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR4_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc3500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc3501 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR4_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc3502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc3504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_LINK_CAP_16GT 0 0x3fff7bfc3505 1 0 5 RESERVED 0 31 regBIFPLR4_1_LINK_CNTL_16GT 0 0x3fff7bfc3506 1 0 5 RESERVED 0 31 regBIFPLR4_1_LINK_STATUS_16GT 0 0x3fff7bfc3507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc350a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc350f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc3510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_MARGINING_PORT_CAP 0 0x3fff7bfc3511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR4_1_MARGINING_PORT_STATUS 0 0x3fff7bfc3511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR4_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc3512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc3512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc3513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc3513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc3514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc3514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc3515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc3515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc3516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc3516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc3517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc3517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc3518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc3518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc3519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc3519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc351a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc351a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc351b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc351b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc351c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc351c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc351d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc351d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc351e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc351e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc351f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc351f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc3520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc3520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc3521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR4_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc3521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR4_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc3522 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR4_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc3523 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR4_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc3524 1 0 5 CAP_ID 0 15 regBIFPLR4_1_PCIE_CCIX_CAP 0 0x3fff7bfc3524 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc3525 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc3526 1 0 5 RESERVED 0 31 regBIFPLR4_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc3527 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR4_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc3528 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3529 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3529 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3529 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3529 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc352c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc352f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3530 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3530 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3530 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3530 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR4_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc3531 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR4_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc3532 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR5_1_VENDOR_ID 0 0x3fff7bfc3800 1 0 5 VENDOR_ID 0 15 regBIFPLR5_1_DEVICE_ID 0 0x3fff7bfc3800 1 0 5 DEVICE_ID 0 15 regBIFPLR5_1_COMMAND 0 0x3fff7bfc3801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR5_1_STATUS 0 0x3fff7bfc3801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR5_1_REVISION_ID 0 0x3fff7bfc3802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR5_1_PROG_INTERFACE 0 0x3fff7bfc3802 1 0 5 PROG_INTERFACE 0 7 regBIFPLR5_1_SUB_CLASS 0 0x3fff7bfc3802 1 0 5 SUB_CLASS 0 7 regBIFPLR5_1_BASE_CLASS 0 0x3fff7bfc3802 1 0 5 BASE_CLASS 0 7 regBIFPLR5_1_CACHE_LINE 0 0x3fff7bfc3803 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR5_1_LATENCY 0 0x3fff7bfc3803 1 0 5 LATENCY_TIMER 0 7 regBIFPLR5_1_HEADER 0 0x3fff7bfc3803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR5_1_BIST 0 0x3fff7bfc3803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR5_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc3806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR5_1_IO_BASE_LIMIT 0 0x3fff7bfc3807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR5_1_SECONDARY_STATUS 0 0x3fff7bfc3807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR5_1_MEM_BASE_LIMIT 0 0x3fff7bfc3808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR5_1_PREF_BASE_LIMIT 0 0x3fff7bfc3809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR5_1_PREF_BASE_UPPER 0 0x3fff7bfc380a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR5_1_PREF_LIMIT_UPPER 0 0x3fff7bfc380b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR5_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc380c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR5_1_CAP_PTR 0 0x3fff7bfc380d 1 0 5 CAP_PTR 0 7 regBIFPLR5_1_ROM_BASE_ADDR 0 0x3fff7bfc380e 1 0 5 BASE_ADDR 0 31 regBIFPLR5_1_INTERRUPT_LINE 0 0x3fff7bfc380f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR5_1_INTERRUPT_PIN 0 0x3fff7bfc380f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR5_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc380f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR5_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc3810 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR5_1_VENDOR_CAP_LIST 0 0x3fff7bfc3812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR5_1_ADAPTER_ID_W 0 0x3fff7bfc3813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR5_1_PMI_CAP_LIST 0 0x3fff7bfc3814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_1_PMI_CAP 0 0x3fff7bfc3814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR5_1_PMI_STATUS_CNTL 0 0x3fff7bfc3815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR5_1_PCIE_CAP_LIST 0 0x3fff7bfc3816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_1_PCIE_CAP 0 0x3fff7bfc3816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR5_1_DEVICE_CAP 0 0x3fff7bfc3817 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR5_1_DEVICE_CNTL 0 0x3fff7bfc3818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR5_1_DEVICE_STATUS 0 0x3fff7bfc3818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR5_1_LINK_CAP 0 0x3fff7bfc3819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR5_1_LINK_CNTL 0 0x3fff7bfc381a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR5_1_LINK_STATUS 0 0x3fff7bfc381a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR5_1_SLOT_CAP 0 0x3fff7bfc381b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR5_1_SLOT_CNTL 0 0x3fff7bfc381c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR5_1_SLOT_STATUS 0 0x3fff7bfc381c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR5_1_ROOT_CNTL 0 0x3fff7bfc381d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR5_1_ROOT_CAP 0 0x3fff7bfc381d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR5_1_ROOT_STATUS 0 0x3fff7bfc381e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR5_1_DEVICE_CAP2 0 0x3fff7bfc381f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR5_1_DEVICE_CNTL2 0 0x3fff7bfc3820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR5_1_DEVICE_STATUS2 0 0x3fff7bfc3820 1 0 5 RESERVED 0 15 regBIFPLR5_1_LINK_CAP2 0 0x3fff7bfc3821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR5_1_LINK_CNTL2 0 0x3fff7bfc3822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR5_1_LINK_STATUS2 0 0x3fff7bfc3822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR5_1_SLOT_CAP2 0 0x3fff7bfc3823 1 0 5 RESERVED 0 31 regBIFPLR5_1_SLOT_CNTL2 0 0x3fff7bfc3824 1 0 5 RESERVED 0 15 regBIFPLR5_1_SLOT_STATUS2 0 0x3fff7bfc3824 1 0 5 RESERVED 0 15 regBIFPLR5_1_MSI_CAP_LIST 0 0x3fff7bfc3828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_1_MSI_MSG_CNTL 0 0x3fff7bfc3828 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR5_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc3829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR5_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc382a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR5_1_MSI_MSG_DATA 0 0x3fff7bfc382a 1 0 5 MSI_DATA 0 15 regBIFPLR5_1_MSI_MSG_DATA_64 0 0x3fff7bfc382b 1 0 5 MSI_DATA_64 0 15 regBIFPLR5_1_SSID_CAP_LIST 0 0x3fff7bfc3830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_1_SSID_CAP 0 0x3fff7bfc3831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR5_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc3832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR5_1_MSI_MAP_CAP 0 0x3fff7bfc3832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc3840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc3841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR5_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc3842 1 0 5 SCRATCH 0 31 regBIFPLR5_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc3843 1 0 5 SCRATCH 0 31 regBIFPLR5_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc3844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc3845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR5_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc3846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR5_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc3847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR5_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc3847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR5_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc3848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc3849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc384a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR5_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc384b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc384c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc384d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc3850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc3851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc3852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc3854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc3855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR5_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc3856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc3857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR5_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc3858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR5_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc3859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc385a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR5_1_PCIE_HDR_LOG0 0 0x3fff7bfc385b 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_HDR_LOG1 0 0x3fff7bfc385c 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_HDR_LOG2 0 0x3fff7bfc385d 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_HDR_LOG3 0 0x3fff7bfc385e 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc385f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR5_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc3860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR5_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc3861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR5_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc3862 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc3863 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc3864 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc3865 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc389c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_LINK_CNTL3 0 0x3fff7bfc389d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR5_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc389e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc389f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc389f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc38a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc38a0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc38a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc38a1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc38a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc38a2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc38a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc38a3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc38a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc38a4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc38a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc38a5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc38a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc38a6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc38a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_ACS_CAP 0 0x3fff7bfc38a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR5_1_PCIE_ACS_CNTL 0 0x3fff7bfc38a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR5_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc38bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_MC_CAP 0 0x3fff7bfc38bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR5_1_PCIE_MC_CNTL 0 0x3fff7bfc38bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR5_1_PCIE_MC_ADDR0 0 0x3fff7bfc38be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR5_1_PCIE_MC_ADDR1 0 0x3fff7bfc38bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR5_1_PCIE_MC_RCV0 0 0x3fff7bfc38c0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR5_1_PCIE_MC_RCV1 0 0x3fff7bfc38c1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR5_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc38c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR5_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc38c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc38c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc38c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR5_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc38c6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR5_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc38c7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc38dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc38dd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc38de 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc38df 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc38e0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc38e1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR5_1_PCIE_DPC_CNTL 0 0x3fff7bfc38e1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR5_1_PCIE_DPC_STATUS 0 0x3fff7bfc38e2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc38e2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR5_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc38e3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc38e4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc38e5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc38e6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc38e7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc38e8 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc38e9 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc38ea 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc38eb 1 0 5 TLP_HDR 0 31 regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc38ed 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc38ee 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc38ef 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc38f0 1 0 5 TLP_PREFIX 0 31 regBIFPLR5_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc38f1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc38f2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR5_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc38f3 1 0 5 CAP_ID 0 15 regBIFPLR5_1_PCIE_ESM_STATUS 0 0x3fff7bfc38f3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR5_1_PCIE_ESM_CTRL 0 0x3fff7bfc38f4 1 0 5 ESM_ENABLED 15 15 regBIFPLR5_1_PCIE_ESM_CAP_1 0 0x3fff7bfc38f5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR5_1_PCIE_ESM_CAP_2 0 0x3fff7bfc38f6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR5_1_PCIE_ESM_CAP_3 0 0x3fff7bfc38f7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR5_1_PCIE_ESM_CAP_4 0 0x3fff7bfc38f8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR5_1_PCIE_ESM_CAP_5 0 0x3fff7bfc38f9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR5_1_PCIE_ESM_CAP_6 0 0x3fff7bfc38fa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR5_1_PCIE_ESM_CAP_7 0 0x3fff7bfc38fb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR5_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc3900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc3901 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR5_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc3902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc3904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_LINK_CAP_16GT 0 0x3fff7bfc3905 1 0 5 RESERVED 0 31 regBIFPLR5_1_LINK_CNTL_16GT 0 0x3fff7bfc3906 1 0 5 RESERVED 0 31 regBIFPLR5_1_LINK_STATUS_16GT 0 0x3fff7bfc3907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc390a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc390f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc3910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_MARGINING_PORT_CAP 0 0x3fff7bfc3911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR5_1_MARGINING_PORT_STATUS 0 0x3fff7bfc3911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR5_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc3912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc3912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc3913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc3913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc3914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc3914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc3915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc3915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc3916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc3916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc3917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc3917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc3918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc3918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc3919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc3919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc391a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc391a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc391b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc391b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc391c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc391c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc391d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc391d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc391e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc391e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc391f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc391f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc3920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc3920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc3921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR5_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc3921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR5_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc3922 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR5_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc3923 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR5_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc3924 1 0 5 CAP_ID 0 15 regBIFPLR5_1_PCIE_CCIX_CAP 0 0x3fff7bfc3924 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc3925 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc3926 1 0 5 RESERVED 0 31 regBIFPLR5_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc3927 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR5_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc3928 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3929 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3929 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3929 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3929 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc392c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc392f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3930 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3930 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3930 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3930 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR5_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc3931 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR5_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc3932 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIFPLR6_1_VENDOR_ID 0 0x3fff7bfc3c00 1 0 5 VENDOR_ID 0 15 regBIFPLR6_1_DEVICE_ID 0 0x3fff7bfc3c00 1 0 5 DEVICE_ID 0 15 regBIFPLR6_1_COMMAND 0 0x3fff7bfc3c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIFPLR6_1_STATUS 0 0x3fff7bfc3c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR6_1_REVISION_ID 0 0x3fff7bfc3c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIFPLR6_1_PROG_INTERFACE 0 0x3fff7bfc3c02 1 0 5 PROG_INTERFACE 0 7 regBIFPLR6_1_SUB_CLASS 0 0x3fff7bfc3c02 1 0 5 SUB_CLASS 0 7 regBIFPLR6_1_BASE_CLASS 0 0x3fff7bfc3c02 1 0 5 BASE_CLASS 0 7 regBIFPLR6_1_CACHE_LINE 0 0x3fff7bfc3c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIFPLR6_1_LATENCY 0 0x3fff7bfc3c03 1 0 5 LATENCY_TIMER 0 7 regBIFPLR6_1_HEADER 0 0x3fff7bfc3c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIFPLR6_1_BIST 0 0x3fff7bfc3c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIFPLR6_1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfc3c06 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIFPLR6_1_IO_BASE_LIMIT 0 0x3fff7bfc3c07 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIFPLR6_1_SECONDARY_STATUS 0 0x3fff7bfc3c07 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIFPLR6_1_MEM_BASE_LIMIT 0 0x3fff7bfc3c08 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIFPLR6_1_PREF_BASE_LIMIT 0 0x3fff7bfc3c09 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIFPLR6_1_PREF_BASE_UPPER 0 0x3fff7bfc3c0a 1 0 5 PREF_BASE_UPPER 0 31 regBIFPLR6_1_PREF_LIMIT_UPPER 0 0x3fff7bfc3c0b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIFPLR6_1_IO_BASE_LIMIT_HI 0 0x3fff7bfc3c0c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIFPLR6_1_CAP_PTR 0 0x3fff7bfc3c0d 1 0 5 CAP_PTR 0 7 regBIFPLR6_1_ROM_BASE_ADDR 0 0x3fff7bfc3c0e 1 0 5 BASE_ADDR 0 31 regBIFPLR6_1_INTERRUPT_LINE 0 0x3fff7bfc3c0f 1 0 5 INTERRUPT_LINE 0 7 regBIFPLR6_1_INTERRUPT_PIN 0 0x3fff7bfc3c0f 1 0 5 INTERRUPT_PIN 0 7 regBIFPLR6_1_IRQ_BRIDGE_CNTL 0 0x3fff7bfc3c0f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIFPLR6_1_EXT_BRIDGE_CNTL 0 0x3fff7bfc3c10 1 0 5 IO_PORT_80_EN 0 0 regBIFPLR6_1_VENDOR_CAP_LIST 0 0x3fff7bfc3c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIFPLR6_1_ADAPTER_ID_W 0 0x3fff7bfc3c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR6_1_PMI_CAP_LIST 0 0x3fff7bfc3c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_1_PMI_CAP 0 0x3fff7bfc3c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIFPLR6_1_PMI_STATUS_CNTL 0 0x3fff7bfc3c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIFPLR6_1_PCIE_CAP_LIST 0 0x3fff7bfc3c16 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_1_PCIE_CAP 0 0x3fff7bfc3c16 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIFPLR6_1_DEVICE_CAP 0 0x3fff7bfc3c17 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIFPLR6_1_DEVICE_CNTL 0 0x3fff7bfc3c18 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIFPLR6_1_DEVICE_STATUS 0 0x3fff7bfc3c18 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIFPLR6_1_LINK_CAP 0 0x3fff7bfc3c19 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIFPLR6_1_LINK_CNTL 0 0x3fff7bfc3c1a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIFPLR6_1_LINK_STATUS 0 0x3fff7bfc3c1a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIFPLR6_1_SLOT_CAP 0 0x3fff7bfc3c1b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIFPLR6_1_SLOT_CNTL 0 0x3fff7bfc3c1c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIFPLR6_1_SLOT_STATUS 0 0x3fff7bfc3c1c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIFPLR6_1_ROOT_CNTL 0 0x3fff7bfc3c1d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIFPLR6_1_ROOT_CAP 0 0x3fff7bfc3c1d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIFPLR6_1_ROOT_STATUS 0 0x3fff7bfc3c1e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIFPLR6_1_DEVICE_CAP2 0 0x3fff7bfc3c1f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIFPLR6_1_DEVICE_CNTL2 0 0x3fff7bfc3c20 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIFPLR6_1_DEVICE_STATUS2 0 0x3fff7bfc3c20 1 0 5 RESERVED 0 15 regBIFPLR6_1_LINK_CAP2 0 0x3fff7bfc3c21 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIFPLR6_1_LINK_CNTL2 0 0x3fff7bfc3c22 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIFPLR6_1_LINK_STATUS2 0 0x3fff7bfc3c22 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIFPLR6_1_SLOT_CAP2 0 0x3fff7bfc3c23 1 0 5 RESERVED 0 31 regBIFPLR6_1_SLOT_CNTL2 0 0x3fff7bfc3c24 1 0 5 RESERVED 0 15 regBIFPLR6_1_SLOT_STATUS2 0 0x3fff7bfc3c24 1 0 5 RESERVED 0 15 regBIFPLR6_1_MSI_CAP_LIST 0 0x3fff7bfc3c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_1_MSI_MSG_CNTL 0 0x3fff7bfc3c28 5 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 regBIFPLR6_1_MSI_MSG_ADDR_LO 0 0x3fff7bfc3c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIFPLR6_1_MSI_MSG_ADDR_HI 0 0x3fff7bfc3c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIFPLR6_1_MSI_MSG_DATA 0 0x3fff7bfc3c2a 1 0 5 MSI_DATA 0 15 regBIFPLR6_1_MSI_MSG_DATA_64 0 0x3fff7bfc3c2b 1 0 5 MSI_DATA_64 0 15 regBIFPLR6_1_SSID_CAP_LIST 0 0x3fff7bfc3c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_1_SSID_CAP 0 0x3fff7bfc3c31 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIFPLR6_1_MSI_MAP_CAP_LIST 0 0x3fff7bfc3c32 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIFPLR6_1_MSI_MAP_CAP 0 0x3fff7bfc3c32 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfc3c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfc3c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIFPLR6_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfc3c42 1 0 5 SCRATCH 0 31 regBIFPLR6_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfc3c43 1 0 5 SCRATCH 0 31 regBIFPLR6_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfc3c44 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfc3c45 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIFPLR6_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfc3c46 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIFPLR6_1_PCIE_PORT_VC_CNTL 0 0x3fff7bfc3c47 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIFPLR6_1_PCIE_PORT_VC_STATUS 0 0x3fff7bfc3c47 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIFPLR6_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfc3c48 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR6_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfc3c49 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR6_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfc3c4a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR6_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfc3c4b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIFPLR6_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfc3c4c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIFPLR6_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfc3c4d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfc3c50 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfc3c51 1 0 5 SERIAL_NUMBER_LO 0 31 regBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfc3c52 1 0 5 SERIAL_NUMBER_HI 0 31 regBIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfc3c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfc3c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIFPLR6_1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfc3c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfc3c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIFPLR6_1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfc3c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIFPLR6_1_PCIE_CORR_ERR_MASK 0 0x3fff7bfc3c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfc3c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIFPLR6_1_PCIE_HDR_LOG0 0 0x3fff7bfc3c5b 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_HDR_LOG1 0 0x3fff7bfc3c5c 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_HDR_LOG2 0 0x3fff7bfc3c5d 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_HDR_LOG3 0 0x3fff7bfc3c5e 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfc3c5f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIFPLR6_1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfc3c60 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIFPLR6_1_PCIE_ERR_SRC_ID 0 0x3fff7bfc3c61 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIFPLR6_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfc3c62 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfc3c63 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfc3c64 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfc3c65 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfc3c9c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_LINK_CNTL3 0 0x3fff7bfc3c9d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIFPLR6_1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfc3c9e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfc3c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfc3c9f 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfc3ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfc3ca0 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfc3ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfc3ca1 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfc3ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfc3ca2 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfc3ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfc3ca3 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfc3ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfc3ca4 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfc3ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfc3ca5 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfc3ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfc3ca6 4 0 5 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 regBIFPLR6_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfc3ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_ACS_CAP 0 0x3fff7bfc3ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIFPLR6_1_PCIE_ACS_CNTL 0 0x3fff7bfc3ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIFPLR6_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff7bfc3cbc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_MC_CAP 0 0x3fff7bfc3cbd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIFPLR6_1_PCIE_MC_CNTL 0 0x3fff7bfc3cbd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIFPLR6_1_PCIE_MC_ADDR0 0 0x3fff7bfc3cbe 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIFPLR6_1_PCIE_MC_ADDR1 0 0x3fff7bfc3cbf 1 0 5 MC_BASE_ADDR_1 0 31 regBIFPLR6_1_PCIE_MC_RCV0 0 0x3fff7bfc3cc0 1 0 5 MC_RECEIVE_0 0 31 regBIFPLR6_1_PCIE_MC_RCV1 0 0x3fff7bfc3cc1 1 0 5 MC_RECEIVE_1 0 31 regBIFPLR6_1_PCIE_MC_BLOCK_ALL0 0 0x3fff7bfc3cc2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIFPLR6_1_PCIE_MC_BLOCK_ALL1 0 0x3fff7bfc3cc3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff7bfc3cc4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff7bfc3cc5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIFPLR6_1_PCIE_MC_OVERLAY_BAR0 0 0x3fff7bfc3cc6 2 0 5 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 regBIFPLR6_1_PCIE_MC_OVERLAY_BAR1 0 0x3fff7bfc3cc7 1 0 5 MC_OVERLAY_BAR_1 0 31 regBIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST 0 0x3fff7bfc3cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_L1_PM_SUB_CAP 0 0x3fff7bfc3cdd 8 0 5 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL 0 0x3fff7bfc3cde 7 0 5 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 regBIFPLR6_1_PCIE_L1_PM_SUB_CNTL2 0 0x3fff7bfc3cdf 2 0 5 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 regBIFPLR6_1_PCIE_DPC_ENH_CAP_LIST 0 0x3fff7bfc3ce0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_DPC_CAP_LIST 0 0x3fff7bfc3ce1 6 0 5 DPC_INTR_MSG_NUM 0 4 RP_EXTENSIONS_FOR_DPC 5 5 POISONED_TLP_EGRESS_BLOCKING_SUPPORTED 6 6 DPC_SOFTWARE_TRIGGERING_SUPPORTED 7 7 RP_PIO_LOG_SIZE 8 11 DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED 12 12 regBIFPLR6_1_PCIE_DPC_CNTL 0 0x3fff7bfc3ce1 7 0 5 DPC_TRIGGER_ENABLE 0 1 DPC_COMPLETION_CONTROL 2 2 DPC_INTERRUPT_ENABLE 3 3 DPC_ERR_COR_ENABLE 4 4 POISONED_TLP_EGRESS_BLOCKING_ENABLE 5 5 DPC_SOFTWARE_TRIGGER 6 6 DL_ACTIVE_ERR_COR_ENABLE 7 7 regBIFPLR6_1_PCIE_DPC_STATUS 0 0x3fff7bfc3ce2 6 0 5 DPC_TRIGGER_STATUS 0 0 DPC_TRIGGER_REASON 1 2 DPC_INTERRUPT_STATUS 3 3 DPC_RP_BUSY 4 4 DPC_TRIGGER_REASON_EXTENSION 5 6 RP_PIO_FIRST_ERROR_POINTER 8 12 regBIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID 0 0x3fff7bfc3ce2 1 0 5 DPC_ERROR_SOURCE_ID 0 15 regBIFPLR6_1_PCIE_RP_PIO_STATUS 0 0x3fff7bfc3ce3 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_1_PCIE_RP_PIO_MASK 0 0x3fff7bfc3ce4 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_1_PCIE_RP_PIO_SEVERITY 0 0x3fff7bfc3ce5 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_1_PCIE_RP_PIO_SYSERROR 0 0x3fff7bfc3ce6 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_1_PCIE_RP_PIO_EXCEPTION 0 0x3fff7bfc3ce7 9 0 5 CFG_UR_CPL 0 0 CFG_CA_CPL 1 1 CFG_CTO 2 2 IO_UR_CPL 8 8 IO_CA_CPL 9 9 IO_CTO 10 10 MEM_UR_CPL 16 16 MEM_CA_CPL 17 17 MEM_CTO 18 18 regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG0 0 0x3fff7bfc3ce8 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG1 0 0x3fff7bfc3ce9 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG2 0 0x3fff7bfc3cea 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_RP_PIO_HDR_LOG3 0 0x3fff7bfc3ceb 1 0 5 TLP_HDR 0 31 regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0 0 0x3fff7bfc3ced 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1 0 0x3fff7bfc3cee 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2 0 0x3fff7bfc3cef 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3 0 0x3fff7bfc3cf0 1 0 5 TLP_PREFIX 0 31 regBIFPLR6_1_PCIE_ESM_CAP_LIST 0 0x3fff7bfc3cf1 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_ESM_HEADER_1 0 0x3fff7bfc3cf2 3 0 5 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 regBIFPLR6_1_PCIE_ESM_HEADER_2 0 0x3fff7bfc3cf3 1 0 5 CAP_ID 0 15 regBIFPLR6_1_PCIE_ESM_STATUS 0 0x3fff7bfc3cf3 2 0 5 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 regBIFPLR6_1_PCIE_ESM_CTRL 0 0x3fff7bfc3cf4 1 0 5 ESM_ENABLED 15 15 regBIFPLR6_1_PCIE_ESM_CAP_1 0 0x3fff7bfc3cf5 30 0 5 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 regBIFPLR6_1_PCIE_ESM_CAP_2 0 0x3fff7bfc3cf6 30 0 5 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 regBIFPLR6_1_PCIE_ESM_CAP_3 0 0x3fff7bfc3cf7 20 0 5 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 regBIFPLR6_1_PCIE_ESM_CAP_4 0 0x3fff7bfc3cf8 30 0 5 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 regBIFPLR6_1_PCIE_ESM_CAP_5 0 0x3fff7bfc3cf9 30 0 5 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 regBIFPLR6_1_PCIE_ESM_CAP_6 0 0x3fff7bfc3cfa 30 0 5 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 regBIFPLR6_1_PCIE_ESM_CAP_7 0 0x3fff7bfc3cfb 31 0 5 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 regBIFPLR6_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfc3d00 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfc3d01 3 0 5 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 regBIFPLR6_1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfc3d02 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfc3d04 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_LINK_CAP_16GT 0 0x3fff7bfc3d05 1 0 5 RESERVED 0 31 regBIFPLR6_1_LINK_CNTL_16GT 0 0x3fff7bfc3d06 1 0 5 RESERVED 0 31 regBIFPLR6_1_LINK_STATUS_16GT 0 0x3fff7bfc3d07 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3d08 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3d09 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfc3d0a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfc3d0f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfc3d10 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_MARGINING_PORT_CAP 0 0x3fff7bfc3d11 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIFPLR6_1_MARGINING_PORT_STATUS 0 0x3fff7bfc3d11 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIFPLR6_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfc3d12 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfc3d12 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfc3d13 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfc3d13 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfc3d14 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfc3d14 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfc3d15 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfc3d15 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfc3d16 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfc3d16 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfc3d17 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfc3d17 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfc3d18 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfc3d18 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfc3d19 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfc3d19 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfc3d1f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfc3d1f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfc3d20 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfc3d20 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfc3d21 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIFPLR6_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfc3d21 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIFPLR6_1_PCIE_CCIX_CAP_LIST 0 0x3fff7bfc3d22 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIFPLR6_1_PCIE_CCIX_HEADER_1 0 0x3fff7bfc3d23 3 0 5 CCIX_VENDOR_ID 0 15 CCIX_CAP_REV 16 19 CCIX_CAP_LEN 20 31 regBIFPLR6_1_PCIE_CCIX_HEADER_2 0 0x3fff7bfc3d24 1 0 5 CAP_ID 0 15 regBIFPLR6_1_PCIE_CCIX_CAP 0 0x3fff7bfc3d24 5 0 5 ESM_MODE_SUPPORTED 0 0 ESM_PHY_REACH_LENGTH_CAPABILITY 1 2 ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE 3 3 ESM_CALIBRATION_TIME 4 6 ESM_QUICK_EQUALIZATION_TIMEOUT 8 10 regBIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP 0 0x3fff7bfc3d25 6 0 5 ESM_SUPPORT_2P5GT 0 0 ESM_SUPPORT_5GT 1 1 ESM_SUPPORT_8GT 2 2 ESM_SUPPORT_16GT 5 5 ESM_SUPPORT_20GT 9 9 ESM_SUPPORT_25GT 14 14 regBIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP 0 0x3fff7bfc3d26 1 0 5 RESERVED 0 31 regBIFPLR6_1_PCIE_CCIX_ESM_STATUS 0 0x3fff7bfc3d27 2 0 5 ESM_CURRENT_DATA_RATE 0 6 ESM_CALIBRATION_COMPLETE 7 7 regBIFPLR6_1_PCIE_CCIX_ESM_CNTL 0 0x3fff7bfc3d28 9 0 5 ESM_DATA_RATE0 0 6 ESM_PERFORM_CALIBRATION 7 7 ESM_DATA_RATE1 8 14 ESM_ENABLE 15 15 ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT 16 18 ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT 20 22 LINK_REACH_TARGET 24 24 RETIMER_PRESENT 25 25 ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT 26 28 regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d29 2 0 5 ESM_LANE_0_DSP_20GT_TX_PRESET 0 3 ESM_LANE_0_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d29 2 0 5 ESM_LANE_1_DSP_20GT_TX_PRESET 0 3 ESM_LANE_1_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d29 2 0 5 ESM_LANE_2_DSP_20GT_TX_PRESET 0 3 ESM_LANE_2_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d29 2 0 5 ESM_LANE_3_DSP_20GT_TX_PRESET 0 3 ESM_LANE_3_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2a 2 0 5 ESM_LANE_4_DSP_20GT_TX_PRESET 0 3 ESM_LANE_4_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2a 2 0 5 ESM_LANE_5_DSP_20GT_TX_PRESET 0 3 ESM_LANE_5_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2a 2 0 5 ESM_LANE_6_DSP_20GT_TX_PRESET 0 3 ESM_LANE_6_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2a 2 0 5 ESM_LANE_7_DSP_20GT_TX_PRESET 0 3 ESM_LANE_7_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2b 2 0 5 ESM_LANE_8_DSP_20GT_TX_PRESET 0 3 ESM_LANE_8_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2b 2 0 5 ESM_LANE_9_DSP_20GT_TX_PRESET 0 3 ESM_LANE_9_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2b 2 0 5 ESM_LANE_10_DSP_20GT_TX_PRESET 0 3 ESM_LANE_10_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2b 2 0 5 ESM_LANE_11_DSP_20GT_TX_PRESET 0 3 ESM_LANE_11_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2c 2 0 5 ESM_LANE_12_DSP_20GT_TX_PRESET 0 3 ESM_LANE_12_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2c 2 0 5 ESM_LANE_13_DSP_20GT_TX_PRESET 0 3 ESM_LANE_13_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2c 2 0 5 ESM_LANE_14_DSP_20GT_TX_PRESET 0 3 ESM_LANE_14_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0 0x3fff7bfc3d2c 2 0 5 ESM_LANE_15_DSP_20GT_TX_PRESET 0 3 ESM_LANE_15_USP_20GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2d 2 0 5 ESM_LANE_0_DSP_25GT_TX_PRESET 0 3 ESM_LANE_0_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2d 2 0 5 ESM_LANE_1_DSP_25GT_TX_PRESET 0 3 ESM_LANE_1_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2d 2 0 5 ESM_LANE_2_DSP_25GT_TX_PRESET 0 3 ESM_LANE_2_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2d 2 0 5 ESM_LANE_3_DSP_25GT_TX_PRESET 0 3 ESM_LANE_3_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2e 2 0 5 ESM_LANE_4_DSP_25GT_TX_PRESET 0 3 ESM_LANE_4_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2e 2 0 5 ESM_LANE_5_DSP_25GT_TX_PRESET 0 3 ESM_LANE_5_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2e 2 0 5 ESM_LANE_6_DSP_25GT_TX_PRESET 0 3 ESM_LANE_6_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2e 2 0 5 ESM_LANE_7_DSP_25GT_TX_PRESET 0 3 ESM_LANE_7_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2f 2 0 5 ESM_LANE_8_DSP_25GT_TX_PRESET 0 3 ESM_LANE_8_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2f 2 0 5 ESM_LANE_9_DSP_25GT_TX_PRESET 0 3 ESM_LANE_9_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2f 2 0 5 ESM_LANE_10_DSP_25GT_TX_PRESET 0 3 ESM_LANE_10_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d2f 2 0 5 ESM_LANE_11_DSP_25GT_TX_PRESET 0 3 ESM_LANE_11_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d30 2 0 5 ESM_LANE_12_DSP_25GT_TX_PRESET 0 3 ESM_LANE_12_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d30 2 0 5 ESM_LANE_13_DSP_25GT_TX_PRESET 0 3 ESM_LANE_13_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d30 2 0 5 ESM_LANE_14_DSP_25GT_TX_PRESET 0 3 ESM_LANE_14_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0 0x3fff7bfc3d30 2 0 5 ESM_LANE_15_DSP_25GT_TX_PRESET 0 3 ESM_LANE_15_USP_25GT_TX_PRESET 4 7 regBIFPLR6_1_PCIE_CCIX_TRANS_CAP 0 0x3fff7bfc3d31 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT 0 0 regBIFPLR6_1_PCIE_CCIX_TRANS_CNTL 0 0x3fff7bfc3d32 1 0 5 CCIX_OPTIMIZED_TLP_FORMAT_ENABLE 0 0 regBIF_CFG_DEV0_RC1_VENDOR_ID 0 0x3fff7bfd0400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_RC1_DEVICE_ID 0 0x3fff7bfd0400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_RC1_COMMAND 0 0x3fff7bfd0401 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_RC1_STATUS 0 0x3fff7bfd0401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_RC1_REVISION_ID 0 0x3fff7bfd0402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_RC1_PROG_INTERFACE 0 0x3fff7bfd0402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_RC1_SUB_CLASS 0 0x3fff7bfd0402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_RC1_BASE_CLASS 0 0x3fff7bfd0402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_RC1_CACHE_LINE 0 0x3fff7bfd0403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_RC1_LATENCY 0 0x3fff7bfd0403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_RC1_HEADER 0 0x3fff7bfd0403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_RC1_BIST 0 0x3fff7bfd0403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_RC1_BASE_ADDR_1 0 0x3fff7bfd0404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC1_BASE_ADDR_2 0 0x3fff7bfd0405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfd0406 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT 0 0x3fff7bfd0407 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV0_RC1_SECONDARY_STATUS 0 0x3fff7bfd0407 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT 0 0x3fff7bfd0408 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT 0 0x3fff7bfd0409 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV0_RC1_PREF_BASE_UPPER 0 0x3fff7bfd040a 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER 0 0x3fff7bfd040b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI 0 0x3fff7bfd040c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV0_RC1_CAP_PTR 0 0x3fff7bfd040d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_RC1_ROM_BASE_ADDR 0 0x3fff7bfd040e 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_RC1_INTERRUPT_LINE 0 0x3fff7bfd040f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_RC1_INTERRUPT_PIN 0 0x3fff7bfd040f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL 0 0x3fff7bfd040f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL 0 0x3fff7bfd0410 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV0_RC1_PMI_CAP_LIST 0 0x3fff7bfd0414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC1_PMI_CAP 0 0x3fff7bfd0414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL 0 0x3fff7bfd0415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_RC1_PCIE_CAP_LIST 0 0x3fff7bfd0416 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC1_PCIE_CAP 0 0x3fff7bfd0416 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_RC1_DEVICE_CAP 0 0x3fff7bfd0417 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_RC1_DEVICE_CNTL 0 0x3fff7bfd0418 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV0_RC1_DEVICE_STATUS 0 0x3fff7bfd0418 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_RC1_LINK_CAP 0 0x3fff7bfd0419 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_RC1_LINK_CNTL 0 0x3fff7bfd041a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_RC1_LINK_STATUS 0 0x3fff7bfd041a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_RC1_SLOT_CAP 0 0x3fff7bfd041b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV0_RC1_SLOT_CNTL 0 0x3fff7bfd041c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV0_RC1_SLOT_STATUS 0 0x3fff7bfd041c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV0_RC1_ROOT_CNTL 0 0x3fff7bfd041d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV0_RC1_ROOT_CAP 0 0x3fff7bfd041d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV0_RC1_ROOT_STATUS 0 0x3fff7bfd041e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV0_RC1_DEVICE_CAP2 0 0x3fff7bfd041f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_RC1_DEVICE_CNTL2 0 0x3fff7bfd0420 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_RC1_DEVICE_STATUS2 0 0x3fff7bfd0420 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC1_LINK_CAP2 0 0x3fff7bfd0421 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_RC1_LINK_CNTL2 0 0x3fff7bfd0422 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_RC1_LINK_STATUS2 0 0x3fff7bfd0422 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_RC1_SLOT_CAP2 0 0x3fff7bfd0423 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC1_SLOT_CNTL2 0 0x3fff7bfd0424 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC1_SLOT_STATUS2 0 0x3fff7bfd0424 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_RC1_MSI_CAP_LIST 0 0x3fff7bfd0428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC1_MSI_MSG_CNTL 0 0x3fff7bfd0428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO 0 0x3fff7bfd0429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI 0 0x3fff7bfd042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_RC1_MSI_MSG_DATA 0 0x3fff7bfd042a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA 0 0x3fff7bfd042a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64 0 0x3fff7bfd042b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64 0 0x3fff7bfd042b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_RC1_SSID_CAP_LIST 0 0x3fff7bfd0430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC1_SSID_CAP 0 0x3fff7bfd0431 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST 0 0x3fff7bfd0432 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_RC1_MSI_MAP_CAP 0 0x3fff7bfd0432 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfd0440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfd0441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfd0442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfd0443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfd0444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfd0445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfd0446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL 0 0x3fff7bfd0447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS 0 0x3fff7bfd0447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfd0448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfd0449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfd044a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfd044b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfd044c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfd044d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfd0450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfd0451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfd0452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfd0454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfd0455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfd0456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfd0457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfd0458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK 0 0x3fff7bfd0459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfd045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0 0 0x3fff7bfd045b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1 0 0x3fff7bfd045c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2 0 0x3fff7bfd045d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3 0 0x3fff7bfd045e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfd045f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfd0460 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID 0 0x3fff7bfd0461 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfd0462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfd0463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfd0464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfd0465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfd049c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3 0 0x3fff7bfd049d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfd049e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfd049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfd049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfd04a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfd04a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfd04a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfd04a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfd04a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfd04a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfd04a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfd04a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfd04a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfd04a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfd04a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfd04a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfd04a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfd04a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfd04a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_PCIE_ACS_CAP 0 0x3fff7bfd04a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL 0 0x3fff7bfd04a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfd0500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfd0501 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfd0502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfd0504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_LINK_CAP_16GT 0 0x3fff7bfd0505 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC1_LINK_CNTL_16GT 0 0x3fff7bfd0506 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_RC1_LINK_STATUS_16GT 0 0x3fff7bfd0507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd050a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd050f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfd0510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_RC1_MARGINING_PORT_CAP 0 0x3fff7bfd0511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS 0 0x3fff7bfd0511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfd0512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfd0512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfd0513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfd0513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfd0514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfd0514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfd0515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfd0515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfd0516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfd0516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfd0517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfd0517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfd0518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfd0518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfd0519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfd0519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfd051a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfd051a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfd051b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfd051b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfd051c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfd051c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfd051d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfd051d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfd051e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfd051e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfd051f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfd051f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfd0520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfd0520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfd0521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfd0521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_VENDOR_ID 0 0x3fff7bfd0800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_RC1_DEVICE_ID 0 0x3fff7bfd0800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_RC1_COMMAND 0 0x3fff7bfd0801 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_RC1_STATUS 0 0x3fff7bfd0801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_RC1_REVISION_ID 0 0x3fff7bfd0802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_RC1_PROG_INTERFACE 0 0x3fff7bfd0802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_RC1_SUB_CLASS 0 0x3fff7bfd0802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_RC1_BASE_CLASS 0 0x3fff7bfd0802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_RC1_CACHE_LINE 0 0x3fff7bfd0803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_RC1_LATENCY 0 0x3fff7bfd0803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_RC1_HEADER 0 0x3fff7bfd0803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_RC1_BIST 0 0x3fff7bfd0803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_RC1_BASE_ADDR_1 0 0x3fff7bfd0804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC1_BASE_ADDR_2 0 0x3fff7bfd0805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfd0806 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT 0 0x3fff7bfd0807 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV1_RC1_SECONDARY_STATUS 0 0x3fff7bfd0807 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT 0 0x3fff7bfd0808 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT 0 0x3fff7bfd0809 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV1_RC1_PREF_BASE_UPPER 0 0x3fff7bfd080a 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER 0 0x3fff7bfd080b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI 0 0x3fff7bfd080c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV1_RC1_CAP_PTR 0 0x3fff7bfd080d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_RC1_ROM_BASE_ADDR 0 0x3fff7bfd080e 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_RC1_INTERRUPT_LINE 0 0x3fff7bfd080f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_RC1_INTERRUPT_PIN 0 0x3fff7bfd080f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL 0 0x3fff7bfd080f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL 0 0x3fff7bfd0810 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV1_RC1_PMI_CAP_LIST 0 0x3fff7bfd0814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC1_PMI_CAP 0 0x3fff7bfd0814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL 0 0x3fff7bfd0815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_RC1_PCIE_CAP_LIST 0 0x3fff7bfd0816 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC1_PCIE_CAP 0 0x3fff7bfd0816 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_RC1_DEVICE_CAP 0 0x3fff7bfd0817 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_RC1_DEVICE_CNTL 0 0x3fff7bfd0818 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV1_RC1_DEVICE_STATUS 0 0x3fff7bfd0818 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_RC1_LINK_CAP 0 0x3fff7bfd0819 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_RC1_LINK_CNTL 0 0x3fff7bfd081a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_RC1_LINK_STATUS 0 0x3fff7bfd081a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_RC1_SLOT_CAP 0 0x3fff7bfd081b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV1_RC1_SLOT_CNTL 0 0x3fff7bfd081c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV1_RC1_SLOT_STATUS 0 0x3fff7bfd081c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV1_RC1_ROOT_CNTL 0 0x3fff7bfd081d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV1_RC1_ROOT_CAP 0 0x3fff7bfd081d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV1_RC1_ROOT_STATUS 0 0x3fff7bfd081e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV1_RC1_DEVICE_CAP2 0 0x3fff7bfd081f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_RC1_DEVICE_CNTL2 0 0x3fff7bfd0820 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_RC1_DEVICE_STATUS2 0 0x3fff7bfd0820 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC1_LINK_CAP2 0 0x3fff7bfd0821 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_RC1_LINK_CNTL2 0 0x3fff7bfd0822 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_RC1_LINK_STATUS2 0 0x3fff7bfd0822 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_RC1_SLOT_CAP2 0 0x3fff7bfd0823 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC1_SLOT_CNTL2 0 0x3fff7bfd0824 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC1_SLOT_STATUS2 0 0x3fff7bfd0824 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_RC1_MSI_CAP_LIST 0 0x3fff7bfd0828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC1_MSI_MSG_CNTL 0 0x3fff7bfd0828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO 0 0x3fff7bfd0829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI 0 0x3fff7bfd082a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_RC1_MSI_MSG_DATA 0 0x3fff7bfd082a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA 0 0x3fff7bfd082a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64 0 0x3fff7bfd082b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64 0 0x3fff7bfd082b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_RC1_SSID_CAP_LIST 0 0x3fff7bfd0830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC1_SSID_CAP 0 0x3fff7bfd0831 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST 0 0x3fff7bfd0832 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_RC1_MSI_MAP_CAP 0 0x3fff7bfd0832 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfd0840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfd0841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfd0842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfd0843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfd0844 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfd0845 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfd0846 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL 0 0x3fff7bfd0847 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS 0 0x3fff7bfd0847 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfd0848 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfd0849 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfd084a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfd084b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfd084c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfd084d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfd0850 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfd0851 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfd0852 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfd0854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfd0855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfd0856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfd0857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfd0858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK 0 0x3fff7bfd0859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfd085a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0 0 0x3fff7bfd085b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1 0 0x3fff7bfd085c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2 0 0x3fff7bfd085d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3 0 0x3fff7bfd085e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfd085f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfd0860 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID 0 0x3fff7bfd0861 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfd0862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfd0863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfd0864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfd0865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfd089c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3 0 0x3fff7bfd089d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfd089e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfd089f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfd089f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfd08a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfd08a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfd08a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfd08a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfd08a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfd08a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfd08a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfd08a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfd08a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfd08a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfd08a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfd08a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfd08a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfd08a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfd08a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_PCIE_ACS_CAP 0 0x3fff7bfd08a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL 0 0x3fff7bfd08a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfd0900 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfd0901 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfd0902 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfd0904 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_LINK_CAP_16GT 0 0x3fff7bfd0905 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC1_LINK_CNTL_16GT 0 0x3fff7bfd0906 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_RC1_LINK_STATUS_16GT 0 0x3fff7bfd0907 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0908 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0909 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd090a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd090f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfd0910 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_RC1_MARGINING_PORT_CAP 0 0x3fff7bfd0911 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS 0 0x3fff7bfd0911 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfd0912 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfd0912 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfd0913 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfd0913 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfd0914 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfd0914 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfd0915 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfd0915 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfd0916 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfd0916 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfd0917 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfd0917 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfd0918 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfd0918 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfd0919 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfd0919 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfd091a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfd091a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfd091b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfd091b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfd091c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfd091c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfd091d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfd091d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfd091e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfd091e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfd091f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfd091f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfd0920 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfd0920 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfd0921 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfd0921 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_VENDOR_ID 0 0x3fff7bfd0c00 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_RC1_DEVICE_ID 0 0x3fff7bfd0c00 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_RC1_COMMAND 0 0x3fff7bfd0c01 11 0 5 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_RC1_STATUS 0 0x3fff7bfd0c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_RC1_REVISION_ID 0 0x3fff7bfd0c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_RC1_PROG_INTERFACE 0 0x3fff7bfd0c02 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_RC1_SUB_CLASS 0 0x3fff7bfd0c02 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_RC1_BASE_CLASS 0 0x3fff7bfd0c02 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_RC1_CACHE_LINE 0 0x3fff7bfd0c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_RC1_LATENCY 0 0x3fff7bfd0c03 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_RC1_HEADER 0 0x3fff7bfd0c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_RC1_BIST 0 0x3fff7bfd0c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_RC1_BASE_ADDR_1 0 0x3fff7bfd0c04 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC1_BASE_ADDR_2 0 0x3fff7bfd0c05 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY 0 0x3fff7bfd0c06 4 0 5 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT 0 0x3fff7bfd0c07 4 0 5 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 regBIF_CFG_DEV2_RC1_SECONDARY_STATUS 0 0x3fff7bfd0c07 9 0 5 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_RC1_MEM_BASE_LIMIT 0 0x3fff7bfd0c08 4 0 5 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV2_RC1_PREF_BASE_LIMIT 0 0x3fff7bfd0c09 4 0 5 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 regBIF_CFG_DEV2_RC1_PREF_BASE_UPPER 0 0x3fff7bfd0c0a 1 0 5 PREF_BASE_UPPER 0 31 regBIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER 0 0x3fff7bfd0c0b 1 0 5 PREF_LIMIT_UPPER 0 31 regBIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI 0 0x3fff7bfd0c0c 2 0 5 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 regBIF_CFG_DEV2_RC1_CAP_PTR 0 0x3fff7bfd0c0d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_RC1_ROM_BASE_ADDR 0 0x3fff7bfd0c0e 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_RC1_INTERRUPT_LINE 0 0x3fff7bfd0c0f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_RC1_INTERRUPT_PIN 0 0x3fff7bfd0c0f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL 0 0x3fff7bfd0c0f 12 0 5 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 PRIMARY_DISCARD_TIMER 8 8 SECONDARY_DISCARD_TIMER 9 9 DISCARD_TIMER_STATUS 10 10 DISCARD_TIMER_SERR_ENABLE 11 11 regBIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL 0 0x3fff7bfd0c10 1 0 5 IO_PORT_80_EN 0 0 regBIF_CFG_DEV2_RC1_PMI_CAP_LIST 0 0x3fff7bfd0c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC1_PMI_CAP 0 0x3fff7bfd0c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_RC1_PMI_STATUS_CNTL 0 0x3fff7bfd0c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_RC1_PCIE_CAP_LIST 0 0x3fff7bfd0c16 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC1_PCIE_CAP 0 0x3fff7bfd0c16 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_RC1_DEVICE_CAP 0 0x3fff7bfd0c17 7 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_RC1_DEVICE_CNTL 0 0x3fff7bfd0c18 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 regBIF_CFG_DEV2_RC1_DEVICE_STATUS 0 0x3fff7bfd0c18 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_RC1_LINK_CAP 0 0x3fff7bfd0c19 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_RC1_LINK_CNTL 0 0x3fff7bfd0c1a 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_RC1_LINK_STATUS 0 0x3fff7bfd0c1a 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_RC1_SLOT_CAP 0 0x3fff7bfd0c1b 12 0 5 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 regBIF_CFG_DEV2_RC1_SLOT_CNTL 0 0x3fff7bfd0c1c 12 0 5 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 AUTO_SLOT_PWR_LIMIT_DISABLE 13 13 regBIF_CFG_DEV2_RC1_SLOT_STATUS 0 0x3fff7bfd0c1c 9 0 5 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 regBIF_CFG_DEV2_RC1_ROOT_CNTL 0 0x3fff7bfd0c1d 5 0 5 SERR_ON_CORR_ERR_EN 0 0 SERR_ON_NONFATAL_ERR_EN 1 1 SERR_ON_FATAL_ERR_EN 2 2 PM_INTERRUPT_EN 3 3 CRS_SOFTWARE_VISIBILITY_EN 4 4 regBIF_CFG_DEV2_RC1_ROOT_CAP 0 0x3fff7bfd0c1d 1 0 5 CRS_SOFTWARE_VISIBILITY 0 0 regBIF_CFG_DEV2_RC1_ROOT_STATUS 0 0x3fff7bfd0c1e 3 0 5 PME_REQUESTOR_ID 0 15 PME_STATUS 16 16 PME_PENDING 17 17 regBIF_CFG_DEV2_RC1_DEVICE_CAP2 0 0x3fff7bfd0c1f 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_RC1_DEVICE_CNTL2 0 0x3fff7bfd0c20 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_RC1_DEVICE_STATUS2 0 0x3fff7bfd0c20 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC1_LINK_CAP2 0 0x3fff7bfd0c21 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_RC1_LINK_CNTL2 0 0x3fff7bfd0c22 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_RC1_LINK_STATUS2 0 0x3fff7bfd0c22 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_RC1_SLOT_CAP2 0 0x3fff7bfd0c23 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC1_SLOT_CNTL2 0 0x3fff7bfd0c24 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC1_SLOT_STATUS2 0 0x3fff7bfd0c24 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_RC1_MSI_CAP_LIST 0 0x3fff7bfd0c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC1_MSI_MSG_CNTL 0 0x3fff7bfd0c28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO 0 0x3fff7bfd0c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI 0 0x3fff7bfd0c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_RC1_MSI_MSG_DATA 0 0x3fff7bfd0c2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA 0 0x3fff7bfd0c2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_RC1_MSI_MSG_DATA_64 0 0x3fff7bfd0c2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64 0 0x3fff7bfd0c2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_RC1_SSID_CAP_LIST 0 0x3fff7bfd0c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC1_SSID_CAP 0 0x3fff7bfd0c31 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST 0 0x3fff7bfd0c32 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_RC1_MSI_MAP_CAP 0 0x3fff7bfd0c32 3 0 5 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff7bfd0c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff7bfd0c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1 0 0x3fff7bfd0c42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2 0 0x3fff7bfd0c43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST 0 0x3fff7bfd0c44 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1 0 0x3fff7bfd0c45 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2 0 0x3fff7bfd0c46 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL 0 0x3fff7bfd0c47 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS 0 0x3fff7bfd0c47 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP 0 0x3fff7bfd0c48 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff7bfd0c49 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff7bfd0c4a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP 0 0x3fff7bfd0c4b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff7bfd0c4c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff7bfd0c4d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff7bfd0c50 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff7bfd0c51 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff7bfd0c52 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff7bfd0c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS 0 0x3fff7bfd0c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK 0 0x3fff7bfd0c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff7bfd0c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS 0 0x3fff7bfd0c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK 0 0x3fff7bfd0c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff7bfd0c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG0 0 0x3fff7bfd0c5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG1 0 0x3fff7bfd0c5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG2 0 0x3fff7bfd0c5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC1_PCIE_HDR_LOG3 0 0x3fff7bfd0c5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD 0 0x3fff7bfd0c5f 3 0 5 CORR_ERR_REP_EN 0 0 NONFATAL_ERR_REP_EN 1 1 FATAL_ERR_REP_EN 2 2 regBIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS 0 0x3fff7bfd0c60 8 0 5 ERR_CORR_RCVD 0 0 MULT_ERR_CORR_RCVD 1 1 ERR_FATAL_NONFATAL_RCVD 2 2 MULT_ERR_FATAL_NONFATAL_RCVD 3 3 FIRST_UNCORRECTABLE_FATAL 4 4 NONFATAL_ERROR_MSG_RCVD 5 5 FATAL_ERROR_MSG_RCVD 6 6 ADV_ERR_INT_MSG_NUM 27 31 regBIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID 0 0x3fff7bfd0c61 2 0 5 ERR_CORR_SRC_ID 0 15 ERR_FATAL_NONFATAL_SRC_ID 16 31 regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0 0 0x3fff7bfd0c62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1 0 0x3fff7bfd0c63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2 0 0x3fff7bfd0c64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3 0 0x3fff7bfd0c65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff7bfd0c9c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3 0 0x3fff7bfd0c9d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS 0 0x3fff7bfd0c9e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff7bfd0c9f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff7bfd0c9f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff7bfd0ca0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff7bfd0ca0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff7bfd0ca1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff7bfd0ca1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff7bfd0ca2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff7bfd0ca2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff7bfd0ca3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff7bfd0ca3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff7bfd0ca4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff7bfd0ca4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff7bfd0ca5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff7bfd0ca5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff7bfd0ca6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff7bfd0ca6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff7bfd0ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_PCIE_ACS_CAP 0 0x3fff7bfd0ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_RC1_PCIE_ACS_CNTL 0 0x3fff7bfd0ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff7bfd0d00 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP 0 0x3fff7bfd0d01 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS 0 0x3fff7bfd0d02 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff7bfd0d04 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_LINK_CAP_16GT 0 0x3fff7bfd0d05 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC1_LINK_CNTL_16GT 0 0x3fff7bfd0d06 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_RC1_LINK_STATUS_16GT 0 0x3fff7bfd0d07 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0d08 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0d09 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff7bfd0d0a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff7bfd0d0f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff7bfd0d10 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_RC1_MARGINING_PORT_CAP 0 0x3fff7bfd0d11 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS 0 0x3fff7bfd0d11 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff7bfd0d12 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff7bfd0d12 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff7bfd0d13 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff7bfd0d13 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff7bfd0d14 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff7bfd0d14 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff7bfd0d15 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff7bfd0d15 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff7bfd0d16 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff7bfd0d16 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff7bfd0d17 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff7bfd0d17 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff7bfd0d18 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff7bfd0d18 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff7bfd0d19 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff7bfd0d19 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff7bfd0d1f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff7bfd0d1f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff7bfd0d20 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff7bfd0d20 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff7bfd0d21 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff7bfd0d21 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0 0x3fff80800000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0 0x3fff80800000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF0_1_COMMAND 0 0x3fff80800001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF0_1_STATUS 0 0x3fff80800001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF0_1_REVISION_ID 0 0x3fff80800002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0 0x3fff80800002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0 0x3fff80800002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0 0x3fff80800002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0 0x3fff80800003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF0_1_LATENCY 0 0x3fff80800003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF0_1_HEADER 0 0x3fff80800003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF0_1_BIST 0 0x3fff80800003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0 0x3fff80800004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0 0x3fff80800005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0 0x3fff80800006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0 0x3fff80800007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0 0x3fff80800008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0 0x3fff80800009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0 0x3fff8080000a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0 0x3fff8080000b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0 0x3fff8080000c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_CAP_PTR 0 0x3fff8080000d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0 0x3fff8080000f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0 0x3fff8080000f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0 0x3fff8080000f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0 0x3fff8080000f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0 0x3fff80800012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0 0x3fff80800013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0 0x3fff80800014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_1_PMI_CAP 0 0x3fff80800014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0 0x3fff80800015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0 0x3fff80800019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0 0x3fff80800019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0 0x3fff8080001a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0 0x3fff8080001b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0 0x3fff8080001b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF0_1_LINK_CAP 0 0x3fff8080001c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0 0x3fff8080001d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0 0x3fff8080001d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0 0x3fff80800022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0 0x3fff80800023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0 0x3fff80800023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0 0x3fff80800024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0 0x3fff80800025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0 0x3fff80800025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0 0x3fff80800028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0 0x3fff80800028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0 0x3fff80800029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0 0x3fff8080002a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0 0x3fff8080002a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA 0 0x3fff8080002a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF0_1_MSI_MASK 0 0x3fff8080002b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0 0x3fff8080002b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080002b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0 0x3fff8080002c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0 0x3fff8080002c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0 0x3fff8080002d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0 0x3fff80800030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0 0x3fff80800030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0 0x3fff80800031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0 0x3fff80800032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80800040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80800041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80800042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80800043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff80800044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff80800045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff80800046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0 0x3fff80800047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0 0x3fff80800047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff80800048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff80800049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff8080004a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff8080004b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff8080004c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff8080004d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff80800050 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff80800051 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff80800052 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80800054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80800055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80800056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80800057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0 0x3fff80800058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0 0x3fff80800059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080005a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0 0x3fff8080005b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0 0x3fff8080005c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0 0x3fff8080005d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0 0x3fff8080005e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80800062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80800063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80800064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80800065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80800080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0 0x3fff80800081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0 0x3fff80800082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0 0x3fff80800083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0 0x3fff80800084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0 0x3fff80800085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0 0x3fff80800086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0 0x3fff80800087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0 0x3fff80800088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0 0x3fff80800089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0 0x3fff8080008a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0 0x3fff8080008b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0 0x3fff8080008c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80800090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80800091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80800092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80800093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80800094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0 0x3fff80800095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80800096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0 0x3fff80800097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0 0x3fff80800097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80800098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80800098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80800098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80800098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80800099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80800099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80800099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80800099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff8080009c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0 0x3fff8080009d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0 0x3fff8080009e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff8080009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff8080009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff808000a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff808000a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff808000a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff808000a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff808000a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff808000a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff808000a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff808000a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff808000a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff808000a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff808000a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff808000a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff808000a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff808000a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808000a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0 0x3fff808000a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0 0x3fff808000a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST 0 0x3fff808000ac 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP 0 0x3fff808000ad 3 0 5 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 regBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL 0 0x3fff808000ad 2 0 5 STU 0 4 ATC_ENABLE 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0 0x3fff808000b0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL 0 0x3fff808000b1 2 0 5 PRI_ENABLE 0 0 PRI_RESET 1 1 regBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS 0 0x3fff808000b1 4 0 5 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0x3fff808000b2 1 0 5 OUTSTAND_PAGE_REQ_CAPACITY 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0x3fff808000b3 1 0 5 OUTSTAND_PAGE_REQ_ALLOC 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808000b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0 0x3fff808000b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0 0x3fff808000b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff808000bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0 0x3fff808000bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0 0x3fff808000bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0 0x3fff808000be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0 0x3fff808000bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0 0x3fff808000c0 1 0 5 MC_RECEIVE_0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0 0x3fff808000c1 1 0 5 MC_RECEIVE_1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0 0x3fff808000c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0 0x3fff808000c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff808000c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff808000c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0 0x3fff808000c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0 0x3fff808000c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808000ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0 0x3fff808000cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0 0x3fff808000cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0 0x3fff808000cc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0 0x3fff808000cd 4 0 5 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0 0x3fff808000ce 6 0 5 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0 0x3fff808000ce 1 0 5 SRIOV_VF_MIGRATION_STATUS 0 0 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0 0x3fff808000cf 1 0 5 SRIOV_INITIAL_VFS 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0 0x3fff808000cf 1 0 5 SRIOV_TOTAL_VFS 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0 0x3fff808000d0 1 0 5 SRIOV_NUM_VFS 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0 0x3fff808000d0 1 0 5 SRIOV_FUNC_DEP_LINK 0 7 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0 0x3fff808000d1 1 0 5 SRIOV_FIRST_VF_OFFSET 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0 0x3fff808000d1 1 0 5 SRIOV_VF_STRIDE 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0 0x3fff808000d2 1 0 5 SRIOV_VF_DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0 0x3fff808000d3 1 0 5 SRIOV_SUPPORTED_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0 0x3fff808000d4 1 0 5 SRIOV_SYSTEM_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0 0x3fff808000d5 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0 0x3fff808000d6 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0 0x3fff808000d7 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0 0x3fff808000d8 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0 0x3fff808000d9 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0 0x3fff808000da 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0x3fff808000db 2 0 5 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808000dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP 0 0x3fff808000dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL 0 0x3fff808000de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff80800100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0 0x3fff80800101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0 0x3fff80800102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff80800104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0 0x3fff80800105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0 0x3fff80800106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0 0x3fff80800107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80800108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80800109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff8080010a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff8080010c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff8080010c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff8080010c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff8080010c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff8080010d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff8080010d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff8080010d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff8080010d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff8080010e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff8080010e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff8080010e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff8080010e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff8080010f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff8080010f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff8080010f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff8080010f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff80800110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0 0x3fff80800111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0 0x3fff80800111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff80800112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff80800112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff80800113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff80800113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff80800114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff80800114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff80800115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff80800115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff80800116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff80800116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff80800117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff80800117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff80800118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff80800118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff80800119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff80800119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff8080011a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff8080011a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff8080011b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff8080011b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff8080011c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff8080011c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff8080011d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff8080011d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff8080011e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff8080011e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff8080011f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff8080011f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff80800120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff80800120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff80800121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff80800121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0 0x3fff80800130 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0 0x3fff80800131 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0 0x3fff80800132 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0 0x3fff80800133 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0 0x3fff80800134 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0 0x3fff80800135 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0 0x3fff80800136 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0 0x3fff80800137 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0 0x3fff80800138 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0 0x3fff80800139 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0 0x3fff8080013a 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0 0x3fff8080013b 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0 0x3fff8080013c 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0 0x3fff80800140 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0 0x3fff80800141 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0 0x3fff80800142 2 0 5 VF_EN 0 0 VF_NUM 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0 0x3fff80800143 18 0 5 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0 0x3fff80800144 18 0 5 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0 0x3fff80800145 1 0 5 SOFT_PF_FLR 0 0 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0 0x3fff80800146 5 0 5 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0 0x3fff80800147 32 0 5 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0 0x3fff80800148 32 0 5 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0 0x3fff80800149 3 0 5 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0 0x3fff8080014a 2 0 5 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0 0x3fff8080014b 3 0 5 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0 0x3fff8080014c 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0 0x3fff8080014d 2 0 5 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0 0x3fff8080014e 2 0 5 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0 0x3fff8080014f 2 0 5 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0 0x3fff80800150 2 0 5 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0 0x3fff80800151 2 0 5 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0 0x3fff80800152 2 0 5 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0 0x3fff80800153 2 0 5 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0 0x3fff80800154 2 0 5 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0 0x3fff80800155 2 0 5 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0 0x3fff80800156 2 0 5 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0 0x3fff80800157 2 0 5 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0 0x3fff80800158 2 0 5 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0 0x3fff80800159 2 0 5 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0 0x3fff8080015a 2 0 5 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0 0x3fff8080015b 2 0 5 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0 0x3fff8080015c 2 0 5 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0 0x3fff8080015d 2 0 5 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0 0x3fff8080015e 2 0 5 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0 0x3fff8080015f 2 0 5 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0 0x3fff80800160 2 0 5 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0 0x3fff80800161 2 0 5 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0 0x3fff80800162 2 0 5 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0 0x3fff80800163 2 0 5 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0 0x3fff80800164 2 0 5 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0 0x3fff80800165 2 0 5 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0 0x3fff80800166 2 0 5 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0 0x3fff80800167 2 0 5 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0 0x3fff80800168 2 0 5 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0 0x3fff80800169 2 0 5 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0 0x3fff8080016a 2 0 5 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0 0x3fff8080016b 2 0 5 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0 0x3fff8080016c 2 0 5 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0 0x3fff80800170 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0 0x3fff80800171 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0 0x3fff80800172 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0 0x3fff80800173 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0 0x3fff80800174 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0 0x3fff80800175 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0 0x3fff80800176 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0 0x3fff80800177 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0 0x3fff80800178 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0 0x3fff8080017c 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0 0x3fff8080017d 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0 0x3fff8080017e 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0 0x3fff8080017f 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0 0x3fff80800180 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0 0x3fff80800181 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0 0x3fff80800182 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0 0x3fff80800183 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0 0x3fff80800184 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0 0x3fff80800188 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0 0x3fff80800189 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0 0x3fff8080018a 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0 0x3fff8080018b 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0 0x3fff8080018c 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0 0x3fff8080018d 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0 0x3fff8080018e 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0 0x3fff8080018f 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0 0x3fff80800190 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0 0x3fff80800194 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0 0x3fff80800195 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0 0x3fff80800196 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0 0x3fff80800197 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0 0x3fff80800198 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0 0x3fff80800199 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0 0x3fff8080019a 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0 0x3fff8080019b 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0 0x3fff8080019c 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0 0x3fff80800400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0 0x3fff80800400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF1_1_COMMAND 0 0x3fff80800401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF1_1_STATUS 0 0x3fff80800401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF1_1_REVISION_ID 0 0x3fff80800402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0 0x3fff80800402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0 0x3fff80800402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0 0x3fff80800402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0 0x3fff80800403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF1_1_LATENCY 0 0x3fff80800403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF1_1_HEADER 0 0x3fff80800403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF1_1_BIST 0 0x3fff80800403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0 0x3fff80800404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0 0x3fff80800405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0 0x3fff80800406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0 0x3fff80800407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0 0x3fff80800408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0 0x3fff80800409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0 0x3fff8080040a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0 0x3fff8080040b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0 0x3fff8080040c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_CAP_PTR 0 0x3fff8080040d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0 0x3fff8080040f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0 0x3fff8080040f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0 0x3fff8080040f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0 0x3fff8080040f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0 0x3fff80800412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0 0x3fff80800413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0 0x3fff80800414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_1_PMI_CAP 0 0x3fff80800414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0 0x3fff80800415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0 0x3fff80800419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0 0x3fff80800419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0 0x3fff8080041a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0 0x3fff8080041b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0 0x3fff8080041b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF1_1_LINK_CAP 0 0x3fff8080041c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0 0x3fff8080041d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0 0x3fff8080041d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0 0x3fff80800422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0 0x3fff80800423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0 0x3fff80800423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0 0x3fff80800424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0 0x3fff80800425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0 0x3fff80800425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0 0x3fff80800428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0 0x3fff80800428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0 0x3fff80800429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0 0x3fff8080042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0 0x3fff8080042a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA 0 0x3fff8080042a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF1_1_MSI_MASK 0 0x3fff8080042b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0 0x3fff8080042b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080042b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0 0x3fff8080042c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0 0x3fff8080042c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0 0x3fff8080042d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0 0x3fff80800430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0 0x3fff80800430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0 0x3fff80800431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0 0x3fff80800432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80800440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80800441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80800442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80800443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff80800444 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff80800445 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff80800446 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL 0 0x3fff80800447 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS 0 0x3fff80800447 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff80800448 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff80800449 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff8080044a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff8080044b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff8080044c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff8080044d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0 0x3fff80800450 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0 0x3fff80800451 1 0 5 SERIAL_NUMBER_LO 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0 0x3fff80800452 1 0 5 SERIAL_NUMBER_HI 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80800454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80800455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80800456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80800457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0 0x3fff80800458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0 0x3fff80800459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0 0x3fff8080045b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0 0x3fff8080045c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0 0x3fff8080045d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0 0x3fff8080045e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80800462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80800463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80800464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80800465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80800480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0 0x3fff80800481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0 0x3fff80800482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0 0x3fff80800483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0 0x3fff80800484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0 0x3fff80800485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0 0x3fff80800486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0 0x3fff80800487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0 0x3fff80800488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0 0x3fff80800489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0 0x3fff8080048a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0 0x3fff8080048b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0 0x3fff8080048c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80800490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80800491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80800492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80800493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80800494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0 0x3fff80800495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80800496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0 0x3fff80800497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0 0x3fff80800497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80800498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80800498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80800498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80800498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80800499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80800499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80800499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80800499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff8080049c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0 0x3fff8080049d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0 0x3fff8080049e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff8080049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff8080049f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff808004a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff808004a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff808004a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff808004a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff808004a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff808004a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff808004a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff808004a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff808004a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff808004a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff808004a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff808004a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff808004a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff808004a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808004a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0 0x3fff808004a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0 0x3fff808004a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST 0 0x3fff808004ac 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP 0 0x3fff808004ad 3 0 5 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 regBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL 0 0x3fff808004ad 2 0 5 STU 0 4 ATC_ENABLE 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0 0x3fff808004b0 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL 0 0x3fff808004b1 2 0 5 PRI_ENABLE 0 0 PRI_RESET 1 1 regBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS 0 0x3fff808004b1 4 0 5 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0 0x3fff808004b2 1 0 5 OUTSTAND_PAGE_REQ_CAPACITY 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0 0x3fff808004b3 1 0 5 OUTSTAND_PAGE_REQ_ALLOC 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808004b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0 0x3fff808004b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0 0x3fff808004b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0 0x3fff808004bc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0 0x3fff808004bd 3 0 5 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0 0x3fff808004bd 2 0 5 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0 0x3fff808004be 2 0 5 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0 0x3fff808004bf 1 0 5 MC_BASE_ADDR_1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0 0x3fff808004c0 1 0 5 MC_RECEIVE_0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0 0x3fff808004c1 1 0 5 MC_RECEIVE_1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0 0x3fff808004c2 1 0 5 MC_BLOCK_ALL_0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0 0x3fff808004c3 1 0 5 MC_BLOCK_ALL_1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0 0x3fff808004c4 1 0 5 MC_BLOCK_UNTRANSLATED_0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0 0x3fff808004c5 1 0 5 MC_BLOCK_UNTRANSLATED_1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0 0x3fff808004c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0 0x3fff808004c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808004ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0 0x3fff808004cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0 0x3fff808004cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0 0x3fff808004cc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0 0x3fff808004cd 4 0 5 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0 0x3fff808004ce 6 0 5 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0 0x3fff808004ce 1 0 5 SRIOV_VF_MIGRATION_STATUS 0 0 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0 0x3fff808004cf 1 0 5 SRIOV_INITIAL_VFS 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0 0x3fff808004cf 1 0 5 SRIOV_TOTAL_VFS 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0 0x3fff808004d0 1 0 5 SRIOV_NUM_VFS 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0 0x3fff808004d0 1 0 5 SRIOV_FUNC_DEP_LINK 0 7 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0 0x3fff808004d1 1 0 5 SRIOV_FIRST_VF_OFFSET 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0 0x3fff808004d1 1 0 5 SRIOV_VF_STRIDE 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0 0x3fff808004d2 1 0 5 SRIOV_VF_DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0 0x3fff808004d3 1 0 5 SRIOV_SUPPORTED_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0 0x3fff808004d4 1 0 5 SRIOV_SYSTEM_PAGE_SIZE 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0 0x3fff808004d5 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0 0x3fff808004d6 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0 0x3fff808004d7 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0 0x3fff808004d8 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0 0x3fff808004d9 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0 0x3fff808004da 1 0 5 VF_BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0 0x3fff808004db 2 0 5 SRIOV_VF_MIGRATION_STATE_BIR 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808004dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP 0 0x3fff808004dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL 0 0x3fff808004de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff80800500 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP 0 0x3fff80800501 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS 0 0x3fff80800502 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff80800504 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT 0 0x3fff80800505 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT 0 0x3fff80800506 1 0 5 RESERVED 0 31 regBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT 0 0x3fff80800507 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80800508 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80800509 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff8080050a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff8080050c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff8080050c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff8080050c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff8080050c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff8080050d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff8080050d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff8080050d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff8080050d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff8080050e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff8080050e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff8080050e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff8080050e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff8080050f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff8080050f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff8080050f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff8080050f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff80800510 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP 0 0x3fff80800511 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS 0 0x3fff80800511 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff80800512 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff80800512 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff80800513 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff80800513 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff80800514 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff80800514 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff80800515 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff80800515 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff80800516 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff80800516 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff80800517 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff80800517 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff80800518 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff80800518 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff80800519 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff80800519 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff8080051a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff8080051a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff8080051b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff8080051b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff8080051c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff8080051c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff8080051d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff8080051d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff8080051e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff8080051e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff8080051f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff8080051f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff80800520 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff80800520 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff80800521 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff80800521 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0 0x3fff80800530 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0 0x3fff80800531 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0 0x3fff80800532 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0 0x3fff80800533 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0 0x3fff80800534 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0 0x3fff80800535 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0 0x3fff80800536 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0 0x3fff80800537 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0 0x3fff80800538 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0 0x3fff80800539 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0 0x3fff8080053a 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0 0x3fff8080053b 1 0 5 VF_BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0 0x3fff8080053c 4 0 5 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 VF_BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0 0x3fff80800540 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0 0x3fff80800541 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0 0x3fff80800542 2 0 5 VF_EN 0 0 VF_NUM 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0 0x3fff80800543 18 0 5 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0 0x3fff80800544 18 0 5 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0 0x3fff80800545 1 0 5 SOFT_PF_FLR 0 0 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0 0x3fff80800546 5 0 5 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0 0x3fff80800547 32 0 5 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0 0x3fff80800548 32 0 5 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0 0x3fff80800549 3 0 5 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0 0x3fff8080054a 2 0 5 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0 0x3fff8080054b 3 0 5 VCN0SCH_OFFSET 0 7 GFXSCH_OFFSET 16 23 VCN1SCH_OFFSET 24 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0 0x3fff8080054c 2 0 5 LFB_REGION 0 2 MAX_REGION 4 6 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0 0x3fff8080054d 2 0 5 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0 0x3fff8080054e 2 0 5 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0 0x3fff8080054f 2 0 5 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0 0x3fff80800550 2 0 5 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0 0x3fff80800551 2 0 5 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0 0x3fff80800552 2 0 5 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0 0x3fff80800553 2 0 5 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0 0x3fff80800554 2 0 5 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0 0x3fff80800555 2 0 5 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0 0x3fff80800556 2 0 5 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0 0x3fff80800557 2 0 5 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0 0x3fff80800558 2 0 5 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0 0x3fff80800559 2 0 5 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0 0x3fff8080055a 2 0 5 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0 0x3fff8080055b 2 0 5 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0 0x3fff8080055c 2 0 5 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0 0x3fff8080055d 2 0 5 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0 0x3fff8080055e 2 0 5 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0 0x3fff8080055f 2 0 5 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0 0x3fff80800560 2 0 5 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0 0x3fff80800561 2 0 5 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0 0x3fff80800562 2 0 5 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0 0x3fff80800563 2 0 5 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0 0x3fff80800564 2 0 5 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0 0x3fff80800565 2 0 5 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0 0x3fff80800566 2 0 5 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0 0x3fff80800567 2 0 5 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0 0x3fff80800568 2 0 5 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0 0x3fff80800569 2 0 5 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0 0x3fff8080056a 2 0 5 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0 0x3fff8080056b 2 0 5 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0 0x3fff8080056c 2 0 5 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0 0x3fff80800570 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0 0x3fff80800571 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0 0x3fff80800572 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0 0x3fff80800573 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0 0x3fff80800574 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0 0x3fff80800575 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0 0x3fff80800576 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0 0x3fff80800577 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0 0x3fff80800578 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0 0x3fff8080057c 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0 0x3fff8080057d 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0 0x3fff8080057e 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0 0x3fff8080057f 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0 0x3fff80800580 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0 0x3fff80800581 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0 0x3fff80800582 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0 0x3fff80800583 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0 0x3fff80800584 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0 0x3fff80800588 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0 0x3fff80800589 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0 0x3fff8080058a 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0 0x3fff8080058b 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0 0x3fff8080058c 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0 0x3fff8080058d 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0 0x3fff8080058e 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0 0x3fff8080058f 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0 0x3fff80800590 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0 0x3fff80800594 1 0 5 DW0 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0 0x3fff80800595 1 0 5 DW1 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0 0x3fff80800596 1 0 5 DW2 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0 0x3fff80800597 1 0 5 DW3 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0 0x3fff80800598 1 0 5 DW4 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0 0x3fff80800599 1 0 5 DW5 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0 0x3fff8080059a 1 0 5 DW6 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0 0x3fff8080059b 1 0 5 DW7 0 31 regBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0 0x3fff8080059c 1 0 5 DW8 0 31 regBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0 0x3fff80800800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0 0x3fff80800800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF2_1_COMMAND 0 0x3fff80800801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF2_1_STATUS 0 0x3fff80800801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF2_1_REVISION_ID 0 0x3fff80800802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0 0x3fff80800802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0 0x3fff80800802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0 0x3fff80800802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0 0x3fff80800803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF2_1_LATENCY 0 0x3fff80800803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF2_1_HEADER 0 0x3fff80800803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF2_1_BIST 0 0x3fff80800803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0 0x3fff80800804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0 0x3fff80800805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0 0x3fff80800806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0 0x3fff80800807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0 0x3fff80800808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0 0x3fff80800809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0 0x3fff8080080a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0 0x3fff8080080b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0 0x3fff8080080c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF2_1_CAP_PTR 0 0x3fff8080080d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0 0x3fff8080080f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0 0x3fff8080080f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0 0x3fff8080080f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0 0x3fff8080080f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0 0x3fff80800812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0 0x3fff80800813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0 0x3fff80800814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_1_PMI_CAP 0 0x3fff80800814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0 0x3fff80800815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF2_1_SBRN 0 0x3fff80800818 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF2_1_FLADJ 0 0x3fff80800818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0 0x3fff80800818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0 0x3fff80800819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0 0x3fff80800819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0 0x3fff8080081a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0 0x3fff8080081b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0 0x3fff8080081b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF2_1_LINK_CAP 0 0x3fff8080081c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0 0x3fff8080081d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0 0x3fff8080081d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0 0x3fff80800822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0 0x3fff80800823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0 0x3fff80800823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0 0x3fff80800824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0 0x3fff80800825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0 0x3fff80800825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0 0x3fff80800828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0 0x3fff80800828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0 0x3fff80800829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0 0x3fff8080082a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0 0x3fff8080082a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA 0 0x3fff8080082a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF2_1_MSI_MASK 0 0x3fff8080082b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0 0x3fff8080082b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080082b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0 0x3fff8080082c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0 0x3fff8080082c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0 0x3fff8080082d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0 0x3fff80800830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0 0x3fff80800830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0 0x3fff80800831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0 0x3fff80800832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80800840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80800841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80800842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80800843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80800854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80800855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80800856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80800857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0 0x3fff80800858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0 0x3fff80800859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080085a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0 0x3fff8080085b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0 0x3fff8080085c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0 0x3fff8080085d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0 0x3fff8080085e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80800862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80800863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80800864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80800865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80800880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0 0x3fff80800881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0 0x3fff80800882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0 0x3fff80800883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0 0x3fff80800884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0 0x3fff80800885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0 0x3fff80800886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0 0x3fff80800887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0 0x3fff80800888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0 0x3fff80800889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0 0x3fff8080088a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0 0x3fff8080088b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0 0x3fff8080088c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80800890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80800891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80800892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80800893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80800894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0 0x3fff80800895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80800896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0 0x3fff80800897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0 0x3fff80800897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80800898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80800898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80800898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80800898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80800899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80800899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80800899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80800899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808008a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0 0x3fff808008a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0 0x3fff808008a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808008b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0 0x3fff808008b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0 0x3fff808008b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808008ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0 0x3fff808008cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0 0x3fff808008cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808008dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP 0 0x3fff808008dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL 0 0x3fff808008de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808008df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808008df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808008e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808008e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808008e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808008e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808008e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808008e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808008e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808008e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808008e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808008e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808008e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808008e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808008e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808008e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808008e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808008e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808008e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808008e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808008e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808008e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808008ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808008ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808008eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808008eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808008ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808008ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808008ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808008ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808008ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808008ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808008ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808008ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808008f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808008f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808008f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808008f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808008f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808008f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808008f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808008f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808008f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808008f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808008f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808008f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808008f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808008f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808008f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808008f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808008f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808008f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808008f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808008f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808008fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808008fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808008fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808008fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808008fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808008fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808008fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808008fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808008fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808008fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0 0x3fff80800c00 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0 0x3fff80800c00 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF3_1_COMMAND 0 0x3fff80800c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF3_1_STATUS 0 0x3fff80800c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF3_1_REVISION_ID 0 0x3fff80800c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0 0x3fff80800c02 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0 0x3fff80800c02 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0 0x3fff80800c02 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0 0x3fff80800c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF3_1_LATENCY 0 0x3fff80800c03 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF3_1_HEADER 0 0x3fff80800c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF3_1_BIST 0 0x3fff80800c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0 0x3fff80800c04 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0 0x3fff80800c05 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0 0x3fff80800c06 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0 0x3fff80800c07 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0 0x3fff80800c08 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0 0x3fff80800c09 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0 0x3fff80800c0a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0 0x3fff80800c0b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0 0x3fff80800c0c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF3_1_CAP_PTR 0 0x3fff80800c0d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0 0x3fff80800c0f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0 0x3fff80800c0f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0 0x3fff80800c0f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0 0x3fff80800c0f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0 0x3fff80800c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0 0x3fff80800c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0 0x3fff80800c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_1_PMI_CAP 0 0x3fff80800c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0 0x3fff80800c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF3_1_SBRN 0 0x3fff80800c18 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF3_1_FLADJ 0 0x3fff80800c18 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0 0x3fff80800c18 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0 0x3fff80800c19 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0 0x3fff80800c19 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0 0x3fff80800c1a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0 0x3fff80800c1b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0 0x3fff80800c1b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF3_1_LINK_CAP 0 0x3fff80800c1c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0 0x3fff80800c1d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0 0x3fff80800c1d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0 0x3fff80800c22 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0 0x3fff80800c23 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0 0x3fff80800c23 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0 0x3fff80800c24 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0 0x3fff80800c25 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0 0x3fff80800c25 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0 0x3fff80800c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0 0x3fff80800c28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0 0x3fff80800c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0 0x3fff80800c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0 0x3fff80800c2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA 0 0x3fff80800c2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF3_1_MSI_MASK 0 0x3fff80800c2b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0 0x3fff80800c2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64 0 0x3fff80800c2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0 0x3fff80800c2c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0 0x3fff80800c2c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0 0x3fff80800c2d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0 0x3fff80800c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0 0x3fff80800c30 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0 0x3fff80800c31 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0 0x3fff80800c32 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80800c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80800c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80800c42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80800c43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80800c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80800c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80800c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80800c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0 0x3fff80800c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0 0x3fff80800c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff80800c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0 0x3fff80800c5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0 0x3fff80800c5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0 0x3fff80800c5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0 0x3fff80800c5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80800c62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80800c63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80800c64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80800c65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80800c80 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0 0x3fff80800c81 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0 0x3fff80800c82 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0 0x3fff80800c83 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0 0x3fff80800c84 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0 0x3fff80800c85 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0 0x3fff80800c86 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0 0x3fff80800c87 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0 0x3fff80800c88 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0 0x3fff80800c89 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0 0x3fff80800c8a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0 0x3fff80800c8b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0 0x3fff80800c8c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80800c90 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80800c91 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80800c92 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80800c93 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80800c94 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0 0x3fff80800c95 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80800c96 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0 0x3fff80800c97 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0 0x3fff80800c97 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80800c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80800c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80800c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80800c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80800c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80800c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80800c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80800c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff80800ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0 0x3fff80800ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0 0x3fff80800ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff80800cb4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0 0x3fff80800cb5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0 0x3fff80800cb5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff80800cca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0 0x3fff80800ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0 0x3fff80800ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff80800cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP 0 0x3fff80800cdd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL 0 0x3fff80800cde 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0 0 0x3fff80800cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1 0 0x3fff80800cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2 0 0x3fff80800ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3 0 0x3fff80800ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4 0 0x3fff80800ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5 0 0x3fff80800ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6 0 0x3fff80800ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7 0 0x3fff80800ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8 0 0x3fff80800ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9 0 0x3fff80800ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10 0 0x3fff80800ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11 0 0x3fff80800ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12 0 0x3fff80800ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13 0 0x3fff80800ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14 0 0x3fff80800ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15 0 0x3fff80800ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16 0 0x3fff80800ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17 0 0x3fff80800ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18 0 0x3fff80800ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19 0 0x3fff80800ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20 0 0x3fff80800ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21 0 0x3fff80800ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22 0 0x3fff80800cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23 0 0x3fff80800cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24 0 0x3fff80800ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25 0 0x3fff80800ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26 0 0x3fff80800cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27 0 0x3fff80800cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28 0 0x3fff80800ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29 0 0x3fff80800ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30 0 0x3fff80800cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31 0 0x3fff80800cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32 0 0x3fff80800cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33 0 0x3fff80800cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34 0 0x3fff80800cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35 0 0x3fff80800cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36 0 0x3fff80800cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37 0 0x3fff80800cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38 0 0x3fff80800cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39 0 0x3fff80800cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40 0 0x3fff80800cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41 0 0x3fff80800cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42 0 0x3fff80800cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43 0 0x3fff80800cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44 0 0x3fff80800cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45 0 0x3fff80800cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46 0 0x3fff80800cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47 0 0x3fff80800cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48 0 0x3fff80800cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49 0 0x3fff80800cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50 0 0x3fff80800cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51 0 0x3fff80800cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52 0 0x3fff80800cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53 0 0x3fff80800cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54 0 0x3fff80800cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55 0 0x3fff80800cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56 0 0x3fff80800cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57 0 0x3fff80800cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58 0 0x3fff80800cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59 0 0x3fff80800cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60 0 0x3fff80800cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61 0 0x3fff80800cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62 0 0x3fff80800cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63 0 0x3fff80800cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_VENDOR_ID 0 0x3fff80801000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF4_1_DEVICE_ID 0 0x3fff80801000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF4_1_COMMAND 0 0x3fff80801001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF4_1_STATUS 0 0x3fff80801001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF4_1_REVISION_ID 0 0x3fff80801002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE 0 0x3fff80801002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF4_1_SUB_CLASS 0 0x3fff80801002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF4_1_BASE_CLASS 0 0x3fff80801002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF4_1_CACHE_LINE 0 0x3fff80801003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF4_1_LATENCY 0 0x3fff80801003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF4_1_HEADER 0 0x3fff80801003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF4_1_BIST 0 0x3fff80801003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1 0 0x3fff80801004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2 0 0x3fff80801005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3 0 0x3fff80801006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4 0 0x3fff80801007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5 0 0x3fff80801008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6 0 0x3fff80801009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR 0 0x3fff8080100a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID 0 0x3fff8080100b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR 0 0x3fff8080100c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF4_1_CAP_PTR 0 0x3fff8080100d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE 0 0x3fff8080100f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN 0 0x3fff8080100f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF4_1_MIN_GRANT 0 0x3fff8080100f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF4_1_MAX_LATENCY 0 0x3fff8080100f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST 0 0x3fff80801012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W 0 0x3fff80801013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST 0 0x3fff80801014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_1_PMI_CAP 0 0x3fff80801014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL 0 0x3fff80801015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF4_1_SBRN 0 0x3fff80801018 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF4_1_FLADJ 0 0x3fff80801018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD 0 0x3fff80801018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST 0 0x3fff80801019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_CAP 0 0x3fff80801019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP 0 0x3fff8080101a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL 0 0x3fff8080101b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS 0 0x3fff8080101b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF4_1_LINK_CAP 0 0x3fff8080101c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF4_1_LINK_CNTL 0 0x3fff8080101d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF4_1_LINK_STATUS 0 0x3fff8080101d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2 0 0x3fff80801022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2 0 0x3fff80801023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2 0 0x3fff80801023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF4_1_LINK_CAP2 0 0x3fff80801024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF4_1_LINK_CNTL2 0 0x3fff80801025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF4_1_LINK_STATUS2 0 0x3fff80801025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST 0 0x3fff80801028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL 0 0x3fff80801028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO 0 0x3fff80801029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI 0 0x3fff8080102a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA 0 0x3fff8080102a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA 0 0x3fff8080102a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF4_1_MSI_MASK 0 0x3fff8080102b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64 0 0x3fff8080102b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080102b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF4_1_MSI_MASK_64 0 0x3fff8080102c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF4_1_MSI_PENDING 0 0x3fff8080102c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64 0 0x3fff8080102d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST 0 0x3fff80801030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL 0 0x3fff80801030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF4_1_MSIX_TABLE 0 0x3fff80801031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF4_1_MSIX_PBA 0 0x3fff80801032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80801040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80801041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80801042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80801043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80801054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80801055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80801056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80801057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS 0 0x3fff80801058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK 0 0x3fff80801059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080105a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0 0 0x3fff8080105b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1 0 0x3fff8080105c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2 0 0x3fff8080105d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3 0 0x3fff8080105e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80801062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80801063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80801064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80801065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80801080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP 0 0x3fff80801081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL 0 0x3fff80801082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP 0 0x3fff80801083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL 0 0x3fff80801084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP 0 0x3fff80801085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL 0 0x3fff80801086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP 0 0x3fff80801087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL 0 0x3fff80801088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP 0 0x3fff80801089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL 0 0x3fff8080108a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP 0 0x3fff8080108b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL 0 0x3fff8080108c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80801090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80801091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80801092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80801093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80801094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP 0 0x3fff80801095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80801096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS 0 0x3fff80801097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL 0 0x3fff80801097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80801098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80801098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80801098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80801098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80801099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80801099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80801099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80801099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808010a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP 0 0x3fff808010a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL 0 0x3fff808010a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808010b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP 0 0x3fff808010b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL 0 0x3fff808010b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808010ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP 0 0x3fff808010cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL 0 0x3fff808010cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808010dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP 0 0x3fff808010dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL 0 0x3fff808010de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808010df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808010df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808010e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808010e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808010e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808010e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808010e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808010e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808010e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808010e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808010e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808010e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808010e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808010e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808010e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808010e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808010e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808010e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808010e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808010e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808010e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808010e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808010ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808010ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808010eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808010eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808010ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808010ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808010ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808010ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808010ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808010ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808010ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808010ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808010f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808010f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808010f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808010f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808010f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808010f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808010f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808010f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808010f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808010f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808010f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808010f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808010f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808010f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808010f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808010f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808010f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808010f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808010f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808010f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808010fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808010fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808010fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808010fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808010fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808010fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808010fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808010fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808010fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808010fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_VENDOR_ID 0 0x3fff80801400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF5_1_DEVICE_ID 0 0x3fff80801400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF5_1_COMMAND 0 0x3fff80801401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF5_1_STATUS 0 0x3fff80801401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF5_1_REVISION_ID 0 0x3fff80801402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE 0 0x3fff80801402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF5_1_SUB_CLASS 0 0x3fff80801402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF5_1_BASE_CLASS 0 0x3fff80801402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF5_1_CACHE_LINE 0 0x3fff80801403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF5_1_LATENCY 0 0x3fff80801403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF5_1_HEADER 0 0x3fff80801403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF5_1_BIST 0 0x3fff80801403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1 0 0x3fff80801404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2 0 0x3fff80801405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3 0 0x3fff80801406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4 0 0x3fff80801407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5 0 0x3fff80801408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6 0 0x3fff80801409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR 0 0x3fff8080140a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID 0 0x3fff8080140b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR 0 0x3fff8080140c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF5_1_CAP_PTR 0 0x3fff8080140d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE 0 0x3fff8080140f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN 0 0x3fff8080140f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF5_1_MIN_GRANT 0 0x3fff8080140f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF5_1_MAX_LATENCY 0 0x3fff8080140f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST 0 0x3fff80801412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W 0 0x3fff80801413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST 0 0x3fff80801414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_1_PMI_CAP 0 0x3fff80801414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL 0 0x3fff80801415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF5_1_SBRN 0 0x3fff80801418 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF5_1_FLADJ 0 0x3fff80801418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD 0 0x3fff80801418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST 0 0x3fff80801419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_CAP 0 0x3fff80801419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP 0 0x3fff8080141a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL 0 0x3fff8080141b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS 0 0x3fff8080141b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF5_1_LINK_CAP 0 0x3fff8080141c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF5_1_LINK_CNTL 0 0x3fff8080141d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF5_1_LINK_STATUS 0 0x3fff8080141d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2 0 0x3fff80801422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2 0 0x3fff80801423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2 0 0x3fff80801423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF5_1_LINK_CAP2 0 0x3fff80801424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF5_1_LINK_CNTL2 0 0x3fff80801425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF5_1_LINK_STATUS2 0 0x3fff80801425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST 0 0x3fff80801428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL 0 0x3fff80801428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO 0 0x3fff80801429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI 0 0x3fff8080142a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA 0 0x3fff8080142a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA 0 0x3fff8080142a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF5_1_MSI_MASK 0 0x3fff8080142b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64 0 0x3fff8080142b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080142b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF5_1_MSI_MASK_64 0 0x3fff8080142c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF5_1_MSI_PENDING 0 0x3fff8080142c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64 0 0x3fff8080142d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST 0 0x3fff80801430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL 0 0x3fff80801430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF5_1_MSIX_TABLE 0 0x3fff80801431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF5_1_MSIX_PBA 0 0x3fff80801432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80801440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80801441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80801442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80801443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80801454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80801455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80801456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80801457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS 0 0x3fff80801458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK 0 0x3fff80801459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080145a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0 0 0x3fff8080145b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1 0 0x3fff8080145c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2 0 0x3fff8080145d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3 0 0x3fff8080145e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80801462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80801463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80801464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80801465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80801480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP 0 0x3fff80801481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL 0 0x3fff80801482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP 0 0x3fff80801483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL 0 0x3fff80801484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP 0 0x3fff80801485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL 0 0x3fff80801486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP 0 0x3fff80801487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL 0 0x3fff80801488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP 0 0x3fff80801489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL 0 0x3fff8080148a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP 0 0x3fff8080148b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL 0 0x3fff8080148c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80801490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80801491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80801492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80801493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80801494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP 0 0x3fff80801495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80801496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS 0 0x3fff80801497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL 0 0x3fff80801497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80801498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80801498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80801498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80801498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80801499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80801499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80801499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80801499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808014a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP 0 0x3fff808014a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL 0 0x3fff808014a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808014b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP 0 0x3fff808014b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL 0 0x3fff808014b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808014ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP 0 0x3fff808014cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL 0 0x3fff808014cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808014dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP 0 0x3fff808014dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL 0 0x3fff808014de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808014df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808014df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808014e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808014e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808014e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808014e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808014e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808014e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808014e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808014e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808014e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808014e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808014e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808014e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808014e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808014e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808014e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808014e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808014e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808014e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808014e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808014e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808014ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808014ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808014eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808014eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808014ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808014ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808014ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808014ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808014ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808014ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808014ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808014ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808014f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808014f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808014f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808014f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808014f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808014f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808014f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808014f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808014f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808014f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808014f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808014f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808014f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808014f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808014f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808014f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808014f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808014f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808014f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808014f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808014fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808014fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808014fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808014fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808014fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808014fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808014fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808014fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808014fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808014fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_VENDOR_ID 0 0x3fff80801800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF6_1_DEVICE_ID 0 0x3fff80801800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF6_1_COMMAND 0 0x3fff80801801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF6_1_STATUS 0 0x3fff80801801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF6_1_REVISION_ID 0 0x3fff80801802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE 0 0x3fff80801802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF6_1_SUB_CLASS 0 0x3fff80801802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF6_1_BASE_CLASS 0 0x3fff80801802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF6_1_CACHE_LINE 0 0x3fff80801803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF6_1_LATENCY 0 0x3fff80801803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF6_1_HEADER 0 0x3fff80801803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF6_1_BIST 0 0x3fff80801803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1 0 0x3fff80801804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2 0 0x3fff80801805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3 0 0x3fff80801806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4 0 0x3fff80801807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5 0 0x3fff80801808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6 0 0x3fff80801809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR 0 0x3fff8080180a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID 0 0x3fff8080180b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR 0 0x3fff8080180c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF6_1_CAP_PTR 0 0x3fff8080180d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE 0 0x3fff8080180f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN 0 0x3fff8080180f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF6_1_MIN_GRANT 0 0x3fff8080180f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF6_1_MAX_LATENCY 0 0x3fff8080180f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST 0 0x3fff80801812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W 0 0x3fff80801813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST 0 0x3fff80801814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_1_PMI_CAP 0 0x3fff80801814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL 0 0x3fff80801815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF6_1_SBRN 0 0x3fff80801818 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF6_1_FLADJ 0 0x3fff80801818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD 0 0x3fff80801818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST 0 0x3fff80801819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_CAP 0 0x3fff80801819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP 0 0x3fff8080181a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL 0 0x3fff8080181b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS 0 0x3fff8080181b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF6_1_LINK_CAP 0 0x3fff8080181c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF6_1_LINK_CNTL 0 0x3fff8080181d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF6_1_LINK_STATUS 0 0x3fff8080181d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2 0 0x3fff80801822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2 0 0x3fff80801823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2 0 0x3fff80801823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF6_1_LINK_CAP2 0 0x3fff80801824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF6_1_LINK_CNTL2 0 0x3fff80801825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF6_1_LINK_STATUS2 0 0x3fff80801825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST 0 0x3fff80801828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL 0 0x3fff80801828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO 0 0x3fff80801829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI 0 0x3fff8080182a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA 0 0x3fff8080182a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA 0 0x3fff8080182a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF6_1_MSI_MASK 0 0x3fff8080182b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64 0 0x3fff8080182b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64 0 0x3fff8080182b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF6_1_MSI_MASK_64 0 0x3fff8080182c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF6_1_MSI_PENDING 0 0x3fff8080182c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64 0 0x3fff8080182d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST 0 0x3fff80801830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL 0 0x3fff80801830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF6_1_MSIX_TABLE 0 0x3fff80801831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF6_1_MSIX_PBA 0 0x3fff80801832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80801840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80801841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80801842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80801843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80801854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80801855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80801856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80801857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS 0 0x3fff80801858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK 0 0x3fff80801859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8080185a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0 0 0x3fff8080185b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1 0 0x3fff8080185c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2 0 0x3fff8080185d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3 0 0x3fff8080185e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80801862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80801863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80801864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80801865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80801880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP 0 0x3fff80801881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL 0 0x3fff80801882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP 0 0x3fff80801883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL 0 0x3fff80801884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP 0 0x3fff80801885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL 0 0x3fff80801886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP 0 0x3fff80801887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL 0 0x3fff80801888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP 0 0x3fff80801889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL 0 0x3fff8080188a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP 0 0x3fff8080188b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL 0 0x3fff8080188c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80801890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80801891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80801892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80801893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80801894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP 0 0x3fff80801895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80801896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS 0 0x3fff80801897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL 0 0x3fff80801897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80801898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80801898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80801898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80801898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80801899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80801899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80801899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80801899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808018a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP 0 0x3fff808018a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL 0 0x3fff808018a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808018b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP 0 0x3fff808018b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL 0 0x3fff808018b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808018ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP 0 0x3fff808018cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL 0 0x3fff808018cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808018dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP 0 0x3fff808018dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL 0 0x3fff808018de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808018df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808018df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808018e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808018e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808018e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808018e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808018e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808018e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808018e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808018e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808018e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808018e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808018e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808018e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808018e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808018e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808018e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808018e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808018e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808018e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808018e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808018e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808018ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808018ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808018eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808018eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808018ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808018ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808018ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808018ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808018ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808018ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808018ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808018ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808018f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808018f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808018f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808018f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808018f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808018f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808018f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808018f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808018f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808018f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808018f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808018f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808018f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808018f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808018f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808018f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808018f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808018f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808018f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808018f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808018fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808018fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808018fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808018fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808018fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808018fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808018fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808018fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808018fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808018fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_VENDOR_ID 0 0x3fff80801c00 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV0_EPF7_1_DEVICE_ID 0 0x3fff80801c00 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV0_EPF7_1_COMMAND 0 0x3fff80801c01 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV0_EPF7_1_STATUS 0 0x3fff80801c01 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV0_EPF7_1_REVISION_ID 0 0x3fff80801c02 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE 0 0x3fff80801c02 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV0_EPF7_1_SUB_CLASS 0 0x3fff80801c02 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV0_EPF7_1_BASE_CLASS 0 0x3fff80801c02 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV0_EPF7_1_CACHE_LINE 0 0x3fff80801c03 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV0_EPF7_1_LATENCY 0 0x3fff80801c03 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV0_EPF7_1_HEADER 0 0x3fff80801c03 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV0_EPF7_1_BIST 0 0x3fff80801c03 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1 0 0x3fff80801c04 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2 0 0x3fff80801c05 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3 0 0x3fff80801c06 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4 0 0x3fff80801c07 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5 0 0x3fff80801c08 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6 0 0x3fff80801c09 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR 0 0x3fff80801c0a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID 0 0x3fff80801c0b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR 0 0x3fff80801c0c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV0_EPF7_1_CAP_PTR 0 0x3fff80801c0d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE 0 0x3fff80801c0f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN 0 0x3fff80801c0f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV0_EPF7_1_MIN_GRANT 0 0x3fff80801c0f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV0_EPF7_1_MAX_LATENCY 0 0x3fff80801c0f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST 0 0x3fff80801c12 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W 0 0x3fff80801c13 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST 0 0x3fff80801c14 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_1_PMI_CAP 0 0x3fff80801c14 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL 0 0x3fff80801c15 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV0_EPF7_1_SBRN 0 0x3fff80801c18 1 0 5 SBRN 0 7 regBIF_CFG_DEV0_EPF7_1_FLADJ 0 0x3fff80801c18 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD 0 0x3fff80801c18 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST 0 0x3fff80801c19 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_CAP 0 0x3fff80801c19 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP 0 0x3fff80801c1a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL 0 0x3fff80801c1b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS 0 0x3fff80801c1b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV0_EPF7_1_LINK_CAP 0 0x3fff80801c1c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV0_EPF7_1_LINK_CNTL 0 0x3fff80801c1d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV0_EPF7_1_LINK_STATUS 0 0x3fff80801c1d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2 0 0x3fff80801c22 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2 0 0x3fff80801c23 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2 0 0x3fff80801c23 1 0 5 RESERVED 0 15 regBIF_CFG_DEV0_EPF7_1_LINK_CAP2 0 0x3fff80801c24 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV0_EPF7_1_LINK_CNTL2 0 0x3fff80801c25 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV0_EPF7_1_LINK_STATUS2 0 0x3fff80801c25 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST 0 0x3fff80801c28 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL 0 0x3fff80801c28 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO 0 0x3fff80801c29 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI 0 0x3fff80801c2a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA 0 0x3fff80801c2a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA 0 0x3fff80801c2a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV0_EPF7_1_MSI_MASK 0 0x3fff80801c2b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64 0 0x3fff80801c2b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64 0 0x3fff80801c2b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV0_EPF7_1_MSI_MASK_64 0 0x3fff80801c2c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV0_EPF7_1_MSI_PENDING 0 0x3fff80801c2c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64 0 0x3fff80801c2d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST 0 0x3fff80801c30 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL 0 0x3fff80801c30 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV0_EPF7_1_MSIX_TABLE 0 0x3fff80801c31 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV0_EPF7_1_MSIX_PBA 0 0x3fff80801c32 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80801c40 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80801c41 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80801c42 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80801c43 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80801c54 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80801c55 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80801c56 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80801c57 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS 0 0x3fff80801c58 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK 0 0x3fff80801c59 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff80801c5a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0 0 0x3fff80801c5b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1 0 0x3fff80801c5c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2 0 0x3fff80801c5d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3 0 0x3fff80801c5e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80801c62 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80801c63 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80801c64 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80801c65 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80801c80 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP 0 0x3fff80801c81 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL 0 0x3fff80801c82 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP 0 0x3fff80801c83 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL 0 0x3fff80801c84 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP 0 0x3fff80801c85 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL 0 0x3fff80801c86 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP 0 0x3fff80801c87 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL 0 0x3fff80801c88 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP 0 0x3fff80801c89 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL 0 0x3fff80801c8a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP 0 0x3fff80801c8b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL 0 0x3fff80801c8c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80801c90 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80801c91 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80801c92 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80801c93 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80801c94 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP 0 0x3fff80801c95 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80801c96 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS 0 0x3fff80801c97 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL 0 0x3fff80801c97 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80801c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80801c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80801c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80801c98 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80801c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80801c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80801c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80801c99 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff80801ca8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP 0 0x3fff80801ca9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL 0 0x3fff80801ca9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff80801cb4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP 0 0x3fff80801cb5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL 0 0x3fff80801cb5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff80801cca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP 0 0x3fff80801ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL 0 0x3fff80801ccb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff80801cdc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP 0 0x3fff80801cdd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL 0 0x3fff80801cde 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0 0 0x3fff80801cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1 0 0x3fff80801cdf 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2 0 0x3fff80801ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3 0 0x3fff80801ce0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4 0 0x3fff80801ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5 0 0x3fff80801ce1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6 0 0x3fff80801ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7 0 0x3fff80801ce2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8 0 0x3fff80801ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9 0 0x3fff80801ce3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10 0 0x3fff80801ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11 0 0x3fff80801ce4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12 0 0x3fff80801ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13 0 0x3fff80801ce5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14 0 0x3fff80801ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15 0 0x3fff80801ce6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16 0 0x3fff80801ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17 0 0x3fff80801ce7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18 0 0x3fff80801ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19 0 0x3fff80801ce8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20 0 0x3fff80801ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21 0 0x3fff80801ce9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22 0 0x3fff80801cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23 0 0x3fff80801cea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24 0 0x3fff80801ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25 0 0x3fff80801ceb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26 0 0x3fff80801cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27 0 0x3fff80801cec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28 0 0x3fff80801ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29 0 0x3fff80801ced 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30 0 0x3fff80801cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31 0 0x3fff80801cee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32 0 0x3fff80801cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33 0 0x3fff80801cef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34 0 0x3fff80801cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35 0 0x3fff80801cf0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36 0 0x3fff80801cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37 0 0x3fff80801cf1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38 0 0x3fff80801cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39 0 0x3fff80801cf2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40 0 0x3fff80801cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41 0 0x3fff80801cf3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42 0 0x3fff80801cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43 0 0x3fff80801cf4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44 0 0x3fff80801cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45 0 0x3fff80801cf5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46 0 0x3fff80801cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47 0 0x3fff80801cf6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48 0 0x3fff80801cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49 0 0x3fff80801cf7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50 0 0x3fff80801cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51 0 0x3fff80801cf8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52 0 0x3fff80801cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53 0 0x3fff80801cf9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54 0 0x3fff80801cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55 0 0x3fff80801cfa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56 0 0x3fff80801cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57 0 0x3fff80801cfb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58 0 0x3fff80801cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59 0 0x3fff80801cfc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60 0 0x3fff80801cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61 0 0x3fff80801cfd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62 0 0x3fff80801cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63 0 0x3fff80801cfe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_VENDOR_ID 0 0x3fff80880000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_EPF0_1_DEVICE_ID 0 0x3fff80880000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_EPF0_1_COMMAND 0 0x3fff80880001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_EPF0_1_STATUS 0 0x3fff80880001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_EPF0_1_REVISION_ID 0 0x3fff80880002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE 0 0x3fff80880002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_EPF0_1_SUB_CLASS 0 0x3fff80880002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_EPF0_1_BASE_CLASS 0 0x3fff80880002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_EPF0_1_CACHE_LINE 0 0x3fff80880003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_EPF0_1_LATENCY 0 0x3fff80880003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_EPF0_1_HEADER 0 0x3fff80880003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_EPF0_1_BIST 0 0x3fff80880003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1 0 0x3fff80880004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2 0 0x3fff80880005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3 0 0x3fff80880006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4 0 0x3fff80880007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5 0 0x3fff80880008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6 0 0x3fff80880009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR 0 0x3fff8088000a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID 0 0x3fff8088000b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR 0 0x3fff8088000c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF0_1_CAP_PTR 0 0x3fff8088000d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE 0 0x3fff8088000f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN 0 0x3fff8088000f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_EPF0_1_MIN_GRANT 0 0x3fff8088000f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV1_EPF0_1_MAX_LATENCY 0 0x3fff8088000f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST 0 0x3fff80880012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W 0 0x3fff80880013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST 0 0x3fff80880014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_1_PMI_CAP 0 0x3fff80880014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL 0 0x3fff80880015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_EPF0_1_SBRN 0 0x3fff80880018 1 0 5 SBRN 0 7 regBIF_CFG_DEV1_EPF0_1_FLADJ 0 0x3fff80880018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV1_EPF0_1_DBESL_DBESLD 0 0x3fff80880018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST 0 0x3fff80880019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_CAP 0 0x3fff80880019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP 0 0x3fff8088001a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL 0 0x3fff8088001b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS 0 0x3fff8088001b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_EPF0_1_LINK_CAP 0 0x3fff8088001c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_EPF0_1_LINK_CNTL 0 0x3fff8088001d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_EPF0_1_LINK_STATUS 0 0x3fff8088001d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2 0 0x3fff80880022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2 0 0x3fff80880023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2 0 0x3fff80880023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_EPF0_1_LINK_CAP2 0 0x3fff80880024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF0_1_LINK_CNTL2 0 0x3fff80880025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_EPF0_1_LINK_STATUS2 0 0x3fff80880025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST 0 0x3fff80880028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL 0 0x3fff80880028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO 0 0x3fff80880029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI 0 0x3fff8088002a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA 0 0x3fff8088002a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA 0 0x3fff8088002a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_EPF0_1_MSI_MASK 0 0x3fff8088002b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64 0 0x3fff8088002b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64 0 0x3fff8088002b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_EPF0_1_MSI_MASK_64 0 0x3fff8088002c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV1_EPF0_1_MSI_PENDING 0 0x3fff8088002c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64 0 0x3fff8088002d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST 0 0x3fff80880030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL 0 0x3fff80880030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV1_EPF0_1_MSIX_TABLE 0 0x3fff80880031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV1_EPF0_1_MSIX_PBA 0 0x3fff80880032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80880040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80880041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80880042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80880043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff80880044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff80880045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff80880046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL 0 0x3fff80880047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS 0 0x3fff80880047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff80880048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff80880049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff8088004a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff8088004b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff8088004c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff8088004d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80880054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80880055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80880056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80880057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS 0 0x3fff80880058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK 0 0x3fff80880059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8088005a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0 0 0x3fff8088005b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1 0 0x3fff8088005c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2 0 0x3fff8088005d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3 0 0x3fff8088005e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80880062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80880063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80880064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80880065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80880080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP 0 0x3fff80880081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL 0 0x3fff80880082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP 0 0x3fff80880083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL 0 0x3fff80880084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP 0 0x3fff80880085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL 0 0x3fff80880086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP 0 0x3fff80880087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL 0 0x3fff80880088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP 0 0x3fff80880089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL 0 0x3fff8088008a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP 0 0x3fff8088008b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL 0 0x3fff8088008c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80880090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80880091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80880092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80880093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80880094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP 0 0x3fff80880095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80880096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS 0 0x3fff80880097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL 0 0x3fff80880097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80880098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80880098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80880098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80880098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80880099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80880099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80880099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80880099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff8088009c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3 0 0x3fff8088009d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS 0 0x3fff8088009e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff8088009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff8088009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff808800a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff808800a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff808800a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff808800a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff808800a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff808800a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff808800a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff808800a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff808800a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff808800a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff808800a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff808800a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff808800a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff808800a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808800a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP 0 0x3fff808800a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL 0 0x3fff808800a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808800b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP 0 0x3fff808800b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL 0 0x3fff808800b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0 0x3fff808800c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP 0 0x3fff808800c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808800ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP 0 0x3fff808800cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL 0 0x3fff808800cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808800dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP 0 0x3fff808800dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL 0 0x3fff808800de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808800df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808800df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808800e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808800e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808800e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808800e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808800e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808800e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808800e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808800e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808800e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808800e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808800e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808800e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808800e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808800e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808800e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808800e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808800e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808800e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808800e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808800e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808800ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808800ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808800eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808800eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808800ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808800ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808800ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808800ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808800ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808800ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808800ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808800ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808800f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808800f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808800f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808800f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808800f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808800f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808800f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808800f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808800f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808800f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808800f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808800f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808800f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808800f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808800f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808800f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808800f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808800f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808800f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808800f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808800fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808800fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808800fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808800fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808800fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808800fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808800fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808800fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808800fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808800fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff80880100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP 0 0x3fff80880101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS 0 0x3fff80880102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff80880104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT 0 0x3fff80880105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT 0 0x3fff80880106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT 0 0x3fff80880107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80880108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80880109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff8088010a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff8088010c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff8088010c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff8088010c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff8088010c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff8088010d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff8088010d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff8088010d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff8088010d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff8088010e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff8088010e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff8088010e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff8088010e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff8088010f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff8088010f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff8088010f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff8088010f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff80880110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP 0 0x3fff80880111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS 0 0x3fff80880111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff80880112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff80880112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff80880113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff80880113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff80880114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff80880114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff80880115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff80880115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff80880116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff80880116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff80880117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff80880117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff80880118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff80880118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff80880119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff80880119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff8088011a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff8088011a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff8088011b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff8088011b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff8088011c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff8088011c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff8088011d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff8088011d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff8088011e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff8088011e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff8088011f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff8088011f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff80880120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff80880120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff80880121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff80880121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV1_EPF1_1_VENDOR_ID 0 0x3fff80880400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV1_EPF1_1_DEVICE_ID 0 0x3fff80880400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV1_EPF1_1_COMMAND 0 0x3fff80880401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV1_EPF1_1_STATUS 0 0x3fff80880401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV1_EPF1_1_REVISION_ID 0 0x3fff80880402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE 0 0x3fff80880402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV1_EPF1_1_SUB_CLASS 0 0x3fff80880402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV1_EPF1_1_BASE_CLASS 0 0x3fff80880402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV1_EPF1_1_CACHE_LINE 0 0x3fff80880403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV1_EPF1_1_LATENCY 0 0x3fff80880403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV1_EPF1_1_HEADER 0 0x3fff80880403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV1_EPF1_1_BIST 0 0x3fff80880403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1 0 0x3fff80880404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2 0 0x3fff80880405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3 0 0x3fff80880406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4 0 0x3fff80880407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5 0 0x3fff80880408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6 0 0x3fff80880409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR 0 0x3fff8088040a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID 0 0x3fff8088040b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR 0 0x3fff8088040c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV1_EPF1_1_CAP_PTR 0 0x3fff8088040d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE 0 0x3fff8088040f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN 0 0x3fff8088040f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV1_EPF1_1_MIN_GRANT 0 0x3fff8088040f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV1_EPF1_1_MAX_LATENCY 0 0x3fff8088040f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST 0 0x3fff80880412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W 0 0x3fff80880413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST 0 0x3fff80880414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_1_PMI_CAP 0 0x3fff80880414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL 0 0x3fff80880415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV1_EPF1_1_SBRN 0 0x3fff80880418 1 0 5 SBRN 0 7 regBIF_CFG_DEV1_EPF1_1_FLADJ 0 0x3fff80880418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD 0 0x3fff80880418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST 0 0x3fff80880419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_CAP 0 0x3fff80880419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP 0 0x3fff8088041a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL 0 0x3fff8088041b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS 0 0x3fff8088041b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV1_EPF1_1_LINK_CAP 0 0x3fff8088041c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV1_EPF1_1_LINK_CNTL 0 0x3fff8088041d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV1_EPF1_1_LINK_STATUS 0 0x3fff8088041d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2 0 0x3fff80880422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2 0 0x3fff80880423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2 0 0x3fff80880423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV1_EPF1_1_LINK_CAP2 0 0x3fff80880424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV1_EPF1_1_LINK_CNTL2 0 0x3fff80880425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV1_EPF1_1_LINK_STATUS2 0 0x3fff80880425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST 0 0x3fff80880428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL 0 0x3fff80880428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO 0 0x3fff80880429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI 0 0x3fff8088042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA 0 0x3fff8088042a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA 0 0x3fff8088042a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV1_EPF1_1_MSI_MASK 0 0x3fff8088042b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64 0 0x3fff8088042b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64 0 0x3fff8088042b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV1_EPF1_1_MSI_MASK_64 0 0x3fff8088042c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV1_EPF1_1_MSI_PENDING 0 0x3fff8088042c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64 0 0x3fff8088042d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST 0 0x3fff80880430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL 0 0x3fff80880430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV1_EPF1_1_MSIX_TABLE 0 0x3fff80880431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV1_EPF1_1_MSIX_PBA 0 0x3fff80880432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80880440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80880441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80880442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80880443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80880454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80880455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80880456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80880457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS 0 0x3fff80880458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK 0 0x3fff80880459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8088045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0 0 0x3fff8088045b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1 0 0x3fff8088045c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2 0 0x3fff8088045d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3 0 0x3fff8088045e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80880462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80880463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80880464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80880465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80880480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP 0 0x3fff80880481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL 0 0x3fff80880482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP 0 0x3fff80880483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL 0 0x3fff80880484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP 0 0x3fff80880485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL 0 0x3fff80880486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP 0 0x3fff80880487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL 0 0x3fff80880488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP 0 0x3fff80880489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL 0 0x3fff8088048a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP 0 0x3fff8088048b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL 0 0x3fff8088048c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80880490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80880491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80880492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80880493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80880494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP 0 0x3fff80880495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80880496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS 0 0x3fff80880497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL 0 0x3fff80880497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80880498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80880498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80880498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80880498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80880499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80880499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80880499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80880499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff808804a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP 0 0x3fff808804a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL 0 0x3fff808804a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff808804b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP 0 0x3fff808804b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL 0 0x3fff808804b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff808804ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP 0 0x3fff808804cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL 0 0x3fff808804cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff808804dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP 0 0x3fff808804dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL 0 0x3fff808804de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0 0 0x3fff808804df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1 0 0x3fff808804df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2 0 0x3fff808804e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3 0 0x3fff808804e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4 0 0x3fff808804e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5 0 0x3fff808804e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6 0 0x3fff808804e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7 0 0x3fff808804e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8 0 0x3fff808804e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9 0 0x3fff808804e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10 0 0x3fff808804e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11 0 0x3fff808804e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12 0 0x3fff808804e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13 0 0x3fff808804e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14 0 0x3fff808804e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15 0 0x3fff808804e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16 0 0x3fff808804e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17 0 0x3fff808804e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18 0 0x3fff808804e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19 0 0x3fff808804e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20 0 0x3fff808804e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21 0 0x3fff808804e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22 0 0x3fff808804ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23 0 0x3fff808804ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24 0 0x3fff808804eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25 0 0x3fff808804eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26 0 0x3fff808804ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27 0 0x3fff808804ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28 0 0x3fff808804ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29 0 0x3fff808804ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30 0 0x3fff808804ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31 0 0x3fff808804ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32 0 0x3fff808804ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33 0 0x3fff808804ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34 0 0x3fff808804f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35 0 0x3fff808804f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36 0 0x3fff808804f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37 0 0x3fff808804f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38 0 0x3fff808804f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39 0 0x3fff808804f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40 0 0x3fff808804f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41 0 0x3fff808804f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42 0 0x3fff808804f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43 0 0x3fff808804f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44 0 0x3fff808804f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45 0 0x3fff808804f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46 0 0x3fff808804f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47 0 0x3fff808804f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48 0 0x3fff808804f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49 0 0x3fff808804f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50 0 0x3fff808804f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51 0 0x3fff808804f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52 0 0x3fff808804f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53 0 0x3fff808804f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54 0 0x3fff808804fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55 0 0x3fff808804fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56 0 0x3fff808804fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57 0 0x3fff808804fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58 0 0x3fff808804fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59 0 0x3fff808804fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60 0 0x3fff808804fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61 0 0x3fff808804fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62 0 0x3fff808804fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63 0 0x3fff808804fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_VENDOR_ID 0 0x3fff80900000 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF0_1_DEVICE_ID 0 0x3fff80900000 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF0_1_COMMAND 0 0x3fff80900001 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF0_1_STATUS 0 0x3fff80900001 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF0_1_REVISION_ID 0 0x3fff80900002 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF0_1_PROG_INTERFACE 0 0x3fff80900002 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF0_1_SUB_CLASS 0 0x3fff80900002 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF0_1_BASE_CLASS 0 0x3fff80900002 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF0_1_CACHE_LINE 0 0x3fff80900003 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF0_1_LATENCY 0 0x3fff80900003 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF0_1_HEADER 0 0x3fff80900003 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF0_1_BIST 0 0x3fff80900003 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_1 0 0x3fff80900004 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_2 0 0x3fff80900005 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_3 0 0x3fff80900006 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_4 0 0x3fff80900007 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_5 0 0x3fff80900008 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_BASE_ADDR_6 0 0x3fff80900009 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR 0 0x3fff8090000a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID 0 0x3fff8090000b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR 0 0x3fff8090000c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF0_1_CAP_PTR 0 0x3fff8090000d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE 0 0x3fff8090000f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN 0 0x3fff8090000f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF0_1_MIN_GRANT 0 0x3fff8090000f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF0_1_MAX_LATENCY 0 0x3fff8090000f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST 0 0x3fff80900012 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W 0 0x3fff80900013 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST 0 0x3fff80900014 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_1_PMI_CAP 0 0x3fff80900014 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL 0 0x3fff80900015 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF0_1_SBRN 0 0x3fff80900018 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF0_1_FLADJ 0 0x3fff80900018 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF0_1_DBESL_DBESLD 0 0x3fff80900018 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST 0 0x3fff80900019 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_CAP 0 0x3fff80900019 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP 0 0x3fff8090001a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL 0 0x3fff8090001b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS 0 0x3fff8090001b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF0_1_LINK_CAP 0 0x3fff8090001c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF0_1_LINK_CNTL 0 0x3fff8090001d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF0_1_LINK_STATUS 0 0x3fff8090001d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF0_1_DEVICE_CAP2 0 0x3fff80900022 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2 0 0x3fff80900023 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2 0 0x3fff80900023 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF0_1_LINK_CAP2 0 0x3fff80900024 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF0_1_LINK_CNTL2 0 0x3fff80900025 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF0_1_LINK_STATUS2 0 0x3fff80900025 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST 0 0x3fff80900028 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL 0 0x3fff80900028 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO 0 0x3fff80900029 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI 0 0x3fff8090002a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA 0 0x3fff8090002a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA 0 0x3fff8090002a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF0_1_MSI_MASK 0 0x3fff8090002b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64 0 0x3fff8090002b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64 0 0x3fff8090002b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF0_1_MSI_MASK_64 0 0x3fff8090002c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF0_1_MSI_PENDING 0 0x3fff8090002c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF0_1_MSI_PENDING_64 0 0x3fff8090002d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST 0 0x3fff80900030 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL 0 0x3fff80900030 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF0_1_MSIX_TABLE 0 0x3fff80900031 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF0_1_MSIX_PBA 0 0x3fff80900032 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80900040 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80900041 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80900042 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80900043 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST 0 0x3fff80900044 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1 0 0x3fff80900045 4 0 5 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2 0 0x3fff80900046 2 0 5 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL 0 0x3fff80900047 2 0 5 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 regBIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS 0 0x3fff80900047 1 0 5 VC_ARB_TABLE_STATUS 0 0 regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP 0 0x3fff80900048 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 22 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0 0x3fff80900049 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0 0x3fff8090004a 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP 0 0x3fff8090004b 4 0 5 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0 0x3fff8090004c 6 0 5 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0 0x3fff8090004d 2 0 5 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80900054 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80900055 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80900056 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80900057 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS 0 0x3fff80900058 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK 0 0x3fff80900059 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8090005a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0 0 0x3fff8090005b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1 0 0x3fff8090005c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2 0 0x3fff8090005d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3 0 0x3fff8090005e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80900062 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80900063 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80900064 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80900065 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80900080 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP 0 0x3fff80900081 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL 0 0x3fff80900082 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP 0 0x3fff80900083 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL 0 0x3fff80900084 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP 0 0x3fff80900085 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL 0 0x3fff80900086 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP 0 0x3fff80900087 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL 0 0x3fff80900088 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP 0 0x3fff80900089 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL 0 0x3fff8090008a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP 0 0x3fff8090008b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL 0 0x3fff8090008c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80900090 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80900091 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80900092 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80900093 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80900094 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP 0 0x3fff80900095 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80900096 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS 0 0x3fff80900097 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL 0 0x3fff80900097 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80900098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80900098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80900098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80900098 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80900099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80900099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80900099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80900099 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0 0x3fff8090009c 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3 0 0x3fff8090009d 2 0 5 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS 0 0x3fff8090009e 1 0 5 LANE_ERROR_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0 0x3fff8090009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0 0x3fff8090009f 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0 0x3fff809000a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0 0x3fff809000a0 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0 0x3fff809000a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0 0x3fff809000a1 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0 0x3fff809000a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0 0x3fff809000a2 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0 0x3fff809000a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0 0x3fff809000a3 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0 0x3fff809000a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0 0x3fff809000a4 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0 0x3fff809000a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0 0x3fff809000a5 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0 0x3fff809000a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0 0x3fff809000a6 4 0 5 DOWNSTREAM_PORT_8GT_TX_PRESET 0 3 DOWNSTREAM_PORT_8GT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_8GT_TX_PRESET 8 11 UPSTREAM_PORT_8GT_RX_PRESET_HINT 12 14 regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff809000a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP 0 0x3fff809000a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL 0 0x3fff809000a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff809000b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP 0 0x3fff809000b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL 0 0x3fff809000b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0 0x3fff809000c8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP 0 0x3fff809000c9 4 0 5 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff809000ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP 0 0x3fff809000cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL 0 0x3fff809000cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff809000dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP 0 0x3fff809000dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL 0 0x3fff809000de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0 0 0x3fff809000df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1 0 0x3fff809000df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2 0 0x3fff809000e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3 0 0x3fff809000e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4 0 0x3fff809000e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5 0 0x3fff809000e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6 0 0x3fff809000e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7 0 0x3fff809000e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8 0 0x3fff809000e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9 0 0x3fff809000e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10 0 0x3fff809000e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11 0 0x3fff809000e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12 0 0x3fff809000e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13 0 0x3fff809000e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14 0 0x3fff809000e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15 0 0x3fff809000e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16 0 0x3fff809000e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17 0 0x3fff809000e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18 0 0x3fff809000e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19 0 0x3fff809000e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20 0 0x3fff809000e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21 0 0x3fff809000e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22 0 0x3fff809000ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23 0 0x3fff809000ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24 0 0x3fff809000eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25 0 0x3fff809000eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26 0 0x3fff809000ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27 0 0x3fff809000ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28 0 0x3fff809000ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29 0 0x3fff809000ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30 0 0x3fff809000ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31 0 0x3fff809000ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32 0 0x3fff809000ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33 0 0x3fff809000ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34 0 0x3fff809000f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35 0 0x3fff809000f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36 0 0x3fff809000f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37 0 0x3fff809000f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38 0 0x3fff809000f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39 0 0x3fff809000f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40 0 0x3fff809000f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41 0 0x3fff809000f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42 0 0x3fff809000f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43 0 0x3fff809000f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44 0 0x3fff809000f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45 0 0x3fff809000f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46 0 0x3fff809000f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47 0 0x3fff809000f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48 0 0x3fff809000f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49 0 0x3fff809000f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50 0 0x3fff809000f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51 0 0x3fff809000f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52 0 0x3fff809000f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53 0 0x3fff809000f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54 0 0x3fff809000fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55 0 0x3fff809000fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56 0 0x3fff809000fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57 0 0x3fff809000fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58 0 0x3fff809000fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59 0 0x3fff809000fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60 0 0x3fff809000fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61 0 0x3fff809000fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62 0 0x3fff809000fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63 0 0x3fff809000fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0 0x3fff80900100 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP 0 0x3fff80900101 2 0 5 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 regBIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS 0 0x3fff80900102 2 0 5 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 regBIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0 0x3fff80900104 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT 0 0x3fff80900105 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT 0 0x3fff80900106 1 0 5 RESERVED 0 31 regBIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT 0 0x3fff80900107 5 0 5 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 regBIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80900108 1 0 5 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0 0x3fff80900109 1 0 5 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0 0x3fff8090010a 1 0 5 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 regBIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0 0x3fff8090010c 2 0 5 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0 0x3fff8090010c 2 0 5 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0 0x3fff8090010c 2 0 5 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0 0x3fff8090010c 2 0 5 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0 0x3fff8090010d 2 0 5 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0 0x3fff8090010d 2 0 5 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0 0x3fff8090010d 2 0 5 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0 0x3fff8090010d 2 0 5 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0 0x3fff8090010e 2 0 5 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0 0x3fff8090010e 2 0 5 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0 0x3fff8090010e 2 0 5 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0 0x3fff8090010e 2 0 5 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0 0x3fff8090010f 2 0 5 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0 0x3fff8090010f 2 0 5 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0 0x3fff8090010f 2 0 5 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0 0x3fff8090010f 2 0 5 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 regBIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0 0x3fff80900110 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP 0 0x3fff80900111 1 0 5 MARGINING_USES_SOFTWARE 0 0 regBIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS 0 0x3fff80900111 2 0 5 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0 0x3fff80900112 4 0 5 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0 0x3fff80900112 4 0 5 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0 0x3fff80900113 4 0 5 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0 0x3fff80900113 4 0 5 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0 0x3fff80900114 4 0 5 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0 0x3fff80900114 4 0 5 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0 0x3fff80900115 4 0 5 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0 0x3fff80900115 4 0 5 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0 0x3fff80900116 4 0 5 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0 0x3fff80900116 4 0 5 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0 0x3fff80900117 4 0 5 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0 0x3fff80900117 4 0 5 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0 0x3fff80900118 4 0 5 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0 0x3fff80900118 4 0 5 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0 0x3fff80900119 4 0 5 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0 0x3fff80900119 4 0 5 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0 0x3fff8090011a 4 0 5 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0 0x3fff8090011a 4 0 5 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0 0x3fff8090011b 4 0 5 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0 0x3fff8090011b 4 0 5 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0 0x3fff8090011c 4 0 5 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0 0x3fff8090011c 4 0 5 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0 0x3fff8090011d 4 0 5 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0 0x3fff8090011d 4 0 5 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0 0x3fff8090011e 4 0 5 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0 0x3fff8090011e 4 0 5 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0 0x3fff8090011f 4 0 5 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0 0x3fff8090011f 4 0 5 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0 0x3fff80900120 4 0 5 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0 0x3fff80900120 4 0 5 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0 0x3fff80900121 4 0 5 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 regBIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0 0x3fff80900121 4 0 5 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 regBIF_CFG_DEV2_EPF1_1_VENDOR_ID 0 0x3fff80900400 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF1_1_DEVICE_ID 0 0x3fff80900400 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF1_1_COMMAND 0 0x3fff80900401 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF1_1_STATUS 0 0x3fff80900401 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF1_1_REVISION_ID 0 0x3fff80900402 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF1_1_PROG_INTERFACE 0 0x3fff80900402 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF1_1_SUB_CLASS 0 0x3fff80900402 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF1_1_BASE_CLASS 0 0x3fff80900402 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF1_1_CACHE_LINE 0 0x3fff80900403 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF1_1_LATENCY 0 0x3fff80900403 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF1_1_HEADER 0 0x3fff80900403 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF1_1_BIST 0 0x3fff80900403 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_1 0 0x3fff80900404 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_2 0 0x3fff80900405 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_3 0 0x3fff80900406 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_4 0 0x3fff80900407 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_5 0 0x3fff80900408 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_BASE_ADDR_6 0 0x3fff80900409 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR 0 0x3fff8090040a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID 0 0x3fff8090040b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR 0 0x3fff8090040c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF1_1_CAP_PTR 0 0x3fff8090040d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE 0 0x3fff8090040f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN 0 0x3fff8090040f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF1_1_MIN_GRANT 0 0x3fff8090040f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF1_1_MAX_LATENCY 0 0x3fff8090040f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST 0 0x3fff80900412 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W 0 0x3fff80900413 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST 0 0x3fff80900414 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_1_PMI_CAP 0 0x3fff80900414 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL 0 0x3fff80900415 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF1_1_SBRN 0 0x3fff80900418 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF1_1_FLADJ 0 0x3fff80900418 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF1_1_DBESL_DBESLD 0 0x3fff80900418 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST 0 0x3fff80900419 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_CAP 0 0x3fff80900419 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP 0 0x3fff8090041a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL 0 0x3fff8090041b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS 0 0x3fff8090041b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF1_1_LINK_CAP 0 0x3fff8090041c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF1_1_LINK_CNTL 0 0x3fff8090041d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF1_1_LINK_STATUS 0 0x3fff8090041d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF1_1_DEVICE_CAP2 0 0x3fff80900422 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2 0 0x3fff80900423 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2 0 0x3fff80900423 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF1_1_LINK_CAP2 0 0x3fff80900424 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF1_1_LINK_CNTL2 0 0x3fff80900425 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF1_1_LINK_STATUS2 0 0x3fff80900425 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST 0 0x3fff80900428 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL 0 0x3fff80900428 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO 0 0x3fff80900429 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI 0 0x3fff8090042a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA 0 0x3fff8090042a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA 0 0x3fff8090042a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF1_1_MSI_MASK 0 0x3fff8090042b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64 0 0x3fff8090042b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64 0 0x3fff8090042b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF1_1_MSI_MASK_64 0 0x3fff8090042c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF1_1_MSI_PENDING 0 0x3fff8090042c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF1_1_MSI_PENDING_64 0 0x3fff8090042d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST 0 0x3fff80900430 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL 0 0x3fff80900430 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF1_1_MSIX_TABLE 0 0x3fff80900431 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF1_1_MSIX_PBA 0 0x3fff80900432 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80900440 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80900441 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80900442 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80900443 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80900454 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80900455 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80900456 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80900457 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS 0 0x3fff80900458 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK 0 0x3fff80900459 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8090045a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0 0 0x3fff8090045b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1 0 0x3fff8090045c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2 0 0x3fff8090045d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3 0 0x3fff8090045e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80900462 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80900463 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80900464 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80900465 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80900480 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP 0 0x3fff80900481 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL 0 0x3fff80900482 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP 0 0x3fff80900483 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL 0 0x3fff80900484 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP 0 0x3fff80900485 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL 0 0x3fff80900486 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP 0 0x3fff80900487 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL 0 0x3fff80900488 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP 0 0x3fff80900489 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL 0 0x3fff8090048a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP 0 0x3fff8090048b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL 0 0x3fff8090048c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80900490 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80900491 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80900492 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80900493 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80900494 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP 0 0x3fff80900495 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80900496 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS 0 0x3fff80900497 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL 0 0x3fff80900497 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80900498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80900498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80900498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80900498 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80900499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80900499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80900499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80900499 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff809004a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP 0 0x3fff809004a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL 0 0x3fff809004a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff809004b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP 0 0x3fff809004b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL 0 0x3fff809004b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff809004ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP 0 0x3fff809004cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL 0 0x3fff809004cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff809004dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP 0 0x3fff809004dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL 0 0x3fff809004de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0 0 0x3fff809004df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1 0 0x3fff809004df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2 0 0x3fff809004e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3 0 0x3fff809004e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4 0 0x3fff809004e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5 0 0x3fff809004e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6 0 0x3fff809004e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7 0 0x3fff809004e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8 0 0x3fff809004e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9 0 0x3fff809004e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10 0 0x3fff809004e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11 0 0x3fff809004e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12 0 0x3fff809004e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13 0 0x3fff809004e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14 0 0x3fff809004e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15 0 0x3fff809004e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16 0 0x3fff809004e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17 0 0x3fff809004e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18 0 0x3fff809004e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19 0 0x3fff809004e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20 0 0x3fff809004e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21 0 0x3fff809004e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22 0 0x3fff809004ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23 0 0x3fff809004ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24 0 0x3fff809004eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25 0 0x3fff809004eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26 0 0x3fff809004ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27 0 0x3fff809004ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28 0 0x3fff809004ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29 0 0x3fff809004ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30 0 0x3fff809004ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31 0 0x3fff809004ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32 0 0x3fff809004ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33 0 0x3fff809004ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34 0 0x3fff809004f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35 0 0x3fff809004f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36 0 0x3fff809004f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37 0 0x3fff809004f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38 0 0x3fff809004f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39 0 0x3fff809004f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40 0 0x3fff809004f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41 0 0x3fff809004f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42 0 0x3fff809004f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43 0 0x3fff809004f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44 0 0x3fff809004f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45 0 0x3fff809004f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46 0 0x3fff809004f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47 0 0x3fff809004f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48 0 0x3fff809004f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49 0 0x3fff809004f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50 0 0x3fff809004f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51 0 0x3fff809004f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52 0 0x3fff809004f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53 0 0x3fff809004f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54 0 0x3fff809004fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55 0 0x3fff809004fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56 0 0x3fff809004fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57 0 0x3fff809004fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58 0 0x3fff809004fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59 0 0x3fff809004fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60 0 0x3fff809004fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61 0 0x3fff809004fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62 0 0x3fff809004fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63 0 0x3fff809004fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_VENDOR_ID 0 0x3fff80900800 1 0 5 VENDOR_ID 0 15 regBIF_CFG_DEV2_EPF2_1_DEVICE_ID 0 0x3fff80900800 1 0 5 DEVICE_ID 0 15 regBIF_CFG_DEV2_EPF2_1_COMMAND 0 0x3fff80900801 11 0 5 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 regBIF_CFG_DEV2_EPF2_1_STATUS 0 0x3fff80900801 12 0 5 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 regBIF_CFG_DEV2_EPF2_1_REVISION_ID 0 0x3fff80900802 2 0 5 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 regBIF_CFG_DEV2_EPF2_1_PROG_INTERFACE 0 0x3fff80900802 1 0 5 PROG_INTERFACE 0 7 regBIF_CFG_DEV2_EPF2_1_SUB_CLASS 0 0x3fff80900802 1 0 5 SUB_CLASS 0 7 regBIF_CFG_DEV2_EPF2_1_BASE_CLASS 0 0x3fff80900802 1 0 5 BASE_CLASS 0 7 regBIF_CFG_DEV2_EPF2_1_CACHE_LINE 0 0x3fff80900803 1 0 5 CACHE_LINE_SIZE 0 7 regBIF_CFG_DEV2_EPF2_1_LATENCY 0 0x3fff80900803 1 0 5 LATENCY_TIMER 0 7 regBIF_CFG_DEV2_EPF2_1_HEADER 0 0x3fff80900803 2 0 5 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 regBIF_CFG_DEV2_EPF2_1_BIST 0 0x3fff80900803 3 0 5 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_1 0 0x3fff80900804 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_2 0 0x3fff80900805 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_3 0 0x3fff80900806 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_4 0 0x3fff80900807 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_5 0 0x3fff80900808 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_BASE_ADDR_6 0 0x3fff80900809 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR 0 0x3fff8090080a 1 0 5 CARDBUS_CIS_PTR 0 31 regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID 0 0x3fff8090080b 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR 0 0x3fff8090080c 1 0 5 BASE_ADDR 0 31 regBIF_CFG_DEV2_EPF2_1_CAP_PTR 0 0x3fff8090080d 1 0 5 CAP_PTR 0 7 regBIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE 0 0x3fff8090080f 1 0 5 INTERRUPT_LINE 0 7 regBIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN 0 0x3fff8090080f 1 0 5 INTERRUPT_PIN 0 7 regBIF_CFG_DEV2_EPF2_1_MIN_GRANT 0 0x3fff8090080f 1 0 5 MIN_GNT 0 7 regBIF_CFG_DEV2_EPF2_1_MAX_LATENCY 0 0x3fff8090080f 1 0 5 MAX_LAT 0 7 regBIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST 0 0x3fff80900812 3 0 5 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 regBIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W 0 0x3fff80900813 2 0 5 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 regBIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST 0 0x3fff80900814 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_1_PMI_CAP 0 0x3fff80900814 8 0 5 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 regBIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL 0 0x3fff80900815 9 0 5 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 regBIF_CFG_DEV2_EPF2_1_SBRN 0 0x3fff80900818 1 0 5 SBRN 0 7 regBIF_CFG_DEV2_EPF2_1_FLADJ 0 0x3fff80900818 2 0 5 FLADJ 0 5 NFC 6 6 regBIF_CFG_DEV2_EPF2_1_DBESL_DBESLD 0 0x3fff80900818 2 0 5 DBESL 0 3 DBESLD 4 7 regBIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST 0 0x3fff80900819 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_CAP 0 0x3fff80900819 4 0 5 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP 0 0x3fff8090081a 9 0 5 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL 0 0x3fff8090081b 12 0 5 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS 0 0x3fff8090081b 7 0 5 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 regBIF_CFG_DEV2_EPF2_1_LINK_CAP 0 0x3fff8090081c 11 0 5 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 regBIF_CFG_DEV2_EPF2_1_LINK_CNTL 0 0x3fff8090081d 11 0 5 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 regBIF_CFG_DEV2_EPF2_1_LINK_STATUS 0 0x3fff8090081d 7 0 5 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 regBIF_CFG_DEV2_EPF2_1_DEVICE_CAP2 0 0x3fff80900822 20 0 5 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 FRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2 0 0x3fff80900823 12 0 5 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 regBIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2 0 0x3fff80900823 1 0 5 RESERVED 0 15 regBIF_CFG_DEV2_EPF2_1_LINK_CAP2 0 0x3fff80900824 6 0 5 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_RCV_SUPPORT 16 22 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 regBIF_CFG_DEV2_EPF2_1_LINK_CNTL2 0 0x3fff80900825 8 0 5 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 regBIF_CFG_DEV2_EPF2_1_LINK_STATUS2 0 0x3fff80900825 11 0 5 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 regBIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST 0 0x3fff80900828 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL 0 0x3fff80900828 7 0 5 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 MSI_EXT_MSG_DATA_CAP 9 9 MSI_EXT_MSG_DATA_EN 10 10 regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO 0 0x3fff80900829 1 0 5 MSI_MSG_ADDR_LO 2 31 regBIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI 0 0x3fff8090082a 1 0 5 MSI_MSG_ADDR_HI 0 31 regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA 0 0x3fff8090082a 1 0 5 MSI_DATA 0 15 regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA 0 0x3fff8090082a 1 0 5 MSI_EXT_DATA 0 15 regBIF_CFG_DEV2_EPF2_1_MSI_MASK 0 0x3fff8090082b 1 0 5 MSI_MASK 0 31 regBIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64 0 0x3fff8090082b 1 0 5 MSI_DATA_64 0 15 regBIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64 0 0x3fff8090082b 1 0 5 MSI_EXT_DATA_64 0 15 regBIF_CFG_DEV2_EPF2_1_MSI_MASK_64 0 0x3fff8090082c 1 0 5 MSI_MASK_64 0 31 regBIF_CFG_DEV2_EPF2_1_MSI_PENDING 0 0x3fff8090082c 1 0 5 MSI_PENDING 0 31 regBIF_CFG_DEV2_EPF2_1_MSI_PENDING_64 0 0x3fff8090082d 1 0 5 MSI_PENDING_64 0 31 regBIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST 0 0x3fff80900830 2 0 5 CAP_ID 0 7 NEXT_PTR 8 15 regBIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL 0 0x3fff80900830 3 0 5 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 regBIF_CFG_DEV2_EPF2_1_MSIX_TABLE 0 0x3fff80900831 2 0 5 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 regBIF_CFG_DEV2_EPF2_1_MSIX_PBA 0 0x3fff80900832 2 0 5 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0 0x3fff80900840 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0 0x3fff80900841 3 0 5 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1 0 0x3fff80900842 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2 0 0x3fff80900843 1 0 5 SCRATCH 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0 0x3fff80900854 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS 0 0x3fff80900855 17 0 5 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK 0 0x3fff80900856 17 0 5 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 regBIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0 0x3fff80900857 17 0 5 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS 0 0x3fff80900858 8 0 5 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 regBIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK 0 0x3fff80900859 8 0 5 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 regBIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0 0x3fff8090085a 7 0 5 FIRST_ERR_PTR 0 4 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0 0 0x3fff8090085b 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1 0 0x3fff8090085c 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2 0 0x3fff8090085d 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3 0 0x3fff8090085e 1 0 5 TLP_HDR 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0 0 0x3fff80900862 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1 0 0x3fff80900863 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2 0 0x3fff80900864 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3 0 0x3fff80900865 1 0 5 TLP_PREFIX 0 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0 0x3fff80900880 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP 0 0x3fff80900881 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL 0 0x3fff80900882 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP 0 0x3fff80900883 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL 0 0x3fff80900884 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP 0 0x3fff80900885 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL 0 0x3fff80900886 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP 0 0x3fff80900887 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL 0 0x3fff80900888 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP 0 0x3fff80900889 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL 0 0x3fff8090088a 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP 0 0x3fff8090088b 1 0 5 BAR_SIZE_SUPPORTED 4 31 regBIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL 0 0x3fff8090088c 4 0 5 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 BAR_SIZE_SUPPORTED_UPPER 16 31 regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0 0x3fff80900890 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0 0x3fff80900891 1 0 5 DATA_SELECT 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA 0 0x3fff80900892 6 0 5 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 regBIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP 0 0x3fff80900893 1 0 5 SYSTEM_ALLOCATED 0 0 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0 0x3fff80900894 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP 0 0x3fff80900895 5 0 5 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0 0x3fff80900896 1 0 5 TRANS_LAT_INDICATOR_BITS 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS 0 0x3fff80900897 2 0 5 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL 0 0x3fff80900897 1 0 5 SUBSTATE_CNTL 0 4 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0 0x3fff80900898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0 0x3fff80900898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0 0x3fff80900898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0 0x3fff80900898 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0 0x3fff80900899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0 0x3fff80900899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0 0x3fff80900899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0 0x3fff80900899 1 0 5 SUBSTATE_PWR_ALLOC 0 7 regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0 0x3fff809008a8 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP 0 0x3fff809008a9 8 0 5 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL 0 0x3fff809008a9 7 0 5 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0 0x3fff809008b4 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP 0 0x3fff809008b5 3 0 5 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 regBIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL 0 0x3fff809008b5 3 0 5 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0 0x3fff809008ca 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP 0 0x3fff809008cb 3 0 5 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL 0 0x3fff809008cb 3 0 5 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST 0 0x3fff809008dc 3 0 5 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP 0 0x3fff809008dd 6 0 5 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL 0 0x3fff809008de 2 0 5 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0 0 0x3fff809008df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1 0 0x3fff809008df 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2 0 0x3fff809008e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3 0 0x3fff809008e0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4 0 0x3fff809008e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5 0 0x3fff809008e1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6 0 0x3fff809008e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7 0 0x3fff809008e2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8 0 0x3fff809008e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9 0 0x3fff809008e3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10 0 0x3fff809008e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11 0 0x3fff809008e4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12 0 0x3fff809008e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13 0 0x3fff809008e5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14 0 0x3fff809008e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15 0 0x3fff809008e6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16 0 0x3fff809008e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17 0 0x3fff809008e7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18 0 0x3fff809008e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19 0 0x3fff809008e8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20 0 0x3fff809008e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21 0 0x3fff809008e9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22 0 0x3fff809008ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23 0 0x3fff809008ea 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24 0 0x3fff809008eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25 0 0x3fff809008eb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26 0 0x3fff809008ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27 0 0x3fff809008ec 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28 0 0x3fff809008ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29 0 0x3fff809008ed 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30 0 0x3fff809008ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31 0 0x3fff809008ee 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32 0 0x3fff809008ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33 0 0x3fff809008ef 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34 0 0x3fff809008f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35 0 0x3fff809008f0 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36 0 0x3fff809008f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37 0 0x3fff809008f1 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38 0 0x3fff809008f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39 0 0x3fff809008f2 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40 0 0x3fff809008f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41 0 0x3fff809008f3 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42 0 0x3fff809008f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43 0 0x3fff809008f4 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44 0 0x3fff809008f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45 0 0x3fff809008f5 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46 0 0x3fff809008f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47 0 0x3fff809008f6 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48 0 0x3fff809008f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49 0 0x3fff809008f7 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50 0 0x3fff809008f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51 0 0x3fff809008f8 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52 0 0x3fff809008f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53 0 0x3fff809008f9 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54 0 0x3fff809008fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55 0 0x3fff809008fa 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56 0 0x3fff809008fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57 0 0x3fff809008fb 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58 0 0x3fff809008fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59 0 0x3fff809008fc 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60 0 0x3fff809008fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61 0 0x3fff809008fd 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62 0 0x3fff809008fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15 regBIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63 0 0x3fff809008fe 2 0 5 TPH_ST_LOWER_ENTRY 0 7 TPH_ST_UPPER_ENTRY 8 15