3279 cfgPSWUSCFG0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgPSWUSCFG0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgPSWUSCFG0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgPSWUSCFG0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgPSWUSCFG0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgPSWUSCFG0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgPSWUSCFG0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgPSWUSCFG0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgPSWUSCFG0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgPSWUSCFG0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgPSWUSCFG0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgPSWUSCFG0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgPSWUSCFG0_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgPSWUSCFG0_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgPSWUSCFG0_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgPSWUSCFG0_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgPSWUSCFG0_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgPSWUSCFG0_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgPSWUSCFG0_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgPSWUSCFG0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgPSWUSCFG0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgPSWUSCFG0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 3 0x3e 8 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 cfgEXT_BRIDGE_CNTL 3 0x40 1 0 4294967295 IO_PORT_80_EN 0 0 cfgPSWUSCFG0_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgPSWUSCFG0_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgPSWUSCFG0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgPSWUSCFG0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgPSWUSCFG0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgPSWUSCFG0_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgPSWUSCFG0_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgPSWUSCFG0_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgPSWUSCFG0_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgPSWUSCFG0_DEVICE_STATUS 3 0x62 6 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 cfgPSWUSCFG0_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgPSWUSCFG0_LINK_CNTL 3 0x68 11 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 DRS_SIGNALING_CONTROL 14 15 cfgPSWUSCFG0_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgPSWUSCFG0_DEVICE_CAP2 3 0x7c 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 LN_SYSTEM_CLS 14 15 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 FRS_SUPPORTED 31 31 cfgPSWUSCFG0_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgPSWUSCFG0_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgPSWUSCFG0_LINK_CAP2 3 0x84 7 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 LOWER_SKP_OS_GEN_SUPPORT 9 12 LOWER_SKP_OS_RCV_SUPPORT 16 19 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 DRS_SUPPORTED 31 31 cfgPSWUSCFG0_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgPSWUSCFG0_LINK_STATUS2 3 0x8a 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 DOWNSTREAM_COMPONENT_PRESENCE 12 14 DRS_MESSAGE_RECEIVED 15 15 cfgPSWUSCFG0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgPSWUSCFG0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgPSWUSCFG0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgPSWUSCFG0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgPSWUSCFG0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgPSWUSCFG0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgPSWUSCFG0_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgPSWUSCFG0_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgMSI_MAP_CAP_LIST 3 0xc8 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgMSI_MAP_CAP 3 0xca 3 0 4294967295 EN 0 0 FIXD 1 1 CAP_TYPE 11 15 cfgMSI_MAP_ADDR_LO 3 0xcc 1 0 4294967295 MSI_MAP_ADDR_LO 20 31 cfgMSI_MAP_ADDR_HI 3 0xd0 1 0 4294967295 MSI_MAP_ADDR_HI 0 31 cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 3 0x154 17 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 POISONED_TLP_EGRESS_BLOCKED_STATUS 26 26 cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 3 0x158 17 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 POISONED_TLP_EGRESS_BLOCKED_MASK 26 26 cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 17 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 POISONED_TLP_EGRESS_BLOCKED_SEVERITY 26 26 cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgPSWUSCFG0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgPSWUSCFG0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgPSWUSCFG0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgPSWUSCFG0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_LINK_CNTL3 3 0x274 4 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 ENABLE_LOWER_SKP_OS_GEN 9 15 RESERVED 16 31 cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 3 0x278 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 4 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgPSWUSCFG0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_MC_CAP 3 0x2f4 2 0 4294967295 MC_MAX_GROUP 0 5 MC_ECRC_REGEN_SUPP 15 15 cfgPSWUSCFG0_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgPSWUSCFG0_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgPSWUSCFG0_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgPSWUSCFG0_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgPSWUSCFG0_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgPCIE_MC_OVERLAY_BAR0 3 0x318 2 0 4294967295 MC_OVERLAY_SIZE 0 5 MC_OVERLAY_BAR_0 6 31 cfgPCIE_MC_OVERLAY_BAR1 3 0x31c 1 0 4294967295 MC_OVERLAY_BAR_1 0 31 cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 3 0x320 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_LTR_CAP 3 0x324 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgPSWUSCFG0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgPCIE_L1_PM_SUB_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPCIE_L1_PM_SUB_CAP 3 0x374 8 0 4294967295 PCI_PM_L1_2_SUPPORTED 0 0 PCI_PM_L1_1_SUPPORTED 1 1 ASPM_L1_2_SUPPORTED 2 2 ASPM_L1_1_SUPPORTED 3 3 L1_PM_SUB_SUPPORTED 4 4 PORT_CM_RESTORE_TIME 8 15 PORT_T_POWER_ON_SCALE 16 17 PORT_T_POWER_ON_VALUE 19 23 cfgPCIE_L1_PM_SUB_CNTL 3 0x378 7 0 4294967295 PCI_PM_L1_2_EN 0 0 PCI_PM_L1_1_EN 1 1 ASPM_L1_2_EN 2 2 ASPM_L1_1_EN 3 3 COMMON_MODE_RESTORE_TIME 8 15 LTR_L1_2_THRESHOLD_VALUE 16 25 LTR_L1_2_THRESHOLD_SCALE 29 31 cfgPCIE_L1_PM_SUB_CNTL2 3 0x37c 2 0 4294967295 T_POWER_ON_SCALE 0 1 T_POWER_ON_VALUE 3 7 cfgPCIE_ESM_CAP_LIST 3 0x3c4 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPCIE_ESM_HEADER_1 3 0x3c8 3 0 4294967295 ESM_VENDOR_ID 0 15 ESM_CAP_REV 16 19 ESM_CAP_LEN 20 31 cfgPCIE_ESM_HEADER_2 3 0x3cc 1 0 4294967295 CAP_ID 0 15 cfgPCIE_ESM_STATUS 3 0x3ce 2 0 4294967295 MIN_TIME_IN_EI_VAL 0 8 MIN_TIME_IN_EI_SCALE 9 11 cfgPCIE_ESM_CTRL 3 0x3d0 3 0 4294967295 ESM_GEN_3_DATA_RATE 0 6 ESM_GEN_4_DATA_RATE 8 14 ESM_ENABLED 15 15 cfgPCIE_ESM_CAP_1 3 0x3d4 30 0 4294967295 ESM_8P0G 0 0 ESM_8P1G 1 1 ESM_8P2G 2 2 ESM_8P3G 3 3 ESM_8P4G 4 4 ESM_8P5G 5 5 ESM_8P6G 6 6 ESM_8P7G 7 7 ESM_8P8G 8 8 ESM_8P9G 9 9 ESM_9P0G 10 10 ESM_9P1G 11 11 ESM_9P2G 12 12 ESM_9P3G 13 13 ESM_9P4G 14 14 ESM_9P5G 15 15 ESM_9P6G 16 16 ESM_9P7G 17 17 ESM_9P8G 18 18 ESM_9P9G 19 19 ESM_10P0G 20 20 ESM_10P1G 21 21 ESM_10P2G 22 22 ESM_10P3G 23 23 ESM_10P4G 24 24 ESM_10P5G 25 25 ESM_10P6G 26 26 ESM_10P7G 27 27 ESM_10P8G 28 28 ESM_10P9G 29 29 cfgPCIE_ESM_CAP_2 3 0x3d8 30 0 4294967295 ESM_11P0G 0 0 ESM_11P1G 1 1 ESM_11P2G 2 2 ESM_11P3G 3 3 ESM_11P4G 4 4 ESM_11P5G 5 5 ESM_11P6G 6 6 ESM_11P7G 7 7 ESM_11P8G 8 8 ESM_11P9G 9 9 ESM_12P0G 10 10 ESM_12P1G 11 11 ESM_12P2G 12 12 ESM_12P3G 13 13 ESM_12P4G 14 14 ESM_12P5G 15 15 ESM_12P6G 16 16 ESM_12P7G 17 17 ESM_12P8G 18 18 ESM_12P9G 19 19 ESM_13P0G 20 20 ESM_13P1G 21 21 ESM_13P2G 22 22 ESM_13P3G 23 23 ESM_13P4G 24 24 ESM_13P5G 25 25 ESM_13P6G 26 26 ESM_13P7G 27 27 ESM_13P8G 28 28 ESM_13P9G 29 29 cfgPCIE_ESM_CAP_3 3 0x3dc 20 0 4294967295 ESM_14P0G 0 0 ESM_14P1G 1 1 ESM_14P2G 2 2 ESM_14P3G 3 3 ESM_14P4G 4 4 ESM_14P5G 5 5 ESM_14P6G 6 6 ESM_14P7G 7 7 ESM_14P8G 8 8 ESM_14P9G 9 9 ESM_15P0G 10 10 ESM_15P1G 11 11 ESM_15P2G 12 12 ESM_15P3G 13 13 ESM_15P4G 14 14 ESM_15P5G 15 15 ESM_15P6G 16 16 ESM_15P7G 17 17 ESM_15P8G 18 18 ESM_15P9G 19 19 cfgPCIE_ESM_CAP_4 3 0x3e0 30 0 4294967295 ESM_16P0G 0 0 ESM_16P1G 1 1 ESM_16P2G 2 2 ESM_16P3G 3 3 ESM_16P4G 4 4 ESM_16P5G 5 5 ESM_16P6G 6 6 ESM_16P7G 7 7 ESM_16P8G 8 8 ESM_16P9G 9 9 ESM_17P0G 10 10 ESM_17P1G 11 11 ESM_17P2G 12 12 ESM_17P3G 13 13 ESM_17P4G 14 14 ESM_17P5G 15 15 ESM_17P6G 16 16 ESM_17P7G 17 17 ESM_17P8G 18 18 ESM_17P9G 19 19 ESM_18P0G 20 20 ESM_18P1G 21 21 ESM_18P2G 22 22 ESM_18P3G 23 23 ESM_18P4G 24 24 ESM_18P5G 25 25 ESM_18P6G 26 26 ESM_18P7G 27 27 ESM_18P8G 28 28 ESM_18P9G 29 29 cfgPCIE_ESM_CAP_5 3 0x3e4 30 0 4294967295 ESM_19P0G 0 0 ESM_19P1G 1 1 ESM_19P2G 2 2 ESM_19P3G 3 3 ESM_19P4G 4 4 ESM_19P5G 5 5 ESM_19P6G 6 6 ESM_19P7G 7 7 ESM_19P8G 8 8 ESM_19P9G 9 9 ESM_20P0G 10 10 ESM_20P1G 11 11 ESM_20P2G 12 12 ESM_20P3G 13 13 ESM_20P4G 14 14 ESM_20P5G 15 15 ESM_20P6G 16 16 ESM_20P7G 17 17 ESM_20P8G 18 18 ESM_20P9G 19 19 ESM_21P0G 20 20 ESM_21P1G 21 21 ESM_21P2G 22 22 ESM_21P3G 23 23 ESM_21P4G 24 24 ESM_21P5G 25 25 ESM_21P6G 26 26 ESM_21P7G 27 27 ESM_21P8G 28 28 ESM_21P9G 29 29 cfgPCIE_ESM_CAP_6 3 0x3e8 30 0 4294967295 ESM_22P0G 0 0 ESM_22P1G 1 1 ESM_22P2G 2 2 ESM_22P3G 3 3 ESM_22P4G 4 4 ESM_22P5G 5 5 ESM_22P6G 6 6 ESM_22P7G 7 7 ESM_22P8G 8 8 ESM_22P9G 9 9 ESM_23P0G 10 10 ESM_23P1G 11 11 ESM_23P2G 12 12 ESM_23P3G 13 13 ESM_23P4G 14 14 ESM_23P5G 15 15 ESM_23P6G 16 16 ESM_23P7G 17 17 ESM_23P8G 18 18 ESM_23P9G 19 19 ESM_24P0G 20 20 ESM_24P1G 21 21 ESM_24P2G 22 22 ESM_24P3G 23 23 ESM_24P4G 24 24 ESM_24P5G 25 25 ESM_24P6G 26 26 ESM_24P7G 27 27 ESM_24P8G 28 28 ESM_24P9G 29 29 cfgPCIE_ESM_CAP_7 3 0x3ec 31 0 4294967295 ESM_25P0G 0 0 ESM_25P1G 1 1 ESM_25P2G 2 2 ESM_25P3G 3 3 ESM_25P4G 4 4 ESM_25P5G 5 5 ESM_25P6G 6 6 ESM_25P7G 7 7 ESM_25P8G 8 8 ESM_25P9G 9 9 ESM_26P0G 10 10 ESM_26P1G 11 11 ESM_26P2G 12 12 ESM_26P3G 13 13 ESM_26P4G 14 14 ESM_26P5G 15 15 ESM_26P6G 16 16 ESM_26P7G 17 17 ESM_26P8G 18 18 ESM_26P9G 19 19 ESM_27P0G 20 20 ESM_27P1G 21 21 ESM_27P2G 22 22 ESM_27P3G 23 23 ESM_27P4G 24 24 ESM_27P5G 25 25 ESM_27P6G 26 26 ESM_27P7G 27 27 ESM_27P8G 28 28 ESM_27P9G 29 29 ESM_28P0G 30 30 cfgPSWUSCFG0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_DATA_LINK_FEATURE_CAP 3 0x404 3 0 4294967295 LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED 0 0 LOCAL_DLF_SUPPORTED_22_1 1 22 DLF_EXCHANGE_ENABLE 31 31 cfgPSWUSCFG0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgPCIE_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgPSWUSCFG0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgPSWUSCFG0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgPSWUSCFG0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgPSWUSCFG0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgPSWUSCFG0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgPSWUSCFG0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgPSWUSCFG0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgPCIE_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgPSWUSCFG0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgPSWUSCFG0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgPSWUSCFG0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgPSWUSCFG0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgPSWUSCFG0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 3 0x208 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 3 0x210 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 3 0x218 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 3 0x220 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 3 0x228 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 3 0x230 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 3 0x274 3 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 RESERVED 2 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 3 0x278 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 3 0x2c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 3 0x2c4 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 3 0x2c6 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 3 0x2c8 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 3 0x2cc 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 3 0x320 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 3 0x324 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 3 0x330 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 3 0x334 4 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 3 0x338 6 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 3 0x33a 1 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 3 0x33c 1 0 4294967295 SRIOV_INITIAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 3 0x33e 1 0 4294967295 SRIOV_TOTAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 3 0x340 1 0 4294967295 SRIOV_NUM_VFS 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 3 0x342 1 0 4294967295 SRIOV_FUNC_DEP_LINK 0 7 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 3 0x344 1 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 3 0x346 1 0 4294967295 SRIOV_VF_STRIDE 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 3 0x34a 1 0 4294967295 SRIOV_VF_DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 3 0x34c 1 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 3 0x350 1 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 3 0x354 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 3 0x358 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 3 0x35c 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 3 0x360 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 3 0x364 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 3 0x368 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 0x36c 2 0 4294967295 SRIOV_VF_MIGRATION_STATE_BIF 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_0_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF0_0_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 3 0x4c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 3 0x4c4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 3 0x4c8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 3 0x4cc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 3 0x4d0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 3 0x4d4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 3 0x4d8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 3 0x4dc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 3 0x4e0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 3 0x4e4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 3 0x4e8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 3 0x4ec 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 3 0x4f0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 3 0x500 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 3 0x504 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 3 0x508 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 3 0x50c 18 0 4294967295 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 3 0x510 18 0 4294967295 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 3 0x514 1 0 4294967295 SOFT_PF_FLR 0 0 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 3 0x518 5 0 4294967295 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 3 0x51c 32 0 4294967295 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 3 0x520 32 0 4294967295 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 3 0x524 3 0 4294967295 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 3 0x528 2 0 4294967295 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 3 0x52c 4 0 4294967295 UVDSCH_OFFSET 0 7 VCESCH_OFFSET 8 15 GFXSCH_OFFSET 16 23 UVD1SCH_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 3 0x530 2 0 4294967295 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 3 0x534 2 0 4294967295 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 3 0x538 2 0 4294967295 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 3 0x53c 2 0 4294967295 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 3 0x540 2 0 4294967295 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 3 0x544 2 0 4294967295 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 3 0x548 2 0 4294967295 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 3 0x54c 2 0 4294967295 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 3 0x550 2 0 4294967295 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 3 0x554 2 0 4294967295 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 3 0x558 2 0 4294967295 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 3 0x55c 2 0 4294967295 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 3 0x560 2 0 4294967295 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 3 0x564 2 0 4294967295 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 3 0x568 2 0 4294967295 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 3 0x56c 2 0 4294967295 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 3 0x570 2 0 4294967295 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 3 0x574 2 0 4294967295 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 3 0x578 2 0 4294967295 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 3 0x57c 2 0 4294967295 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 3 0x580 2 0 4294967295 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 3 0x584 2 0 4294967295 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 3 0x588 2 0 4294967295 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 3 0x58c 2 0 4294967295 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 3 0x590 2 0 4294967295 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 3 0x594 2 0 4294967295 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 3 0x598 2 0 4294967295 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 3 0x59c 2 0 4294967295 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 3 0x5a0 2 0 4294967295 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 3 0x5a4 2 0 4294967295 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 3 0x5a8 2 0 4294967295 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 3 0x5ac 2 0 4294967295 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 3 0x5b0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 3 0x5b4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 3 0x5b8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 3 0x5bc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 3 0x5c0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 3 0x5c4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 3 0x5c8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 3 0x5cc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 3 0x5d0 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 3 0x5e0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 3 0x5e4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 3 0x5e8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 3 0x5ec 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 3 0x5f0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 3 0x5f4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 3 0x5f8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 3 0x5fc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 3 0x600 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 3 0x610 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 3 0x614 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 3 0x618 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 3 0x61c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 3 0x620 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 3 0x624 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 3 0x628 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 3 0x62c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 3 0x630 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 3 0x640 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 3 0x644 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 3 0x648 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 3 0x64c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 3 0x650 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 3 0x654 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 3 0x658 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 3 0x65c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 3 0x660 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF1_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF1_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF1_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF1_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF1_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 3 0x3e 1 0 4294967295 MIN_GNT 0 7 cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 3 0x3f 1 0 4294967295 MAX_LAT 0 7 cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 3 0x48 3 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 LENGTH 16 23 cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 3 0x4c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 3 0x200 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 3 0x204 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 3 0x208 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 3 0x20c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 3 0x210 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 3 0x214 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 3 0x218 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 3 0x21c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 3 0x220 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 3 0x224 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 3 0x228 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 3 0x22c 1 0 4294967295 BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 3 0x230 3 0 4294967295 BAR_INDEX 0 2 BAR_TOTAL_NUM 5 7 BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 3 0x240 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 3 0x244 1 0 4294967295 DATA_SELECT 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 3 0x248 6 0 4294967295 BASE_POWER 0 7 DATA_SCALE 8 9 PM_SUB_STATE 10 12 PM_STATE 13 14 TYPE 15 17 POWER_RAIL 18 20 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 3 0x24c 1 0 4294967295 SYSTEM_ALLOCATED 0 0 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 3 0x250 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 3 0x254 5 0 4294967295 SUBSTATE_MAX 0 4 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 3 0x258 1 0 4294967295 TRANS_LAT_INDICATOR_BITS 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 3 0x25c 2 0 4294967295 SUBSTATE_STATUS 0 4 SUBSTATE_CNTL_ENABLED 8 8 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 3 0x25e 1 0 4294967295 SUBSTATE_CNTL 0 4 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 3 0x260 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 3 0x261 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 3 0x262 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 3 0x263 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 3 0x264 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 3 0x265 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 3 0x266 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 3 0x267 1 0 4294967295 SUBSTATE_PWR_ALLOC 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 3 0x274 3 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 RESERVED 2 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 3 0x278 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 3 0x2c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 3 0x2c4 2 0 4294967295 PRI_ENABLE 0 0 PRI_RESET 1 1 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 3 0x2c6 4 0 4294967295 RESPONSE_FAILURE 0 0 UNEXPECTED_PAGE_REQ_GRP_INDEX 1 1 STOPPED 8 8 PRG_RESPONSE_PASID_REQUIRED 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 3 0x2c8 1 0 4294967295 OUTSTAND_PAGE_REQ_CAPACITY 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 3 0x2cc 1 0 4294967295 OUTSTAND_PAGE_REQ_ALLOC 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 3 0x2d0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 3 0x2d4 3 0 4294967295 PASID_EXE_PERMISSION_SUPPORTED 1 1 PASID_PRIV_MODE_SUPPORTED 2 2 MAX_PASID_WIDTH 8 12 cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 3 0x2d6 3 0 4294967295 PASID_ENABLE 0 0 PASID_EXE_PERMISSION_ENABLE 1 1 PASID_PRIV_MODE_SUPPORTED_ENABLE 2 2 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 3 0x2f0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 3 0x2f4 3 0 4294967295 MC_MAX_GROUP 0 5 MC_WIN_SIZE_REQ 8 13 MC_ECRC_REGEN_SUPP 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 3 0x2f6 2 0 4294967295 MC_NUM_GROUP 0 5 MC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 3 0x2f8 2 0 4294967295 MC_INDEX_POS 0 5 MC_BASE_ADDR_0 12 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 3 0x2fc 1 0 4294967295 MC_BASE_ADDR_1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 3 0x300 1 0 4294967295 MC_RECEIVE_0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 3 0x304 1 0 4294967295 MC_RECEIVE_1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 3 0x308 1 0 4294967295 MC_BLOCK_ALL_0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 3 0x30c 1 0 4294967295 MC_BLOCK_ALL_1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 3 0x310 1 0 4294967295 MC_BLOCK_UNTRANSLATED_0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 3 0x314 1 0 4294967295 MC_BLOCK_UNTRANSLATED_1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 3 0x320 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 3 0x324 4 0 4294967295 LTR_MAX_S_LATENCY_VALUE 0 9 LTR_MAX_S_LATENCY_SCALE 10 12 LTR_MAX_NS_LATENCY_VALUE 16 25 LTR_MAX_NS_LATENCY_SCALE 26 28 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 3 0x330 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 3 0x334 4 0 4294967295 SRIOV_VF_MIGRATION_CAP 0 0 SRIOV_ARI_CAP_HIERARCHY_PRESERVED 1 1 SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED 2 2 SRIOV_VF_MIGRATION_INTR_MSG_NUM 21 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 3 0x338 6 0 4294967295 SRIOV_VF_ENABLE 0 0 SRIOV_VF_MIGRATION_ENABLE 1 1 SRIOV_VF_MIGRATION_INTR_ENABLE 2 2 SRIOV_VF_MSE 3 3 SRIOV_ARI_CAP_HIERARCHY 4 4 SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE 5 5 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 3 0x33a 1 0 4294967295 SRIOV_VF_MIGRATION_STATUS 0 0 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 3 0x33c 1 0 4294967295 SRIOV_INITIAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 3 0x33e 1 0 4294967295 SRIOV_TOTAL_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 3 0x340 1 0 4294967295 SRIOV_NUM_VFS 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 3 0x342 1 0 4294967295 SRIOV_FUNC_DEP_LINK 0 7 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 3 0x344 1 0 4294967295 SRIOV_FIRST_VF_OFFSET 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 3 0x346 1 0 4294967295 SRIOV_VF_STRIDE 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 3 0x34a 1 0 4294967295 SRIOV_VF_DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 3 0x34c 1 0 4294967295 SRIOV_SUPPORTED_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 3 0x350 1 0 4294967295 SRIOV_SYSTEM_PAGE_SIZE 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 3 0x354 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 3 0x358 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 3 0x35c 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 3 0x360 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 3 0x364 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 3 0x368 1 0 4294967295 VF_BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 0x36c 2 0 4294967295 SRIOV_VF_MIGRATION_STATE_BIF 0 2 SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 3 0x370 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 3 0x374 6 0 4294967295 TPH_REQR_NO_ST_MODE_SUPPORTED 0 0 TPH_REQR_INT_VEC_MODE_SUPPORTED 1 1 TPH_REQR_DEV_SPC_MODE_SUPPORTED 2 2 TPH_REQR_EXTND_TPH_REQR_SUPPORED 8 8 TPH_REQR_ST_TABLE_LOCATION 9 10 TPH_REQR_ST_TABLE_SIZE 16 26 cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 3 0x378 2 0 4294967295 TPH_REQR_ST_MODE_SEL 0 2 TPH_REQR_EN 8 9 cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_0_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_EPF1_0_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 3 0x4c0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 3 0x4c4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 3 0x4c8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 3 0x4cc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 3 0x4d0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 3 0x4d4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 3 0x4d8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 3 0x4dc 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 3 0x4e0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 3 0x4e4 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 3 0x4e8 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 3 0x4ec 1 0 4294967295 VF_BAR_SIZE_SUPPORTED 4 23 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 3 0x4f0 3 0 4294967295 VF_BAR_INDEX 0 2 VF_BAR_TOTAL_NUM 5 7 VF_BAR_SIZE 8 13 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 3 0x500 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 3 0x504 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 3 0x508 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 3 0x50c 18 0 4294967295 GFX_CMD_COMPLETE_INTR_EN 0 0 GFX_HANG_SELF_RECOVERED_INTR_EN 1 1 GFX_HANG_NEED_FLR_INTR_EN 2 2 GFX_VM_BUSY_TRANSITION_INTR_EN 3 3 UVD_CMD_COMPLETE_INTR_EN 8 8 UVD_HANG_SELF_RECOVERED_INTR_EN 9 9 UVD_HANG_NEED_FLR_INTR_EN 10 10 UVD_VM_BUSY_TRANSITION_INTR_EN 11 11 UVD1_CMD_COMPLETE_INTR_EN 12 12 UVD1_HANG_SELF_RECOVERED_INTR_EN 13 13 UVD1_HANG_NEED_FLR_INTR_EN 14 14 UVD1_VM_BUSY_TRANSITION_INTR_EN 15 15 VCE_CMD_COMPLETE_INTR_EN 16 16 VCE_HANG_SELF_RECOVERED_INTR_EN 17 17 VCE_HANG_NEED_FLR_INTR_EN 18 18 VCE_VM_BUSY_TRANSITION_INTR_EN 19 19 HVVM_MAILBOX_TRN_ACK_INTR_EN 24 24 HVVM_MAILBOX_RCV_VALID_INTR_EN 25 25 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 3 0x510 18 0 4294967295 GFX_CMD_COMPLETE_INTR_STATUS 0 0 GFX_HANG_SELF_RECOVERED_INTR_STATUS 1 1 GFX_HANG_NEED_FLR_INTR_STATUS 2 2 GFX_VM_BUSY_TRANSITION_INTR_STATUS 3 3 UVD_CMD_COMPLETE_INTR_STATUS 8 8 UVD_HANG_SELF_RECOVERED_INTR_STATUS 9 9 UVD_HANG_NEED_FLR_INTR_STATUS 10 10 UVD_VM_BUSY_TRANSITION_INTR_STATUS 11 11 UVD1_CMD_COMPLETE_INTR_STATUS 12 12 UVD1_HANG_SELF_RECOVERED_INTR_STATUS 13 13 UVD1_HANG_NEED_FLR_INTR_STATUS 14 14 UVD1_VM_BUSY_TRANSITION_INTR_STATUS 15 15 VCE_CMD_COMPLETE_INTR_STATUS 16 16 VCE_HANG_SELF_RECOVERED_INTR_STATUS 17 17 VCE_HANG_NEED_FLR_INTR_STATUS 18 18 VCE_VM_BUSY_TRANSITION_INTR_STATUS 19 19 HVVM_MAILBOX_TRN_ACK_INTR_STATUS 24 24 HVVM_MAILBOX_RCV_VALID_INTR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 3 0x514 1 0 4294967295 SOFT_PF_FLR 0 0 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 3 0x518 5 0 4294967295 VF_INDEX 0 7 TRN_MSG_DATA 8 11 TRN_MSG_VALID 15 15 RCV_MSG_DATA 16 19 RCV_MSG_ACK 24 24 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 3 0x51c 32 0 4294967295 VF0_TRN_ACK 0 0 VF0_RCV_VALID 1 1 VF1_TRN_ACK 2 2 VF1_RCV_VALID 3 3 VF2_TRN_ACK 4 4 VF2_RCV_VALID 5 5 VF3_TRN_ACK 6 6 VF3_RCV_VALID 7 7 VF4_TRN_ACK 8 8 VF4_RCV_VALID 9 9 VF5_TRN_ACK 10 10 VF5_RCV_VALID 11 11 VF6_TRN_ACK 12 12 VF6_RCV_VALID 13 13 VF7_TRN_ACK 14 14 VF7_RCV_VALID 15 15 VF8_TRN_ACK 16 16 VF8_RCV_VALID 17 17 VF9_TRN_ACK 18 18 VF9_RCV_VALID 19 19 VF10_TRN_ACK 20 20 VF10_RCV_VALID 21 21 VF11_TRN_ACK 22 22 VF11_RCV_VALID 23 23 VF12_TRN_ACK 24 24 VF12_RCV_VALID 25 25 VF13_TRN_ACK 26 26 VF13_RCV_VALID 27 27 VF14_TRN_ACK 28 28 VF14_RCV_VALID 29 29 VF15_TRN_ACK 30 30 VF15_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 3 0x520 32 0 4294967295 VF16_TRN_ACK 0 0 VF16_RCV_VALID 1 1 VF17_TRN_ACK 2 2 VF17_RCV_VALID 3 3 VF18_TRN_ACK 4 4 VF18_RCV_VALID 5 5 VF19_TRN_ACK 6 6 VF19_RCV_VALID 7 7 VF20_TRN_ACK 8 8 VF20_RCV_VALID 9 9 VF21_TRN_ACK 10 10 VF21_RCV_VALID 11 11 VF22_TRN_ACK 12 12 VF22_RCV_VALID 13 13 VF23_TRN_ACK 14 14 VF23_RCV_VALID 15 15 VF24_TRN_ACK 16 16 VF24_RCV_VALID 17 17 VF25_TRN_ACK 18 18 VF25_RCV_VALID 19 19 VF26_TRN_ACK 20 20 VF26_RCV_VALID 21 21 VF27_TRN_ACK 22 22 VF27_RCV_VALID 23 23 VF28_TRN_ACK 24 24 VF28_RCV_VALID 25 25 VF29_TRN_ACK 26 26 VF29_RCV_VALID 27 27 VF30_TRN_ACK 28 28 VF30_RCV_VALID 29 29 PF_TRN_ACK 30 30 PF_RCV_VALID 31 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 3 0x524 3 0 4294967295 CONTEXT_SIZE 0 6 LOC 7 7 CONTEXT_OFFSET 10 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 3 0x528 2 0 4294967295 TOTAL_FB_AVAILABLE 0 15 TOTAL_FB_CONSUMED 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 3 0x52c 4 0 4294967295 UVDSCH_OFFSET 0 7 VCESCH_OFFSET 8 15 GFXSCH_OFFSET 16 23 UVD1SCH_OFFSET 24 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 3 0x530 2 0 4294967295 P2P_OVER_XGMI_ENABLE_VF 0 30 P2P_OVER_XGMI_ENABLE_PF 31 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 3 0x534 2 0 4294967295 VF0_FB_SIZE 0 15 VF0_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 3 0x538 2 0 4294967295 VF1_FB_SIZE 0 15 VF1_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 3 0x53c 2 0 4294967295 VF2_FB_SIZE 0 15 VF2_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 3 0x540 2 0 4294967295 VF3_FB_SIZE 0 15 VF3_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 3 0x544 2 0 4294967295 VF4_FB_SIZE 0 15 VF4_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 3 0x548 2 0 4294967295 VF5_FB_SIZE 0 15 VF5_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 3 0x54c 2 0 4294967295 VF6_FB_SIZE 0 15 VF6_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 3 0x550 2 0 4294967295 VF7_FB_SIZE 0 15 VF7_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 3 0x554 2 0 4294967295 VF8_FB_SIZE 0 15 VF8_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 3 0x558 2 0 4294967295 VF9_FB_SIZE 0 15 VF9_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 3 0x55c 2 0 4294967295 VF10_FB_SIZE 0 15 VF10_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 3 0x560 2 0 4294967295 VF11_FB_SIZE 0 15 VF11_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 3 0x564 2 0 4294967295 VF12_FB_SIZE 0 15 VF12_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 3 0x568 2 0 4294967295 VF13_FB_SIZE 0 15 VF13_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 3 0x56c 2 0 4294967295 VF14_FB_SIZE 0 15 VF14_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 3 0x570 2 0 4294967295 VF15_FB_SIZE 0 15 VF15_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 3 0x574 2 0 4294967295 VF16_FB_SIZE 0 15 VF16_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 3 0x578 2 0 4294967295 VF17_FB_SIZE 0 15 VF17_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 3 0x57c 2 0 4294967295 VF18_FB_SIZE 0 15 VF18_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 3 0x580 2 0 4294967295 VF19_FB_SIZE 0 15 VF19_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 3 0x584 2 0 4294967295 VF20_FB_SIZE 0 15 VF20_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 3 0x588 2 0 4294967295 VF21_FB_SIZE 0 15 VF21_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 3 0x58c 2 0 4294967295 VF22_FB_SIZE 0 15 VF22_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 3 0x590 2 0 4294967295 VF23_FB_SIZE 0 15 VF23_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 3 0x594 2 0 4294967295 VF24_FB_SIZE 0 15 VF24_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 3 0x598 2 0 4294967295 VF25_FB_SIZE 0 15 VF25_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 3 0x59c 2 0 4294967295 VF26_FB_SIZE 0 15 VF26_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 3 0x5a0 2 0 4294967295 VF27_FB_SIZE 0 15 VF27_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 3 0x5a4 2 0 4294967295 VF28_FB_SIZE 0 15 VF28_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 3 0x5a8 2 0 4294967295 VF29_FB_SIZE 0 15 VF29_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 3 0x5ac 2 0 4294967295 VF30_FB_SIZE 0 15 VF30_FB_OFFSET 16 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 3 0x5b0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 3 0x5b4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 3 0x5b8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 3 0x5bc 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 3 0x5c0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 3 0x5c4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 3 0x5c8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 3 0x5cc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 3 0x5d0 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 3 0x5e0 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 3 0x5e4 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 3 0x5e8 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 3 0x5ec 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 3 0x5f0 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 3 0x5f4 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 3 0x5f8 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 3 0x5fc 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 3 0x600 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 3 0x610 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 3 0x614 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 3 0x618 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 3 0x61c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 3 0x620 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 3 0x624 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 3 0x628 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 3 0x62c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 3 0x630 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 3 0x640 1 0 4294967295 DW0 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 3 0x644 1 0 4294967295 DW1 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 3 0x648 1 0 4294967295 DW2 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 3 0x64c 1 0 4294967295 DW3 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 3 0x650 1 0 4294967295 DW4 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 3 0x654 1 0 4294967295 DW5 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 3 0x658 1 0 4294967295 DW6 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 3 0x65c 1 0 4294967295 DW7 0 31 cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 3 0x660 1 0 4294967295 DW8 0 31 cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_SWDS0_COMMAND 3 0x4 11 0 4294967295 IOEN_DN 0 0 MEMEN_DN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_SWDS0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_SWDS0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_SWDS0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_SWDS0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 3 0x18 4 0 4294967295 PRIMARY_BUS 0 7 SECONDARY_BUS 8 15 SUB_BUS_NUM 16 23 SECONDARY_LATENCY_TIMER 24 31 cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 3 0x1c 4 0 4294967295 IO_BASE_TYPE 0 3 IO_BASE 4 7 IO_LIMIT_TYPE 8 11 IO_LIMIT 12 15 cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 3 0x1e 9 0 4294967295 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 RECEIVED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 3 0x20 4 0 4294967295 MEM_BASE_TYPE 0 3 MEM_BASE_31_20 4 15 MEM_LIMIT_TYPE 16 19 MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 3 0x24 4 0 4294967295 PREF_MEM_BASE_TYPE 0 3 PREF_MEM_BASE_31_20 4 15 PREF_MEM_LIMIT_TYPE 16 19 PREF_MEM_LIMIT_31_20 20 31 cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 3 0x28 1 0 4294967295 PREF_BASE_UPPER 0 31 cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 3 0x2c 1 0 4294967295 PREF_LIMIT_UPPER 0 31 cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 3 0x30 2 0 4294967295 IO_BASE_31_16 0 15 IO_LIMIT_31_16 16 31 cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 3 0x3e 8 0 4294967295 PARITY_RESPONSE_EN 0 0 SERR_EN 1 1 ISA_EN 2 2 VGA_EN 3 3 VGA_DEC 4 4 MASTER_ABORT_MODE 5 5 SECONDARY_BUS_RESET 6 6 FAST_B2B_EN 7 7 cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 3 0x50 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 3 0x52 8 0 4294967295 VERSION 0 2 PME_CLOCK 3 3 IMMEDIATE_READINESS_ON_RETURN_TO_D0 4 4 DEV_SPECIFIC_INIT 5 5 AUX_CURRENT 6 8 D1_SUPPORT 9 9 D2_SUPPORT 10 10 PME_SUPPORT 11 15 cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 3 0x54 9 0 4294967295 POWER_STATE 0 1 NO_SOFT_RESET 3 3 PME_EN 8 8 DATA_SELECT 9 12 DATA_SCALE 13 14 PME_STATUS 15 15 B2_B3_SUPPORT 22 22 BUS_PWR_EN 23 23 PMI_DATA 24 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 3 0x58 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 3 0x5a 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 3 0x5c 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 3 0x60 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 BRIDGE_CFG_RETRY_EN 15 15 cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 3 0x62 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 3 0x64 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 3 0x68 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 3 0x6a 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 3 0x6c 12 0 4294967295 ATTN_BUTTON_PRESENT 0 0 PWR_CONTROLLER_PRESENT 1 1 MRL_SENSOR_PRESENT 2 2 ATTN_INDICATOR_PRESENT 3 3 PWR_INDICATOR_PRESENT 4 4 HOTPLUG_SURPRISE 5 5 HOTPLUG_CAPABLE 6 6 SLOT_PWR_LIMIT_VALUE 7 14 SLOT_PWR_LIMIT_SCALE 15 16 ELECTROMECH_INTERLOCK_PRESENT 17 17 NO_COMMAND_COMPLETED_SUPPORTED 18 18 PHYSICAL_SLOT_NUM 19 31 cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 3 0x70 11 0 4294967295 ATTN_BUTTON_PRESSED_EN 0 0 PWR_FAULT_DETECTED_EN 1 1 MRL_SENSOR_CHANGED_EN 2 2 PRESENCE_DETECT_CHANGED_EN 3 3 COMMAND_COMPLETED_INTR_EN 4 4 HOTPLUG_INTR_EN 5 5 ATTN_INDICATOR_CNTL 6 7 PWR_INDICATOR_CNTL 8 9 PWR_CONTROLLER_CNTL 10 10 ELECTROMECH_INTERLOCK_CNTL 11 11 DL_STATE_CHANGED_EN 12 12 cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 3 0x72 9 0 4294967295 ATTN_BUTTON_PRESSED 0 0 PWR_FAULT_DETECTED 1 1 MRL_SENSOR_CHANGED 2 2 PRESENCE_DETECT_CHANGED 3 3 COMMAND_COMPLETED 4 4 MRL_SENSOR_STATE 5 5 PRESENCE_DETECT_STATE 6 6 ELECTROMECH_INTERLOCK_STATUS 7 7 DL_STATE_CHANGED 8 8 cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 3 0x7c 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 3 0x80 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 3 0x82 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 3 0x84 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 3 0x88 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 3 0x8a 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 3 0x8c 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 3 0x90 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 3 0x92 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 3 0xc4 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 3 0x110 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 3 0x114 4 0 4294967295 EXT_VC_COUNT 0 2 LOW_PRIORITY_EXT_VC_COUNT 4 6 REF_CLK 8 9 PORT_ARB_TABLE_ENTRY_SIZE 10 11 cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 3 0x118 2 0 4294967295 VC_ARB_CAP 0 7 VC_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 3 0x11c 2 0 4294967295 LOAD_VC_ARB_TABLE 0 0 VC_ARB_SELECT 1 3 cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 3 0x11e 1 0 4294967295 VC_ARB_TABLE_STATUS 0 0 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 3 0x120 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 3 0x124 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 3 0x12a 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 3 0x12c 4 0 4294967295 PORT_ARB_CAP 0 7 REJECT_SNOOP_TRANS 15 15 MAX_TIME_SLOTS 16 21 PORT_ARB_TABLE_OFFSET 24 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 3 0x130 6 0 4294967295 TC_VC_MAP_TC0 0 0 TC_VC_MAP_TC1_7 1 7 LOAD_PORT_ARB_TABLE 16 16 PORT_ARB_SELECT 17 19 VC_ID 24 26 VC_ENABLE 31 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 3 0x136 2 0 4294967295 PORT_ARB_TABLE_STATUS 0 0 VC_NEGOTIATION_PENDING 1 1 cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 3 0x140 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 3 0x144 1 0 4294967295 SERIAL_NUMBER_LO 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 3 0x148 1 0 4294967295 SERIAL_NUMBER_HI 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 3 0x270 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 3 0x274 3 0 4294967295 PERFORM_EQUALIZATION 0 0 LINK_EQUALIZATION_REQ_INT_EN 1 1 RESERVED 2 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 3 0x278 2 0 4294967295 LANE_ERROR_STATUS_BITS 0 15 RESERVED 16 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 3 0x27c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 3 0x27e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 3 0x280 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 3 0x282 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 3 0x284 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 3 0x286 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 3 0x288 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 3 0x28a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 3 0x28c 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 3 0x28e 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 3 0x290 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 3 0x292 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 3 0x294 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 3 0x296 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 3 0x298 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 3 0x29a 5 0 4294967295 DOWNSTREAM_PORT_TX_PRESET 0 3 DOWNSTREAM_PORT_RX_PRESET_HINT 4 6 UPSTREAM_PORT_TX_PRESET 8 11 UPSTREAM_PORT_RX_PRESET_HINT 12 14 RESERVED 15 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 3 0x2a0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 3 0x2a4 8 0 4294967295 SOURCE_VALIDATION 0 0 TRANSLATION_BLOCKING 1 1 P2P_REQUEST_REDIRECT 2 2 P2P_COMPLETION_REDIRECT 3 3 UPSTREAM_FORWARDING 4 4 P2P_EGRESS_CONTROL 5 5 DIRECT_TRANSLATED_P2P 6 6 EGRESS_CONTROL_VECTOR_SIZE 8 15 cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 3 0x2a6 7 0 4294967295 SOURCE_VALIDATION_EN 0 0 TRANSLATION_BLOCKING_EN 1 1 P2P_REQUEST_REDIRECT_EN 2 2 P2P_COMPLETION_REDIRECT_EN 3 3 UPSTREAM_FORWARDING_EN 4 4 P2P_EGRESS_CONTROL_EN 5 5 DIRECT_TRANSLATED_P2P_EN 6 6 cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 3 0x400 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 3 0x404 2 0 4294967295 LOCAL_DLF_SUPPORTED 0 22 DLF_EXCHANGE_ENABLE 31 31 cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 3 0x408 2 0 4294967295 REMOTE_DLF_SUPPORTED 0 22 REMOTE_DLF_SUPPORTED_VALID 31 31 cfgBIF_CFG_DEV0_SWDS0_PHY_16GT_ENH_CAP_LIST 3 0x410 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 3 0x414 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 3 0x418 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 3 0x41c 5 0 4294967295 EQUALIZATION_COMPLETE_16GT 0 0 EQUALIZATION_PHASE1_SUCCESS_16GT 1 1 EQUALIZATION_PHASE2_SUCCESS_16GT 2 2 EQUALIZATION_PHASE3_SUCCESS_16GT 3 3 LINK_EQUALIZATION_REQUEST_16GT 4 4 cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 3 0x420 1 0 4294967295 LOCAL_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 3 0x424 1 0 4294967295 RTM1_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 3 0x428 1 0 4294967295 RTM2_PARITY_MISMATCH_STATUS_BITS 0 15 cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 3 0x430 2 0 4294967295 LANE_0_DSP_16GT_TX_PRESET 0 3 LANE_0_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 3 0x431 2 0 4294967295 LANE_1_DSP_16GT_TX_PRESET 0 3 LANE_1_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 3 0x432 2 0 4294967295 LANE_2_DSP_16GT_TX_PRESET 0 3 LANE_2_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 3 0x433 2 0 4294967295 LANE_3_DSP_16GT_TX_PRESET 0 3 LANE_3_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 3 0x434 2 0 4294967295 LANE_4_DSP_16GT_TX_PRESET 0 3 LANE_4_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 3 0x435 2 0 4294967295 LANE_5_DSP_16GT_TX_PRESET 0 3 LANE_5_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 3 0x436 2 0 4294967295 LANE_6_DSP_16GT_TX_PRESET 0 3 LANE_6_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 3 0x437 2 0 4294967295 LANE_7_DSP_16GT_TX_PRESET 0 3 LANE_7_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 3 0x438 2 0 4294967295 LANE_8_DSP_16GT_TX_PRESET 0 3 LANE_8_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 3 0x439 2 0 4294967295 LANE_9_DSP_16GT_TX_PRESET 0 3 LANE_9_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 3 0x43a 2 0 4294967295 LANE_10_DSP_16GT_TX_PRESET 0 3 LANE_10_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 3 0x43b 2 0 4294967295 LANE_11_DSP_16GT_TX_PRESET 0 3 LANE_11_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 3 0x43c 2 0 4294967295 LANE_12_DSP_16GT_TX_PRESET 0 3 LANE_12_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 3 0x43d 2 0 4294967295 LANE_13_DSP_16GT_TX_PRESET 0 3 LANE_13_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 3 0x43e 2 0 4294967295 LANE_14_DSP_16GT_TX_PRESET 0 3 LANE_14_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 3 0x43f 2 0 4294967295 LANE_15_DSP_16GT_TX_PRESET 0 3 LANE_15_USP_16GT_TX_PRESET 4 7 cfgBIF_CFG_DEV0_SWDS0_MARGINING_ENH_CAP_LIST 3 0x440 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 3 0x444 1 0 4294967295 MARGINING_USES_SOFTWARE 0 0 cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 3 0x446 2 0 4294967295 MARGINING_READY 0 0 MARGINING_SOFTWARE_READY 1 1 cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 3 0x448 4 0 4294967295 LANE_0_RECEIVER_NUMBER 0 2 LANE_0_MARGIN_TYPE 3 5 LANE_0_USAGE_MODEL 6 6 LANE_0_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 3 0x44a 4 0 4294967295 LANE_0_RECEIVER_NUMBER_STATUS 0 2 LANE_0_MARGIN_TYPE_STATUS 3 5 LANE_0_USAGE_MODEL_STATUS 6 6 LANE_0_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 3 0x44c 4 0 4294967295 LANE_1_RECEIVER_NUMBER 0 2 LANE_1_MARGIN_TYPE 3 5 LANE_1_USAGE_MODEL 6 6 LANE_1_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 3 0x44e 4 0 4294967295 LANE_1_RECEIVER_NUMBER_STATUS 0 2 LANE_1_MARGIN_TYPE_STATUS 3 5 LANE_1_USAGE_MODEL_STATUS 6 6 LANE_1_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 3 0x450 4 0 4294967295 LANE_2_RECEIVER_NUMBER 0 2 LANE_2_MARGIN_TYPE 3 5 LANE_2_USAGE_MODEL 6 6 LANE_2_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 3 0x452 4 0 4294967295 LANE_2_RECEIVER_NUMBER_STATUS 0 2 LANE_2_MARGIN_TYPE_STATUS 3 5 LANE_2_USAGE_MODEL_STATUS 6 6 LANE_2_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 3 0x454 4 0 4294967295 LANE_3_RECEIVER_NUMBER 0 2 LANE_3_MARGIN_TYPE 3 5 LANE_3_USAGE_MODEL 6 6 LANE_3_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 3 0x456 4 0 4294967295 LANE_3_RECEIVER_NUMBER_STATUS 0 2 LANE_3_MARGIN_TYPE_STATUS 3 5 LANE_3_USAGE_MODEL_STATUS 6 6 LANE_3_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 3 0x458 4 0 4294967295 LANE_4_RECEIVER_NUMBER 0 2 LANE_4_MARGIN_TYPE 3 5 LANE_4_USAGE_MODEL 6 6 LANE_4_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 3 0x45a 4 0 4294967295 LANE_4_RECEIVER_NUMBER_STATUS 0 2 LANE_4_MARGIN_TYPE_STATUS 3 5 LANE_4_USAGE_MODEL_STATUS 6 6 LANE_4_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 3 0x45c 4 0 4294967295 LANE_5_RECEIVER_NUMBER 0 2 LANE_5_MARGIN_TYPE 3 5 LANE_5_USAGE_MODEL 6 6 LANE_5_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 3 0x45e 4 0 4294967295 LANE_5_RECEIVER_NUMBER_STATUS 0 2 LANE_5_MARGIN_TYPE_STATUS 3 5 LANE_5_USAGE_MODEL_STATUS 6 6 LANE_5_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 3 0x460 4 0 4294967295 LANE_6_RECEIVER_NUMBER 0 2 LANE_6_MARGIN_TYPE 3 5 LANE_6_USAGE_MODEL 6 6 LANE_6_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 3 0x462 4 0 4294967295 LANE_6_RECEIVER_NUMBER_STATUS 0 2 LANE_6_MARGIN_TYPE_STATUS 3 5 LANE_6_USAGE_MODEL_STATUS 6 6 LANE_6_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 3 0x464 4 0 4294967295 LANE_7_RECEIVER_NUMBER 0 2 LANE_7_MARGIN_TYPE 3 5 LANE_7_USAGE_MODEL 6 6 LANE_7_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 3 0x466 4 0 4294967295 LANE_7_RECEIVER_NUMBER_STATUS 0 2 LANE_7_MARGIN_TYPE_STATUS 3 5 LANE_7_USAGE_MODEL_STATUS 6 6 LANE_7_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 3 0x468 4 0 4294967295 LANE_8_RECEIVER_NUMBER 0 2 LANE_8_MARGIN_TYPE 3 5 LANE_8_USAGE_MODEL 6 6 LANE_8_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 3 0x46a 4 0 4294967295 LANE_8_RECEIVER_NUMBER_STATUS 0 2 LANE_8_MARGIN_TYPE_STATUS 3 5 LANE_8_USAGE_MODEL_STATUS 6 6 LANE_8_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 3 0x46c 4 0 4294967295 LANE_9_RECEIVER_NUMBER 0 2 LANE_9_MARGIN_TYPE 3 5 LANE_9_USAGE_MODEL 6 6 LANE_9_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 3 0x46e 4 0 4294967295 LANE_9_RECEIVER_NUMBER_STATUS 0 2 LANE_9_MARGIN_TYPE_STATUS 3 5 LANE_9_USAGE_MODEL_STATUS 6 6 LANE_9_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 3 0x470 4 0 4294967295 LANE_10_RECEIVER_NUMBER 0 2 LANE_10_MARGIN_TYPE 3 5 LANE_10_USAGE_MODEL 6 6 LANE_10_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 3 0x472 4 0 4294967295 LANE_10_RECEIVER_NUMBER_STATUS 0 2 LANE_10_MARGIN_TYPE_STATUS 3 5 LANE_10_USAGE_MODEL_STATUS 6 6 LANE_10_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 3 0x474 4 0 4294967295 LANE_11_RECEIVER_NUMBER 0 2 LANE_11_MARGIN_TYPE 3 5 LANE_11_USAGE_MODEL 6 6 LANE_11_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 3 0x476 4 0 4294967295 LANE_11_RECEIVER_NUMBER_STATUS 0 2 LANE_11_MARGIN_TYPE_STATUS 3 5 LANE_11_USAGE_MODEL_STATUS 6 6 LANE_11_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 3 0x478 4 0 4294967295 LANE_12_RECEIVER_NUMBER 0 2 LANE_12_MARGIN_TYPE 3 5 LANE_12_USAGE_MODEL 6 6 LANE_12_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 3 0x47a 4 0 4294967295 LANE_12_RECEIVER_NUMBER_STATUS 0 2 LANE_12_MARGIN_TYPE_STATUS 3 5 LANE_12_USAGE_MODEL_STATUS 6 6 LANE_12_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 3 0x47c 4 0 4294967295 LANE_13_RECEIVER_NUMBER 0 2 LANE_13_MARGIN_TYPE 3 5 LANE_13_USAGE_MODEL 6 6 LANE_13_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 3 0x47e 4 0 4294967295 LANE_13_RECEIVER_NUMBER_STATUS 0 2 LANE_13_MARGIN_TYPE_STATUS 3 5 LANE_13_USAGE_MODEL_STATUS 6 6 LANE_13_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 3 0x480 4 0 4294967295 LANE_14_RECEIVER_NUMBER 0 2 LANE_14_MARGIN_TYPE 3 5 LANE_14_USAGE_MODEL 6 6 LANE_14_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 3 0x482 4 0 4294967295 LANE_14_RECEIVER_NUMBER_STATUS 0 2 LANE_14_MARGIN_TYPE_STATUS 3 5 LANE_14_USAGE_MODEL_STATUS 6 6 LANE_14_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 3 0x484 4 0 4294967295 LANE_15_RECEIVER_NUMBER 0 2 LANE_15_MARGIN_TYPE 3 5 LANE_15_USAGE_MODEL 6 6 LANE_15_MARGIN_PAYLOAD 8 15 cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 3 0x486 4 0 4294967295 LANE_15_RECEIVER_NUMBER_STATUS 0 2 LANE_15_MARGIN_TYPE_STATUS 3 5 LANE_15_USAGE_MODEL_STATUS 6 6 LANE_15_MARGIN_PAYLOAD_STATUS 8 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 3 0x0 1 0 4294967295 VENDOR_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 3 0x2 1 0 4294967295 DEVICE_ID 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 3 0x4 11 0 4294967295 IO_ACCESS_EN 0 0 MEM_ACCESS_EN 1 1 BUS_MASTER_EN 2 2 SPECIAL_CYCLE_EN 3 3 MEM_WRITE_INVALIDATE_EN 4 4 PAL_SNOOP_EN 5 5 PARITY_ERROR_RESPONSE 6 6 AD_STEPPING 7 7 SERR_EN 8 8 FAST_B2B_EN 9 9 INT_DIS 10 10 cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 3 0x6 12 0 4294967295 IMMEDIATE_READINESS 0 0 INT_STATUS 3 3 CAP_LIST 4 4 PCI_66_CAP 5 5 FAST_BACK_CAPABLE 7 7 MASTER_DATA_PARITY_ERROR 8 8 DEVSEL_TIMING 9 10 SIGNAL_TARGET_ABORT 11 11 RECEIVED_TARGET_ABORT 12 12 RECEIVED_MASTER_ABORT 13 13 SIGNALED_SYSTEM_ERROR 14 14 PARITY_ERROR_DETECTED 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 3 0x8 2 0 4294967295 MINOR_REV_ID 0 3 MAJOR_REV_ID 4 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 3 0x9 1 0 4294967295 PROG_INTERFACE 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 3 0xa 1 0 4294967295 SUB_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 3 0xb 1 0 4294967295 BASE_CLASS 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 3 0xc 1 0 4294967295 CACHE_LINE_SIZE 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 3 0xd 1 0 4294967295 LATENCY_TIMER 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 3 0xe 2 0 4294967295 HEADER_TYPE 0 6 DEVICE_TYPE 7 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 3 0xf 3 0 4294967295 BIST_COMP 0 3 BIST_STRT 6 6 BIST_CAP 7 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 3 0x10 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 3 0x14 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 3 0x18 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 3 0x1c 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 3 0x20 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 3 0x24 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 3 0x2c 2 0 4294967295 SUBSYSTEM_VENDOR_ID 0 15 SUBSYSTEM_ID 16 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 3 0x30 1 0 4294967295 BASE_ADDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 3 0x34 1 0 4294967295 CAP_PTR 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 3 0x3c 1 0 4294967295 INTERRUPT_LINE 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 3 0x3d 1 0 4294967295 INTERRUPT_PIN 0 7 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 3 0x64 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 3 0x66 4 0 4294967295 VERSION 0 3 DEVICE_TYPE 4 7 SLOT_IMPLEMENTED 8 8 INT_MESSAGE_NUM 9 13 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 3 0x68 9 0 4294967295 MAX_PAYLOAD_SUPPORT 0 2 PHANTOM_FUNC 3 4 EXTENDED_TAG 5 5 L0S_ACCEPTABLE_LATENCY 6 8 L1_ACCEPTABLE_LATENCY 9 11 ROLE_BASED_ERR_REPORTING 15 15 CAPTURED_SLOT_POWER_LIMIT 18 25 CAPTURED_SLOT_POWER_SCALE 26 27 FLR_CAPABLE 28 28 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 3 0x6c 12 0 4294967295 CORR_ERR_EN 0 0 NON_FATAL_ERR_EN 1 1 FATAL_ERR_EN 2 2 USR_REPORT_EN 3 3 RELAXED_ORD_EN 4 4 MAX_PAYLOAD_SIZE 5 7 EXTENDED_TAG_EN 8 8 PHANTOM_FUNC_EN 9 9 AUX_POWER_PM_EN 10 10 NO_SNOOP_EN 11 11 MAX_READ_REQUEST_SIZE 12 14 INITIATE_FLR 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 3 0x6e 7 0 4294967295 CORR_ERR 0 0 NON_FATAL_ERR 1 1 FATAL_ERR 2 2 USR_DETECTED 3 3 AUX_PWR 4 4 TRANSACTIONS_PEND 5 5 EMER_POWER_REDUCTION_DETECTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 3 0x70 11 0 4294967295 LINK_SPEED 0 3 LINK_WIDTH 4 9 PM_SUPPORT 10 11 L0S_EXIT_LATENCY 12 14 L1_EXIT_LATENCY 15 17 CLOCK_POWER_MANAGEMENT 18 18 SURPRISE_DOWN_ERR_REPORTING 19 19 DL_ACTIVE_REPORTING_CAPABLE 20 20 LINK_BW_NOTIFICATION_CAP 21 21 ASPM_OPTIONALITY_COMPLIANCE 22 22 PORT_NUMBER 24 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 3 0x74 10 0 4294967295 PM_CONTROL 0 1 READ_CPL_BOUNDARY 3 3 LINK_DIS 4 4 RETRAIN_LINK 5 5 COMMON_CLOCK_CFG 6 6 EXTENDED_SYNC 7 7 CLOCK_POWER_MANAGEMENT_EN 8 8 HW_AUTONOMOUS_WIDTH_DISABLE 9 9 LINK_BW_MANAGEMENT_INT_EN 10 10 LINK_AUTONOMOUS_BW_INT_EN 11 11 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 3 0x76 7 0 4294967295 CURRENT_LINK_SPEED 0 3 NEGOTIATED_LINK_WIDTH 4 9 LINK_TRAINING 11 11 SLOT_CLOCK_CFG 12 12 DL_ACTIVE 13 13 LINK_BW_MANAGEMENT_STATUS 14 14 LINK_AUTONOMOUS_BW_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 3 0x88 18 0 4294967295 CPL_TIMEOUT_RANGE_SUPPORTED 0 3 CPL_TIMEOUT_DIS_SUPPORTED 4 4 ARI_FORWARDING_SUPPORTED 5 5 ATOMICOP_ROUTING_SUPPORTED 6 6 ATOMICOP_32CMPLT_SUPPORTED 7 7 ATOMICOP_64CMPLT_SUPPORTED 8 8 CAS128_CMPLT_SUPPORTED 9 9 NO_RO_ENABLED_P2P_PASSING 10 10 LTR_SUPPORTED 11 11 TPH_CPLR_SUPPORTED 12 13 TEN_BIT_TAG_COMPLETER_SUPPORTED 16 16 TEN_BIT_TAG_REQUESTER_SUPPORTED 17 17 OBFF_SUPPORTED 18 19 EXTENDED_FMT_FIELD_SUPPORTED 20 20 END_END_TLP_PREFIX_SUPPORTED 21 21 MAX_END_END_TLP_PREFIXES 22 23 EMER_POWER_REDUCTION_SUPPORTED 24 25 EMER_POWER_REDUCTION_INIT_REQ 26 26 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 3 0x8c 12 0 4294967295 CPL_TIMEOUT_VALUE 0 3 CPL_TIMEOUT_DIS 4 4 ARI_FORWARDING_EN 5 5 ATOMICOP_REQUEST_EN 6 6 ATOMICOP_EGRESS_BLOCKING 7 7 IDO_REQUEST_ENABLE 8 8 IDO_COMPLETION_ENABLE 9 9 LTR_EN 10 10 EMER_POWER_REDUCTION_REQUEST 11 11 TEN_BIT_TAG_REQUESTER_ENABLE 12 12 OBFF_EN 13 14 END_END_TLP_PREFIX_BLOCKING 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 3 0x8e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 3 0x90 5 0 4294967295 SUPPORTED_LINK_SPEED 1 7 CROSSLINK_SUPPORTED 8 8 RTM1_PRESENCE_DET_SUPPORT 23 23 RTM2_PRESENCE_DET_SUPPORT 24 24 RESERVED 25 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 3 0x94 8 0 4294967295 TARGET_LINK_SPEED 0 3 ENTER_COMPLIANCE 4 4 HW_AUTONOMOUS_SPEED_DISABLE 5 5 SELECTABLE_DEEMPHASIS 6 6 XMIT_MARGIN 7 9 ENTER_MOD_COMPLIANCE 10 10 COMPLIANCE_SOS 11 11 COMPLIANCE_DEEMPHASIS 12 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 3 0x96 10 0 4294967295 CUR_DEEMPHASIS_LEVEL 0 0 EQUALIZATION_COMPLETE_8GT 1 1 EQUALIZATION_PHASE1_SUCCESS_8GT 2 2 EQUALIZATION_PHASE2_SUCCESS_8GT 3 3 EQUALIZATION_PHASE3_SUCCESS_8GT 4 4 LINK_EQUALIZATION_REQUEST_8GT 5 5 RTM1_PRESENCE_DET 6 6 RTM2_PRESENCE_DET 7 7 CROSSLINK_RESOLUTION 8 9 DOWNSTREAM_COMPONENT_PRESENCE 12 14 cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 3 0x98 1 0 4294967295 RESERVED 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 3 0x9c 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 3 0x9e 1 0 4294967295 RESERVED 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 3 0xa0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 3 0xa2 5 0 4294967295 MSI_EN 0 0 MSI_MULTI_CAP 1 3 MSI_MULTI_EN 4 6 MSI_64BIT 7 7 MSI_PERVECTOR_MASKING_CAP 8 8 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 3 0xa4 1 0 4294967295 MSI_MSG_ADDR_LO 2 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 3 0xa8 1 0 4294967295 MSI_MSG_ADDR_HI 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 3 0xa8 1 0 4294967295 MSI_DATA 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 3 0xac 1 0 4294967295 MSI_MASK 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 3 0xac 1 0 4294967295 MSI_DATA_64 0 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 3 0xb0 1 0 4294967295 MSI_MASK_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 3 0xb0 1 0 4294967295 MSI_PENDING 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 3 0xb4 1 0 4294967295 MSI_PENDING_64 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 3 0xc0 2 0 4294967295 CAP_ID 0 7 NEXT_PTR 8 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 3 0xc2 3 0 4294967295 MSIX_TABLE_SIZE 0 10 MSIX_FUNC_MASK 14 14 MSIX_EN 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 3 0xc4 2 0 4294967295 MSIX_TABLE_BIR 0 2 MSIX_TABLE_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 3 0xc8 2 0 4294967295 MSIX_PBA_BIR 0 2 MSIX_PBA_OFFSET 3 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 3 0x100 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 3 0x104 3 0 4294967295 VSEC_ID 0 15 VSEC_REV 16 19 VSEC_LENGTH 20 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 3 0x108 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 3 0x10c 1 0 4294967295 SCRATCH 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 3 0x150 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 3 0x154 16 0 4294967295 DLP_ERR_STATUS 4 4 SURPDN_ERR_STATUS 5 5 PSN_ERR_STATUS 12 12 FC_ERR_STATUS 13 13 CPL_TIMEOUT_STATUS 14 14 CPL_ABORT_ERR_STATUS 15 15 UNEXP_CPL_STATUS 16 16 RCV_OVFL_STATUS 17 17 MAL_TLP_STATUS 18 18 ECRC_ERR_STATUS 19 19 UNSUPP_REQ_ERR_STATUS 20 20 ACS_VIOLATION_STATUS 21 21 UNCORR_INT_ERR_STATUS 22 22 MC_BLOCKED_TLP_STATUS 23 23 ATOMICOP_EGRESS_BLOCKED_STATUS 24 24 TLP_PREFIX_BLOCKED_ERR_STATUS 25 25 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 3 0x158 16 0 4294967295 DLP_ERR_MASK 4 4 SURPDN_ERR_MASK 5 5 PSN_ERR_MASK 12 12 FC_ERR_MASK 13 13 CPL_TIMEOUT_MASK 14 14 CPL_ABORT_ERR_MASK 15 15 UNEXP_CPL_MASK 16 16 RCV_OVFL_MASK 17 17 MAL_TLP_MASK 18 18 ECRC_ERR_MASK 19 19 UNSUPP_REQ_ERR_MASK 20 20 ACS_VIOLATION_MASK 21 21 UNCORR_INT_ERR_MASK 22 22 MC_BLOCKED_TLP_MASK 23 23 ATOMICOP_EGRESS_BLOCKED_MASK 24 24 TLP_PREFIX_BLOCKED_ERR_MASK 25 25 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 3 0x15c 16 0 4294967295 DLP_ERR_SEVERITY 4 4 SURPDN_ERR_SEVERITY 5 5 PSN_ERR_SEVERITY 12 12 FC_ERR_SEVERITY 13 13 CPL_TIMEOUT_SEVERITY 14 14 CPL_ABORT_ERR_SEVERITY 15 15 UNEXP_CPL_SEVERITY 16 16 RCV_OVFL_SEVERITY 17 17 MAL_TLP_SEVERITY 18 18 ECRC_ERR_SEVERITY 19 19 UNSUPP_REQ_ERR_SEVERITY 20 20 ACS_VIOLATION_SEVERITY 21 21 UNCORR_INT_ERR_SEVERITY 22 22 MC_BLOCKED_TLP_SEVERITY 23 23 ATOMICOP_EGRESS_BLOCKED_SEVERITY 24 24 TLP_PREFIX_BLOCKED_ERR_SEVERITY 25 25 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 3 0x160 8 0 4294967295 RCV_ERR_STATUS 0 0 BAD_TLP_STATUS 6 6 BAD_DLLP_STATUS 7 7 REPLAY_NUM_ROLLOVER_STATUS 8 8 REPLAY_TIMER_TIMEOUT_STATUS 12 12 ADVISORY_NONFATAL_ERR_STATUS 13 13 CORR_INT_ERR_STATUS 14 14 HDR_LOG_OVFL_STATUS 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 3 0x164 8 0 4294967295 RCV_ERR_MASK 0 0 BAD_TLP_MASK 6 6 BAD_DLLP_MASK 7 7 REPLAY_NUM_ROLLOVER_MASK 8 8 REPLAY_TIMER_TIMEOUT_MASK 12 12 ADVISORY_NONFATAL_ERR_MASK 13 13 CORR_INT_ERR_MASK 14 14 HDR_LOG_OVFL_MASK 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 3 0x168 9 0 4294967295 FIRST_ERR_PTR 0 4 ECRC_GEN_CAP 5 5 ECRC_GEN_EN 6 6 ECRC_CHECK_CAP 7 7 ECRC_CHECK_EN 8 8 MULTI_HDR_RECD_CAP 9 9 MULTI_HDR_RECD_EN 10 10 TLP_PREFIX_LOG_PRESENT 11 11 COMPLETION_TIMEOUT_LOG_CAPABLE 12 12 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 3 0x16c 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 3 0x170 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 3 0x174 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 3 0x178 1 0 4294967295 TLP_HDR 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 3 0x188 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 3 0x18c 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 3 0x190 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 3 0x194 1 0 4294967295 TLP_PREFIX 0 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 3 0x2b0 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 3 0x2b4 3 0 4294967295 INVALIDATE_Q_DEPTH 0 4 PAGE_ALIGNED_REQUEST 5 5 GLOBAL_INVALIDATE_SUPPORTED 6 6 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 3 0x2b6 2 0 4294967295 STU 0 4 ATC_ENABLE 15 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 3 0x328 3 0 4294967295 CAP_ID 0 15 CAP_VER 16 19 NEXT_PTR 20 31 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 3 0x32c 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_CAP 0 0 ARI_ACS_FUNC_GROUPS_CAP 1 1 ARI_NEXT_FUNC_NUM 8 15 cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 3 0x32e 3 0 4294967295 ARI_MFVC_FUNC_GROUPS_EN 0 0 ARI_ACS_FUNC_GROUPS_EN 1 1 ARI_FUNCTION_GROUP 4 6 mmMM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmMM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmMM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmSYSHUB_INDEX_OVLP 0 0x8 1 0 0 SYSHUB_OFFSET 0 21 mmSYSHUB_DATA_OVLP 0 0x9 1 0 0 SYSHUB_DATA 0 31 mmPCIE_INDEX 0 0xc 1 0 0 PCIE_INDEX 0 31 mmPCIE_DATA 0 0xd 1 0 0 PCIE_DATA 0 31 mmPCIE_INDEX2 0 0xe 1 0 0 PCIE_INDEX2 0 31 mmPCIE_DATA2 0 0xf 1 0 0 PCIE_DATA2 0 31 mmSBIOS_SCRATCH_0 0 0x34 1 0 1 SBIOS_SCRATCH_DW 0 31 mmSBIOS_SCRATCH_1 0 0x35 1 0 1 SBIOS_SCRATCH_DW 0 31 mmSBIOS_SCRATCH_2 0 0x36 1 0 1 SBIOS_SCRATCH_DW 0 31 mmSBIOS_SCRATCH_3 0 0x37 1 0 1 SBIOS_SCRATCH_DW 0 31 mmBIOS_SCRATCH_0 0 0x38 1 0 1 BIOS_SCRATCH_0 0 31 mmBIOS_SCRATCH_1 0 0x39 1 0 1 BIOS_SCRATCH_1 0 31 mmBIOS_SCRATCH_2 0 0x3a 1 0 1 BIOS_SCRATCH_2 0 31 mmBIOS_SCRATCH_3 0 0x3b 1 0 1 BIOS_SCRATCH_3 0 31 mmBIOS_SCRATCH_4 0 0x3c 1 0 1 BIOS_SCRATCH_4 0 31 mmBIOS_SCRATCH_5 0 0x3d 1 0 1 BIOS_SCRATCH_5 0 31 mmBIOS_SCRATCH_6 0 0x3e 1 0 1 BIOS_SCRATCH_6 0 31 mmBIOS_SCRATCH_7 0 0x3f 1 0 1 BIOS_SCRATCH_7 0 31 mmBIOS_SCRATCH_8 0 0x40 1 0 1 BIOS_SCRATCH_8 0 31 mmBIOS_SCRATCH_9 0 0x41 1 0 1 BIOS_SCRATCH_9 0 31 mmBIOS_SCRATCH_10 0 0x42 1 0 1 BIOS_SCRATCH_10 0 31 mmBIOS_SCRATCH_11 0 0x43 1 0 1 BIOS_SCRATCH_11 0 31 mmBIOS_SCRATCH_12 0 0x44 1 0 1 BIOS_SCRATCH_12 0 31 mmBIOS_SCRATCH_13 0 0x45 1 0 1 BIOS_SCRATCH_13 0 31 mmBIOS_SCRATCH_14 0 0x46 1 0 1 BIOS_SCRATCH_14 0 31 mmBIOS_SCRATCH_15 0 0x47 1 0 1 BIOS_SCRATCH_15 0 31 mmBIF_RLC_INTR_CNTL 0 0x4c 4 0 1 RLC_CMD_COMPLETE 0 0 RLC_HANG_SELF_RECOVERED 1 1 RLC_HANG_NEED_FLR 2 2 RLC_VM_BUSY_TRANSITION 3 3 mmBIF_VCE_INTR_CNTL 0 0x4d 4 0 1 VCE_CMD_COMPLETE 0 0 VCE_HANG_SELF_RECOVERED 1 1 VCE_HANG_NEED_FLR 2 2 VCE_VM_BUSY_TRANSITION 3 3 mmBIF_UVD_INTR_CNTL 0 0x4e 5 0 1 UVD_CMD_COMPLETE 0 0 UVD_HANG_SELF_RECOVERED 1 1 UVD_HANG_NEED_FLR 2 2 UVD_VM_BUSY_TRANSITION 3 3 UVD_INST_SEL 28 31 mmGFX_MMIOREG_CAM_ADDR0 0 0x6c 1 0 1 CAM_ADDR0 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR0 0 0x6d 1 0 1 CAM_REMAP_ADDR0 0 19 mmGFX_MMIOREG_CAM_ADDR1 0 0x6e 1 0 1 CAM_ADDR1 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR1 0 0x6f 1 0 1 CAM_REMAP_ADDR1 0 19 mmGFX_MMIOREG_CAM_ADDR2 0 0x70 1 0 1 CAM_ADDR2 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR2 0 0x71 1 0 1 CAM_REMAP_ADDR2 0 19 mmGFX_MMIOREG_CAM_ADDR3 0 0x72 1 0 1 CAM_ADDR3 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR3 0 0x73 1 0 1 CAM_REMAP_ADDR3 0 19 mmGFX_MMIOREG_CAM_ADDR4 0 0x74 1 0 1 CAM_ADDR4 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR4 0 0x75 1 0 1 CAM_REMAP_ADDR4 0 19 mmGFX_MMIOREG_CAM_ADDR5 0 0x76 1 0 1 CAM_ADDR5 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR5 0 0x77 1 0 1 CAM_REMAP_ADDR5 0 19 mmGFX_MMIOREG_CAM_ADDR6 0 0x78 1 0 1 CAM_ADDR6 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR6 0 0x79 1 0 1 CAM_REMAP_ADDR6 0 19 mmGFX_MMIOREG_CAM_ADDR7 0 0x7a 1 0 1 CAM_ADDR7 0 19 mmGFX_MMIOREG_CAM_REMAP_ADDR7 0 0x7b 1 0 1 CAM_REMAP_ADDR7 0 19 mmGFX_MMIOREG_CAM_CNTL 0 0x7c 1 0 1 CAM_ENABLE 0 7 mmGFX_MMIOREG_CAM_ZERO_CPL 0 0x7d 1 0 1 CAM_ZERO_CPL 0 31 mmGFX_MMIOREG_CAM_ONE_CPL 0 0x7e 1 0 1 CAM_ONE_CPL 0 31 mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0 0x7f 1 0 1 CAM_PROGRAMMABLE_CPL 0 31 mmSYSHUB_INDEX 0 0x8 1 0 0 INDEX 0 31 mmSYSHUB_DATA 0 0x9 1 0 0 DATA 0 31 mmRCC_BIF_STRAP0 0 0x0 1 0 2 STRAP_PX_CAPABLE 7 7 mmRCC_DEV0_EPF0_STRAP0 0 0x11 8 0 2 STRAP_DEVICE_ID_DEV0_F0 0 15 STRAP_MAJOR_REV_ID_DEV0_F0 16 19 STRAP_MINOR_REV_ID_DEV0_F0 20 23 STRAP_ATI_REV_ID_DEV0_F0 24 27 STRAP_FUNC_EN_DEV0_F0 28 28 STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0 29 29 STRAP_D1_SUPPORT_DEV0_F0 30 30 STRAP_D2_SUPPORT_DEV0_F0 31 31 mmEP_PCIE_SCRATCH 0 0x25 1 0 2 PCIE_SCRATCH 0 31 mmEP_PCIE_CNTL 0 0x27 3 0 2 UR_ERR_REPORT_DIS 7 7 PCIE_MALFORM_ATOMIC_OPS 8 8 RX_IGNORE_LTR_MSG_UR 30 30 mmEP_PCIE_INT_CNTL 0 0x28 6 0 2 CORR_ERR_INT_EN 0 0 NON_FATAL_ERR_INT_EN 1 1 FATAL_ERR_INT_EN 2 2 USR_DETECTED_INT_EN 3 3 MISC_ERR_INT_EN 4 4 POWER_STATE_CHG_INT_EN 6 6 mmEP_PCIE_INT_STATUS 0 0x29 6 0 2 CORR_ERR_INT_STATUS 0 0 NON_FATAL_ERR_INT_STATUS 1 1 FATAL_ERR_INT_STATUS 2 2 USR_DETECTED_INT_STATUS 3 3 MISC_ERR_INT_STATUS 4 4 POWER_STATE_CHG_INT_STATUS 6 6 mmEP_PCIE_RX_CNTL2 0 0x2a 1 0 2 RX_IGNORE_EP_INVALIDPASID_UR 0 0 mmEP_PCIE_BUS_CNTL 0 0x2b 1 0 2 IMMEDIATE_PMI_DIS 7 7 mmEP_PCIE_CFG_CNTL 0 0x2c 4 0 2 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 mmEP_PCIE_TX_LTR_CNTL 0 0x2e 10 0 2 LTR_PRIV_S_SHORT_VALUE 0 2 LTR_PRIV_S_LONG_VALUE 3 5 LTR_PRIV_S_REQUIREMENT 6 6 LTR_PRIV_NS_SHORT_VALUE 7 9 LTR_PRIV_NS_LONG_VALUE 10 12 LTR_PRIV_NS_REQUIREMENT 13 13 LTR_PRIV_MSG_DIS_IN_PM_NON_D0 14 14 LTR_PRIV_RST_LTR_IN_DL_DOWN 15 15 TX_CHK_FC_FOR_L1 16 16 LTR_DSTATE_USING_WDATA_EN 17 17 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0 0x2f 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0 0x2f 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0 0x2f 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0 0x2f 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0 0x30 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0 0x30 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0 0x30 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0 0x30 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmEP_PCIE_F0_DPA_CAP 0 0x34 4 0 2 TRANS_LAT_UNIT 8 9 PWR_ALLOC_SCALE 12 13 TRANS_LAT_VAL_0 16 23 TRANS_LAT_VAL_1 24 31 mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0 0x35 1 0 2 TRANS_LAT_INDICATOR_BITS 0 7 mmEP_PCIE_F0_DPA_CNTL 0 0x35 2 0 2 SUBSTATE_STATUS 0 4 DPA_COMPLIANCE_MODE 8 8 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0 0x35 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0 0x36 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0 0x36 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0 0x36 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0 0x36 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0 0x37 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0 0x37 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0 0x37 1 0 2 SUBSTATE_PWR_ALLOC 0 7 mmEP_PCIE_PME_CONTROL 0 0x37 1 0 2 PME_SERVICE_TIMER 0 4 mmEP_PCIEP_RESERVED 0 0x38 1 0 2 PCIEP_RESERVED 0 31 mmEP_PCIE_TX_CNTL 0 0x3a 5 0 2 TX_SNR_OVERRIDE 10 11 TX_RO_OVERRIDE 12 13 TX_F0_TPH_DIS 24 24 TX_F1_TPH_DIS 25 25 TX_F2_TPH_DIS 26 26 mmEP_PCIE_TX_REQUESTER_ID 0 0x3b 3 0 2 TX_REQUESTER_ID_FUNCTION 0 2 TX_REQUESTER_ID_DEVICE 3 7 TX_REQUESTER_ID_BUS 8 15 mmEP_PCIE_ERR_CNTL 0 0x3c 12 0 2 ERR_REPORTING_DIS 0 0 AER_HDR_LOG_TIMEOUT 8 10 SEND_ERR_MSG_IMMEDIATELY 17 17 STRAP_POISONED_ADVISORY_NONFATAL 18 18 AER_HDR_LOG_F0_TIMER_EXPIRED 24 24 AER_HDR_LOG_F1_TIMER_EXPIRED 25 25 AER_HDR_LOG_F2_TIMER_EXPIRED 26 26 AER_HDR_LOG_F3_TIMER_EXPIRED 27 27 AER_HDR_LOG_F4_TIMER_EXPIRED 28 28 AER_HDR_LOG_F5_TIMER_EXPIRED 29 29 AER_HDR_LOG_F6_TIMER_EXPIRED 30 30 AER_HDR_LOG_F7_TIMER_EXPIRED 31 31 mmEP_PCIE_RX_CNTL 0 0x3d 8 0 2 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR 21 21 RX_IGNORE_MAXPREFIX_ERR 22 22 RX_IGNORE_INVALIDPASID_ERR 24 24 RX_IGNORE_NOT_PASID_UR 25 25 RX_TPH_DIS 26 26 mmEP_PCIE_LC_SPEED_CNTL 0 0x3e 3 0 2 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 mmDN_PCIE_RESERVED 0 0x40 1 0 2 PCIE_RESERVED 0 31 mmDN_PCIE_SCRATCH 0 0x41 1 0 2 PCIE_SCRATCH 0 31 mmDN_PCIE_CNTL 0 0x43 3 0 2 HWINIT_WR_LOCK 0 0 UR_ERR_REPORT_DIS_DN 7 7 RX_IGNORE_LTR_MSG_UR 30 30 mmDN_PCIE_CONFIG_CNTL 0 0x44 1 0 2 CI_EXTENDED_TAG_EN_OVERRIDE 25 26 mmDN_PCIE_RX_CNTL2 0 0x45 1 0 2 FLR_EXTEND_MODE 28 30 mmDN_PCIE_BUS_CNTL 0 0x46 2 0 2 IMMEDIATE_PMI_DIS 7 7 AER_CPL_TIMEOUT_RO_DIS_SWDN 8 8 mmDN_PCIE_CFG_CNTL 0 0x47 4 0 2 CFG_EN_DEC_TO_HIDDEN_REG 0 0 CFG_EN_DEC_TO_GEN2_HIDDEN_REG 1 1 CFG_EN_DEC_TO_GEN3_HIDDEN_REG 2 2 CFG_EN_DEC_TO_GEN4_HIDDEN_REG 3 3 mmPCIE_ERR_CNTL 0 0x4f 2 0 2 ERR_REPORTING_DIS 0 0 SEND_ERR_MSG_IMMEDIATELY 17 17 mmPCIE_RX_CNTL 0 0x50 5 0 2 RX_IGNORE_MAX_PAYLOAD_ERR 8 8 RX_IGNORE_TC_ERR_DN 9 9 RX_PCIE_CPL_TIMEOUT_DIS 20 20 RX_IGNORE_SHORTPREFIX_ERR_DN 21 21 RX_RCB_FLR_TIMEOUT_DIS 27 27 mmPCIE_LC_SPEED_CNTL 0 0x51 3 0 2 LC_GEN2_EN_STRAP 0 0 LC_GEN3_EN_STRAP 1 1 LC_GEN4_EN_STRAP 2 2 mmPCIE_LC_CNTL2 0 0x52 1 0 2 LC_LINK_BW_NOTIFICATION_DIS 27 27 mmLTR_MSG_INFO_FROM_EP 0 0x54 1 0 2 LTR_MSG_INFO_FROM_EP 0 31 mmRCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmRCC_ERR_INT_CNTL 0 0x86 1 0 2 INVALID_REG_ACCESS_IN_SRIOV_INT_EN 0 0 mmRCC_BACO_CNTL_MISC 0 0x87 2 0 2 BIF_ROM_REQ_DIS 0 0 BIF_AZ_REQ_DIS 1 1 mmRCC_RESET_EN 0 0x88 1 0 2 DB_APER_RESET_EN 15 15 mmRCC_VDM_SUPPORT 0 0x89 5 0 2 MCTP_SUPPORT 0 0 AMPTP_SUPPORT 1 1 OTHER_VDM_SUPPORT 2 2 ROUTE_TO_RC_CHECK_IN_RCMODE 3 3 ROUTE_BROADCAST_CHECK_IN_RCMODE 4 4 mmRCC_MARGIN_PARAM_CNTL0 0 0x8a 9 0 2 MARGINING_VOLTAGE_SUPPORTED 0 0 MARGINING_IND_LEFTRIGHT_TIMING 1 1 MARGINING_IND_UPDOWN_VOLTAGE 2 2 MARGINING_IND_ERROR_SAMPLER 3 3 MARGINING_SAMPLE_REPORTING_METHOD 4 4 MARGINING_NUM_TIMING_STEPS 5 10 MARGINING_MAX_TIMING_OFFSET 11 17 MARGINING_NUM_VOLTAGE_STEPS 18 24 MARGINING_MAX_VOLTAGE_OFFSET 25 31 mmRCC_MARGIN_PARAM_CNTL1 0 0x8b 4 0 2 MARGINING_SAMPLING_RATE_VOLTAGE 0 5 MARGINING_SAMPLING_RATE_TIMING 6 11 MARGINING_MAX_LANES 12 16 MARGINING_SAMPLE_COUNT 17 23 mmRCC_PEER_REG_RANGE0 0 0xbe 2 0 2 START_ADDR 0 15 END_ADDR 16 31 mmRCC_PEER_REG_RANGE1 0 0xbf 2 0 2 START_ADDR 0 15 END_ADDR 16 31 mmRCC_BUS_CNTL 0 0xc1 17 0 2 PMI_IO_DIS 2 2 PMI_MEM_DIS 3 3 PMI_BM_DIS 4 4 PMI_IO_DIS_DN 5 5 PMI_MEM_DIS_DN 6 6 PMI_IO_DIS_UP 7 7 PMI_MEM_DIS_UP 8 8 DN_SEC_SIG_CPLCA_WITH_EP_ERR 16 16 DN_SEC_RCV_CPLCA_WITH_EP_ERR 17 17 DN_SEC_RCV_CPLUR_WITH_EP_ERR 18 18 DN_PRI_SIG_CPLCA_WITH_EP_ERR 19 19 DN_PRI_RCV_CPLCA_WITH_EP_ERR 20 20 DN_PRI_RCV_CPLUR_WITH_EP_ERR 21 21 MAX_PAYLOAD_SIZE_MODE 24 24 PRIV_MAX_PAYLOAD_SIZE 25 27 MAX_READ_REQUEST_SIZE_MODE 28 28 PRIV_MAX_READ_REQUEST_SIZE 29 31 mmRCC_CONFIG_CNTL 0 0xc2 3 0 2 CFG_VGA_RAM_EN 0 0 GENMO_MONO_ADDRESS_B 2 2 GRPH_ADRSEL 3 4 mmRCC_CONFIG_F0_BASE 0 0xc6 1 0 2 F0_BASE 0 31 mmRCC_CONFIG_APER_SIZE 0 0xc7 1 0 2 APER_SIZE 0 31 mmRCC_CONFIG_REG_APER_SIZE 0 0xc8 1 0 2 REG_APER_SIZE 0 19 mmRCC_XDMA_LO 0 0xc9 2 0 2 BIF_XDMA_LOWER_BOUND 0 30 BIF_XDMA_APER_EN 31 31 mmRCC_XDMA_HI 0 0xca 1 0 2 BIF_XDMA_UPPER_BOUND 0 30 mmRCC_FEATURES_CONTROL_MISC 0 0xcb 16 0 2 UR_PSN_PKT_REPORT_POISON_DIS 4 4 POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS 5 5 POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS 6 6 INIT_PFFLR_CRS_RET_DIS 7 7 ATC_PRG_RESP_PASID_UR_EN 8 8 RX_IGNORE_TRANSMRD_UR 9 9 RX_IGNORE_TRANSMWR_UR 10 10 RX_IGNORE_ATSTRANSREQ_UR 11 11 RX_IGNORE_PAGEREQMSG_UR 12 12 RX_IGNORE_INVCPL_UR 13 13 CLR_MSI_X_PENDING_WHEN_DISABLED_DIS 14 14 CHECK_BME_ON_PENDING_PKT_GEN_DIS 15 15 PSN_CHECK_ON_PAYLOAD_DIS 16 16 CLR_MSI_PENDING_ON_MULTIEN_DIS 17 17 SET_DEVICE_ERR_FOR_ECRC_EN 18 18 HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS 19 19 mmRCC_BUSNUM_CNTL1 0 0xcc 1 0 2 ID_MASK 0 7 mmRCC_BUSNUM_LIST0 0 0xcd 4 0 2 ID0 0 7 ID1 8 15 ID2 16 23 ID3 24 31 mmRCC_BUSNUM_LIST1 0 0xce 4 0 2 ID4 0 7 ID5 8 15 ID6 16 23 ID7 24 31 mmRCC_BUSNUM_CNTL2 0 0xcf 4 0 2 AUTOUPDATE_SEL 0 7 AUTOUPDATE_EN 8 8 HDPREG_CNTL 16 16 ERROR_MULTIPLE_ID_MATCH 17 17 mmRCC_CAPTURE_HOST_BUSNUM 0 0xd0 1 0 2 CHECK_EN 0 0 mmRCC_HOST_BUSNUM 0 0xd1 1 0 2 HOST_ID 0 15 mmRCC_PEER0_FB_OFFSET_HI 0 0xd2 1 0 2 PEER0_FB_OFFSET_HI 0 19 mmRCC_PEER0_FB_OFFSET_LO 0 0xd3 2 0 2 PEER0_FB_OFFSET_LO 0 19 PEER0_FB_EN 31 31 mmRCC_PEER1_FB_OFFSET_HI 0 0xd4 1 0 2 PEER1_FB_OFFSET_HI 0 19 mmRCC_PEER1_FB_OFFSET_LO 0 0xd5 2 0 2 PEER1_FB_OFFSET_LO 0 19 PEER1_FB_EN 31 31 mmRCC_PEER2_FB_OFFSET_HI 0 0xd6 1 0 2 PEER2_FB_OFFSET_HI 0 19 mmRCC_PEER2_FB_OFFSET_LO 0 0xd7 2 0 2 PEER2_FB_OFFSET_LO 0 19 PEER2_FB_EN 31 31 mmRCC_PEER3_FB_OFFSET_HI 0 0xd8 1 0 2 PEER3_FB_OFFSET_HI 0 19 mmRCC_PEER3_FB_OFFSET_LO 0 0xd9 2 0 2 PEER3_FB_OFFSET_LO 0 19 PEER3_FB_EN 31 31 mmRCC_CMN_LINK_CNTL 0 0xde 5 0 2 BLOCK_PME_ON_L0S_DIS 0 0 BLOCK_PME_ON_L1_DIS 1 1 BLOCK_PME_ON_LDN_DIS 2 2 PM_L1_IDLE_CHECK_DMA_EN 3 3 VLINK_IN_L1LTR_TIMER 16 31 mmRCC_EP_REQUESTERID_RESTORE 0 0xdf 2 0 2 EP_REQID_BUS 0 7 EP_REQID_DEV 8 12 mmRCC_LTR_LSWITCH_CNTL 0 0xe0 1 0 2 LSWITCH_LATENCY_VALUE 0 9 mmRCC_MH_ARB_CNTL 0 0xe1 2 0 2 MH_ARB_MODE 0 0 MH_ARB_FIX_PRIORITY 1 14 mmBIF_MM_INDACCESS_CNTL 0 0xe6 1 0 2 MM_INDACCESS_DIS 1 1 mmBUS_CNTL 0 0xe7 12 0 2 VGA_REG_COHERENCY_DIS 6 6 VGA_MEM_COHERENCY_DIS 7 7 SET_AZ_TC 10 12 SET_MC_TC 13 15 ZERO_BE_WR_EN 16 16 ZERO_BE_RD_EN 17 17 RD_STALL_IO_WR 18 18 PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS 25 25 PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS 26 26 HDP_REG_FLUSH_VF_MASK_EN 29 29 VGAFB_ZERO_BE_WR_EN 30 30 VGAFB_ZERO_BE_RD_EN 31 31 mmBIF_SCRATCH0 0 0xe8 1 0 2 BIF_SCRATCH0 0 31 mmBIF_SCRATCH1 0 0xe9 1 0 2 BIF_SCRATCH1 0 31 mmBX_RESET_EN 0 0xed 1 0 2 RESET_ON_VFENABLE_LOW_EN 16 16 mmMM_CFGREGS_CNTL 0 0xee 3 0 2 MM_CFG_FUNC_SEL 0 2 MM_CFG_DEV_SEL 6 7 MM_WR_TO_CFG_EN 31 31 mmBX_RESET_CNTL 0 0xf0 1 0 2 LINK_TRAIN_EN 0 0 mmINTERRUPT_CNTL 0 0xf1 8 0 2 IH_DUMMY_RD_OVERRIDE 0 0 IH_DUMMY_RD_EN 1 1 IH_REQ_NONSNOOP_EN 3 3 IH_INTR_DLY_CNTR 4 7 GEN_IH_INT_EN 8 8 BIF_RB_REQ_NONSNOOP_EN 15 15 DUMMYRD_BYPASS_IN_MSI_EN 16 16 ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS 17 17 mmINTERRUPT_CNTL2 0 0xf2 1 0 2 IH_DUMMY_RD_ADDR 0 31 mmCLKREQB_PAD_CNTL 0 0xf8 13 0 2 CLKREQB_PAD_A 0 0 CLKREQB_PAD_SEL 1 1 CLKREQB_PAD_MODE 2 2 CLKREQB_PAD_SPARE 3 4 CLKREQB_PAD_SN0 5 5 CLKREQB_PAD_SN1 6 6 CLKREQB_PAD_SN2 7 7 CLKREQB_PAD_SN3 8 8 CLKREQB_PAD_SLEWN 9 9 CLKREQB_PAD_WAKE 10 10 CLKREQB_PAD_SCHMEN 11 11 CLKREQB_PAD_CNTL_EN 12 12 CLKREQB_PAD_Y 13 13 mmBIF_FEATURES_CONTROL_MISC 0 0xfb 8 0 2 MST_BIF_REQ_EP_DIS 0 0 SLV_BIF_CPL_EP_DIS 1 1 BIF_SLV_REQ_EP_DIS 2 2 BIF_MST_CPL_EP_DIS 3 3 BIF_RB_SET_OVERFLOW_EN 12 12 ATOMIC_ERR_INT_DIS 13 13 BME_HDL_NONVIR_EN 15 15 DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR 24 24 mmBIF_DOORBELL_CNTL 0 0xfc 9 0 2 SELF_RING_DIS 0 0 TRANS_CHECK_DIS 1 1 UNTRANS_LBACK_EN 2 2 NON_CONSECUTIVE_BE_ZERO_DIS 3 3 DOORBELL_MONITOR_EN 4 4 DB_MNTR_INTGEN_DIS 24 24 DB_MNTR_INTGEN_MODE_0 25 25 DB_MNTR_INTGEN_MODE_1 26 26 DB_MNTR_INTGEN_MODE_2 27 27 mmBIF_DOORBELL_INT_CNTL 0 0xfd 9 0 2 DOORBELL_INTERRUPT_STATUS 0 0 RAS_CNTLR_INTERRUPT_STATUS 1 1 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS 2 2 DOORBELL_INTERRUPT_CLEAR 16 16 RAS_CNTLR_INTERRUPT_CLEAR 17 17 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR 18 18 DOORBELL_INTERRUPT_DISABLE 24 24 RAS_CNTLR_INTERRUPT_DISABLE 25 25 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE 26 26 mmBIF_FB_EN 0 0xff 2 0 2 FB_READ_EN 0 0 FB_WRITE_EN 1 1 mmBIF_INTR_CNTL 0 0x100 1 0 2 RAS_INTR_VEC_SEL 0 0 mmBIF_MST_TRANS_PENDING_VF 0 0x109 1 0 2 BIF_MST_TRANS_PENDING 0 30 mmBIF_SLV_TRANS_PENDING_VF 0 0x10a 1 0 2 BIF_SLV_TRANS_PENDING 0 30 mmBACO_CNTL 0 0x10b 8 0 2 BACO_EN 0 0 BACO_DUMMY_EN 2 2 BACO_POWER_OFF 3 3 BACO_DSTATE_BYPASS 5 5 BACO_RST_INTR_MASK 6 6 BACO_MODE 8 8 RCU_BIF_CONFIG_DONE 9 9 BACO_AUTO_EXIT 31 31 mmBIF_BACO_EXIT_TIME0 0 0x10c 1 0 2 BACO_EXIT_PXEN_CLR_TIMER 0 19 mmBIF_BACO_EXIT_TIMER1 0 0x10d 8 0 2 BACO_EXIT_SIDEBAND_TIMER 0 19 BACO_HW_AUTO_FLUSH_EN 24 24 BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR 25 25 BACO_HW_EXIT_DIS 26 26 PX_EN_OE_IN_PX_EN_HIGH 27 27 PX_EN_OE_IN_PX_EN_LOW 28 28 BACO_MODE_SEL 29 30 AUTO_BACO_EXIT_CLR_BY_HW_DIS 31 31 mmBIF_BACO_EXIT_TIMER2 0 0x10e 1 0 2 BACO_EXIT_LCLK_BAK_TIMER 0 19 mmBIF_BACO_EXIT_TIMER3 0 0x10f 1 0 2 BACO_EXIT_DUMMY_EN_CLR_TIMER 0 19 mmBIF_BACO_EXIT_TIMER4 0 0x110 1 0 2 BACO_EXIT_BACO_EN_CLR_TIMER 0 19 mmMEM_TYPE_CNTL 0 0x111 1 0 2 BF_MEM_PHY_G5_G3 0 0 mmNBIF_GFX_ADDR_LUT_CNTL 0 0x113 2 0 2 LUT_ENABLE 0 0 MSI_ADDR_MODE 1 1 mmNBIF_GFX_ADDR_LUT_0 0 0x114 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_1 0 0x115 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_2 0 0x116 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_3 0 0x117 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_4 0 0x118 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_5 0 0x119 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_6 0 0x11a 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_7 0 0x11b 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_8 0 0x11c 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_9 0 0x11d 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_10 0 0x11e 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_11 0 0x11f 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_12 0 0x120 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_13 0 0x121 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_14 0 0x122 1 0 2 ADDR 0 23 mmNBIF_GFX_ADDR_LUT_15 0 0x123 1 0 2 ADDR 0 23 mmREMAP_HDP_MEM_FLUSH_CNTL 0 0x12d 1 0 2 ADDRESS 2 18 mmREMAP_HDP_REG_FLUSH_CNTL 0 0x12e 1 0 2 ADDRESS 2 18 mmBIF_RB_CNTL 0 0x12f 9 0 2 RB_ENABLE 0 0 RB_SIZE 1 5 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 BIF_RB_TRAN 17 17 RB_INTR_FIX_PRIORITY 26 28 RB_INTR_ARB_MODE 29 29 RB_RST_BY_FLR_DISABLE 30 30 WPTR_OVERFLOW_CLEAR 31 31 mmBIF_RB_BASE 0 0x130 1 0 2 ADDR 0 31 mmBIF_RB_RPTR 0 0x131 1 0 2 OFFSET 2 17 mmBIF_RB_WPTR 0 0x132 2 0 2 BIF_RB_OVERFLOW 0 0 OFFSET 2 17 mmBIF_RB_WPTR_ADDR_HI 0 0x133 1 0 2 ADDR 0 7 mmBIF_RB_WPTR_ADDR_LO 0 0x134 1 0 2 ADDR 2 31 mmMAILBOX_INDEX 0 0x135 1 0 2 MAILBOX_INDEX 0 4 mmBIF_MP1_INTR_CTRL 0 0x142 1 0 2 BACO_EXIT_DONE 0 0 mmBIF_UVD_GPUIOV_CFG_SIZE 0 0x143 1 0 2 UVD_GPUIOV_CFG_SIZE 0 3 mmBIF_VCE_GPUIOV_CFG_SIZE 0 0x144 1 0 2 VCE_GPUIOV_CFG_SIZE 0 3 mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0 0x145 1 0 2 GFX_SDMA_GPUIOV_CFG_SIZE 0 3 mmBIF_PERSTB_PAD_CNTL 0 0x148 1 0 2 PERSTB_PAD_CNTL 0 15 mmBIF_PX_EN_PAD_CNTL 0 0x149 1 0 2 PX_EN_PAD_CNTL 0 7 mmBIF_REFPADKIN_PAD_CNTL 0 0x14a 1 0 2 REFPADKIN_PAD_CNTL 0 7 mmBIF_CLKREQB_PAD_CNTL 0 0x14b 1 0 2 CLKREQB_PAD_CNTL 0 23 mmBIF_PWRBRK_PAD_CNTL 0 0x14c 1 0 2 PWRBRK_PAD_CNTL 0 7 mmBIF_WAKEB_PAD_CNTL 0 0x14d 8 0 2 GPIO33_ITXIMPSEL 0 0 GPIO33_ICTFEN 1 1 GPIO33_IPD 2 2 GPIO33_IPU 3 3 GPIO33_IRXEN 4 4 GPIO33_IRXSEL0 5 5 GPIO33_IRXSEL1 6 6 GPIO33_RESERVED 7 7 mmBIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_ATOMIC_ERR_LOG 0 0xec 0 0 2 mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmDOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmHDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmHDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmGPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmGPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmNBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmMAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmMAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmMAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmNGDC_SDP_PORT_CTRL 0 0x1c2 1 0 2 SDP_DISCON_HYSTERESIS 0 7 mmSHUB_REGS_IF_CTL 0 0x1c3 1 0 2 SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS 0 0 mmNGDC_MGCG_CTRL 0 0x1ca 7 0 2 NGDC_MGCG_EN 0 0 NGDC_MGCG_MODE 1 1 NGDC_MGCG_HYSTERESIS 2 9 NGDC_MGCG_HST_DIS 10 10 NGDC_MGCG_DMA_DIS 11 11 NGDC_MGCG_REG_DIS 12 12 NGDC_MGCG_AER_DIS 13 13 mmNGDC_RESERVED_0 0 0x1cb 1 0 2 RESERVED 0 31 mmNGDC_RESERVED_1 0 0x1cc 1 0 2 RESERVED 0 31 mmNGDC_SDP_PORT_CTRL_SOCCLK 0 0x1cd 1 0 2 SDP_DISCON_HYSTERESIS_SOCCLK 0 7 mmBIF_SDMA0_DOORBELL_RANGE 0 0x1d0 2 0 2 OFFSET 2 11 SIZE 16 20 mmBIF_SDMA1_DOORBELL_RANGE 0 0x1d1 2 0 2 OFFSET 2 11 SIZE 16 20 mmBIF_IH_DOORBELL_RANGE 0 0x1d2 2 0 2 OFFSET 2 11 SIZE 16 20 mmBIF_MMSCH0_DOORBELL_RANGE 0 0x1d3 2 0 2 OFFSET 2 11 SIZE 16 20 mmBIF_ACV_DOORBELL_RANGE 0 0x1d4 2 0 2 OFFSET 2 11 SIZE 16 20 mmBIF_DOORBELL_FENCE_CNTL 0 0x1de 5 0 2 DOORBELL_FENCE_CP_ENABLE 0 0 DOORBELL_FENCE_SDMA0_ENABLE 1 1 DOORBELL_FENCE_SDMA1_ENABLE 2 2 DOORBELL_FENCE_ACV_ENABLE 3 3 DOORBELL_FENCE_ONCE_TRIGGER_DIS 16 16 mmS2A_MISC_CNTL 0 0x1df 9 0 2 DOORBELL_64BIT_SUPPORT_SDMA0_DIS 0 0 DOORBELL_64BIT_SUPPORT_SDMA1_DIS 1 1 DOORBELL_64BIT_SUPPORT_CP_DIS 2 2 AXI_HST_CPL_EP_DIS 3 3 DOORBELL_64BIT_SUPPORT_ACV_DIS 4 4 ATM_ARB_MODE 8 9 RB_ARB_MODE 10 11 HSTR_ARB_MODE 12 13 WRSP_ARB_MODE 16 19 mmGFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmGFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmGFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmGFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmGFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmGFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmGFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmGFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmGFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmGFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmGFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmGFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmGFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2 mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0 0x0 2 0 0 MM_OFFSET 0 30 MM_APER 31 31 mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0 0x1 1 0 0 MM_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0 0x6 1 0 0 MM_OFFSET_HI 0 31 mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0 0x85 2 0 2 INVALID_REG_ACCESS_IN_SRIOV_STATUS 0 0 DOORBELL_READ_ACCESS_STATUS 1 1 mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0 0xc0 1 0 2 BIF_DOORBELL_APER_EN 0 0 mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0 0xc3 1 0 2 CONFIG_MEMSIZE 0 31 mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0 0xc4 1 0 2 CONFIG_RESERVED 0 31 mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0 0xc5 2 0 2 FUNC_IDENTIFIER 0 0 IOV_ENABLE 31 31 mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0 0xeb 2 0 2 DMA_ON_BME_LOW 0 0 CLEAR_DMA_ON_BME_LOW 16 16 mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0 0xec 8 0 2 UR_ATOMIC_OPCODE 0 0 UR_ATOMIC_REQEN_LOW 1 1 UR_ATOMIC_LENGTH 2 2 UR_ATOMIC_NR 3 3 CLEAR_UR_ATOMIC_OPCODE 16 16 CLEAR_UR_ATOMIC_REQEN_LOW 17 17 CLEAR_UR_ATOMIC_LENGTH 18 18 CLEAR_UR_ATOMIC_NR 19 19 mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 0xf3 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0 31 mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 0xf4 1 0 2 DOORBELL_SELFRING_GPA_APER_BASE_LOW 0 31 mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0 0xf5 3 0 2 DOORBELL_SELFRING_GPA_APER_EN 0 0 DOORBELL_SELFRING_GPA_APER_MODE 1 1 DOORBELL_SELFRING_GPA_APER_SIZE 8 19 mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0 0xf6 1 0 2 HDP_REG_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0 0xf7 1 0 2 HDP_MEM_FLUSH_ADDR 0 0 mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0 0x106 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0 0x107 12 0 2 CP0 0 0 CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 CP5 5 5 CP6 6 6 CP7 7 7 CP8 8 8 CP9 9 9 SDMA0 10 10 SDMA1 11 11 mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0 0x108 2 0 2 BIF_MST_TRANS_PENDING 0 0 BIF_SLV_TRANS_PENDING 1 1 mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0 0x112 1 0 2 LUT_BYPASS 0 0 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0 0x136 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0 0x137 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0 0x138 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0 0x139 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0 0x13a 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0 0x13b 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0 0x13c 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0 0x13d 1 0 2 MSGBUF_DATA 0 31 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0 0x13e 4 0 2 TRN_MSG_VALID 0 0 TRN_MSG_ACK 1 1 RCV_MSG_VALID 8 8 RCV_MSG_ACK 9 9 mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0 0x13f 2 0 2 VALID_INT_EN 0 0 ACK_INT_EN 1 1 mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0 0x140 8 0 2 VMHV_MAILBOX_TRN_ACK_INTR_EN 0 0 VMHV_MAILBOX_RCV_VALID_INTR_EN 1 1 VMHV_MAILBOX_TRN_MSG_DATA 8 11 VMHV_MAILBOX_TRN_MSG_VALID 15 15 VMHV_MAILBOX_RCV_MSG_DATA 16 19 VMHV_MAILBOX_RCV_MSG_VALID 23 23 VMHV_MAILBOX_TRN_MSG_ACK 24 24 VMHV_MAILBOX_RCV_MSG_ACK 25 25 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0 0x400 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0 0x401 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0 0x402 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0 0x403 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0 0x404 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0 0x405 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0 0x406 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0 0x407 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0 0x408 1 0 3 MSG_ADDR_LO 2 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0 0x409 1 0 3 MSG_ADDR_HI 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0 0x40a 1 0 3 MSG_DATA 0 31 mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0 0x40b 1 0 3 MASK_BIT 0 0 mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0 0x800 3 0 3 MSIX_PENDING_BITS_0 0 0 MSIX_PENDING_BITS_1 1 1 MSIX_PENDING_BITS_2 2 2