246 ixCLIENT0_BM 2 0x220 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD0 2 0x210 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD1 2 0x214 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD2 2 0x218 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD3 2 0x21c 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK0 2 0x200 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK1 2 0x204 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK2 2 0x208 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK3 2 0x20c 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K0 2 0x1f0 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K1 2 0x1f4 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K2 2 0x1f8 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K3 2 0x1fc 1 0 4294967295 RESERVED 0 31 ixCLIENT0_OFFSET 2 0x224 1 0 4294967295 RESERVED 0 31 ixCLIENT0_OFFSET_HI 2 0x290 1 0 4294967295 RESERVED 0 31 ixCLIENT0_STATUS 2 0x228 1 0 4294967295 RESERVED 0 31 ixCLIENT1_BM 2 0x25c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD0 2 0x24c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD1 2 0x250 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD2 2 0x254 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD3 2 0x258 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK0 2 0x23c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK1 2 0x240 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK2 2 0x244 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK3 2 0x248 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K0 2 0x22c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K1 2 0x230 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K2 2 0x234 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K3 2 0x238 1 0 4294967295 RESERVED 0 31 ixCLIENT1_OFFSET 2 0x260 1 0 4294967295 RESERVED 0 31 ixCLIENT1_OFFSET_HI 2 0x294 1 0 4294967295 RESERVED 0 31 ixCLIENT1_PORT_STATUS 2 0x264 1 0 4294967295 RESERVED 0 31 ixCLIENT2_BM 2 0x1e4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD0 2 0x1d4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD1 2 0x1d8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD2 2 0x1dc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD3 2 0x1e0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK0 2 0x1c4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK1 2 0x1c8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK2 2 0x1cc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK3 2 0x1d0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K0 2 0x1b4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K1 2 0x1b8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K2 2 0x1bc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K3 2 0x1c0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_OFFSET 2 0x1e8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_OFFSET_HI 2 0x298 1 0 4294967295 RESERVED 0 31 ixCLIENT2_STATUS 2 0x1ec 1 0 4294967295 RESERVED 0 31 ixCLIENT3_BM 2 0x2d4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD0 2 0x2c4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD1 2 0x2c8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD2 2 0x2cc 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD3 2 0x2d0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK0 2 0x2b4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK1 2 0x2b8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK2 2 0x2bc 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK3 2 0x2c0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K0 2 0x2a4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K1 2 0x2a8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K2 2 0x2ac 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K3 2 0x2b0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_OFFSET 2 0x2d8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_OFFSET_HI 2 0x2a0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_STATUS 2 0x2dc 1 0 4294967295 RESERVED 0 31 ixDH_TEST 2 0x0 1 0 4294967295 DH_TEST 0 0 ixEXP0 2 0x34 1 0 4294967295 RESERVED 0 31 ixEXP1 2 0x38 1 0 4294967295 RESERVED 0 31 ixEXP2 2 0x3c 1 0 4294967295 RESERVED 0 31 ixEXP3 2 0x40 1 0 4294967295 RESERVED 0 31 ixEXP4 2 0x44 1 0 4294967295 RESERVED 0 31 ixEXP5 2 0x48 1 0 4294967295 RESERVED 0 31 ixEXP6 2 0x4c 1 0 4294967295 RESERVED 0 31 ixEXP7 2 0x50 1 0 4294967295 RESERVED 0 31 ixHFS_SEED0 2 0x278 1 0 4294967295 RESERVED 0 31 ixHFS_SEED1 2 0x27c 1 0 4294967295 RESERVED 0 31 ixHFS_SEED2 2 0x280 1 0 4294967295 RESERVED 0 31 ixHFS_SEED3 2 0x284 1 0 4294967295 RESERVED 0 31 ixKEFUSE0 2 0x268 1 0 4294967295 RESERVED 0 31 ixKEFUSE1 2 0x26c 1 0 4294967295 RESERVED 0 31 ixKEFUSE2 2 0x270 1 0 4294967295 RESERVED 0 31 ixKEFUSE3 2 0x274 1 0 4294967295 RESERVED 0 31 ixKHFS0 2 0x4 1 0 4294967295 RESERVED 0 31 ixKHFS1 2 0x8 1 0 4294967295 RESERVED 0 31 ixKHFS2 2 0xc 1 0 4294967295 RESERVED 0 31 ixKHFS3 2 0x10 1 0 4294967295 RESERVED 0 31 ixKSESSION0 2 0x14 1 0 4294967295 RESERVED 0 31 ixKSESSION1 2 0x18 1 0 4294967295 RESERVED 0 31 ixKSESSION2 2 0x1c 1 0 4294967295 RESERVED 0 31 ixKSESSION3 2 0x20 1 0 4294967295 RESERVED 0 31 ixKSIG0 2 0x24 1 0 4294967295 RESERVED 0 31 ixKSIG1 2 0x28 1 0 4294967295 RESERVED 0 31 ixKSIG2 2 0x2c 1 0 4294967295 RESERVED 0 31 ixKSIG3 2 0x30 1 0 4294967295 RESERVED 0 31 ixLX0 2 0x54 1 0 4294967295 RESERVED 0 31 ixLX1 2 0x58 1 0 4294967295 RESERVED 0 31 ixLX2 2 0x5c 1 0 4294967295 RESERVED 0 31 ixLX3 2 0x60 1 0 4294967295 RESERVED 0 31 ixRINGOSC_MASK 2 0x288 1 0 4294967295 MASK 0 15 ixSPU_PORT_STATUS 2 0x29c 1 0 4294967295 RESERVED 0 31 mmCC_DRM_ID_STRAPS 0 0x1559 4 0 4294967295 ATI_REV_ID 28 31 DEVICE_ID 4 19 MAJOR_REV_ID 20 23 MINOR_REV_ID 24 27 mmCC_SYS_RB_BACKEND_DISABLE 0 0x3a0 1 0 4294967295 BACKEND_DISABLE 16 23 mmCC_SYS_RB_REDUNDANCY 0 0x39f 0 0 4294967295 mmCGTT_DRM_CLK_CTRL0 0 0x1579 0 0 4294967295 mmCP_CONFIG 0 0xf92 2 0 4294967295 CP_RDREQ_URG 8 11 CP_REQ_TRAN 16 16 mmDC_TEST_DEBUG_DATA 0 0x157d 1 0 4294967295 DC_TEST_DEBUG_DATA 0 31 mmDC_TEST_DEBUG_INDEX 0 0x157c 2 0 4294967295 DC_TEST_DEBUG_INDEX 0 7 DC_TEST_DEBUG_WRITE_EN 8 8 mmGC_USER_SYS_RB_BACKEND_DISABLE 0 0x3a1 1 0 4294967295 BACKEND_DISABLE 16 23 mmHDP_ADDR_CONFIG 0 0xbd2 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmHDP_DEBUG0 0 0xbcc 1 0 4294967295 HDP_DEBUG 0 0 mmHDP_DEBUG1 0 0xbcd 1 0 4294967295 HDP_DEBUG 0 0 mmHDP_HOST_PATH_CNTL 0 0xb00 12 0 4294967295 ALL_SURFACES_DIS 29 29 BIF_RDRET_CREDIT 0 2 CACHE_INVALIDATE 22 22 CLOCK_GATING_DIS 23 23 LIN_RD_CACHE_DIS 31 31 MC_WRREQ_CREDIT 3 8 RD_STALL_TIMER 11 12 REG_CLK_ENABLE_COUNT 24 27 WRITE_COMBINE_EN 21 21 WRITE_COMBINE_TIMER 19 20 WRITE_THROUGH_CACHE_DIS 30 30 WR_STALL_TIMER 9 10 mmHDP_LAST_SURFACE_HIT 0 0xbce 1 0 4294967295 LAST_SURFACE_HIT 0 5 mmHDP_MEMIO_ADDR 0 0xbf7 1 0 4294967295 MEMIO_ADDR_LOWER 0 31 mmHDP_MEMIO_CNTL 0 0xbf6 8 0 4294967295 MEMIO_ADDR_UPPER 8 13 MEMIO_BE 2 5 MEMIO_CLR_RD_ERROR 15 15 MEMIO_CLR_WR_ERROR 14 14 MEMIO_OP 1 1 MEMIO_RD_STROBE 7 7 MEMIO_SEND 0 0 MEMIO_WR_STROBE 6 6 mmHDP_MEMIO_RD_DATA 0 0xbfa 1 0 4294967295 MEMIO_RD_DATA 0 31 mmHDP_MEMIO_STATUS 0 0xbf8 4 0 4294967295 MEMIO_RD_ERROR 3 3 MEMIO_RD_STATUS 1 1 MEMIO_WR_ERROR 2 2 MEMIO_WR_STATUS 0 0 mmHDP_MEMIO_WR_DATA 0 0xbf9 1 0 4294967295 MEMIO_WR_DATA 0 31 mmHDP_MEM_POWER_LS 0 0xbd4 3 0 4294967295 LS_ENABLE 0 0 LS_HOLD 7 12 LS_SETUP 1 6 mmHDP_MISC_CNTL 0 0xbd3 11 0 4294967295 ADDRLIB_LINEAR_BYPASS 20 20 FED_ENABLE 21 21 FLUSH_INVALIDATE_CACHE 0 0 HDP_BIF_RDRET_CREDIT 7 10 MC_RDREQ_CREDIT 13 18 MULTIPLE_READS 6 6 NO_SPLIT_ARRAY_LINEAR 12 12 OUTSTANDING_WRITE_COUNT_1024 5 5 READ_CACHE_INVALIDATE 19 19 SIMULTANEOUS_READS_WRITES 11 11 VM_ID 1 4 mmHDP_NONSURFACE_BASE 0 0xb01 1 0 4294967295 NONSURF_BASE 0 31 mmHDP_NONSURFACE_INFO 0 0xb02 15 0 4294967295 NONSURF_ADDR_TYPE 0 0 NONSURF_ARRAY_MODE 1 4 NONSURF_BANK_HEIGHT 24 25 NONSURF_BANK_WIDTH 22 23 NONSURF_ENDIAN 5 6 NONSURF_MACRO_TILE_ASPECT 26 27 NONSURF_MICRO_TILE_MODE 28 29 NONSURF_NUM_BANKS 20 21 NONSURF_PIXEL_SIZE 7 9 NONSURF_PRIV 15 15 NONSURF_SAMPLE_NUM 10 12 NONSURF_SAMPLE_SIZE 13 14 NONSURF_SLICE_TILE_MAX_MSB 30 30 NONSURF_TILE_COMPACT 16 16 NONSURF_TILE_SPLIT 17 19 mmHDP_NONSURFACE_PREFETCH 0 0xbd5 5 0 4294967295 NONSURF_PIPE_CONFIG 27 31 NONSURF_PREFETCH_DIR 3 5 NONSURF_PREFETCH_MAX_Z 9 19 NONSURF_PREFETCH_NUM 6 8 NONSURF_PREFETCH_PRI 0 2 mmHDP_NONSURFACE_SIZE 0 0xb03 2 0 4294967295 NONSURF_PITCH_TILE_MAX 0 10 NONSURF_SLICE_TILE_MAX 11 31 mmHDP_NONSURF_FLAGS 0 0xbc9 2 0 4294967295 NONSURF_READ_FLAG 1 1 NONSURF_WRITE_FLAG 0 0 mmHDP_NONSURF_FLAGS_CLR 0 0xbca 2 0 4294967295 NONSURF_READ_FLAG_CLR 1 1 NONSURF_WRITE_FLAG_CLR 0 0 mmHDP_OUTSTANDING_REQ 0 0xbd1 2 0 4294967295 READ_REQ 8 15 WRITE_REQ 0 7 mmHDP_SC_MULTI_CHIP_CNTL 0 0xbd0 2 0 4294967295 LOG2_NUM_CHIPS 0 2 MULTI_CHIP_TILE_SIZE 3 4 mmHDP_SW_SEMAPHORE 0 0xbcb 1 0 4294967295 SW_SEMAPHORE 0 31 mmHDP_TILING_CONFIG 0 0xbcf 6 0 4294967295 BANK_SWAPS 11 13 BANK_TILING 4 5 GROUP_SIZE 6 7 PIPE_TILING 1 3 ROW_TILING 8 10 SAMPLE_SPLIT 14 15 mmHDP_XDP_BARS_ADDR_39_36 0 0xc44 8 0 4294967295 BAR0_ADDR_39_36 0 3 BAR1_ADDR_39_36 4 7 BAR2_ADDR_39_36 8 11 BAR3_ADDR_39_36 12 15 BAR4_ADDR_39_36 16 19 BAR5_ADDR_39_36 20 23 BAR6_ADDR_39_36 24 27 BAR7_ADDR_39_36 28 31 mmHDP_XDP_BUSY_STS 0 0xc3e 1 0 4294967295 BUSY_BITS 0 17 mmHDP_XDP_CGTT_BLK_CTRL 0 0xc33 5 0 4294967295 CGTT_BLK_CTRL_0_ON_DELAY 0 3 CGTT_BLK_CTRL_1_OFF_DELAY 4 11 CGTT_BLK_CTRL_2_RSVD 12 29 CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE 30 30 CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE 31 31 mmHDP_XDP_CHKN 0 0xc40 4 0 4294967295 CHKN_0_RSVD 0 7 CHKN_1_RSVD 8 15 CHKN_2_RSVD 16 23 CHKN_3_RSVD 24 31 mmHDP_XDP_D2H_BAR_UPDATE 0 0xc02 3 0 4294967295 D2H_BAR_UPDATE_ADDR 0 15 D2H_BAR_UPDATE_BAR_NUM 20 22 D2H_BAR_UPDATE_FLUSH_NUM 16 19 mmHDP_XDP_D2H_FLUSH 0 0xc01 9 0 4294967295 D2H_FLUSH_ALTER_FLUSH_NUM 18 18 D2H_FLUSH_FLUSH_NUM 0 3 D2H_FLUSH_MBX_ADDR_SEL 8 10 D2H_FLUSH_MBX_ENC_DATA 4 7 D2H_FLUSH_RSVD_0 19 19 D2H_FLUSH_RSVD_1 20 20 D2H_FLUSH_SEND_HOST 16 16 D2H_FLUSH_SEND_SIDE 17 17 D2H_FLUSH_XPB_CLG 11 15 mmHDP_XDP_D2H_RSVD_10 0 0xc0a 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_11 0 0xc0b 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_12 0 0xc0c 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_13 0 0xc0d 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_14 0 0xc0e 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_15 0 0xc0f 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_16 0 0xc10 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_17 0 0xc11 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_18 0 0xc12 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_19 0 0xc13 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_20 0 0xc14 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_21 0 0xc15 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_22 0 0xc16 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_23 0 0xc17 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_24 0 0xc18 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_25 0 0xc19 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_26 0 0xc1a 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_27 0 0xc1b 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_28 0 0xc1c 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_29 0 0xc1d 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_30 0 0xc1e 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_3 0 0xc03 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_31 0 0xc1f 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_32 0 0xc20 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_33 0 0xc21 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_34 0 0xc22 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_4 0 0xc04 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_5 0 0xc05 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_6 0 0xc06 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_7 0 0xc07 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_8 0 0xc08 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_9 0 0xc09 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_DBG_ADDR 0 0xc41 2 0 4294967295 CTRL 16 31 STS 0 15 mmHDP_XDP_DBG_DATA 0 0xc42 2 0 4294967295 CTRL 16 31 STS 0 15 mmHDP_XDP_DBG_MASK 0 0xc43 2 0 4294967295 CTRL 16 31 STS 0 15 mmHDP_XDP_DIRECT2HDP_FIRST 0 0xc00 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_DIRECT2HDP_LAST 0 0xc23 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_FLUSH_ARMED_STS 0 0xc3c 1 0 4294967295 FLUSH_ARMED_STS 0 31 mmHDP_XDP_FLUSH_CNTR0_STS 0 0xc3d 1 0 4294967295 FLUSH_CNTR0_STS 0 25 mmHDP_XDP_HDP_IPH_CFG 0 0xc31 4 0 4294967295 HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING 12 12 HDP_IPH_CFG_P2P_RD_EN 13 13 HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE 0 5 HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE 6 11 mmHDP_XDP_HDP_MBX_MC_CFG 0 0xc2d 4 0 4294967295 HDP_MBX_MC_CFG_TAP_WRREQ_PRIV 0 0 HDP_MBX_MC_CFG_TAP_WRREQ_SWAP 1 2 HDP_MBX_MC_CFG_TAP_WRREQ_TRAN 3 3 HDP_MBX_MC_CFG_TAP_WRREQ_VMID 4 7 mmHDP_XDP_HDP_MC_CFG 0 0xc2e 11 0 4294967295 HDP_MC_CFG_HST_TAP_WRREQ_PRIV 0 0 HDP_MC_CFG_HST_TAP_WRREQ_SWAP 1 2 HDP_MC_CFG_HST_TAP_WRREQ_TRAN 3 3 HDP_MC_CFG_HST_TAP_WRREQ_VMID 23 26 HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK 20 22 HDP_MC_CFG_SID_TAP_WRREQ_PRIV 4 4 HDP_MC_CFG_SID_TAP_WRREQ_SWAP 5 6 HDP_MC_CFG_SID_TAP_WRREQ_TRAN 7 7 HDP_MC_CFG_SID_TAP_WRREQ_VMID 27 30 HDP_MC_CFG_XDP_HIGHER_PRI_THRESH 14 19 HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE 8 13 mmHDP_XDP_HST_CFG 0 0xc2f 2 0 4294967295 HST_CFG_WR_COMBINE_EN 0 0 HST_CFG_WR_COMBINE_TIMER 1 2 mmHDP_XDP_P2P_BAR0 0 0xc34 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR1 0 0xc35 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR2 0 0xc36 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR3 0 0xc37 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR4 0 0xc38 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR5 0 0xc39 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR6 0 0xc3a 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR7 0 0xc3b 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR_CFG 0 0xc24 2 0 4294967295 P2P_BAR_CFG_ADDR_SIZE 0 3 P2P_BAR_CFG_BAR_FROM 4 5 mmHDP_XDP_P2P_MBX_ADDR0 0 0xc26 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR1 0 0xc27 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR2 0 0xc28 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR3 0 0xc29 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR4 0 0xc2a 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR5 0 0xc2b 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_ADDR6 0 0xc2c 3 0 4294967295 ADDR_39_36 21 24 ADDR 1 20 VALID 0 0 mmHDP_XDP_P2P_MBX_OFFSET 0 0xc25 1 0 4294967295 P2P_MBX_OFFSET 0 13 mmHDP_XDP_SID_CFG 0 0xc30 3 0 4294967295 SID_CFG_FLNUM_MSB_SEL 3 4 SID_CFG_WR_COMBINE_EN 0 0 SID_CFG_WR_COMBINE_TIMER 1 2 mmHDP_XDP_SRBM_CFG 0 0xc32 3 0 4294967295 SRBM_CFG_REG_CLK_ENABLE_COUNT 0 5 SRBM_CFG_REG_CLK_GATING_DIS 6 6 SRBM_CFG_WAKE_DYN_CLK 7 7 mmHDP_XDP_STICKY 0 0xc3f 2 0 4294967295 STICKY_STS 0 15 STICKY_W1C 16 31 mmIH_ADVFAULT_CNTL 0 0xf8c 5 0 4294967295 NUM_FAULTS_DROPPED 8 15 WAIT_TIMER 16 29 WATERMARK_ENABLE 3 3 WATERMARK 0 2 WATERMARK_REACHED 4 4 mmIH_CNTL 0 0xf86 9 0 4294967295 CLIENT_FIFO_HIGHWATER 8 9 ENABLE_INTR 0 0 MC_FIFO_HIGHWATER 10 14 MC_SWAP 1 2 MC_TRAN 3 3 MC_VMID 25 28 MC_WR_CLEAN_CNT 20 24 MC_WRREQ_CREDIT 15 19 RPTR_REARM 4 4 mmIH_LEVEL_STATUS 0 0xf87 5 0 4294967295 BIF_STATUS 4 4 DC_STATUS 0 0 ROM_STATUS 2 2 SRBM_STATUS 3 3 XDMA_STATUS 5 5 mmIH_PERFCOUNTER0_RESULT 0 0xf8a 1 0 4294967295 PERF_COUNT 0 31 mmIH_PERFCOUNTER1_RESULT 0 0xf8b 1 0 4294967295 PERF_COUNT 0 31 mmIH_PERFMON_CNTL 0 0xf89 6 0 4294967295 CLEAR0 1 1 CLEAR1 9 9 ENABLE0 0 0 ENABLE1 8 8 PERF_SEL0 2 7 PERF_SEL1 10 15 mmIH_RB_BASE 0 0xf81 1 0 4294967295 ADDR 0 31 mmIH_RB_CNTL 0 0xf80 8 0 4294967295 RB_ENABLE 0 0 RB_FULL_DRAIN_ENABLE 6 6 RB_GPU_TS_ENABLE 7 7 RB_SIZE 1 5 WPTR_OVERFLOW_CLEAR 31 31 WPTR_OVERFLOW_ENABLE 16 16 WPTR_WRITEBACK_ENABLE 8 8 WPTR_WRITEBACK_TIMER 9 13 mmIH_RB_RPTR 0 0xf82 1 0 4294967295 OFFSET 2 17 mmIH_RB_WPTR 0 0xf83 2 0 4294967295 OFFSET 2 17 RB_OVERFLOW 0 0 mmIH_RB_WPTR_ADDR_HI 0 0xf84 1 0 4294967295 ADDR 0 7 mmIH_RB_WPTR_ADDR_LO 0 0xf85 1 0 4294967295 ADDR 2 31 mmIH_STATUS 0 0xf88 11 0 4294967295 BIF_INTERRUPT_LINE 10 10 IDLE 0 0 INPUT_IDLE 1 1 MC_WR_CLEAN_PENDING 8 8 MC_WR_CLEAN_STALL 9 9 MC_WR_IDLE 6 6 MC_WR_STALL 7 7 RB_FULL_DRAIN 4 4 RB_FULL 3 3 RB_IDLE 2 2 RB_OVERFLOW 5 5 mmSEM_MAILBOX 0 0xf9b 2 0 4294967295 HOSTPORT 8 15 SIDEPORT 0 7 mmSEM_MAILBOX_CLIENTCONFIG 0 0xf9a 6 0 4294967295 CP_CLIENT0 0 2 CP_CLIENT1 3 5 CP_CLIENT2 6 8 CP_CLIENT3 9 11 UVD_CLIENT0 15 17 VCE_CLIENT0 21 23 mmSEM_MAILBOX_CONTROL 0 0xf9c 2 0 4294967295 HOSTPORT_ENABLE 8 15 SIDEPORT_ENABLE 0 7 mmSEM_MCIF_CONFIG 0 0xf90 1 0 4294967295 MC_REQ_SWAP 0 1 mmSRBM_CAM_DATA 0 0x397 2 0 4294967295 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 mmSRBM_CAM_INDEX 0 0x396 1 0 4294967295 CAM_INDEX 0 2 mmSRBM_CHIP_REVISION 0 0x39b 1 0 4294967295 CHIP_REVISION 0 7 mmSRBM_CNTL 0 0x390 3 0 4294967295 COMBINE_SYSTEM_MC 17 17 PWR_REQUEST_HALT 16 16 READ_TIMEOUT 0 9 mmSRBM_DEBUG 0 0x3a4 7 0 4294967295 DISABLE_READ_TIMEOUT 1 1 IGNORE_RDY 0 0 MC_CLOCK_DOMAIN_OVERRIDE 8 8 SNAPSHOT_FREE_CNTRS 2 2 SYS_CLOCK_DOMAIN_OVERRIDE 4 4 UVD_CLOCK_DOMAIN_OVERRIDE 6 6 VCE_CLOCK_DOMAIN_OVERRIDE 5 5 mmSRBM_DEBUG_CNTL 0 0x399 1 0 4294967295 SRBM_DEBUG_INDEX 0 5 mmSRBM_DEBUG_DATA 0 0x39a 1 0 4294967295 DATA 0 31 mmSRBM_DEBUG_SNAPSHOT 0 0x3a5 26 0 4294967295 BIF_RDY 7 7 DC_RDY 6 6 GRBM_RDY 5 5 MCB_RDY 0 0 MCC0_RDY 28 28 MCC1_RDY 27 27 MCC2_RDY 26 26 MCC3_RDY 25 25 MCC4_RDY 24 24 MCC5_RDY 23 23 MCC6_RDY 22 22 MCC7_RDY 21 21 MCD0_RDY 20 20 MCD1_RDY 19 19 MCD2_RDY 18 18 MCD3_RDY 17 17 MCD4_RDY 16 16 MCD5_RDY 15 15 MCD6_RDY 14 14 MCD7_RDY 13 13 ORB_RDY 12 12 REGBB_RDY 11 11 UVD_RDY 9 9 VCE_RDY 29 29 XDMA_RDY 8 8 XSP_RDY 10 10 mmSRBM_GFX_CNTL 0 0x391 1 0 4294967295 VMID 4 7 mmSRBM_INT_ACK 0 0x3aa 1 0 4294967295 RDERR_INT_ACK 0 0 mmSRBM_INT_CNTL 0 0x3a8 1 0 4294967295 RDERR_INT_MASK 0 0 mmSRBM_INT_STATUS 0 0x3a9 1 0 4294967295 RDERR_INT_STAT 0 0 mmSRBM_MC_CLKEN_CNTL 0 0x3b3 2 0 4294967295 POST_DELAY_CNT 8 12 PREFIX_DELAY_CNT 0 3 mmSRBM_PERFCOUNTER0_HI 0 0x704 1 0 4294967295 PERF_COUNT0_HI 0 31 mmSRBM_PERFCOUNTER0_LO 0 0x703 1 0 4294967295 PERF_COUNT0_LO 0 31 mmSRBM_PERFCOUNTER0_SELECT 0 0x701 1 0 4294967295 PERF_SEL 0 5 mmSRBM_PERFCOUNTER1_HI 0 0x706 1 0 4294967295 PERF_COUNT1_HI 0 31 mmSRBM_PERFCOUNTER1_LO 0 0x705 1 0 4294967295 PERF_COUNT1_LO 0 31 mmSRBM_PERFCOUNTER1_SELECT 0 0x702 1 0 4294967295 PERF_SEL 0 5 mmSRBM_PERFMON_CNTL 0 0x700 3 0 4294967295 PERFMON_ENABLE_MODE 8 9 PERFMON_SAMPLE_ENABLE 10 10 PERFMON_STATE 0 3 mmSRBM_READ_ERROR 0 0x3a6 8 0 4294967295 READ_ADDRESS 2 17 READ_ERROR 31 31 READ_REQUESTER_GRBM 25 25 READ_REQUESTER_HI 24 24 READ_REQUESTER_SMU 26 26 READ_REQUESTER_TST 22 22 READ_REQUESTER_UVD 29 29 READ_REQUESTER_VCE 20 20 mmSRBM_SOFT_RESET 0 0x398 16 0 4294967295 SOFT_RESET_BIF 1 1 SOFT_RESET_DC 5 5 SOFT_RESET_GRBM 8 8 SOFT_RESET_HDP 9 9 SOFT_RESET_IH 10 10 SOFT_RESET_MC 11 11 SOFT_RESET_ORB 23 23 SOFT_RESET_REGBB 22 22 SOFT_RESET_ROM 14 14 SOFT_RESET_SEM 15 15 SOFT_RESET_TST 21 21 SOFT_RESET_UVD 18 18 SOFT_RESET_VCE 24 24 SOFT_RESET_VMC 17 17 SOFT_RESET_XDMA 25 25 SOFT_RESET_XSP 19 19 mmSRBM_STATUS 0 0x394 14 0 4294967295 BIF_BUSY 29 29 GRBM_RQ_PENDING 5 5 HI_RQ_PENDING 6 6 IH_BUSY 17 17 IO_EXTERN_SIGNAL 7 7 MCB_BUSY 9 9 MCB_NON_DISPLAY_BUSY 10 10 MCC_BUSY 11 11 MCD_BUSY 12 12 SEM_BUSY 14 14 SMU_RQ_PENDING 4 4 UVD_BUSY 19 19 UVD_RQ_PENDING 1 1 VMC_BUSY 8 8 mmSRBM_STATUS2 0 0x393 5 0 4294967295 TST_RQ_PENDING 1 1 VCE_BUSY 7 7 VCE_RQ_PENDING 3 3 XDMA_BUSY 8 8 XSP_BUSY 4 4 mmSRBM_SYS_CLKEN_CNTL 0 0x3b4 2 0 4294967295 POST_DELAY_CNT 8 12 PREFIX_DELAY_CNT 0 3 mmSRBM_UVD_CLKEN_CNTL 0 0x3b6 2 0 4294967295 POST_DELAY_CNT 8 12 PREFIX_DELAY_CNT 0 3 mmSRBM_VCE_CLKEN_CNTL 0 0x3b5 2 0 4294967295 POST_DELAY_CNT 8 12 PREFIX_DELAY_CNT 0 3 mmUVD_CONFIG 0 0xf98 2 0 4294967295 UVD_RDREQ_URG 8 11 UVD_REQ_TRAN 16 16 mmVCE_CONFIG 0 0xf94 2 0 4294967295 VCE_RDREQ_URG 8 11 VCE_REQ_TRAN 16 16 mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0 0x3f8 3 0 4294967295 XDMA_MSTR_OVERFLOW_COUNT_ENABLE 31 31 XDMA_MSTR_OVERFLOW_COUNT 0 15 XDMA_MSTR_OVERFLOW_THRESHOLD 16 29 mmDMA_TILING_CONFIG 0 0x342e 0 0 4294967295