660 mmIH_VMID_0_LUT 0 0xe00 1 0 4294967295 PASID 0 15 mmIH_VMID_1_LUT 0 0xe01 1 0 4294967295 PASID 0 15 mmIH_VMID_2_LUT 0 0xe02 1 0 4294967295 PASID 0 15 mmIH_VMID_3_LUT 0 0xe03 1 0 4294967295 PASID 0 15 mmIH_VMID_4_LUT 0 0xe04 1 0 4294967295 PASID 0 15 mmIH_VMID_5_LUT 0 0xe05 1 0 4294967295 PASID 0 15 mmIH_VMID_6_LUT 0 0xe06 1 0 4294967295 PASID 0 15 mmIH_VMID_7_LUT 0 0xe07 1 0 4294967295 PASID 0 15 mmIH_VMID_8_LUT 0 0xe08 1 0 4294967295 PASID 0 15 mmIH_VMID_9_LUT 0 0xe09 1 0 4294967295 PASID 0 15 mmIH_VMID_10_LUT 0 0xe0a 1 0 4294967295 PASID 0 15 mmIH_VMID_11_LUT 0 0xe0b 1 0 4294967295 PASID 0 15 mmIH_VMID_12_LUT 0 0xe0c 1 0 4294967295 PASID 0 15 mmIH_VMID_13_LUT 0 0xe0d 1 0 4294967295 PASID 0 15 mmIH_VMID_14_LUT 0 0xe0e 1 0 4294967295 PASID 0 15 mmIH_VMID_15_LUT 0 0xe0f 1 0 4294967295 PASID 0 15 mmIH_RB_CNTL 0 0xe30 9 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_GPU_TS_ENABLE 7 7 WPTR_WRITEBACK_ENABLE 8 8 ENABLE_INTR 17 17 MC_SWAP 18 19 RPTR_REARM 21 21 MC_VMID 24 27 WPTR_OVERFLOW_CLEAR 31 31 mmIH_RB_BASE 0 0xe31 1 0 4294967295 ADDR 0 31 mmIH_RB_RPTR 0 0xe32 1 0 4294967295 OFFSET 2 17 mmIH_RB_WPTR 0 0xe33 4 0 4294967295 RB_OVERFLOW 0 0 OFFSET 2 17 RB_LEFT_NONE 18 18 RB_MAY_OVERFLOW 19 19 mmIH_RB_WPTR_ADDR_HI 0 0xe34 1 0 4294967295 ADDR 0 7 mmIH_RB_WPTR_ADDR_LO 0 0xe35 1 0 4294967295 ADDR 2 31 mmIH_CNTL 0 0xe36 5 0 4294967295 WPTR_WRITEBACK_TIMER 0 4 CLIENT_FIFO_HIGHWATER 8 9 MC_FIFO_HIGHWATER 10 14 MC_WRREQ_CREDIT 15 19 MC_WR_CLEAN_CNT 20 24 mmIH_LEVEL_STATUS 0 0xe37 5 0 4294967295 DC_STATUS 0 0 ROM_STATUS 2 2 SRBM_STATUS 3 3 BIF_STATUS 4 4 XDMA_STATUS 5 5 mmIH_STATUS 0 0xe38 12 0 4294967295 IDLE 0 0 INPUT_IDLE 1 1 RB_IDLE 2 2 RB_FULL 3 3 RB_FULL_DRAIN 4 4 RB_OVERFLOW 5 5 MC_WR_IDLE 6 6 MC_WR_STALL 7 7 MC_WR_CLEAN_PENDING 8 8 MC_WR_CLEAN_STALL 9 9 BIF_INTERRUPT_LINE 10 10 SWITCH_READY 11 11 mmIH_PERFMON_CNTL 0 0xe39 6 0 4294967295 ENABLE0 0 0 CLEAR0 1 1 PERF_SEL0 2 9 ENABLE1 10 10 CLEAR1 11 11 PERF_SEL1 12 19 mmIH_PERFCOUNTER0_RESULT 0 0xe3a 1 0 4294967295 PERF_COUNT 0 31 mmIH_PERFCOUNTER1_RESULT 0 0xe3b 1 0 4294967295 PERF_COUNT 0 31 mmIH_DEBUG 0 0xe3c 3 0 4294967295 RB_FULL_DRAIN_ENABLE 0 0 WPTR_OVERFLOW_ENABLE 1 1 MC_WR_FIFO_BLOCK_ENABLE 2 2 mmIH_DSM_MATCH_VALUE_BIT_31_0 0 0xe3d 1 0 4294967295 VALUE 0 31 mmIH_DSM_MATCH_VALUE_BIT_63_32 0 0xe3e 1 0 4294967295 VALUE 0 31 mmIH_DSM_MATCH_VALUE_BIT_95_64 0 0xe3f 1 0 4294967295 VALUE 0 31 mmIH_DSM_MATCH_FIELD_CONTROL 0 0xe40 6 0 4294967295 SRC_EN 0 0 FCNID_EN 1 1 TIMESTAMP_EN 2 2 RINGID_EN 3 3 VMID_EN 4 4 PASID_EN 5 5 mmIH_DSM_MATCH_DATA_CONTROL 0 0xe41 1 0 4294967295 VALUE 0 27 mmIH_DOORBELL_RPTR 0 0xe42 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmIH_ACTIVE_FCN_ID 0 0xe43 3 0 4294967295 VF_ID 0 3 RESERVED 4 30 PF_VF 31 31 mmIH_VF_RB_STATUS 0 0xe44 2 0 4294967295 RB_FULL_DRAIN_VF 0 15 RB_OVERFLOW_VF 16 31 mmIH_VF_ENABLE 0 0xe45 1 0 4294967295 VALUE 0 0 mmIH_VIRT_RESET_REQ 0 0xe46 2 0 4294967295 VF 0 15 PF 31 31 mmIH_VF_RB_BIF_STATUS 0 0xe47 2 0 4294967295 RB_FULL_VF 0 15 BIF_INTERRUPT_LINE_VF 16 31 mmIH_VERSION 0 0xe48 1 0 4294967295 VALUE 0 11 mmIH_LEVEL_INTR_MASK 0 0xe49 1 0 4294967295 MASK 0 0 mmIH_RESET_INCOMPLETE_INT_CNTL 0 0xe4a 23 0 4294967295 CG 0 0 DC 1 1 SAMMSP 3 3 RLC 4 4 ROM 5 5 SRBM 6 6 VMC 7 7 UVD 8 8 BIF 9 9 SDMA0 10 10 SDMA1 11 11 ISP 12 12 VCE0 13 13 VCE1 14 14 ATC 15 15 XDMA 16 16 ACP 17 17 SH 18 18 SH1 19 19 SH2 20 20 SH3 21 21 RESET_ENABLE 22 22 INCOMPLETE_CNT 24 27 mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT 0 0xe4b 21 0 4294967295 CG 0 0 DC 1 1 SAMMSP 3 3 RLC 4 4 ROM 5 5 SRBM 6 6 VMC 7 7 UVD 8 8 BIF 9 9 SDMA0 10 10 SDMA1 11 11 ISP 12 12 VCE0 13 13 VCE1 14 14 ATC 15 15 XDMA 16 16 ACP 17 17 SH 18 18 SH1 19 19 SH2 20 20 SH3 21 21 mmSEM_MCIF_CONFIG 0 0xf90 3 0 4294967295 MC_REQ_SWAP 0 1 MC_WRREQ_CREDIT 2 7 MC_RDREQ_CREDIT 8 13 mmSDMA_CONFIG 0 0xf91 2 0 4294967295 SDMA_RDREQ_URG 8 11 SDMA_REQ_TRAN 16 16 mmSDMA1_CONFIG 0 0xf92 2 0 4294967295 SDMA_RDREQ_URG 8 11 SDMA_REQ_TRAN 16 16 mmUVD_CONFIG 0 0xf93 2 0 4294967295 UVD_RDREQ_URG 8 11 UVD_REQ_TRAN 16 16 mmVCE_CONFIG 0 0xf94 2 0 4294967295 VCE_RDREQ_URG 8 11 VCE_REQ_TRAN 16 16 mmSEM_VF_ENABLE 0 0xf95 1 0 4294967295 VALUE 0 0 mmCP_CONFIG 0 0xf96 2 0 4294967295 CP_RDREQ_URG 8 11 CP_REQ_TRAN 16 16 mmSEM_ACTIVE_FCN_ID 0 0xf97 2 0 4294967295 VFID 0 3 VF 31 31 mmSEM_VIRT_RESET_REQ 0 0xf98 2 0 4294967295 VF 0 15 PF 31 31 mmSEM_STATUS 0 0xf99 16 0 4294967295 SEM_IDLE 0 0 SEM_INTERNAL_IDLE 1 1 MC_RDREQ_FIFO_FULL 2 2 MC_WRREQ_FIFO_FULL 3 3 WRITE1_FIFO_FULL 4 4 CHECK0_FIFO_FULL 5 5 MC_RDREQ_PENDING 6 6 MC_WRREQ_PENDING 7 7 SDMA0_MAILBOX_PENDING 8 8 SDMA1_MAILBOX_PENDING 9 9 UVD_MAILBOX_PENDING 10 10 VCE_MAILBOX_PENDING 11 11 CPG1_MAILBOX_PENDING 12 12 CPG2_MAILBOX_PENDING 13 13 VCE1_MAILBOX_PENDING 14 14 SWITCH_READY 31 31 mmSEM_EDC_CONFIG 0 0xf9a 1 0 4294967295 DIS_EDC 1 1 mmSEM_MAILBOX_CLIENTCONFIG 0 0xf9b 8 0 4294967295 CP_CLIENT0 0 2 CP_CLIENT1 3 5 CP_CLIENT2 6 8 CP_CLIENT3 9 11 SDMA_CLIENT0 12 14 UVD_CLIENT0 15 17 SDMA1_CLIENT0 18 20 VCE_CLIENT0 21 23 mmSEM_MAILBOX 0 0xf9c 4 0 4294967295 SIDEPORT 0 7 HOSTPORT 8 15 SIDEPORT_EXTRA 16 23 HOSTPORT_EXTRA 24 31 mmSEM_MAILBOX_CONTROL 0 0xf9d 4 0 4294967295 SIDEPORT_ENABLE 0 7 HOSTPORT_ENABLE 8 15 SIDEPORT_ENABLE_EXTRA 16 23 HOSTPORT_ENABLE_EXTRA 24 31 mmSEM_CHICKEN_BITS 0 0xf9e 5 0 4294967295 VMID_PIPELINE_EN 0 0 ENTRY_PIPELINE_EN 1 1 CHECK_COUNTER_EN 2 2 ECC_BEHAVIOR 3 4 IDLE_COUNTER_INDEX 8 11 mmSEM_MAILBOX_CLIENTCONFIG_EXTRA 0 0xf9f 1 0 4294967295 VCE1_CLIENT0 0 4 mmSRBM_CNTL 0 0x390 3 0 4294967295 PWR_REQUEST_HALT 16 16 COMBINE_SYSTEM_MC 17 17 REPORT_LAST_RDERR 18 18 mmSRBM_GFX_CNTL 0 0x391 4 0 4294967295 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 mmSRBM_READ_CNTL 0 0x392 1 0 4294967295 READ_TIMEOUT 0 23 mmSRBM_STATUS2 0 0x393 21 0 4294967295 SDMA_RQ_PENDING 0 0 TST_RQ_PENDING 1 1 SDMA1_RQ_PENDING 2 2 VCE0_RQ_PENDING 3 3 VP8_BUSY 4 4 SDMA_BUSY 5 5 SDMA1_BUSY 6 6 VCE0_BUSY 7 7 XDMA_BUSY 8 8 CHUB_BUSY 9 9 SDMA2_BUSY 10 10 SDMA3_BUSY 11 11 SAMSCP_BUSY 12 12 ISP_BUSY 13 13 VCE1_BUSY 14 14 ODE_BUSY 15 15 SDMA2_RQ_PENDING 16 16 SDMA3_RQ_PENDING 17 17 SAMSCP_RQ_PENDING 18 18 ISP_RQ_PENDING 19 19 VCE1_RQ_PENDING 20 20 mmSRBM_STATUS 0 0x394 20 0 4294967295 UVD_RQ_PENDING 1 1 SAMMSP_RQ_PENDING 2 2 ACP_RQ_PENDING 3 3 SMU_RQ_PENDING 4 4 GRBM_RQ_PENDING 5 5 HI_RQ_PENDING 6 6 VMC_BUSY 8 8 MCB_BUSY 9 9 MCB_NON_DISPLAY_BUSY 10 10 MCC_BUSY 11 11 MCD_BUSY 12 12 VMC1_BUSY 13 13 SEM_BUSY 14 14 ACP_BUSY 16 16 IH_BUSY 17 17 UVD_BUSY 19 19 SAMMSP_BUSY 20 20 GCATCL2_BUSY 21 21 OSATCL2_BUSY 22 22 BIF_BUSY 29 29 mmSRBM_STATUS3 0 0x395 16 0 4294967295 MCC0_BUSY 0 0 MCC1_BUSY 1 1 MCC2_BUSY 2 2 MCC3_BUSY 3 3 MCC4_BUSY 4 4 MCC5_BUSY 5 5 MCC6_BUSY 6 6 MCC7_BUSY 7 7 MCD0_BUSY 8 8 MCD1_BUSY 9 9 MCD2_BUSY 10 10 MCD3_BUSY 11 11 MCD4_BUSY 12 12 MCD5_BUSY 13 13 MCD6_BUSY 14 14 MCD7_BUSY 15 15 mmSRBM_SOFT_RESET 0 0x398 31 0 4294967295 SOFT_RESET_ATCL2 0 0 SOFT_RESET_BIF 1 1 SOFT_RESET_SDMA3 2 2 SOFT_RESET_SDMA2 3 3 SOFT_RESET_GIONB 4 4 SOFT_RESET_DC 5 5 SOFT_RESET_SDMA1 6 6 SOFT_RESET_GRBM 8 8 SOFT_RESET_HDP 9 9 SOFT_RESET_IH 10 10 SOFT_RESET_MC 11 11 SOFT_RESET_CHUB 12 12 SOFT_RESET_ESRAM 13 13 SOFT_RESET_ROM 14 14 SOFT_RESET_SEM 15 15 SOFT_RESET_SMU 16 16 SOFT_RESET_VMC 17 17 SOFT_RESET_UVD 18 18 SOFT_RESET_VP8 19 19 SOFT_RESET_SDMA 20 20 SOFT_RESET_TST 21 21 SOFT_RESET_REGBB 22 22 SOFT_RESET_ODE 23 23 SOFT_RESET_VCE0 24 24 SOFT_RESET_XDMA 25 25 SOFT_RESET_ACP 26 26 SOFT_RESET_SAMMSP 27 27 SOFT_RESET_SAMSCP 28 28 SOFT_RESET_GRN 29 29 SOFT_RESET_ISP 30 30 SOFT_RESET_VCE1 31 31 mmSRBM_DEBUG_CNTL 0 0x399 1 0 4294967295 SRBM_DEBUG_INDEX 0 5 mmSRBM_DEBUG_DATA 0 0x39a 1 0 4294967295 DATA 0 31 mmSRBM_CHIP_REVISION 0 0x39b 1 0 4294967295 CHIP_REVISION 0 7 mmSRBM_CREDIT_RECOVER_CNTL 0 0x39c 2 0 4294967295 CREDIT_RECOVER_TIME 0 11 CREDIT_RECOVER_ENABLE 31 31 mmSRBM_CREDIT_RECOVER 0 0x39d 32 0 4294967295 CREDIT_RECOVER_BIF 0 0 CREDIT_RECOVER_SMU 1 1 CREDIT_RECOVER_DC 2 2 CREDIT_RECOVER_GIONB 3 3 CREDIT_RECOVER_ACP 4 4 CREDIT_RECOVER_XDMA 5 5 CREDIT_RECOVER_ODE 6 6 CREDIT_RECOVER_REGBB 7 7 CREDIT_RECOVER_VP8 8 8 CREDIT_RECOVER_GRBM 9 9 CREDIT_RECOVER_UVD 10 10 CREDIT_RECOVER_VCE0 11 11 CREDIT_RECOVER_VCE1 12 12 CREDIT_RECOVER_ISP 13 13 CREDIT_RECOVER_SAM 14 14 CREDIT_RECOVER_MCB 15 15 CREDIT_RECOVER_MCC0 16 16 CREDIT_RECOVER_MCC1 17 17 CREDIT_RECOVER_MCC2 18 18 CREDIT_RECOVER_MCC3 19 19 CREDIT_RECOVER_MCC4 20 20 CREDIT_RECOVER_MCC5 21 21 CREDIT_RECOVER_MCC6 22 22 CREDIT_RECOVER_MCC7 23 23 CREDIT_RECOVER_MCD0 24 24 CREDIT_RECOVER_MCD1 25 25 CREDIT_RECOVER_MCD2 26 26 CREDIT_RECOVER_MCD3 27 27 CREDIT_RECOVER_MCD4 28 28 CREDIT_RECOVER_MCD5 29 29 CREDIT_RECOVER_MCD6 30 30 CREDIT_RECOVER_MCD7 31 31 mmSRBM_CREDIT_RESET 0 0x39e 32 0 4294967295 CREDIT_RESET_BIF 0 0 CREDIT_RESET_SMU 1 1 CREDIT_RESET_DC 2 2 CREDIT_RESET_GIONB 3 3 CREDIT_RESET_ACP 4 4 CREDIT_RESET_XDMA 5 5 CREDIT_RESET_ODE 6 6 CREDIT_RESET_REGBB 7 7 CREDIT_RESET_VP8 8 8 CREDIT_RESET_GRBM 9 9 CREDIT_RESET_UVD 10 10 CREDIT_RESET_VCE0 11 11 CREDIT_RESET_VCE1 12 12 CREDIT_RESET_ISP 13 13 CREDIT_RESET_SAM 14 14 CREDIT_RESET_MCB 15 15 CREDIT_RESET_MCC0 16 16 CREDIT_RESET_MCC1 17 17 CREDIT_RESET_MCC2 18 18 CREDIT_RESET_MCC3 19 19 CREDIT_RESET_MCC4 20 20 CREDIT_RESET_MCC5 21 21 CREDIT_RESET_MCC6 22 22 CREDIT_RESET_MCC7 23 23 CREDIT_RESET_MCD0 24 24 CREDIT_RESET_MCD1 25 25 CREDIT_RESET_MCD2 26 26 CREDIT_RESET_MCD3 27 27 CREDIT_RESET_MCD4 28 28 CREDIT_RESET_MCD5 29 29 CREDIT_RESET_MCD6 30 30 CREDIT_RESET_MCD7 31 31 mmCC_SYS_RB_REDUNDANCY 0 0x39f 4 0 4294967295 FAILED_RB0 8 11 EN_REDUNDANCY0 12 12 FAILED_RB1 16 19 EN_REDUNDANCY1 20 20 mmCC_SYS_RB_BACKEND_DISABLE 0 0x3a0 1 0 4294967295 BACKEND_DISABLE 16 23 mmGC_USER_SYS_RB_BACKEND_DISABLE 0 0x3a1 1 0 4294967295 BACKEND_DISABLE 16 23 mmSRBM_MC_CLKEN_CNTL 0 0x3b3 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_SYS_CLKEN_CNTL 0 0x3b4 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_VCE_CLKEN_CNTL 0 0x3b5 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_UVD_CLKEN_CNTL 0 0x3b6 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_SDMA_CLKEN_CNTL 0 0x3b7 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_SAM_CLKEN_CNTL 0 0x3b8 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_ISP_CLKEN_CNTL 0 0x3b9 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_VP8_CLKEN_CNTL 0 0x3ba 2 0 4294967295 PREFIX_DELAY_CNT 0 3 POST_DELAY_CNT 8 12 mmSRBM_DEBUG 0 0x3a4 11 0 4294967295 IGNORE_RDY 0 0 DISABLE_READ_TIMEOUT 1 1 SNAPSHOT_FREE_CNTRS 2 2 SYS_CLOCK_DOMAIN_OVERRIDE 4 4 VCE_CLOCK_DOMAIN_OVERRIDE 5 5 UVD_CLOCK_DOMAIN_OVERRIDE 6 6 SDMA_CLOCK_DOMAIN_OVERRIDE 7 7 MC_CLOCK_DOMAIN_OVERRIDE 8 8 SAM_CLOCK_DOMAIN_OVERRIDE 9 9 ISP_CLOCK_DOMAIN_OVERRIDE 10 10 VP8_CLOCK_DOMAIN_OVERRIDE 11 11 mmSRBM_DEBUG_SNAPSHOT 0 0x3a5 32 0 4294967295 MCB_RDY 0 0 GIONB_RDY 1 1 SMU_RDY 2 2 SAMMSP_RDY 3 3 ACP_RDY 4 4 GRBM_RDY 5 5 DC_RDY 6 6 BIF_RDY 7 7 XDMA_RDY 8 8 UVD_RDY 9 9 VP8_RDY 10 10 REGBB_RDY 11 11 ODE_RDY 12 12 MCD7_RDY 13 13 MCD6_RDY 14 14 MCD5_RDY 15 15 MCD4_RDY 16 16 MCD3_RDY 17 17 MCD2_RDY 18 18 MCD1_RDY 19 19 MCD0_RDY 20 20 MCC7_RDY 21 21 MCC6_RDY 22 22 MCC5_RDY 23 23 MCC4_RDY 24 24 MCC3_RDY 25 25 MCC2_RDY 26 26 MCC1_RDY 27 27 MCC0_RDY 28 28 VCE0_RDY 29 29 SAMSCP_RDY 30 30 ISP_RDY 31 31 mmSRBM_DEBUG_SNAPSHOT2 0 0x3ad 1 0 4294967295 VCE1_RDY 0 0 mmSRBM_READ_ERROR 0 0x3a6 14 0 4294967295 READ_ADDRESS 2 17 READ_REQUESTER_SDMA3 18 18 READ_REQUESTER_SDMA2 19 19 READ_REQUESTER_VCE0 20 20 READ_REQUESTER_SDMA1 21 21 READ_REQUESTER_TST 22 22 READ_REQUESTER_SAMMSP 23 23 READ_REQUESTER_HI 24 24 READ_REQUESTER_GRBM 25 25 READ_REQUESTER_SMU 26 26 READ_REQUESTER_SAMSCP 27 27 READ_REQUESTER_SDMA 28 28 READ_REQUESTER_UVD 29 29 READ_ERROR 31 31 mmSRBM_READ_ERROR2 0 0x3ae 5 0 4294967295 READ_REQUESTER_ACP 0 0 READ_REQUESTER_ISP 1 1 READ_REQUESTER_VCE1 2 2 READ_VF 23 23 READ_VFID 24 27 mmSRBM_INT_CNTL 0 0x3a8 2 0 4294967295 RDERR_INT_MASK 0 0 RAERR_INT_MASK 1 1 mmSRBM_INT_STATUS 0 0x3a9 2 0 4294967295 RDERR_INT_STAT 0 0 RAERR_INT_STAT 1 1 mmSRBM_INT_ACK 0 0x3aa 2 0 4294967295 RDERR_INT_ACK 0 0 RAERR_INT_ACK 1 1 mmSRBM_FIREWALL_ERROR_SRC 0 0x3ab 25 0 4294967295 ACCESS_REQUESTER_BIF 0 0 ACCESS_REQUESTER_ACP 1 1 ACCESS_REQUESTER_SAMSCP 2 2 ACCESS_REQUESTER_SAMMSP 3 3 ACCESS_REQUESTER_TST 5 5 ACCESS_REQUESTER_SDMA3 6 6 ACCESS_REQUESTER_SDMA2 7 7 ACCESS_REQUESTER_SDMA1 8 8 ACCESS_REQUESTER_SDMA0 9 9 ACCESS_REQUESTER_UVD 10 10 ACCESS_REQUESTER_VCE0 11 11 ACCESS_REQUESTER_GRBM 12 12 ACCESS_REQUESTER_SMU 13 13 ACCESS_REQUESTER_PEER 14 14 ACCESS_REQUESTER_CPU 15 15 ACCESS_REQUESTER_ISP 16 16 ACCESS_REQUESTER_VCE1 17 17 ACCESS_REQUESTER_RLCHYP 18 18 ACCESS_REQUESTER_SMUHYP 19 19 ACCESS_REQUESTER_BIFHYP 20 20 RAERR_FIREWALL_VIOLATION 24 24 RAERR_HAR_REGIONSIZE_OVERFLOW 25 25 RAERR_BIF_ADDR_OVERFLOW 26 26 RAERR_P2SRP_REGIONSIZE_OVERFLOW 27 27 RAERR_P2SRP_FIREWALL_VIOLATION 28 28 mmSRBM_FIREWALL_ERROR_ADDR 0 0x3ac 4 0 4294967295 ACCESS_ADDRESS 2 17 ACCESS_VF 19 19 ACCESS_VFID 20 23 FIREWALL_VIOLATION 31 31 mmSRBM_DSM_TRIG_CNTL0 0 0x3af 2 0 4294967295 DSM_TRIG_ADDR 0 15 DSM_TRIG_OP 16 16 mmSRBM_DSM_TRIG_CNTL1 0 0x3b0 1 0 4294967295 DSM_TRIG_WD 0 31 mmSRBM_DSM_TRIG_MASK0 0 0x3b1 2 0 4294967295 DSM_TRIG_ADDR_MASK 0 15 DSM_TRIG_OP_MASK 16 16 mmSRBM_DSM_TRIG_MASK1 0 0x3b2 1 0 4294967295 DSM_TRIG_WD_MASK 0 31 mmSRBM_PERFMON_CNTL 0 0x7c00 3 0 4294967295 PERFMON_STATE 0 3 PERFMON_ENABLE_MODE 8 9 PERFMON_SAMPLE_ENABLE 10 10 mmSRBM_PERFCOUNTER0_SELECT 0 0x7c01 1 0 4294967295 PERF_SEL 0 5 mmSRBM_PERFCOUNTER1_SELECT 0 0x7c02 1 0 4294967295 PERF_SEL 0 5 mmSRBM_PERFCOUNTER0_LO 0 0x7c03 1 0 4294967295 PERF_COUNT0_LO 0 31 mmSRBM_PERFCOUNTER0_HI 0 0x7c04 1 0 4294967295 PERF_COUNT0_HI 0 31 mmSRBM_PERFCOUNTER1_LO 0 0x7c05 1 0 4294967295 PERF_COUNT1_LO 0 31 mmSRBM_PERFCOUNTER1_HI 0 0x7c06 1 0 4294967295 PERF_COUNT1_HI 0 31 mmSRBM_CAM_INDEX 0 0xfe34 1 0 4294967295 CAM_INDEX 0 1 mmSRBM_CAM_DATA 0 0xfe35 2 0 4294967295 CAM_ADDR 0 15 CAM_REMAPADDR 16 31 mmSRBM_MC_DOMAIN_ADDR0 0 0xfa00 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR1 0 0xfa01 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR2 0 0xfa02 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR3 0 0xfa03 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR4 0 0xfa04 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR5 0 0xfa05 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_MC_DOMAIN_ADDR6 0 0xfa06 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR0 0 0xfa08 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR1 0 0xfa09 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR2 0 0xfa0a 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR3 0 0xfa0b 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR4 0 0xfa0c 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR5 0 0xfa0d 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SYS_DOMAIN_ADDR6 0 0xfa0e 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SDMA_DOMAIN_ADDR0 0 0xfa10 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SDMA_DOMAIN_ADDR1 0 0xfa11 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SDMA_DOMAIN_ADDR2 0 0xfa12 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SDMA_DOMAIN_ADDR3 0 0xfa13 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_UVD_DOMAIN_ADDR0 0 0xfa14 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_UVD_DOMAIN_ADDR1 0 0xfa15 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_UVD_DOMAIN_ADDR2 0 0xfa16 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_VCE_DOMAIN_ADDR0 0 0xfa18 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_VCE_DOMAIN_ADDR1 0 0xfa19 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_VCE_DOMAIN_ADDR2 0 0xfa1a 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SAM_DOMAIN_ADDR0 0 0xfa1c 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SAM_DOMAIN_ADDR1 0 0xfa1d 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_SAM_DOMAIN_ADDR2 0 0xfa1e 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_ISP_DOMAIN_ADDR0 0 0xfa20 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_ISP_DOMAIN_ADDR1 0 0xfa21 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_ISP_DOMAIN_ADDR2 0 0xfa22 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSRBM_VP8_DOMAIN_ADDR0 0 0xfa24 2 0 4294967295 ADDR_LO 0 15 ADDR_HI 16 31 mmSYS_GRBM_GFX_INDEX_SELECT 0 0xfa2c 1 0 4294967295 SYS_GRBM_GFX_INDEX_SEL 0 3 mmSYS_GRBM_GFX_INDEX_DATA 0 0xfa2d 6 0 4294967295 INSTANCE_INDEX 0 7 SH_INDEX 8 15 SE_INDEX 16 23 SH_BROADCAST_WRITES 29 29 INSTANCE_BROADCAST_WRITES 30 30 SE_BROADCAST_WRITES 31 31 mmSRBM_GFX_CNTL_SELECT 0 0xfa2e 1 0 4294967295 SRBM_GFX_CNTL_SEL 0 3 mmSRBM_GFX_CNTL_DATA 0 0xfa2f 4 0 4294967295 PIPEID 0 1 MEID 2 3 VMID 4 7 QUEUEID 8 10 mmSRBM_VF_ENABLE 0 0xfa30 1 0 4294967295 VF_ENABLE 0 0 mmSRBM_VIRT_CNTL 0 0xfa31 1 0 4294967295 VF_WRITE_ENABLE 0 0 mmSRBM_VIRT_RESET_REQ 0 0xfa32 2 0 4294967295 VF 0 15 PF 31 31 mmCC_DRM_ID_STRAPS 0 0x1559 4 0 4294967295 DEVICE_ID 4 19 MAJOR_REV_ID 20 23 MINOR_REV_ID 24 27 ATI_REV_ID 28 31 mmCGTT_DRM_CLK_CTRL0 0 0x1579 0 0 4294967295 ixDH_TEST 2 0x0 1 0 4294967295 DH_TEST 0 0 ixKHFS0 2 0x4 1 0 4294967295 RESERVED 0 31 ixKHFS1 2 0x8 1 0 4294967295 RESERVED 0 31 ixKHFS2 2 0xc 1 0 4294967295 RESERVED 0 31 ixKHFS3 2 0x10 1 0 4294967295 RESERVED 0 31 ixKSESSION0 2 0x14 1 0 4294967295 RESERVED 0 31 ixKSESSION1 2 0x18 1 0 4294967295 RESERVED 0 31 ixKSESSION2 2 0x1c 1 0 4294967295 RESERVED 0 31 ixKSESSION3 2 0x20 1 0 4294967295 RESERVED 0 31 ixKSIG0 2 0x24 1 0 4294967295 RESERVED 0 31 ixKSIG1 2 0x28 1 0 4294967295 RESERVED 0 31 ixKSIG2 2 0x2c 1 0 4294967295 RESERVED 0 31 ixKSIG3 2 0x30 1 0 4294967295 RESERVED 0 31 ixEXP0 2 0x34 1 0 4294967295 RESERVED 0 31 ixEXP1 2 0x38 1 0 4294967295 RESERVED 0 31 ixEXP2 2 0x3c 1 0 4294967295 RESERVED 0 31 ixEXP3 2 0x40 1 0 4294967295 RESERVED 0 31 ixEXP4 2 0x44 1 0 4294967295 RESERVED 0 31 ixEXP5 2 0x48 1 0 4294967295 RESERVED 0 31 ixEXP6 2 0x4c 1 0 4294967295 RESERVED 0 31 ixEXP7 2 0x50 1 0 4294967295 RESERVED 0 31 ixLX0 2 0x54 1 0 4294967295 RESERVED 0 31 ixLX1 2 0x58 1 0 4294967295 RESERVED 0 31 ixLX2 2 0x5c 1 0 4294967295 RESERVED 0 31 ixLX3 2 0x60 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K0 2 0x1b4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K1 2 0x1b8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K2 2 0x1bc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_K3 2 0x1c0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK0 2 0x1c4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK1 2 0x1c8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK2 2 0x1cc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CK3 2 0x1d0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD0 2 0x1d4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD1 2 0x1d8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD2 2 0x1dc 1 0 4294967295 RESERVED 0 31 ixCLIENT2_CD3 2 0x1e0 1 0 4294967295 RESERVED 0 31 ixCLIENT2_BM 2 0x1e4 1 0 4294967295 RESERVED 0 31 ixCLIENT2_OFFSET 2 0x1e8 1 0 4294967295 RESERVED 0 31 ixCLIENT2_STATUS 2 0x1ec 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K0 2 0x1f0 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K1 2 0x1f4 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K2 2 0x1f8 1 0 4294967295 RESERVED 0 31 ixCLIENT0_K3 2 0x1fc 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK0 2 0x200 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK1 2 0x204 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK2 2 0x208 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CK3 2 0x20c 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD0 2 0x210 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD1 2 0x214 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD2 2 0x218 1 0 4294967295 RESERVED 0 31 ixCLIENT0_CD3 2 0x21c 1 0 4294967295 RESERVED 0 31 ixCLIENT0_BM 2 0x220 1 0 4294967295 RESERVED 0 31 ixCLIENT0_OFFSET 2 0x224 1 0 4294967295 RESERVED 0 31 ixCLIENT0_STATUS 2 0x228 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K0 2 0x22c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K1 2 0x230 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K2 2 0x234 1 0 4294967295 RESERVED 0 31 ixCLIENT1_K3 2 0x238 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK0 2 0x23c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK1 2 0x240 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK2 2 0x244 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CK3 2 0x248 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD0 2 0x24c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD1 2 0x250 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD2 2 0x254 1 0 4294967295 RESERVED 0 31 ixCLIENT1_CD3 2 0x258 1 0 4294967295 RESERVED 0 31 ixCLIENT1_BM 2 0x25c 1 0 4294967295 RESERVED 0 31 ixCLIENT1_OFFSET 2 0x260 1 0 4294967295 RESERVED 0 31 ixCLIENT1_PORT_STATUS 2 0x264 1 0 4294967295 RESERVED 0 31 ixKEFUSE0 2 0x268 1 0 4294967295 RESERVED 0 31 ixKEFUSE1 2 0x26c 1 0 4294967295 RESERVED 0 31 ixKEFUSE2 2 0x270 1 0 4294967295 RESERVED 0 31 ixKEFUSE3 2 0x274 1 0 4294967295 RESERVED 0 31 ixHFS_SEED0 2 0x278 1 0 4294967295 RESERVED 0 31 ixHFS_SEED1 2 0x27c 1 0 4294967295 RESERVED 0 31 ixHFS_SEED2 2 0x280 1 0 4294967295 RESERVED 0 31 ixHFS_SEED3 2 0x284 1 0 4294967295 RESERVED 0 31 ixRINGOSC_MASK 2 0x288 1 0 4294967295 MASK 0 15 ixCLIENT0_OFFSET_HI 2 0x290 1 0 4294967295 RESERVED 0 31 ixCLIENT1_OFFSET_HI 2 0x294 1 0 4294967295 RESERVED 0 31 ixCLIENT2_OFFSET_HI 2 0x298 1 0 4294967295 RESERVED 0 31 ixSPU_PORT_STATUS 2 0x29c 1 0 4294967295 RESERVED 0 31 ixCLIENT3_OFFSET_HI 2 0x2a0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K0 2 0x2a4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K1 2 0x2a8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K2 2 0x2ac 1 0 4294967295 RESERVED 0 31 ixCLIENT3_K3 2 0x2b0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK0 2 0x2b4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK1 2 0x2b8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK2 2 0x2bc 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CK3 2 0x2c0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD0 2 0x2c4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD1 2 0x2c8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD2 2 0x2cc 1 0 4294967295 RESERVED 0 31 ixCLIENT3_CD3 2 0x2d0 1 0 4294967295 RESERVED 0 31 ixCLIENT3_BM 2 0x2d4 1 0 4294967295 RESERVED 0 31 ixCLIENT3_OFFSET 2 0x2d8 1 0 4294967295 RESERVED 0 31 ixCLIENT3_STATUS 2 0x2dc 1 0 4294967295 RESERVED 0 31 ixCLIENT4_OFFSET_HI 2 0x2e0 1 0 4294967295 RESERVED 0 31 ixCLIENT4_K0 2 0x2e4 1 0 4294967295 RESERVED 0 31 ixCLIENT4_K1 2 0x2e8 1 0 4294967295 RESERVED 0 31 ixCLIENT4_K2 2 0x2ec 1 0 4294967295 RESERVED 0 31 ixCLIENT4_K3 2 0x2f0 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CK0 2 0x2f4 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CK1 2 0x2f8 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CK2 2 0x2fc 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CK3 2 0x300 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CD0 2 0x304 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CD1 2 0x308 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CD2 2 0x30c 1 0 4294967295 RESERVED 0 31 ixCLIENT4_CD3 2 0x310 1 0 4294967295 RESERVED 0 31 ixCLIENT4_BM 2 0x314 1 0 4294967295 RESERVED 0 31 ixCLIENT4_OFFSET 2 0x318 1 0 4294967295 RESERVED 0 31 ixCLIENT4_STATUS 2 0x31c 1 0 4294967295 RESERVED 0 31 mmDC_TEST_DEBUG_INDEX 0 0x157c 2 0 4294967295 DC_TEST_DEBUG_INDEX 0 7 DC_TEST_DEBUG_WRITE_EN 8 8 mmDC_TEST_DEBUG_DATA 0 0x157d 1 0 4294967295 DC_TEST_DEBUG_DATA 0 31 mmSDMA0_UCODE_ADDR 0 0x3400 1 0 4294967295 VALUE 0 12 mmSDMA0_UCODE_DATA 0 0x3401 1 0 4294967295 VALUE 0 31 mmSDMA0_POWER_CNTL 0 0x3402 5 0 4294967295 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 mmSDMA0_CLK_CTRL 0 0x3403 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmSDMA0_CNTL 0 0x3404 13 0 4294967295 TRAP_ENABLE 0 0 ATC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MC_WRREQ_CREDIT 11 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 MC_RDREQ_CREDIT 22 27 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA0_CHICKEN_BITS 0 0x3405 9 0 4294967295 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 COPY_OVERLAP_ENABLE 16 16 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA0_TILING_CONFIG 0 0x3406 1 0 4294967295 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA0_HASH 0 0x3407 4 0 4294967295 CHANNEL_BITS 0 2 BANK_BITS 4 6 CHANNEL_XOR_COUNT 8 10 BANK_XOR_COUNT 12 14 mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0 0x3409 1 0 4294967295 TIMER 0 31 mmSDMA0_RB_RPTR_FETCH 0 0x340a 1 0 4294967295 OFFSET 2 31 mmSDMA0_IB_OFFSET_FETCH 0 0x340b 1 0 4294967295 OFFSET 2 21 mmSDMA0_PROGRAM 0 0x340c 1 0 4294967295 STREAM 0 31 mmSDMA0_STATUS_REG 0 0x340d 29 0 4294967295 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA0_STATUS1_REG 0 0x340e 13 0 4294967295 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA0_RD_BURST_CNTL 0 0x340f 1 0 4294967295 RD_BURST 0 1 mmSDMA0_PERFMON_CNTL 0 0x9000 6 0 4294967295 PERF_ENABLE0 0 0 PERF_CLEAR0 1 1 PERF_SEL0 2 7 PERF_ENABLE1 8 8 PERF_CLEAR1 9 9 PERF_SEL1 10 15 mmSDMA0_PERFCOUNTER0_RESULT 0 0x9001 1 0 4294967295 PERF_COUNT 0 31 mmSDMA0_PERFCOUNTER1_RESULT 0 0x9002 1 0 4294967295 PERF_COUNT 0 31 mmSDMA0_F32_CNTL 0 0x3412 3 0 4294967295 HALT 0 0 STEP 1 1 DBG_SELECT_BITS 2 7 mmSDMA0_FREEZE 0 0x3413 3 0 4294967295 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA0_PHASE0_QUANTUM 0 0x3414 3 0 4294967295 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA0_PHASE1_QUANTUM 0 0x3415 3 0 4294967295 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA_POWER_GATING 0 0x3416 8 0 4294967295 PG_CNTL_ENABLE 0 0 AUTOMATIC_STATUS_ENABLE 1 1 PG_STATE_VALID 2 2 PG_CNTL_STATUS 4 5 SDMA0_ON_CONDITION 6 6 SDMA1_ON_CONDITION 7 7 POWER_OFF_DELAY 8 19 POWER_ON_DELAY 20 31 mmSDMA_PGFSM_CONFIG 0 0x3417 9 0 4294967295 FSM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE 12 12 READ 13 13 SRBM_OVERRIDE 27 27 REG_ADDR 28 31 mmSDMA_PGFSM_WRITE 0 0x3418 1 0 4294967295 VALUE 0 31 mmSDMA_PGFSM_READ 0 0x3419 1 0 4294967295 VALUE 0 23 mmSDMA0_EDC_CONFIG 0 0x341a 2 0 4294967295 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA0_VM_CNTL 0 0x3420 1 0 4294967295 CMD 0 3 mmSDMA0_VM_CTX_LO 0 0x3421 1 0 4294967295 ADDR 2 31 mmSDMA0_VM_CTX_HI 0 0x3422 1 0 4294967295 ADDR 0 31 mmSDMA0_STATUS2_REG 0 0x3423 4 0 4294967295 ID 0 1 F32_INSTR_PTR 2 11 CURRENT_FCN_IDLE 14 15 CMD_OP 16 31 mmSDMA0_ACTIVE_FCN_ID 0 0x3424 2 0 4294967295 VFID 0 3 VF 31 31 mmSDMA0_VM_CTX_CNTL 0 0x3425 2 0 4294967295 PRIV 0 0 VMID 4 7 mmSDMA0_VIRT_RESET_REQ 0 0x3426 2 0 4294967295 VF 0 15 PF 31 31 mmSDMA0_VF_ENABLE 0 0x3427 1 0 4294967295 VF_ENABLE 0 0 mmSDMA0_BA_THRESHOLD 0 0x341b 2 0 4294967295 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA0_ID 0 0x341c 1 0 4294967295 DEVICE_ID 0 7 mmSDMA0_VERSION 0 0x341d 1 0 4294967295 VALUE 0 15 mmSDMA0_ATOMIC_CNTL 0 0x3428 2 0 4294967295 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA0_ATOMIC_PREOP_LO 0 0x3429 1 0 4294967295 DATA 0 31 mmSDMA0_ATOMIC_PREOP_HI 0 0x342a 1 0 4294967295 DATA 0 31 mmSDMA0_POWER_CNTL_IDLE 0 0x342c 2 0 4294967295 DELAY1 0 15 DELAY2 16 31 mmSDMA0_PERF_REG_TYPE0 0 0x3477 4 0 4294967295 SDMA0_PERFMON_CNTL 0 0 SDMA0_PERFCOUNTER0_RESULT 1 1 SDMA0_PERFCOUNTER1_RESULT 2 2 RESERVED_31_3 3 31 mmSDMA0_CONTEXT_REG_TYPE0 0 0x3478 20 0 4294967295 SDMA0_GFX_RB_CNTL 0 0 SDMA0_GFX_RB_BASE 1 1 SDMA0_GFX_RB_BASE_HI 2 2 SDMA0_GFX_RB_RPTR 3 3 SDMA0_GFX_RB_WPTR 4 4 SDMA0_GFX_RB_WPTR_POLL_CNTL 5 5 SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 6 6 SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 7 7 SDMA0_GFX_RB_RPTR_ADDR_HI 8 8 SDMA0_GFX_RB_RPTR_ADDR_LO 9 9 SDMA0_GFX_IB_CNTL 10 10 SDMA0_GFX_IB_RPTR 11 11 SDMA0_GFX_IB_OFFSET 12 12 SDMA0_GFX_IB_BASE_LO 13 13 SDMA0_GFX_IB_BASE_HI 14 14 SDMA0_GFX_IB_SIZE 15 15 SDMA0_GFX_SKIP_CNTL 16 16 SDMA0_GFX_CONTEXT_STATUS 17 17 SDMA0_GFX_DOORBELL 18 18 SDMA0_GFX_CONTEXT_CNTL 19 19 mmSDMA0_CONTEXT_REG_TYPE1 0 0x3479 12 0 4294967295 SDMA0_GFX_VIRTUAL_ADDR 7 7 SDMA0_GFX_APE1_CNTL 8 8 SDMA0_GFX_DOORBELL_LOG 9 9 SDMA0_GFX_WATERMARK 10 10 VOID_REG1 11 11 SDMA0_GFX_CSA_ADDR_LO 12 12 SDMA0_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA0_GFX_IB_SUB_REMAIN 15 15 SDMA0_GFX_PREEMPT 16 16 SDMA0_GFX_DUMMY_REG 17 17 RESERVED 18 31 mmSDMA0_CONTEXT_REG_TYPE2 0 0x347a 8 0 4294967295 SDMA0_GFX_MIDCMD_DATA0 0 0 SDMA0_GFX_MIDCMD_DATA1 1 1 SDMA0_GFX_MIDCMD_DATA2 2 2 SDMA0_GFX_MIDCMD_DATA3 3 3 SDMA0_GFX_MIDCMD_DATA4 4 4 SDMA0_GFX_MIDCMD_DATA5 5 5 SDMA0_GFX_MIDCMD_CNTL 6 6 RESERVED 7 31 mmSDMA0_PUB_REG_TYPE0 0 0x347c 30 0 4294967295 SDMA0_UCODE_ADDR 0 0 SDMA0_UCODE_DATA 1 1 SDMA0_POWER_CNTL 2 2 SDMA0_CLK_CTRL 3 3 SDMA0_CNTL 4 4 SDMA0_CHICKEN_BITS 5 5 SDMA0_TILING_CONFIG 6 6 SDMA0_HASH 7 7 SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 9 9 SDMA0_RB_RPTR_FETCH 10 10 SDMA0_IB_OFFSET_FETCH 11 11 SDMA0_PROGRAM 12 12 SDMA0_STATUS_REG 13 13 SDMA0_STATUS1_REG 14 14 SDMA0_RD_BURST_CNTL 15 15 RESERVED_16 16 16 RESERVED_17 17 17 SDMA0_F32_CNTL 18 18 SDMA0_FREEZE 19 19 SDMA0_PHASE0_QUANTUM 20 20 SDMA0_PHASE1_QUANTUM 21 21 SDMA_POWER_GATING 22 22 SDMA_PGFSM_CONFIG 23 23 SDMA_PGFSM_WRITE 24 24 SDMA_PGFSM_READ 25 25 SDMA0_EDC_CONFIG 26 26 SDMA0_BA_THRESHOLD 27 27 SDMA0_DEVICE_ID 28 28 SDMA0_VERSION 29 29 RESERVED 30 31 mmSDMA0_PUB_REG_TYPE1 0 0x347d 12 0 4294967295 SDMA0_VM_CNTL 0 0 SDMA0_VM_CTX_LO 1 1 SDMA0_VM_CTX_HI 2 2 SDMA0_STATUS2_REG 3 3 SDMA0_ACTIVE_FCN_ID 4 4 SDMA0_VM_CTX_CNTL 5 5 SDMA0_VIRT_RESET_REQ 6 6 SDMA0_VF_ENABLE 7 7 SDMA0_ATOMIC_CNTL 8 8 SDMA0_ATOMIC_PREOP_LO 9 9 SDMA0_ATOMIC_PREOP_HI 10 10 RESERVED 11 31 mmSDMA0_GFX_RB_CNTL 0 0x3480 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA0_GFX_RB_BASE 0 0x3481 1 0 4294967295 ADDR 0 31 mmSDMA0_GFX_RB_BASE_HI 0 0x3482 1 0 4294967295 ADDR 0 23 mmSDMA0_GFX_RB_RPTR 0 0x3483 1 0 4294967295 OFFSET 2 31 mmSDMA0_GFX_RB_WPTR 0 0x3484 1 0 4294967295 OFFSET 2 31 mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0 0x3485 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0 0x3486 1 0 4294967295 ADDR 0 31 mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0 0x3487 1 0 4294967295 ADDR 2 31 mmSDMA0_GFX_RB_RPTR_ADDR_HI 0 0x3488 1 0 4294967295 ADDR 0 31 mmSDMA0_GFX_RB_RPTR_ADDR_LO 0 0x3489 1 0 4294967295 ADDR 2 31 mmSDMA0_GFX_IB_CNTL 0 0x348a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_GFX_IB_RPTR 0 0x348b 1 0 4294967295 OFFSET 2 21 mmSDMA0_GFX_IB_OFFSET 0 0x348c 1 0 4294967295 OFFSET 2 21 mmSDMA0_GFX_IB_BASE_LO 0 0x348d 1 0 4294967295 ADDR 5 31 mmSDMA0_GFX_IB_BASE_HI 0 0x348e 1 0 4294967295 ADDR 0 31 mmSDMA0_GFX_IB_SIZE 0 0x348f 1 0 4294967295 SIZE 0 19 mmSDMA0_GFX_SKIP_CNTL 0 0x3490 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA0_GFX_CONTEXT_STATUS 0 0x3491 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_GFX_DOORBELL 0 0x3492 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_GFX_CONTEXT_CNTL 0 0x3493 2 0 4294967295 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA0_GFX_VIRTUAL_ADDR 0 0x34a7 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA0_GFX_APE1_CNTL 0 0x34a8 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA0_GFX_DOORBELL_LOG 0 0x34a9 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA0_GFX_WATERMARK 0 0x34aa 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA0_GFX_CSA_ADDR_LO 0 0x34ac 1 0 4294967295 ADDR 2 31 mmSDMA0_GFX_CSA_ADDR_HI 0 0x34ad 1 0 4294967295 ADDR 0 31 mmSDMA0_GFX_IB_SUB_REMAIN 0 0x34af 1 0 4294967295 SIZE 0 13 mmSDMA0_GFX_PREEMPT 0 0x34b0 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA0_GFX_DUMMY_REG 0 0x34b1 1 0 4294967295 DUMMY 0 31 mmSDMA0_GFX_MIDCMD_DATA0 0 0x34c1 1 0 4294967295 DATA0 0 31 mmSDMA0_GFX_MIDCMD_DATA1 0 0x34c2 1 0 4294967295 DATA1 0 31 mmSDMA0_GFX_MIDCMD_DATA2 0 0x34c3 1 0 4294967295 DATA2 0 31 mmSDMA0_GFX_MIDCMD_DATA3 0 0x34c4 1 0 4294967295 DATA3 0 31 mmSDMA0_GFX_MIDCMD_DATA4 0 0x34c5 1 0 4294967295 DATA4 0 31 mmSDMA0_GFX_MIDCMD_DATA5 0 0x34c6 1 0 4294967295 DATA5 0 31 mmSDMA0_GFX_MIDCMD_CNTL 0 0x34c7 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC0_RB_CNTL 0 0x3500 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA0_RLC0_RB_BASE 0 0x3501 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC0_RB_BASE_HI 0 0x3502 1 0 4294967295 ADDR 0 23 mmSDMA0_RLC0_RB_RPTR 0 0x3503 1 0 4294967295 OFFSET 2 31 mmSDMA0_RLC0_RB_WPTR 0 0x3504 1 0 4294967295 OFFSET 2 31 mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0 0x3505 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x3506 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x3507 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0 0x3508 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0 0x3509 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC0_IB_CNTL 0 0x350a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC0_IB_RPTR 0 0x350b 1 0 4294967295 OFFSET 2 21 mmSDMA0_RLC0_IB_OFFSET 0 0x350c 1 0 4294967295 OFFSET 2 21 mmSDMA0_RLC0_IB_BASE_LO 0 0x350d 1 0 4294967295 ADDR 5 31 mmSDMA0_RLC0_IB_BASE_HI 0 0x350e 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC0_IB_SIZE 0 0x350f 1 0 4294967295 SIZE 0 19 mmSDMA0_RLC0_SKIP_CNTL 0 0x3510 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA0_RLC0_CONTEXT_STATUS 0 0x3511 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC0_DOORBELL 0 0x3512 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC0_VIRTUAL_ADDR 0 0x3527 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA0_RLC0_APE1_CNTL 0 0x3528 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA0_RLC0_DOORBELL_LOG 0 0x3529 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC0_WATERMARK 0 0x352a 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA0_RLC0_CSA_ADDR_LO 0 0x352c 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC0_CSA_ADDR_HI 0 0x352d 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC0_IB_SUB_REMAIN 0 0x352f 1 0 4294967295 SIZE 0 13 mmSDMA0_RLC0_PREEMPT 0 0x3530 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA0_RLC0_DUMMY_REG 0 0x3531 1 0 4294967295 DUMMY 0 31 mmSDMA0_RLC0_MIDCMD_DATA0 0 0x3541 1 0 4294967295 DATA0 0 31 mmSDMA0_RLC0_MIDCMD_DATA1 0 0x3542 1 0 4294967295 DATA1 0 31 mmSDMA0_RLC0_MIDCMD_DATA2 0 0x3543 1 0 4294967295 DATA2 0 31 mmSDMA0_RLC0_MIDCMD_DATA3 0 0x3544 1 0 4294967295 DATA3 0 31 mmSDMA0_RLC0_MIDCMD_DATA4 0 0x3545 1 0 4294967295 DATA4 0 31 mmSDMA0_RLC0_MIDCMD_DATA5 0 0x3546 1 0 4294967295 DATA5 0 31 mmSDMA0_RLC0_MIDCMD_CNTL 0 0x3547 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA0_RLC1_RB_CNTL 0 0x3580 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA0_RLC1_RB_BASE 0 0x3581 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC1_RB_BASE_HI 0 0x3582 1 0 4294967295 ADDR 0 23 mmSDMA0_RLC1_RB_RPTR 0 0x3583 1 0 4294967295 OFFSET 2 31 mmSDMA0_RLC1_RB_WPTR 0 0x3584 1 0 4294967295 OFFSET 2 31 mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0 0x3585 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x3586 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x3587 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0 0x3588 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0 0x3589 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC1_IB_CNTL 0 0x358a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA0_RLC1_IB_RPTR 0 0x358b 1 0 4294967295 OFFSET 2 21 mmSDMA0_RLC1_IB_OFFSET 0 0x358c 1 0 4294967295 OFFSET 2 21 mmSDMA0_RLC1_IB_BASE_LO 0 0x358d 1 0 4294967295 ADDR 5 31 mmSDMA0_RLC1_IB_BASE_HI 0 0x358e 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC1_IB_SIZE 0 0x358f 1 0 4294967295 SIZE 0 19 mmSDMA0_RLC1_SKIP_CNTL 0 0x3590 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA0_RLC1_CONTEXT_STATUS 0 0x3591 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA0_RLC1_DOORBELL 0 0x3592 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA0_RLC1_VIRTUAL_ADDR 0 0x35a7 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA0_RLC1_APE1_CNTL 0 0x35a8 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA0_RLC1_DOORBELL_LOG 0 0x35a9 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA0_RLC1_WATERMARK 0 0x35aa 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA0_RLC1_CSA_ADDR_LO 0 0x35ac 1 0 4294967295 ADDR 2 31 mmSDMA0_RLC1_CSA_ADDR_HI 0 0x35ad 1 0 4294967295 ADDR 0 31 mmSDMA0_RLC1_IB_SUB_REMAIN 0 0x35af 1 0 4294967295 SIZE 0 13 mmSDMA0_RLC1_PREEMPT 0 0x35b0 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA0_RLC1_DUMMY_REG 0 0x35b1 1 0 4294967295 DUMMY 0 31 mmSDMA0_RLC1_MIDCMD_DATA0 0 0x35c1 1 0 4294967295 DATA0 0 31 mmSDMA0_RLC1_MIDCMD_DATA1 0 0x35c2 1 0 4294967295 DATA1 0 31 mmSDMA0_RLC1_MIDCMD_DATA2 0 0x35c3 1 0 4294967295 DATA2 0 31 mmSDMA0_RLC1_MIDCMD_DATA3 0 0x35c4 1 0 4294967295 DATA3 0 31 mmSDMA0_RLC1_MIDCMD_DATA4 0 0x35c5 1 0 4294967295 DATA4 0 31 mmSDMA0_RLC1_MIDCMD_DATA5 0 0x35c6 1 0 4294967295 DATA5 0 31 mmSDMA0_RLC1_MIDCMD_CNTL 0 0x35c7 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_UCODE_ADDR 0 0x3600 1 0 4294967295 VALUE 0 12 mmSDMA1_UCODE_DATA 0 0x3601 1 0 4294967295 VALUE 0 31 mmSDMA1_POWER_CNTL 0 0x3602 5 0 4294967295 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 mmSDMA1_CLK_CTRL 0 0x3603 10 0 4294967295 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmSDMA1_CNTL 0 0x3604 13 0 4294967295 TRAP_ENABLE 0 0 ATC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MC_WRREQ_CREDIT 11 16 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 MC_RDREQ_CREDIT 22 27 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA1_CHICKEN_BITS 0 0x3605 9 0 4294967295 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 COPY_OVERLAP_ENABLE 16 16 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA1_TILING_CONFIG 0 0x3606 1 0 4294967295 PIPE_INTERLEAVE_SIZE 4 6 mmSDMA1_HASH 0 0x3607 4 0 4294967295 CHANNEL_BITS 0 2 BANK_BITS 4 6 CHANNEL_XOR_COUNT 8 10 BANK_XOR_COUNT 12 14 mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0 0x3609 1 0 4294967295 TIMER 0 31 mmSDMA1_RB_RPTR_FETCH 0 0x360a 1 0 4294967295 OFFSET 2 31 mmSDMA1_IB_OFFSET_FETCH 0 0x360b 1 0 4294967295 OFFSET 2 21 mmSDMA1_PROGRAM 0 0x360c 1 0 4294967295 STREAM 0 31 mmSDMA1_STATUS_REG 0 0x360d 29 0 4294967295 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA1_STATUS1_REG 0 0x360e 13 0 4294967295 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA1_RD_BURST_CNTL 0 0x360f 1 0 4294967295 RD_BURST 0 1 mmSDMA1_PERFMON_CNTL 0 0x9010 6 0 4294967295 PERF_ENABLE0 0 0 PERF_CLEAR0 1 1 PERF_SEL0 2 7 PERF_ENABLE1 8 8 PERF_CLEAR1 9 9 PERF_SEL1 10 15 mmSDMA1_PERFCOUNTER0_RESULT 0 0x9011 1 0 4294967295 PERF_COUNT 0 31 mmSDMA1_PERFCOUNTER1_RESULT 0 0x9012 1 0 4294967295 PERF_COUNT 0 31 mmSDMA1_F32_CNTL 0 0x3612 3 0 4294967295 HALT 0 0 STEP 1 1 DBG_SELECT_BITS 2 7 mmSDMA1_FREEZE 0 0x3613 3 0 4294967295 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA1_PHASE0_QUANTUM 0 0x3614 3 0 4294967295 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA1_PHASE1_QUANTUM 0 0x3615 3 0 4294967295 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA1_EDC_CONFIG 0 0x361a 2 0 4294967295 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA1_VM_CNTL 0 0x3620 1 0 4294967295 CMD 0 3 mmSDMA1_VM_CTX_LO 0 0x3621 1 0 4294967295 ADDR 2 31 mmSDMA1_VM_CTX_HI 0 0x3622 1 0 4294967295 ADDR 0 31 mmSDMA1_STATUS2_REG 0 0x3623 4 0 4294967295 ID 0 1 F32_INSTR_PTR 2 11 CURRENT_FCN_IDLE 14 15 CMD_OP 16 31 mmSDMA1_ACTIVE_FCN_ID 0 0x3624 2 0 4294967295 VFID 0 3 VF 31 31 mmSDMA1_VM_CTX_CNTL 0 0x3625 2 0 4294967295 PRIV 0 0 VMID 4 7 mmSDMA1_VIRT_RESET_REQ 0 0x3626 2 0 4294967295 VF 0 15 PF 31 31 mmSDMA1_VF_ENABLE 0 0x3627 1 0 4294967295 VF_ENABLE 0 0 mmSDMA1_BA_THRESHOLD 0 0x361b 2 0 4294967295 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA1_ID 0 0x361c 1 0 4294967295 DEVICE_ID 0 7 mmSDMA1_VERSION 0 0x361d 1 0 4294967295 VALUE 0 15 mmSDMA1_ATOMIC_CNTL 0 0x3628 2 0 4294967295 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA1_ATOMIC_PREOP_LO 0 0x3629 1 0 4294967295 DATA 0 31 mmSDMA1_ATOMIC_PREOP_HI 0 0x362a 1 0 4294967295 DATA 0 31 mmSDMA1_POWER_CNTL_IDLE 0 0x362c 2 0 4294967295 DELAY1 0 15 DELAY2 16 31 mmSDMA1_PERF_REG_TYPE0 0 0x3677 4 0 4294967295 SDMA1_PERFMON_CNTL 0 0 SDMA1_PERFCOUNTER0_RESULT 1 1 SDMA1_PERFCOUNTER1_RESULT 2 2 RESERVED_31_3 3 31 mmSDMA1_CONTEXT_REG_TYPE0 0 0x3678 21 0 4294967295 SDMA1_GFX_RB_CNTL 0 0 SDMA1_GFX_RB_BASE 1 1 SDMA1_GFX_RB_BASE_HI 2 2 SDMA1_GFX_RB_RPTR 3 3 SDMA1_GFX_RB_WPTR 4 4 SDMA1_GFX_RB_WPTR_POLL_CNTL 5 5 SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 6 6 SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 7 7 SDMA1_GFX_RB_RPTR_ADDR_HI 8 8 SDMA1_GFX_RB_RPTR_ADDR_LO 9 9 SDMA1_GFX_IB_CNTL 10 10 SDMA1_GFX_IB_RPTR 11 11 SDMA1_GFX_IB_OFFSET 12 12 SDMA1_GFX_IB_BASE_LO 13 13 SDMA1_GFX_IB_BASE_HI 14 14 SDMA1_GFX_IB_SIZE 15 15 SDMA1_GFX_SKIP_CNTL 16 16 SDMA1_GFX_CONTEXT_STATUS 17 17 SDMA1_GFX_DOORBELL 18 18 SDMA1_GFX_CONTEXT_CNTL 19 19 RESERVED 20 31 mmSDMA1_CONTEXT_REG_TYPE1 0 0x3679 13 0 4294967295 VOID_REG0 0 6 SDMA1_GFX_VIRTUAL_ADDR 7 7 SDMA1_GFX_APE1_CNTL 8 8 SDMA1_GFX_DOORBELL_LOG 9 9 SDMA1_GFX_WATERMARK 10 10 VOID_REG2 11 11 SDMA1_GFX_CSA_ADDR_LO 12 12 SDMA1_GFX_CSA_ADDR_HI 13 13 VOID_REG3 14 14 SDMA1_GFX_IB_SUB_REMAIN 15 15 SDMA1_GFX_PREEMPT 16 16 SDMA1_GFX_DUMMY_REG 17 17 RESERVED 18 31 mmSDMA1_CONTEXT_REG_TYPE2 0 0x367a 8 0 4294967295 SDMA1_GFX_MIDCMD_DATA0 0 0 SDMA1_GFX_MIDCMD_DATA1 1 1 SDMA1_GFX_MIDCMD_DATA2 2 2 SDMA1_GFX_MIDCMD_DATA3 3 3 SDMA1_GFX_MIDCMD_DATA4 4 4 SDMA1_GFX_MIDCMD_DATA5 5 5 SDMA1_GFX_MIDCMD_CNTL 6 6 RESERVED 7 31 mmSDMA1_PUB_REG_TYPE0 0 0x367c 27 0 4294967295 SDMA1_UCODE_ADDR 0 0 SDMA1_UCODE_DATA 1 1 SDMA1_POWER_CNTL 2 2 SDMA1_CLK_CTRL 3 3 SDMA1_CNTL 4 4 SDMA1_CHICKEN_BITS 5 5 SDMA1_TILING_CONFIG 6 6 SDMA1_HASH 7 7 SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 9 9 SDMA1_RB_RPTR_FETCH 10 10 SDMA1_IB_OFFSET_FETCH 11 11 SDMA1_PROGRAM 12 12 SDMA1_STATUS_REG 13 13 SDMA1_STATUS1_REG 14 14 SDMA1_RD_BURST_CNTL 15 15 RESERVED_16 16 16 RESERVED_17 17 17 SDMA1_F32_CNTL 18 18 SDMA1_FREEZE 19 19 SDMA1_PHASE0_QUANTUM 20 20 SDMA1_PHASE1_QUANTUM 21 21 VOID_REG0 22 25 SDMA1_EDC_CONFIG 26 26 SDMA1_BA_THRESHOLD 27 27 SDMA1_DEVICE_ID 28 28 SDMA1_VERSION 29 29 RESERVED 30 31 mmSDMA1_PUB_REG_TYPE1 0 0x367d 12 0 4294967295 SDMA1_VM_CNTL 0 0 SDMA1_VM_CTX_LO 1 1 SDMA1_VM_CTX_HI 2 2 SDMA1_STATUS2_REG 3 3 SDMA1_ACTIVE_FCN_ID 4 4 SDMA1_VM_CTX_CNTL 5 5 SDMA1_VIRT_RESET_REQ 6 6 SDMA1_VF_ENABLE 7 7 SDMA1_ATOMIC_CNTL 8 8 SDMA1_ATOMIC_PREOP_LO 9 9 SDMA1_ATOMIC_PREOP_HI 10 10 RESERVED 11 31 mmSDMA1_GFX_RB_CNTL 0 0x3680 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA1_GFX_RB_BASE 0 0x3681 1 0 4294967295 ADDR 0 31 mmSDMA1_GFX_RB_BASE_HI 0 0x3682 1 0 4294967295 ADDR 0 23 mmSDMA1_GFX_RB_RPTR 0 0x3683 1 0 4294967295 OFFSET 2 31 mmSDMA1_GFX_RB_WPTR 0 0x3684 1 0 4294967295 OFFSET 2 31 mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0 0x3685 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0 0x3686 1 0 4294967295 ADDR 0 31 mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0 0x3687 1 0 4294967295 ADDR 2 31 mmSDMA1_GFX_RB_RPTR_ADDR_HI 0 0x3688 1 0 4294967295 ADDR 0 31 mmSDMA1_GFX_RB_RPTR_ADDR_LO 0 0x3689 1 0 4294967295 ADDR 2 31 mmSDMA1_GFX_IB_CNTL 0 0x368a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_GFX_IB_RPTR 0 0x368b 1 0 4294967295 OFFSET 2 21 mmSDMA1_GFX_IB_OFFSET 0 0x368c 1 0 4294967295 OFFSET 2 21 mmSDMA1_GFX_IB_BASE_LO 0 0x368d 1 0 4294967295 ADDR 5 31 mmSDMA1_GFX_IB_BASE_HI 0 0x368e 1 0 4294967295 ADDR 0 31 mmSDMA1_GFX_IB_SIZE 0 0x368f 1 0 4294967295 SIZE 0 19 mmSDMA1_GFX_SKIP_CNTL 0 0x3690 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA1_GFX_CONTEXT_STATUS 0 0x3691 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_GFX_DOORBELL 0 0x3692 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_GFX_CONTEXT_CNTL 0 0x3693 2 0 4294967295 RESUME_CTX 16 16 SESSION_SEL 24 27 mmSDMA1_GFX_VIRTUAL_ADDR 0 0x36a7 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA1_GFX_APE1_CNTL 0 0x36a8 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA1_GFX_DOORBELL_LOG 0 0x36a9 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA1_GFX_WATERMARK 0 0x36aa 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA1_GFX_CSA_ADDR_LO 0 0x36ac 1 0 4294967295 ADDR 2 31 mmSDMA1_GFX_CSA_ADDR_HI 0 0x36ad 1 0 4294967295 ADDR 0 31 mmSDMA1_GFX_IB_SUB_REMAIN 0 0x36af 1 0 4294967295 SIZE 0 13 mmSDMA1_GFX_PREEMPT 0 0x36b0 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA1_GFX_DUMMY_REG 0 0x36b1 1 0 4294967295 DUMMY 0 31 mmSDMA1_GFX_MIDCMD_DATA0 0 0x36c1 1 0 4294967295 DATA0 0 31 mmSDMA1_GFX_MIDCMD_DATA1 0 0x36c2 1 0 4294967295 DATA1 0 31 mmSDMA1_GFX_MIDCMD_DATA2 0 0x36c3 1 0 4294967295 DATA2 0 31 mmSDMA1_GFX_MIDCMD_DATA3 0 0x36c4 1 0 4294967295 DATA3 0 31 mmSDMA1_GFX_MIDCMD_DATA4 0 0x36c5 1 0 4294967295 DATA4 0 31 mmSDMA1_GFX_MIDCMD_DATA5 0 0x36c6 1 0 4294967295 DATA5 0 31 mmSDMA1_GFX_MIDCMD_CNTL 0 0x36c7 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC0_RB_CNTL 0 0x3700 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA1_RLC0_RB_BASE 0 0x3701 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC0_RB_BASE_HI 0 0x3702 1 0 4294967295 ADDR 0 23 mmSDMA1_RLC0_RB_RPTR 0 0x3703 1 0 4294967295 OFFSET 2 31 mmSDMA1_RLC0_RB_WPTR 0 0x3704 1 0 4294967295 OFFSET 2 31 mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0 0x3705 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x3706 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x3707 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0 0x3708 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0 0x3709 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC0_IB_CNTL 0 0x370a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC0_IB_RPTR 0 0x370b 1 0 4294967295 OFFSET 2 21 mmSDMA1_RLC0_IB_OFFSET 0 0x370c 1 0 4294967295 OFFSET 2 21 mmSDMA1_RLC0_IB_BASE_LO 0 0x370d 1 0 4294967295 ADDR 5 31 mmSDMA1_RLC0_IB_BASE_HI 0 0x370e 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC0_IB_SIZE 0 0x370f 1 0 4294967295 SIZE 0 19 mmSDMA1_RLC0_SKIP_CNTL 0 0x3710 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA1_RLC0_CONTEXT_STATUS 0 0x3711 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC0_DOORBELL 0 0x3712 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC0_VIRTUAL_ADDR 0 0x3727 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA1_RLC0_APE1_CNTL 0 0x3728 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA1_RLC0_DOORBELL_LOG 0 0x3729 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC0_WATERMARK 0 0x372a 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA1_RLC0_CSA_ADDR_LO 0 0x372c 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC0_CSA_ADDR_HI 0 0x372d 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC0_IB_SUB_REMAIN 0 0x372f 1 0 4294967295 SIZE 0 13 mmSDMA1_RLC0_PREEMPT 0 0x3730 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA1_RLC0_DUMMY_REG 0 0x3731 1 0 4294967295 DUMMY 0 31 mmSDMA1_RLC0_MIDCMD_DATA0 0 0x3741 1 0 4294967295 DATA0 0 31 mmSDMA1_RLC0_MIDCMD_DATA1 0 0x3742 1 0 4294967295 DATA1 0 31 mmSDMA1_RLC0_MIDCMD_DATA2 0 0x3743 1 0 4294967295 DATA2 0 31 mmSDMA1_RLC0_MIDCMD_DATA3 0 0x3744 1 0 4294967295 DATA3 0 31 mmSDMA1_RLC0_MIDCMD_DATA4 0 0x3745 1 0 4294967295 DATA4 0 31 mmSDMA1_RLC0_MIDCMD_DATA5 0 0x3746 1 0 4294967295 DATA5 0 31 mmSDMA1_RLC0_MIDCMD_CNTL 0 0x3747 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA1_RLC1_RB_CNTL 0 0x3780 8 0 4294967295 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA1_RLC1_RB_BASE 0 0x3781 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC1_RB_BASE_HI 0 0x3782 1 0 4294967295 ADDR 0 23 mmSDMA1_RLC1_RB_RPTR 0 0x3783 1 0 4294967295 OFFSET 2 31 mmSDMA1_RLC1_RB_WPTR 0 0x3784 1 0 4294967295 OFFSET 2 31 mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0 0x3785 5 0 4294967295 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x3786 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x3787 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0 0x3788 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0 0x3789 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC1_IB_CNTL 0 0x378a 4 0 4294967295 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA1_RLC1_IB_RPTR 0 0x378b 1 0 4294967295 OFFSET 2 21 mmSDMA1_RLC1_IB_OFFSET 0 0x378c 1 0 4294967295 OFFSET 2 21 mmSDMA1_RLC1_IB_BASE_LO 0 0x378d 1 0 4294967295 ADDR 5 31 mmSDMA1_RLC1_IB_BASE_HI 0 0x378e 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC1_IB_SIZE 0 0x378f 1 0 4294967295 SIZE 0 19 mmSDMA1_RLC1_SKIP_CNTL 0 0x3790 1 0 4294967295 SKIP_COUNT 0 13 mmSDMA1_RLC1_CONTEXT_STATUS 0 0x3791 8 0 4294967295 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA1_RLC1_DOORBELL 0 0x3792 3 0 4294967295 OFFSET 0 20 ENABLE 28 28 CAPTURED 30 30 mmSDMA1_RLC1_VIRTUAL_ADDR 0 0x37a7 5 0 4294967295 ATC 0 0 INVAL 1 1 PTR32 4 4 SHARED_BASE 8 10 VM_HOLE 30 30 mmSDMA1_RLC1_APE1_CNTL 0 0x37a8 2 0 4294967295 BASE 0 15 LIMIT 16 31 mmSDMA1_RLC1_DOORBELL_LOG 0 0x37a9 2 0 4294967295 BE_ERROR 0 0 DATA 2 31 mmSDMA1_RLC1_WATERMARK 0 0x37aa 2 0 4294967295 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 24 mmSDMA1_RLC1_CSA_ADDR_LO 0 0x37ac 1 0 4294967295 ADDR 2 31 mmSDMA1_RLC1_CSA_ADDR_HI 0 0x37ad 1 0 4294967295 ADDR 0 31 mmSDMA1_RLC1_IB_SUB_REMAIN 0 0x37af 1 0 4294967295 SIZE 0 13 mmSDMA1_RLC1_PREEMPT 0 0x37b0 1 0 4294967295 IB_PREEMPT 0 0 mmSDMA1_RLC1_DUMMY_REG 0 0x37b1 1 0 4294967295 DUMMY 0 31 mmSDMA1_RLC1_MIDCMD_DATA0 0 0x37c1 1 0 4294967295 DATA0 0 31 mmSDMA1_RLC1_MIDCMD_DATA1 0 0x37c2 1 0 4294967295 DATA1 0 31 mmSDMA1_RLC1_MIDCMD_DATA2 0 0x37c3 1 0 4294967295 DATA2 0 31 mmSDMA1_RLC1_MIDCMD_DATA3 0 0x37c4 1 0 4294967295 DATA3 0 31 mmSDMA1_RLC1_MIDCMD_DATA4 0 0x37c5 1 0 4294967295 DATA4 0 31 mmSDMA1_RLC1_MIDCMD_DATA5 0 0x37c6 1 0 4294967295 DATA5 0 31 mmSDMA1_RLC1_MIDCMD_CNTL 0 0x37c7 4 0 4294967295 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmHDP_HOST_PATH_CNTL 0 0xb00 12 0 4294967295 BIF_RDRET_CREDIT 0 2 MC_WRREQ_CREDIT 3 8 WR_STALL_TIMER 9 10 RD_STALL_TIMER 11 12 WRITE_COMBINE_TIMER 19 20 WRITE_COMBINE_EN 21 21 CACHE_INVALIDATE 22 22 CLOCK_GATING_DIS 23 23 REG_CLK_ENABLE_COUNT 24 27 ALL_SURFACES_DIS 29 29 WRITE_THROUGH_CACHE_DIS 30 30 LIN_RD_CACHE_DIS 31 31 mmHDP_NONSURFACE_BASE 0 0xb01 1 0 4294967295 NONSURF_BASE 0 31 mmHDP_NONSURFACE_INFO 0 0xb02 15 0 4294967295 NONSURF_ADDR_TYPE 0 0 NONSURF_ARRAY_MODE 1 4 NONSURF_ENDIAN 5 6 NONSURF_PIXEL_SIZE 7 9 NONSURF_SAMPLE_NUM 10 12 NONSURF_SAMPLE_SIZE 13 14 NONSURF_PRIV 15 15 NONSURF_TILE_COMPACT 16 16 NONSURF_TILE_SPLIT 17 19 NONSURF_NUM_BANKS 20 21 NONSURF_BANK_WIDTH 22 23 NONSURF_BANK_HEIGHT 24 25 NONSURF_MACRO_TILE_ASPECT 26 27 NONSURF_MICRO_TILE_MODE 28 30 NONSURF_SLICE_TILE_MAX_MSB 31 31 mmHDP_NONSURFACE_SIZE 0 0xb03 2 0 4294967295 NONSURF_PITCH_TILE_MAX 0 10 NONSURF_SLICE_TILE_MAX 11 31 mmHDP_NONSURF_FLAGS 0 0xbc9 2 0 4294967295 NONSURF_WRITE_FLAG 0 0 NONSURF_READ_FLAG 1 1 mmHDP_NONSURF_FLAGS_CLR 0 0xbca 2 0 4294967295 NONSURF_WRITE_FLAG_CLR 0 0 NONSURF_READ_FLAG_CLR 1 1 mmHDP_SW_SEMAPHORE 0 0xbcb 1 0 4294967295 SW_SEMAPHORE 0 31 mmHDP_DEBUG0 0 0xbcc 1 0 4294967295 HDP_DEBUG 0 0 mmHDP_DEBUG1 0 0xbcd 1 0 4294967295 HDP_DEBUG 0 0 mmHDP_LAST_SURFACE_HIT 0 0xbce 1 0 4294967295 LAST_SURFACE_HIT 0 5 mmHDP_TILING_CONFIG 0 0xbcf 6 0 4294967295 PIPE_TILING 1 3 BANK_TILING 4 5 GROUP_SIZE 6 7 ROW_TILING 8 10 BANK_SWAPS 11 13 SAMPLE_SPLIT 14 15 mmHDP_SC_MULTI_CHIP_CNTL 0 0xbd0 2 0 4294967295 LOG2_NUM_CHIPS 0 2 MULTI_CHIP_TILE_SIZE 3 4 mmHDP_OUTSTANDING_REQ 0 0xbd1 2 0 4294967295 WRITE_REQ 0 7 READ_REQ 8 15 mmHDP_ADDR_CONFIG 0 0xbd2 9 0 4294967295 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 4 6 BANK_INTERLEAVE_SIZE 8 10 NUM_SHADER_ENGINES 12 13 SHADER_ENGINE_TILE_SIZE 16 18 NUM_GPUS 20 22 MULTI_GPU_TILE_SIZE 24 25 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 mmHDP_MISC_CNTL 0 0xbd3 13 0 4294967295 FLUSH_INVALIDATE_CACHE 0 0 VM_ID 1 4 OUTSTANDING_WRITE_COUNT_1024 5 5 MULTIPLE_READS 6 6 HDP_BIF_RDRET_CREDIT 7 10 SIMULTANEOUS_READS_WRITES 11 11 NO_SPLIT_ARRAY_LINEAR 12 12 MC_RDREQ_CREDIT 13 18 READ_CACHE_INVALIDATE 19 19 ADDRLIB_LINEAR_BYPASS 20 20 FED_ENABLE 21 21 LEGACY_TILING_ENABLE 22 22 LEGACY_SURFACES_ENABLE 23 23 mmHDP_MEM_POWER_LS 0 0xbd4 3 0 4294967295 LS_ENABLE 0 0 LS_SETUP 1 6 LS_HOLD 7 12 mmHDP_NONSURFACE_PREFETCH 0 0xbd5 5 0 4294967295 NONSURF_PREFETCH_PRI 0 2 NONSURF_PREFETCH_DIR 3 5 NONSURF_PREFETCH_NUM 6 8 NONSURF_PREFETCH_MAX_Z 9 19 NONSURF_PIPE_CONFIG 27 31 mmHDP_MEMIO_CNTL 0 0xbf6 10 0 4294967295 MEMIO_SEND 0 0 MEMIO_OP 1 1 MEMIO_BE 2 5 MEMIO_WR_STROBE 6 6 MEMIO_RD_STROBE 7 7 MEMIO_ADDR_UPPER 8 13 MEMIO_CLR_WR_ERROR 14 14 MEMIO_CLR_RD_ERROR 15 15 MEMIO_VF 16 16 MEMIO_VFID 17 20 mmHDP_MEMIO_ADDR 0 0xbf7 1 0 4294967295 MEMIO_ADDR_LOWER 0 31 mmHDP_MEMIO_STATUS 0 0xbf8 4 0 4294967295 MEMIO_WR_STATUS 0 0 MEMIO_RD_STATUS 1 1 MEMIO_WR_ERROR 2 2 MEMIO_RD_ERROR 3 3 mmHDP_MEMIO_WR_DATA 0 0xbf9 1 0 4294967295 MEMIO_WR_DATA 0 31 mmHDP_MEMIO_RD_DATA 0 0xbfa 1 0 4294967295 MEMIO_RD_DATA 0 31 mmHDP_VF_ENABLE 0 0xbfb 2 0 4294967295 VF_EN 0 0 VF_NUM 16 31 mmHDP_XDP_DIRECT2HDP_FIRST 0 0xc00 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_FLUSH 0 0xc01 9 0 4294967295 D2H_FLUSH_FLUSH_NUM 0 3 D2H_FLUSH_MBX_ENC_DATA 4 7 D2H_FLUSH_MBX_ADDR_SEL 8 10 D2H_FLUSH_XPB_CLG 11 15 D2H_FLUSH_SEND_HOST 16 16 D2H_FLUSH_SEND_SIDE 17 17 D2H_FLUSH_ALTER_FLUSH_NUM 18 18 D2H_FLUSH_RSVD_0 19 19 D2H_FLUSH_RSVD_1 20 20 mmHDP_XDP_D2H_BAR_UPDATE 0 0xc02 3 0 4294967295 D2H_BAR_UPDATE_ADDR 0 15 D2H_BAR_UPDATE_FLUSH_NUM 16 19 D2H_BAR_UPDATE_BAR_NUM 20 22 mmHDP_XDP_D2H_RSVD_3 0 0xc03 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_4 0 0xc04 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_5 0 0xc05 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_6 0 0xc06 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_7 0 0xc07 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_8 0 0xc08 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_9 0 0xc09 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_10 0 0xc0a 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_11 0 0xc0b 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_12 0 0xc0c 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_13 0 0xc0d 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_14 0 0xc0e 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_15 0 0xc0f 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_16 0 0xc10 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_17 0 0xc11 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_18 0 0xc12 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_19 0 0xc13 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_20 0 0xc14 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_21 0 0xc15 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_22 0 0xc16 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_23 0 0xc17 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_24 0 0xc18 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_25 0 0xc19 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_26 0 0xc1a 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_27 0 0xc1b 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_28 0 0xc1c 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_29 0 0xc1d 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_30 0 0xc1e 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_31 0 0xc1f 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_32 0 0xc20 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_33 0 0xc21 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_D2H_RSVD_34 0 0xc22 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_DIRECT2HDP_LAST 0 0xc23 1 0 4294967295 RESERVED 0 31 mmHDP_XDP_P2P_BAR_CFG 0 0xc24 2 0 4294967295 P2P_BAR_CFG_ADDR_SIZE 0 3 P2P_BAR_CFG_BAR_FROM 4 5 mmHDP_XDP_P2P_MBX_OFFSET 0 0xc25 1 0 4294967295 P2P_MBX_OFFSET 0 13 mmHDP_XDP_P2P_MBX_ADDR0 0 0xc26 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR1 0 0xc27 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR2 0 0xc28 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR3 0 0xc29 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR4 0 0xc2a 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR5 0 0xc2b 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_P2P_MBX_ADDR6 0 0xc2c 3 0 4294967295 VALID 0 0 ADDR 1 20 ADDR_39_36 21 24 mmHDP_XDP_HDP_MBX_MC_CFG 0 0xc2d 4 0 4294967295 HDP_MBX_MC_CFG_TAP_WRREQ_PRIV 0 0 HDP_MBX_MC_CFG_TAP_WRREQ_SWAP 1 2 HDP_MBX_MC_CFG_TAP_WRREQ_TRAN 3 3 HDP_MBX_MC_CFG_TAP_WRREQ_VMID 4 7 mmHDP_XDP_HDP_MC_CFG 0 0xc2e 11 0 4294967295 HDP_MC_CFG_HST_TAP_WRREQ_PRIV 0 0 HDP_MC_CFG_HST_TAP_WRREQ_SWAP 1 2 HDP_MC_CFG_HST_TAP_WRREQ_TRAN 3 3 HDP_MC_CFG_SID_TAP_WRREQ_PRIV 4 4 HDP_MC_CFG_SID_TAP_WRREQ_SWAP 5 6 HDP_MC_CFG_SID_TAP_WRREQ_TRAN 7 7 HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE 8 13 HDP_MC_CFG_XDP_HIGHER_PRI_THRESH 14 19 HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK 20 22 HDP_MC_CFG_HST_TAP_WRREQ_VMID 23 26 HDP_MC_CFG_SID_TAP_WRREQ_VMID 27 30 mmHDP_XDP_HST_CFG 0 0xc2f 2 0 4294967295 HST_CFG_WR_COMBINE_EN 0 0 HST_CFG_WR_COMBINE_TIMER 1 2 mmHDP_XDP_SID_CFG 0 0xc30 3 0 4294967295 SID_CFG_WR_COMBINE_EN 0 0 SID_CFG_WR_COMBINE_TIMER 1 2 SID_CFG_FLNUM_MSB_SEL 3 4 mmHDP_XDP_HDP_IPH_CFG 0 0xc31 4 0 4294967295 HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE 0 5 HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE 6 11 HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING 12 12 HDP_IPH_CFG_P2P_RD_EN 13 13 mmHDP_XDP_SRBM_CFG 0 0xc32 3 0 4294967295 SRBM_CFG_REG_CLK_ENABLE_COUNT 0 5 SRBM_CFG_REG_CLK_GATING_DIS 6 6 SRBM_CFG_WAKE_DYN_CLK 7 7 mmHDP_XDP_CGTT_BLK_CTRL 0 0xc33 5 0 4294967295 CGTT_BLK_CTRL_0_ON_DELAY 0 3 CGTT_BLK_CTRL_1_OFF_DELAY 4 11 CGTT_BLK_CTRL_2_RSVD 12 29 CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE 30 30 CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE 31 31 mmHDP_XDP_P2P_BAR0 0 0xc34 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR1 0 0xc35 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR2 0 0xc36 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR3 0 0xc37 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR4 0 0xc38 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR5 0 0xc39 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR6 0 0xc3a 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_P2P_BAR7 0 0xc3b 3 0 4294967295 ADDR 0 15 FLUSH 16 19 VALID 20 20 mmHDP_XDP_FLUSH_ARMED_STS 0 0xc3c 1 0 4294967295 FLUSH_ARMED_STS 0 31 mmHDP_XDP_FLUSH_CNTR0_STS 0 0xc3d 1 0 4294967295 FLUSH_CNTR0_STS 0 25 mmHDP_XDP_BUSY_STS 0 0xc3e 1 0 4294967295 BUSY_BITS 0 17 mmHDP_XDP_STICKY 0 0xc3f 2 0 4294967295 STICKY_STS 0 15 STICKY_W1C 16 31 mmHDP_XDP_CHKN 0 0xc40 4 0 4294967295 CHKN_0_RSVD 0 7 CHKN_1_RSVD 8 15 CHKN_2_RSVD 16 23 CHKN_3_RSVD 24 31 mmHDP_XDP_DBG_ADDR 0 0xc41 2 0 4294967295 STS 0 15 CTRL 16 31 mmHDP_XDP_DBG_DATA 0 0xc42 2 0 4294967295 STS 0 15 CTRL 16 31 mmHDP_XDP_DBG_MASK 0 0xc43 2 0 4294967295 STS 0 15 CTRL 16 31 mmHDP_XDP_BARS_ADDR_39_36 0 0xc44 8 0 4294967295 BAR0_ADDR_39_36 0 3 BAR1_ADDR_39_36 4 7 BAR2_ADDR_39_36 8 11 BAR3_ADDR_39_36 12 15 BAR4_ADDR_39_36 16 19 BAR5_ADDR_39_36 20 23 BAR6_ADDR_39_36 24 27 BAR7_ADDR_39_36 28 31