507 mmSDMA3_UCODE_ADDR 0 0x0 1 0 1 VALUE 0 12 mmSDMA3_UCODE_DATA 0 0x1 1 0 1 VALUE 0 31 mmSDMA3_VM_CNTL 0 0x4 1 0 1 CMD 0 3 mmSDMA3_VM_CTX_LO 0 0x5 1 0 1 ADDR 2 31 mmSDMA3_VM_CTX_HI 0 0x6 1 0 1 ADDR 0 31 mmSDMA3_ACTIVE_FCN_ID 0 0x7 3 0 1 VFID 0 3 RESERVED 4 30 VF 31 31 mmSDMA3_VM_CTX_CNTL 0 0x8 2 0 1 PRIV 0 0 VMID 4 7 mmSDMA3_VIRT_RESET_REQ 0 0x9 2 0 1 VF 0 15 PF 31 31 mmSDMA3_VF_ENABLE 0 0xa 1 0 1 VF_ENABLE 0 0 mmSDMA3_CONTEXT_REG_TYPE0 0 0xb 20 0 1 SDMA3_GFX_RB_CNTL 0 0 SDMA3_GFX_RB_BASE 1 1 SDMA3_GFX_RB_BASE_HI 2 2 SDMA3_GFX_RB_RPTR 3 3 SDMA3_GFX_RB_RPTR_HI 4 4 SDMA3_GFX_RB_WPTR 5 5 SDMA3_GFX_RB_WPTR_HI 6 6 SDMA3_GFX_RB_WPTR_POLL_CNTL 7 7 SDMA3_GFX_RB_RPTR_ADDR_HI 8 8 SDMA3_GFX_RB_RPTR_ADDR_LO 9 9 SDMA3_GFX_IB_CNTL 10 10 SDMA3_GFX_IB_RPTR 11 11 SDMA3_GFX_IB_OFFSET 12 12 SDMA3_GFX_IB_BASE_LO 13 13 SDMA3_GFX_IB_BASE_HI 14 14 SDMA3_GFX_IB_SIZE 15 15 SDMA3_GFX_SKIP_CNTL 16 16 SDMA3_GFX_CONTEXT_STATUS 17 17 SDMA3_GFX_DOORBELL 18 18 SDMA3_GFX_CONTEXT_CNTL 19 19 mmSDMA3_CONTEXT_REG_TYPE1 0 0xc 15 0 1 SDMA3_GFX_STATUS 8 8 SDMA3_GFX_DOORBELL_LOG 9 9 SDMA3_GFX_WATERMARK 10 10 SDMA3_GFX_DOORBELL_OFFSET 11 11 SDMA3_GFX_CSA_ADDR_LO 12 12 SDMA3_GFX_CSA_ADDR_HI 13 13 VOID_REG2 14 14 SDMA3_GFX_IB_SUB_REMAIN 15 15 SDMA3_GFX_PREEMPT 16 16 SDMA3_GFX_DUMMY_REG 17 17 SDMA3_GFX_RB_WPTR_POLL_ADDR_HI 18 18 SDMA3_GFX_RB_WPTR_POLL_ADDR_LO 19 19 SDMA3_GFX_RB_AQL_CNTL 20 20 SDMA3_GFX_MINOR_PTR_UPDATE 21 21 RESERVED 22 31 mmSDMA3_CONTEXT_REG_TYPE2 0 0xd 11 0 1 SDMA3_GFX_MIDCMD_DATA0 0 0 SDMA3_GFX_MIDCMD_DATA1 1 1 SDMA3_GFX_MIDCMD_DATA2 2 2 SDMA3_GFX_MIDCMD_DATA3 3 3 SDMA3_GFX_MIDCMD_DATA4 4 4 SDMA3_GFX_MIDCMD_DATA5 5 5 SDMA3_GFX_MIDCMD_DATA6 6 6 SDMA3_GFX_MIDCMD_DATA7 7 7 SDMA3_GFX_MIDCMD_DATA8 8 8 SDMA3_GFX_MIDCMD_CNTL 9 9 RESERVED 10 31 mmSDMA3_CONTEXT_REG_TYPE3 0 0xe 1 0 1 RESERVED 0 31 mmSDMA3_PUB_REG_TYPE0 0 0xf 27 0 1 SDMA3_UCODE_ADDR 0 0 SDMA3_UCODE_DATA 1 1 RESERVED3 3 3 SDMA3_VM_CNTL 4 4 SDMA3_VM_CTX_LO 5 5 SDMA3_VM_CTX_HI 6 6 SDMA3_ACTIVE_FCN_ID 7 7 SDMA3_VM_CTX_CNTL 8 8 SDMA3_VIRT_RESET_REQ 9 9 RESERVED10 10 10 SDMA3_CONTEXT_REG_TYPE0 11 11 SDMA3_CONTEXT_REG_TYPE1 12 12 SDMA3_CONTEXT_REG_TYPE2 13 13 SDMA3_CONTEXT_REG_TYPE3 14 14 SDMA3_PUB_REG_TYPE0 15 15 SDMA3_PUB_REG_TYPE1 16 16 SDMA3_PUB_REG_TYPE2 17 17 SDMA3_PUB_REG_TYPE3 18 18 SDMA3_MMHUB_CNTL 19 19 RESERVED_FOR_PSPSMU_ACCESS_ONLY 21 24 SDMA3_CONTEXT_GROUP_BOUNDARY 25 25 SDMA3_POWER_CNTL 26 26 SDMA3_CLK_CTRL 27 27 SDMA3_CNTL 28 28 SDMA3_CHICKEN_BITS 29 29 SDMA3_GB_ADDR_CONFIG 30 30 SDMA3_GB_ADDR_CONFIG_READ 31 31 mmSDMA3_PUB_REG_TYPE1 0 0x10 32 0 1 SDMA3_RB_RPTR_FETCH_HI 0 0 SDMA3_SEM_WAIT_FAIL_TIMER_CNTL 1 1 SDMA3_RB_RPTR_FETCH 2 2 SDMA3_IB_OFFSET_FETCH 3 3 SDMA3_PROGRAM 4 4 SDMA3_STATUS_REG 5 5 SDMA3_STATUS1_REG 6 6 SDMA3_RD_BURST_CNTL 7 7 SDMA3_HBM_PAGE_CONFIG 8 8 SDMA3_UCODE_CHECKSUM 9 9 SDMA3_F32_CNTL 10 10 SDMA3_FREEZE 11 11 SDMA3_PHASE0_QUANTUM 12 12 SDMA3_PHASE1_QUANTUM 13 13 SDMA_POWER_GATING 14 14 SDMA_PGFSM_CONFIG 15 15 SDMA_PGFSM_WRITE 16 16 SDMA_PGFSM_READ 17 17 SDMA3_EDC_CONFIG 18 18 SDMA3_BA_THRESHOLD 19 19 SDMA3_ID 20 20 SDMA3_VERSION 21 21 SDMA3_EDC_COUNTER 22 22 SDMA3_EDC_COUNTER_CLEAR 23 23 SDMA3_STATUS2_REG 24 24 SDMA3_ATOMIC_CNTL 25 25 SDMA3_ATOMIC_PREOP_LO 26 26 SDMA3_ATOMIC_PREOP_HI 27 27 SDMA3_UTCL1_CNTL 28 28 SDMA3_UTCL1_WATERMK 29 29 SDMA3_UTCL1_RD_STATUS 30 30 SDMA3_UTCL1_WR_STATUS 31 31 mmSDMA3_PUB_REG_TYPE2 0 0x11 32 0 1 SDMA3_UTCL1_INV0 0 0 SDMA3_UTCL1_INV1 1 1 SDMA3_UTCL1_INV2 2 2 SDMA3_UTCL1_RD_XNACK0 3 3 SDMA3_UTCL1_RD_XNACK1 4 4 SDMA3_UTCL1_WR_XNACK0 5 5 SDMA3_UTCL1_WR_XNACK1 6 6 SDMA3_UTCL1_TIMEOUT 7 7 SDMA3_UTCL1_PAGE 8 8 SDMA3_POWER_CNTL_IDLE 9 9 SDMA3_RELAX_ORDERING_LUT 10 10 SDMA3_CHICKEN_BITS_2 11 11 SDMA3_STATUS3_REG 12 12 SDMA3_PHYSICAL_ADDR_LO 13 13 SDMA3_PHYSICAL_ADDR_HI 14 14 SDMA3_PHASE2_QUANTUM 15 15 SDMA3_ERROR_LOG 16 16 SDMA3_PUB_DUMMY_REG0 17 17 SDMA3_PUB_DUMMY_REG1 18 18 SDMA3_PUB_DUMMY_REG2 19 19 SDMA3_PUB_DUMMY_REG3 20 20 SDMA3_F32_COUNTER 21 21 SDMA3_UNBREAKABLE 22 22 SDMA3_PERFMON_CNTL 23 23 SDMA3_PERFCOUNTER0_RESULT 24 24 SDMA3_PERFCOUNTER1_RESULT 25 25 SDMA3_PERFCOUNTER_TAG_DELAY_RANGE 26 26 SDMA3_CRD_CNTL 27 27 RESERVED28 28 28 SDMA3_GPU_IOV_VIOLATION_LOG 29 29 SDMA3_ULV_CNTL 30 30 RESERVED 31 31 mmSDMA3_PUB_REG_TYPE3 0 0x12 4 0 1 SDMA3_EA_DBIT_ADDR_DATA 0 0 SDMA3_EA_DBIT_ADDR_INDEX 1 1 SDMA3_GPU_IOV_VIOLATION_LOG2 2 2 RESERVED 3 31 mmSDMA3_MMHUB_CNTL 0 0x13 1 0 1 UNIT_ID 0 5 mmSDMA3_CONTEXT_GROUP_BOUNDARY 0 0x19 1 0 1 RESERVED 0 31 mmSDMA3_POWER_CNTL 0 0x1a 5 0 1 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 mmSDMA3_CLK_CTRL 0 0x1b 11 0 1 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmSDMA3_CNTL 0 0x1c 11 0 1 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 mmSDMA3_CHICKEN_BITS 0 0x1d 13 0 1 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 CE_AFIFO_WATERMARK 26 27 CE_DFIFO_WATERMARK 28 29 CE_LFIFO_WATERMARK 30 31 mmSDMA3_GB_ADDR_CONFIG 0 0x1e 5 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmSDMA3_GB_ADDR_CONFIG_READ 0 0x1f 5 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmSDMA3_RB_RPTR_FETCH_HI 0 0x20 1 0 1 OFFSET 0 31 mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0 0x21 1 0 1 TIMER 0 31 mmSDMA3_RB_RPTR_FETCH 0 0x22 1 0 1 OFFSET 2 31 mmSDMA3_IB_OFFSET_FETCH 0 0x23 1 0 1 OFFSET 2 21 mmSDMA3_PROGRAM 0 0x24 1 0 1 STREAM 0 31 mmSDMA3_STATUS_REG 0 0x25 29 0 1 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 mmSDMA3_STATUS1_REG 0 0x26 14 0 1 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 mmSDMA3_RD_BURST_CNTL 0 0x27 2 0 1 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 mmSDMA3_HBM_PAGE_CONFIG 0 0x28 1 0 1 PAGE_SIZE_EXPONENT 0 0 mmSDMA3_UCODE_CHECKSUM 0 0x29 1 0 1 DATA 0 31 mmSDMA3_F32_CNTL 0 0x2a 2 0 1 HALT 0 0 STEP 1 1 mmSDMA3_FREEZE 0 0x2b 4 0 1 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 mmSDMA3_PHASE0_QUANTUM 0 0x2c 3 0 1 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_PHASE1_QUANTUM 0 0x2d 3 0 1 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_EDC_CONFIG 0 0x32 2 0 1 DIS_EDC 1 1 ECC_INT_ENABLE 2 2 mmSDMA3_BA_THRESHOLD 0 0x33 2 0 1 READ_THRES 0 9 WRITE_THRES 16 25 mmSDMA3_ID 0 0x34 1 0 1 DEVICE_ID 0 7 mmSDMA3_VERSION 0 0x35 3 0 1 MINVER 0 6 MAJVER 8 14 REV 16 21 mmSDMA3_EDC_COUNTER 0 0x36 24 0 1 SDMA_UCODE_BUF_SED 0 0 SDMA_RB_CMD_BUF_SED 2 2 SDMA_IB_CMD_BUF_SED 3 3 SDMA_UTCL1_RD_FIFO_SED 4 4 SDMA_UTCL1_RDBST_FIFO_SED 5 5 SDMA_DATA_LUT_FIFO_SED 6 6 SDMA_MBANK_DATA_BUF0_SED 7 7 SDMA_MBANK_DATA_BUF1_SED 8 8 SDMA_MBANK_DATA_BUF2_SED 9 9 SDMA_MBANK_DATA_BUF3_SED 10 10 SDMA_MBANK_DATA_BUF4_SED 11 11 SDMA_MBANK_DATA_BUF5_SED 12 12 SDMA_MBANK_DATA_BUF6_SED 13 13 SDMA_MBANK_DATA_BUF7_SED 14 14 SDMA_MBANK_DATA_BUF8_SED 15 15 SDMA_MBANK_DATA_BUF9_SED 16 16 SDMA_MBANK_DATA_BUF10_SED 17 17 SDMA_MBANK_DATA_BUF11_SED 18 18 SDMA_MBANK_DATA_BUF12_SED 19 19 SDMA_MBANK_DATA_BUF13_SED 20 20 SDMA_MBANK_DATA_BUF14_SED 21 21 SDMA_MBANK_DATA_BUF15_SED 22 22 SDMA_SPLIT_DAT_BUF_SED 23 23 SDMA_MC_WR_ADDR_FIFO_SED 24 24 mmSDMA3_EDC_COUNTER_CLEAR 0 0x37 1 0 1 DUMMY 0 0 mmSDMA3_STATUS2_REG 0 0x38 3 0 1 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 mmSDMA3_ATOMIC_CNTL 0 0x39 2 0 1 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 mmSDMA3_ATOMIC_PREOP_LO 0 0x3a 1 0 1 DATA 0 31 mmSDMA3_ATOMIC_PREOP_HI 0 0x3b 1 0 1 DATA 0 31 mmSDMA3_UTCL1_CNTL 0 0x3c 6 0 1 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 mmSDMA3_UTCL1_WATERMK 0 0x3d 4 0 1 REQMC_WATERMK 0 8 REQPG_WATERMK 9 16 INVREQ_WATERMK 17 24 XNACK_WATERMK 25 31 mmSDMA3_UTCL1_RD_STATUS 0 0x3e 27 0 1 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 mmSDMA3_UTCL1_WR_STATUS 0 0x3f 28 0 1 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 mmSDMA3_UTCL1_INV0 0 0x40 14 0 1 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 mmSDMA3_UTCL1_INV1 0 0x41 1 0 1 INV_ADDR_LO 0 31 mmSDMA3_UTCL1_INV2 0 0x42 1 0 1 INV_NFLUSH_VMID_VEC 0 31 mmSDMA3_UTCL1_RD_XNACK0 0 0x43 1 0 1 XNACK_ADDR_LO 0 31 mmSDMA3_UTCL1_RD_XNACK1 0 0x44 4 0 1 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA3_UTCL1_WR_XNACK0 0 0x45 1 0 1 XNACK_ADDR_LO 0 31 mmSDMA3_UTCL1_WR_XNACK1 0 0x46 4 0 1 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 mmSDMA3_UTCL1_TIMEOUT 0 0x47 2 0 1 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 mmSDMA3_UTCL1_PAGE 0 0x48 4 0 1 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 mmSDMA3_POWER_CNTL_IDLE 0 0x49 3 0 1 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 mmSDMA3_RELAX_ORDERING_LUT 0 0x4a 19 0 1 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 mmSDMA3_CHICKEN_BITS_2 0 0x4b 1 0 1 F32_CMD_PROC_DELAY 0 3 mmSDMA3_STATUS3_REG 0 0x4c 5 0 1 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 mmSDMA3_PHYSICAL_ADDR_LO 0 0x4d 4 0 1 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 mmSDMA3_PHYSICAL_ADDR_HI 0 0x4e 1 0 1 ADDR 0 15 mmSDMA3_PHASE2_QUANTUM 0 0x4f 3 0 1 UNIT 0 3 VALUE 8 23 PREFER 30 30 mmSDMA3_ERROR_LOG 0 0x50 2 0 1 OVERRIDE 0 15 STATUS 16 31 mmSDMA3_PUB_DUMMY_REG0 0 0x51 1 0 1 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG1 0 0x52 1 0 1 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG2 0 0x53 1 0 1 VALUE 0 31 mmSDMA3_PUB_DUMMY_REG3 0 0x54 1 0 1 VALUE 0 31 mmSDMA3_F32_COUNTER 0 0x55 1 0 1 VALUE 0 31 mmSDMA3_UNBREAKABLE 0 0x56 1 0 1 VALUE 0 0 mmSDMA3_PERFMON_CNTL 0 0x57 6 0 1 PERF_ENABLE0 0 0 PERF_CLEAR0 1 1 PERF_SEL0 2 9 PERF_ENABLE1 10 10 PERF_CLEAR1 11 11 PERF_SEL1 12 19 mmSDMA3_PERFCOUNTER0_RESULT 0 0x58 1 0 1 PERF_COUNT 0 31 mmSDMA3_PERFCOUNTER1_RESULT 0 0x59 1 0 1 PERF_COUNT 0 31 mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE 0 0x5a 3 0 1 RANGE_LOW 0 13 RANGE_HIGH 14 27 SELECT_RW 28 28 mmSDMA3_CRD_CNTL 0 0x5b 2 0 1 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 mmSDMA3_GPU_IOV_VIOLATION_LOG 0 0x5d 6 0 1 VIOLATION_STATUS 0 0 MULTIPLE_VIOLATION_STATUS 1 1 ADDRESS 2 19 WRITE_OPERATION 20 20 VF 21 21 VFID 22 25 mmSDMA3_ULV_CNTL 0 0x5e 6 0 1 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 mmSDMA3_EA_DBIT_ADDR_DATA 0 0x60 1 0 1 VALUE 0 31 mmSDMA3_EA_DBIT_ADDR_INDEX 0 0x61 1 0 1 VALUE 0 2 mmSDMA3_GPU_IOV_VIOLATION_LOG2 0 0x62 1 0 1 INITIATOR_ID 0 7 mmSDMA3_GFX_RB_CNTL 0 0x80 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_GFX_RB_BASE 0 0x81 1 0 1 ADDR 0 31 mmSDMA3_GFX_RB_BASE_HI 0 0x82 1 0 1 ADDR 0 23 mmSDMA3_GFX_RB_RPTR 0 0x83 1 0 1 OFFSET 0 31 mmSDMA3_GFX_RB_RPTR_HI 0 0x84 1 0 1 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR 0 0x85 1 0 1 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR_HI 0 0x86 1 0 1 OFFSET 0 31 mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0 0x87 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_GFX_RB_RPTR_ADDR_HI 0 0x88 1 0 1 ADDR 0 31 mmSDMA3_GFX_RB_RPTR_ADDR_LO 0 0x89 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_GFX_IB_CNTL 0 0x8a 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_GFX_IB_RPTR 0 0x8b 1 0 1 OFFSET 2 21 mmSDMA3_GFX_IB_OFFSET 0 0x8c 1 0 1 OFFSET 2 21 mmSDMA3_GFX_IB_BASE_LO 0 0x8d 1 0 1 ADDR 5 31 mmSDMA3_GFX_IB_BASE_HI 0 0x8e 1 0 1 ADDR 0 31 mmSDMA3_GFX_IB_SIZE 0 0x8f 1 0 1 SIZE 0 19 mmSDMA3_GFX_SKIP_CNTL 0 0x90 1 0 1 SKIP_COUNT 0 19 mmSDMA3_GFX_CONTEXT_STATUS 0 0x91 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_GFX_DOORBELL 0 0x92 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_GFX_CONTEXT_CNTL 0 0x93 1 0 1 RESUME_CTX 16 16 mmSDMA3_GFX_STATUS 0 0xa8 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_GFX_DOORBELL_LOG 0 0xa9 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_GFX_WATERMARK 0 0xaa 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_GFX_DOORBELL_OFFSET 0 0xab 1 0 1 OFFSET 2 27 mmSDMA3_GFX_CSA_ADDR_LO 0 0xac 1 0 1 ADDR 2 31 mmSDMA3_GFX_CSA_ADDR_HI 0 0xad 1 0 1 ADDR 0 31 mmSDMA3_GFX_IB_SUB_REMAIN 0 0xaf 1 0 1 SIZE 0 19 mmSDMA3_GFX_PREEMPT 0 0xb0 1 0 1 IB_PREEMPT 0 0 mmSDMA3_GFX_DUMMY_REG 0 0xb1 1 0 1 DUMMY 0 31 mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0 0xb2 1 0 1 ADDR 0 31 mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0 0xb3 1 0 1 ADDR 2 31 mmSDMA3_GFX_RB_AQL_CNTL 0 0xb4 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_GFX_MINOR_PTR_UPDATE 0 0xb5 1 0 1 ENABLE 0 0 mmSDMA3_GFX_MIDCMD_DATA0 0 0xc0 1 0 1 DATA0 0 31 mmSDMA3_GFX_MIDCMD_DATA1 0 0xc1 1 0 1 DATA1 0 31 mmSDMA3_GFX_MIDCMD_DATA2 0 0xc2 1 0 1 DATA2 0 31 mmSDMA3_GFX_MIDCMD_DATA3 0 0xc3 1 0 1 DATA3 0 31 mmSDMA3_GFX_MIDCMD_DATA4 0 0xc4 1 0 1 DATA4 0 31 mmSDMA3_GFX_MIDCMD_DATA5 0 0xc5 1 0 1 DATA5 0 31 mmSDMA3_GFX_MIDCMD_DATA6 0 0xc6 1 0 1 DATA6 0 31 mmSDMA3_GFX_MIDCMD_DATA7 0 0xc7 1 0 1 DATA7 0 31 mmSDMA3_GFX_MIDCMD_DATA8 0 0xc8 1 0 1 DATA8 0 31 mmSDMA3_GFX_MIDCMD_CNTL 0 0xc9 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_PAGE_RB_CNTL 0 0xd8 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_PAGE_RB_BASE 0 0xd9 1 0 1 ADDR 0 31 mmSDMA3_PAGE_RB_BASE_HI 0 0xda 1 0 1 ADDR 0 23 mmSDMA3_PAGE_RB_RPTR 0 0xdb 1 0 1 OFFSET 0 31 mmSDMA3_PAGE_RB_RPTR_HI 0 0xdc 1 0 1 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR 0 0xdd 1 0 1 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR_HI 0 0xde 1 0 1 OFFSET 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0 0xdf 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0 0xe0 1 0 1 ADDR 0 31 mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0 0xe1 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_PAGE_IB_CNTL 0 0xe2 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_PAGE_IB_RPTR 0 0xe3 1 0 1 OFFSET 2 21 mmSDMA3_PAGE_IB_OFFSET 0 0xe4 1 0 1 OFFSET 2 21 mmSDMA3_PAGE_IB_BASE_LO 0 0xe5 1 0 1 ADDR 5 31 mmSDMA3_PAGE_IB_BASE_HI 0 0xe6 1 0 1 ADDR 0 31 mmSDMA3_PAGE_IB_SIZE 0 0xe7 1 0 1 SIZE 0 19 mmSDMA3_PAGE_SKIP_CNTL 0 0xe8 1 0 1 SKIP_COUNT 0 19 mmSDMA3_PAGE_CONTEXT_STATUS 0 0xe9 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_PAGE_DOORBELL 0 0xea 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_PAGE_STATUS 0 0x100 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_PAGE_DOORBELL_LOG 0 0x101 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_PAGE_WATERMARK 0 0x102 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_PAGE_DOORBELL_OFFSET 0 0x103 1 0 1 OFFSET 2 27 mmSDMA3_PAGE_CSA_ADDR_LO 0 0x104 1 0 1 ADDR 2 31 mmSDMA3_PAGE_CSA_ADDR_HI 0 0x105 1 0 1 ADDR 0 31 mmSDMA3_PAGE_IB_SUB_REMAIN 0 0x107 1 0 1 SIZE 0 19 mmSDMA3_PAGE_PREEMPT 0 0x108 1 0 1 IB_PREEMPT 0 0 mmSDMA3_PAGE_DUMMY_REG 0 0x109 1 0 1 DUMMY 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x10a 1 0 1 ADDR 0 31 mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x10b 1 0 1 ADDR 2 31 mmSDMA3_PAGE_RB_AQL_CNTL 0 0x10c 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_PAGE_MINOR_PTR_UPDATE 0 0x10d 1 0 1 ENABLE 0 0 mmSDMA3_PAGE_MIDCMD_DATA0 0 0x118 1 0 1 DATA0 0 31 mmSDMA3_PAGE_MIDCMD_DATA1 0 0x119 1 0 1 DATA1 0 31 mmSDMA3_PAGE_MIDCMD_DATA2 0 0x11a 1 0 1 DATA2 0 31 mmSDMA3_PAGE_MIDCMD_DATA3 0 0x11b 1 0 1 DATA3 0 31 mmSDMA3_PAGE_MIDCMD_DATA4 0 0x11c 1 0 1 DATA4 0 31 mmSDMA3_PAGE_MIDCMD_DATA5 0 0x11d 1 0 1 DATA5 0 31 mmSDMA3_PAGE_MIDCMD_DATA6 0 0x11e 1 0 1 DATA6 0 31 mmSDMA3_PAGE_MIDCMD_DATA7 0 0x11f 1 0 1 DATA7 0 31 mmSDMA3_PAGE_MIDCMD_DATA8 0 0x120 1 0 1 DATA8 0 31 mmSDMA3_PAGE_MIDCMD_CNTL 0 0x121 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC0_RB_CNTL 0 0x130 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC0_RB_BASE 0 0x131 1 0 1 ADDR 0 31 mmSDMA3_RLC0_RB_BASE_HI 0 0x132 1 0 1 ADDR 0 23 mmSDMA3_RLC0_RB_RPTR 0 0x133 1 0 1 OFFSET 0 31 mmSDMA3_RLC0_RB_RPTR_HI 0 0x134 1 0 1 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR 0 0x135 1 0 1 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR_HI 0 0x136 1 0 1 OFFSET 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0 0x137 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0 0x138 1 0 1 ADDR 0 31 mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0 0x139 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC0_IB_CNTL 0 0x13a 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC0_IB_RPTR 0 0x13b 1 0 1 OFFSET 2 21 mmSDMA3_RLC0_IB_OFFSET 0 0x13c 1 0 1 OFFSET 2 21 mmSDMA3_RLC0_IB_BASE_LO 0 0x13d 1 0 1 ADDR 5 31 mmSDMA3_RLC0_IB_BASE_HI 0 0x13e 1 0 1 ADDR 0 31 mmSDMA3_RLC0_IB_SIZE 0 0x13f 1 0 1 SIZE 0 19 mmSDMA3_RLC0_SKIP_CNTL 0 0x140 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC0_CONTEXT_STATUS 0 0x141 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC0_DOORBELL 0 0x142 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC0_STATUS 0 0x158 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC0_DOORBELL_LOG 0 0x159 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC0_WATERMARK 0 0x15a 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC0_DOORBELL_OFFSET 0 0x15b 1 0 1 OFFSET 2 27 mmSDMA3_RLC0_CSA_ADDR_LO 0 0x15c 1 0 1 ADDR 2 31 mmSDMA3_RLC0_CSA_ADDR_HI 0 0x15d 1 0 1 ADDR 0 31 mmSDMA3_RLC0_IB_SUB_REMAIN 0 0x15f 1 0 1 SIZE 0 19 mmSDMA3_RLC0_PREEMPT 0 0x160 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC0_DUMMY_REG 0 0x161 1 0 1 DUMMY 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x162 1 0 1 ADDR 0 31 mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x163 1 0 1 ADDR 2 31 mmSDMA3_RLC0_RB_AQL_CNTL 0 0x164 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC0_MINOR_PTR_UPDATE 0 0x165 1 0 1 ENABLE 0 0 mmSDMA3_RLC0_MIDCMD_DATA0 0 0x170 1 0 1 DATA0 0 31 mmSDMA3_RLC0_MIDCMD_DATA1 0 0x171 1 0 1 DATA1 0 31 mmSDMA3_RLC0_MIDCMD_DATA2 0 0x172 1 0 1 DATA2 0 31 mmSDMA3_RLC0_MIDCMD_DATA3 0 0x173 1 0 1 DATA3 0 31 mmSDMA3_RLC0_MIDCMD_DATA4 0 0x174 1 0 1 DATA4 0 31 mmSDMA3_RLC0_MIDCMD_DATA5 0 0x175 1 0 1 DATA5 0 31 mmSDMA3_RLC0_MIDCMD_DATA6 0 0x176 1 0 1 DATA6 0 31 mmSDMA3_RLC0_MIDCMD_DATA7 0 0x177 1 0 1 DATA7 0 31 mmSDMA3_RLC0_MIDCMD_DATA8 0 0x178 1 0 1 DATA8 0 31 mmSDMA3_RLC0_MIDCMD_CNTL 0 0x179 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC1_RB_CNTL 0 0x188 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC1_RB_BASE 0 0x189 1 0 1 ADDR 0 31 mmSDMA3_RLC1_RB_BASE_HI 0 0x18a 1 0 1 ADDR 0 23 mmSDMA3_RLC1_RB_RPTR 0 0x18b 1 0 1 OFFSET 0 31 mmSDMA3_RLC1_RB_RPTR_HI 0 0x18c 1 0 1 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR 0 0x18d 1 0 1 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR_HI 0 0x18e 1 0 1 OFFSET 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0 0x18f 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0 0x190 1 0 1 ADDR 0 31 mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0 0x191 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC1_IB_CNTL 0 0x192 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC1_IB_RPTR 0 0x193 1 0 1 OFFSET 2 21 mmSDMA3_RLC1_IB_OFFSET 0 0x194 1 0 1 OFFSET 2 21 mmSDMA3_RLC1_IB_BASE_LO 0 0x195 1 0 1 ADDR 5 31 mmSDMA3_RLC1_IB_BASE_HI 0 0x196 1 0 1 ADDR 0 31 mmSDMA3_RLC1_IB_SIZE 0 0x197 1 0 1 SIZE 0 19 mmSDMA3_RLC1_SKIP_CNTL 0 0x198 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC1_CONTEXT_STATUS 0 0x199 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC1_DOORBELL 0 0x19a 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC1_STATUS 0 0x1b0 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC1_DOORBELL_LOG 0 0x1b1 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC1_WATERMARK 0 0x1b2 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC1_DOORBELL_OFFSET 0 0x1b3 1 0 1 OFFSET 2 27 mmSDMA3_RLC1_CSA_ADDR_LO 0 0x1b4 1 0 1 ADDR 2 31 mmSDMA3_RLC1_CSA_ADDR_HI 0 0x1b5 1 0 1 ADDR 0 31 mmSDMA3_RLC1_IB_SUB_REMAIN 0 0x1b7 1 0 1 SIZE 0 19 mmSDMA3_RLC1_PREEMPT 0 0x1b8 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC1_DUMMY_REG 0 0x1b9 1 0 1 DUMMY 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1ba 1 0 1 ADDR 0 31 mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1bb 1 0 1 ADDR 2 31 mmSDMA3_RLC1_RB_AQL_CNTL 0 0x1bc 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC1_MINOR_PTR_UPDATE 0 0x1bd 1 0 1 ENABLE 0 0 mmSDMA3_RLC1_MIDCMD_DATA0 0 0x1c8 1 0 1 DATA0 0 31 mmSDMA3_RLC1_MIDCMD_DATA1 0 0x1c9 1 0 1 DATA1 0 31 mmSDMA3_RLC1_MIDCMD_DATA2 0 0x1ca 1 0 1 DATA2 0 31 mmSDMA3_RLC1_MIDCMD_DATA3 0 0x1cb 1 0 1 DATA3 0 31 mmSDMA3_RLC1_MIDCMD_DATA4 0 0x1cc 1 0 1 DATA4 0 31 mmSDMA3_RLC1_MIDCMD_DATA5 0 0x1cd 1 0 1 DATA5 0 31 mmSDMA3_RLC1_MIDCMD_DATA6 0 0x1ce 1 0 1 DATA6 0 31 mmSDMA3_RLC1_MIDCMD_DATA7 0 0x1cf 1 0 1 DATA7 0 31 mmSDMA3_RLC1_MIDCMD_DATA8 0 0x1d0 1 0 1 DATA8 0 31 mmSDMA3_RLC1_MIDCMD_CNTL 0 0x1d1 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC2_RB_CNTL 0 0x1e0 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC2_RB_BASE 0 0x1e1 1 0 1 ADDR 0 31 mmSDMA3_RLC2_RB_BASE_HI 0 0x1e2 1 0 1 ADDR 0 23 mmSDMA3_RLC2_RB_RPTR 0 0x1e3 1 0 1 OFFSET 0 31 mmSDMA3_RLC2_RB_RPTR_HI 0 0x1e4 1 0 1 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR 0 0x1e5 1 0 1 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR_HI 0 0x1e6 1 0 1 OFFSET 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0 0x1e7 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0 0x1e8 1 0 1 ADDR 0 31 mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0 0x1e9 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC2_IB_CNTL 0 0x1ea 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC2_IB_RPTR 0 0x1eb 1 0 1 OFFSET 2 21 mmSDMA3_RLC2_IB_OFFSET 0 0x1ec 1 0 1 OFFSET 2 21 mmSDMA3_RLC2_IB_BASE_LO 0 0x1ed 1 0 1 ADDR 5 31 mmSDMA3_RLC2_IB_BASE_HI 0 0x1ee 1 0 1 ADDR 0 31 mmSDMA3_RLC2_IB_SIZE 0 0x1ef 1 0 1 SIZE 0 19 mmSDMA3_RLC2_SKIP_CNTL 0 0x1f0 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC2_CONTEXT_STATUS 0 0x1f1 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC2_DOORBELL 0 0x1f2 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC2_STATUS 0 0x208 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC2_DOORBELL_LOG 0 0x209 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC2_WATERMARK 0 0x20a 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC2_DOORBELL_OFFSET 0 0x20b 1 0 1 OFFSET 2 27 mmSDMA3_RLC2_CSA_ADDR_LO 0 0x20c 1 0 1 ADDR 2 31 mmSDMA3_RLC2_CSA_ADDR_HI 0 0x20d 1 0 1 ADDR 0 31 mmSDMA3_RLC2_IB_SUB_REMAIN 0 0x20f 1 0 1 SIZE 0 19 mmSDMA3_RLC2_PREEMPT 0 0x210 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC2_DUMMY_REG 0 0x211 1 0 1 DUMMY 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x212 1 0 1 ADDR 0 31 mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x213 1 0 1 ADDR 2 31 mmSDMA3_RLC2_RB_AQL_CNTL 0 0x214 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC2_MINOR_PTR_UPDATE 0 0x215 1 0 1 ENABLE 0 0 mmSDMA3_RLC2_MIDCMD_DATA0 0 0x220 1 0 1 DATA0 0 31 mmSDMA3_RLC2_MIDCMD_DATA1 0 0x221 1 0 1 DATA1 0 31 mmSDMA3_RLC2_MIDCMD_DATA2 0 0x222 1 0 1 DATA2 0 31 mmSDMA3_RLC2_MIDCMD_DATA3 0 0x223 1 0 1 DATA3 0 31 mmSDMA3_RLC2_MIDCMD_DATA4 0 0x224 1 0 1 DATA4 0 31 mmSDMA3_RLC2_MIDCMD_DATA5 0 0x225 1 0 1 DATA5 0 31 mmSDMA3_RLC2_MIDCMD_DATA6 0 0x226 1 0 1 DATA6 0 31 mmSDMA3_RLC2_MIDCMD_DATA7 0 0x227 1 0 1 DATA7 0 31 mmSDMA3_RLC2_MIDCMD_DATA8 0 0x228 1 0 1 DATA8 0 31 mmSDMA3_RLC2_MIDCMD_CNTL 0 0x229 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC3_RB_CNTL 0 0x238 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC3_RB_BASE 0 0x239 1 0 1 ADDR 0 31 mmSDMA3_RLC3_RB_BASE_HI 0 0x23a 1 0 1 ADDR 0 23 mmSDMA3_RLC3_RB_RPTR 0 0x23b 1 0 1 OFFSET 0 31 mmSDMA3_RLC3_RB_RPTR_HI 0 0x23c 1 0 1 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR 0 0x23d 1 0 1 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR_HI 0 0x23e 1 0 1 OFFSET 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0 0x23f 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0 0x240 1 0 1 ADDR 0 31 mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0 0x241 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC3_IB_CNTL 0 0x242 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC3_IB_RPTR 0 0x243 1 0 1 OFFSET 2 21 mmSDMA3_RLC3_IB_OFFSET 0 0x244 1 0 1 OFFSET 2 21 mmSDMA3_RLC3_IB_BASE_LO 0 0x245 1 0 1 ADDR 5 31 mmSDMA3_RLC3_IB_BASE_HI 0 0x246 1 0 1 ADDR 0 31 mmSDMA3_RLC3_IB_SIZE 0 0x247 1 0 1 SIZE 0 19 mmSDMA3_RLC3_SKIP_CNTL 0 0x248 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC3_CONTEXT_STATUS 0 0x249 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC3_DOORBELL 0 0x24a 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC3_STATUS 0 0x260 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC3_DOORBELL_LOG 0 0x261 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC3_WATERMARK 0 0x262 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC3_DOORBELL_OFFSET 0 0x263 1 0 1 OFFSET 2 27 mmSDMA3_RLC3_CSA_ADDR_LO 0 0x264 1 0 1 ADDR 2 31 mmSDMA3_RLC3_CSA_ADDR_HI 0 0x265 1 0 1 ADDR 0 31 mmSDMA3_RLC3_IB_SUB_REMAIN 0 0x267 1 0 1 SIZE 0 19 mmSDMA3_RLC3_PREEMPT 0 0x268 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC3_DUMMY_REG 0 0x269 1 0 1 DUMMY 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x26a 1 0 1 ADDR 0 31 mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x26b 1 0 1 ADDR 2 31 mmSDMA3_RLC3_RB_AQL_CNTL 0 0x26c 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC3_MINOR_PTR_UPDATE 0 0x26d 1 0 1 ENABLE 0 0 mmSDMA3_RLC3_MIDCMD_DATA0 0 0x278 1 0 1 DATA0 0 31 mmSDMA3_RLC3_MIDCMD_DATA1 0 0x279 1 0 1 DATA1 0 31 mmSDMA3_RLC3_MIDCMD_DATA2 0 0x27a 1 0 1 DATA2 0 31 mmSDMA3_RLC3_MIDCMD_DATA3 0 0x27b 1 0 1 DATA3 0 31 mmSDMA3_RLC3_MIDCMD_DATA4 0 0x27c 1 0 1 DATA4 0 31 mmSDMA3_RLC3_MIDCMD_DATA5 0 0x27d 1 0 1 DATA5 0 31 mmSDMA3_RLC3_MIDCMD_DATA6 0 0x27e 1 0 1 DATA6 0 31 mmSDMA3_RLC3_MIDCMD_DATA7 0 0x27f 1 0 1 DATA7 0 31 mmSDMA3_RLC3_MIDCMD_DATA8 0 0x280 1 0 1 DATA8 0 31 mmSDMA3_RLC3_MIDCMD_CNTL 0 0x281 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC4_RB_CNTL 0 0x290 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC4_RB_BASE 0 0x291 1 0 1 ADDR 0 31 mmSDMA3_RLC4_RB_BASE_HI 0 0x292 1 0 1 ADDR 0 23 mmSDMA3_RLC4_RB_RPTR 0 0x293 1 0 1 OFFSET 0 31 mmSDMA3_RLC4_RB_RPTR_HI 0 0x294 1 0 1 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR 0 0x295 1 0 1 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR_HI 0 0x296 1 0 1 OFFSET 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0 0x297 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0 0x298 1 0 1 ADDR 0 31 mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0 0x299 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC4_IB_CNTL 0 0x29a 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC4_IB_RPTR 0 0x29b 1 0 1 OFFSET 2 21 mmSDMA3_RLC4_IB_OFFSET 0 0x29c 1 0 1 OFFSET 2 21 mmSDMA3_RLC4_IB_BASE_LO 0 0x29d 1 0 1 ADDR 5 31 mmSDMA3_RLC4_IB_BASE_HI 0 0x29e 1 0 1 ADDR 0 31 mmSDMA3_RLC4_IB_SIZE 0 0x29f 1 0 1 SIZE 0 19 mmSDMA3_RLC4_SKIP_CNTL 0 0x2a0 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC4_CONTEXT_STATUS 0 0x2a1 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC4_DOORBELL 0 0x2a2 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC4_STATUS 0 0x2b8 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC4_DOORBELL_LOG 0 0x2b9 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC4_WATERMARK 0 0x2ba 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC4_DOORBELL_OFFSET 0 0x2bb 1 0 1 OFFSET 2 27 mmSDMA3_RLC4_CSA_ADDR_LO 0 0x2bc 1 0 1 ADDR 2 31 mmSDMA3_RLC4_CSA_ADDR_HI 0 0x2bd 1 0 1 ADDR 0 31 mmSDMA3_RLC4_IB_SUB_REMAIN 0 0x2bf 1 0 1 SIZE 0 19 mmSDMA3_RLC4_PREEMPT 0 0x2c0 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC4_DUMMY_REG 0 0x2c1 1 0 1 DUMMY 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x2c2 1 0 1 ADDR 0 31 mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x2c3 1 0 1 ADDR 2 31 mmSDMA3_RLC4_RB_AQL_CNTL 0 0x2c4 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC4_MINOR_PTR_UPDATE 0 0x2c5 1 0 1 ENABLE 0 0 mmSDMA3_RLC4_MIDCMD_DATA0 0 0x2d0 1 0 1 DATA0 0 31 mmSDMA3_RLC4_MIDCMD_DATA1 0 0x2d1 1 0 1 DATA1 0 31 mmSDMA3_RLC4_MIDCMD_DATA2 0 0x2d2 1 0 1 DATA2 0 31 mmSDMA3_RLC4_MIDCMD_DATA3 0 0x2d3 1 0 1 DATA3 0 31 mmSDMA3_RLC4_MIDCMD_DATA4 0 0x2d4 1 0 1 DATA4 0 31 mmSDMA3_RLC4_MIDCMD_DATA5 0 0x2d5 1 0 1 DATA5 0 31 mmSDMA3_RLC4_MIDCMD_DATA6 0 0x2d6 1 0 1 DATA6 0 31 mmSDMA3_RLC4_MIDCMD_DATA7 0 0x2d7 1 0 1 DATA7 0 31 mmSDMA3_RLC4_MIDCMD_DATA8 0 0x2d8 1 0 1 DATA8 0 31 mmSDMA3_RLC4_MIDCMD_CNTL 0 0x2d9 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC5_RB_CNTL 0 0x2e8 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC5_RB_BASE 0 0x2e9 1 0 1 ADDR 0 31 mmSDMA3_RLC5_RB_BASE_HI 0 0x2ea 1 0 1 ADDR 0 23 mmSDMA3_RLC5_RB_RPTR 0 0x2eb 1 0 1 OFFSET 0 31 mmSDMA3_RLC5_RB_RPTR_HI 0 0x2ec 1 0 1 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR 0 0x2ed 1 0 1 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR_HI 0 0x2ee 1 0 1 OFFSET 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0 0x2ef 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0 0x2f0 1 0 1 ADDR 0 31 mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0 0x2f1 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC5_IB_CNTL 0 0x2f2 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC5_IB_RPTR 0 0x2f3 1 0 1 OFFSET 2 21 mmSDMA3_RLC5_IB_OFFSET 0 0x2f4 1 0 1 OFFSET 2 21 mmSDMA3_RLC5_IB_BASE_LO 0 0x2f5 1 0 1 ADDR 5 31 mmSDMA3_RLC5_IB_BASE_HI 0 0x2f6 1 0 1 ADDR 0 31 mmSDMA3_RLC5_IB_SIZE 0 0x2f7 1 0 1 SIZE 0 19 mmSDMA3_RLC5_SKIP_CNTL 0 0x2f8 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC5_CONTEXT_STATUS 0 0x2f9 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC5_DOORBELL 0 0x2fa 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC5_STATUS 0 0x310 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC5_DOORBELL_LOG 0 0x311 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC5_WATERMARK 0 0x312 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC5_DOORBELL_OFFSET 0 0x313 1 0 1 OFFSET 2 27 mmSDMA3_RLC5_CSA_ADDR_LO 0 0x314 1 0 1 ADDR 2 31 mmSDMA3_RLC5_CSA_ADDR_HI 0 0x315 1 0 1 ADDR 0 31 mmSDMA3_RLC5_IB_SUB_REMAIN 0 0x317 1 0 1 SIZE 0 19 mmSDMA3_RLC5_PREEMPT 0 0x318 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC5_DUMMY_REG 0 0x319 1 0 1 DUMMY 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x31a 1 0 1 ADDR 0 31 mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x31b 1 0 1 ADDR 2 31 mmSDMA3_RLC5_RB_AQL_CNTL 0 0x31c 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC5_MINOR_PTR_UPDATE 0 0x31d 1 0 1 ENABLE 0 0 mmSDMA3_RLC5_MIDCMD_DATA0 0 0x328 1 0 1 DATA0 0 31 mmSDMA3_RLC5_MIDCMD_DATA1 0 0x329 1 0 1 DATA1 0 31 mmSDMA3_RLC5_MIDCMD_DATA2 0 0x32a 1 0 1 DATA2 0 31 mmSDMA3_RLC5_MIDCMD_DATA3 0 0x32b 1 0 1 DATA3 0 31 mmSDMA3_RLC5_MIDCMD_DATA4 0 0x32c 1 0 1 DATA4 0 31 mmSDMA3_RLC5_MIDCMD_DATA5 0 0x32d 1 0 1 DATA5 0 31 mmSDMA3_RLC5_MIDCMD_DATA6 0 0x32e 1 0 1 DATA6 0 31 mmSDMA3_RLC5_MIDCMD_DATA7 0 0x32f 1 0 1 DATA7 0 31 mmSDMA3_RLC5_MIDCMD_DATA8 0 0x330 1 0 1 DATA8 0 31 mmSDMA3_RLC5_MIDCMD_CNTL 0 0x331 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC6_RB_CNTL 0 0x340 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC6_RB_BASE 0 0x341 1 0 1 ADDR 0 31 mmSDMA3_RLC6_RB_BASE_HI 0 0x342 1 0 1 ADDR 0 23 mmSDMA3_RLC6_RB_RPTR 0 0x343 1 0 1 OFFSET 0 31 mmSDMA3_RLC6_RB_RPTR_HI 0 0x344 1 0 1 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR 0 0x345 1 0 1 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR_HI 0 0x346 1 0 1 OFFSET 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0 0x347 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0 0x348 1 0 1 ADDR 0 31 mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0 0x349 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC6_IB_CNTL 0 0x34a 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC6_IB_RPTR 0 0x34b 1 0 1 OFFSET 2 21 mmSDMA3_RLC6_IB_OFFSET 0 0x34c 1 0 1 OFFSET 2 21 mmSDMA3_RLC6_IB_BASE_LO 0 0x34d 1 0 1 ADDR 5 31 mmSDMA3_RLC6_IB_BASE_HI 0 0x34e 1 0 1 ADDR 0 31 mmSDMA3_RLC6_IB_SIZE 0 0x34f 1 0 1 SIZE 0 19 mmSDMA3_RLC6_SKIP_CNTL 0 0x350 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC6_CONTEXT_STATUS 0 0x351 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC6_DOORBELL 0 0x352 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC6_STATUS 0 0x368 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC6_DOORBELL_LOG 0 0x369 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC6_WATERMARK 0 0x36a 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC6_DOORBELL_OFFSET 0 0x36b 1 0 1 OFFSET 2 27 mmSDMA3_RLC6_CSA_ADDR_LO 0 0x36c 1 0 1 ADDR 2 31 mmSDMA3_RLC6_CSA_ADDR_HI 0 0x36d 1 0 1 ADDR 0 31 mmSDMA3_RLC6_IB_SUB_REMAIN 0 0x36f 1 0 1 SIZE 0 19 mmSDMA3_RLC6_PREEMPT 0 0x370 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC6_DUMMY_REG 0 0x371 1 0 1 DUMMY 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x372 1 0 1 ADDR 0 31 mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x373 1 0 1 ADDR 2 31 mmSDMA3_RLC6_RB_AQL_CNTL 0 0x374 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC6_MINOR_PTR_UPDATE 0 0x375 1 0 1 ENABLE 0 0 mmSDMA3_RLC6_MIDCMD_DATA0 0 0x380 1 0 1 DATA0 0 31 mmSDMA3_RLC6_MIDCMD_DATA1 0 0x381 1 0 1 DATA1 0 31 mmSDMA3_RLC6_MIDCMD_DATA2 0 0x382 1 0 1 DATA2 0 31 mmSDMA3_RLC6_MIDCMD_DATA3 0 0x383 1 0 1 DATA3 0 31 mmSDMA3_RLC6_MIDCMD_DATA4 0 0x384 1 0 1 DATA4 0 31 mmSDMA3_RLC6_MIDCMD_DATA5 0 0x385 1 0 1 DATA5 0 31 mmSDMA3_RLC6_MIDCMD_DATA6 0 0x386 1 0 1 DATA6 0 31 mmSDMA3_RLC6_MIDCMD_DATA7 0 0x387 1 0 1 DATA7 0 31 mmSDMA3_RLC6_MIDCMD_DATA8 0 0x388 1 0 1 DATA8 0 31 mmSDMA3_RLC6_MIDCMD_CNTL 0 0x389 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 mmSDMA3_RLC7_RB_CNTL 0 0x398 8 0 1 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 mmSDMA3_RLC7_RB_BASE 0 0x399 1 0 1 ADDR 0 31 mmSDMA3_RLC7_RB_BASE_HI 0 0x39a 1 0 1 ADDR 0 23 mmSDMA3_RLC7_RB_RPTR 0 0x39b 1 0 1 OFFSET 0 31 mmSDMA3_RLC7_RB_RPTR_HI 0 0x39c 1 0 1 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR 0 0x39d 1 0 1 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR_HI 0 0x39e 1 0 1 OFFSET 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0 0x39f 5 0 1 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0 0x3a0 1 0 1 ADDR 0 31 mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0 0x3a1 2 0 1 RPTR_WB_IDLE 0 0 ADDR 2 31 mmSDMA3_RLC7_IB_CNTL 0 0x3a2 4 0 1 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 mmSDMA3_RLC7_IB_RPTR 0 0x3a3 1 0 1 OFFSET 2 21 mmSDMA3_RLC7_IB_OFFSET 0 0x3a4 1 0 1 OFFSET 2 21 mmSDMA3_RLC7_IB_BASE_LO 0 0x3a5 1 0 1 ADDR 5 31 mmSDMA3_RLC7_IB_BASE_HI 0 0x3a6 1 0 1 ADDR 0 31 mmSDMA3_RLC7_IB_SIZE 0 0x3a7 1 0 1 SIZE 0 19 mmSDMA3_RLC7_SKIP_CNTL 0 0x3a8 1 0 1 SKIP_COUNT 0 19 mmSDMA3_RLC7_CONTEXT_STATUS 0 0x3a9 8 0 1 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 mmSDMA3_RLC7_DOORBELL 0 0x3aa 2 0 1 ENABLE 28 28 CAPTURED 30 30 mmSDMA3_RLC7_STATUS 0 0x3c0 2 0 1 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 mmSDMA3_RLC7_DOORBELL_LOG 0 0x3c1 2 0 1 BE_ERROR 0 0 DATA 2 31 mmSDMA3_RLC7_WATERMARK 0 0x3c2 2 0 1 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 mmSDMA3_RLC7_DOORBELL_OFFSET 0 0x3c3 1 0 1 OFFSET 2 27 mmSDMA3_RLC7_CSA_ADDR_LO 0 0x3c4 1 0 1 ADDR 2 31 mmSDMA3_RLC7_CSA_ADDR_HI 0 0x3c5 1 0 1 ADDR 0 31 mmSDMA3_RLC7_IB_SUB_REMAIN 0 0x3c7 1 0 1 SIZE 0 19 mmSDMA3_RLC7_PREEMPT 0 0x3c8 1 0 1 IB_PREEMPT 0 0 mmSDMA3_RLC7_DUMMY_REG 0 0x3c9 1 0 1 DUMMY 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x3ca 1 0 1 ADDR 0 31 mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x3cb 1 0 1 ADDR 2 31 mmSDMA3_RLC7_RB_AQL_CNTL 0 0x3cc 3 0 1 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 mmSDMA3_RLC7_MINOR_PTR_UPDATE 0 0x3cd 1 0 1 ENABLE 0 0 mmSDMA3_RLC7_MIDCMD_DATA0 0 0x3d8 1 0 1 DATA0 0 31 mmSDMA3_RLC7_MIDCMD_DATA1 0 0x3d9 1 0 1 DATA1 0 31 mmSDMA3_RLC7_MIDCMD_DATA2 0 0x3da 1 0 1 DATA2 0 31 mmSDMA3_RLC7_MIDCMD_DATA3 0 0x3db 1 0 1 DATA3 0 31 mmSDMA3_RLC7_MIDCMD_DATA4 0 0x3dc 1 0 1 DATA4 0 31 mmSDMA3_RLC7_MIDCMD_DATA5 0 0x3dd 1 0 1 DATA5 0 31 mmSDMA3_RLC7_MIDCMD_DATA6 0 0x3de 1 0 1 DATA6 0 31 mmSDMA3_RLC7_MIDCMD_DATA7 0 0x3df 1 0 1 DATA7 0 31 mmSDMA3_RLC7_MIDCMD_DATA8 0 0x3e0 1 0 1 DATA8 0 31 mmSDMA3_RLC7_MIDCMD_CNTL 0 0x3e1 4 0 1 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8