2589 regSDMA0_UCODE_ADDR 0 0x0 1 0 0 VALUE 0 13 regSDMA0_UCODE_DATA 0 0x1 1 0 0 VALUE 0 31 regSDMA0_VF_ENABLE 0 0xa 1 0 0 VF_ENABLE 0 0 regSDMA0_CONTEXT_GROUP_BOUNDARY 0 0x19 1 0 0 RESERVED 0 31 regSDMA0_POWER_CNTL 0 0x1a 10 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 ON_OFF_STATUS_DURATION_TIME 26 31 regSDMA0_CLK_CTRL 0 0x1b 11 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSDMA0_CNTL 0 0x1c 12 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_EXPIRE_ENABLE 6 6 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 regSDMA0_CHICKEN_BITS 0 0x1d 12 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 SRAM_FGCG_ENABLE 26 26 RESERVED 27 31 regSDMA0_GB_ADDR_CONFIG 0 0x1e 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA0_GB_ADDR_CONFIG_READ 0 0x1f 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA0_RB_RPTR_FETCH_HI 0 0x20 1 0 0 OFFSET 0 31 regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0 0x21 1 0 0 TIMER 0 31 regSDMA0_RB_RPTR_FETCH 0 0x22 1 0 0 OFFSET 2 31 regSDMA0_IB_OFFSET_FETCH 0 0x23 1 0 0 OFFSET 2 21 regSDMA0_PROGRAM 0 0x24 1 0 0 STREAM 0 31 regSDMA0_STATUS_REG 0 0x25 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 regSDMA0_STATUS1_REG 0 0x26 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 regSDMA0_RD_BURST_CNTL 0 0x27 2 0 0 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 regSDMA0_HBM_PAGE_CONFIG 0 0x28 1 0 0 PAGE_SIZE_EXPONENT 0 1 regSDMA0_UCODE_CHECKSUM 0 0x29 1 0 0 DATA 0 31 regSDMA0_F32_CNTL 0 0x2a 3 0 0 HALT 0 0 STEP 1 1 RESET 8 8 regSDMA0_FREEZE 0 0x2b 4 0 0 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 regSDMA0_PHASE0_QUANTUM 0 0x2c 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA0_PHASE1_QUANTUM 0 0x2d 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA_POWER_GATING 0 0x2e 5 0 0 SDMA0_POWER_OFF_CONDITION 0 0 SDMA0_POWER_ON_CONDITION 1 1 SDMA0_POWER_OFF_REQ 2 2 SDMA0_POWER_ON_REQ 3 3 PG_CNTL_STATUS 4 5 regSDMA_PGFSM_CONFIG 0 0x2f 9 0 0 FSM_ADDR 0 7 POWER_DOWN 8 8 POWER_UP 9 9 P1_SELECT 10 10 P2_SELECT 11 11 WRITE 12 12 READ 13 13 SRBM_OVERRIDE 27 27 REG_ADDR 28 31 regSDMA_PGFSM_WRITE 0 0x30 1 0 0 VALUE 0 31 regSDMA_PGFSM_READ 0 0x31 1 0 0 VALUE 0 23 regCC_SDMA0_EDC_CONFIG 0 0x32 1 0 0 DIS_EDC 1 1 regSDMA0_BA_THRESHOLD 0 0x33 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 regSDMA0_ID 0 0x34 1 0 0 DEVICE_ID 0 7 regSDMA0_VERSION 0 0x35 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 regSDMA0_EDC_COUNTER 0 0x36 16 0 0 SDMA_MBANK_DATA_BUF0_SED 0 1 SDMA_MBANK_DATA_BUF1_SED 2 3 SDMA_MBANK_DATA_BUF2_SED 4 5 SDMA_MBANK_DATA_BUF3_SED 6 7 SDMA_MBANK_DATA_BUF4_SED 8 9 SDMA_MBANK_DATA_BUF5_SED 10 11 SDMA_MBANK_DATA_BUF6_SED 12 13 SDMA_MBANK_DATA_BUF7_SED 14 15 SDMA_MBANK_DATA_BUF8_SED 16 17 SDMA_MBANK_DATA_BUF9_SED 18 19 SDMA_MBANK_DATA_BUF10_SED 20 21 SDMA_MBANK_DATA_BUF11_SED 22 23 SDMA_MBANK_DATA_BUF12_SED 24 25 SDMA_MBANK_DATA_BUF13_SED 26 27 SDMA_MBANK_DATA_BUF14_SED 28 29 SDMA_MBANK_DATA_BUF15_SED 30 31 regSDMA0_EDC_COUNTER2 0 0x37 10 0 0 SDMA_UCODE_BUF_SED 0 1 SDMA_RB_CMD_BUF_SED 2 3 SDMA_IB_CMD_BUF_SED 4 5 SDMA_UTCL1_RD_FIFO_SED 6 7 SDMA_UTCL1_RDBST_FIFO_SED 8 9 SDMA_UTCL1_WR_FIFO_SED 10 11 SDMA_DATA_LUT_FIFO_SED 12 13 SDMA_SPLIT_DATA_BUF_SED 14 15 SDMA_MC_WR_ADDR_FIFO_SED 16 17 SDMA_MC_RDRET_BUF_SED 18 19 regSDMA0_STATUS2_REG 0 0x38 3 0 0 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 regSDMA0_ATOMIC_CNTL 0 0x39 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 regSDMA0_ATOMIC_PREOP_LO 0 0x3a 1 0 0 DATA 0 31 regSDMA0_ATOMIC_PREOP_HI 0 0x3b 1 0 0 DATA 0 31 regSDMA0_UTCL1_CNTL 0 0x3c 6 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 regSDMA0_UTCL1_WATERMK 0 0x3d 5 0 0 REQ_WATERMK 0 2 REQ_DEPTH 3 4 PAGE_WATERMK 5 7 INVREQ_WATERMK 8 15 RESERVED 16 31 regSDMA0_UTCL1_RD_STATUS 0 0x3e 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 regSDMA0_UTCL1_WR_STATUS 0 0x3f 28 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 regSDMA0_UTCL1_INV0 0 0x40 14 0 0 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 regSDMA0_UTCL1_INV1 0 0x41 1 0 0 INV_ADDR_LO 0 31 regSDMA0_UTCL1_INV2 0 0x42 1 0 0 INV_NFLUSH_VMID_VEC 0 31 regSDMA0_UTCL1_RD_XNACK0 0 0x43 1 0 0 XNACK_ADDR_LO 0 31 regSDMA0_UTCL1_RD_XNACK1 0 0x44 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA0_UTCL1_WR_XNACK0 0 0x45 1 0 0 XNACK_ADDR_LO 0 31 regSDMA0_UTCL1_WR_XNACK1 0 0x46 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA0_UTCL1_TIMEOUT 0 0x47 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 regSDMA0_UTCL1_PAGE 0 0x48 4 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 regSDMA0_POWER_CNTL_IDLE 0 0x49 3 0 0 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 regSDMA0_RELAX_ORDERING_LUT 0 0x4a 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 regSDMA0_CHICKEN_BITS_2 0 0x4b 2 0 0 F32_CMD_PROC_DELAY 0 3 F32_SEND_POSTCODE_EN 4 4 regSDMA0_STATUS3_REG 0 0x4c 5 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 regSDMA0_PHYSICAL_ADDR_LO 0 0x4d 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 regSDMA0_PHYSICAL_ADDR_HI 0 0x4e 1 0 0 ADDR 0 15 regSDMA0_PHASE2_QUANTUM 0 0x4f 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA0_ERROR_LOG 0 0x50 2 0 0 OVERRIDE 0 15 STATUS 16 31 regSDMA0_PUB_DUMMY_REG0 0 0x51 1 0 0 VALUE 0 31 regSDMA0_PUB_DUMMY_REG1 0 0x52 1 0 0 VALUE 0 31 regSDMA0_PUB_DUMMY_REG2 0 0x53 1 0 0 VALUE 0 31 regSDMA0_PUB_DUMMY_REG3 0 0x54 1 0 0 VALUE 0 31 regSDMA0_F32_COUNTER 0 0x55 1 0 0 VALUE 0 31 regSDMA0_PERFCNT_PERFCOUNTER0_CFG 0 0x57 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA0_PERFCNT_PERFCOUNTER1_CFG 0 0x58 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x59 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regSDMA0_PERFCNT_MISC_CNTL 0 0x5a 1 0 0 CMD_OP 0 15 regSDMA0_PERFCNT_PERFCOUNTER_LO 0 0x5b 1 0 0 COUNTER_LO 0 31 regSDMA0_PERFCNT_PERFCOUNTER_HI 0 0x5c 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regSDMA0_CRD_CNTL 0 0x5d 2 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 regSDMA0_ULV_CNTL 0 0x5f 6 0 0 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 regSDMA0_EA_DBIT_ADDR_DATA 0 0x60 1 0 0 VALUE 0 31 regSDMA0_EA_DBIT_ADDR_INDEX 0 0x61 1 0 0 VALUE 0 2 regSDMA0_STATUS4_REG 0 0x63 14 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 MMHUB_RD_OUTSTANDING 4 4 MMHUB_WR_OUTSTANDING 5 5 UTCL2_RD_OUTSTANDING 6 6 UTCL2_WR_OUTSTANDING 7 7 REG_POLLING 8 8 MEM_POLLING 9 9 UTCL2_RD_XNACK 10 11 UTCL2_WR_XNACK 12 13 ACTIVE_QUEUE_ID 14 17 SRIOV_WATING_RLCV_CMD 18 18 SRIOV_SDMA_EXECUTING_CMD 19 19 regSDMA0_SCRATCH_RAM_DATA 0 0x64 1 0 0 DATA 0 31 regSDMA0_SCRATCH_RAM_ADDR 0 0x65 1 0 0 ADDR 0 6 regSDMA0_CE_CTRL 0 0x66 4 0 0 RD_LUT_WATERMARK 0 2 RD_LUT_DEPTH 3 4 WR_AFIFO_WATERMARK 5 7 RESERVED 8 31 regSDMA0_RAS_STATUS 0 0x67 12 0 0 RB_FETCH_ECC 0 0 IB_FETCH_ECC 1 1 F32_DATA_ECC 2 2 SEM_WPTR_ATOMIC_ECC 3 3 COPY_DATA_ECC 4 4 SRAM_ECC 5 5 RB_FETCH_NACK_GEN_ERR 8 8 IB_FETCH_NACK_GEN_ERR 9 9 F32_DATA_NACK_GEN_ERR 10 10 COPY_DATA_NACK_GEN_ERR 11 11 WRRET_DATA_NACK_GEN_ERR 12 12 WPTR_RPTR_ATOMIC_NACK_GEN_ERR 13 13 regSDMA0_CLK_STATUS 0 0x68 4 0 0 DYN_CLK 0 0 PTR_CLK 1 1 REG_CLK 2 2 F32_CLK 3 3 regSDMA0_GFX_RB_CNTL 0 0x80 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_GFX_RB_BASE 0 0x81 1 0 0 ADDR 0 31 regSDMA0_GFX_RB_BASE_HI 0 0x82 1 0 0 ADDR 0 23 regSDMA0_GFX_RB_RPTR 0 0x83 1 0 0 OFFSET 0 31 regSDMA0_GFX_RB_RPTR_HI 0 0x84 1 0 0 OFFSET 0 31 regSDMA0_GFX_RB_WPTR 0 0x85 1 0 0 OFFSET 0 31 regSDMA0_GFX_RB_WPTR_HI 0 0x86 1 0 0 OFFSET 0 31 regSDMA0_GFX_RB_WPTR_POLL_CNTL 0 0x87 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_GFX_RB_RPTR_ADDR_HI 0 0x88 1 0 0 ADDR 0 31 regSDMA0_GFX_RB_RPTR_ADDR_LO 0 0x89 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_GFX_IB_CNTL 0 0x8a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_GFX_IB_RPTR 0 0x8b 1 0 0 OFFSET 2 21 regSDMA0_GFX_IB_OFFSET 0 0x8c 1 0 0 OFFSET 2 21 regSDMA0_GFX_IB_BASE_LO 0 0x8d 1 0 0 ADDR 5 31 regSDMA0_GFX_IB_BASE_HI 0 0x8e 1 0 0 ADDR 0 31 regSDMA0_GFX_IB_SIZE 0 0x8f 1 0 0 SIZE 0 19 regSDMA0_GFX_SKIP_CNTL 0 0x90 1 0 0 SKIP_COUNT 0 19 regSDMA0_GFX_CONTEXT_STATUS 0 0x91 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_GFX_DOORBELL 0 0x92 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_GFX_CONTEXT_CNTL 0 0x93 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 regSDMA0_GFX_STATUS 0 0xa8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_GFX_DOORBELL_LOG 0 0xa9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_GFX_WATERMARK 0 0xaa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_GFX_DOORBELL_OFFSET 0 0xab 1 0 0 OFFSET 2 27 regSDMA0_GFX_CSA_ADDR_LO 0 0xac 1 0 0 ADDR 2 31 regSDMA0_GFX_CSA_ADDR_HI 0 0xad 1 0 0 ADDR 0 31 regSDMA0_GFX_IB_SUB_REMAIN 0 0xaf 1 0 0 SIZE 0 19 regSDMA0_GFX_PREEMPT 0 0xb0 1 0 0 IB_PREEMPT 0 0 regSDMA0_GFX_DUMMY_REG 0 0xb1 1 0 0 DUMMY 0 31 regSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0 0xb2 1 0 0 ADDR 0 31 regSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0 0xb3 1 0 0 ADDR 2 31 regSDMA0_GFX_RB_AQL_CNTL 0 0xb4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_GFX_MINOR_PTR_UPDATE 0 0xb5 1 0 0 ENABLE 0 0 regSDMA0_GFX_MIDCMD_DATA0 0 0xc0 1 0 0 DATA0 0 31 regSDMA0_GFX_MIDCMD_DATA1 0 0xc1 1 0 0 DATA1 0 31 regSDMA0_GFX_MIDCMD_DATA2 0 0xc2 1 0 0 DATA2 0 31 regSDMA0_GFX_MIDCMD_DATA3 0 0xc3 1 0 0 DATA3 0 31 regSDMA0_GFX_MIDCMD_DATA4 0 0xc4 1 0 0 DATA4 0 31 regSDMA0_GFX_MIDCMD_DATA5 0 0xc5 1 0 0 DATA5 0 31 regSDMA0_GFX_MIDCMD_DATA6 0 0xc6 1 0 0 DATA6 0 31 regSDMA0_GFX_MIDCMD_DATA7 0 0xc7 1 0 0 DATA7 0 31 regSDMA0_GFX_MIDCMD_DATA8 0 0xc8 1 0 0 DATA8 0 31 regSDMA0_GFX_MIDCMD_DATA9 0 0xc9 1 0 0 DATA9 0 31 regSDMA0_GFX_MIDCMD_DATA10 0 0xca 1 0 0 DATA10 0 31 regSDMA0_GFX_MIDCMD_CNTL 0 0xcb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_PAGE_RB_CNTL 0 0xd8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_PAGE_RB_BASE 0 0xd9 1 0 0 ADDR 0 31 regSDMA0_PAGE_RB_BASE_HI 0 0xda 1 0 0 ADDR 0 23 regSDMA0_PAGE_RB_RPTR 0 0xdb 1 0 0 OFFSET 0 31 regSDMA0_PAGE_RB_RPTR_HI 0 0xdc 1 0 0 OFFSET 0 31 regSDMA0_PAGE_RB_WPTR 0 0xdd 1 0 0 OFFSET 0 31 regSDMA0_PAGE_RB_WPTR_HI 0 0xde 1 0 0 OFFSET 0 31 regSDMA0_PAGE_RB_WPTR_POLL_CNTL 0 0xdf 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_PAGE_RB_RPTR_ADDR_HI 0 0xe0 1 0 0 ADDR 0 31 regSDMA0_PAGE_RB_RPTR_ADDR_LO 0 0xe1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_PAGE_IB_CNTL 0 0xe2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_PAGE_IB_RPTR 0 0xe3 1 0 0 OFFSET 2 21 regSDMA0_PAGE_IB_OFFSET 0 0xe4 1 0 0 OFFSET 2 21 regSDMA0_PAGE_IB_BASE_LO 0 0xe5 1 0 0 ADDR 5 31 regSDMA0_PAGE_IB_BASE_HI 0 0xe6 1 0 0 ADDR 0 31 regSDMA0_PAGE_IB_SIZE 0 0xe7 1 0 0 SIZE 0 19 regSDMA0_PAGE_SKIP_CNTL 0 0xe8 1 0 0 SKIP_COUNT 0 19 regSDMA0_PAGE_CONTEXT_STATUS 0 0xe9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_PAGE_DOORBELL 0 0xea 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_PAGE_STATUS 0 0x100 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_PAGE_DOORBELL_LOG 0 0x101 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_PAGE_WATERMARK 0 0x102 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_PAGE_DOORBELL_OFFSET 0 0x103 1 0 0 OFFSET 2 27 regSDMA0_PAGE_CSA_ADDR_LO 0 0x104 1 0 0 ADDR 2 31 regSDMA0_PAGE_CSA_ADDR_HI 0 0x105 1 0 0 ADDR 0 31 regSDMA0_PAGE_IB_SUB_REMAIN 0 0x107 1 0 0 SIZE 0 19 regSDMA0_PAGE_PREEMPT 0 0x108 1 0 0 IB_PREEMPT 0 0 regSDMA0_PAGE_DUMMY_REG 0 0x109 1 0 0 DUMMY 0 31 regSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x10a 1 0 0 ADDR 0 31 regSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x10b 1 0 0 ADDR 2 31 regSDMA0_PAGE_RB_AQL_CNTL 0 0x10c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_PAGE_MINOR_PTR_UPDATE 0 0x10d 1 0 0 ENABLE 0 0 regSDMA0_PAGE_MIDCMD_DATA0 0 0x118 1 0 0 DATA0 0 31 regSDMA0_PAGE_MIDCMD_DATA1 0 0x119 1 0 0 DATA1 0 31 regSDMA0_PAGE_MIDCMD_DATA2 0 0x11a 1 0 0 DATA2 0 31 regSDMA0_PAGE_MIDCMD_DATA3 0 0x11b 1 0 0 DATA3 0 31 regSDMA0_PAGE_MIDCMD_DATA4 0 0x11c 1 0 0 DATA4 0 31 regSDMA0_PAGE_MIDCMD_DATA5 0 0x11d 1 0 0 DATA5 0 31 regSDMA0_PAGE_MIDCMD_DATA6 0 0x11e 1 0 0 DATA6 0 31 regSDMA0_PAGE_MIDCMD_DATA7 0 0x11f 1 0 0 DATA7 0 31 regSDMA0_PAGE_MIDCMD_DATA8 0 0x120 1 0 0 DATA8 0 31 regSDMA0_PAGE_MIDCMD_DATA9 0 0x121 1 0 0 DATA9 0 31 regSDMA0_PAGE_MIDCMD_DATA10 0 0x122 1 0 0 DATA10 0 31 regSDMA0_PAGE_MIDCMD_CNTL 0 0x123 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC0_RB_CNTL 0 0x130 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC0_RB_BASE 0 0x131 1 0 0 ADDR 0 31 regSDMA0_RLC0_RB_BASE_HI 0 0x132 1 0 0 ADDR 0 23 regSDMA0_RLC0_RB_RPTR 0 0x133 1 0 0 OFFSET 0 31 regSDMA0_RLC0_RB_RPTR_HI 0 0x134 1 0 0 OFFSET 0 31 regSDMA0_RLC0_RB_WPTR 0 0x135 1 0 0 OFFSET 0 31 regSDMA0_RLC0_RB_WPTR_HI 0 0x136 1 0 0 OFFSET 0 31 regSDMA0_RLC0_RB_WPTR_POLL_CNTL 0 0x137 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC0_RB_RPTR_ADDR_HI 0 0x138 1 0 0 ADDR 0 31 regSDMA0_RLC0_RB_RPTR_ADDR_LO 0 0x139 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC0_IB_CNTL 0 0x13a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC0_IB_RPTR 0 0x13b 1 0 0 OFFSET 2 21 regSDMA0_RLC0_IB_OFFSET 0 0x13c 1 0 0 OFFSET 2 21 regSDMA0_RLC0_IB_BASE_LO 0 0x13d 1 0 0 ADDR 5 31 regSDMA0_RLC0_IB_BASE_HI 0 0x13e 1 0 0 ADDR 0 31 regSDMA0_RLC0_IB_SIZE 0 0x13f 1 0 0 SIZE 0 19 regSDMA0_RLC0_SKIP_CNTL 0 0x140 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC0_CONTEXT_STATUS 0 0x141 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC0_DOORBELL 0 0x142 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC0_STATUS 0 0x158 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC0_DOORBELL_LOG 0 0x159 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC0_WATERMARK 0 0x15a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC0_DOORBELL_OFFSET 0 0x15b 1 0 0 OFFSET 2 27 regSDMA0_RLC0_CSA_ADDR_LO 0 0x15c 1 0 0 ADDR 2 31 regSDMA0_RLC0_CSA_ADDR_HI 0 0x15d 1 0 0 ADDR 0 31 regSDMA0_RLC0_IB_SUB_REMAIN 0 0x15f 1 0 0 SIZE 0 19 regSDMA0_RLC0_PREEMPT 0 0x160 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC0_DUMMY_REG 0 0x161 1 0 0 DUMMY 0 31 regSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x162 1 0 0 ADDR 0 31 regSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x163 1 0 0 ADDR 2 31 regSDMA0_RLC0_RB_AQL_CNTL 0 0x164 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC0_MINOR_PTR_UPDATE 0 0x165 1 0 0 ENABLE 0 0 regSDMA0_RLC0_MIDCMD_DATA0 0 0x170 1 0 0 DATA0 0 31 regSDMA0_RLC0_MIDCMD_DATA1 0 0x171 1 0 0 DATA1 0 31 regSDMA0_RLC0_MIDCMD_DATA2 0 0x172 1 0 0 DATA2 0 31 regSDMA0_RLC0_MIDCMD_DATA3 0 0x173 1 0 0 DATA3 0 31 regSDMA0_RLC0_MIDCMD_DATA4 0 0x174 1 0 0 DATA4 0 31 regSDMA0_RLC0_MIDCMD_DATA5 0 0x175 1 0 0 DATA5 0 31 regSDMA0_RLC0_MIDCMD_DATA6 0 0x176 1 0 0 DATA6 0 31 regSDMA0_RLC0_MIDCMD_DATA7 0 0x177 1 0 0 DATA7 0 31 regSDMA0_RLC0_MIDCMD_DATA8 0 0x178 1 0 0 DATA8 0 31 regSDMA0_RLC0_MIDCMD_DATA9 0 0x179 1 0 0 DATA9 0 31 regSDMA0_RLC0_MIDCMD_DATA10 0 0x17a 1 0 0 DATA10 0 31 regSDMA0_RLC0_MIDCMD_CNTL 0 0x17b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC1_RB_CNTL 0 0x188 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC1_RB_BASE 0 0x189 1 0 0 ADDR 0 31 regSDMA0_RLC1_RB_BASE_HI 0 0x18a 1 0 0 ADDR 0 23 regSDMA0_RLC1_RB_RPTR 0 0x18b 1 0 0 OFFSET 0 31 regSDMA0_RLC1_RB_RPTR_HI 0 0x18c 1 0 0 OFFSET 0 31 regSDMA0_RLC1_RB_WPTR 0 0x18d 1 0 0 OFFSET 0 31 regSDMA0_RLC1_RB_WPTR_HI 0 0x18e 1 0 0 OFFSET 0 31 regSDMA0_RLC1_RB_WPTR_POLL_CNTL 0 0x18f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC1_RB_RPTR_ADDR_HI 0 0x190 1 0 0 ADDR 0 31 regSDMA0_RLC1_RB_RPTR_ADDR_LO 0 0x191 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC1_IB_CNTL 0 0x192 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC1_IB_RPTR 0 0x193 1 0 0 OFFSET 2 21 regSDMA0_RLC1_IB_OFFSET 0 0x194 1 0 0 OFFSET 2 21 regSDMA0_RLC1_IB_BASE_LO 0 0x195 1 0 0 ADDR 5 31 regSDMA0_RLC1_IB_BASE_HI 0 0x196 1 0 0 ADDR 0 31 regSDMA0_RLC1_IB_SIZE 0 0x197 1 0 0 SIZE 0 19 regSDMA0_RLC1_SKIP_CNTL 0 0x198 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC1_CONTEXT_STATUS 0 0x199 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC1_DOORBELL 0 0x19a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC1_STATUS 0 0x1b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC1_DOORBELL_LOG 0 0x1b1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC1_WATERMARK 0 0x1b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC1_DOORBELL_OFFSET 0 0x1b3 1 0 0 OFFSET 2 27 regSDMA0_RLC1_CSA_ADDR_LO 0 0x1b4 1 0 0 ADDR 2 31 regSDMA0_RLC1_CSA_ADDR_HI 0 0x1b5 1 0 0 ADDR 0 31 regSDMA0_RLC1_IB_SUB_REMAIN 0 0x1b7 1 0 0 SIZE 0 19 regSDMA0_RLC1_PREEMPT 0 0x1b8 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC1_DUMMY_REG 0 0x1b9 1 0 0 DUMMY 0 31 regSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1ba 1 0 0 ADDR 0 31 regSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1bb 1 0 0 ADDR 2 31 regSDMA0_RLC1_RB_AQL_CNTL 0 0x1bc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC1_MINOR_PTR_UPDATE 0 0x1bd 1 0 0 ENABLE 0 0 regSDMA0_RLC1_MIDCMD_DATA0 0 0x1c8 1 0 0 DATA0 0 31 regSDMA0_RLC1_MIDCMD_DATA1 0 0x1c9 1 0 0 DATA1 0 31 regSDMA0_RLC1_MIDCMD_DATA2 0 0x1ca 1 0 0 DATA2 0 31 regSDMA0_RLC1_MIDCMD_DATA3 0 0x1cb 1 0 0 DATA3 0 31 regSDMA0_RLC1_MIDCMD_DATA4 0 0x1cc 1 0 0 DATA4 0 31 regSDMA0_RLC1_MIDCMD_DATA5 0 0x1cd 1 0 0 DATA5 0 31 regSDMA0_RLC1_MIDCMD_DATA6 0 0x1ce 1 0 0 DATA6 0 31 regSDMA0_RLC1_MIDCMD_DATA7 0 0x1cf 1 0 0 DATA7 0 31 regSDMA0_RLC1_MIDCMD_DATA8 0 0x1d0 1 0 0 DATA8 0 31 regSDMA0_RLC1_MIDCMD_DATA9 0 0x1d1 1 0 0 DATA9 0 31 regSDMA0_RLC1_MIDCMD_DATA10 0 0x1d2 1 0 0 DATA10 0 31 regSDMA0_RLC1_MIDCMD_CNTL 0 0x1d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC2_RB_CNTL 0 0x1e0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC2_RB_BASE 0 0x1e1 1 0 0 ADDR 0 31 regSDMA0_RLC2_RB_BASE_HI 0 0x1e2 1 0 0 ADDR 0 23 regSDMA0_RLC2_RB_RPTR 0 0x1e3 1 0 0 OFFSET 0 31 regSDMA0_RLC2_RB_RPTR_HI 0 0x1e4 1 0 0 OFFSET 0 31 regSDMA0_RLC2_RB_WPTR 0 0x1e5 1 0 0 OFFSET 0 31 regSDMA0_RLC2_RB_WPTR_HI 0 0x1e6 1 0 0 OFFSET 0 31 regSDMA0_RLC2_RB_WPTR_POLL_CNTL 0 0x1e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC2_RB_RPTR_ADDR_HI 0 0x1e8 1 0 0 ADDR 0 31 regSDMA0_RLC2_RB_RPTR_ADDR_LO 0 0x1e9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC2_IB_CNTL 0 0x1ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC2_IB_RPTR 0 0x1eb 1 0 0 OFFSET 2 21 regSDMA0_RLC2_IB_OFFSET 0 0x1ec 1 0 0 OFFSET 2 21 regSDMA0_RLC2_IB_BASE_LO 0 0x1ed 1 0 0 ADDR 5 31 regSDMA0_RLC2_IB_BASE_HI 0 0x1ee 1 0 0 ADDR 0 31 regSDMA0_RLC2_IB_SIZE 0 0x1ef 1 0 0 SIZE 0 19 regSDMA0_RLC2_SKIP_CNTL 0 0x1f0 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC2_CONTEXT_STATUS 0 0x1f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC2_DOORBELL 0 0x1f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC2_STATUS 0 0x208 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC2_DOORBELL_LOG 0 0x209 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC2_WATERMARK 0 0x20a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC2_DOORBELL_OFFSET 0 0x20b 1 0 0 OFFSET 2 27 regSDMA0_RLC2_CSA_ADDR_LO 0 0x20c 1 0 0 ADDR 2 31 regSDMA0_RLC2_CSA_ADDR_HI 0 0x20d 1 0 0 ADDR 0 31 regSDMA0_RLC2_IB_SUB_REMAIN 0 0x20f 1 0 0 SIZE 0 19 regSDMA0_RLC2_PREEMPT 0 0x210 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC2_DUMMY_REG 0 0x211 1 0 0 DUMMY 0 31 regSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x212 1 0 0 ADDR 0 31 regSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x213 1 0 0 ADDR 2 31 regSDMA0_RLC2_RB_AQL_CNTL 0 0x214 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC2_MINOR_PTR_UPDATE 0 0x215 1 0 0 ENABLE 0 0 regSDMA0_RLC2_MIDCMD_DATA0 0 0x220 1 0 0 DATA0 0 31 regSDMA0_RLC2_MIDCMD_DATA1 0 0x221 1 0 0 DATA1 0 31 regSDMA0_RLC2_MIDCMD_DATA2 0 0x222 1 0 0 DATA2 0 31 regSDMA0_RLC2_MIDCMD_DATA3 0 0x223 1 0 0 DATA3 0 31 regSDMA0_RLC2_MIDCMD_DATA4 0 0x224 1 0 0 DATA4 0 31 regSDMA0_RLC2_MIDCMD_DATA5 0 0x225 1 0 0 DATA5 0 31 regSDMA0_RLC2_MIDCMD_DATA6 0 0x226 1 0 0 DATA6 0 31 regSDMA0_RLC2_MIDCMD_DATA7 0 0x227 1 0 0 DATA7 0 31 regSDMA0_RLC2_MIDCMD_DATA8 0 0x228 1 0 0 DATA8 0 31 regSDMA0_RLC2_MIDCMD_DATA9 0 0x229 1 0 0 DATA9 0 31 regSDMA0_RLC2_MIDCMD_DATA10 0 0x22a 1 0 0 DATA10 0 31 regSDMA0_RLC2_MIDCMD_CNTL 0 0x22b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC3_RB_CNTL 0 0x238 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC3_RB_BASE 0 0x239 1 0 0 ADDR 0 31 regSDMA0_RLC3_RB_BASE_HI 0 0x23a 1 0 0 ADDR 0 23 regSDMA0_RLC3_RB_RPTR 0 0x23b 1 0 0 OFFSET 0 31 regSDMA0_RLC3_RB_RPTR_HI 0 0x23c 1 0 0 OFFSET 0 31 regSDMA0_RLC3_RB_WPTR 0 0x23d 1 0 0 OFFSET 0 31 regSDMA0_RLC3_RB_WPTR_HI 0 0x23e 1 0 0 OFFSET 0 31 regSDMA0_RLC3_RB_WPTR_POLL_CNTL 0 0x23f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC3_RB_RPTR_ADDR_HI 0 0x240 1 0 0 ADDR 0 31 regSDMA0_RLC3_RB_RPTR_ADDR_LO 0 0x241 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC3_IB_CNTL 0 0x242 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC3_IB_RPTR 0 0x243 1 0 0 OFFSET 2 21 regSDMA0_RLC3_IB_OFFSET 0 0x244 1 0 0 OFFSET 2 21 regSDMA0_RLC3_IB_BASE_LO 0 0x245 1 0 0 ADDR 5 31 regSDMA0_RLC3_IB_BASE_HI 0 0x246 1 0 0 ADDR 0 31 regSDMA0_RLC3_IB_SIZE 0 0x247 1 0 0 SIZE 0 19 regSDMA0_RLC3_SKIP_CNTL 0 0x248 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC3_CONTEXT_STATUS 0 0x249 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC3_DOORBELL 0 0x24a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC3_STATUS 0 0x260 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC3_DOORBELL_LOG 0 0x261 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC3_WATERMARK 0 0x262 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC3_DOORBELL_OFFSET 0 0x263 1 0 0 OFFSET 2 27 regSDMA0_RLC3_CSA_ADDR_LO 0 0x264 1 0 0 ADDR 2 31 regSDMA0_RLC3_CSA_ADDR_HI 0 0x265 1 0 0 ADDR 0 31 regSDMA0_RLC3_IB_SUB_REMAIN 0 0x267 1 0 0 SIZE 0 19 regSDMA0_RLC3_PREEMPT 0 0x268 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC3_DUMMY_REG 0 0x269 1 0 0 DUMMY 0 31 regSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x26a 1 0 0 ADDR 0 31 regSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x26b 1 0 0 ADDR 2 31 regSDMA0_RLC3_RB_AQL_CNTL 0 0x26c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC3_MINOR_PTR_UPDATE 0 0x26d 1 0 0 ENABLE 0 0 regSDMA0_RLC3_MIDCMD_DATA0 0 0x278 1 0 0 DATA0 0 31 regSDMA0_RLC3_MIDCMD_DATA1 0 0x279 1 0 0 DATA1 0 31 regSDMA0_RLC3_MIDCMD_DATA2 0 0x27a 1 0 0 DATA2 0 31 regSDMA0_RLC3_MIDCMD_DATA3 0 0x27b 1 0 0 DATA3 0 31 regSDMA0_RLC3_MIDCMD_DATA4 0 0x27c 1 0 0 DATA4 0 31 regSDMA0_RLC3_MIDCMD_DATA5 0 0x27d 1 0 0 DATA5 0 31 regSDMA0_RLC3_MIDCMD_DATA6 0 0x27e 1 0 0 DATA6 0 31 regSDMA0_RLC3_MIDCMD_DATA7 0 0x27f 1 0 0 DATA7 0 31 regSDMA0_RLC3_MIDCMD_DATA8 0 0x280 1 0 0 DATA8 0 31 regSDMA0_RLC3_MIDCMD_DATA9 0 0x281 1 0 0 DATA9 0 31 regSDMA0_RLC3_MIDCMD_DATA10 0 0x282 1 0 0 DATA10 0 31 regSDMA0_RLC3_MIDCMD_CNTL 0 0x283 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC4_RB_CNTL 0 0x290 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC4_RB_BASE 0 0x291 1 0 0 ADDR 0 31 regSDMA0_RLC4_RB_BASE_HI 0 0x292 1 0 0 ADDR 0 23 regSDMA0_RLC4_RB_RPTR 0 0x293 1 0 0 OFFSET 0 31 regSDMA0_RLC4_RB_RPTR_HI 0 0x294 1 0 0 OFFSET 0 31 regSDMA0_RLC4_RB_WPTR 0 0x295 1 0 0 OFFSET 0 31 regSDMA0_RLC4_RB_WPTR_HI 0 0x296 1 0 0 OFFSET 0 31 regSDMA0_RLC4_RB_WPTR_POLL_CNTL 0 0x297 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC4_RB_RPTR_ADDR_HI 0 0x298 1 0 0 ADDR 0 31 regSDMA0_RLC4_RB_RPTR_ADDR_LO 0 0x299 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC4_IB_CNTL 0 0x29a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC4_IB_RPTR 0 0x29b 1 0 0 OFFSET 2 21 regSDMA0_RLC4_IB_OFFSET 0 0x29c 1 0 0 OFFSET 2 21 regSDMA0_RLC4_IB_BASE_LO 0 0x29d 1 0 0 ADDR 5 31 regSDMA0_RLC4_IB_BASE_HI 0 0x29e 1 0 0 ADDR 0 31 regSDMA0_RLC4_IB_SIZE 0 0x29f 1 0 0 SIZE 0 19 regSDMA0_RLC4_SKIP_CNTL 0 0x2a0 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC4_CONTEXT_STATUS 0 0x2a1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC4_DOORBELL 0 0x2a2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC4_STATUS 0 0x2b8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC4_DOORBELL_LOG 0 0x2b9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC4_WATERMARK 0 0x2ba 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC4_DOORBELL_OFFSET 0 0x2bb 1 0 0 OFFSET 2 27 regSDMA0_RLC4_CSA_ADDR_LO 0 0x2bc 1 0 0 ADDR 2 31 regSDMA0_RLC4_CSA_ADDR_HI 0 0x2bd 1 0 0 ADDR 0 31 regSDMA0_RLC4_IB_SUB_REMAIN 0 0x2bf 1 0 0 SIZE 0 19 regSDMA0_RLC4_PREEMPT 0 0x2c0 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC4_DUMMY_REG 0 0x2c1 1 0 0 DUMMY 0 31 regSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x2c2 1 0 0 ADDR 0 31 regSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x2c3 1 0 0 ADDR 2 31 regSDMA0_RLC4_RB_AQL_CNTL 0 0x2c4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC4_MINOR_PTR_UPDATE 0 0x2c5 1 0 0 ENABLE 0 0 regSDMA0_RLC4_MIDCMD_DATA0 0 0x2d0 1 0 0 DATA0 0 31 regSDMA0_RLC4_MIDCMD_DATA1 0 0x2d1 1 0 0 DATA1 0 31 regSDMA0_RLC4_MIDCMD_DATA2 0 0x2d2 1 0 0 DATA2 0 31 regSDMA0_RLC4_MIDCMD_DATA3 0 0x2d3 1 0 0 DATA3 0 31 regSDMA0_RLC4_MIDCMD_DATA4 0 0x2d4 1 0 0 DATA4 0 31 regSDMA0_RLC4_MIDCMD_DATA5 0 0x2d5 1 0 0 DATA5 0 31 regSDMA0_RLC4_MIDCMD_DATA6 0 0x2d6 1 0 0 DATA6 0 31 regSDMA0_RLC4_MIDCMD_DATA7 0 0x2d7 1 0 0 DATA7 0 31 regSDMA0_RLC4_MIDCMD_DATA8 0 0x2d8 1 0 0 DATA8 0 31 regSDMA0_RLC4_MIDCMD_DATA9 0 0x2d9 1 0 0 DATA9 0 31 regSDMA0_RLC4_MIDCMD_DATA10 0 0x2da 1 0 0 DATA10 0 31 regSDMA0_RLC4_MIDCMD_CNTL 0 0x2db 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC5_RB_CNTL 0 0x2e8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC5_RB_BASE 0 0x2e9 1 0 0 ADDR 0 31 regSDMA0_RLC5_RB_BASE_HI 0 0x2ea 1 0 0 ADDR 0 23 regSDMA0_RLC5_RB_RPTR 0 0x2eb 1 0 0 OFFSET 0 31 regSDMA0_RLC5_RB_RPTR_HI 0 0x2ec 1 0 0 OFFSET 0 31 regSDMA0_RLC5_RB_WPTR 0 0x2ed 1 0 0 OFFSET 0 31 regSDMA0_RLC5_RB_WPTR_HI 0 0x2ee 1 0 0 OFFSET 0 31 regSDMA0_RLC5_RB_WPTR_POLL_CNTL 0 0x2ef 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC5_RB_RPTR_ADDR_HI 0 0x2f0 1 0 0 ADDR 0 31 regSDMA0_RLC5_RB_RPTR_ADDR_LO 0 0x2f1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC5_IB_CNTL 0 0x2f2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC5_IB_RPTR 0 0x2f3 1 0 0 OFFSET 2 21 regSDMA0_RLC5_IB_OFFSET 0 0x2f4 1 0 0 OFFSET 2 21 regSDMA0_RLC5_IB_BASE_LO 0 0x2f5 1 0 0 ADDR 5 31 regSDMA0_RLC5_IB_BASE_HI 0 0x2f6 1 0 0 ADDR 0 31 regSDMA0_RLC5_IB_SIZE 0 0x2f7 1 0 0 SIZE 0 19 regSDMA0_RLC5_SKIP_CNTL 0 0x2f8 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC5_CONTEXT_STATUS 0 0x2f9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC5_DOORBELL 0 0x2fa 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC5_STATUS 0 0x310 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC5_DOORBELL_LOG 0 0x311 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC5_WATERMARK 0 0x312 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC5_DOORBELL_OFFSET 0 0x313 1 0 0 OFFSET 2 27 regSDMA0_RLC5_CSA_ADDR_LO 0 0x314 1 0 0 ADDR 2 31 regSDMA0_RLC5_CSA_ADDR_HI 0 0x315 1 0 0 ADDR 0 31 regSDMA0_RLC5_IB_SUB_REMAIN 0 0x317 1 0 0 SIZE 0 19 regSDMA0_RLC5_PREEMPT 0 0x318 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC5_DUMMY_REG 0 0x319 1 0 0 DUMMY 0 31 regSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x31a 1 0 0 ADDR 0 31 regSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x31b 1 0 0 ADDR 2 31 regSDMA0_RLC5_RB_AQL_CNTL 0 0x31c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC5_MINOR_PTR_UPDATE 0 0x31d 1 0 0 ENABLE 0 0 regSDMA0_RLC5_MIDCMD_DATA0 0 0x328 1 0 0 DATA0 0 31 regSDMA0_RLC5_MIDCMD_DATA1 0 0x329 1 0 0 DATA1 0 31 regSDMA0_RLC5_MIDCMD_DATA2 0 0x32a 1 0 0 DATA2 0 31 regSDMA0_RLC5_MIDCMD_DATA3 0 0x32b 1 0 0 DATA3 0 31 regSDMA0_RLC5_MIDCMD_DATA4 0 0x32c 1 0 0 DATA4 0 31 regSDMA0_RLC5_MIDCMD_DATA5 0 0x32d 1 0 0 DATA5 0 31 regSDMA0_RLC5_MIDCMD_DATA6 0 0x32e 1 0 0 DATA6 0 31 regSDMA0_RLC5_MIDCMD_DATA7 0 0x32f 1 0 0 DATA7 0 31 regSDMA0_RLC5_MIDCMD_DATA8 0 0x330 1 0 0 DATA8 0 31 regSDMA0_RLC5_MIDCMD_DATA9 0 0x331 1 0 0 DATA9 0 31 regSDMA0_RLC5_MIDCMD_DATA10 0 0x332 1 0 0 DATA10 0 31 regSDMA0_RLC5_MIDCMD_CNTL 0 0x333 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC6_RB_CNTL 0 0x340 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC6_RB_BASE 0 0x341 1 0 0 ADDR 0 31 regSDMA0_RLC6_RB_BASE_HI 0 0x342 1 0 0 ADDR 0 23 regSDMA0_RLC6_RB_RPTR 0 0x343 1 0 0 OFFSET 0 31 regSDMA0_RLC6_RB_RPTR_HI 0 0x344 1 0 0 OFFSET 0 31 regSDMA0_RLC6_RB_WPTR 0 0x345 1 0 0 OFFSET 0 31 regSDMA0_RLC6_RB_WPTR_HI 0 0x346 1 0 0 OFFSET 0 31 regSDMA0_RLC6_RB_WPTR_POLL_CNTL 0 0x347 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC6_RB_RPTR_ADDR_HI 0 0x348 1 0 0 ADDR 0 31 regSDMA0_RLC6_RB_RPTR_ADDR_LO 0 0x349 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC6_IB_CNTL 0 0x34a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC6_IB_RPTR 0 0x34b 1 0 0 OFFSET 2 21 regSDMA0_RLC6_IB_OFFSET 0 0x34c 1 0 0 OFFSET 2 21 regSDMA0_RLC6_IB_BASE_LO 0 0x34d 1 0 0 ADDR 5 31 regSDMA0_RLC6_IB_BASE_HI 0 0x34e 1 0 0 ADDR 0 31 regSDMA0_RLC6_IB_SIZE 0 0x34f 1 0 0 SIZE 0 19 regSDMA0_RLC6_SKIP_CNTL 0 0x350 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC6_CONTEXT_STATUS 0 0x351 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC6_DOORBELL 0 0x352 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC6_STATUS 0 0x368 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC6_DOORBELL_LOG 0 0x369 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC6_WATERMARK 0 0x36a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC6_DOORBELL_OFFSET 0 0x36b 1 0 0 OFFSET 2 27 regSDMA0_RLC6_CSA_ADDR_LO 0 0x36c 1 0 0 ADDR 2 31 regSDMA0_RLC6_CSA_ADDR_HI 0 0x36d 1 0 0 ADDR 0 31 regSDMA0_RLC6_IB_SUB_REMAIN 0 0x36f 1 0 0 SIZE 0 19 regSDMA0_RLC6_PREEMPT 0 0x370 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC6_DUMMY_REG 0 0x371 1 0 0 DUMMY 0 31 regSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x372 1 0 0 ADDR 0 31 regSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x373 1 0 0 ADDR 2 31 regSDMA0_RLC6_RB_AQL_CNTL 0 0x374 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC6_MINOR_PTR_UPDATE 0 0x375 1 0 0 ENABLE 0 0 regSDMA0_RLC6_MIDCMD_DATA0 0 0x380 1 0 0 DATA0 0 31 regSDMA0_RLC6_MIDCMD_DATA1 0 0x381 1 0 0 DATA1 0 31 regSDMA0_RLC6_MIDCMD_DATA2 0 0x382 1 0 0 DATA2 0 31 regSDMA0_RLC6_MIDCMD_DATA3 0 0x383 1 0 0 DATA3 0 31 regSDMA0_RLC6_MIDCMD_DATA4 0 0x384 1 0 0 DATA4 0 31 regSDMA0_RLC6_MIDCMD_DATA5 0 0x385 1 0 0 DATA5 0 31 regSDMA0_RLC6_MIDCMD_DATA6 0 0x386 1 0 0 DATA6 0 31 regSDMA0_RLC6_MIDCMD_DATA7 0 0x387 1 0 0 DATA7 0 31 regSDMA0_RLC6_MIDCMD_DATA8 0 0x388 1 0 0 DATA8 0 31 regSDMA0_RLC6_MIDCMD_DATA9 0 0x389 1 0 0 DATA9 0 31 regSDMA0_RLC6_MIDCMD_DATA10 0 0x38a 1 0 0 DATA10 0 31 regSDMA0_RLC6_MIDCMD_CNTL 0 0x38b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA0_RLC7_RB_CNTL 0 0x398 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA0_RLC7_RB_BASE 0 0x399 1 0 0 ADDR 0 31 regSDMA0_RLC7_RB_BASE_HI 0 0x39a 1 0 0 ADDR 0 23 regSDMA0_RLC7_RB_RPTR 0 0x39b 1 0 0 OFFSET 0 31 regSDMA0_RLC7_RB_RPTR_HI 0 0x39c 1 0 0 OFFSET 0 31 regSDMA0_RLC7_RB_WPTR 0 0x39d 1 0 0 OFFSET 0 31 regSDMA0_RLC7_RB_WPTR_HI 0 0x39e 1 0 0 OFFSET 0 31 regSDMA0_RLC7_RB_WPTR_POLL_CNTL 0 0x39f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA0_RLC7_RB_RPTR_ADDR_HI 0 0x3a0 1 0 0 ADDR 0 31 regSDMA0_RLC7_RB_RPTR_ADDR_LO 0 0x3a1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA0_RLC7_IB_CNTL 0 0x3a2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA0_RLC7_IB_RPTR 0 0x3a3 1 0 0 OFFSET 2 21 regSDMA0_RLC7_IB_OFFSET 0 0x3a4 1 0 0 OFFSET 2 21 regSDMA0_RLC7_IB_BASE_LO 0 0x3a5 1 0 0 ADDR 5 31 regSDMA0_RLC7_IB_BASE_HI 0 0x3a6 1 0 0 ADDR 0 31 regSDMA0_RLC7_IB_SIZE 0 0x3a7 1 0 0 SIZE 0 19 regSDMA0_RLC7_SKIP_CNTL 0 0x3a8 1 0 0 SKIP_COUNT 0 19 regSDMA0_RLC7_CONTEXT_STATUS 0 0x3a9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA0_RLC7_DOORBELL 0 0x3aa 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA0_RLC7_STATUS 0 0x3c0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA0_RLC7_DOORBELL_LOG 0 0x3c1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA0_RLC7_WATERMARK 0 0x3c2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA0_RLC7_DOORBELL_OFFSET 0 0x3c3 1 0 0 OFFSET 2 27 regSDMA0_RLC7_CSA_ADDR_LO 0 0x3c4 1 0 0 ADDR 2 31 regSDMA0_RLC7_CSA_ADDR_HI 0 0x3c5 1 0 0 ADDR 0 31 regSDMA0_RLC7_IB_SUB_REMAIN 0 0x3c7 1 0 0 SIZE 0 19 regSDMA0_RLC7_PREEMPT 0 0x3c8 1 0 0 IB_PREEMPT 0 0 regSDMA0_RLC7_DUMMY_REG 0 0x3c9 1 0 0 DUMMY 0 31 regSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x3ca 1 0 0 ADDR 0 31 regSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x3cb 1 0 0 ADDR 2 31 regSDMA0_RLC7_RB_AQL_CNTL 0 0x3cc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA0_RLC7_MINOR_PTR_UPDATE 0 0x3cd 1 0 0 ENABLE 0 0 regSDMA0_RLC7_MIDCMD_DATA0 0 0x3d8 1 0 0 DATA0 0 31 regSDMA0_RLC7_MIDCMD_DATA1 0 0x3d9 1 0 0 DATA1 0 31 regSDMA0_RLC7_MIDCMD_DATA2 0 0x3da 1 0 0 DATA2 0 31 regSDMA0_RLC7_MIDCMD_DATA3 0 0x3db 1 0 0 DATA3 0 31 regSDMA0_RLC7_MIDCMD_DATA4 0 0x3dc 1 0 0 DATA4 0 31 regSDMA0_RLC7_MIDCMD_DATA5 0 0x3dd 1 0 0 DATA5 0 31 regSDMA0_RLC7_MIDCMD_DATA6 0 0x3de 1 0 0 DATA6 0 31 regSDMA0_RLC7_MIDCMD_DATA7 0 0x3df 1 0 0 DATA7 0 31 regSDMA0_RLC7_MIDCMD_DATA8 0 0x3e0 1 0 0 DATA8 0 31 regSDMA0_RLC7_MIDCMD_DATA9 0 0x3e1 1 0 0 DATA9 0 31 regSDMA0_RLC7_MIDCMD_DATA10 0 0x3e2 1 0 0 DATA10 0 31 regSDMA0_RLC7_MIDCMD_CNTL 0 0x3e3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_UCODE_ADDR 0 0x600 1 0 0 VALUE 0 13 regSDMA1_UCODE_DATA 0 0x601 1 0 0 VALUE 0 31 regSDMA1_VF_ENABLE 0 0x60a 1 0 0 VF_ENABLE 0 0 regSDMA1_CONTEXT_GROUP_BOUNDARY 0 0x619 1 0 0 RESERVED 0 31 regSDMA1_POWER_CNTL 0 0x61a 10 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 ON_OFF_STATUS_DURATION_TIME 26 31 regSDMA1_CLK_CTRL 0 0x61b 11 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSDMA1_CNTL 0 0x61c 12 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_EXPIRE_ENABLE 6 6 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 regSDMA1_CHICKEN_BITS 0 0x61d 12 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 SRAM_FGCG_ENABLE 26 26 RESERVED 27 31 regSDMA1_GB_ADDR_CONFIG 0 0x61e 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA1_GB_ADDR_CONFIG_READ 0 0x61f 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA1_RB_RPTR_FETCH_HI 0 0x620 1 0 0 OFFSET 0 31 regSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0 0x621 1 0 0 TIMER 0 31 regSDMA1_RB_RPTR_FETCH 0 0x622 1 0 0 OFFSET 2 31 regSDMA1_IB_OFFSET_FETCH 0 0x623 1 0 0 OFFSET 2 21 regSDMA1_PROGRAM 0 0x624 1 0 0 STREAM 0 31 regSDMA1_STATUS_REG 0 0x625 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 regSDMA1_STATUS1_REG 0 0x626 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 regSDMA1_RD_BURST_CNTL 0 0x627 2 0 0 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 regSDMA1_HBM_PAGE_CONFIG 0 0x628 1 0 0 PAGE_SIZE_EXPONENT 0 1 regSDMA1_UCODE_CHECKSUM 0 0x629 1 0 0 DATA 0 31 regSDMA1_F32_CNTL 0 0x62a 3 0 0 HALT 0 0 STEP 1 1 RESET 8 8 regSDMA1_FREEZE 0 0x62b 4 0 0 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 regSDMA1_PHASE0_QUANTUM 0 0x62c 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA1_PHASE1_QUANTUM 0 0x62d 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regCC_SDMA1_EDC_CONFIG 0 0x632 1 0 0 DIS_EDC 1 1 regSDMA1_BA_THRESHOLD 0 0x633 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 regSDMA1_ID 0 0x634 1 0 0 DEVICE_ID 0 7 regSDMA1_VERSION 0 0x635 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 regSDMA1_EDC_COUNTER 0 0x636 16 0 0 SDMA_MBANK_DATA_BUF0_SED 0 1 SDMA_MBANK_DATA_BUF1_SED 2 3 SDMA_MBANK_DATA_BUF2_SED 4 5 SDMA_MBANK_DATA_BUF3_SED 6 7 SDMA_MBANK_DATA_BUF4_SED 8 9 SDMA_MBANK_DATA_BUF5_SED 10 11 SDMA_MBANK_DATA_BUF6_SED 12 13 SDMA_MBANK_DATA_BUF7_SED 14 15 SDMA_MBANK_DATA_BUF8_SED 16 17 SDMA_MBANK_DATA_BUF9_SED 18 19 SDMA_MBANK_DATA_BUF10_SED 20 21 SDMA_MBANK_DATA_BUF11_SED 22 23 SDMA_MBANK_DATA_BUF12_SED 24 25 SDMA_MBANK_DATA_BUF13_SED 26 27 SDMA_MBANK_DATA_BUF14_SED 28 29 SDMA_MBANK_DATA_BUF15_SED 30 31 regSDMA1_EDC_COUNTER2 0 0x637 10 0 0 SDMA_UCODE_BUF_SED 0 1 SDMA_RB_CMD_BUF_SED 2 3 SDMA_IB_CMD_BUF_SED 4 5 SDMA_UTCL1_RD_FIFO_SED 6 7 SDMA_UTCL1_RDBST_FIFO_SED 8 9 SDMA_UTCL1_WR_FIFO_SED 10 11 SDMA_DATA_LUT_FIFO_SED 12 13 SDMA_SPLIT_DATA_BUF_SED 14 15 SDMA_MC_WR_ADDR_FIFO_SED 16 17 SDMA_MC_RDRET_BUF_SED 18 19 regSDMA1_STATUS2_REG 0 0x638 3 0 0 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 regSDMA1_ATOMIC_CNTL 0 0x639 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 regSDMA1_ATOMIC_PREOP_LO 0 0x63a 1 0 0 DATA 0 31 regSDMA1_ATOMIC_PREOP_HI 0 0x63b 1 0 0 DATA 0 31 regSDMA1_UTCL1_CNTL 0 0x63c 6 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 regSDMA1_UTCL1_WATERMK 0 0x63d 5 0 0 REQ_WATERMK 0 2 REQ_DEPTH 3 4 PAGE_WATERMK 5 7 INVREQ_WATERMK 8 15 RESERVED 16 31 regSDMA1_UTCL1_RD_STATUS 0 0x63e 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 regSDMA1_UTCL1_WR_STATUS 0 0x63f 28 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 regSDMA1_UTCL1_INV0 0 0x640 14 0 0 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 regSDMA1_UTCL1_INV1 0 0x641 1 0 0 INV_ADDR_LO 0 31 regSDMA1_UTCL1_INV2 0 0x642 1 0 0 INV_NFLUSH_VMID_VEC 0 31 regSDMA1_UTCL1_RD_XNACK0 0 0x643 1 0 0 XNACK_ADDR_LO 0 31 regSDMA1_UTCL1_RD_XNACK1 0 0x644 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA1_UTCL1_WR_XNACK0 0 0x645 1 0 0 XNACK_ADDR_LO 0 31 regSDMA1_UTCL1_WR_XNACK1 0 0x646 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA1_UTCL1_TIMEOUT 0 0x647 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 regSDMA1_UTCL1_PAGE 0 0x648 4 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 regSDMA1_POWER_CNTL_IDLE 0 0x649 3 0 0 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 regSDMA1_RELAX_ORDERING_LUT 0 0x64a 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 regSDMA1_CHICKEN_BITS_2 0 0x64b 2 0 0 F32_CMD_PROC_DELAY 0 3 F32_SEND_POSTCODE_EN 4 4 regSDMA1_STATUS3_REG 0 0x64c 5 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 regSDMA1_PHYSICAL_ADDR_LO 0 0x64d 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 regSDMA1_PHYSICAL_ADDR_HI 0 0x64e 1 0 0 ADDR 0 15 regSDMA1_PHASE2_QUANTUM 0 0x64f 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA1_ERROR_LOG 0 0x650 2 0 0 OVERRIDE 0 15 STATUS 16 31 regSDMA1_PUB_DUMMY_REG0 0 0x651 1 0 0 VALUE 0 31 regSDMA1_PUB_DUMMY_REG1 0 0x652 1 0 0 VALUE 0 31 regSDMA1_PUB_DUMMY_REG2 0 0x653 1 0 0 VALUE 0 31 regSDMA1_PUB_DUMMY_REG3 0 0x654 1 0 0 VALUE 0 31 regSDMA1_F32_COUNTER 0 0x655 1 0 0 VALUE 0 31 regSDMA1_PERFCNT_PERFCOUNTER0_CFG 0 0x657 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA1_PERFCNT_PERFCOUNTER1_CFG 0 0x658 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x659 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regSDMA1_PERFCNT_MISC_CNTL 0 0x65a 1 0 0 CMD_OP 0 15 regSDMA1_PERFCNT_PERFCOUNTER_LO 0 0x65b 1 0 0 COUNTER_LO 0 31 regSDMA1_PERFCNT_PERFCOUNTER_HI 0 0x65c 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regSDMA1_CRD_CNTL 0 0x65d 2 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 regSDMA1_ULV_CNTL 0 0x65f 6 0 0 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 regSDMA1_EA_DBIT_ADDR_DATA 0 0x660 1 0 0 VALUE 0 31 regSDMA1_EA_DBIT_ADDR_INDEX 0 0x661 1 0 0 VALUE 0 2 regSDMA1_STATUS4_REG 0 0x663 14 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 MMHUB_RD_OUTSTANDING 4 4 MMHUB_WR_OUTSTANDING 5 5 UTCL2_RD_OUTSTANDING 6 6 UTCL2_WR_OUTSTANDING 7 7 REG_POLLING 8 8 MEM_POLLING 9 9 UTCL2_RD_XNACK 10 11 UTCL2_WR_XNACK 12 13 ACTIVE_QUEUE_ID 14 17 SRIOV_WATING_RLCV_CMD 18 18 SRIOV_SDMA_EXECUTING_CMD 19 19 regSDMA1_SCRATCH_RAM_DATA 0 0x664 1 0 0 DATA 0 31 regSDMA1_SCRATCH_RAM_ADDR 0 0x665 1 0 0 ADDR 0 6 regSDMA1_CE_CTRL 0 0x666 4 0 0 RD_LUT_WATERMARK 0 2 RD_LUT_DEPTH 3 4 WR_AFIFO_WATERMARK 5 7 RESERVED 8 31 regSDMA1_RAS_STATUS 0 0x667 12 0 0 RB_FETCH_ECC 0 0 IB_FETCH_ECC 1 1 F32_DATA_ECC 2 2 SEM_WPTR_ATOMIC_ECC 3 3 COPY_DATA_ECC 4 4 SRAM_ECC 5 5 RB_FETCH_NACK_GEN_ERR 8 8 IB_FETCH_NACK_GEN_ERR 9 9 F32_DATA_NACK_GEN_ERR 10 10 COPY_DATA_NACK_GEN_ERR 11 11 WRRET_DATA_NACK_GEN_ERR 12 12 WPTR_RPTR_ATOMIC_NACK_GEN_ERR 13 13 regSDMA1_CLK_STATUS 0 0x668 4 0 0 DYN_CLK 0 0 PTR_CLK 1 1 REG_CLK 2 2 F32_CLK 3 3 regSDMA1_GFX_RB_CNTL 0 0x680 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_GFX_RB_BASE 0 0x681 1 0 0 ADDR 0 31 regSDMA1_GFX_RB_BASE_HI 0 0x682 1 0 0 ADDR 0 23 regSDMA1_GFX_RB_RPTR 0 0x683 1 0 0 OFFSET 0 31 regSDMA1_GFX_RB_RPTR_HI 0 0x684 1 0 0 OFFSET 0 31 regSDMA1_GFX_RB_WPTR 0 0x685 1 0 0 OFFSET 0 31 regSDMA1_GFX_RB_WPTR_HI 0 0x686 1 0 0 OFFSET 0 31 regSDMA1_GFX_RB_WPTR_POLL_CNTL 0 0x687 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_GFX_RB_RPTR_ADDR_HI 0 0x688 1 0 0 ADDR 0 31 regSDMA1_GFX_RB_RPTR_ADDR_LO 0 0x689 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_GFX_IB_CNTL 0 0x68a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_GFX_IB_RPTR 0 0x68b 1 0 0 OFFSET 2 21 regSDMA1_GFX_IB_OFFSET 0 0x68c 1 0 0 OFFSET 2 21 regSDMA1_GFX_IB_BASE_LO 0 0x68d 1 0 0 ADDR 5 31 regSDMA1_GFX_IB_BASE_HI 0 0x68e 1 0 0 ADDR 0 31 regSDMA1_GFX_IB_SIZE 0 0x68f 1 0 0 SIZE 0 19 regSDMA1_GFX_SKIP_CNTL 0 0x690 1 0 0 SKIP_COUNT 0 19 regSDMA1_GFX_CONTEXT_STATUS 0 0x691 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_GFX_DOORBELL 0 0x692 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_GFX_CONTEXT_CNTL 0 0x693 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 regSDMA1_GFX_STATUS 0 0x6a8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_GFX_DOORBELL_LOG 0 0x6a9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_GFX_WATERMARK 0 0x6aa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_GFX_DOORBELL_OFFSET 0 0x6ab 1 0 0 OFFSET 2 27 regSDMA1_GFX_CSA_ADDR_LO 0 0x6ac 1 0 0 ADDR 2 31 regSDMA1_GFX_CSA_ADDR_HI 0 0x6ad 1 0 0 ADDR 0 31 regSDMA1_GFX_IB_SUB_REMAIN 0 0x6af 1 0 0 SIZE 0 19 regSDMA1_GFX_PREEMPT 0 0x6b0 1 0 0 IB_PREEMPT 0 0 regSDMA1_GFX_DUMMY_REG 0 0x6b1 1 0 0 DUMMY 0 31 regSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0 0x6b2 1 0 0 ADDR 0 31 regSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0 0x6b3 1 0 0 ADDR 2 31 regSDMA1_GFX_RB_AQL_CNTL 0 0x6b4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_GFX_MINOR_PTR_UPDATE 0 0x6b5 1 0 0 ENABLE 0 0 regSDMA1_GFX_MIDCMD_DATA0 0 0x6c0 1 0 0 DATA0 0 31 regSDMA1_GFX_MIDCMD_DATA1 0 0x6c1 1 0 0 DATA1 0 31 regSDMA1_GFX_MIDCMD_DATA2 0 0x6c2 1 0 0 DATA2 0 31 regSDMA1_GFX_MIDCMD_DATA3 0 0x6c3 1 0 0 DATA3 0 31 regSDMA1_GFX_MIDCMD_DATA4 0 0x6c4 1 0 0 DATA4 0 31 regSDMA1_GFX_MIDCMD_DATA5 0 0x6c5 1 0 0 DATA5 0 31 regSDMA1_GFX_MIDCMD_DATA6 0 0x6c6 1 0 0 DATA6 0 31 regSDMA1_GFX_MIDCMD_DATA7 0 0x6c7 1 0 0 DATA7 0 31 regSDMA1_GFX_MIDCMD_DATA8 0 0x6c8 1 0 0 DATA8 0 31 regSDMA1_GFX_MIDCMD_DATA9 0 0x6c9 1 0 0 DATA9 0 31 regSDMA1_GFX_MIDCMD_DATA10 0 0x6ca 1 0 0 DATA10 0 31 regSDMA1_GFX_MIDCMD_CNTL 0 0x6cb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_PAGE_RB_CNTL 0 0x6d8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_PAGE_RB_BASE 0 0x6d9 1 0 0 ADDR 0 31 regSDMA1_PAGE_RB_BASE_HI 0 0x6da 1 0 0 ADDR 0 23 regSDMA1_PAGE_RB_RPTR 0 0x6db 1 0 0 OFFSET 0 31 regSDMA1_PAGE_RB_RPTR_HI 0 0x6dc 1 0 0 OFFSET 0 31 regSDMA1_PAGE_RB_WPTR 0 0x6dd 1 0 0 OFFSET 0 31 regSDMA1_PAGE_RB_WPTR_HI 0 0x6de 1 0 0 OFFSET 0 31 regSDMA1_PAGE_RB_WPTR_POLL_CNTL 0 0x6df 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_PAGE_RB_RPTR_ADDR_HI 0 0x6e0 1 0 0 ADDR 0 31 regSDMA1_PAGE_RB_RPTR_ADDR_LO 0 0x6e1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_PAGE_IB_CNTL 0 0x6e2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_PAGE_IB_RPTR 0 0x6e3 1 0 0 OFFSET 2 21 regSDMA1_PAGE_IB_OFFSET 0 0x6e4 1 0 0 OFFSET 2 21 regSDMA1_PAGE_IB_BASE_LO 0 0x6e5 1 0 0 ADDR 5 31 regSDMA1_PAGE_IB_BASE_HI 0 0x6e6 1 0 0 ADDR 0 31 regSDMA1_PAGE_IB_SIZE 0 0x6e7 1 0 0 SIZE 0 19 regSDMA1_PAGE_SKIP_CNTL 0 0x6e8 1 0 0 SKIP_COUNT 0 19 regSDMA1_PAGE_CONTEXT_STATUS 0 0x6e9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_PAGE_DOORBELL 0 0x6ea 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_PAGE_STATUS 0 0x700 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_PAGE_DOORBELL_LOG 0 0x701 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_PAGE_WATERMARK 0 0x702 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_PAGE_DOORBELL_OFFSET 0 0x703 1 0 0 OFFSET 2 27 regSDMA1_PAGE_CSA_ADDR_LO 0 0x704 1 0 0 ADDR 2 31 regSDMA1_PAGE_CSA_ADDR_HI 0 0x705 1 0 0 ADDR 0 31 regSDMA1_PAGE_IB_SUB_REMAIN 0 0x707 1 0 0 SIZE 0 19 regSDMA1_PAGE_PREEMPT 0 0x708 1 0 0 IB_PREEMPT 0 0 regSDMA1_PAGE_DUMMY_REG 0 0x709 1 0 0 DUMMY 0 31 regSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x70a 1 0 0 ADDR 0 31 regSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x70b 1 0 0 ADDR 2 31 regSDMA1_PAGE_RB_AQL_CNTL 0 0x70c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_PAGE_MINOR_PTR_UPDATE 0 0x70d 1 0 0 ENABLE 0 0 regSDMA1_PAGE_MIDCMD_DATA0 0 0x718 1 0 0 DATA0 0 31 regSDMA1_PAGE_MIDCMD_DATA1 0 0x719 1 0 0 DATA1 0 31 regSDMA1_PAGE_MIDCMD_DATA2 0 0x71a 1 0 0 DATA2 0 31 regSDMA1_PAGE_MIDCMD_DATA3 0 0x71b 1 0 0 DATA3 0 31 regSDMA1_PAGE_MIDCMD_DATA4 0 0x71c 1 0 0 DATA4 0 31 regSDMA1_PAGE_MIDCMD_DATA5 0 0x71d 1 0 0 DATA5 0 31 regSDMA1_PAGE_MIDCMD_DATA6 0 0x71e 1 0 0 DATA6 0 31 regSDMA1_PAGE_MIDCMD_DATA7 0 0x71f 1 0 0 DATA7 0 31 regSDMA1_PAGE_MIDCMD_DATA8 0 0x720 1 0 0 DATA8 0 31 regSDMA1_PAGE_MIDCMD_DATA9 0 0x721 1 0 0 DATA9 0 31 regSDMA1_PAGE_MIDCMD_DATA10 0 0x722 1 0 0 DATA10 0 31 regSDMA1_PAGE_MIDCMD_CNTL 0 0x723 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC0_RB_CNTL 0 0x730 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC0_RB_BASE 0 0x731 1 0 0 ADDR 0 31 regSDMA1_RLC0_RB_BASE_HI 0 0x732 1 0 0 ADDR 0 23 regSDMA1_RLC0_RB_RPTR 0 0x733 1 0 0 OFFSET 0 31 regSDMA1_RLC0_RB_RPTR_HI 0 0x734 1 0 0 OFFSET 0 31 regSDMA1_RLC0_RB_WPTR 0 0x735 1 0 0 OFFSET 0 31 regSDMA1_RLC0_RB_WPTR_HI 0 0x736 1 0 0 OFFSET 0 31 regSDMA1_RLC0_RB_WPTR_POLL_CNTL 0 0x737 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC0_RB_RPTR_ADDR_HI 0 0x738 1 0 0 ADDR 0 31 regSDMA1_RLC0_RB_RPTR_ADDR_LO 0 0x739 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC0_IB_CNTL 0 0x73a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC0_IB_RPTR 0 0x73b 1 0 0 OFFSET 2 21 regSDMA1_RLC0_IB_OFFSET 0 0x73c 1 0 0 OFFSET 2 21 regSDMA1_RLC0_IB_BASE_LO 0 0x73d 1 0 0 ADDR 5 31 regSDMA1_RLC0_IB_BASE_HI 0 0x73e 1 0 0 ADDR 0 31 regSDMA1_RLC0_IB_SIZE 0 0x73f 1 0 0 SIZE 0 19 regSDMA1_RLC0_SKIP_CNTL 0 0x740 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC0_CONTEXT_STATUS 0 0x741 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC0_DOORBELL 0 0x742 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC0_STATUS 0 0x758 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC0_DOORBELL_LOG 0 0x759 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC0_WATERMARK 0 0x75a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC0_DOORBELL_OFFSET 0 0x75b 1 0 0 OFFSET 2 27 regSDMA1_RLC0_CSA_ADDR_LO 0 0x75c 1 0 0 ADDR 2 31 regSDMA1_RLC0_CSA_ADDR_HI 0 0x75d 1 0 0 ADDR 0 31 regSDMA1_RLC0_IB_SUB_REMAIN 0 0x75f 1 0 0 SIZE 0 19 regSDMA1_RLC0_PREEMPT 0 0x760 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC0_DUMMY_REG 0 0x761 1 0 0 DUMMY 0 31 regSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x762 1 0 0 ADDR 0 31 regSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x763 1 0 0 ADDR 2 31 regSDMA1_RLC0_RB_AQL_CNTL 0 0x764 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC0_MINOR_PTR_UPDATE 0 0x765 1 0 0 ENABLE 0 0 regSDMA1_RLC0_MIDCMD_DATA0 0 0x770 1 0 0 DATA0 0 31 regSDMA1_RLC0_MIDCMD_DATA1 0 0x771 1 0 0 DATA1 0 31 regSDMA1_RLC0_MIDCMD_DATA2 0 0x772 1 0 0 DATA2 0 31 regSDMA1_RLC0_MIDCMD_DATA3 0 0x773 1 0 0 DATA3 0 31 regSDMA1_RLC0_MIDCMD_DATA4 0 0x774 1 0 0 DATA4 0 31 regSDMA1_RLC0_MIDCMD_DATA5 0 0x775 1 0 0 DATA5 0 31 regSDMA1_RLC0_MIDCMD_DATA6 0 0x776 1 0 0 DATA6 0 31 regSDMA1_RLC0_MIDCMD_DATA7 0 0x777 1 0 0 DATA7 0 31 regSDMA1_RLC0_MIDCMD_DATA8 0 0x778 1 0 0 DATA8 0 31 regSDMA1_RLC0_MIDCMD_DATA9 0 0x779 1 0 0 DATA9 0 31 regSDMA1_RLC0_MIDCMD_DATA10 0 0x77a 1 0 0 DATA10 0 31 regSDMA1_RLC0_MIDCMD_CNTL 0 0x77b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC1_RB_CNTL 0 0x788 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC1_RB_BASE 0 0x789 1 0 0 ADDR 0 31 regSDMA1_RLC1_RB_BASE_HI 0 0x78a 1 0 0 ADDR 0 23 regSDMA1_RLC1_RB_RPTR 0 0x78b 1 0 0 OFFSET 0 31 regSDMA1_RLC1_RB_RPTR_HI 0 0x78c 1 0 0 OFFSET 0 31 regSDMA1_RLC1_RB_WPTR 0 0x78d 1 0 0 OFFSET 0 31 regSDMA1_RLC1_RB_WPTR_HI 0 0x78e 1 0 0 OFFSET 0 31 regSDMA1_RLC1_RB_WPTR_POLL_CNTL 0 0x78f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC1_RB_RPTR_ADDR_HI 0 0x790 1 0 0 ADDR 0 31 regSDMA1_RLC1_RB_RPTR_ADDR_LO 0 0x791 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC1_IB_CNTL 0 0x792 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC1_IB_RPTR 0 0x793 1 0 0 OFFSET 2 21 regSDMA1_RLC1_IB_OFFSET 0 0x794 1 0 0 OFFSET 2 21 regSDMA1_RLC1_IB_BASE_LO 0 0x795 1 0 0 ADDR 5 31 regSDMA1_RLC1_IB_BASE_HI 0 0x796 1 0 0 ADDR 0 31 regSDMA1_RLC1_IB_SIZE 0 0x797 1 0 0 SIZE 0 19 regSDMA1_RLC1_SKIP_CNTL 0 0x798 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC1_CONTEXT_STATUS 0 0x799 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC1_DOORBELL 0 0x79a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC1_STATUS 0 0x7b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC1_DOORBELL_LOG 0 0x7b1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC1_WATERMARK 0 0x7b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC1_DOORBELL_OFFSET 0 0x7b3 1 0 0 OFFSET 2 27 regSDMA1_RLC1_CSA_ADDR_LO 0 0x7b4 1 0 0 ADDR 2 31 regSDMA1_RLC1_CSA_ADDR_HI 0 0x7b5 1 0 0 ADDR 0 31 regSDMA1_RLC1_IB_SUB_REMAIN 0 0x7b7 1 0 0 SIZE 0 19 regSDMA1_RLC1_PREEMPT 0 0x7b8 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC1_DUMMY_REG 0 0x7b9 1 0 0 DUMMY 0 31 regSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x7ba 1 0 0 ADDR 0 31 regSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x7bb 1 0 0 ADDR 2 31 regSDMA1_RLC1_RB_AQL_CNTL 0 0x7bc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC1_MINOR_PTR_UPDATE 0 0x7bd 1 0 0 ENABLE 0 0 regSDMA1_RLC1_MIDCMD_DATA0 0 0x7c8 1 0 0 DATA0 0 31 regSDMA1_RLC1_MIDCMD_DATA1 0 0x7c9 1 0 0 DATA1 0 31 regSDMA1_RLC1_MIDCMD_DATA2 0 0x7ca 1 0 0 DATA2 0 31 regSDMA1_RLC1_MIDCMD_DATA3 0 0x7cb 1 0 0 DATA3 0 31 regSDMA1_RLC1_MIDCMD_DATA4 0 0x7cc 1 0 0 DATA4 0 31 regSDMA1_RLC1_MIDCMD_DATA5 0 0x7cd 1 0 0 DATA5 0 31 regSDMA1_RLC1_MIDCMD_DATA6 0 0x7ce 1 0 0 DATA6 0 31 regSDMA1_RLC1_MIDCMD_DATA7 0 0x7cf 1 0 0 DATA7 0 31 regSDMA1_RLC1_MIDCMD_DATA8 0 0x7d0 1 0 0 DATA8 0 31 regSDMA1_RLC1_MIDCMD_DATA9 0 0x7d1 1 0 0 DATA9 0 31 regSDMA1_RLC1_MIDCMD_DATA10 0 0x7d2 1 0 0 DATA10 0 31 regSDMA1_RLC1_MIDCMD_CNTL 0 0x7d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC2_RB_CNTL 0 0x7e0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC2_RB_BASE 0 0x7e1 1 0 0 ADDR 0 31 regSDMA1_RLC2_RB_BASE_HI 0 0x7e2 1 0 0 ADDR 0 23 regSDMA1_RLC2_RB_RPTR 0 0x7e3 1 0 0 OFFSET 0 31 regSDMA1_RLC2_RB_RPTR_HI 0 0x7e4 1 0 0 OFFSET 0 31 regSDMA1_RLC2_RB_WPTR 0 0x7e5 1 0 0 OFFSET 0 31 regSDMA1_RLC2_RB_WPTR_HI 0 0x7e6 1 0 0 OFFSET 0 31 regSDMA1_RLC2_RB_WPTR_POLL_CNTL 0 0x7e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC2_RB_RPTR_ADDR_HI 0 0x7e8 1 0 0 ADDR 0 31 regSDMA1_RLC2_RB_RPTR_ADDR_LO 0 0x7e9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC2_IB_CNTL 0 0x7ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC2_IB_RPTR 0 0x7eb 1 0 0 OFFSET 2 21 regSDMA1_RLC2_IB_OFFSET 0 0x7ec 1 0 0 OFFSET 2 21 regSDMA1_RLC2_IB_BASE_LO 0 0x7ed 1 0 0 ADDR 5 31 regSDMA1_RLC2_IB_BASE_HI 0 0x7ee 1 0 0 ADDR 0 31 regSDMA1_RLC2_IB_SIZE 0 0x7ef 1 0 0 SIZE 0 19 regSDMA1_RLC2_SKIP_CNTL 0 0x7f0 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC2_CONTEXT_STATUS 0 0x7f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC2_DOORBELL 0 0x7f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC2_STATUS 0 0x808 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC2_DOORBELL_LOG 0 0x809 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC2_WATERMARK 0 0x80a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC2_DOORBELL_OFFSET 0 0x80b 1 0 0 OFFSET 2 27 regSDMA1_RLC2_CSA_ADDR_LO 0 0x80c 1 0 0 ADDR 2 31 regSDMA1_RLC2_CSA_ADDR_HI 0 0x80d 1 0 0 ADDR 0 31 regSDMA1_RLC2_IB_SUB_REMAIN 0 0x80f 1 0 0 SIZE 0 19 regSDMA1_RLC2_PREEMPT 0 0x810 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC2_DUMMY_REG 0 0x811 1 0 0 DUMMY 0 31 regSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x812 1 0 0 ADDR 0 31 regSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x813 1 0 0 ADDR 2 31 regSDMA1_RLC2_RB_AQL_CNTL 0 0x814 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC2_MINOR_PTR_UPDATE 0 0x815 1 0 0 ENABLE 0 0 regSDMA1_RLC2_MIDCMD_DATA0 0 0x820 1 0 0 DATA0 0 31 regSDMA1_RLC2_MIDCMD_DATA1 0 0x821 1 0 0 DATA1 0 31 regSDMA1_RLC2_MIDCMD_DATA2 0 0x822 1 0 0 DATA2 0 31 regSDMA1_RLC2_MIDCMD_DATA3 0 0x823 1 0 0 DATA3 0 31 regSDMA1_RLC2_MIDCMD_DATA4 0 0x824 1 0 0 DATA4 0 31 regSDMA1_RLC2_MIDCMD_DATA5 0 0x825 1 0 0 DATA5 0 31 regSDMA1_RLC2_MIDCMD_DATA6 0 0x826 1 0 0 DATA6 0 31 regSDMA1_RLC2_MIDCMD_DATA7 0 0x827 1 0 0 DATA7 0 31 regSDMA1_RLC2_MIDCMD_DATA8 0 0x828 1 0 0 DATA8 0 31 regSDMA1_RLC2_MIDCMD_DATA9 0 0x829 1 0 0 DATA9 0 31 regSDMA1_RLC2_MIDCMD_DATA10 0 0x82a 1 0 0 DATA10 0 31 regSDMA1_RLC2_MIDCMD_CNTL 0 0x82b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC3_RB_CNTL 0 0x838 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC3_RB_BASE 0 0x839 1 0 0 ADDR 0 31 regSDMA1_RLC3_RB_BASE_HI 0 0x83a 1 0 0 ADDR 0 23 regSDMA1_RLC3_RB_RPTR 0 0x83b 1 0 0 OFFSET 0 31 regSDMA1_RLC3_RB_RPTR_HI 0 0x83c 1 0 0 OFFSET 0 31 regSDMA1_RLC3_RB_WPTR 0 0x83d 1 0 0 OFFSET 0 31 regSDMA1_RLC3_RB_WPTR_HI 0 0x83e 1 0 0 OFFSET 0 31 regSDMA1_RLC3_RB_WPTR_POLL_CNTL 0 0x83f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC3_RB_RPTR_ADDR_HI 0 0x840 1 0 0 ADDR 0 31 regSDMA1_RLC3_RB_RPTR_ADDR_LO 0 0x841 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC3_IB_CNTL 0 0x842 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC3_IB_RPTR 0 0x843 1 0 0 OFFSET 2 21 regSDMA1_RLC3_IB_OFFSET 0 0x844 1 0 0 OFFSET 2 21 regSDMA1_RLC3_IB_BASE_LO 0 0x845 1 0 0 ADDR 5 31 regSDMA1_RLC3_IB_BASE_HI 0 0x846 1 0 0 ADDR 0 31 regSDMA1_RLC3_IB_SIZE 0 0x847 1 0 0 SIZE 0 19 regSDMA1_RLC3_SKIP_CNTL 0 0x848 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC3_CONTEXT_STATUS 0 0x849 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC3_DOORBELL 0 0x84a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC3_STATUS 0 0x860 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC3_DOORBELL_LOG 0 0x861 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC3_WATERMARK 0 0x862 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC3_DOORBELL_OFFSET 0 0x863 1 0 0 OFFSET 2 27 regSDMA1_RLC3_CSA_ADDR_LO 0 0x864 1 0 0 ADDR 2 31 regSDMA1_RLC3_CSA_ADDR_HI 0 0x865 1 0 0 ADDR 0 31 regSDMA1_RLC3_IB_SUB_REMAIN 0 0x867 1 0 0 SIZE 0 19 regSDMA1_RLC3_PREEMPT 0 0x868 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC3_DUMMY_REG 0 0x869 1 0 0 DUMMY 0 31 regSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x86a 1 0 0 ADDR 0 31 regSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x86b 1 0 0 ADDR 2 31 regSDMA1_RLC3_RB_AQL_CNTL 0 0x86c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC3_MINOR_PTR_UPDATE 0 0x86d 1 0 0 ENABLE 0 0 regSDMA1_RLC3_MIDCMD_DATA0 0 0x878 1 0 0 DATA0 0 31 regSDMA1_RLC3_MIDCMD_DATA1 0 0x879 1 0 0 DATA1 0 31 regSDMA1_RLC3_MIDCMD_DATA2 0 0x87a 1 0 0 DATA2 0 31 regSDMA1_RLC3_MIDCMD_DATA3 0 0x87b 1 0 0 DATA3 0 31 regSDMA1_RLC3_MIDCMD_DATA4 0 0x87c 1 0 0 DATA4 0 31 regSDMA1_RLC3_MIDCMD_DATA5 0 0x87d 1 0 0 DATA5 0 31 regSDMA1_RLC3_MIDCMD_DATA6 0 0x87e 1 0 0 DATA6 0 31 regSDMA1_RLC3_MIDCMD_DATA7 0 0x87f 1 0 0 DATA7 0 31 regSDMA1_RLC3_MIDCMD_DATA8 0 0x880 1 0 0 DATA8 0 31 regSDMA1_RLC3_MIDCMD_DATA9 0 0x881 1 0 0 DATA9 0 31 regSDMA1_RLC3_MIDCMD_DATA10 0 0x882 1 0 0 DATA10 0 31 regSDMA1_RLC3_MIDCMD_CNTL 0 0x883 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC4_RB_CNTL 0 0x890 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC4_RB_BASE 0 0x891 1 0 0 ADDR 0 31 regSDMA1_RLC4_RB_BASE_HI 0 0x892 1 0 0 ADDR 0 23 regSDMA1_RLC4_RB_RPTR 0 0x893 1 0 0 OFFSET 0 31 regSDMA1_RLC4_RB_RPTR_HI 0 0x894 1 0 0 OFFSET 0 31 regSDMA1_RLC4_RB_WPTR 0 0x895 1 0 0 OFFSET 0 31 regSDMA1_RLC4_RB_WPTR_HI 0 0x896 1 0 0 OFFSET 0 31 regSDMA1_RLC4_RB_WPTR_POLL_CNTL 0 0x897 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC4_RB_RPTR_ADDR_HI 0 0x898 1 0 0 ADDR 0 31 regSDMA1_RLC4_RB_RPTR_ADDR_LO 0 0x899 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC4_IB_CNTL 0 0x89a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC4_IB_RPTR 0 0x89b 1 0 0 OFFSET 2 21 regSDMA1_RLC4_IB_OFFSET 0 0x89c 1 0 0 OFFSET 2 21 regSDMA1_RLC4_IB_BASE_LO 0 0x89d 1 0 0 ADDR 5 31 regSDMA1_RLC4_IB_BASE_HI 0 0x89e 1 0 0 ADDR 0 31 regSDMA1_RLC4_IB_SIZE 0 0x89f 1 0 0 SIZE 0 19 regSDMA1_RLC4_SKIP_CNTL 0 0x8a0 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC4_CONTEXT_STATUS 0 0x8a1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC4_DOORBELL 0 0x8a2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC4_STATUS 0 0x8b8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC4_DOORBELL_LOG 0 0x8b9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC4_WATERMARK 0 0x8ba 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC4_DOORBELL_OFFSET 0 0x8bb 1 0 0 OFFSET 2 27 regSDMA1_RLC4_CSA_ADDR_LO 0 0x8bc 1 0 0 ADDR 2 31 regSDMA1_RLC4_CSA_ADDR_HI 0 0x8bd 1 0 0 ADDR 0 31 regSDMA1_RLC4_IB_SUB_REMAIN 0 0x8bf 1 0 0 SIZE 0 19 regSDMA1_RLC4_PREEMPT 0 0x8c0 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC4_DUMMY_REG 0 0x8c1 1 0 0 DUMMY 0 31 regSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x8c2 1 0 0 ADDR 0 31 regSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x8c3 1 0 0 ADDR 2 31 regSDMA1_RLC4_RB_AQL_CNTL 0 0x8c4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC4_MINOR_PTR_UPDATE 0 0x8c5 1 0 0 ENABLE 0 0 regSDMA1_RLC4_MIDCMD_DATA0 0 0x8d0 1 0 0 DATA0 0 31 regSDMA1_RLC4_MIDCMD_DATA1 0 0x8d1 1 0 0 DATA1 0 31 regSDMA1_RLC4_MIDCMD_DATA2 0 0x8d2 1 0 0 DATA2 0 31 regSDMA1_RLC4_MIDCMD_DATA3 0 0x8d3 1 0 0 DATA3 0 31 regSDMA1_RLC4_MIDCMD_DATA4 0 0x8d4 1 0 0 DATA4 0 31 regSDMA1_RLC4_MIDCMD_DATA5 0 0x8d5 1 0 0 DATA5 0 31 regSDMA1_RLC4_MIDCMD_DATA6 0 0x8d6 1 0 0 DATA6 0 31 regSDMA1_RLC4_MIDCMD_DATA7 0 0x8d7 1 0 0 DATA7 0 31 regSDMA1_RLC4_MIDCMD_DATA8 0 0x8d8 1 0 0 DATA8 0 31 regSDMA1_RLC4_MIDCMD_DATA9 0 0x8d9 1 0 0 DATA9 0 31 regSDMA1_RLC4_MIDCMD_DATA10 0 0x8da 1 0 0 DATA10 0 31 regSDMA1_RLC4_MIDCMD_CNTL 0 0x8db 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC5_RB_CNTL 0 0x8e8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC5_RB_BASE 0 0x8e9 1 0 0 ADDR 0 31 regSDMA1_RLC5_RB_BASE_HI 0 0x8ea 1 0 0 ADDR 0 23 regSDMA1_RLC5_RB_RPTR 0 0x8eb 1 0 0 OFFSET 0 31 regSDMA1_RLC5_RB_RPTR_HI 0 0x8ec 1 0 0 OFFSET 0 31 regSDMA1_RLC5_RB_WPTR 0 0x8ed 1 0 0 OFFSET 0 31 regSDMA1_RLC5_RB_WPTR_HI 0 0x8ee 1 0 0 OFFSET 0 31 regSDMA1_RLC5_RB_WPTR_POLL_CNTL 0 0x8ef 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC5_RB_RPTR_ADDR_HI 0 0x8f0 1 0 0 ADDR 0 31 regSDMA1_RLC5_RB_RPTR_ADDR_LO 0 0x8f1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC5_IB_CNTL 0 0x8f2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC5_IB_RPTR 0 0x8f3 1 0 0 OFFSET 2 21 regSDMA1_RLC5_IB_OFFSET 0 0x8f4 1 0 0 OFFSET 2 21 regSDMA1_RLC5_IB_BASE_LO 0 0x8f5 1 0 0 ADDR 5 31 regSDMA1_RLC5_IB_BASE_HI 0 0x8f6 1 0 0 ADDR 0 31 regSDMA1_RLC5_IB_SIZE 0 0x8f7 1 0 0 SIZE 0 19 regSDMA1_RLC5_SKIP_CNTL 0 0x8f8 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC5_CONTEXT_STATUS 0 0x8f9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC5_DOORBELL 0 0x8fa 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC5_STATUS 0 0x910 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC5_DOORBELL_LOG 0 0x911 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC5_WATERMARK 0 0x912 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC5_DOORBELL_OFFSET 0 0x913 1 0 0 OFFSET 2 27 regSDMA1_RLC5_CSA_ADDR_LO 0 0x914 1 0 0 ADDR 2 31 regSDMA1_RLC5_CSA_ADDR_HI 0 0x915 1 0 0 ADDR 0 31 regSDMA1_RLC5_IB_SUB_REMAIN 0 0x917 1 0 0 SIZE 0 19 regSDMA1_RLC5_PREEMPT 0 0x918 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC5_DUMMY_REG 0 0x919 1 0 0 DUMMY 0 31 regSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x91a 1 0 0 ADDR 0 31 regSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x91b 1 0 0 ADDR 2 31 regSDMA1_RLC5_RB_AQL_CNTL 0 0x91c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC5_MINOR_PTR_UPDATE 0 0x91d 1 0 0 ENABLE 0 0 regSDMA1_RLC5_MIDCMD_DATA0 0 0x928 1 0 0 DATA0 0 31 regSDMA1_RLC5_MIDCMD_DATA1 0 0x929 1 0 0 DATA1 0 31 regSDMA1_RLC5_MIDCMD_DATA2 0 0x92a 1 0 0 DATA2 0 31 regSDMA1_RLC5_MIDCMD_DATA3 0 0x92b 1 0 0 DATA3 0 31 regSDMA1_RLC5_MIDCMD_DATA4 0 0x92c 1 0 0 DATA4 0 31 regSDMA1_RLC5_MIDCMD_DATA5 0 0x92d 1 0 0 DATA5 0 31 regSDMA1_RLC5_MIDCMD_DATA6 0 0x92e 1 0 0 DATA6 0 31 regSDMA1_RLC5_MIDCMD_DATA7 0 0x92f 1 0 0 DATA7 0 31 regSDMA1_RLC5_MIDCMD_DATA8 0 0x930 1 0 0 DATA8 0 31 regSDMA1_RLC5_MIDCMD_DATA9 0 0x931 1 0 0 DATA9 0 31 regSDMA1_RLC5_MIDCMD_DATA10 0 0x932 1 0 0 DATA10 0 31 regSDMA1_RLC5_MIDCMD_CNTL 0 0x933 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC6_RB_CNTL 0 0x940 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC6_RB_BASE 0 0x941 1 0 0 ADDR 0 31 regSDMA1_RLC6_RB_BASE_HI 0 0x942 1 0 0 ADDR 0 23 regSDMA1_RLC6_RB_RPTR 0 0x943 1 0 0 OFFSET 0 31 regSDMA1_RLC6_RB_RPTR_HI 0 0x944 1 0 0 OFFSET 0 31 regSDMA1_RLC6_RB_WPTR 0 0x945 1 0 0 OFFSET 0 31 regSDMA1_RLC6_RB_WPTR_HI 0 0x946 1 0 0 OFFSET 0 31 regSDMA1_RLC6_RB_WPTR_POLL_CNTL 0 0x947 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC6_RB_RPTR_ADDR_HI 0 0x948 1 0 0 ADDR 0 31 regSDMA1_RLC6_RB_RPTR_ADDR_LO 0 0x949 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC6_IB_CNTL 0 0x94a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC6_IB_RPTR 0 0x94b 1 0 0 OFFSET 2 21 regSDMA1_RLC6_IB_OFFSET 0 0x94c 1 0 0 OFFSET 2 21 regSDMA1_RLC6_IB_BASE_LO 0 0x94d 1 0 0 ADDR 5 31 regSDMA1_RLC6_IB_BASE_HI 0 0x94e 1 0 0 ADDR 0 31 regSDMA1_RLC6_IB_SIZE 0 0x94f 1 0 0 SIZE 0 19 regSDMA1_RLC6_SKIP_CNTL 0 0x950 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC6_CONTEXT_STATUS 0 0x951 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC6_DOORBELL 0 0x952 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC6_STATUS 0 0x968 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC6_DOORBELL_LOG 0 0x969 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC6_WATERMARK 0 0x96a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC6_DOORBELL_OFFSET 0 0x96b 1 0 0 OFFSET 2 27 regSDMA1_RLC6_CSA_ADDR_LO 0 0x96c 1 0 0 ADDR 2 31 regSDMA1_RLC6_CSA_ADDR_HI 0 0x96d 1 0 0 ADDR 0 31 regSDMA1_RLC6_IB_SUB_REMAIN 0 0x96f 1 0 0 SIZE 0 19 regSDMA1_RLC6_PREEMPT 0 0x970 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC6_DUMMY_REG 0 0x971 1 0 0 DUMMY 0 31 regSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x972 1 0 0 ADDR 0 31 regSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x973 1 0 0 ADDR 2 31 regSDMA1_RLC6_RB_AQL_CNTL 0 0x974 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC6_MINOR_PTR_UPDATE 0 0x975 1 0 0 ENABLE 0 0 regSDMA1_RLC6_MIDCMD_DATA0 0 0x980 1 0 0 DATA0 0 31 regSDMA1_RLC6_MIDCMD_DATA1 0 0x981 1 0 0 DATA1 0 31 regSDMA1_RLC6_MIDCMD_DATA2 0 0x982 1 0 0 DATA2 0 31 regSDMA1_RLC6_MIDCMD_DATA3 0 0x983 1 0 0 DATA3 0 31 regSDMA1_RLC6_MIDCMD_DATA4 0 0x984 1 0 0 DATA4 0 31 regSDMA1_RLC6_MIDCMD_DATA5 0 0x985 1 0 0 DATA5 0 31 regSDMA1_RLC6_MIDCMD_DATA6 0 0x986 1 0 0 DATA6 0 31 regSDMA1_RLC6_MIDCMD_DATA7 0 0x987 1 0 0 DATA7 0 31 regSDMA1_RLC6_MIDCMD_DATA8 0 0x988 1 0 0 DATA8 0 31 regSDMA1_RLC6_MIDCMD_DATA9 0 0x989 1 0 0 DATA9 0 31 regSDMA1_RLC6_MIDCMD_DATA10 0 0x98a 1 0 0 DATA10 0 31 regSDMA1_RLC6_MIDCMD_CNTL 0 0x98b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA1_RLC7_RB_CNTL 0 0x998 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA1_RLC7_RB_BASE 0 0x999 1 0 0 ADDR 0 31 regSDMA1_RLC7_RB_BASE_HI 0 0x99a 1 0 0 ADDR 0 23 regSDMA1_RLC7_RB_RPTR 0 0x99b 1 0 0 OFFSET 0 31 regSDMA1_RLC7_RB_RPTR_HI 0 0x99c 1 0 0 OFFSET 0 31 regSDMA1_RLC7_RB_WPTR 0 0x99d 1 0 0 OFFSET 0 31 regSDMA1_RLC7_RB_WPTR_HI 0 0x99e 1 0 0 OFFSET 0 31 regSDMA1_RLC7_RB_WPTR_POLL_CNTL 0 0x99f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA1_RLC7_RB_RPTR_ADDR_HI 0 0x9a0 1 0 0 ADDR 0 31 regSDMA1_RLC7_RB_RPTR_ADDR_LO 0 0x9a1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA1_RLC7_IB_CNTL 0 0x9a2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA1_RLC7_IB_RPTR 0 0x9a3 1 0 0 OFFSET 2 21 regSDMA1_RLC7_IB_OFFSET 0 0x9a4 1 0 0 OFFSET 2 21 regSDMA1_RLC7_IB_BASE_LO 0 0x9a5 1 0 0 ADDR 5 31 regSDMA1_RLC7_IB_BASE_HI 0 0x9a6 1 0 0 ADDR 0 31 regSDMA1_RLC7_IB_SIZE 0 0x9a7 1 0 0 SIZE 0 19 regSDMA1_RLC7_SKIP_CNTL 0 0x9a8 1 0 0 SKIP_COUNT 0 19 regSDMA1_RLC7_CONTEXT_STATUS 0 0x9a9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA1_RLC7_DOORBELL 0 0x9aa 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA1_RLC7_STATUS 0 0x9c0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA1_RLC7_DOORBELL_LOG 0 0x9c1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA1_RLC7_WATERMARK 0 0x9c2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA1_RLC7_DOORBELL_OFFSET 0 0x9c3 1 0 0 OFFSET 2 27 regSDMA1_RLC7_CSA_ADDR_LO 0 0x9c4 1 0 0 ADDR 2 31 regSDMA1_RLC7_CSA_ADDR_HI 0 0x9c5 1 0 0 ADDR 0 31 regSDMA1_RLC7_IB_SUB_REMAIN 0 0x9c7 1 0 0 SIZE 0 19 regSDMA1_RLC7_PREEMPT 0 0x9c8 1 0 0 IB_PREEMPT 0 0 regSDMA1_RLC7_DUMMY_REG 0 0x9c9 1 0 0 DUMMY 0 31 regSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x9ca 1 0 0 ADDR 0 31 regSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x9cb 1 0 0 ADDR 2 31 regSDMA1_RLC7_RB_AQL_CNTL 0 0x9cc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA1_RLC7_MINOR_PTR_UPDATE 0 0x9cd 1 0 0 ENABLE 0 0 regSDMA1_RLC7_MIDCMD_DATA0 0 0x9d8 1 0 0 DATA0 0 31 regSDMA1_RLC7_MIDCMD_DATA1 0 0x9d9 1 0 0 DATA1 0 31 regSDMA1_RLC7_MIDCMD_DATA2 0 0x9da 1 0 0 DATA2 0 31 regSDMA1_RLC7_MIDCMD_DATA3 0 0x9db 1 0 0 DATA3 0 31 regSDMA1_RLC7_MIDCMD_DATA4 0 0x9dc 1 0 0 DATA4 0 31 regSDMA1_RLC7_MIDCMD_DATA5 0 0x9dd 1 0 0 DATA5 0 31 regSDMA1_RLC7_MIDCMD_DATA6 0 0x9de 1 0 0 DATA6 0 31 regSDMA1_RLC7_MIDCMD_DATA7 0 0x9df 1 0 0 DATA7 0 31 regSDMA1_RLC7_MIDCMD_DATA8 0 0x9e0 1 0 0 DATA8 0 31 regSDMA1_RLC7_MIDCMD_DATA9 0 0x9e1 1 0 0 DATA9 0 31 regSDMA1_RLC7_MIDCMD_DATA10 0 0x9e2 1 0 0 DATA10 0 31 regSDMA1_RLC7_MIDCMD_CNTL 0 0x9e3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_UCODE_ADDR 0 0x1cda0 1 0 0 VALUE 0 13 regSDMA2_UCODE_DATA 0 0x1cda1 1 0 0 VALUE 0 31 regSDMA2_VF_ENABLE 0 0x1cdaa 1 0 0 VF_ENABLE 0 0 regSDMA2_CONTEXT_GROUP_BOUNDARY 0 0x1cdb9 1 0 0 RESERVED 0 31 regSDMA2_POWER_CNTL 0 0x1cdba 10 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 ON_OFF_STATUS_DURATION_TIME 26 31 regSDMA2_CLK_CTRL 0 0x1cdbb 11 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSDMA2_CNTL 0 0x1cdbc 12 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_EXPIRE_ENABLE 6 6 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 regSDMA2_CHICKEN_BITS 0 0x1cdbd 12 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 SRAM_FGCG_ENABLE 26 26 RESERVED 27 31 regSDMA2_GB_ADDR_CONFIG 0 0x1cdbe 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA2_GB_ADDR_CONFIG_READ 0 0x1cdbf 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA2_RB_RPTR_FETCH_HI 0 0x1cdc0 1 0 0 OFFSET 0 31 regSDMA2_SEM_WAIT_FAIL_TIMER_CNTL 0 0x1cdc1 1 0 0 TIMER 0 31 regSDMA2_RB_RPTR_FETCH 0 0x1cdc2 1 0 0 OFFSET 2 31 regSDMA2_IB_OFFSET_FETCH 0 0x1cdc3 1 0 0 OFFSET 2 21 regSDMA2_PROGRAM 0 0x1cdc4 1 0 0 STREAM 0 31 regSDMA2_STATUS_REG 0 0x1cdc5 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 regSDMA2_STATUS1_REG 0 0x1cdc6 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 regSDMA2_RD_BURST_CNTL 0 0x1cdc7 2 0 0 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 regSDMA2_HBM_PAGE_CONFIG 0 0x1cdc8 1 0 0 PAGE_SIZE_EXPONENT 0 1 regSDMA2_UCODE_CHECKSUM 0 0x1cdc9 1 0 0 DATA 0 31 regSDMA2_F32_CNTL 0 0x1cdca 3 0 0 HALT 0 0 STEP 1 1 RESET 8 8 regSDMA2_FREEZE 0 0x1cdcb 4 0 0 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 regSDMA2_PHASE0_QUANTUM 0 0x1cdcc 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA2_PHASE1_QUANTUM 0 0x1cdcd 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regCC_SDMA2_EDC_CONFIG 0 0x1cdd2 1 0 0 DIS_EDC 1 1 regSDMA2_BA_THRESHOLD 0 0x1cdd3 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 regSDMA2_ID 0 0x1cdd4 1 0 0 DEVICE_ID 0 7 regSDMA2_VERSION 0 0x1cdd5 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 regSDMA2_EDC_COUNTER 0 0x1cdd6 16 0 0 SDMA_MBANK_DATA_BUF0_SED 0 1 SDMA_MBANK_DATA_BUF1_SED 2 3 SDMA_MBANK_DATA_BUF2_SED 4 5 SDMA_MBANK_DATA_BUF3_SED 6 7 SDMA_MBANK_DATA_BUF4_SED 8 9 SDMA_MBANK_DATA_BUF5_SED 10 11 SDMA_MBANK_DATA_BUF6_SED 12 13 SDMA_MBANK_DATA_BUF7_SED 14 15 SDMA_MBANK_DATA_BUF8_SED 16 17 SDMA_MBANK_DATA_BUF9_SED 18 19 SDMA_MBANK_DATA_BUF10_SED 20 21 SDMA_MBANK_DATA_BUF11_SED 22 23 SDMA_MBANK_DATA_BUF12_SED 24 25 SDMA_MBANK_DATA_BUF13_SED 26 27 SDMA_MBANK_DATA_BUF14_SED 28 29 SDMA_MBANK_DATA_BUF15_SED 30 31 regSDMA2_EDC_COUNTER2 0 0x1cdd7 10 0 0 SDMA_UCODE_BUF_SED 0 1 SDMA_RB_CMD_BUF_SED 2 3 SDMA_IB_CMD_BUF_SED 4 5 SDMA_UTCL1_RD_FIFO_SED 6 7 SDMA_UTCL1_RDBST_FIFO_SED 8 9 SDMA_UTCL1_WR_FIFO_SED 10 11 SDMA_DATA_LUT_FIFO_SED 12 13 SDMA_SPLIT_DATA_BUF_SED 14 15 SDMA_MC_WR_ADDR_FIFO_SED 16 17 SDMA_MC_RDRET_BUF_SED 18 19 regSDMA2_STATUS2_REG 0 0x1cdd8 3 0 0 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 regSDMA2_ATOMIC_CNTL 0 0x1cdd9 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 regSDMA2_ATOMIC_PREOP_LO 0 0x1cdda 1 0 0 DATA 0 31 regSDMA2_ATOMIC_PREOP_HI 0 0x1cddb 1 0 0 DATA 0 31 regSDMA2_UTCL1_CNTL 0 0x1cddc 6 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 regSDMA2_UTCL1_WATERMK 0 0x1cddd 5 0 0 REQ_WATERMK 0 2 REQ_DEPTH 3 4 PAGE_WATERMK 5 7 INVREQ_WATERMK 8 15 RESERVED 16 31 regSDMA2_UTCL1_RD_STATUS 0 0x1cdde 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 regSDMA2_UTCL1_WR_STATUS 0 0x1cddf 28 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 regSDMA2_UTCL1_INV0 0 0x1cde0 14 0 0 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 regSDMA2_UTCL1_INV1 0 0x1cde1 1 0 0 INV_ADDR_LO 0 31 regSDMA2_UTCL1_INV2 0 0x1cde2 1 0 0 INV_NFLUSH_VMID_VEC 0 31 regSDMA2_UTCL1_RD_XNACK0 0 0x1cde3 1 0 0 XNACK_ADDR_LO 0 31 regSDMA2_UTCL1_RD_XNACK1 0 0x1cde4 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA2_UTCL1_WR_XNACK0 0 0x1cde5 1 0 0 XNACK_ADDR_LO 0 31 regSDMA2_UTCL1_WR_XNACK1 0 0x1cde6 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA2_UTCL1_TIMEOUT 0 0x1cde7 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 regSDMA2_UTCL1_PAGE 0 0x1cde8 4 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 regSDMA2_POWER_CNTL_IDLE 0 0x1cde9 3 0 0 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 regSDMA2_RELAX_ORDERING_LUT 0 0x1cdea 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 regSDMA2_CHICKEN_BITS_2 0 0x1cdeb 2 0 0 F32_CMD_PROC_DELAY 0 3 F32_SEND_POSTCODE_EN 4 4 regSDMA2_STATUS3_REG 0 0x1cdec 5 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 regSDMA2_PHYSICAL_ADDR_LO 0 0x1cded 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 regSDMA2_PHYSICAL_ADDR_HI 0 0x1cdee 1 0 0 ADDR 0 15 regSDMA2_PHASE2_QUANTUM 0 0x1cdef 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA2_ERROR_LOG 0 0x1cdf0 2 0 0 OVERRIDE 0 15 STATUS 16 31 regSDMA2_PUB_DUMMY_REG0 0 0x1cdf1 1 0 0 VALUE 0 31 regSDMA2_PUB_DUMMY_REG1 0 0x1cdf2 1 0 0 VALUE 0 31 regSDMA2_PUB_DUMMY_REG2 0 0x1cdf3 1 0 0 VALUE 0 31 regSDMA2_PUB_DUMMY_REG3 0 0x1cdf4 1 0 0 VALUE 0 31 regSDMA2_F32_COUNTER 0 0x1cdf5 1 0 0 VALUE 0 31 regSDMA2_PERFCNT_PERFCOUNTER0_CFG 0 0x1cdf7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA2_PERFCNT_PERFCOUNTER1_CFG 0 0x1cdf8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x1cdf9 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regSDMA2_PERFCNT_MISC_CNTL 0 0x1cdfa 1 0 0 CMD_OP 0 15 regSDMA2_PERFCNT_PERFCOUNTER_LO 0 0x1cdfb 1 0 0 COUNTER_LO 0 31 regSDMA2_PERFCNT_PERFCOUNTER_HI 0 0x1cdfc 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regSDMA2_CRD_CNTL 0 0x1cdfd 2 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 regSDMA2_ULV_CNTL 0 0x1cdff 6 0 0 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 regSDMA2_EA_DBIT_ADDR_DATA 0 0x1ce00 1 0 0 VALUE 0 31 regSDMA2_EA_DBIT_ADDR_INDEX 0 0x1ce01 1 0 0 VALUE 0 2 regSDMA2_STATUS4_REG 0 0x1ce03 14 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 MMHUB_RD_OUTSTANDING 4 4 MMHUB_WR_OUTSTANDING 5 5 UTCL2_RD_OUTSTANDING 6 6 UTCL2_WR_OUTSTANDING 7 7 REG_POLLING 8 8 MEM_POLLING 9 9 UTCL2_RD_XNACK 10 11 UTCL2_WR_XNACK 12 13 ACTIVE_QUEUE_ID 14 17 SRIOV_WATING_RLCV_CMD 18 18 SRIOV_SDMA_EXECUTING_CMD 19 19 regSDMA2_SCRATCH_RAM_DATA 0 0x1ce04 1 0 0 DATA 0 31 regSDMA2_SCRATCH_RAM_ADDR 0 0x1ce05 1 0 0 ADDR 0 6 regSDMA2_CE_CTRL 0 0x1ce06 4 0 0 RD_LUT_WATERMARK 0 2 RD_LUT_DEPTH 3 4 WR_AFIFO_WATERMARK 5 7 RESERVED 8 31 regSDMA2_RAS_STATUS 0 0x1ce07 12 0 0 RB_FETCH_ECC 0 0 IB_FETCH_ECC 1 1 F32_DATA_ECC 2 2 SEM_WPTR_ATOMIC_ECC 3 3 COPY_DATA_ECC 4 4 SRAM_ECC 5 5 RB_FETCH_NACK_GEN_ERR 8 8 IB_FETCH_NACK_GEN_ERR 9 9 F32_DATA_NACK_GEN_ERR 10 10 COPY_DATA_NACK_GEN_ERR 11 11 WRRET_DATA_NACK_GEN_ERR 12 12 WPTR_RPTR_ATOMIC_NACK_GEN_ERR 13 13 regSDMA2_CLK_STATUS 0 0x1ce08 4 0 0 DYN_CLK 0 0 PTR_CLK 1 1 REG_CLK 2 2 F32_CLK 3 3 regSDMA2_GFX_RB_CNTL 0 0x1ce20 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_GFX_RB_BASE 0 0x1ce21 1 0 0 ADDR 0 31 regSDMA2_GFX_RB_BASE_HI 0 0x1ce22 1 0 0 ADDR 0 23 regSDMA2_GFX_RB_RPTR 0 0x1ce23 1 0 0 OFFSET 0 31 regSDMA2_GFX_RB_RPTR_HI 0 0x1ce24 1 0 0 OFFSET 0 31 regSDMA2_GFX_RB_WPTR 0 0x1ce25 1 0 0 OFFSET 0 31 regSDMA2_GFX_RB_WPTR_HI 0 0x1ce26 1 0 0 OFFSET 0 31 regSDMA2_GFX_RB_WPTR_POLL_CNTL 0 0x1ce27 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_GFX_RB_RPTR_ADDR_HI 0 0x1ce28 1 0 0 ADDR 0 31 regSDMA2_GFX_RB_RPTR_ADDR_LO 0 0x1ce29 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_GFX_IB_CNTL 0 0x1ce2a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_GFX_IB_RPTR 0 0x1ce2b 1 0 0 OFFSET 2 21 regSDMA2_GFX_IB_OFFSET 0 0x1ce2c 1 0 0 OFFSET 2 21 regSDMA2_GFX_IB_BASE_LO 0 0x1ce2d 1 0 0 ADDR 5 31 regSDMA2_GFX_IB_BASE_HI 0 0x1ce2e 1 0 0 ADDR 0 31 regSDMA2_GFX_IB_SIZE 0 0x1ce2f 1 0 0 SIZE 0 19 regSDMA2_GFX_SKIP_CNTL 0 0x1ce30 1 0 0 SKIP_COUNT 0 19 regSDMA2_GFX_CONTEXT_STATUS 0 0x1ce31 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_GFX_DOORBELL 0 0x1ce32 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_GFX_CONTEXT_CNTL 0 0x1ce33 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 regSDMA2_GFX_STATUS 0 0x1ce48 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_GFX_DOORBELL_LOG 0 0x1ce49 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_GFX_WATERMARK 0 0x1ce4a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_GFX_DOORBELL_OFFSET 0 0x1ce4b 1 0 0 OFFSET 2 27 regSDMA2_GFX_CSA_ADDR_LO 0 0x1ce4c 1 0 0 ADDR 2 31 regSDMA2_GFX_CSA_ADDR_HI 0 0x1ce4d 1 0 0 ADDR 0 31 regSDMA2_GFX_IB_SUB_REMAIN 0 0x1ce4f 1 0 0 SIZE 0 19 regSDMA2_GFX_PREEMPT 0 0x1ce50 1 0 0 IB_PREEMPT 0 0 regSDMA2_GFX_DUMMY_REG 0 0x1ce51 1 0 0 DUMMY 0 31 regSDMA2_GFX_RB_WPTR_POLL_ADDR_HI 0 0x1ce52 1 0 0 ADDR 0 31 regSDMA2_GFX_RB_WPTR_POLL_ADDR_LO 0 0x1ce53 1 0 0 ADDR 2 31 regSDMA2_GFX_RB_AQL_CNTL 0 0x1ce54 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_GFX_MINOR_PTR_UPDATE 0 0x1ce55 1 0 0 ENABLE 0 0 regSDMA2_GFX_MIDCMD_DATA0 0 0x1ce60 1 0 0 DATA0 0 31 regSDMA2_GFX_MIDCMD_DATA1 0 0x1ce61 1 0 0 DATA1 0 31 regSDMA2_GFX_MIDCMD_DATA2 0 0x1ce62 1 0 0 DATA2 0 31 regSDMA2_GFX_MIDCMD_DATA3 0 0x1ce63 1 0 0 DATA3 0 31 regSDMA2_GFX_MIDCMD_DATA4 0 0x1ce64 1 0 0 DATA4 0 31 regSDMA2_GFX_MIDCMD_DATA5 0 0x1ce65 1 0 0 DATA5 0 31 regSDMA2_GFX_MIDCMD_DATA6 0 0x1ce66 1 0 0 DATA6 0 31 regSDMA2_GFX_MIDCMD_DATA7 0 0x1ce67 1 0 0 DATA7 0 31 regSDMA2_GFX_MIDCMD_DATA8 0 0x1ce68 1 0 0 DATA8 0 31 regSDMA2_GFX_MIDCMD_DATA9 0 0x1ce69 1 0 0 DATA9 0 31 regSDMA2_GFX_MIDCMD_DATA10 0 0x1ce6a 1 0 0 DATA10 0 31 regSDMA2_GFX_MIDCMD_CNTL 0 0x1ce6b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_PAGE_RB_CNTL 0 0x1ce78 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_PAGE_RB_BASE 0 0x1ce79 1 0 0 ADDR 0 31 regSDMA2_PAGE_RB_BASE_HI 0 0x1ce7a 1 0 0 ADDR 0 23 regSDMA2_PAGE_RB_RPTR 0 0x1ce7b 1 0 0 OFFSET 0 31 regSDMA2_PAGE_RB_RPTR_HI 0 0x1ce7c 1 0 0 OFFSET 0 31 regSDMA2_PAGE_RB_WPTR 0 0x1ce7d 1 0 0 OFFSET 0 31 regSDMA2_PAGE_RB_WPTR_HI 0 0x1ce7e 1 0 0 OFFSET 0 31 regSDMA2_PAGE_RB_WPTR_POLL_CNTL 0 0x1ce7f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_PAGE_RB_RPTR_ADDR_HI 0 0x1ce80 1 0 0 ADDR 0 31 regSDMA2_PAGE_RB_RPTR_ADDR_LO 0 0x1ce81 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_PAGE_IB_CNTL 0 0x1ce82 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_PAGE_IB_RPTR 0 0x1ce83 1 0 0 OFFSET 2 21 regSDMA2_PAGE_IB_OFFSET 0 0x1ce84 1 0 0 OFFSET 2 21 regSDMA2_PAGE_IB_BASE_LO 0 0x1ce85 1 0 0 ADDR 5 31 regSDMA2_PAGE_IB_BASE_HI 0 0x1ce86 1 0 0 ADDR 0 31 regSDMA2_PAGE_IB_SIZE 0 0x1ce87 1 0 0 SIZE 0 19 regSDMA2_PAGE_SKIP_CNTL 0 0x1ce88 1 0 0 SKIP_COUNT 0 19 regSDMA2_PAGE_CONTEXT_STATUS 0 0x1ce89 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_PAGE_DOORBELL 0 0x1ce8a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_PAGE_STATUS 0 0x1cea0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_PAGE_DOORBELL_LOG 0 0x1cea1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_PAGE_WATERMARK 0 0x1cea2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_PAGE_DOORBELL_OFFSET 0 0x1cea3 1 0 0 OFFSET 2 27 regSDMA2_PAGE_CSA_ADDR_LO 0 0x1cea4 1 0 0 ADDR 2 31 regSDMA2_PAGE_CSA_ADDR_HI 0 0x1cea5 1 0 0 ADDR 0 31 regSDMA2_PAGE_IB_SUB_REMAIN 0 0x1cea7 1 0 0 SIZE 0 19 regSDMA2_PAGE_PREEMPT 0 0x1cea8 1 0 0 IB_PREEMPT 0 0 regSDMA2_PAGE_DUMMY_REG 0 0x1cea9 1 0 0 DUMMY 0 31 regSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x1ceaa 1 0 0 ADDR 0 31 regSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x1ceab 1 0 0 ADDR 2 31 regSDMA2_PAGE_RB_AQL_CNTL 0 0x1ceac 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_PAGE_MINOR_PTR_UPDATE 0 0x1cead 1 0 0 ENABLE 0 0 regSDMA2_PAGE_MIDCMD_DATA0 0 0x1ceb8 1 0 0 DATA0 0 31 regSDMA2_PAGE_MIDCMD_DATA1 0 0x1ceb9 1 0 0 DATA1 0 31 regSDMA2_PAGE_MIDCMD_DATA2 0 0x1ceba 1 0 0 DATA2 0 31 regSDMA2_PAGE_MIDCMD_DATA3 0 0x1cebb 1 0 0 DATA3 0 31 regSDMA2_PAGE_MIDCMD_DATA4 0 0x1cebc 1 0 0 DATA4 0 31 regSDMA2_PAGE_MIDCMD_DATA5 0 0x1cebd 1 0 0 DATA5 0 31 regSDMA2_PAGE_MIDCMD_DATA6 0 0x1cebe 1 0 0 DATA6 0 31 regSDMA2_PAGE_MIDCMD_DATA7 0 0x1cebf 1 0 0 DATA7 0 31 regSDMA2_PAGE_MIDCMD_DATA8 0 0x1cec0 1 0 0 DATA8 0 31 regSDMA2_PAGE_MIDCMD_DATA9 0 0x1cec1 1 0 0 DATA9 0 31 regSDMA2_PAGE_MIDCMD_DATA10 0 0x1cec2 1 0 0 DATA10 0 31 regSDMA2_PAGE_MIDCMD_CNTL 0 0x1cec3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC0_RB_CNTL 0 0x1ced0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC0_RB_BASE 0 0x1ced1 1 0 0 ADDR 0 31 regSDMA2_RLC0_RB_BASE_HI 0 0x1ced2 1 0 0 ADDR 0 23 regSDMA2_RLC0_RB_RPTR 0 0x1ced3 1 0 0 OFFSET 0 31 regSDMA2_RLC0_RB_RPTR_HI 0 0x1ced4 1 0 0 OFFSET 0 31 regSDMA2_RLC0_RB_WPTR 0 0x1ced5 1 0 0 OFFSET 0 31 regSDMA2_RLC0_RB_WPTR_HI 0 0x1ced6 1 0 0 OFFSET 0 31 regSDMA2_RLC0_RB_WPTR_POLL_CNTL 0 0x1ced7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC0_RB_RPTR_ADDR_HI 0 0x1ced8 1 0 0 ADDR 0 31 regSDMA2_RLC0_RB_RPTR_ADDR_LO 0 0x1ced9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC0_IB_CNTL 0 0x1ceda 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC0_IB_RPTR 0 0x1cedb 1 0 0 OFFSET 2 21 regSDMA2_RLC0_IB_OFFSET 0 0x1cedc 1 0 0 OFFSET 2 21 regSDMA2_RLC0_IB_BASE_LO 0 0x1cedd 1 0 0 ADDR 5 31 regSDMA2_RLC0_IB_BASE_HI 0 0x1cede 1 0 0 ADDR 0 31 regSDMA2_RLC0_IB_SIZE 0 0x1cedf 1 0 0 SIZE 0 19 regSDMA2_RLC0_SKIP_CNTL 0 0x1cee0 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC0_CONTEXT_STATUS 0 0x1cee1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC0_DOORBELL 0 0x1cee2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC0_STATUS 0 0x1cef8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC0_DOORBELL_LOG 0 0x1cef9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC0_WATERMARK 0 0x1cefa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC0_DOORBELL_OFFSET 0 0x1cefb 1 0 0 OFFSET 2 27 regSDMA2_RLC0_CSA_ADDR_LO 0 0x1cefc 1 0 0 ADDR 2 31 regSDMA2_RLC0_CSA_ADDR_HI 0 0x1cefd 1 0 0 ADDR 0 31 regSDMA2_RLC0_IB_SUB_REMAIN 0 0x1ceff 1 0 0 SIZE 0 19 regSDMA2_RLC0_PREEMPT 0 0x1cf00 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC0_DUMMY_REG 0 0x1cf01 1 0 0 DUMMY 0 31 regSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x1cf02 1 0 0 ADDR 0 31 regSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x1cf03 1 0 0 ADDR 2 31 regSDMA2_RLC0_RB_AQL_CNTL 0 0x1cf04 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC0_MINOR_PTR_UPDATE 0 0x1cf05 1 0 0 ENABLE 0 0 regSDMA2_RLC0_MIDCMD_DATA0 0 0x1cf10 1 0 0 DATA0 0 31 regSDMA2_RLC0_MIDCMD_DATA1 0 0x1cf11 1 0 0 DATA1 0 31 regSDMA2_RLC0_MIDCMD_DATA2 0 0x1cf12 1 0 0 DATA2 0 31 regSDMA2_RLC0_MIDCMD_DATA3 0 0x1cf13 1 0 0 DATA3 0 31 regSDMA2_RLC0_MIDCMD_DATA4 0 0x1cf14 1 0 0 DATA4 0 31 regSDMA2_RLC0_MIDCMD_DATA5 0 0x1cf15 1 0 0 DATA5 0 31 regSDMA2_RLC0_MIDCMD_DATA6 0 0x1cf16 1 0 0 DATA6 0 31 regSDMA2_RLC0_MIDCMD_DATA7 0 0x1cf17 1 0 0 DATA7 0 31 regSDMA2_RLC0_MIDCMD_DATA8 0 0x1cf18 1 0 0 DATA8 0 31 regSDMA2_RLC0_MIDCMD_DATA9 0 0x1cf19 1 0 0 DATA9 0 31 regSDMA2_RLC0_MIDCMD_DATA10 0 0x1cf1a 1 0 0 DATA10 0 31 regSDMA2_RLC0_MIDCMD_CNTL 0 0x1cf1b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC1_RB_CNTL 0 0x1cf28 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC1_RB_BASE 0 0x1cf29 1 0 0 ADDR 0 31 regSDMA2_RLC1_RB_BASE_HI 0 0x1cf2a 1 0 0 ADDR 0 23 regSDMA2_RLC1_RB_RPTR 0 0x1cf2b 1 0 0 OFFSET 0 31 regSDMA2_RLC1_RB_RPTR_HI 0 0x1cf2c 1 0 0 OFFSET 0 31 regSDMA2_RLC1_RB_WPTR 0 0x1cf2d 1 0 0 OFFSET 0 31 regSDMA2_RLC1_RB_WPTR_HI 0 0x1cf2e 1 0 0 OFFSET 0 31 regSDMA2_RLC1_RB_WPTR_POLL_CNTL 0 0x1cf2f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC1_RB_RPTR_ADDR_HI 0 0x1cf30 1 0 0 ADDR 0 31 regSDMA2_RLC1_RB_RPTR_ADDR_LO 0 0x1cf31 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC1_IB_CNTL 0 0x1cf32 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC1_IB_RPTR 0 0x1cf33 1 0 0 OFFSET 2 21 regSDMA2_RLC1_IB_OFFSET 0 0x1cf34 1 0 0 OFFSET 2 21 regSDMA2_RLC1_IB_BASE_LO 0 0x1cf35 1 0 0 ADDR 5 31 regSDMA2_RLC1_IB_BASE_HI 0 0x1cf36 1 0 0 ADDR 0 31 regSDMA2_RLC1_IB_SIZE 0 0x1cf37 1 0 0 SIZE 0 19 regSDMA2_RLC1_SKIP_CNTL 0 0x1cf38 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC1_CONTEXT_STATUS 0 0x1cf39 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC1_DOORBELL 0 0x1cf3a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC1_STATUS 0 0x1cf50 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC1_DOORBELL_LOG 0 0x1cf51 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC1_WATERMARK 0 0x1cf52 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC1_DOORBELL_OFFSET 0 0x1cf53 1 0 0 OFFSET 2 27 regSDMA2_RLC1_CSA_ADDR_LO 0 0x1cf54 1 0 0 ADDR 2 31 regSDMA2_RLC1_CSA_ADDR_HI 0 0x1cf55 1 0 0 ADDR 0 31 regSDMA2_RLC1_IB_SUB_REMAIN 0 0x1cf57 1 0 0 SIZE 0 19 regSDMA2_RLC1_PREEMPT 0 0x1cf58 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC1_DUMMY_REG 0 0x1cf59 1 0 0 DUMMY 0 31 regSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1cf5a 1 0 0 ADDR 0 31 regSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1cf5b 1 0 0 ADDR 2 31 regSDMA2_RLC1_RB_AQL_CNTL 0 0x1cf5c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC1_MINOR_PTR_UPDATE 0 0x1cf5d 1 0 0 ENABLE 0 0 regSDMA2_RLC1_MIDCMD_DATA0 0 0x1cf68 1 0 0 DATA0 0 31 regSDMA2_RLC1_MIDCMD_DATA1 0 0x1cf69 1 0 0 DATA1 0 31 regSDMA2_RLC1_MIDCMD_DATA2 0 0x1cf6a 1 0 0 DATA2 0 31 regSDMA2_RLC1_MIDCMD_DATA3 0 0x1cf6b 1 0 0 DATA3 0 31 regSDMA2_RLC1_MIDCMD_DATA4 0 0x1cf6c 1 0 0 DATA4 0 31 regSDMA2_RLC1_MIDCMD_DATA5 0 0x1cf6d 1 0 0 DATA5 0 31 regSDMA2_RLC1_MIDCMD_DATA6 0 0x1cf6e 1 0 0 DATA6 0 31 regSDMA2_RLC1_MIDCMD_DATA7 0 0x1cf6f 1 0 0 DATA7 0 31 regSDMA2_RLC1_MIDCMD_DATA8 0 0x1cf70 1 0 0 DATA8 0 31 regSDMA2_RLC1_MIDCMD_DATA9 0 0x1cf71 1 0 0 DATA9 0 31 regSDMA2_RLC1_MIDCMD_DATA10 0 0x1cf72 1 0 0 DATA10 0 31 regSDMA2_RLC1_MIDCMD_CNTL 0 0x1cf73 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC2_RB_CNTL 0 0x1cf80 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC2_RB_BASE 0 0x1cf81 1 0 0 ADDR 0 31 regSDMA2_RLC2_RB_BASE_HI 0 0x1cf82 1 0 0 ADDR 0 23 regSDMA2_RLC2_RB_RPTR 0 0x1cf83 1 0 0 OFFSET 0 31 regSDMA2_RLC2_RB_RPTR_HI 0 0x1cf84 1 0 0 OFFSET 0 31 regSDMA2_RLC2_RB_WPTR 0 0x1cf85 1 0 0 OFFSET 0 31 regSDMA2_RLC2_RB_WPTR_HI 0 0x1cf86 1 0 0 OFFSET 0 31 regSDMA2_RLC2_RB_WPTR_POLL_CNTL 0 0x1cf87 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC2_RB_RPTR_ADDR_HI 0 0x1cf88 1 0 0 ADDR 0 31 regSDMA2_RLC2_RB_RPTR_ADDR_LO 0 0x1cf89 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC2_IB_CNTL 0 0x1cf8a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC2_IB_RPTR 0 0x1cf8b 1 0 0 OFFSET 2 21 regSDMA2_RLC2_IB_OFFSET 0 0x1cf8c 1 0 0 OFFSET 2 21 regSDMA2_RLC2_IB_BASE_LO 0 0x1cf8d 1 0 0 ADDR 5 31 regSDMA2_RLC2_IB_BASE_HI 0 0x1cf8e 1 0 0 ADDR 0 31 regSDMA2_RLC2_IB_SIZE 0 0x1cf8f 1 0 0 SIZE 0 19 regSDMA2_RLC2_SKIP_CNTL 0 0x1cf90 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC2_CONTEXT_STATUS 0 0x1cf91 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC2_DOORBELL 0 0x1cf92 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC2_STATUS 0 0x1cfa8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC2_DOORBELL_LOG 0 0x1cfa9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC2_WATERMARK 0 0x1cfaa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC2_DOORBELL_OFFSET 0 0x1cfab 1 0 0 OFFSET 2 27 regSDMA2_RLC2_CSA_ADDR_LO 0 0x1cfac 1 0 0 ADDR 2 31 regSDMA2_RLC2_CSA_ADDR_HI 0 0x1cfad 1 0 0 ADDR 0 31 regSDMA2_RLC2_IB_SUB_REMAIN 0 0x1cfaf 1 0 0 SIZE 0 19 regSDMA2_RLC2_PREEMPT 0 0x1cfb0 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC2_DUMMY_REG 0 0x1cfb1 1 0 0 DUMMY 0 31 regSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x1cfb2 1 0 0 ADDR 0 31 regSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x1cfb3 1 0 0 ADDR 2 31 regSDMA2_RLC2_RB_AQL_CNTL 0 0x1cfb4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC2_MINOR_PTR_UPDATE 0 0x1cfb5 1 0 0 ENABLE 0 0 regSDMA2_RLC2_MIDCMD_DATA0 0 0x1cfc0 1 0 0 DATA0 0 31 regSDMA2_RLC2_MIDCMD_DATA1 0 0x1cfc1 1 0 0 DATA1 0 31 regSDMA2_RLC2_MIDCMD_DATA2 0 0x1cfc2 1 0 0 DATA2 0 31 regSDMA2_RLC2_MIDCMD_DATA3 0 0x1cfc3 1 0 0 DATA3 0 31 regSDMA2_RLC2_MIDCMD_DATA4 0 0x1cfc4 1 0 0 DATA4 0 31 regSDMA2_RLC2_MIDCMD_DATA5 0 0x1cfc5 1 0 0 DATA5 0 31 regSDMA2_RLC2_MIDCMD_DATA6 0 0x1cfc6 1 0 0 DATA6 0 31 regSDMA2_RLC2_MIDCMD_DATA7 0 0x1cfc7 1 0 0 DATA7 0 31 regSDMA2_RLC2_MIDCMD_DATA8 0 0x1cfc8 1 0 0 DATA8 0 31 regSDMA2_RLC2_MIDCMD_DATA9 0 0x1cfc9 1 0 0 DATA9 0 31 regSDMA2_RLC2_MIDCMD_DATA10 0 0x1cfca 1 0 0 DATA10 0 31 regSDMA2_RLC2_MIDCMD_CNTL 0 0x1cfcb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC3_RB_CNTL 0 0x1cfd8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC3_RB_BASE 0 0x1cfd9 1 0 0 ADDR 0 31 regSDMA2_RLC3_RB_BASE_HI 0 0x1cfda 1 0 0 ADDR 0 23 regSDMA2_RLC3_RB_RPTR 0 0x1cfdb 1 0 0 OFFSET 0 31 regSDMA2_RLC3_RB_RPTR_HI 0 0x1cfdc 1 0 0 OFFSET 0 31 regSDMA2_RLC3_RB_WPTR 0 0x1cfdd 1 0 0 OFFSET 0 31 regSDMA2_RLC3_RB_WPTR_HI 0 0x1cfde 1 0 0 OFFSET 0 31 regSDMA2_RLC3_RB_WPTR_POLL_CNTL 0 0x1cfdf 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC3_RB_RPTR_ADDR_HI 0 0x1cfe0 1 0 0 ADDR 0 31 regSDMA2_RLC3_RB_RPTR_ADDR_LO 0 0x1cfe1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC3_IB_CNTL 0 0x1cfe2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC3_IB_RPTR 0 0x1cfe3 1 0 0 OFFSET 2 21 regSDMA2_RLC3_IB_OFFSET 0 0x1cfe4 1 0 0 OFFSET 2 21 regSDMA2_RLC3_IB_BASE_LO 0 0x1cfe5 1 0 0 ADDR 5 31 regSDMA2_RLC3_IB_BASE_HI 0 0x1cfe6 1 0 0 ADDR 0 31 regSDMA2_RLC3_IB_SIZE 0 0x1cfe7 1 0 0 SIZE 0 19 regSDMA2_RLC3_SKIP_CNTL 0 0x1cfe8 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC3_CONTEXT_STATUS 0 0x1cfe9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC3_DOORBELL 0 0x1cfea 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC3_STATUS 0 0x1d000 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC3_DOORBELL_LOG 0 0x1d001 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC3_WATERMARK 0 0x1d002 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC3_DOORBELL_OFFSET 0 0x1d003 1 0 0 OFFSET 2 27 regSDMA2_RLC3_CSA_ADDR_LO 0 0x1d004 1 0 0 ADDR 2 31 regSDMA2_RLC3_CSA_ADDR_HI 0 0x1d005 1 0 0 ADDR 0 31 regSDMA2_RLC3_IB_SUB_REMAIN 0 0x1d007 1 0 0 SIZE 0 19 regSDMA2_RLC3_PREEMPT 0 0x1d008 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC3_DUMMY_REG 0 0x1d009 1 0 0 DUMMY 0 31 regSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x1d00a 1 0 0 ADDR 0 31 regSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x1d00b 1 0 0 ADDR 2 31 regSDMA2_RLC3_RB_AQL_CNTL 0 0x1d00c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC3_MINOR_PTR_UPDATE 0 0x1d00d 1 0 0 ENABLE 0 0 regSDMA2_RLC3_MIDCMD_DATA0 0 0x1d018 1 0 0 DATA0 0 31 regSDMA2_RLC3_MIDCMD_DATA1 0 0x1d019 1 0 0 DATA1 0 31 regSDMA2_RLC3_MIDCMD_DATA2 0 0x1d01a 1 0 0 DATA2 0 31 regSDMA2_RLC3_MIDCMD_DATA3 0 0x1d01b 1 0 0 DATA3 0 31 regSDMA2_RLC3_MIDCMD_DATA4 0 0x1d01c 1 0 0 DATA4 0 31 regSDMA2_RLC3_MIDCMD_DATA5 0 0x1d01d 1 0 0 DATA5 0 31 regSDMA2_RLC3_MIDCMD_DATA6 0 0x1d01e 1 0 0 DATA6 0 31 regSDMA2_RLC3_MIDCMD_DATA7 0 0x1d01f 1 0 0 DATA7 0 31 regSDMA2_RLC3_MIDCMD_DATA8 0 0x1d020 1 0 0 DATA8 0 31 regSDMA2_RLC3_MIDCMD_DATA9 0 0x1d021 1 0 0 DATA9 0 31 regSDMA2_RLC3_MIDCMD_DATA10 0 0x1d022 1 0 0 DATA10 0 31 regSDMA2_RLC3_MIDCMD_CNTL 0 0x1d023 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC4_RB_CNTL 0 0x1d030 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC4_RB_BASE 0 0x1d031 1 0 0 ADDR 0 31 regSDMA2_RLC4_RB_BASE_HI 0 0x1d032 1 0 0 ADDR 0 23 regSDMA2_RLC4_RB_RPTR 0 0x1d033 1 0 0 OFFSET 0 31 regSDMA2_RLC4_RB_RPTR_HI 0 0x1d034 1 0 0 OFFSET 0 31 regSDMA2_RLC4_RB_WPTR 0 0x1d035 1 0 0 OFFSET 0 31 regSDMA2_RLC4_RB_WPTR_HI 0 0x1d036 1 0 0 OFFSET 0 31 regSDMA2_RLC4_RB_WPTR_POLL_CNTL 0 0x1d037 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC4_RB_RPTR_ADDR_HI 0 0x1d038 1 0 0 ADDR 0 31 regSDMA2_RLC4_RB_RPTR_ADDR_LO 0 0x1d039 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC4_IB_CNTL 0 0x1d03a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC4_IB_RPTR 0 0x1d03b 1 0 0 OFFSET 2 21 regSDMA2_RLC4_IB_OFFSET 0 0x1d03c 1 0 0 OFFSET 2 21 regSDMA2_RLC4_IB_BASE_LO 0 0x1d03d 1 0 0 ADDR 5 31 regSDMA2_RLC4_IB_BASE_HI 0 0x1d03e 1 0 0 ADDR 0 31 regSDMA2_RLC4_IB_SIZE 0 0x1d03f 1 0 0 SIZE 0 19 regSDMA2_RLC4_SKIP_CNTL 0 0x1d040 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC4_CONTEXT_STATUS 0 0x1d041 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC4_DOORBELL 0 0x1d042 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC4_STATUS 0 0x1d058 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC4_DOORBELL_LOG 0 0x1d059 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC4_WATERMARK 0 0x1d05a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC4_DOORBELL_OFFSET 0 0x1d05b 1 0 0 OFFSET 2 27 regSDMA2_RLC4_CSA_ADDR_LO 0 0x1d05c 1 0 0 ADDR 2 31 regSDMA2_RLC4_CSA_ADDR_HI 0 0x1d05d 1 0 0 ADDR 0 31 regSDMA2_RLC4_IB_SUB_REMAIN 0 0x1d05f 1 0 0 SIZE 0 19 regSDMA2_RLC4_PREEMPT 0 0x1d060 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC4_DUMMY_REG 0 0x1d061 1 0 0 DUMMY 0 31 regSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x1d062 1 0 0 ADDR 0 31 regSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x1d063 1 0 0 ADDR 2 31 regSDMA2_RLC4_RB_AQL_CNTL 0 0x1d064 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC4_MINOR_PTR_UPDATE 0 0x1d065 1 0 0 ENABLE 0 0 regSDMA2_RLC4_MIDCMD_DATA0 0 0x1d070 1 0 0 DATA0 0 31 regSDMA2_RLC4_MIDCMD_DATA1 0 0x1d071 1 0 0 DATA1 0 31 regSDMA2_RLC4_MIDCMD_DATA2 0 0x1d072 1 0 0 DATA2 0 31 regSDMA2_RLC4_MIDCMD_DATA3 0 0x1d073 1 0 0 DATA3 0 31 regSDMA2_RLC4_MIDCMD_DATA4 0 0x1d074 1 0 0 DATA4 0 31 regSDMA2_RLC4_MIDCMD_DATA5 0 0x1d075 1 0 0 DATA5 0 31 regSDMA2_RLC4_MIDCMD_DATA6 0 0x1d076 1 0 0 DATA6 0 31 regSDMA2_RLC4_MIDCMD_DATA7 0 0x1d077 1 0 0 DATA7 0 31 regSDMA2_RLC4_MIDCMD_DATA8 0 0x1d078 1 0 0 DATA8 0 31 regSDMA2_RLC4_MIDCMD_DATA9 0 0x1d079 1 0 0 DATA9 0 31 regSDMA2_RLC4_MIDCMD_DATA10 0 0x1d07a 1 0 0 DATA10 0 31 regSDMA2_RLC4_MIDCMD_CNTL 0 0x1d07b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC5_RB_CNTL 0 0x1d088 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC5_RB_BASE 0 0x1d089 1 0 0 ADDR 0 31 regSDMA2_RLC5_RB_BASE_HI 0 0x1d08a 1 0 0 ADDR 0 23 regSDMA2_RLC5_RB_RPTR 0 0x1d08b 1 0 0 OFFSET 0 31 regSDMA2_RLC5_RB_RPTR_HI 0 0x1d08c 1 0 0 OFFSET 0 31 regSDMA2_RLC5_RB_WPTR 0 0x1d08d 1 0 0 OFFSET 0 31 regSDMA2_RLC5_RB_WPTR_HI 0 0x1d08e 1 0 0 OFFSET 0 31 regSDMA2_RLC5_RB_WPTR_POLL_CNTL 0 0x1d08f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC5_RB_RPTR_ADDR_HI 0 0x1d090 1 0 0 ADDR 0 31 regSDMA2_RLC5_RB_RPTR_ADDR_LO 0 0x1d091 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC5_IB_CNTL 0 0x1d092 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC5_IB_RPTR 0 0x1d093 1 0 0 OFFSET 2 21 regSDMA2_RLC5_IB_OFFSET 0 0x1d094 1 0 0 OFFSET 2 21 regSDMA2_RLC5_IB_BASE_LO 0 0x1d095 1 0 0 ADDR 5 31 regSDMA2_RLC5_IB_BASE_HI 0 0x1d096 1 0 0 ADDR 0 31 regSDMA2_RLC5_IB_SIZE 0 0x1d097 1 0 0 SIZE 0 19 regSDMA2_RLC5_SKIP_CNTL 0 0x1d098 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC5_CONTEXT_STATUS 0 0x1d099 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC5_DOORBELL 0 0x1d09a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC5_STATUS 0 0x1d0b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC5_DOORBELL_LOG 0 0x1d0b1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC5_WATERMARK 0 0x1d0b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC5_DOORBELL_OFFSET 0 0x1d0b3 1 0 0 OFFSET 2 27 regSDMA2_RLC5_CSA_ADDR_LO 0 0x1d0b4 1 0 0 ADDR 2 31 regSDMA2_RLC5_CSA_ADDR_HI 0 0x1d0b5 1 0 0 ADDR 0 31 regSDMA2_RLC5_IB_SUB_REMAIN 0 0x1d0b7 1 0 0 SIZE 0 19 regSDMA2_RLC5_PREEMPT 0 0x1d0b8 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC5_DUMMY_REG 0 0x1d0b9 1 0 0 DUMMY 0 31 regSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x1d0ba 1 0 0 ADDR 0 31 regSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x1d0bb 1 0 0 ADDR 2 31 regSDMA2_RLC5_RB_AQL_CNTL 0 0x1d0bc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC5_MINOR_PTR_UPDATE 0 0x1d0bd 1 0 0 ENABLE 0 0 regSDMA2_RLC5_MIDCMD_DATA0 0 0x1d0c8 1 0 0 DATA0 0 31 regSDMA2_RLC5_MIDCMD_DATA1 0 0x1d0c9 1 0 0 DATA1 0 31 regSDMA2_RLC5_MIDCMD_DATA2 0 0x1d0ca 1 0 0 DATA2 0 31 regSDMA2_RLC5_MIDCMD_DATA3 0 0x1d0cb 1 0 0 DATA3 0 31 regSDMA2_RLC5_MIDCMD_DATA4 0 0x1d0cc 1 0 0 DATA4 0 31 regSDMA2_RLC5_MIDCMD_DATA5 0 0x1d0cd 1 0 0 DATA5 0 31 regSDMA2_RLC5_MIDCMD_DATA6 0 0x1d0ce 1 0 0 DATA6 0 31 regSDMA2_RLC5_MIDCMD_DATA7 0 0x1d0cf 1 0 0 DATA7 0 31 regSDMA2_RLC5_MIDCMD_DATA8 0 0x1d0d0 1 0 0 DATA8 0 31 regSDMA2_RLC5_MIDCMD_DATA9 0 0x1d0d1 1 0 0 DATA9 0 31 regSDMA2_RLC5_MIDCMD_DATA10 0 0x1d0d2 1 0 0 DATA10 0 31 regSDMA2_RLC5_MIDCMD_CNTL 0 0x1d0d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC6_RB_CNTL 0 0x1d0e0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC6_RB_BASE 0 0x1d0e1 1 0 0 ADDR 0 31 regSDMA2_RLC6_RB_BASE_HI 0 0x1d0e2 1 0 0 ADDR 0 23 regSDMA2_RLC6_RB_RPTR 0 0x1d0e3 1 0 0 OFFSET 0 31 regSDMA2_RLC6_RB_RPTR_HI 0 0x1d0e4 1 0 0 OFFSET 0 31 regSDMA2_RLC6_RB_WPTR 0 0x1d0e5 1 0 0 OFFSET 0 31 regSDMA2_RLC6_RB_WPTR_HI 0 0x1d0e6 1 0 0 OFFSET 0 31 regSDMA2_RLC6_RB_WPTR_POLL_CNTL 0 0x1d0e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC6_RB_RPTR_ADDR_HI 0 0x1d0e8 1 0 0 ADDR 0 31 regSDMA2_RLC6_RB_RPTR_ADDR_LO 0 0x1d0e9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC6_IB_CNTL 0 0x1d0ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC6_IB_RPTR 0 0x1d0eb 1 0 0 OFFSET 2 21 regSDMA2_RLC6_IB_OFFSET 0 0x1d0ec 1 0 0 OFFSET 2 21 regSDMA2_RLC6_IB_BASE_LO 0 0x1d0ed 1 0 0 ADDR 5 31 regSDMA2_RLC6_IB_BASE_HI 0 0x1d0ee 1 0 0 ADDR 0 31 regSDMA2_RLC6_IB_SIZE 0 0x1d0ef 1 0 0 SIZE 0 19 regSDMA2_RLC6_SKIP_CNTL 0 0x1d0f0 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC6_CONTEXT_STATUS 0 0x1d0f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC6_DOORBELL 0 0x1d0f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC6_STATUS 0 0x1d108 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC6_DOORBELL_LOG 0 0x1d109 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC6_WATERMARK 0 0x1d10a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC6_DOORBELL_OFFSET 0 0x1d10b 1 0 0 OFFSET 2 27 regSDMA2_RLC6_CSA_ADDR_LO 0 0x1d10c 1 0 0 ADDR 2 31 regSDMA2_RLC6_CSA_ADDR_HI 0 0x1d10d 1 0 0 ADDR 0 31 regSDMA2_RLC6_IB_SUB_REMAIN 0 0x1d10f 1 0 0 SIZE 0 19 regSDMA2_RLC6_PREEMPT 0 0x1d110 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC6_DUMMY_REG 0 0x1d111 1 0 0 DUMMY 0 31 regSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x1d112 1 0 0 ADDR 0 31 regSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x1d113 1 0 0 ADDR 2 31 regSDMA2_RLC6_RB_AQL_CNTL 0 0x1d114 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC6_MINOR_PTR_UPDATE 0 0x1d115 1 0 0 ENABLE 0 0 regSDMA2_RLC6_MIDCMD_DATA0 0 0x1d120 1 0 0 DATA0 0 31 regSDMA2_RLC6_MIDCMD_DATA1 0 0x1d121 1 0 0 DATA1 0 31 regSDMA2_RLC6_MIDCMD_DATA2 0 0x1d122 1 0 0 DATA2 0 31 regSDMA2_RLC6_MIDCMD_DATA3 0 0x1d123 1 0 0 DATA3 0 31 regSDMA2_RLC6_MIDCMD_DATA4 0 0x1d124 1 0 0 DATA4 0 31 regSDMA2_RLC6_MIDCMD_DATA5 0 0x1d125 1 0 0 DATA5 0 31 regSDMA2_RLC6_MIDCMD_DATA6 0 0x1d126 1 0 0 DATA6 0 31 regSDMA2_RLC6_MIDCMD_DATA7 0 0x1d127 1 0 0 DATA7 0 31 regSDMA2_RLC6_MIDCMD_DATA8 0 0x1d128 1 0 0 DATA8 0 31 regSDMA2_RLC6_MIDCMD_DATA9 0 0x1d129 1 0 0 DATA9 0 31 regSDMA2_RLC6_MIDCMD_DATA10 0 0x1d12a 1 0 0 DATA10 0 31 regSDMA2_RLC6_MIDCMD_CNTL 0 0x1d12b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA2_RLC7_RB_CNTL 0 0x1d138 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA2_RLC7_RB_BASE 0 0x1d139 1 0 0 ADDR 0 31 regSDMA2_RLC7_RB_BASE_HI 0 0x1d13a 1 0 0 ADDR 0 23 regSDMA2_RLC7_RB_RPTR 0 0x1d13b 1 0 0 OFFSET 0 31 regSDMA2_RLC7_RB_RPTR_HI 0 0x1d13c 1 0 0 OFFSET 0 31 regSDMA2_RLC7_RB_WPTR 0 0x1d13d 1 0 0 OFFSET 0 31 regSDMA2_RLC7_RB_WPTR_HI 0 0x1d13e 1 0 0 OFFSET 0 31 regSDMA2_RLC7_RB_WPTR_POLL_CNTL 0 0x1d13f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA2_RLC7_RB_RPTR_ADDR_HI 0 0x1d140 1 0 0 ADDR 0 31 regSDMA2_RLC7_RB_RPTR_ADDR_LO 0 0x1d141 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA2_RLC7_IB_CNTL 0 0x1d142 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA2_RLC7_IB_RPTR 0 0x1d143 1 0 0 OFFSET 2 21 regSDMA2_RLC7_IB_OFFSET 0 0x1d144 1 0 0 OFFSET 2 21 regSDMA2_RLC7_IB_BASE_LO 0 0x1d145 1 0 0 ADDR 5 31 regSDMA2_RLC7_IB_BASE_HI 0 0x1d146 1 0 0 ADDR 0 31 regSDMA2_RLC7_IB_SIZE 0 0x1d147 1 0 0 SIZE 0 19 regSDMA2_RLC7_SKIP_CNTL 0 0x1d148 1 0 0 SKIP_COUNT 0 19 regSDMA2_RLC7_CONTEXT_STATUS 0 0x1d149 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA2_RLC7_DOORBELL 0 0x1d14a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA2_RLC7_STATUS 0 0x1d160 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA2_RLC7_DOORBELL_LOG 0 0x1d161 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA2_RLC7_WATERMARK 0 0x1d162 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA2_RLC7_DOORBELL_OFFSET 0 0x1d163 1 0 0 OFFSET 2 27 regSDMA2_RLC7_CSA_ADDR_LO 0 0x1d164 1 0 0 ADDR 2 31 regSDMA2_RLC7_CSA_ADDR_HI 0 0x1d165 1 0 0 ADDR 0 31 regSDMA2_RLC7_IB_SUB_REMAIN 0 0x1d167 1 0 0 SIZE 0 19 regSDMA2_RLC7_PREEMPT 0 0x1d168 1 0 0 IB_PREEMPT 0 0 regSDMA2_RLC7_DUMMY_REG 0 0x1d169 1 0 0 DUMMY 0 31 regSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x1d16a 1 0 0 ADDR 0 31 regSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x1d16b 1 0 0 ADDR 2 31 regSDMA2_RLC7_RB_AQL_CNTL 0 0x1d16c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA2_RLC7_MINOR_PTR_UPDATE 0 0x1d16d 1 0 0 ENABLE 0 0 regSDMA2_RLC7_MIDCMD_DATA0 0 0x1d178 1 0 0 DATA0 0 31 regSDMA2_RLC7_MIDCMD_DATA1 0 0x1d179 1 0 0 DATA1 0 31 regSDMA2_RLC7_MIDCMD_DATA2 0 0x1d17a 1 0 0 DATA2 0 31 regSDMA2_RLC7_MIDCMD_DATA3 0 0x1d17b 1 0 0 DATA3 0 31 regSDMA2_RLC7_MIDCMD_DATA4 0 0x1d17c 1 0 0 DATA4 0 31 regSDMA2_RLC7_MIDCMD_DATA5 0 0x1d17d 1 0 0 DATA5 0 31 regSDMA2_RLC7_MIDCMD_DATA6 0 0x1d17e 1 0 0 DATA6 0 31 regSDMA2_RLC7_MIDCMD_DATA7 0 0x1d17f 1 0 0 DATA7 0 31 regSDMA2_RLC7_MIDCMD_DATA8 0 0x1d180 1 0 0 DATA8 0 31 regSDMA2_RLC7_MIDCMD_DATA9 0 0x1d181 1 0 0 DATA9 0 31 regSDMA2_RLC7_MIDCMD_DATA10 0 0x1d182 1 0 0 DATA10 0 31 regSDMA2_RLC7_MIDCMD_CNTL 0 0x1d183 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_UCODE_ADDR 0 0x1d1a0 1 0 0 VALUE 0 13 regSDMA3_UCODE_DATA 0 0x1d1a1 1 0 0 VALUE 0 31 regSDMA3_VF_ENABLE 0 0x1d1aa 1 0 0 VF_ENABLE 0 0 regSDMA3_CONTEXT_GROUP_BOUNDARY 0 0x1d1b9 1 0 0 RESERVED 0 31 regSDMA3_POWER_CNTL 0 0x1d1ba 10 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 ON_OFF_STATUS_DURATION_TIME 26 31 regSDMA3_CLK_CTRL 0 0x1d1bb 11 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSDMA3_CNTL 0 0x1d1bc 12 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_EXPIRE_ENABLE 6 6 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 regSDMA3_CHICKEN_BITS 0 0x1d1bd 12 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 SRAM_FGCG_ENABLE 26 26 RESERVED 27 31 regSDMA3_GB_ADDR_CONFIG 0 0x1d1be 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA3_GB_ADDR_CONFIG_READ 0 0x1d1bf 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA3_RB_RPTR_FETCH_HI 0 0x1d1c0 1 0 0 OFFSET 0 31 regSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0 0x1d1c1 1 0 0 TIMER 0 31 regSDMA3_RB_RPTR_FETCH 0 0x1d1c2 1 0 0 OFFSET 2 31 regSDMA3_IB_OFFSET_FETCH 0 0x1d1c3 1 0 0 OFFSET 2 21 regSDMA3_PROGRAM 0 0x1d1c4 1 0 0 STREAM 0 31 regSDMA3_STATUS_REG 0 0x1d1c5 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 regSDMA3_STATUS1_REG 0 0x1d1c6 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 regSDMA3_RD_BURST_CNTL 0 0x1d1c7 2 0 0 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 regSDMA3_HBM_PAGE_CONFIG 0 0x1d1c8 1 0 0 PAGE_SIZE_EXPONENT 0 1 regSDMA3_UCODE_CHECKSUM 0 0x1d1c9 1 0 0 DATA 0 31 regSDMA3_F32_CNTL 0 0x1d1ca 3 0 0 HALT 0 0 STEP 1 1 RESET 8 8 regSDMA3_FREEZE 0 0x1d1cb 4 0 0 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 regSDMA3_PHASE0_QUANTUM 0 0x1d1cc 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA3_PHASE1_QUANTUM 0 0x1d1cd 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regCC_SDMA3_EDC_CONFIG 0 0x1d1d2 1 0 0 DIS_EDC 1 1 regSDMA3_BA_THRESHOLD 0 0x1d1d3 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 regSDMA3_ID 0 0x1d1d4 1 0 0 DEVICE_ID 0 7 regSDMA3_VERSION 0 0x1d1d5 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 regSDMA3_EDC_COUNTER 0 0x1d1d6 16 0 0 SDMA_MBANK_DATA_BUF0_SED 0 1 SDMA_MBANK_DATA_BUF1_SED 2 3 SDMA_MBANK_DATA_BUF2_SED 4 5 SDMA_MBANK_DATA_BUF3_SED 6 7 SDMA_MBANK_DATA_BUF4_SED 8 9 SDMA_MBANK_DATA_BUF5_SED 10 11 SDMA_MBANK_DATA_BUF6_SED 12 13 SDMA_MBANK_DATA_BUF7_SED 14 15 SDMA_MBANK_DATA_BUF8_SED 16 17 SDMA_MBANK_DATA_BUF9_SED 18 19 SDMA_MBANK_DATA_BUF10_SED 20 21 SDMA_MBANK_DATA_BUF11_SED 22 23 SDMA_MBANK_DATA_BUF12_SED 24 25 SDMA_MBANK_DATA_BUF13_SED 26 27 SDMA_MBANK_DATA_BUF14_SED 28 29 SDMA_MBANK_DATA_BUF15_SED 30 31 regSDMA3_EDC_COUNTER2 0 0x1d1d7 10 0 0 SDMA_UCODE_BUF_SED 0 1 SDMA_RB_CMD_BUF_SED 2 3 SDMA_IB_CMD_BUF_SED 4 5 SDMA_UTCL1_RD_FIFO_SED 6 7 SDMA_UTCL1_RDBST_FIFO_SED 8 9 SDMA_UTCL1_WR_FIFO_SED 10 11 SDMA_DATA_LUT_FIFO_SED 12 13 SDMA_SPLIT_DATA_BUF_SED 14 15 SDMA_MC_WR_ADDR_FIFO_SED 16 17 SDMA_MC_RDRET_BUF_SED 18 19 regSDMA3_STATUS2_REG 0 0x1d1d8 3 0 0 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 regSDMA3_ATOMIC_CNTL 0 0x1d1d9 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 regSDMA3_ATOMIC_PREOP_LO 0 0x1d1da 1 0 0 DATA 0 31 regSDMA3_ATOMIC_PREOP_HI 0 0x1d1db 1 0 0 DATA 0 31 regSDMA3_UTCL1_CNTL 0 0x1d1dc 6 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 regSDMA3_UTCL1_WATERMK 0 0x1d1dd 5 0 0 REQ_WATERMK 0 2 REQ_DEPTH 3 4 PAGE_WATERMK 5 7 INVREQ_WATERMK 8 15 RESERVED 16 31 regSDMA3_UTCL1_RD_STATUS 0 0x1d1de 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 regSDMA3_UTCL1_WR_STATUS 0 0x1d1df 28 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 regSDMA3_UTCL1_INV0 0 0x1d1e0 14 0 0 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 regSDMA3_UTCL1_INV1 0 0x1d1e1 1 0 0 INV_ADDR_LO 0 31 regSDMA3_UTCL1_INV2 0 0x1d1e2 1 0 0 INV_NFLUSH_VMID_VEC 0 31 regSDMA3_UTCL1_RD_XNACK0 0 0x1d1e3 1 0 0 XNACK_ADDR_LO 0 31 regSDMA3_UTCL1_RD_XNACK1 0 0x1d1e4 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA3_UTCL1_WR_XNACK0 0 0x1d1e5 1 0 0 XNACK_ADDR_LO 0 31 regSDMA3_UTCL1_WR_XNACK1 0 0x1d1e6 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA3_UTCL1_TIMEOUT 0 0x1d1e7 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 regSDMA3_UTCL1_PAGE 0 0x1d1e8 4 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 regSDMA3_POWER_CNTL_IDLE 0 0x1d1e9 3 0 0 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 regSDMA3_RELAX_ORDERING_LUT 0 0x1d1ea 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 regSDMA3_CHICKEN_BITS_2 0 0x1d1eb 2 0 0 F32_CMD_PROC_DELAY 0 3 F32_SEND_POSTCODE_EN 4 4 regSDMA3_STATUS3_REG 0 0x1d1ec 5 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 regSDMA3_PHYSICAL_ADDR_LO 0 0x1d1ed 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 regSDMA3_PHYSICAL_ADDR_HI 0 0x1d1ee 1 0 0 ADDR 0 15 regSDMA3_PHASE2_QUANTUM 0 0x1d1ef 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA3_ERROR_LOG 0 0x1d1f0 2 0 0 OVERRIDE 0 15 STATUS 16 31 regSDMA3_PUB_DUMMY_REG0 0 0x1d1f1 1 0 0 VALUE 0 31 regSDMA3_PUB_DUMMY_REG1 0 0x1d1f2 1 0 0 VALUE 0 31 regSDMA3_PUB_DUMMY_REG2 0 0x1d1f3 1 0 0 VALUE 0 31 regSDMA3_PUB_DUMMY_REG3 0 0x1d1f4 1 0 0 VALUE 0 31 regSDMA3_F32_COUNTER 0 0x1d1f5 1 0 0 VALUE 0 31 regSDMA3_PERFCNT_PERFCOUNTER0_CFG 0 0x1d1f7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA3_PERFCNT_PERFCOUNTER1_CFG 0 0x1d1f8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x1d1f9 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regSDMA3_PERFCNT_MISC_CNTL 0 0x1d1fa 1 0 0 CMD_OP 0 15 regSDMA3_PERFCNT_PERFCOUNTER_LO 0 0x1d1fb 1 0 0 COUNTER_LO 0 31 regSDMA3_PERFCNT_PERFCOUNTER_HI 0 0x1d1fc 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regSDMA3_CRD_CNTL 0 0x1d1fd 2 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 regSDMA3_ULV_CNTL 0 0x1d1ff 6 0 0 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 regSDMA3_EA_DBIT_ADDR_DATA 0 0x1d200 1 0 0 VALUE 0 31 regSDMA3_EA_DBIT_ADDR_INDEX 0 0x1d201 1 0 0 VALUE 0 2 regSDMA3_STATUS4_REG 0 0x1d203 14 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 MMHUB_RD_OUTSTANDING 4 4 MMHUB_WR_OUTSTANDING 5 5 UTCL2_RD_OUTSTANDING 6 6 UTCL2_WR_OUTSTANDING 7 7 REG_POLLING 8 8 MEM_POLLING 9 9 UTCL2_RD_XNACK 10 11 UTCL2_WR_XNACK 12 13 ACTIVE_QUEUE_ID 14 17 SRIOV_WATING_RLCV_CMD 18 18 SRIOV_SDMA_EXECUTING_CMD 19 19 regSDMA3_SCRATCH_RAM_DATA 0 0x1d204 1 0 0 DATA 0 31 regSDMA3_SCRATCH_RAM_ADDR 0 0x1d205 1 0 0 ADDR 0 6 regSDMA3_CE_CTRL 0 0x1d206 4 0 0 RD_LUT_WATERMARK 0 2 RD_LUT_DEPTH 3 4 WR_AFIFO_WATERMARK 5 7 RESERVED 8 31 regSDMA3_RAS_STATUS 0 0x1d207 12 0 0 RB_FETCH_ECC 0 0 IB_FETCH_ECC 1 1 F32_DATA_ECC 2 2 SEM_WPTR_ATOMIC_ECC 3 3 COPY_DATA_ECC 4 4 SRAM_ECC 5 5 RB_FETCH_NACK_GEN_ERR 8 8 IB_FETCH_NACK_GEN_ERR 9 9 F32_DATA_NACK_GEN_ERR 10 10 COPY_DATA_NACK_GEN_ERR 11 11 WRRET_DATA_NACK_GEN_ERR 12 12 WPTR_RPTR_ATOMIC_NACK_GEN_ERR 13 13 regSDMA3_CLK_STATUS 0 0x1d208 4 0 0 DYN_CLK 0 0 PTR_CLK 1 1 REG_CLK 2 2 F32_CLK 3 3 regSDMA3_GFX_RB_CNTL 0 0x1d220 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_GFX_RB_BASE 0 0x1d221 1 0 0 ADDR 0 31 regSDMA3_GFX_RB_BASE_HI 0 0x1d222 1 0 0 ADDR 0 23 regSDMA3_GFX_RB_RPTR 0 0x1d223 1 0 0 OFFSET 0 31 regSDMA3_GFX_RB_RPTR_HI 0 0x1d224 1 0 0 OFFSET 0 31 regSDMA3_GFX_RB_WPTR 0 0x1d225 1 0 0 OFFSET 0 31 regSDMA3_GFX_RB_WPTR_HI 0 0x1d226 1 0 0 OFFSET 0 31 regSDMA3_GFX_RB_WPTR_POLL_CNTL 0 0x1d227 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_GFX_RB_RPTR_ADDR_HI 0 0x1d228 1 0 0 ADDR 0 31 regSDMA3_GFX_RB_RPTR_ADDR_LO 0 0x1d229 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_GFX_IB_CNTL 0 0x1d22a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_GFX_IB_RPTR 0 0x1d22b 1 0 0 OFFSET 2 21 regSDMA3_GFX_IB_OFFSET 0 0x1d22c 1 0 0 OFFSET 2 21 regSDMA3_GFX_IB_BASE_LO 0 0x1d22d 1 0 0 ADDR 5 31 regSDMA3_GFX_IB_BASE_HI 0 0x1d22e 1 0 0 ADDR 0 31 regSDMA3_GFX_IB_SIZE 0 0x1d22f 1 0 0 SIZE 0 19 regSDMA3_GFX_SKIP_CNTL 0 0x1d230 1 0 0 SKIP_COUNT 0 19 regSDMA3_GFX_CONTEXT_STATUS 0 0x1d231 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_GFX_DOORBELL 0 0x1d232 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_GFX_CONTEXT_CNTL 0 0x1d233 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 regSDMA3_GFX_STATUS 0 0x1d248 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_GFX_DOORBELL_LOG 0 0x1d249 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_GFX_WATERMARK 0 0x1d24a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_GFX_DOORBELL_OFFSET 0 0x1d24b 1 0 0 OFFSET 2 27 regSDMA3_GFX_CSA_ADDR_LO 0 0x1d24c 1 0 0 ADDR 2 31 regSDMA3_GFX_CSA_ADDR_HI 0 0x1d24d 1 0 0 ADDR 0 31 regSDMA3_GFX_IB_SUB_REMAIN 0 0x1d24f 1 0 0 SIZE 0 19 regSDMA3_GFX_PREEMPT 0 0x1d250 1 0 0 IB_PREEMPT 0 0 regSDMA3_GFX_DUMMY_REG 0 0x1d251 1 0 0 DUMMY 0 31 regSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0 0x1d252 1 0 0 ADDR 0 31 regSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0 0x1d253 1 0 0 ADDR 2 31 regSDMA3_GFX_RB_AQL_CNTL 0 0x1d254 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_GFX_MINOR_PTR_UPDATE 0 0x1d255 1 0 0 ENABLE 0 0 regSDMA3_GFX_MIDCMD_DATA0 0 0x1d260 1 0 0 DATA0 0 31 regSDMA3_GFX_MIDCMD_DATA1 0 0x1d261 1 0 0 DATA1 0 31 regSDMA3_GFX_MIDCMD_DATA2 0 0x1d262 1 0 0 DATA2 0 31 regSDMA3_GFX_MIDCMD_DATA3 0 0x1d263 1 0 0 DATA3 0 31 regSDMA3_GFX_MIDCMD_DATA4 0 0x1d264 1 0 0 DATA4 0 31 regSDMA3_GFX_MIDCMD_DATA5 0 0x1d265 1 0 0 DATA5 0 31 regSDMA3_GFX_MIDCMD_DATA6 0 0x1d266 1 0 0 DATA6 0 31 regSDMA3_GFX_MIDCMD_DATA7 0 0x1d267 1 0 0 DATA7 0 31 regSDMA3_GFX_MIDCMD_DATA8 0 0x1d268 1 0 0 DATA8 0 31 regSDMA3_GFX_MIDCMD_DATA9 0 0x1d269 1 0 0 DATA9 0 31 regSDMA3_GFX_MIDCMD_DATA10 0 0x1d26a 1 0 0 DATA10 0 31 regSDMA3_GFX_MIDCMD_CNTL 0 0x1d26b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_PAGE_RB_CNTL 0 0x1d278 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_PAGE_RB_BASE 0 0x1d279 1 0 0 ADDR 0 31 regSDMA3_PAGE_RB_BASE_HI 0 0x1d27a 1 0 0 ADDR 0 23 regSDMA3_PAGE_RB_RPTR 0 0x1d27b 1 0 0 OFFSET 0 31 regSDMA3_PAGE_RB_RPTR_HI 0 0x1d27c 1 0 0 OFFSET 0 31 regSDMA3_PAGE_RB_WPTR 0 0x1d27d 1 0 0 OFFSET 0 31 regSDMA3_PAGE_RB_WPTR_HI 0 0x1d27e 1 0 0 OFFSET 0 31 regSDMA3_PAGE_RB_WPTR_POLL_CNTL 0 0x1d27f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_PAGE_RB_RPTR_ADDR_HI 0 0x1d280 1 0 0 ADDR 0 31 regSDMA3_PAGE_RB_RPTR_ADDR_LO 0 0x1d281 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_PAGE_IB_CNTL 0 0x1d282 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_PAGE_IB_RPTR 0 0x1d283 1 0 0 OFFSET 2 21 regSDMA3_PAGE_IB_OFFSET 0 0x1d284 1 0 0 OFFSET 2 21 regSDMA3_PAGE_IB_BASE_LO 0 0x1d285 1 0 0 ADDR 5 31 regSDMA3_PAGE_IB_BASE_HI 0 0x1d286 1 0 0 ADDR 0 31 regSDMA3_PAGE_IB_SIZE 0 0x1d287 1 0 0 SIZE 0 19 regSDMA3_PAGE_SKIP_CNTL 0 0x1d288 1 0 0 SKIP_COUNT 0 19 regSDMA3_PAGE_CONTEXT_STATUS 0 0x1d289 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_PAGE_DOORBELL 0 0x1d28a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_PAGE_STATUS 0 0x1d2a0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_PAGE_DOORBELL_LOG 0 0x1d2a1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_PAGE_WATERMARK 0 0x1d2a2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_PAGE_DOORBELL_OFFSET 0 0x1d2a3 1 0 0 OFFSET 2 27 regSDMA3_PAGE_CSA_ADDR_LO 0 0x1d2a4 1 0 0 ADDR 2 31 regSDMA3_PAGE_CSA_ADDR_HI 0 0x1d2a5 1 0 0 ADDR 0 31 regSDMA3_PAGE_IB_SUB_REMAIN 0 0x1d2a7 1 0 0 SIZE 0 19 regSDMA3_PAGE_PREEMPT 0 0x1d2a8 1 0 0 IB_PREEMPT 0 0 regSDMA3_PAGE_DUMMY_REG 0 0x1d2a9 1 0 0 DUMMY 0 31 regSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x1d2aa 1 0 0 ADDR 0 31 regSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x1d2ab 1 0 0 ADDR 2 31 regSDMA3_PAGE_RB_AQL_CNTL 0 0x1d2ac 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_PAGE_MINOR_PTR_UPDATE 0 0x1d2ad 1 0 0 ENABLE 0 0 regSDMA3_PAGE_MIDCMD_DATA0 0 0x1d2b8 1 0 0 DATA0 0 31 regSDMA3_PAGE_MIDCMD_DATA1 0 0x1d2b9 1 0 0 DATA1 0 31 regSDMA3_PAGE_MIDCMD_DATA2 0 0x1d2ba 1 0 0 DATA2 0 31 regSDMA3_PAGE_MIDCMD_DATA3 0 0x1d2bb 1 0 0 DATA3 0 31 regSDMA3_PAGE_MIDCMD_DATA4 0 0x1d2bc 1 0 0 DATA4 0 31 regSDMA3_PAGE_MIDCMD_DATA5 0 0x1d2bd 1 0 0 DATA5 0 31 regSDMA3_PAGE_MIDCMD_DATA6 0 0x1d2be 1 0 0 DATA6 0 31 regSDMA3_PAGE_MIDCMD_DATA7 0 0x1d2bf 1 0 0 DATA7 0 31 regSDMA3_PAGE_MIDCMD_DATA8 0 0x1d2c0 1 0 0 DATA8 0 31 regSDMA3_PAGE_MIDCMD_DATA9 0 0x1d2c1 1 0 0 DATA9 0 31 regSDMA3_PAGE_MIDCMD_DATA10 0 0x1d2c2 1 0 0 DATA10 0 31 regSDMA3_PAGE_MIDCMD_CNTL 0 0x1d2c3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC0_RB_CNTL 0 0x1d2d0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC0_RB_BASE 0 0x1d2d1 1 0 0 ADDR 0 31 regSDMA3_RLC0_RB_BASE_HI 0 0x1d2d2 1 0 0 ADDR 0 23 regSDMA3_RLC0_RB_RPTR 0 0x1d2d3 1 0 0 OFFSET 0 31 regSDMA3_RLC0_RB_RPTR_HI 0 0x1d2d4 1 0 0 OFFSET 0 31 regSDMA3_RLC0_RB_WPTR 0 0x1d2d5 1 0 0 OFFSET 0 31 regSDMA3_RLC0_RB_WPTR_HI 0 0x1d2d6 1 0 0 OFFSET 0 31 regSDMA3_RLC0_RB_WPTR_POLL_CNTL 0 0x1d2d7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC0_RB_RPTR_ADDR_HI 0 0x1d2d8 1 0 0 ADDR 0 31 regSDMA3_RLC0_RB_RPTR_ADDR_LO 0 0x1d2d9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC0_IB_CNTL 0 0x1d2da 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC0_IB_RPTR 0 0x1d2db 1 0 0 OFFSET 2 21 regSDMA3_RLC0_IB_OFFSET 0 0x1d2dc 1 0 0 OFFSET 2 21 regSDMA3_RLC0_IB_BASE_LO 0 0x1d2dd 1 0 0 ADDR 5 31 regSDMA3_RLC0_IB_BASE_HI 0 0x1d2de 1 0 0 ADDR 0 31 regSDMA3_RLC0_IB_SIZE 0 0x1d2df 1 0 0 SIZE 0 19 regSDMA3_RLC0_SKIP_CNTL 0 0x1d2e0 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC0_CONTEXT_STATUS 0 0x1d2e1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC0_DOORBELL 0 0x1d2e2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC0_STATUS 0 0x1d2f8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC0_DOORBELL_LOG 0 0x1d2f9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC0_WATERMARK 0 0x1d2fa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC0_DOORBELL_OFFSET 0 0x1d2fb 1 0 0 OFFSET 2 27 regSDMA3_RLC0_CSA_ADDR_LO 0 0x1d2fc 1 0 0 ADDR 2 31 regSDMA3_RLC0_CSA_ADDR_HI 0 0x1d2fd 1 0 0 ADDR 0 31 regSDMA3_RLC0_IB_SUB_REMAIN 0 0x1d2ff 1 0 0 SIZE 0 19 regSDMA3_RLC0_PREEMPT 0 0x1d300 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC0_DUMMY_REG 0 0x1d301 1 0 0 DUMMY 0 31 regSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x1d302 1 0 0 ADDR 0 31 regSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x1d303 1 0 0 ADDR 2 31 regSDMA3_RLC0_RB_AQL_CNTL 0 0x1d304 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC0_MINOR_PTR_UPDATE 0 0x1d305 1 0 0 ENABLE 0 0 regSDMA3_RLC0_MIDCMD_DATA0 0 0x1d310 1 0 0 DATA0 0 31 regSDMA3_RLC0_MIDCMD_DATA1 0 0x1d311 1 0 0 DATA1 0 31 regSDMA3_RLC0_MIDCMD_DATA2 0 0x1d312 1 0 0 DATA2 0 31 regSDMA3_RLC0_MIDCMD_DATA3 0 0x1d313 1 0 0 DATA3 0 31 regSDMA3_RLC0_MIDCMD_DATA4 0 0x1d314 1 0 0 DATA4 0 31 regSDMA3_RLC0_MIDCMD_DATA5 0 0x1d315 1 0 0 DATA5 0 31 regSDMA3_RLC0_MIDCMD_DATA6 0 0x1d316 1 0 0 DATA6 0 31 regSDMA3_RLC0_MIDCMD_DATA7 0 0x1d317 1 0 0 DATA7 0 31 regSDMA3_RLC0_MIDCMD_DATA8 0 0x1d318 1 0 0 DATA8 0 31 regSDMA3_RLC0_MIDCMD_DATA9 0 0x1d319 1 0 0 DATA9 0 31 regSDMA3_RLC0_MIDCMD_DATA10 0 0x1d31a 1 0 0 DATA10 0 31 regSDMA3_RLC0_MIDCMD_CNTL 0 0x1d31b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC1_RB_CNTL 0 0x1d328 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC1_RB_BASE 0 0x1d329 1 0 0 ADDR 0 31 regSDMA3_RLC1_RB_BASE_HI 0 0x1d32a 1 0 0 ADDR 0 23 regSDMA3_RLC1_RB_RPTR 0 0x1d32b 1 0 0 OFFSET 0 31 regSDMA3_RLC1_RB_RPTR_HI 0 0x1d32c 1 0 0 OFFSET 0 31 regSDMA3_RLC1_RB_WPTR 0 0x1d32d 1 0 0 OFFSET 0 31 regSDMA3_RLC1_RB_WPTR_HI 0 0x1d32e 1 0 0 OFFSET 0 31 regSDMA3_RLC1_RB_WPTR_POLL_CNTL 0 0x1d32f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC1_RB_RPTR_ADDR_HI 0 0x1d330 1 0 0 ADDR 0 31 regSDMA3_RLC1_RB_RPTR_ADDR_LO 0 0x1d331 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC1_IB_CNTL 0 0x1d332 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC1_IB_RPTR 0 0x1d333 1 0 0 OFFSET 2 21 regSDMA3_RLC1_IB_OFFSET 0 0x1d334 1 0 0 OFFSET 2 21 regSDMA3_RLC1_IB_BASE_LO 0 0x1d335 1 0 0 ADDR 5 31 regSDMA3_RLC1_IB_BASE_HI 0 0x1d336 1 0 0 ADDR 0 31 regSDMA3_RLC1_IB_SIZE 0 0x1d337 1 0 0 SIZE 0 19 regSDMA3_RLC1_SKIP_CNTL 0 0x1d338 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC1_CONTEXT_STATUS 0 0x1d339 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC1_DOORBELL 0 0x1d33a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC1_STATUS 0 0x1d350 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC1_DOORBELL_LOG 0 0x1d351 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC1_WATERMARK 0 0x1d352 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC1_DOORBELL_OFFSET 0 0x1d353 1 0 0 OFFSET 2 27 regSDMA3_RLC1_CSA_ADDR_LO 0 0x1d354 1 0 0 ADDR 2 31 regSDMA3_RLC1_CSA_ADDR_HI 0 0x1d355 1 0 0 ADDR 0 31 regSDMA3_RLC1_IB_SUB_REMAIN 0 0x1d357 1 0 0 SIZE 0 19 regSDMA3_RLC1_PREEMPT 0 0x1d358 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC1_DUMMY_REG 0 0x1d359 1 0 0 DUMMY 0 31 regSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1d35a 1 0 0 ADDR 0 31 regSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1d35b 1 0 0 ADDR 2 31 regSDMA3_RLC1_RB_AQL_CNTL 0 0x1d35c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC1_MINOR_PTR_UPDATE 0 0x1d35d 1 0 0 ENABLE 0 0 regSDMA3_RLC1_MIDCMD_DATA0 0 0x1d368 1 0 0 DATA0 0 31 regSDMA3_RLC1_MIDCMD_DATA1 0 0x1d369 1 0 0 DATA1 0 31 regSDMA3_RLC1_MIDCMD_DATA2 0 0x1d36a 1 0 0 DATA2 0 31 regSDMA3_RLC1_MIDCMD_DATA3 0 0x1d36b 1 0 0 DATA3 0 31 regSDMA3_RLC1_MIDCMD_DATA4 0 0x1d36c 1 0 0 DATA4 0 31 regSDMA3_RLC1_MIDCMD_DATA5 0 0x1d36d 1 0 0 DATA5 0 31 regSDMA3_RLC1_MIDCMD_DATA6 0 0x1d36e 1 0 0 DATA6 0 31 regSDMA3_RLC1_MIDCMD_DATA7 0 0x1d36f 1 0 0 DATA7 0 31 regSDMA3_RLC1_MIDCMD_DATA8 0 0x1d370 1 0 0 DATA8 0 31 regSDMA3_RLC1_MIDCMD_DATA9 0 0x1d371 1 0 0 DATA9 0 31 regSDMA3_RLC1_MIDCMD_DATA10 0 0x1d372 1 0 0 DATA10 0 31 regSDMA3_RLC1_MIDCMD_CNTL 0 0x1d373 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC2_RB_CNTL 0 0x1d380 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC2_RB_BASE 0 0x1d381 1 0 0 ADDR 0 31 regSDMA3_RLC2_RB_BASE_HI 0 0x1d382 1 0 0 ADDR 0 23 regSDMA3_RLC2_RB_RPTR 0 0x1d383 1 0 0 OFFSET 0 31 regSDMA3_RLC2_RB_RPTR_HI 0 0x1d384 1 0 0 OFFSET 0 31 regSDMA3_RLC2_RB_WPTR 0 0x1d385 1 0 0 OFFSET 0 31 regSDMA3_RLC2_RB_WPTR_HI 0 0x1d386 1 0 0 OFFSET 0 31 regSDMA3_RLC2_RB_WPTR_POLL_CNTL 0 0x1d387 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC2_RB_RPTR_ADDR_HI 0 0x1d388 1 0 0 ADDR 0 31 regSDMA3_RLC2_RB_RPTR_ADDR_LO 0 0x1d389 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC2_IB_CNTL 0 0x1d38a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC2_IB_RPTR 0 0x1d38b 1 0 0 OFFSET 2 21 regSDMA3_RLC2_IB_OFFSET 0 0x1d38c 1 0 0 OFFSET 2 21 regSDMA3_RLC2_IB_BASE_LO 0 0x1d38d 1 0 0 ADDR 5 31 regSDMA3_RLC2_IB_BASE_HI 0 0x1d38e 1 0 0 ADDR 0 31 regSDMA3_RLC2_IB_SIZE 0 0x1d38f 1 0 0 SIZE 0 19 regSDMA3_RLC2_SKIP_CNTL 0 0x1d390 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC2_CONTEXT_STATUS 0 0x1d391 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC2_DOORBELL 0 0x1d392 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC2_STATUS 0 0x1d3a8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC2_DOORBELL_LOG 0 0x1d3a9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC2_WATERMARK 0 0x1d3aa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC2_DOORBELL_OFFSET 0 0x1d3ab 1 0 0 OFFSET 2 27 regSDMA3_RLC2_CSA_ADDR_LO 0 0x1d3ac 1 0 0 ADDR 2 31 regSDMA3_RLC2_CSA_ADDR_HI 0 0x1d3ad 1 0 0 ADDR 0 31 regSDMA3_RLC2_IB_SUB_REMAIN 0 0x1d3af 1 0 0 SIZE 0 19 regSDMA3_RLC2_PREEMPT 0 0x1d3b0 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC2_DUMMY_REG 0 0x1d3b1 1 0 0 DUMMY 0 31 regSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x1d3b2 1 0 0 ADDR 0 31 regSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x1d3b3 1 0 0 ADDR 2 31 regSDMA3_RLC2_RB_AQL_CNTL 0 0x1d3b4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC2_MINOR_PTR_UPDATE 0 0x1d3b5 1 0 0 ENABLE 0 0 regSDMA3_RLC2_MIDCMD_DATA0 0 0x1d3c0 1 0 0 DATA0 0 31 regSDMA3_RLC2_MIDCMD_DATA1 0 0x1d3c1 1 0 0 DATA1 0 31 regSDMA3_RLC2_MIDCMD_DATA2 0 0x1d3c2 1 0 0 DATA2 0 31 regSDMA3_RLC2_MIDCMD_DATA3 0 0x1d3c3 1 0 0 DATA3 0 31 regSDMA3_RLC2_MIDCMD_DATA4 0 0x1d3c4 1 0 0 DATA4 0 31 regSDMA3_RLC2_MIDCMD_DATA5 0 0x1d3c5 1 0 0 DATA5 0 31 regSDMA3_RLC2_MIDCMD_DATA6 0 0x1d3c6 1 0 0 DATA6 0 31 regSDMA3_RLC2_MIDCMD_DATA7 0 0x1d3c7 1 0 0 DATA7 0 31 regSDMA3_RLC2_MIDCMD_DATA8 0 0x1d3c8 1 0 0 DATA8 0 31 regSDMA3_RLC2_MIDCMD_DATA9 0 0x1d3c9 1 0 0 DATA9 0 31 regSDMA3_RLC2_MIDCMD_DATA10 0 0x1d3ca 1 0 0 DATA10 0 31 regSDMA3_RLC2_MIDCMD_CNTL 0 0x1d3cb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC3_RB_CNTL 0 0x1d3d8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC3_RB_BASE 0 0x1d3d9 1 0 0 ADDR 0 31 regSDMA3_RLC3_RB_BASE_HI 0 0x1d3da 1 0 0 ADDR 0 23 regSDMA3_RLC3_RB_RPTR 0 0x1d3db 1 0 0 OFFSET 0 31 regSDMA3_RLC3_RB_RPTR_HI 0 0x1d3dc 1 0 0 OFFSET 0 31 regSDMA3_RLC3_RB_WPTR 0 0x1d3dd 1 0 0 OFFSET 0 31 regSDMA3_RLC3_RB_WPTR_HI 0 0x1d3de 1 0 0 OFFSET 0 31 regSDMA3_RLC3_RB_WPTR_POLL_CNTL 0 0x1d3df 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC3_RB_RPTR_ADDR_HI 0 0x1d3e0 1 0 0 ADDR 0 31 regSDMA3_RLC3_RB_RPTR_ADDR_LO 0 0x1d3e1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC3_IB_CNTL 0 0x1d3e2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC3_IB_RPTR 0 0x1d3e3 1 0 0 OFFSET 2 21 regSDMA3_RLC3_IB_OFFSET 0 0x1d3e4 1 0 0 OFFSET 2 21 regSDMA3_RLC3_IB_BASE_LO 0 0x1d3e5 1 0 0 ADDR 5 31 regSDMA3_RLC3_IB_BASE_HI 0 0x1d3e6 1 0 0 ADDR 0 31 regSDMA3_RLC3_IB_SIZE 0 0x1d3e7 1 0 0 SIZE 0 19 regSDMA3_RLC3_SKIP_CNTL 0 0x1d3e8 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC3_CONTEXT_STATUS 0 0x1d3e9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC3_DOORBELL 0 0x1d3ea 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC3_STATUS 0 0x1d400 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC3_DOORBELL_LOG 0 0x1d401 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC3_WATERMARK 0 0x1d402 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC3_DOORBELL_OFFSET 0 0x1d403 1 0 0 OFFSET 2 27 regSDMA3_RLC3_CSA_ADDR_LO 0 0x1d404 1 0 0 ADDR 2 31 regSDMA3_RLC3_CSA_ADDR_HI 0 0x1d405 1 0 0 ADDR 0 31 regSDMA3_RLC3_IB_SUB_REMAIN 0 0x1d407 1 0 0 SIZE 0 19 regSDMA3_RLC3_PREEMPT 0 0x1d408 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC3_DUMMY_REG 0 0x1d409 1 0 0 DUMMY 0 31 regSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x1d40a 1 0 0 ADDR 0 31 regSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x1d40b 1 0 0 ADDR 2 31 regSDMA3_RLC3_RB_AQL_CNTL 0 0x1d40c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC3_MINOR_PTR_UPDATE 0 0x1d40d 1 0 0 ENABLE 0 0 regSDMA3_RLC3_MIDCMD_DATA0 0 0x1d418 1 0 0 DATA0 0 31 regSDMA3_RLC3_MIDCMD_DATA1 0 0x1d419 1 0 0 DATA1 0 31 regSDMA3_RLC3_MIDCMD_DATA2 0 0x1d41a 1 0 0 DATA2 0 31 regSDMA3_RLC3_MIDCMD_DATA3 0 0x1d41b 1 0 0 DATA3 0 31 regSDMA3_RLC3_MIDCMD_DATA4 0 0x1d41c 1 0 0 DATA4 0 31 regSDMA3_RLC3_MIDCMD_DATA5 0 0x1d41d 1 0 0 DATA5 0 31 regSDMA3_RLC3_MIDCMD_DATA6 0 0x1d41e 1 0 0 DATA6 0 31 regSDMA3_RLC3_MIDCMD_DATA7 0 0x1d41f 1 0 0 DATA7 0 31 regSDMA3_RLC3_MIDCMD_DATA8 0 0x1d420 1 0 0 DATA8 0 31 regSDMA3_RLC3_MIDCMD_DATA9 0 0x1d421 1 0 0 DATA9 0 31 regSDMA3_RLC3_MIDCMD_DATA10 0 0x1d422 1 0 0 DATA10 0 31 regSDMA3_RLC3_MIDCMD_CNTL 0 0x1d423 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC4_RB_CNTL 0 0x1d430 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC4_RB_BASE 0 0x1d431 1 0 0 ADDR 0 31 regSDMA3_RLC4_RB_BASE_HI 0 0x1d432 1 0 0 ADDR 0 23 regSDMA3_RLC4_RB_RPTR 0 0x1d433 1 0 0 OFFSET 0 31 regSDMA3_RLC4_RB_RPTR_HI 0 0x1d434 1 0 0 OFFSET 0 31 regSDMA3_RLC4_RB_WPTR 0 0x1d435 1 0 0 OFFSET 0 31 regSDMA3_RLC4_RB_WPTR_HI 0 0x1d436 1 0 0 OFFSET 0 31 regSDMA3_RLC4_RB_WPTR_POLL_CNTL 0 0x1d437 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC4_RB_RPTR_ADDR_HI 0 0x1d438 1 0 0 ADDR 0 31 regSDMA3_RLC4_RB_RPTR_ADDR_LO 0 0x1d439 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC4_IB_CNTL 0 0x1d43a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC4_IB_RPTR 0 0x1d43b 1 0 0 OFFSET 2 21 regSDMA3_RLC4_IB_OFFSET 0 0x1d43c 1 0 0 OFFSET 2 21 regSDMA3_RLC4_IB_BASE_LO 0 0x1d43d 1 0 0 ADDR 5 31 regSDMA3_RLC4_IB_BASE_HI 0 0x1d43e 1 0 0 ADDR 0 31 regSDMA3_RLC4_IB_SIZE 0 0x1d43f 1 0 0 SIZE 0 19 regSDMA3_RLC4_SKIP_CNTL 0 0x1d440 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC4_CONTEXT_STATUS 0 0x1d441 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC4_DOORBELL 0 0x1d442 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC4_STATUS 0 0x1d458 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC4_DOORBELL_LOG 0 0x1d459 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC4_WATERMARK 0 0x1d45a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC4_DOORBELL_OFFSET 0 0x1d45b 1 0 0 OFFSET 2 27 regSDMA3_RLC4_CSA_ADDR_LO 0 0x1d45c 1 0 0 ADDR 2 31 regSDMA3_RLC4_CSA_ADDR_HI 0 0x1d45d 1 0 0 ADDR 0 31 regSDMA3_RLC4_IB_SUB_REMAIN 0 0x1d45f 1 0 0 SIZE 0 19 regSDMA3_RLC4_PREEMPT 0 0x1d460 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC4_DUMMY_REG 0 0x1d461 1 0 0 DUMMY 0 31 regSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x1d462 1 0 0 ADDR 0 31 regSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x1d463 1 0 0 ADDR 2 31 regSDMA3_RLC4_RB_AQL_CNTL 0 0x1d464 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC4_MINOR_PTR_UPDATE 0 0x1d465 1 0 0 ENABLE 0 0 regSDMA3_RLC4_MIDCMD_DATA0 0 0x1d470 1 0 0 DATA0 0 31 regSDMA3_RLC4_MIDCMD_DATA1 0 0x1d471 1 0 0 DATA1 0 31 regSDMA3_RLC4_MIDCMD_DATA2 0 0x1d472 1 0 0 DATA2 0 31 regSDMA3_RLC4_MIDCMD_DATA3 0 0x1d473 1 0 0 DATA3 0 31 regSDMA3_RLC4_MIDCMD_DATA4 0 0x1d474 1 0 0 DATA4 0 31 regSDMA3_RLC4_MIDCMD_DATA5 0 0x1d475 1 0 0 DATA5 0 31 regSDMA3_RLC4_MIDCMD_DATA6 0 0x1d476 1 0 0 DATA6 0 31 regSDMA3_RLC4_MIDCMD_DATA7 0 0x1d477 1 0 0 DATA7 0 31 regSDMA3_RLC4_MIDCMD_DATA8 0 0x1d478 1 0 0 DATA8 0 31 regSDMA3_RLC4_MIDCMD_DATA9 0 0x1d479 1 0 0 DATA9 0 31 regSDMA3_RLC4_MIDCMD_DATA10 0 0x1d47a 1 0 0 DATA10 0 31 regSDMA3_RLC4_MIDCMD_CNTL 0 0x1d47b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC5_RB_CNTL 0 0x1d488 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC5_RB_BASE 0 0x1d489 1 0 0 ADDR 0 31 regSDMA3_RLC5_RB_BASE_HI 0 0x1d48a 1 0 0 ADDR 0 23 regSDMA3_RLC5_RB_RPTR 0 0x1d48b 1 0 0 OFFSET 0 31 regSDMA3_RLC5_RB_RPTR_HI 0 0x1d48c 1 0 0 OFFSET 0 31 regSDMA3_RLC5_RB_WPTR 0 0x1d48d 1 0 0 OFFSET 0 31 regSDMA3_RLC5_RB_WPTR_HI 0 0x1d48e 1 0 0 OFFSET 0 31 regSDMA3_RLC5_RB_WPTR_POLL_CNTL 0 0x1d48f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC5_RB_RPTR_ADDR_HI 0 0x1d490 1 0 0 ADDR 0 31 regSDMA3_RLC5_RB_RPTR_ADDR_LO 0 0x1d491 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC5_IB_CNTL 0 0x1d492 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC5_IB_RPTR 0 0x1d493 1 0 0 OFFSET 2 21 regSDMA3_RLC5_IB_OFFSET 0 0x1d494 1 0 0 OFFSET 2 21 regSDMA3_RLC5_IB_BASE_LO 0 0x1d495 1 0 0 ADDR 5 31 regSDMA3_RLC5_IB_BASE_HI 0 0x1d496 1 0 0 ADDR 0 31 regSDMA3_RLC5_IB_SIZE 0 0x1d497 1 0 0 SIZE 0 19 regSDMA3_RLC5_SKIP_CNTL 0 0x1d498 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC5_CONTEXT_STATUS 0 0x1d499 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC5_DOORBELL 0 0x1d49a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC5_STATUS 0 0x1d4b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC5_DOORBELL_LOG 0 0x1d4b1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC5_WATERMARK 0 0x1d4b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC5_DOORBELL_OFFSET 0 0x1d4b3 1 0 0 OFFSET 2 27 regSDMA3_RLC5_CSA_ADDR_LO 0 0x1d4b4 1 0 0 ADDR 2 31 regSDMA3_RLC5_CSA_ADDR_HI 0 0x1d4b5 1 0 0 ADDR 0 31 regSDMA3_RLC5_IB_SUB_REMAIN 0 0x1d4b7 1 0 0 SIZE 0 19 regSDMA3_RLC5_PREEMPT 0 0x1d4b8 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC5_DUMMY_REG 0 0x1d4b9 1 0 0 DUMMY 0 31 regSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x1d4ba 1 0 0 ADDR 0 31 regSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x1d4bb 1 0 0 ADDR 2 31 regSDMA3_RLC5_RB_AQL_CNTL 0 0x1d4bc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC5_MINOR_PTR_UPDATE 0 0x1d4bd 1 0 0 ENABLE 0 0 regSDMA3_RLC5_MIDCMD_DATA0 0 0x1d4c8 1 0 0 DATA0 0 31 regSDMA3_RLC5_MIDCMD_DATA1 0 0x1d4c9 1 0 0 DATA1 0 31 regSDMA3_RLC5_MIDCMD_DATA2 0 0x1d4ca 1 0 0 DATA2 0 31 regSDMA3_RLC5_MIDCMD_DATA3 0 0x1d4cb 1 0 0 DATA3 0 31 regSDMA3_RLC5_MIDCMD_DATA4 0 0x1d4cc 1 0 0 DATA4 0 31 regSDMA3_RLC5_MIDCMD_DATA5 0 0x1d4cd 1 0 0 DATA5 0 31 regSDMA3_RLC5_MIDCMD_DATA6 0 0x1d4ce 1 0 0 DATA6 0 31 regSDMA3_RLC5_MIDCMD_DATA7 0 0x1d4cf 1 0 0 DATA7 0 31 regSDMA3_RLC5_MIDCMD_DATA8 0 0x1d4d0 1 0 0 DATA8 0 31 regSDMA3_RLC5_MIDCMD_DATA9 0 0x1d4d1 1 0 0 DATA9 0 31 regSDMA3_RLC5_MIDCMD_DATA10 0 0x1d4d2 1 0 0 DATA10 0 31 regSDMA3_RLC5_MIDCMD_CNTL 0 0x1d4d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC6_RB_CNTL 0 0x1d4e0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC6_RB_BASE 0 0x1d4e1 1 0 0 ADDR 0 31 regSDMA3_RLC6_RB_BASE_HI 0 0x1d4e2 1 0 0 ADDR 0 23 regSDMA3_RLC6_RB_RPTR 0 0x1d4e3 1 0 0 OFFSET 0 31 regSDMA3_RLC6_RB_RPTR_HI 0 0x1d4e4 1 0 0 OFFSET 0 31 regSDMA3_RLC6_RB_WPTR 0 0x1d4e5 1 0 0 OFFSET 0 31 regSDMA3_RLC6_RB_WPTR_HI 0 0x1d4e6 1 0 0 OFFSET 0 31 regSDMA3_RLC6_RB_WPTR_POLL_CNTL 0 0x1d4e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC6_RB_RPTR_ADDR_HI 0 0x1d4e8 1 0 0 ADDR 0 31 regSDMA3_RLC6_RB_RPTR_ADDR_LO 0 0x1d4e9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC6_IB_CNTL 0 0x1d4ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC6_IB_RPTR 0 0x1d4eb 1 0 0 OFFSET 2 21 regSDMA3_RLC6_IB_OFFSET 0 0x1d4ec 1 0 0 OFFSET 2 21 regSDMA3_RLC6_IB_BASE_LO 0 0x1d4ed 1 0 0 ADDR 5 31 regSDMA3_RLC6_IB_BASE_HI 0 0x1d4ee 1 0 0 ADDR 0 31 regSDMA3_RLC6_IB_SIZE 0 0x1d4ef 1 0 0 SIZE 0 19 regSDMA3_RLC6_SKIP_CNTL 0 0x1d4f0 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC6_CONTEXT_STATUS 0 0x1d4f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC6_DOORBELL 0 0x1d4f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC6_STATUS 0 0x1d508 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC6_DOORBELL_LOG 0 0x1d509 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC6_WATERMARK 0 0x1d50a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC6_DOORBELL_OFFSET 0 0x1d50b 1 0 0 OFFSET 2 27 regSDMA3_RLC6_CSA_ADDR_LO 0 0x1d50c 1 0 0 ADDR 2 31 regSDMA3_RLC6_CSA_ADDR_HI 0 0x1d50d 1 0 0 ADDR 0 31 regSDMA3_RLC6_IB_SUB_REMAIN 0 0x1d50f 1 0 0 SIZE 0 19 regSDMA3_RLC6_PREEMPT 0 0x1d510 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC6_DUMMY_REG 0 0x1d511 1 0 0 DUMMY 0 31 regSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x1d512 1 0 0 ADDR 0 31 regSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x1d513 1 0 0 ADDR 2 31 regSDMA3_RLC6_RB_AQL_CNTL 0 0x1d514 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC6_MINOR_PTR_UPDATE 0 0x1d515 1 0 0 ENABLE 0 0 regSDMA3_RLC6_MIDCMD_DATA0 0 0x1d520 1 0 0 DATA0 0 31 regSDMA3_RLC6_MIDCMD_DATA1 0 0x1d521 1 0 0 DATA1 0 31 regSDMA3_RLC6_MIDCMD_DATA2 0 0x1d522 1 0 0 DATA2 0 31 regSDMA3_RLC6_MIDCMD_DATA3 0 0x1d523 1 0 0 DATA3 0 31 regSDMA3_RLC6_MIDCMD_DATA4 0 0x1d524 1 0 0 DATA4 0 31 regSDMA3_RLC6_MIDCMD_DATA5 0 0x1d525 1 0 0 DATA5 0 31 regSDMA3_RLC6_MIDCMD_DATA6 0 0x1d526 1 0 0 DATA6 0 31 regSDMA3_RLC6_MIDCMD_DATA7 0 0x1d527 1 0 0 DATA7 0 31 regSDMA3_RLC6_MIDCMD_DATA8 0 0x1d528 1 0 0 DATA8 0 31 regSDMA3_RLC6_MIDCMD_DATA9 0 0x1d529 1 0 0 DATA9 0 31 regSDMA3_RLC6_MIDCMD_DATA10 0 0x1d52a 1 0 0 DATA10 0 31 regSDMA3_RLC6_MIDCMD_CNTL 0 0x1d52b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA3_RLC7_RB_CNTL 0 0x1d538 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA3_RLC7_RB_BASE 0 0x1d539 1 0 0 ADDR 0 31 regSDMA3_RLC7_RB_BASE_HI 0 0x1d53a 1 0 0 ADDR 0 23 regSDMA3_RLC7_RB_RPTR 0 0x1d53b 1 0 0 OFFSET 0 31 regSDMA3_RLC7_RB_RPTR_HI 0 0x1d53c 1 0 0 OFFSET 0 31 regSDMA3_RLC7_RB_WPTR 0 0x1d53d 1 0 0 OFFSET 0 31 regSDMA3_RLC7_RB_WPTR_HI 0 0x1d53e 1 0 0 OFFSET 0 31 regSDMA3_RLC7_RB_WPTR_POLL_CNTL 0 0x1d53f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA3_RLC7_RB_RPTR_ADDR_HI 0 0x1d540 1 0 0 ADDR 0 31 regSDMA3_RLC7_RB_RPTR_ADDR_LO 0 0x1d541 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA3_RLC7_IB_CNTL 0 0x1d542 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA3_RLC7_IB_RPTR 0 0x1d543 1 0 0 OFFSET 2 21 regSDMA3_RLC7_IB_OFFSET 0 0x1d544 1 0 0 OFFSET 2 21 regSDMA3_RLC7_IB_BASE_LO 0 0x1d545 1 0 0 ADDR 5 31 regSDMA3_RLC7_IB_BASE_HI 0 0x1d546 1 0 0 ADDR 0 31 regSDMA3_RLC7_IB_SIZE 0 0x1d547 1 0 0 SIZE 0 19 regSDMA3_RLC7_SKIP_CNTL 0 0x1d548 1 0 0 SKIP_COUNT 0 19 regSDMA3_RLC7_CONTEXT_STATUS 0 0x1d549 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA3_RLC7_DOORBELL 0 0x1d54a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA3_RLC7_STATUS 0 0x1d560 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA3_RLC7_DOORBELL_LOG 0 0x1d561 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA3_RLC7_WATERMARK 0 0x1d562 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA3_RLC7_DOORBELL_OFFSET 0 0x1d563 1 0 0 OFFSET 2 27 regSDMA3_RLC7_CSA_ADDR_LO 0 0x1d564 1 0 0 ADDR 2 31 regSDMA3_RLC7_CSA_ADDR_HI 0 0x1d565 1 0 0 ADDR 0 31 regSDMA3_RLC7_IB_SUB_REMAIN 0 0x1d567 1 0 0 SIZE 0 19 regSDMA3_RLC7_PREEMPT 0 0x1d568 1 0 0 IB_PREEMPT 0 0 regSDMA3_RLC7_DUMMY_REG 0 0x1d569 1 0 0 DUMMY 0 31 regSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x1d56a 1 0 0 ADDR 0 31 regSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x1d56b 1 0 0 ADDR 2 31 regSDMA3_RLC7_RB_AQL_CNTL 0 0x1d56c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA3_RLC7_MINOR_PTR_UPDATE 0 0x1d56d 1 0 0 ENABLE 0 0 regSDMA3_RLC7_MIDCMD_DATA0 0 0x1d578 1 0 0 DATA0 0 31 regSDMA3_RLC7_MIDCMD_DATA1 0 0x1d579 1 0 0 DATA1 0 31 regSDMA3_RLC7_MIDCMD_DATA2 0 0x1d57a 1 0 0 DATA2 0 31 regSDMA3_RLC7_MIDCMD_DATA3 0 0x1d57b 1 0 0 DATA3 0 31 regSDMA3_RLC7_MIDCMD_DATA4 0 0x1d57c 1 0 0 DATA4 0 31 regSDMA3_RLC7_MIDCMD_DATA5 0 0x1d57d 1 0 0 DATA5 0 31 regSDMA3_RLC7_MIDCMD_DATA6 0 0x1d57e 1 0 0 DATA6 0 31 regSDMA3_RLC7_MIDCMD_DATA7 0 0x1d57f 1 0 0 DATA7 0 31 regSDMA3_RLC7_MIDCMD_DATA8 0 0x1d580 1 0 0 DATA8 0 31 regSDMA3_RLC7_MIDCMD_DATA9 0 0x1d581 1 0 0 DATA9 0 31 regSDMA3_RLC7_MIDCMD_DATA10 0 0x1d582 1 0 0 DATA10 0 31 regSDMA3_RLC7_MIDCMD_CNTL 0 0x1d583 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_UCODE_ADDR 0 0x1d5a0 1 0 0 VALUE 0 13 regSDMA4_UCODE_DATA 0 0x1d5a1 1 0 0 VALUE 0 31 regSDMA4_VF_ENABLE 0 0x1d5aa 1 0 0 VF_ENABLE 0 0 regSDMA4_CONTEXT_GROUP_BOUNDARY 0 0x1d5b9 1 0 0 RESERVED 0 31 regSDMA4_POWER_CNTL 0 0x1d5ba 10 0 0 PG_CNTL_ENABLE 0 0 EXT_PG_POWER_ON_REQ 1 1 EXT_PG_POWER_OFF_REQ 2 2 ON_OFF_CONDITION_HOLD_TIME 3 7 MEM_POWER_OVERRIDE 8 8 MEM_POWER_LS_EN 9 9 MEM_POWER_DS_EN 10 10 MEM_POWER_SD_EN 11 11 MEM_POWER_DELAY 12 21 ON_OFF_STATUS_DURATION_TIME 26 31 regSDMA4_CLK_CTRL 0 0x1d5bb 11 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 RESERVED 12 23 SOFT_OVERRIDE7 24 24 SOFT_OVERRIDE6 25 25 SOFT_OVERRIDE5 26 26 SOFT_OVERRIDE4 27 27 SOFT_OVERRIDE3 28 28 SOFT_OVERRIDE2 29 29 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 regSDMA4_CNTL 0 0x1d5bc 12 0 0 TRAP_ENABLE 0 0 UTC_L1_ENABLE 1 1 SEM_WAIT_INT_ENABLE 2 2 DATA_SWAP_ENABLE 3 3 FENCE_SWAP_ENABLE 4 4 MIDCMD_PREEMPT_ENABLE 5 5 MIDCMD_EXPIRE_ENABLE 6 6 MIDCMD_WORLDSWITCH_ENABLE 17 17 AUTO_CTXSW_ENABLE 18 18 CTXEMPTY_INT_ENABLE 28 28 FROZEN_INT_ENABLE 29 29 IB_PREEMPT_INT_ENABLE 30 30 regSDMA4_CHICKEN_BITS 0 0x1d5bd 12 0 0 COPY_EFFICIENCY_ENABLE 0 0 STALL_ON_TRANS_FULL_ENABLE 1 1 STALL_ON_NO_FREE_DATA_BUFFER_ENABLE 2 2 WRITE_BURST_LENGTH 8 9 WRITE_BURST_WAIT_CYCLE 10 12 COPY_OVERLAP_ENABLE 16 16 RAW_CHECK_ENABLE 17 17 SRBM_POLL_RETRYING 20 20 CG_STATUS_OUTPUT 23 23 TIME_BASED_QOS 25 25 SRAM_FGCG_ENABLE 26 26 RESERVED 27 31 regSDMA4_GB_ADDR_CONFIG 0 0x1d5be 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA4_GB_ADDR_CONFIG_READ 0 0x1d5bf 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 regSDMA4_RB_RPTR_FETCH_HI 0 0x1d5c0 1 0 0 OFFSET 0 31 regSDMA4_SEM_WAIT_FAIL_TIMER_CNTL 0 0x1d5c1 1 0 0 TIMER 0 31 regSDMA4_RB_RPTR_FETCH 0 0x1d5c2 1 0 0 OFFSET 2 31 regSDMA4_IB_OFFSET_FETCH 0 0x1d5c3 1 0 0 OFFSET 2 21 regSDMA4_PROGRAM 0 0x1d5c4 1 0 0 STREAM 0 31 regSDMA4_STATUS_REG 0 0x1d5c5 29 0 0 IDLE 0 0 REG_IDLE 1 1 RB_EMPTY 2 2 RB_FULL 3 3 RB_CMD_IDLE 4 4 RB_CMD_FULL 5 5 IB_CMD_IDLE 6 6 IB_CMD_FULL 7 7 BLOCK_IDLE 8 8 INSIDE_IB 9 9 EX_IDLE 10 10 EX_IDLE_POLL_TIMER_EXPIRE 11 11 PACKET_READY 12 12 MC_WR_IDLE 13 13 SRBM_IDLE 14 14 CONTEXT_EMPTY 15 15 DELTA_RPTR_FULL 16 16 RB_MC_RREQ_IDLE 17 17 IB_MC_RREQ_IDLE 18 18 MC_RD_IDLE 19 19 DELTA_RPTR_EMPTY 20 20 MC_RD_RET_STALL 21 21 MC_RD_NO_POLL_IDLE 22 22 PREV_CMD_IDLE 25 25 SEM_IDLE 26 26 SEM_REQ_STALL 27 27 SEM_RESP_STATE 28 29 INT_IDLE 30 30 INT_REQ_STALL 31 31 regSDMA4_STATUS1_REG 0 0x1d5c6 14 0 0 CE_WREQ_IDLE 0 0 CE_WR_IDLE 1 1 CE_SPLIT_IDLE 2 2 CE_RREQ_IDLE 3 3 CE_OUT_IDLE 4 4 CE_IN_IDLE 5 5 CE_DST_IDLE 6 6 CE_CMD_IDLE 9 9 CE_AFIFO_FULL 10 10 CE_INFO_FULL 13 13 CE_INFO1_FULL 14 14 EX_START 15 15 CE_RD_STALL 17 17 CE_WR_STALL 18 18 regSDMA4_RD_BURST_CNTL 0 0x1d5c7 2 0 0 RD_BURST 0 1 CMD_BUFFER_RD_BURST 2 3 regSDMA4_HBM_PAGE_CONFIG 0 0x1d5c8 1 0 0 PAGE_SIZE_EXPONENT 0 1 regSDMA4_UCODE_CHECKSUM 0 0x1d5c9 1 0 0 DATA 0 31 regSDMA4_F32_CNTL 0 0x1d5ca 3 0 0 HALT 0 0 STEP 1 1 RESET 8 8 regSDMA4_FREEZE 0 0x1d5cb 4 0 0 PREEMPT 0 0 FREEZE 4 4 FROZEN 5 5 F32_FREEZE 6 6 regSDMA4_PHASE0_QUANTUM 0 0x1d5cc 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA4_PHASE1_QUANTUM 0 0x1d5cd 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regCC_SDMA4_EDC_CONFIG 0 0x1d5d2 1 0 0 DIS_EDC 1 1 regSDMA4_BA_THRESHOLD 0 0x1d5d3 2 0 0 READ_THRES 0 9 WRITE_THRES 16 25 regSDMA4_ID 0 0x1d5d4 1 0 0 DEVICE_ID 0 7 regSDMA4_VERSION 0 0x1d5d5 3 0 0 MINVER 0 6 MAJVER 8 14 REV 16 21 regSDMA4_EDC_COUNTER 0 0x1d5d6 16 0 0 SDMA_MBANK_DATA_BUF0_SED 0 1 SDMA_MBANK_DATA_BUF1_SED 2 3 SDMA_MBANK_DATA_BUF2_SED 4 5 SDMA_MBANK_DATA_BUF3_SED 6 7 SDMA_MBANK_DATA_BUF4_SED 8 9 SDMA_MBANK_DATA_BUF5_SED 10 11 SDMA_MBANK_DATA_BUF6_SED 12 13 SDMA_MBANK_DATA_BUF7_SED 14 15 SDMA_MBANK_DATA_BUF8_SED 16 17 SDMA_MBANK_DATA_BUF9_SED 18 19 SDMA_MBANK_DATA_BUF10_SED 20 21 SDMA_MBANK_DATA_BUF11_SED 22 23 SDMA_MBANK_DATA_BUF12_SED 24 25 SDMA_MBANK_DATA_BUF13_SED 26 27 SDMA_MBANK_DATA_BUF14_SED 28 29 SDMA_MBANK_DATA_BUF15_SED 30 31 regSDMA4_EDC_COUNTER2 0 0x1d5d7 10 0 0 SDMA_UCODE_BUF_SED 0 1 SDMA_RB_CMD_BUF_SED 2 3 SDMA_IB_CMD_BUF_SED 4 5 SDMA_UTCL1_RD_FIFO_SED 6 7 SDMA_UTCL1_RDBST_FIFO_SED 8 9 SDMA_UTCL1_WR_FIFO_SED 10 11 SDMA_DATA_LUT_FIFO_SED 12 13 SDMA_SPLIT_DATA_BUF_SED 14 15 SDMA_MC_WR_ADDR_FIFO_SED 16 17 SDMA_MC_RDRET_BUF_SED 18 19 regSDMA4_STATUS2_REG 0 0x1d5d8 3 0 0 ID 0 2 F32_INSTR_PTR 3 15 CMD_OP 16 31 regSDMA4_ATOMIC_CNTL 0 0x1d5d9 2 0 0 LOOP_TIMER 0 30 ATOMIC_RTN_INT_ENABLE 31 31 regSDMA4_ATOMIC_PREOP_LO 0 0x1d5da 1 0 0 DATA 0 31 regSDMA4_ATOMIC_PREOP_HI 0 0x1d5db 1 0 0 DATA 0 31 regSDMA4_UTCL1_CNTL 0 0x1d5dc 6 0 0 REDO_ENABLE 0 0 REDO_DELAY 1 10 REDO_WATERMK 11 13 INVACK_DELAY 14 23 REQL2_CREDIT 24 28 VADDR_WATERMK 29 31 regSDMA4_UTCL1_WATERMK 0 0x1d5dd 5 0 0 REQ_WATERMK 0 2 REQ_DEPTH 3 4 PAGE_WATERMK 5 7 INVREQ_WATERMK 8 15 RESERVED 16 31 regSDMA4_UTCL1_RD_STATUS 0 0x1d5de 27 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 CE_L1_STALL 21 21 NEXT_RD_VECTOR 22 25 MERGE_STATE 26 28 ADDR_RD_RTR 29 29 WPTR_POLLING 30 30 INVREQ_SIZE 31 31 regSDMA4_UTCL1_WR_STATUS 0 0x1d5df 28 0 0 RQMC_RET_ADDR_FIFO_EMPTY 0 0 RQMC_REQ_FIFO_EMPTY 1 1 RTPG_RET_BUF_EMPTY 2 2 RTPG_VADDR_FIFO_EMPTY 3 3 RQPG_HEAD_VIRT_FIFO_EMPTY 4 4 RQPG_REDO_FIFO_EMPTY 5 5 RQPG_REQPAGE_FIFO_EMPTY 6 6 RQPG_XNACK_FIFO_EMPTY 7 7 RQPG_INVREQ_FIFO_EMPTY 8 8 RQMC_RET_ADDR_FIFO_FULL 9 9 RQMC_REQ_FIFO_FULL 10 10 RTPG_RET_BUF_FULL 11 11 RTPG_VADDR_FIFO_FULL 12 12 RQPG_HEAD_VIRT_FIFO_FULL 13 13 RQPG_REDO_FIFO_FULL 14 14 RQPG_REQPAGE_FIFO_FULL 15 15 RQPG_XNACK_FIFO_FULL 16 16 RQPG_INVREQ_FIFO_FULL 17 17 PAGE_FAULT 18 18 PAGE_NULL 19 19 REQL2_IDLE 20 20 F32_WR_RTR 21 21 NEXT_WR_VECTOR 22 24 MERGE_STATE 25 27 RPTR_DATA_FIFO_EMPTY 28 28 RPTR_DATA_FIFO_FULL 29 29 WRREQ_DATA_FIFO_EMPTY 30 30 WRREQ_DATA_FIFO_FULL 31 31 regSDMA4_UTCL1_INV0 0 0x1d5e0 14 0 0 INV_MIDDLE 0 0 RD_TIMEOUT 1 1 WR_TIMEOUT 2 2 RD_IN_INVADR 3 3 WR_IN_INVADR 4 4 PAGE_NULL_SW 5 5 XNACK_IS_INVADR 6 6 INVREQ_ENABLE 7 7 NACK_TIMEOUT_SW 8 8 NFLUSH_INV_IDLE 9 9 FLUSH_INV_IDLE 10 10 INV_FLUSHTYPE 11 11 INV_VMID_VEC 12 27 INV_ADDR_HI 28 31 regSDMA4_UTCL1_INV1 0 0x1d5e1 1 0 0 INV_ADDR_LO 0 31 regSDMA4_UTCL1_INV2 0 0x1d5e2 1 0 0 INV_NFLUSH_VMID_VEC 0 31 regSDMA4_UTCL1_RD_XNACK0 0 0x1d5e3 1 0 0 XNACK_ADDR_LO 0 31 regSDMA4_UTCL1_RD_XNACK1 0 0x1d5e4 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA4_UTCL1_WR_XNACK0 0 0x1d5e5 1 0 0 XNACK_ADDR_LO 0 31 regSDMA4_UTCL1_WR_XNACK1 0 0x1d5e6 4 0 0 XNACK_ADDR_HI 0 3 XNACK_VMID 4 7 XNACK_VECTOR 8 25 IS_XNACK 26 27 regSDMA4_UTCL1_TIMEOUT 0 0x1d5e7 2 0 0 RD_XNACK_LIMIT 0 15 WR_XNACK_LIMIT 16 31 regSDMA4_UTCL1_PAGE 0 0x1d5e8 4 0 0 VM_HOLE 0 0 REQ_TYPE 1 4 USE_MTYPE 6 8 USE_PT_SNOOP 9 9 regSDMA4_POWER_CNTL_IDLE 0 0x1d5e9 3 0 0 DELAY0 0 15 DELAY1 16 23 DELAY2 24 31 regSDMA4_RELAX_ORDERING_LUT 0 0x1d5ea 19 0 0 RESERVED0 0 0 COPY 1 1 WRITE 2 2 RESERVED3 3 3 RESERVED4 4 4 FENCE 5 5 RESERVED76 6 7 POLL_MEM 8 8 COND_EXE 9 9 ATOMIC 10 10 CONST_FILL 11 11 PTEPDE 12 12 TIMESTAMP 13 13 RESERVED 14 26 WORLD_SWITCH 27 27 RPTR_WRB 28 28 WPTR_POLL 29 29 IB_FETCH 30 30 RB_FETCH 31 31 regSDMA4_CHICKEN_BITS_2 0 0x1d5eb 2 0 0 F32_CMD_PROC_DELAY 0 3 F32_SEND_POSTCODE_EN 4 4 regSDMA4_STATUS3_REG 0 0x1d5ec 5 0 0 CMD_OP_STATUS 0 15 PREV_VM_CMD 16 19 EXCEPTION_IDLE 20 20 QUEUE_ID_MATCH 21 21 INT_QUEUE_ID 22 25 regSDMA4_PHYSICAL_ADDR_LO 0 0x1d5ed 4 0 0 D_VALID 0 0 DIRTY 1 1 PHY_VALID 2 2 ADDR 12 31 regSDMA4_PHYSICAL_ADDR_HI 0 0x1d5ee 1 0 0 ADDR 0 15 regSDMA4_PHASE2_QUANTUM 0 0x1d5ef 3 0 0 UNIT 0 3 VALUE 8 23 PREFER 30 30 regSDMA4_ERROR_LOG 0 0x1d5f0 2 0 0 OVERRIDE 0 15 STATUS 16 31 regSDMA4_PUB_DUMMY_REG0 0 0x1d5f1 1 0 0 VALUE 0 31 regSDMA4_PUB_DUMMY_REG1 0 0x1d5f2 1 0 0 VALUE 0 31 regSDMA4_PUB_DUMMY_REG2 0 0x1d5f3 1 0 0 VALUE 0 31 regSDMA4_PUB_DUMMY_REG3 0 0x1d5f4 1 0 0 VALUE 0 31 regSDMA4_F32_COUNTER 0 0x1d5f5 1 0 0 VALUE 0 31 regSDMA4_PERFCNT_PERFCOUNTER0_CFG 0 0x1d5f7 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA4_PERFCNT_PERFCOUNTER1_CFG 0 0x1d5f8 5 0 0 PERF_SEL 0 7 PERF_SEL_END 8 15 PERF_MODE 24 27 ENABLE 28 28 CLEAR 29 29 regSDMA4_PERFCNT_PERFCOUNTER_RSLT_CNTL 0 0x1d5f9 6 0 0 PERF_COUNTER_SELECT 0 3 START_TRIGGER 8 15 STOP_TRIGGER 16 23 ENABLE_ANY 24 24 CLEAR_ALL 25 25 STOP_ALL_ON_SATURATE 26 26 regSDMA4_PERFCNT_MISC_CNTL 0 0x1d5fa 1 0 0 CMD_OP 0 15 regSDMA4_PERFCNT_PERFCOUNTER_LO 0 0x1d5fb 1 0 0 COUNTER_LO 0 31 regSDMA4_PERFCNT_PERFCOUNTER_HI 0 0x1d5fc 2 0 0 COUNTER_HI 0 15 COMPARE_VALUE 16 31 regSDMA4_CRD_CNTL 0 0x1d5fd 2 0 0 MC_WRREQ_CREDIT 7 12 MC_RDREQ_CREDIT 13 18 regSDMA4_ULV_CNTL 0 0x1d5ff 6 0 0 HYSTERESIS 0 4 ENTER_ULV_INT_CLR 27 27 EXIT_ULV_INT_CLR 28 28 ENTER_ULV_INT 29 29 EXIT_ULV_INT 30 30 ULV_STATUS 31 31 regSDMA4_EA_DBIT_ADDR_DATA 0 0x1d600 1 0 0 VALUE 0 31 regSDMA4_EA_DBIT_ADDR_INDEX 0 0x1d601 1 0 0 VALUE 0 2 regSDMA4_STATUS4_REG 0 0x1d603 14 0 0 IDLE 0 0 IH_OUTSTANDING 2 2 SEM_OUTSTANDING 3 3 MMHUB_RD_OUTSTANDING 4 4 MMHUB_WR_OUTSTANDING 5 5 UTCL2_RD_OUTSTANDING 6 6 UTCL2_WR_OUTSTANDING 7 7 REG_POLLING 8 8 MEM_POLLING 9 9 UTCL2_RD_XNACK 10 11 UTCL2_WR_XNACK 12 13 ACTIVE_QUEUE_ID 14 17 SRIOV_WATING_RLCV_CMD 18 18 SRIOV_SDMA_EXECUTING_CMD 19 19 regSDMA4_SCRATCH_RAM_DATA 0 0x1d604 1 0 0 DATA 0 31 regSDMA4_SCRATCH_RAM_ADDR 0 0x1d605 1 0 0 ADDR 0 6 regSDMA4_CE_CTRL 0 0x1d606 4 0 0 RD_LUT_WATERMARK 0 2 RD_LUT_DEPTH 3 4 WR_AFIFO_WATERMARK 5 7 RESERVED 8 31 regSDMA4_RAS_STATUS 0 0x1d607 12 0 0 RB_FETCH_ECC 0 0 IB_FETCH_ECC 1 1 F32_DATA_ECC 2 2 SEM_WPTR_ATOMIC_ECC 3 3 COPY_DATA_ECC 4 4 SRAM_ECC 5 5 RB_FETCH_NACK_GEN_ERR 8 8 IB_FETCH_NACK_GEN_ERR 9 9 F32_DATA_NACK_GEN_ERR 10 10 COPY_DATA_NACK_GEN_ERR 11 11 WRRET_DATA_NACK_GEN_ERR 12 12 WPTR_RPTR_ATOMIC_NACK_GEN_ERR 13 13 regSDMA4_CLK_STATUS 0 0x1d608 4 0 0 DYN_CLK 0 0 PTR_CLK 1 1 REG_CLK 2 2 F32_CLK 3 3 regSDMA4_GFX_RB_CNTL 0 0x1d620 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_GFX_RB_BASE 0 0x1d621 1 0 0 ADDR 0 31 regSDMA4_GFX_RB_BASE_HI 0 0x1d622 1 0 0 ADDR 0 23 regSDMA4_GFX_RB_RPTR 0 0x1d623 1 0 0 OFFSET 0 31 regSDMA4_GFX_RB_RPTR_HI 0 0x1d624 1 0 0 OFFSET 0 31 regSDMA4_GFX_RB_WPTR 0 0x1d625 1 0 0 OFFSET 0 31 regSDMA4_GFX_RB_WPTR_HI 0 0x1d626 1 0 0 OFFSET 0 31 regSDMA4_GFX_RB_WPTR_POLL_CNTL 0 0x1d627 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_GFX_RB_RPTR_ADDR_HI 0 0x1d628 1 0 0 ADDR 0 31 regSDMA4_GFX_RB_RPTR_ADDR_LO 0 0x1d629 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_GFX_IB_CNTL 0 0x1d62a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_GFX_IB_RPTR 0 0x1d62b 1 0 0 OFFSET 2 21 regSDMA4_GFX_IB_OFFSET 0 0x1d62c 1 0 0 OFFSET 2 21 regSDMA4_GFX_IB_BASE_LO 0 0x1d62d 1 0 0 ADDR 5 31 regSDMA4_GFX_IB_BASE_HI 0 0x1d62e 1 0 0 ADDR 0 31 regSDMA4_GFX_IB_SIZE 0 0x1d62f 1 0 0 SIZE 0 19 regSDMA4_GFX_SKIP_CNTL 0 0x1d630 1 0 0 SKIP_COUNT 0 19 regSDMA4_GFX_CONTEXT_STATUS 0 0x1d631 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_GFX_DOORBELL 0 0x1d632 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_GFX_CONTEXT_CNTL 0 0x1d633 2 0 0 RESUME_CTX 16 16 SESSION_SEL 24 27 regSDMA4_GFX_STATUS 0 0x1d648 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_GFX_DOORBELL_LOG 0 0x1d649 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_GFX_WATERMARK 0 0x1d64a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_GFX_DOORBELL_OFFSET 0 0x1d64b 1 0 0 OFFSET 2 27 regSDMA4_GFX_CSA_ADDR_LO 0 0x1d64c 1 0 0 ADDR 2 31 regSDMA4_GFX_CSA_ADDR_HI 0 0x1d64d 1 0 0 ADDR 0 31 regSDMA4_GFX_IB_SUB_REMAIN 0 0x1d64f 1 0 0 SIZE 0 19 regSDMA4_GFX_PREEMPT 0 0x1d650 1 0 0 IB_PREEMPT 0 0 regSDMA4_GFX_DUMMY_REG 0 0x1d651 1 0 0 DUMMY 0 31 regSDMA4_GFX_RB_WPTR_POLL_ADDR_HI 0 0x1d652 1 0 0 ADDR 0 31 regSDMA4_GFX_RB_WPTR_POLL_ADDR_LO 0 0x1d653 1 0 0 ADDR 2 31 regSDMA4_GFX_RB_AQL_CNTL 0 0x1d654 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_GFX_MINOR_PTR_UPDATE 0 0x1d655 1 0 0 ENABLE 0 0 regSDMA4_GFX_MIDCMD_DATA0 0 0x1d660 1 0 0 DATA0 0 31 regSDMA4_GFX_MIDCMD_DATA1 0 0x1d661 1 0 0 DATA1 0 31 regSDMA4_GFX_MIDCMD_DATA2 0 0x1d662 1 0 0 DATA2 0 31 regSDMA4_GFX_MIDCMD_DATA3 0 0x1d663 1 0 0 DATA3 0 31 regSDMA4_GFX_MIDCMD_DATA4 0 0x1d664 1 0 0 DATA4 0 31 regSDMA4_GFX_MIDCMD_DATA5 0 0x1d665 1 0 0 DATA5 0 31 regSDMA4_GFX_MIDCMD_DATA6 0 0x1d666 1 0 0 DATA6 0 31 regSDMA4_GFX_MIDCMD_DATA7 0 0x1d667 1 0 0 DATA7 0 31 regSDMA4_GFX_MIDCMD_DATA8 0 0x1d668 1 0 0 DATA8 0 31 regSDMA4_GFX_MIDCMD_DATA9 0 0x1d669 1 0 0 DATA9 0 31 regSDMA4_GFX_MIDCMD_DATA10 0 0x1d66a 1 0 0 DATA10 0 31 regSDMA4_GFX_MIDCMD_CNTL 0 0x1d66b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_PAGE_RB_CNTL 0 0x1d678 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_PAGE_RB_BASE 0 0x1d679 1 0 0 ADDR 0 31 regSDMA4_PAGE_RB_BASE_HI 0 0x1d67a 1 0 0 ADDR 0 23 regSDMA4_PAGE_RB_RPTR 0 0x1d67b 1 0 0 OFFSET 0 31 regSDMA4_PAGE_RB_RPTR_HI 0 0x1d67c 1 0 0 OFFSET 0 31 regSDMA4_PAGE_RB_WPTR 0 0x1d67d 1 0 0 OFFSET 0 31 regSDMA4_PAGE_RB_WPTR_HI 0 0x1d67e 1 0 0 OFFSET 0 31 regSDMA4_PAGE_RB_WPTR_POLL_CNTL 0 0x1d67f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_PAGE_RB_RPTR_ADDR_HI 0 0x1d680 1 0 0 ADDR 0 31 regSDMA4_PAGE_RB_RPTR_ADDR_LO 0 0x1d681 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_PAGE_IB_CNTL 0 0x1d682 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_PAGE_IB_RPTR 0 0x1d683 1 0 0 OFFSET 2 21 regSDMA4_PAGE_IB_OFFSET 0 0x1d684 1 0 0 OFFSET 2 21 regSDMA4_PAGE_IB_BASE_LO 0 0x1d685 1 0 0 ADDR 5 31 regSDMA4_PAGE_IB_BASE_HI 0 0x1d686 1 0 0 ADDR 0 31 regSDMA4_PAGE_IB_SIZE 0 0x1d687 1 0 0 SIZE 0 19 regSDMA4_PAGE_SKIP_CNTL 0 0x1d688 1 0 0 SKIP_COUNT 0 19 regSDMA4_PAGE_CONTEXT_STATUS 0 0x1d689 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_PAGE_DOORBELL 0 0x1d68a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_PAGE_STATUS 0 0x1d6a0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_PAGE_DOORBELL_LOG 0 0x1d6a1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_PAGE_WATERMARK 0 0x1d6a2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_PAGE_DOORBELL_OFFSET 0 0x1d6a3 1 0 0 OFFSET 2 27 regSDMA4_PAGE_CSA_ADDR_LO 0 0x1d6a4 1 0 0 ADDR 2 31 regSDMA4_PAGE_CSA_ADDR_HI 0 0x1d6a5 1 0 0 ADDR 0 31 regSDMA4_PAGE_IB_SUB_REMAIN 0 0x1d6a7 1 0 0 SIZE 0 19 regSDMA4_PAGE_PREEMPT 0 0x1d6a8 1 0 0 IB_PREEMPT 0 0 regSDMA4_PAGE_DUMMY_REG 0 0x1d6a9 1 0 0 DUMMY 0 31 regSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI 0 0x1d6aa 1 0 0 ADDR 0 31 regSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO 0 0x1d6ab 1 0 0 ADDR 2 31 regSDMA4_PAGE_RB_AQL_CNTL 0 0x1d6ac 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_PAGE_MINOR_PTR_UPDATE 0 0x1d6ad 1 0 0 ENABLE 0 0 regSDMA4_PAGE_MIDCMD_DATA0 0 0x1d6b8 1 0 0 DATA0 0 31 regSDMA4_PAGE_MIDCMD_DATA1 0 0x1d6b9 1 0 0 DATA1 0 31 regSDMA4_PAGE_MIDCMD_DATA2 0 0x1d6ba 1 0 0 DATA2 0 31 regSDMA4_PAGE_MIDCMD_DATA3 0 0x1d6bb 1 0 0 DATA3 0 31 regSDMA4_PAGE_MIDCMD_DATA4 0 0x1d6bc 1 0 0 DATA4 0 31 regSDMA4_PAGE_MIDCMD_DATA5 0 0x1d6bd 1 0 0 DATA5 0 31 regSDMA4_PAGE_MIDCMD_DATA6 0 0x1d6be 1 0 0 DATA6 0 31 regSDMA4_PAGE_MIDCMD_DATA7 0 0x1d6bf 1 0 0 DATA7 0 31 regSDMA4_PAGE_MIDCMD_DATA8 0 0x1d6c0 1 0 0 DATA8 0 31 regSDMA4_PAGE_MIDCMD_DATA9 0 0x1d6c1 1 0 0 DATA9 0 31 regSDMA4_PAGE_MIDCMD_DATA10 0 0x1d6c2 1 0 0 DATA10 0 31 regSDMA4_PAGE_MIDCMD_CNTL 0 0x1d6c3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC0_RB_CNTL 0 0x1d6d0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC0_RB_BASE 0 0x1d6d1 1 0 0 ADDR 0 31 regSDMA4_RLC0_RB_BASE_HI 0 0x1d6d2 1 0 0 ADDR 0 23 regSDMA4_RLC0_RB_RPTR 0 0x1d6d3 1 0 0 OFFSET 0 31 regSDMA4_RLC0_RB_RPTR_HI 0 0x1d6d4 1 0 0 OFFSET 0 31 regSDMA4_RLC0_RB_WPTR 0 0x1d6d5 1 0 0 OFFSET 0 31 regSDMA4_RLC0_RB_WPTR_HI 0 0x1d6d6 1 0 0 OFFSET 0 31 regSDMA4_RLC0_RB_WPTR_POLL_CNTL 0 0x1d6d7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC0_RB_RPTR_ADDR_HI 0 0x1d6d8 1 0 0 ADDR 0 31 regSDMA4_RLC0_RB_RPTR_ADDR_LO 0 0x1d6d9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC0_IB_CNTL 0 0x1d6da 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC0_IB_RPTR 0 0x1d6db 1 0 0 OFFSET 2 21 regSDMA4_RLC0_IB_OFFSET 0 0x1d6dc 1 0 0 OFFSET 2 21 regSDMA4_RLC0_IB_BASE_LO 0 0x1d6dd 1 0 0 ADDR 5 31 regSDMA4_RLC0_IB_BASE_HI 0 0x1d6de 1 0 0 ADDR 0 31 regSDMA4_RLC0_IB_SIZE 0 0x1d6df 1 0 0 SIZE 0 19 regSDMA4_RLC0_SKIP_CNTL 0 0x1d6e0 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC0_CONTEXT_STATUS 0 0x1d6e1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC0_DOORBELL 0 0x1d6e2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC0_STATUS 0 0x1d6f8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC0_DOORBELL_LOG 0 0x1d6f9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC0_WATERMARK 0 0x1d6fa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC0_DOORBELL_OFFSET 0 0x1d6fb 1 0 0 OFFSET 2 27 regSDMA4_RLC0_CSA_ADDR_LO 0 0x1d6fc 1 0 0 ADDR 2 31 regSDMA4_RLC0_CSA_ADDR_HI 0 0x1d6fd 1 0 0 ADDR 0 31 regSDMA4_RLC0_IB_SUB_REMAIN 0 0x1d6ff 1 0 0 SIZE 0 19 regSDMA4_RLC0_PREEMPT 0 0x1d700 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC0_DUMMY_REG 0 0x1d701 1 0 0 DUMMY 0 31 regSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI 0 0x1d702 1 0 0 ADDR 0 31 regSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO 0 0x1d703 1 0 0 ADDR 2 31 regSDMA4_RLC0_RB_AQL_CNTL 0 0x1d704 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC0_MINOR_PTR_UPDATE 0 0x1d705 1 0 0 ENABLE 0 0 regSDMA4_RLC0_MIDCMD_DATA0 0 0x1d710 1 0 0 DATA0 0 31 regSDMA4_RLC0_MIDCMD_DATA1 0 0x1d711 1 0 0 DATA1 0 31 regSDMA4_RLC0_MIDCMD_DATA2 0 0x1d712 1 0 0 DATA2 0 31 regSDMA4_RLC0_MIDCMD_DATA3 0 0x1d713 1 0 0 DATA3 0 31 regSDMA4_RLC0_MIDCMD_DATA4 0 0x1d714 1 0 0 DATA4 0 31 regSDMA4_RLC0_MIDCMD_DATA5 0 0x1d715 1 0 0 DATA5 0 31 regSDMA4_RLC0_MIDCMD_DATA6 0 0x1d716 1 0 0 DATA6 0 31 regSDMA4_RLC0_MIDCMD_DATA7 0 0x1d717 1 0 0 DATA7 0 31 regSDMA4_RLC0_MIDCMD_DATA8 0 0x1d718 1 0 0 DATA8 0 31 regSDMA4_RLC0_MIDCMD_DATA9 0 0x1d719 1 0 0 DATA9 0 31 regSDMA4_RLC0_MIDCMD_DATA10 0 0x1d71a 1 0 0 DATA10 0 31 regSDMA4_RLC0_MIDCMD_CNTL 0 0x1d71b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC1_RB_CNTL 0 0x1d728 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC1_RB_BASE 0 0x1d729 1 0 0 ADDR 0 31 regSDMA4_RLC1_RB_BASE_HI 0 0x1d72a 1 0 0 ADDR 0 23 regSDMA4_RLC1_RB_RPTR 0 0x1d72b 1 0 0 OFFSET 0 31 regSDMA4_RLC1_RB_RPTR_HI 0 0x1d72c 1 0 0 OFFSET 0 31 regSDMA4_RLC1_RB_WPTR 0 0x1d72d 1 0 0 OFFSET 0 31 regSDMA4_RLC1_RB_WPTR_HI 0 0x1d72e 1 0 0 OFFSET 0 31 regSDMA4_RLC1_RB_WPTR_POLL_CNTL 0 0x1d72f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC1_RB_RPTR_ADDR_HI 0 0x1d730 1 0 0 ADDR 0 31 regSDMA4_RLC1_RB_RPTR_ADDR_LO 0 0x1d731 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC1_IB_CNTL 0 0x1d732 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC1_IB_RPTR 0 0x1d733 1 0 0 OFFSET 2 21 regSDMA4_RLC1_IB_OFFSET 0 0x1d734 1 0 0 OFFSET 2 21 regSDMA4_RLC1_IB_BASE_LO 0 0x1d735 1 0 0 ADDR 5 31 regSDMA4_RLC1_IB_BASE_HI 0 0x1d736 1 0 0 ADDR 0 31 regSDMA4_RLC1_IB_SIZE 0 0x1d737 1 0 0 SIZE 0 19 regSDMA4_RLC1_SKIP_CNTL 0 0x1d738 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC1_CONTEXT_STATUS 0 0x1d739 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC1_DOORBELL 0 0x1d73a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC1_STATUS 0 0x1d750 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC1_DOORBELL_LOG 0 0x1d751 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC1_WATERMARK 0 0x1d752 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC1_DOORBELL_OFFSET 0 0x1d753 1 0 0 OFFSET 2 27 regSDMA4_RLC1_CSA_ADDR_LO 0 0x1d754 1 0 0 ADDR 2 31 regSDMA4_RLC1_CSA_ADDR_HI 0 0x1d755 1 0 0 ADDR 0 31 regSDMA4_RLC1_IB_SUB_REMAIN 0 0x1d757 1 0 0 SIZE 0 19 regSDMA4_RLC1_PREEMPT 0 0x1d758 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC1_DUMMY_REG 0 0x1d759 1 0 0 DUMMY 0 31 regSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI 0 0x1d75a 1 0 0 ADDR 0 31 regSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO 0 0x1d75b 1 0 0 ADDR 2 31 regSDMA4_RLC1_RB_AQL_CNTL 0 0x1d75c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC1_MINOR_PTR_UPDATE 0 0x1d75d 1 0 0 ENABLE 0 0 regSDMA4_RLC1_MIDCMD_DATA0 0 0x1d768 1 0 0 DATA0 0 31 regSDMA4_RLC1_MIDCMD_DATA1 0 0x1d769 1 0 0 DATA1 0 31 regSDMA4_RLC1_MIDCMD_DATA2 0 0x1d76a 1 0 0 DATA2 0 31 regSDMA4_RLC1_MIDCMD_DATA3 0 0x1d76b 1 0 0 DATA3 0 31 regSDMA4_RLC1_MIDCMD_DATA4 0 0x1d76c 1 0 0 DATA4 0 31 regSDMA4_RLC1_MIDCMD_DATA5 0 0x1d76d 1 0 0 DATA5 0 31 regSDMA4_RLC1_MIDCMD_DATA6 0 0x1d76e 1 0 0 DATA6 0 31 regSDMA4_RLC1_MIDCMD_DATA7 0 0x1d76f 1 0 0 DATA7 0 31 regSDMA4_RLC1_MIDCMD_DATA8 0 0x1d770 1 0 0 DATA8 0 31 regSDMA4_RLC1_MIDCMD_DATA9 0 0x1d771 1 0 0 DATA9 0 31 regSDMA4_RLC1_MIDCMD_DATA10 0 0x1d772 1 0 0 DATA10 0 31 regSDMA4_RLC1_MIDCMD_CNTL 0 0x1d773 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC2_RB_CNTL 0 0x1d780 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC2_RB_BASE 0 0x1d781 1 0 0 ADDR 0 31 regSDMA4_RLC2_RB_BASE_HI 0 0x1d782 1 0 0 ADDR 0 23 regSDMA4_RLC2_RB_RPTR 0 0x1d783 1 0 0 OFFSET 0 31 regSDMA4_RLC2_RB_RPTR_HI 0 0x1d784 1 0 0 OFFSET 0 31 regSDMA4_RLC2_RB_WPTR 0 0x1d785 1 0 0 OFFSET 0 31 regSDMA4_RLC2_RB_WPTR_HI 0 0x1d786 1 0 0 OFFSET 0 31 regSDMA4_RLC2_RB_WPTR_POLL_CNTL 0 0x1d787 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC2_RB_RPTR_ADDR_HI 0 0x1d788 1 0 0 ADDR 0 31 regSDMA4_RLC2_RB_RPTR_ADDR_LO 0 0x1d789 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC2_IB_CNTL 0 0x1d78a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC2_IB_RPTR 0 0x1d78b 1 0 0 OFFSET 2 21 regSDMA4_RLC2_IB_OFFSET 0 0x1d78c 1 0 0 OFFSET 2 21 regSDMA4_RLC2_IB_BASE_LO 0 0x1d78d 1 0 0 ADDR 5 31 regSDMA4_RLC2_IB_BASE_HI 0 0x1d78e 1 0 0 ADDR 0 31 regSDMA4_RLC2_IB_SIZE 0 0x1d78f 1 0 0 SIZE 0 19 regSDMA4_RLC2_SKIP_CNTL 0 0x1d790 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC2_CONTEXT_STATUS 0 0x1d791 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC2_DOORBELL 0 0x1d792 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC2_STATUS 0 0x1d7a8 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC2_DOORBELL_LOG 0 0x1d7a9 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC2_WATERMARK 0 0x1d7aa 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC2_DOORBELL_OFFSET 0 0x1d7ab 1 0 0 OFFSET 2 27 regSDMA4_RLC2_CSA_ADDR_LO 0 0x1d7ac 1 0 0 ADDR 2 31 regSDMA4_RLC2_CSA_ADDR_HI 0 0x1d7ad 1 0 0 ADDR 0 31 regSDMA4_RLC2_IB_SUB_REMAIN 0 0x1d7af 1 0 0 SIZE 0 19 regSDMA4_RLC2_PREEMPT 0 0x1d7b0 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC2_DUMMY_REG 0 0x1d7b1 1 0 0 DUMMY 0 31 regSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI 0 0x1d7b2 1 0 0 ADDR 0 31 regSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO 0 0x1d7b3 1 0 0 ADDR 2 31 regSDMA4_RLC2_RB_AQL_CNTL 0 0x1d7b4 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC2_MINOR_PTR_UPDATE 0 0x1d7b5 1 0 0 ENABLE 0 0 regSDMA4_RLC2_MIDCMD_DATA0 0 0x1d7c0 1 0 0 DATA0 0 31 regSDMA4_RLC2_MIDCMD_DATA1 0 0x1d7c1 1 0 0 DATA1 0 31 regSDMA4_RLC2_MIDCMD_DATA2 0 0x1d7c2 1 0 0 DATA2 0 31 regSDMA4_RLC2_MIDCMD_DATA3 0 0x1d7c3 1 0 0 DATA3 0 31 regSDMA4_RLC2_MIDCMD_DATA4 0 0x1d7c4 1 0 0 DATA4 0 31 regSDMA4_RLC2_MIDCMD_DATA5 0 0x1d7c5 1 0 0 DATA5 0 31 regSDMA4_RLC2_MIDCMD_DATA6 0 0x1d7c6 1 0 0 DATA6 0 31 regSDMA4_RLC2_MIDCMD_DATA7 0 0x1d7c7 1 0 0 DATA7 0 31 regSDMA4_RLC2_MIDCMD_DATA8 0 0x1d7c8 1 0 0 DATA8 0 31 regSDMA4_RLC2_MIDCMD_DATA9 0 0x1d7c9 1 0 0 DATA9 0 31 regSDMA4_RLC2_MIDCMD_DATA10 0 0x1d7ca 1 0 0 DATA10 0 31 regSDMA4_RLC2_MIDCMD_CNTL 0 0x1d7cb 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC3_RB_CNTL 0 0x1d7d8 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC3_RB_BASE 0 0x1d7d9 1 0 0 ADDR 0 31 regSDMA4_RLC3_RB_BASE_HI 0 0x1d7da 1 0 0 ADDR 0 23 regSDMA4_RLC3_RB_RPTR 0 0x1d7db 1 0 0 OFFSET 0 31 regSDMA4_RLC3_RB_RPTR_HI 0 0x1d7dc 1 0 0 OFFSET 0 31 regSDMA4_RLC3_RB_WPTR 0 0x1d7dd 1 0 0 OFFSET 0 31 regSDMA4_RLC3_RB_WPTR_HI 0 0x1d7de 1 0 0 OFFSET 0 31 regSDMA4_RLC3_RB_WPTR_POLL_CNTL 0 0x1d7df 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC3_RB_RPTR_ADDR_HI 0 0x1d7e0 1 0 0 ADDR 0 31 regSDMA4_RLC3_RB_RPTR_ADDR_LO 0 0x1d7e1 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC3_IB_CNTL 0 0x1d7e2 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC3_IB_RPTR 0 0x1d7e3 1 0 0 OFFSET 2 21 regSDMA4_RLC3_IB_OFFSET 0 0x1d7e4 1 0 0 OFFSET 2 21 regSDMA4_RLC3_IB_BASE_LO 0 0x1d7e5 1 0 0 ADDR 5 31 regSDMA4_RLC3_IB_BASE_HI 0 0x1d7e6 1 0 0 ADDR 0 31 regSDMA4_RLC3_IB_SIZE 0 0x1d7e7 1 0 0 SIZE 0 19 regSDMA4_RLC3_SKIP_CNTL 0 0x1d7e8 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC3_CONTEXT_STATUS 0 0x1d7e9 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC3_DOORBELL 0 0x1d7ea 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC3_STATUS 0 0x1d800 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC3_DOORBELL_LOG 0 0x1d801 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC3_WATERMARK 0 0x1d802 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC3_DOORBELL_OFFSET 0 0x1d803 1 0 0 OFFSET 2 27 regSDMA4_RLC3_CSA_ADDR_LO 0 0x1d804 1 0 0 ADDR 2 31 regSDMA4_RLC3_CSA_ADDR_HI 0 0x1d805 1 0 0 ADDR 0 31 regSDMA4_RLC3_IB_SUB_REMAIN 0 0x1d807 1 0 0 SIZE 0 19 regSDMA4_RLC3_PREEMPT 0 0x1d808 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC3_DUMMY_REG 0 0x1d809 1 0 0 DUMMY 0 31 regSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI 0 0x1d80a 1 0 0 ADDR 0 31 regSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO 0 0x1d80b 1 0 0 ADDR 2 31 regSDMA4_RLC3_RB_AQL_CNTL 0 0x1d80c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC3_MINOR_PTR_UPDATE 0 0x1d80d 1 0 0 ENABLE 0 0 regSDMA4_RLC3_MIDCMD_DATA0 0 0x1d818 1 0 0 DATA0 0 31 regSDMA4_RLC3_MIDCMD_DATA1 0 0x1d819 1 0 0 DATA1 0 31 regSDMA4_RLC3_MIDCMD_DATA2 0 0x1d81a 1 0 0 DATA2 0 31 regSDMA4_RLC3_MIDCMD_DATA3 0 0x1d81b 1 0 0 DATA3 0 31 regSDMA4_RLC3_MIDCMD_DATA4 0 0x1d81c 1 0 0 DATA4 0 31 regSDMA4_RLC3_MIDCMD_DATA5 0 0x1d81d 1 0 0 DATA5 0 31 regSDMA4_RLC3_MIDCMD_DATA6 0 0x1d81e 1 0 0 DATA6 0 31 regSDMA4_RLC3_MIDCMD_DATA7 0 0x1d81f 1 0 0 DATA7 0 31 regSDMA4_RLC3_MIDCMD_DATA8 0 0x1d820 1 0 0 DATA8 0 31 regSDMA4_RLC3_MIDCMD_DATA9 0 0x1d821 1 0 0 DATA9 0 31 regSDMA4_RLC3_MIDCMD_DATA10 0 0x1d822 1 0 0 DATA10 0 31 regSDMA4_RLC3_MIDCMD_CNTL 0 0x1d823 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC4_RB_CNTL 0 0x1d830 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC4_RB_BASE 0 0x1d831 1 0 0 ADDR 0 31 regSDMA4_RLC4_RB_BASE_HI 0 0x1d832 1 0 0 ADDR 0 23 regSDMA4_RLC4_RB_RPTR 0 0x1d833 1 0 0 OFFSET 0 31 regSDMA4_RLC4_RB_RPTR_HI 0 0x1d834 1 0 0 OFFSET 0 31 regSDMA4_RLC4_RB_WPTR 0 0x1d835 1 0 0 OFFSET 0 31 regSDMA4_RLC4_RB_WPTR_HI 0 0x1d836 1 0 0 OFFSET 0 31 regSDMA4_RLC4_RB_WPTR_POLL_CNTL 0 0x1d837 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC4_RB_RPTR_ADDR_HI 0 0x1d838 1 0 0 ADDR 0 31 regSDMA4_RLC4_RB_RPTR_ADDR_LO 0 0x1d839 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC4_IB_CNTL 0 0x1d83a 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC4_IB_RPTR 0 0x1d83b 1 0 0 OFFSET 2 21 regSDMA4_RLC4_IB_OFFSET 0 0x1d83c 1 0 0 OFFSET 2 21 regSDMA4_RLC4_IB_BASE_LO 0 0x1d83d 1 0 0 ADDR 5 31 regSDMA4_RLC4_IB_BASE_HI 0 0x1d83e 1 0 0 ADDR 0 31 regSDMA4_RLC4_IB_SIZE 0 0x1d83f 1 0 0 SIZE 0 19 regSDMA4_RLC4_SKIP_CNTL 0 0x1d840 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC4_CONTEXT_STATUS 0 0x1d841 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC4_DOORBELL 0 0x1d842 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC4_STATUS 0 0x1d858 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC4_DOORBELL_LOG 0 0x1d859 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC4_WATERMARK 0 0x1d85a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC4_DOORBELL_OFFSET 0 0x1d85b 1 0 0 OFFSET 2 27 regSDMA4_RLC4_CSA_ADDR_LO 0 0x1d85c 1 0 0 ADDR 2 31 regSDMA4_RLC4_CSA_ADDR_HI 0 0x1d85d 1 0 0 ADDR 0 31 regSDMA4_RLC4_IB_SUB_REMAIN 0 0x1d85f 1 0 0 SIZE 0 19 regSDMA4_RLC4_PREEMPT 0 0x1d860 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC4_DUMMY_REG 0 0x1d861 1 0 0 DUMMY 0 31 regSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI 0 0x1d862 1 0 0 ADDR 0 31 regSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO 0 0x1d863 1 0 0 ADDR 2 31 regSDMA4_RLC4_RB_AQL_CNTL 0 0x1d864 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC4_MINOR_PTR_UPDATE 0 0x1d865 1 0 0 ENABLE 0 0 regSDMA4_RLC4_MIDCMD_DATA0 0 0x1d870 1 0 0 DATA0 0 31 regSDMA4_RLC4_MIDCMD_DATA1 0 0x1d871 1 0 0 DATA1 0 31 regSDMA4_RLC4_MIDCMD_DATA2 0 0x1d872 1 0 0 DATA2 0 31 regSDMA4_RLC4_MIDCMD_DATA3 0 0x1d873 1 0 0 DATA3 0 31 regSDMA4_RLC4_MIDCMD_DATA4 0 0x1d874 1 0 0 DATA4 0 31 regSDMA4_RLC4_MIDCMD_DATA5 0 0x1d875 1 0 0 DATA5 0 31 regSDMA4_RLC4_MIDCMD_DATA6 0 0x1d876 1 0 0 DATA6 0 31 regSDMA4_RLC4_MIDCMD_DATA7 0 0x1d877 1 0 0 DATA7 0 31 regSDMA4_RLC4_MIDCMD_DATA8 0 0x1d878 1 0 0 DATA8 0 31 regSDMA4_RLC4_MIDCMD_DATA9 0 0x1d879 1 0 0 DATA9 0 31 regSDMA4_RLC4_MIDCMD_DATA10 0 0x1d87a 1 0 0 DATA10 0 31 regSDMA4_RLC4_MIDCMD_CNTL 0 0x1d87b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC5_RB_CNTL 0 0x1d888 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC5_RB_BASE 0 0x1d889 1 0 0 ADDR 0 31 regSDMA4_RLC5_RB_BASE_HI 0 0x1d88a 1 0 0 ADDR 0 23 regSDMA4_RLC5_RB_RPTR 0 0x1d88b 1 0 0 OFFSET 0 31 regSDMA4_RLC5_RB_RPTR_HI 0 0x1d88c 1 0 0 OFFSET 0 31 regSDMA4_RLC5_RB_WPTR 0 0x1d88d 1 0 0 OFFSET 0 31 regSDMA4_RLC5_RB_WPTR_HI 0 0x1d88e 1 0 0 OFFSET 0 31 regSDMA4_RLC5_RB_WPTR_POLL_CNTL 0 0x1d88f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC5_RB_RPTR_ADDR_HI 0 0x1d890 1 0 0 ADDR 0 31 regSDMA4_RLC5_RB_RPTR_ADDR_LO 0 0x1d891 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC5_IB_CNTL 0 0x1d892 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC5_IB_RPTR 0 0x1d893 1 0 0 OFFSET 2 21 regSDMA4_RLC5_IB_OFFSET 0 0x1d894 1 0 0 OFFSET 2 21 regSDMA4_RLC5_IB_BASE_LO 0 0x1d895 1 0 0 ADDR 5 31 regSDMA4_RLC5_IB_BASE_HI 0 0x1d896 1 0 0 ADDR 0 31 regSDMA4_RLC5_IB_SIZE 0 0x1d897 1 0 0 SIZE 0 19 regSDMA4_RLC5_SKIP_CNTL 0 0x1d898 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC5_CONTEXT_STATUS 0 0x1d899 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC5_DOORBELL 0 0x1d89a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC5_STATUS 0 0x1d8b0 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC5_DOORBELL_LOG 0 0x1d8b1 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC5_WATERMARK 0 0x1d8b2 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC5_DOORBELL_OFFSET 0 0x1d8b3 1 0 0 OFFSET 2 27 regSDMA4_RLC5_CSA_ADDR_LO 0 0x1d8b4 1 0 0 ADDR 2 31 regSDMA4_RLC5_CSA_ADDR_HI 0 0x1d8b5 1 0 0 ADDR 0 31 regSDMA4_RLC5_IB_SUB_REMAIN 0 0x1d8b7 1 0 0 SIZE 0 19 regSDMA4_RLC5_PREEMPT 0 0x1d8b8 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC5_DUMMY_REG 0 0x1d8b9 1 0 0 DUMMY 0 31 regSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI 0 0x1d8ba 1 0 0 ADDR 0 31 regSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO 0 0x1d8bb 1 0 0 ADDR 2 31 regSDMA4_RLC5_RB_AQL_CNTL 0 0x1d8bc 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC5_MINOR_PTR_UPDATE 0 0x1d8bd 1 0 0 ENABLE 0 0 regSDMA4_RLC5_MIDCMD_DATA0 0 0x1d8c8 1 0 0 DATA0 0 31 regSDMA4_RLC5_MIDCMD_DATA1 0 0x1d8c9 1 0 0 DATA1 0 31 regSDMA4_RLC5_MIDCMD_DATA2 0 0x1d8ca 1 0 0 DATA2 0 31 regSDMA4_RLC5_MIDCMD_DATA3 0 0x1d8cb 1 0 0 DATA3 0 31 regSDMA4_RLC5_MIDCMD_DATA4 0 0x1d8cc 1 0 0 DATA4 0 31 regSDMA4_RLC5_MIDCMD_DATA5 0 0x1d8cd 1 0 0 DATA5 0 31 regSDMA4_RLC5_MIDCMD_DATA6 0 0x1d8ce 1 0 0 DATA6 0 31 regSDMA4_RLC5_MIDCMD_DATA7 0 0x1d8cf 1 0 0 DATA7 0 31 regSDMA4_RLC5_MIDCMD_DATA8 0 0x1d8d0 1 0 0 DATA8 0 31 regSDMA4_RLC5_MIDCMD_DATA9 0 0x1d8d1 1 0 0 DATA9 0 31 regSDMA4_RLC5_MIDCMD_DATA10 0 0x1d8d2 1 0 0 DATA10 0 31 regSDMA4_RLC5_MIDCMD_CNTL 0 0x1d8d3 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC6_RB_CNTL 0 0x1d8e0 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC6_RB_BASE 0 0x1d8e1 1 0 0 ADDR 0 31 regSDMA4_RLC6_RB_BASE_HI 0 0x1d8e2 1 0 0 ADDR 0 23 regSDMA4_RLC6_RB_RPTR 0 0x1d8e3 1 0 0 OFFSET 0 31 regSDMA4_RLC6_RB_RPTR_HI 0 0x1d8e4 1 0 0 OFFSET 0 31 regSDMA4_RLC6_RB_WPTR 0 0x1d8e5 1 0 0 OFFSET 0 31 regSDMA4_RLC6_RB_WPTR_HI 0 0x1d8e6 1 0 0 OFFSET 0 31 regSDMA4_RLC6_RB_WPTR_POLL_CNTL 0 0x1d8e7 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC6_RB_RPTR_ADDR_HI 0 0x1d8e8 1 0 0 ADDR 0 31 regSDMA4_RLC6_RB_RPTR_ADDR_LO 0 0x1d8e9 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC6_IB_CNTL 0 0x1d8ea 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC6_IB_RPTR 0 0x1d8eb 1 0 0 OFFSET 2 21 regSDMA4_RLC6_IB_OFFSET 0 0x1d8ec 1 0 0 OFFSET 2 21 regSDMA4_RLC6_IB_BASE_LO 0 0x1d8ed 1 0 0 ADDR 5 31 regSDMA4_RLC6_IB_BASE_HI 0 0x1d8ee 1 0 0 ADDR 0 31 regSDMA4_RLC6_IB_SIZE 0 0x1d8ef 1 0 0 SIZE 0 19 regSDMA4_RLC6_SKIP_CNTL 0 0x1d8f0 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC6_CONTEXT_STATUS 0 0x1d8f1 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC6_DOORBELL 0 0x1d8f2 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC6_STATUS 0 0x1d908 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC6_DOORBELL_LOG 0 0x1d909 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC6_WATERMARK 0 0x1d90a 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC6_DOORBELL_OFFSET 0 0x1d90b 1 0 0 OFFSET 2 27 regSDMA4_RLC6_CSA_ADDR_LO 0 0x1d90c 1 0 0 ADDR 2 31 regSDMA4_RLC6_CSA_ADDR_HI 0 0x1d90d 1 0 0 ADDR 0 31 regSDMA4_RLC6_IB_SUB_REMAIN 0 0x1d90f 1 0 0 SIZE 0 19 regSDMA4_RLC6_PREEMPT 0 0x1d910 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC6_DUMMY_REG 0 0x1d911 1 0 0 DUMMY 0 31 regSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI 0 0x1d912 1 0 0 ADDR 0 31 regSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO 0 0x1d913 1 0 0 ADDR 2 31 regSDMA4_RLC6_RB_AQL_CNTL 0 0x1d914 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC6_MINOR_PTR_UPDATE 0 0x1d915 1 0 0 ENABLE 0 0 regSDMA4_RLC6_MIDCMD_DATA0 0 0x1d920 1 0 0 DATA0 0 31 regSDMA4_RLC6_MIDCMD_DATA1 0 0x1d921 1 0 0 DATA1 0 31 regSDMA4_RLC6_MIDCMD_DATA2 0 0x1d922 1 0 0 DATA2 0 31 regSDMA4_RLC6_MIDCMD_DATA3 0 0x1d923 1 0 0 DATA3 0 31 regSDMA4_RLC6_MIDCMD_DATA4 0 0x1d924 1 0 0 DATA4 0 31 regSDMA4_RLC6_MIDCMD_DATA5 0 0x1d925 1 0 0 DATA5 0 31 regSDMA4_RLC6_MIDCMD_DATA6 0 0x1d926 1 0 0 DATA6 0 31 regSDMA4_RLC6_MIDCMD_DATA7 0 0x1d927 1 0 0 DATA7 0 31 regSDMA4_RLC6_MIDCMD_DATA8 0 0x1d928 1 0 0 DATA8 0 31 regSDMA4_RLC6_MIDCMD_DATA9 0 0x1d929 1 0 0 DATA9 0 31 regSDMA4_RLC6_MIDCMD_DATA10 0 0x1d92a 1 0 0 DATA10 0 31 regSDMA4_RLC6_MIDCMD_CNTL 0 0x1d92b 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8 regSDMA4_RLC7_RB_CNTL 0 0x1d938 8 0 0 RB_ENABLE 0 0 RB_SIZE 1 5 RB_SWAP_ENABLE 9 9 RPTR_WRITEBACK_ENABLE 12 12 RPTR_WRITEBACK_SWAP_ENABLE 13 13 RPTR_WRITEBACK_TIMER 16 20 RB_PRIV 23 23 RB_VMID 24 27 regSDMA4_RLC7_RB_BASE 0 0x1d939 1 0 0 ADDR 0 31 regSDMA4_RLC7_RB_BASE_HI 0 0x1d93a 1 0 0 ADDR 0 23 regSDMA4_RLC7_RB_RPTR 0 0x1d93b 1 0 0 OFFSET 0 31 regSDMA4_RLC7_RB_RPTR_HI 0 0x1d93c 1 0 0 OFFSET 0 31 regSDMA4_RLC7_RB_WPTR 0 0x1d93d 1 0 0 OFFSET 0 31 regSDMA4_RLC7_RB_WPTR_HI 0 0x1d93e 1 0 0 OFFSET 0 31 regSDMA4_RLC7_RB_WPTR_POLL_CNTL 0 0x1d93f 5 0 0 ENABLE 0 0 SWAP_ENABLE 1 1 F32_POLL_ENABLE 2 2 FREQUENCY 4 15 IDLE_POLL_COUNT 16 31 regSDMA4_RLC7_RB_RPTR_ADDR_HI 0 0x1d940 1 0 0 ADDR 0 31 regSDMA4_RLC7_RB_RPTR_ADDR_LO 0 0x1d941 2 0 0 RPTR_WB_IDLE 0 0 ADDR 2 31 regSDMA4_RLC7_IB_CNTL 0 0x1d942 4 0 0 IB_ENABLE 0 0 IB_SWAP_ENABLE 4 4 SWITCH_INSIDE_IB 8 8 CMD_VMID 16 19 regSDMA4_RLC7_IB_RPTR 0 0x1d943 1 0 0 OFFSET 2 21 regSDMA4_RLC7_IB_OFFSET 0 0x1d944 1 0 0 OFFSET 2 21 regSDMA4_RLC7_IB_BASE_LO 0 0x1d945 1 0 0 ADDR 5 31 regSDMA4_RLC7_IB_BASE_HI 0 0x1d946 1 0 0 ADDR 0 31 regSDMA4_RLC7_IB_SIZE 0 0x1d947 1 0 0 SIZE 0 19 regSDMA4_RLC7_SKIP_CNTL 0 0x1d948 1 0 0 SKIP_COUNT 0 19 regSDMA4_RLC7_CONTEXT_STATUS 0 0x1d949 8 0 0 SELECTED 0 0 IDLE 2 2 EXPIRED 3 3 EXCEPTION 4 6 CTXSW_ABLE 7 7 CTXSW_READY 8 8 PREEMPTED 9 9 PREEMPT_DISABLE 10 10 regSDMA4_RLC7_DOORBELL 0 0x1d94a 2 0 0 ENABLE 28 28 CAPTURED 30 30 regSDMA4_RLC7_STATUS 0 0x1d960 2 0 0 WPTR_UPDATE_FAIL_COUNT 0 7 WPTR_UPDATE_PENDING 8 8 regSDMA4_RLC7_DOORBELL_LOG 0 0x1d961 2 0 0 BE_ERROR 0 0 DATA 2 31 regSDMA4_RLC7_WATERMARK 0 0x1d962 2 0 0 RD_OUTSTANDING 0 11 WR_OUTSTANDING 16 25 regSDMA4_RLC7_DOORBELL_OFFSET 0 0x1d963 1 0 0 OFFSET 2 27 regSDMA4_RLC7_CSA_ADDR_LO 0 0x1d964 1 0 0 ADDR 2 31 regSDMA4_RLC7_CSA_ADDR_HI 0 0x1d965 1 0 0 ADDR 0 31 regSDMA4_RLC7_IB_SUB_REMAIN 0 0x1d967 1 0 0 SIZE 0 19 regSDMA4_RLC7_PREEMPT 0 0x1d968 1 0 0 IB_PREEMPT 0 0 regSDMA4_RLC7_DUMMY_REG 0 0x1d969 1 0 0 DUMMY 0 31 regSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI 0 0x1d96a 1 0 0 ADDR 0 31 regSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO 0 0x1d96b 1 0 0 ADDR 2 31 regSDMA4_RLC7_RB_AQL_CNTL 0 0x1d96c 3 0 0 AQL_ENABLE 0 0 AQL_PACKET_SIZE 1 7 PACKET_STEP 8 15 regSDMA4_RLC7_MINOR_PTR_UPDATE 0 0x1d96d 1 0 0 ENABLE 0 0 regSDMA4_RLC7_MIDCMD_DATA0 0 0x1d978 1 0 0 DATA0 0 31 regSDMA4_RLC7_MIDCMD_DATA1 0 0x1d979 1 0 0 DATA1 0 31 regSDMA4_RLC7_MIDCMD_DATA2 0 0x1d97a 1 0 0 DATA2 0 31 regSDMA4_RLC7_MIDCMD_DATA3 0 0x1d97b 1 0 0 DATA3 0 31 regSDMA4_RLC7_MIDCMD_DATA4 0 0x1d97c 1 0 0 DATA4 0 31 regSDMA4_RLC7_MIDCMD_DATA5 0 0x1d97d 1 0 0 DATA5 0 31 regSDMA4_RLC7_MIDCMD_DATA6 0 0x1d97e 1 0 0 DATA6 0 31 regSDMA4_RLC7_MIDCMD_DATA7 0 0x1d97f 1 0 0 DATA7 0 31 regSDMA4_RLC7_MIDCMD_DATA8 0 0x1d980 1 0 0 DATA8 0 31 regSDMA4_RLC7_MIDCMD_DATA9 0 0x1d981 1 0 0 DATA9 0 31 regSDMA4_RLC7_MIDCMD_DATA10 0 0x1d982 1 0 0 DATA10 0 31 regSDMA4_RLC7_MIDCMD_CNTL 0 0x1d983 4 0 0 DATA_VALID 0 0 COPY_MODE 1 1 SPLIT_STATE 4 7 ALLOW_PREEMPT 8 8