237 mmSMUSVI0_TEL_PLANE0 0 0x4 2 0 0 SVI0_PLANE0_IDDCOR 0 7 SVI0_PLANE0_VDDCOR 16 24 mmSMUIO_MCM_CONFIG 0 0x24 4 0 0 DIE_ID 0 1 PKG_TYPE 2 4 SOCKET_ID 5 5 PKG_SUBTYPE 6 7 mmCKSVII2C_IC_CON 0 0x40 9 0 0 IC_MASTER_MODE 0 0 IC_MAX_SPEED_MODE 1 2 IC_10BITADDR_SLAVE 3 3 IC_10BITADDR_MASTER 4 4 IC_RESTART_EN 5 5 IC_SLAVE_DISABLE 6 6 STOP_DET_IFADDRESSED 7 7 TX_EMPTY_CTRL 8 8 RX_FIFO_FULL_HLD_CTRL 9 9 mmCKSVII2C_IC_TAR 0 0x41 4 0 0 IC_TAR 0 9 GC_OR_START 10 10 SPECIAL 11 11 IC_10BITADDR_MASTER 12 12 mmCKSVII2C_IC_SAR 0 0x42 1 0 0 IC_SAR 0 9 mmCKSVII2C_IC_HS_MADDR 0 0x43 1 0 0 IC_HS_MADDR 0 2 mmCKSVII2C_IC_DATA_CMD 0 0x44 4 0 0 DAT 0 7 CMD 8 8 STOP 9 9 RESTART 10 10 mmCKSVII2C_IC_SS_SCL_HCNT 0 0x45 1 0 0 IC_SS_SCL_HCNT 0 15 mmCKSVII2C_IC_SS_SCL_LCNT 0 0x46 1 0 0 IC_SS_SCL_LCNT 0 15 mmCKSVII2C_IC_FS_SCL_HCNT 0 0x47 1 0 0 IC_FS_SCL_HCNT 0 15 mmCKSVII2C_IC_FS_SCL_LCNT 0 0x48 1 0 0 IC_FS_SCL_LCNT 0 15 mmCKSVII2C_IC_HS_SCL_HCNT 0 0x49 1 0 0 IC_HS_SCL_HCNT 0 15 mmCKSVII2C_IC_HS_SCL_LCNT 0 0x4a 1 0 0 IC_HS_SCL_LCNT 0 15 mmCKSVII2C_IC_INTR_STAT 0 0x4b 14 0 0 R_RX_UNDER 0 0 R_RX_OVER 1 1 R_RX_FULL 2 2 R_TX_OVER 3 3 R_TX_EMPTY 4 4 R_RD_REQ 5 5 R_TX_ABRT 6 6 R_RX_DONE 7 7 R_ACTIVITY 8 8 R_STOP_DET 9 9 R_START_DET 10 10 R_GEN_CALL 11 11 R_RESTART_DET 12 12 R_MST_ON_HOLD 13 13 mmCKSVII2C_IC_INTR_MASK 0 0x4c 14 0 0 M_RX_UNDER 0 0 M_RX_OVER 1 1 M_RX_FULL 2 2 M_TX_OVER 3 3 M_TX_EMPTY 4 4 M_RD_REQ 5 5 M_TX_ABRT 6 6 M_RX_DONE 7 7 M_ACTIVITY 8 8 M_STOP_DET 9 9 M_START_DET 10 10 M_GEN_CALL 11 11 M_RESTART_DET 12 12 M_MST_ON_HOLD 13 13 mmCKSVII2C_IC_RAW_INTR_STAT 0 0x4d 14 0 0 R_RX_UNDER 0 0 R_RX_OVER 1 1 R_RX_FULL 2 2 R_TX_OVER 3 3 R_RD_REQ 5 5 R_TX_ABRT 6 6 R_RX_DONE 7 7 R_ACTIVITY 8 8 R_STOP_DET 9 9 R_START_DET 10 10 R_GEN_CALL 11 11 R_RESTART_DET 12 12 R_MST_ON_HOLD 13 13 R_TX_EMPTY 4 4 mmCKSVII2C_IC_RX_TL 0 0x4e 0 0 0 mmCKSVII2C_IC_TX_TL 0 0x4f 0 0 0 mmCKSVII2C_IC_CLR_INTR 0 0x50 0 0 0 mmCKSVII2C_IC_CLR_RX_UNDER 0 0x51 0 0 0 mmCKSVII2C_IC_CLR_RX_OVER 0 0x52 0 0 0 mmCKSVII2C_IC_CLR_TX_OVER 0 0x53 0 0 0 mmCKSVII2C_IC_CLR_RD_REQ 0 0x54 0 0 0 mmCKSVII2C_IC_CLR_TX_ABRT 0 0x55 0 0 0 mmCKSVII2C_IC_CLR_RX_DONE 0 0x56 0 0 0 mmCKSVII2C_IC_CLR_ACTIVITY 0 0x57 1 0 0 CLR_ACTIVITY 0 0 mmCKSVII2C_IC_CLR_STOP_DET 0 0x58 0 0 0 mmCKSVII2C_IC_CLR_START_DET 0 0x59 0 0 0 mmCKSVII2C_IC_CLR_GEN_CALL 0 0x5a 0 0 0 mmCKSVII2C_IC_ENABLE 0 0x5b 2 0 0 ENABLE 0 0 ABORT 1 1 mmCKSVII2C_IC_STATUS 0 0x5c 7 0 0 ACTIVITY 0 0 TFNF 1 1 TFE 2 2 RFNE 3 3 RFF 4 4 MST_ACTIVITY 5 5 SLV_ACTIVITY 6 6 mmCKSVII2C_IC_TXFLR 0 0x5d 0 0 0 mmCKSVII2C_IC_RXFLR 0 0x5e 0 0 0 mmCKSVII2C_IC_SDA_HOLD 0 0x5f 1 0 0 IC_SDA_HOLD 0 23 mmCKSVII2C_IC_TX_ABRT_SOURCE 0 0x60 4 0 0 ABRT_7B_ADDR_NOACK 0 0 ABRT_10ADDR1_NOACK 1 1 ABRT_10ADDR2_NOACK 2 2 ABRT_TXDATA_NOACK 3 3 mmCKSVII2C_IC_SLV_DATA_NACK_ONLY 0 0x61 0 0 0 mmCKSVII2C_IC_DMA_CR 0 0x62 0 0 0 mmCKSVII2C_IC_DMA_TDLR 0 0x63 0 0 0 mmCKSVII2C_IC_DMA_RDLR 0 0x64 0 0 0 mmCKSVII2C_IC_SDA_SETUP 0 0x65 1 0 0 SDA_SETUP 0 7 mmCKSVII2C_IC_ACK_GENERAL_CALL 0 0x66 1 0 0 ACK_GENERAL_CALL 0 0 mmCKSVII2C_IC_ENABLE_STATUS 0 0x67 3 0 0 IC_EN 0 0 SLV_RX_ABORTED 1 1 SLV_FIFO_FILLED_AND_FLUSHED 2 2 mmCKSVII2C_IC_FS_SPKLEN 0 0x68 1 0 0 FS_SPKLEN 0 7 mmCKSVII2C_IC_HS_SPKLEN 0 0x69 1 0 0 HS_SPKLEN 0 7 mmCKSVII2C_IC_CLR_RESTART_DET 0 0x6a 0 0 0 mmCKSVII2C_IC_COMP_PARAM_1 0 0x6b 1 0 0 COMP_PARAM_1 0 31 mmCKSVII2C_IC_COMP_VERSION 0 0x6c 1 0 0 COMP_VERSION 0 31 mmCKSVII2C_IC_COMP_TYPE 0 0x6d 1 0 0 COMP_TYPE 0 31 mmCKSVII2C1_IC_CON 0 0x80 9 0 0 IC1_MASTER_MODE 0 0 IC1_MAX_SPEED_MODE 1 2 IC1_10BITADDR_SLAVE 3 3 IC1_10BITADDR_MASTER 4 4 IC1_RESTART_EN 5 5 IC1_SLAVE_DISABLE 6 6 STOP1_DET_IFADDRESSED 7 7 TX1_EMPTY_CTRL 8 8 RX1_FIFO_FULL_HLD_CTRL 9 9 mmCKSVII2C1_IC_TAR 0 0x81 4 0 0 IC1_TAR 0 9 GC1_OR_START 10 10 SPECIAL1 11 11 IC1_10BITADDR_MASTER 12 12 mmCKSVII2C1_IC_SAR 0 0x82 1 0 0 IC1_SAR 0 9 mmCKSVII2C1_IC_HS_MADDR 0 0x83 1 0 0 IC1_HS_MADDR 0 2 mmCKSVII2C1_IC_DATA_CMD 0 0x84 4 0 0 DAT1 0 7 CMD1 8 8 STOP1 9 9 RESTART1 10 10 mmCKSVII2C1_IC_SS_SCL_HCNT 0 0x85 1 0 0 IC1_SS_SCL_HCNT 0 15 mmCKSVII2C1_IC_SS_SCL_LCNT 0 0x86 1 0 0 IC1_SS_SCL_LCNT 0 15 mmCKSVII2C1_IC_FS_SCL_HCNT 0 0x87 1 0 0 IC1_FS_SCL_HCNT 0 15 mmCKSVII2C1_IC_FS_SCL_LCNT 0 0x88 1 0 0 IC1_FS_SCL_LCNT 0 15 mmCKSVII2C1_IC_HS_SCL_HCNT 0 0x89 1 0 0 IC1_HS_SCL_HCNT 0 15 mmCKSVII2C1_IC_HS_SCL_LCNT 0 0x8a 1 0 0 IC1_HS_SCL_LCNT 0 15 mmCKSVII2C1_IC_INTR_STAT 0 0x8b 14 0 0 R1_RX_UNDER 0 0 R1_RX_OVER 1 1 R1_RX_FULL 2 2 R1_TX_OVER 3 3 R1_TX_EMPTY 4 4 R1_RD_REQ 5 5 R1_TX_ABRT 6 6 R1_RX_DONE 7 7 R1_ACTIVITY 8 8 R1_STOP_DET 9 9 R1_START_DET 10 10 R1_GEN_CALL 11 11 R1_RESTART_DET 12 12 R1_MST_ON_HOLD 13 13 mmCKSVII2C1_IC_INTR_MASK 0 0x8c 14 0 0 M1_RX_UNDER 0 0 M1_RX_OVER 1 1 M1_RX_FULL 2 2 M1_TX_OVER 3 3 M1_TX_EMPTY 4 4 M1_RD_REQ 5 5 M1_TX_ABRT 6 6 M1_RX_DONE 7 7 M1_ACTIVITY 8 8 M1_STOP_DET 9 9 M1_START_DET 10 10 M1_GEN_CALL 11 11 M1_RESTART_DET 12 12 M1_MST_ON_HOLD 13 13 mmCKSVII2C1_IC_RAW_INTR_STAT 0 0x8d 0 0 0 mmCKSVII2C1_IC_RX_TL 0 0x8e 0 0 0 mmCKSVII2C1_IC_TX_TL 0 0x8f 0 0 0 mmCKSVII2C1_IC_CLR_INTR 0 0x90 0 0 0 mmCKSVII2C1_IC_CLR_RX_UNDER 0 0x91 0 0 0 mmCKSVII2C1_IC_CLR_RX_OVER 0 0x92 0 0 0 mmCKSVII2C1_IC_CLR_TX_OVER 0 0x93 0 0 0 mmCKSVII2C1_IC_CLR_RD_REQ 0 0x94 0 0 0 mmCKSVII2C1_IC_CLR_TX_ABRT 0 0x95 0 0 0 mmCKSVII2C1_IC_CLR_RX_DONE 0 0x96 0 0 0 mmCKSVII2C1_IC_CLR_ACTIVITY 0 0x97 0 0 0 mmCKSVII2C1_IC_CLR_STOP_DET 0 0x98 0 0 0 mmCKSVII2C1_IC_CLR_START_DET 0 0x99 0 0 0 mmCKSVII2C1_IC_CLR_GEN_CALL 0 0x9a 0 0 0 mmCKSVII2C1_IC_ENABLE 0 0x9b 2 0 0 ENABLE1 0 0 ABORT1 1 1 mmCKSVII2C1_IC_STATUS 0 0x9c 7 0 0 ACTIVITY1 0 0 TFNF1 1 1 TFE1 2 2 RFNE1 3 3 RFF1 4 4 MST1_ACTIVITY 5 5 SLV1_ACTIVITY 6 6 mmCKSVII2C1_IC_TXFLR 0 0x9d 0 0 0 mmCKSVII2C1_IC_RXFLR 0 0x9e 0 0 0 mmCKSVII2C1_IC_SDA_HOLD 0 0x9f 1 0 0 IC1_SDA_HOLD 0 23 mmCKSVII2C1_IC_TX_ABRT_SOURCE 0 0xa0 0 0 0 mmCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0 0xa1 0 0 0 mmCKSVII2C1_IC_DMA_CR 0 0xa2 0 0 0 mmCKSVII2C1_IC_DMA_TDLR 0 0xa3 0 0 0 mmCKSVII2C1_IC_DMA_RDLR 0 0xa4 0 0 0 mmCKSVII2C1_IC_SDA_SETUP 0 0xa5 1 0 0 SDA1_SETUP 0 7 mmCKSVII2C1_IC_ACK_GENERAL_CALL 0 0xa6 1 0 0 ACK1_GENERAL_CALL 0 0 mmCKSVII2C1_IC_ENABLE_STATUS 0 0xa7 3 0 0 IC1_EN 0 0 SLV1_RX_ABORTED 1 1 SLV1_FIFO_FILLED_AND_FLUSHED 2 2 mmCKSVII2C1_IC_FS_SPKLEN 0 0xa8 0 0 0 mmCKSVII2C1_IC_HS_SPKLEN 0 0xa9 0 0 0 mmCKSVII2C1_IC_CLR_RESTART_DET 0 0xaa 0 0 0 mmCKSVII2C1_IC_COMP_PARAM_1 0 0xab 0 0 0 mmCKSVII2C1_IC_COMP_VERSION 0 0xac 0 0 0 mmCKSVII2C1_IC_COMP_TYPE 0 0xad 0 0 0 mmSMUIO_MP_RESET_INTR 0 0xc1 1 0 0 SMUIO_MP_RESET_INTR 0 0 mmSMUIO_SOC_HALT 0 0xc2 2 0 0 WDT_FORCE_PWROK_EN 2 2 WDT_FORCE_RESETn_EN 3 3 mmSMUIO_PWRMGT 0 0xc8 2 0 0 i2c_clk_gate_en 0 0 i2c1_clk_gate_en 4 4 mmROM_CNTL 0 0xe0 7 0 0 CLOCK_GATING_EN 0 0 SPI_TIMING_RELAX 20 20 SPI_TIMING_RELAX_OVERRIDE 21 21 SPI_FAST_MODE 22 22 SPI_FAST_MODE_OVERRIDE 23 23 SCK_PRESCALE_REFCLK 24 27 SCK_PRESCALE_REFCLK_OVERRIDE 28 28 mmPAGE_MIRROR_CNTL 0 0xe1 4 0 0 PAGE_MIRROR_BASE_ADDR 0 23 PAGE_MIRROR_INVALIDATE 24 24 PAGE_MIRROR_ENABLE 25 25 PAGE_MIRROR_USAGE 26 27 mmROM_STATUS 0 0xe2 1 0 0 ROM_BUSY 0 0 mmCGTT_ROM_CLK_CTRL0 0 0xe3 4 0 0 ON_DELAY 0 3 OFF_HYSTERESIS 4 11 SOFT_OVERRIDE1 30 30 SOFT_OVERRIDE0 31 31 mmROM_INDEX 0 0xe4 1 0 0 ROM_INDEX 0 23 mmROM_DATA 0 0xe5 1 0 0 ROM_DATA 0 31 mmROM_START 0 0xe6 1 0 0 ROM_START 0 23 mmROM_SW_CNTL 0 0xe7 3 0 0 DATA_SIZE 0 15 COMMAND_SIZE 16 17 ROM_SW_RETURN_DATA_ENABLE 18 18 mmROM_SW_STATUS 0 0xe8 1 0 0 ROM_SW_DONE 0 0 mmROM_SW_COMMAND 0 0xe9 2 0 0 ROM_SW_INSTRUCTION 0 7 ROM_SW_ADDRESS 8 31 mmROM_SW_DATA_1 0 0xea 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_2 0 0xeb 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_3 0 0xec 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_4 0 0xed 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_5 0 0xee 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_6 0 0xef 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_7 0 0xf0 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_8 0 0xf1 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_9 0 0xf2 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_10 0 0xf3 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_11 0 0xf4 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_12 0 0xf5 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_13 0 0xf6 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_14 0 0xf7 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_15 0 0xf8 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_16 0 0xf9 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_17 0 0xfa 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_18 0 0xfb 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_19 0 0xfc 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_20 0 0xfd 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_21 0 0xfe 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_22 0 0xff 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_23 0 0x100 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_24 0 0x101 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_25 0 0x102 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_26 0 0x103 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_27 0 0x104 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_28 0 0x105 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_29 0 0x106 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_30 0 0x107 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_31 0 0x108 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_32 0 0x109 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_33 0 0x10a 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_34 0 0x10b 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_35 0 0x10c 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_36 0 0x10d 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_37 0 0x10e 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_38 0 0x10f 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_39 0 0x110 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_40 0 0x111 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_41 0 0x112 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_42 0 0x113 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_43 0 0x114 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_44 0 0x115 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_45 0 0x116 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_46 0 0x117 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_47 0 0x118 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_48 0 0x119 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_49 0 0x11a 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_50 0 0x11b 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_51 0 0x11c 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_52 0 0x11d 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_53 0 0x11e 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_54 0 0x11f 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_55 0 0x120 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_56 0 0x121 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_57 0 0x122 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_58 0 0x123 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_59 0 0x124 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_60 0 0x125 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_61 0 0x126 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_62 0 0x127 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_63 0 0x128 1 0 0 ROM_SW_DATA 0 31 mmROM_SW_DATA_64 0 0x129 1 0 0 ROM_SW_DATA 0 31 mmSMU_GPIOPAD_SW_INT_STAT 0 0x140 1 0 0 SW_INT_STAT 0 0 mmSMU_GPIOPAD_MASK 0 0x141 1 0 0 GPIO_MASK 0 30 mmSMU_GPIOPAD_A 0 0x142 1 0 0 GPIO_A 0 30 mmSMU_GPIOPAD_TXIMPSEL 0 0x143 1 0 0 GPIO_TXIMPSEL 0 30 mmSMU_GPIOPAD_EN 0 0x144 1 0 0 GPIO_EN 0 30 mmSMU_GPIOPAD_Y 0 0x145 1 0 0 GPIO_Y 0 30 mmSMU_GPIOPAD_RXEN 0 0x146 1 0 0 GPIO_RXEN 0 30 mmSMU_GPIOPAD_RCVR_SEL0 0 0x147 1 0 0 GPIO_RCVR_SEL0 0 30 mmSMU_GPIOPAD_RCVR_SEL1 0 0x148 1 0 0 GPIO_RCVR_SEL1 0 30 mmSMU_GPIOPAD_PU_EN 0 0x149 1 0 0 GPIO_PU_EN 0 30 mmSMU_GPIOPAD_PD_EN 0 0x14a 1 0 0 GPIO_PD_EN 0 30 mmSMU_GPIOPAD_PINSTRAPS 0 0x14b 31 0 0 GPIO_PINSTRAP_0 0 0 GPIO_PINSTRAP_1 1 1 GPIO_PINSTRAP_2 2 2 GPIO_PINSTRAP_3 3 3 GPIO_PINSTRAP_4 4 4 GPIO_PINSTRAP_5 5 5 GPIO_PINSTRAP_6 6 6 GPIO_PINSTRAP_7 7 7 GPIO_PINSTRAP_8 8 8 GPIO_PINSTRAP_9 9 9 GPIO_PINSTRAP_10 10 10 GPIO_PINSTRAP_11 11 11 GPIO_PINSTRAP_12 12 12 GPIO_PINSTRAP_13 13 13 GPIO_PINSTRAP_14 14 14 GPIO_PINSTRAP_15 15 15 GPIO_PINSTRAP_16 16 16 GPIO_PINSTRAP_17 17 17 GPIO_PINSTRAP_18 18 18 GPIO_PINSTRAP_19 19 19 GPIO_PINSTRAP_20 20 20 GPIO_PINSTRAP_21 21 21 GPIO_PINSTRAP_22 22 22 GPIO_PINSTRAP_23 23 23 GPIO_PINSTRAP_24 24 24 GPIO_PINSTRAP_25 25 25 GPIO_PINSTRAP_26 26 26 GPIO_PINSTRAP_27 27 27 GPIO_PINSTRAP_28 28 28 GPIO_PINSTRAP_29 29 29 GPIO_PINSTRAP_30 30 30 mmDFT_PINSTRAPS 0 0x14c 1 0 0 DFT_PINSTRAPS 0 7 mmSMU_GPIOPAD_INT_STAT_EN 0 0x14d 2 0 0 GPIO_INT_STAT_EN 0 28 SW_INITIATED_INT_STAT_EN 31 31 mmSMU_GPIOPAD_INT_STAT 0 0x14e 2 0 0 GPIO_INT_STAT 0 28 SW_INITIATED_INT_STAT 31 31 mmSMU_GPIOPAD_INT_STAT_AK 0 0x14f 30 0 0 GPIO_INT_STAT_AK_0 0 0 GPIO_INT_STAT_AK_1 1 1 GPIO_INT_STAT_AK_2 2 2 GPIO_INT_STAT_AK_3 3 3 GPIO_INT_STAT_AK_4 4 4 GPIO_INT_STAT_AK_5 5 5 GPIO_INT_STAT_AK_6 6 6 GPIO_INT_STAT_AK_7 7 7 GPIO_INT_STAT_AK_8 8 8 GPIO_INT_STAT_AK_9 9 9 GPIO_INT_STAT_AK_10 10 10 GPIO_INT_STAT_AK_11 11 11 GPIO_INT_STAT_AK_12 12 12 GPIO_INT_STAT_AK_13 13 13 GPIO_INT_STAT_AK_14 14 14 GPIO_INT_STAT_AK_15 15 15 GPIO_INT_STAT_AK_16 16 16 GPIO_INT_STAT_AK_17 17 17 GPIO_INT_STAT_AK_18 18 18 GPIO_INT_STAT_AK_19 19 19 GPIO_INT_STAT_AK_20 20 20 GPIO_INT_STAT_AK_21 21 21 GPIO_INT_STAT_AK_22 22 22 GPIO_INT_STAT_AK_23 23 23 GPIO_INT_STAT_AK_24 24 24 GPIO_INT_STAT_AK_25 25 25 GPIO_INT_STAT_AK_26 26 26 GPIO_INT_STAT_AK_27 27 27 GPIO_INT_STAT_AK_28 28 28 SW_INITIATED_INT_STAT_AK 31 31 mmSMU_GPIOPAD_INT_EN 0 0x150 2 0 0 GPIO_INT_EN 0 28 SW_INITIATED_INT_EN 31 31 mmSMU_GPIOPAD_INT_TYPE 0 0x151 2 0 0 GPIO_INT_TYPE 0 28 SW_INITIATED_INT_TYPE 31 31 mmSMU_GPIOPAD_INT_POLARITY 0 0x152 2 0 0 GPIO_INT_POLARITY 0 28 SW_INITIATED_INT_POLARITY 31 31 mmROM_CC_BIF_PINSTRAP 0 0x153 7 0 0 BIOS_ROM_EN 0 0 BIF_MEM_AP_SIZE 1 3 ROM_CONFIG 4 6 BIF_GEN3_DIS_A 7 7 BIF_CLK_PM_EN 8 8 BIF_VGA_DIS 9 9 BIF_LC_TX_SWING 10 10 mmIO_SMUIO_PINSTRAP 0 0x154 4 0 0 AUD_PORT_CONN 0 2 AUD 3 4 BOARD_CONFIG 5 7 SMBUS_ADDR 8 8 mmSMUIO_PCC_CONTROL 0 0x155 1 0 0 PCC_POLARITY 0 0 mmSMUIO_PCC_GPIO_SELECT 0 0x156 1 0 0 GPIO 0 31 mmSMUIO_GPIO_INT0_SELECT 0 0x157 1 0 0 GPIO_INT0_SELECT 0 31 mmSMUIO_GPIO_INT1_SELECT 0 0x158 1 0 0 GPIO_INT1_SELECT 0 31 mmSMUIO_GPIO_INT2_SELECT 0 0x159 1 0 0 GPIO_INT2_SELECT 0 31 mmSMUIO_GPIO_INT3_SELECT 0 0x15a 1 0 0 GPIO_INT3_SELECT 0 31 mmSMU_GPIOPAD_MP_INT0_STAT 0 0x15b 1 0 0 GPIO_MP_INT0_STAT 0 28 mmSMU_GPIOPAD_MP_INT1_STAT 0 0x15c 1 0 0 GPIO_MP_INT1_STAT 0 28 mmSMU_GPIOPAD_MP_INT2_STAT 0 0x15d 1 0 0 GPIO_MP_INT2_STAT 0 28 mmSMU_GPIOPAD_MP_INT3_STAT 0 0x15e 1 0 0 GPIO_MP_INT3_STAT 0 28 mmSMIO_INDEX 0 0x15f 1 0 0 SW_SMIO_INDEX 0 0 mmS0_VID_SMIO_CNTL 0 0x160 1 0 0 S0_SMIO_VALUES 0 31 mmS1_VID_SMIO_CNTL 0 0x161 1 0 0 S1_SMIO_VALUES 0 31 mmOPEN_DRAIN_SELECT 0 0x162 2 0 0 OPEN_DRAIN_SELECT 0 30 RESERVED 31 31 mmSMIO_ENABLE 0 0x163 1 0 0 SMIO_ENABLE 0 31 mmSMU_GPIOPAD_S0 0 0x166 1 0 0 GPIO_S0 0 30 mmSMU_GPIOPAD_S1 0 0x167 1 0 0 GPIO_S1 0 30 mmSMU_GPIOPAD_SCL_EN 0 0x168 1 0 0 GPIO_SCL_EN 0 30 mmSMU_GPIOPAD_SDA_EN 0 0x169 1 0 0 GPIO_SDA_EN 0 30 mmSMU_GPIOPAD_SCHMEN 0 0x16a 1 0 0 GPIO_SCHMEN 0 30 mmIP_DISCOVERY_VERSION 0 0x0 1 0 1 IP_DISCOVERY_VERSION 0 31 mmSOC_GAP_PWROK 0 0xf8 1 0 1 soc_gap_pwrok 0 0 mmGFX_GAP_PWROK 0 0xf9 1 0 1 gfx_gap_pwrok 0 0 mmPWROK_REFCLK_GAP_CYCLES 0 0xfa 2 0 1 Pwrok_PreAssertion_clkgap_cycles 0 7 Pwrok_PostAssertion_clkgap_cycles 8 15 mmGOLDEN_TSC_INCREMENT_UPPER 0 0x100 1 0 1 GoldenTscIncrementUpper 0 23 mmGOLDEN_TSC_INCREMENT_LOWER 0 0x101 1 0 1 GoldenTscIncrementLower 0 31 mmGOLDEN_TSC_COUNT_UPPER 0 0x102 1 0 1 GoldenTscCountUpper 0 23 mmGOLDEN_TSC_COUNT_LOWER 0 0x103 1 0 1 GoldenTscCountLower 0 31 mmSOC_GOLDEN_TSC_SHADOW_UPPER 0 0x104 1 0 1 SOCGoldenTscShadowUpper 0 23 mmSOC_GOLDEN_TSC_SHADOW_LOWER 0 0x105 1 0 1 SOCGoldenTscShadowLower 0 31 mmGFX_GOLDEN_TSC_SHADOW_UPPER 0 0x106 1 0 1 GFXGoldenTscShadowUpper 0 23 mmGFX_GOLDEN_TSC_SHADOW_LOWER 0 0x107 1 0 1 GFXGoldenTscShadowLower 0 31 mmPWR_VIRT_RESET_REQ 0 0x108 2 0 1 VF_FLR 0 30 PF_FLR 31 31 mmSCRATCH_REGISTER0 0 0x110 1 0 1 ScratchPad0 0 31 mmSCRATCH_REGISTER1 0 0x111 1 0 1 ScratchPad1 0 31 mmSCRATCH_REGISTER2 0 0x112 1 0 1 ScratchPad2 0 31 mmSCRATCH_REGISTER3 0 0x113 1 0 1 ScratchPad3 0 31 mmSCRATCH_REGISTER4 0 0x114 1 0 1 ScratchPad4 0 31 mmSCRATCH_REGISTER5 0 0x115 1 0 1 ScratchPad5 0 31 mmSCRATCH_REGISTER6 0 0x116 1 0 1 ScratchPad6 0 31 mmSCRATCH_REGISTER7 0 0x117 1 0 1 ScratchPad7 0 31 mmPWR_DISP_TIMER_CONTROL 0 0x12c 7 0 1 DISP_TIMER_INT_COUNT 0 24 DISP_TIMER_INT_ENABLE 25 25 DISP_TIMER_INT_DISABLE 26 26 DISP_TIMER_INT_MASK 27 27 DISP_TIMER_INT_STAT_AK 28 28 DISP_TIMER_INT_TYPE 29 29 DISP_TIMER_INT_MODE 30 30 mmPWR_DISP_TIMER2_CONTROL 0 0x12e 7 0 1 DISP_TIMER_INT_COUNT 0 24 DISP_TIMER_INT_ENABLE 25 25 DISP_TIMER_INT_DISABLE 26 26 DISP_TIMER_INT_MASK 27 27 DISP_TIMER_INT_STAT_AK 28 28 DISP_TIMER_INT_TYPE 29 29 DISP_TIMER_INT_MODE 30 30 mmPWR_DISP_TIMER_GLOBAL_CONTROL 0 0x130 2 0 1 DISP_TIMER_PULSE_WIDTH 0 9 DISP_TIMER_PULSE_EN 10 10 mmPWR_IH_CONTROL 0 0x131 3 0 1 MAX_CREDIT 0 4 DISP_TIMER_TRIGGER_MASK 5 5 DISP_TIMER2_TRIGGER_MASK 6 6