1233 regMCA_UMC_UMC0_MCUMC_STATUST0 0 0x3c2 26 1 0 ErrorCode 0 15 ErrorCodeExt 16 21 RESERV22 22 23 AddrLsb 24 29 RESERV30 30 31 ErrCoreId 32 37 RESERV38 38 39 Scrub 40 40 RESERV41 41 42 Poison 43 43 Deferred 44 44 UECC 45 45 CECC 46 46 RESERV47 47 51 Transparent 52 52 SyndV 53 53 RESERV54 54 54 TCC 55 55 ErrCoreIdVal 56 56 PCC 57 57 AddrV 58 58 MiscV 59 59 En 60 60 UC 61 61 Overflow 62 62 Val 63 63 regMCA_UMC_UMC0_MCUMC_ADDRT0 0 0x3c4 2 1 0 ErrorAddr 0 55 Reserved 56 63 regMCA_UMC_UMC0_MCUMC_MISC0T0 0 0x3c6 0 0 0 regMCA_UMC_UMC0_MCUMC_IPIDT0 0 0x3ca 0 0 0 regMCA_UMC_UMC0_MCUMC_SYNDT0 0 0x3cc 0 0 0 regUMCCH0_0_BaseAddrCS0 0 0x0 2 0 0 CSEnable 0 0 BaseAddr 1 31 regUMCCH0_0_AddrMaskCS01 0 0x8 1 0 0 AddrMask 1 31 regUMCCH0_0_AddrSelCS01 0 0x10 7 0 0 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH0_0_AddrHashBank0 0 0x32 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_AddrHashBank1 0 0x33 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_AddrHashBank2 0 0x34 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_AddrHashBank3 0 0x35 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_AddrHashBank4 0 0x36 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_AddrHashBank5 0 0x37 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_0_UMC_CONFIG 0 0x40 4 0 0 DDR_TYPE 0 2 BurstLength 8 9 BurstCtrl 10 11 DramReady 31 31 regUMCCH0_0_EccCtrl 0 0x53 6 0 0 WrEccEn 0 0 EccReplayEn 1 1 UCFatalEn 8 8 RdEccEn 10 10 PoisonFatalDis 12 12 PoisonInhibit 13 13 regUMCCH0_0_UmcLocalCap 0 0x306 3 0 0 EccDis 0 0 Spare 1 5 WrDis 31 31 regUMCCH0_0_EccErrCntSel 0 0x328 3 0 0 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH0_0_EccErrCnt 0 0x329 1 0 0 EccErrCnt 0 15 regUMCCH0_0_PerfMonCtlClk 0 0x340 6 0 0 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH0_0_PerfMonCtrClk_Lo 0 0x341 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtrClk_Hi 0 0x342 2 0 0 Data 0 15 Overflow 16 16 regUMCCH0_0_PerfMonCtl1 0 0x344 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr1_Lo 0 0x345 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr1_Hi 0 0x346 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl2 0 0x347 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr2_Lo 0 0x348 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr2_Hi 0 0x349 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl3 0 0x34a 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr3_Lo 0 0x34b 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr3_Hi 0 0x34c 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl4 0 0x34d 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr4_Lo 0 0x34e 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr4_Hi 0 0x34f 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl5 0 0x350 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr5_Lo 0 0x351 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr5_Hi 0 0x352 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl6 0 0x353 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr6_Lo 0 0x354 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr6_Hi 0 0x355 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl7 0 0x356 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr7_Lo 0 0x357 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr7_Hi 0 0x358 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_0_PerfMonCtl8 0 0x359 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_0_PerfMonCtr8_Lo 0 0x35a 1 0 0 Data 0 31 regUMCCH0_0_PerfMonCtr8_Hi 0 0x35b 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_BaseAddrCS0 0 0x400 2 0 0 CSEnable 0 0 BaseAddr 1 31 regUMCCH1_0_AddrMaskCS01 0 0x408 1 0 0 AddrMask 1 31 regUMCCH1_0_AddrSelCS01 0 0x410 7 0 0 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH1_0_AddrHashBank0 0 0x432 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_AddrHashBank1 0 0x433 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_AddrHashBank2 0 0x434 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_AddrHashBank3 0 0x435 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_AddrHashBank4 0 0x436 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_AddrHashBank5 0 0x437 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_0_UMC_CONFIG 0 0x440 4 0 0 DDR_TYPE 0 2 BurstLength 8 9 BurstCtrl 10 11 DramReady 31 31 regUMCCH1_0_EccCtrl 0 0x453 6 0 0 WrEccEn 0 0 EccReplayEn 1 1 UCFatalEn 8 8 RdEccEn 10 10 PoisonFatalDis 12 12 PoisonInhibit 13 13 regUMCCH1_0_UmcLocalCap 0 0x706 3 0 0 EccDis 0 0 Spare 1 5 WrDis 31 31 regUMCCH1_0_EccErrCntSel 0 0x728 3 0 0 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH1_0_EccErrCnt 0 0x729 1 0 0 EccErrCnt 0 15 regUMCCH1_0_PerfMonCtlClk 0 0x740 6 0 0 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH1_0_PerfMonCtrClk_Lo 0 0x741 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtrClk_Hi 0 0x742 2 0 0 Data 0 15 Overflow 16 16 regUMCCH1_0_PerfMonCtl1 0 0x744 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr1_Lo 0 0x745 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr1_Hi 0 0x746 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl2 0 0x747 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr2_Lo 0 0x748 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr2_Hi 0 0x749 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl3 0 0x74a 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr3_Lo 0 0x74b 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr3_Hi 0 0x74c 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl4 0 0x74d 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr4_Lo 0 0x74e 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr4_Hi 0 0x74f 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl5 0 0x750 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr5_Lo 0 0x751 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr5_Hi 0 0x752 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl6 0 0x753 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr6_Lo 0 0x754 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr6_Hi 0 0x755 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl7 0 0x756 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr7_Lo 0 0x757 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr7_Hi 0 0x758 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_0_PerfMonCtl8 0 0x759 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_0_PerfMonCtr8_Lo 0 0x75a 1 0 0 Data 0 31 regUMCCH1_0_PerfMonCtr8_Hi 0 0x75b 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_BaseAddrCS0 0 0x800 2 0 0 CSEnable 0 0 BaseAddr 1 31 regUMCCH2_0_AddrMaskCS01 0 0x808 1 0 0 AddrMask 1 31 regUMCCH2_0_AddrSelCS01 0 0x810 7 0 0 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH2_0_AddrHashBank0 0 0x832 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_AddrHashBank1 0 0x833 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_AddrHashBank2 0 0x834 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_AddrHashBank3 0 0x835 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_AddrHashBank4 0 0x836 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_AddrHashBank5 0 0x837 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_0_UMC_CONFIG 0 0x840 4 0 0 DDR_TYPE 0 2 BurstLength 8 9 BurstCtrl 10 11 DramReady 31 31 regUMCCH2_0_EccCtrl 0 0x853 6 0 0 WrEccEn 0 0 EccReplayEn 1 1 UCFatalEn 8 8 RdEccEn 10 10 PoisonFatalDis 12 12 PoisonInhibit 13 13 regUMCCH2_0_UmcLocalCap 0 0xb06 3 0 0 EccDis 0 0 Spare 1 5 WrDis 31 31 regUMCCH2_0_EccErrCntSel 0 0xb28 3 0 0 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH2_0_EccErrCnt 0 0xb29 1 0 0 EccErrCnt 0 15 regUMCCH2_0_PerfMonCtlClk 0 0xb40 6 0 0 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH2_0_PerfMonCtrClk_Lo 0 0xb41 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtrClk_Hi 0 0xb42 2 0 0 Data 0 15 Overflow 16 16 regUMCCH2_0_PerfMonCtl1 0 0xb44 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr1_Lo 0 0xb45 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr1_Hi 0 0xb46 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl2 0 0xb47 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr2_Lo 0 0xb48 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr2_Hi 0 0xb49 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl3 0 0xb4a 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr3_Lo 0 0xb4b 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr3_Hi 0 0xb4c 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl4 0 0xb4d 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr4_Lo 0 0xb4e 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr4_Hi 0 0xb4f 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl5 0 0xb50 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr5_Lo 0 0xb51 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr5_Hi 0 0xb52 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl6 0 0xb53 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr6_Lo 0 0xb54 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr6_Hi 0 0xb55 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl7 0 0xb56 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr7_Lo 0 0xb57 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr7_Hi 0 0xb58 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_0_PerfMonCtl8 0 0xb59 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_0_PerfMonCtr8_Lo 0 0xb5a 1 0 0 Data 0 31 regUMCCH2_0_PerfMonCtr8_Hi 0 0xb5b 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_BaseAddrCS0 0 0xc00 2 0 0 CSEnable 0 0 BaseAddr 1 31 regUMCCH3_0_AddrMaskCS01 0 0xc08 1 0 0 AddrMask 1 31 regUMCCH3_0_AddrSelCS01 0 0xc10 7 0 0 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH3_0_AddrHashBank0 0 0xc32 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_AddrHashBank1 0 0xc33 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_AddrHashBank2 0 0xc34 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_AddrHashBank3 0 0xc35 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_AddrHashBank4 0 0xc36 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_AddrHashBank5 0 0xc37 3 0 0 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_0_UMC_CONFIG 0 0xc40 4 0 0 DDR_TYPE 0 2 BurstLength 8 9 BurstCtrl 10 11 DramReady 31 31 regUMCCH3_0_EccCtrl 0 0xc53 6 0 0 WrEccEn 0 0 EccReplayEn 1 1 UCFatalEn 8 8 RdEccEn 10 10 PoisonFatalDis 12 12 PoisonInhibit 13 13 regUMCCH3_0_UmcLocalCap 0 0xf06 3 0 0 EccDis 0 0 Spare 1 5 WrDis 31 31 regUMCCH3_0_EccErrCntSel 0 0xf28 3 0 0 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH3_0_EccErrCnt 0 0xf29 1 0 0 EccErrCnt 0 15 regUMCCH3_0_PerfMonCtlClk 0 0xf40 6 0 0 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH3_0_PerfMonCtrClk_Lo 0 0xf41 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtrClk_Hi 0 0xf42 2 0 0 Data 0 15 Overflow 16 16 regUMCCH3_0_PerfMonCtl1 0 0xf44 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr1_Lo 0 0xf45 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr1_Hi 0 0xf46 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl2 0 0xf47 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr2_Lo 0 0xf48 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr2_Hi 0 0xf49 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl3 0 0xf4a 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr3_Lo 0 0xf4b 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr3_Hi 0 0xf4c 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl4 0 0xf4d 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr4_Lo 0 0xf4e 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr4_Hi 0 0xf4f 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl5 0 0xf50 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr5_Lo 0 0xf51 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr5_Hi 0 0xf52 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl6 0 0xf53 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr6_Lo 0 0xf54 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr6_Hi 0 0xf55 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl7 0 0xf56 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr7_Lo 0 0xf57 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr7_Hi 0 0xf58 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_0_PerfMonCtl8 0 0xf59 8 0 0 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_0_PerfMonCtr8_Lo 0 0xf5a 1 0 0 Data 0 31 regUMCCH3_0_PerfMonCtr8_Hi 0 0xf5b 4 0 0 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_BaseAddrCS0 0 0x0 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH4_0_AddrMaskCS01 0 0x8 1 0 1 AddrMask 1 31 regUMCCH4_0_AddrSelCS01 0 0x10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH4_0_AddrHashBank0 0 0x32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_AddrHashBank1 0 0x33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_AddrHashBank2 0 0x34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_AddrHashBank3 0 0x35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_AddrHashBank4 0 0x36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_AddrHashBank5 0 0x37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_0_EccErrCntSel 0 0x328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH4_0_EccErrCnt 0 0x329 1 0 1 EccErrCnt 0 15 regUMCCH4_0_PerfMonCtlClk 0 0x340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH4_0_PerfMonCtrClk_Lo 0 0x341 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtrClk_Hi 0 0x342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH4_0_PerfMonCtl1 0 0x344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr1_Lo 0 0x345 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr1_Hi 0 0x346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl2 0 0x347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr2_Lo 0 0x348 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr2_Hi 0 0x349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl3 0 0x34a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr3_Lo 0 0x34b 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr3_Hi 0 0x34c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl4 0 0x34d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr4_Lo 0 0x34e 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr4_Hi 0 0x34f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl5 0 0x350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr5_Lo 0 0x351 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr5_Hi 0 0x352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl6 0 0x353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr6_Lo 0 0x354 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr6_Hi 0 0x355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl7 0 0x356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr7_Lo 0 0x357 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr7_Hi 0 0x358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_0_PerfMonCtl8 0 0x359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_0_PerfMonCtr8_Lo 0 0x35a 1 0 1 Data 0 31 regUMCCH4_0_PerfMonCtr8_Hi 0 0x35b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_BaseAddrCS0 0 0x400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH5_0_AddrMaskCS01 0 0x408 1 0 1 AddrMask 1 31 regUMCCH5_0_AddrSelCS01 0 0x410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH5_0_AddrHashBank0 0 0x432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_AddrHashBank1 0 0x433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_AddrHashBank2 0 0x434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_AddrHashBank3 0 0x435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_AddrHashBank4 0 0x436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_AddrHashBank5 0 0x437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_0_EccErrCntSel 0 0x728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH5_0_EccErrCnt 0 0x729 1 0 1 EccErrCnt 0 15 regUMCCH5_0_PerfMonCtlClk 0 0x740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH5_0_PerfMonCtrClk_Lo 0 0x741 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtrClk_Hi 0 0x742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH5_0_PerfMonCtl1 0 0x744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr1_Lo 0 0x745 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr1_Hi 0 0x746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl2 0 0x747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr2_Lo 0 0x748 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr2_Hi 0 0x749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl3 0 0x74a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr3_Lo 0 0x74b 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr3_Hi 0 0x74c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl4 0 0x74d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr4_Lo 0 0x74e 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr4_Hi 0 0x74f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl5 0 0x750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr5_Lo 0 0x751 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr5_Hi 0 0x752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl6 0 0x753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr6_Lo 0 0x754 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr6_Hi 0 0x755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl7 0 0x756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr7_Lo 0 0x757 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr7_Hi 0 0x758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_0_PerfMonCtl8 0 0x759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_0_PerfMonCtr8_Lo 0 0x75a 1 0 1 Data 0 31 regUMCCH5_0_PerfMonCtr8_Hi 0 0x75b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_BaseAddrCS0 0 0x800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH6_0_AddrMaskCS01 0 0x808 1 0 1 AddrMask 1 31 regUMCCH6_0_AddrSelCS01 0 0x810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH6_0_AddrHashBank0 0 0x832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_AddrHashBank1 0 0x833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_AddrHashBank2 0 0x834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_AddrHashBank3 0 0x835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_AddrHashBank4 0 0x836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_AddrHashBank5 0 0x837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_0_EccErrCntSel 0 0xb28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH6_0_EccErrCnt 0 0xb29 1 0 1 EccErrCnt 0 15 regUMCCH6_0_PerfMonCtlClk 0 0xb40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH6_0_PerfMonCtrClk_Lo 0 0xb41 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtrClk_Hi 0 0xb42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH6_0_PerfMonCtl1 0 0xb44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr1_Lo 0 0xb45 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr1_Hi 0 0xb46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl2 0 0xb47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr2_Lo 0 0xb48 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr2_Hi 0 0xb49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl3 0 0xb4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr3_Lo 0 0xb4b 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr3_Hi 0 0xb4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl4 0 0xb4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr4_Lo 0 0xb4e 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr4_Hi 0 0xb4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl5 0 0xb50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr5_Lo 0 0xb51 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr5_Hi 0 0xb52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl6 0 0xb53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr6_Lo 0 0xb54 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr6_Hi 0 0xb55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl7 0 0xb56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr7_Lo 0 0xb57 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr7_Hi 0 0xb58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_0_PerfMonCtl8 0 0xb59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_0_PerfMonCtr8_Lo 0 0xb5a 1 0 1 Data 0 31 regUMCCH6_0_PerfMonCtr8_Hi 0 0xb5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_BaseAddrCS0 0 0xc00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH7_0_AddrMaskCS01 0 0xc08 1 0 1 AddrMask 1 31 regUMCCH7_0_AddrSelCS01 0 0xc10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH7_0_AddrHashBank0 0 0xc32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_AddrHashBank1 0 0xc33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_AddrHashBank2 0 0xc34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_AddrHashBank3 0 0xc35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_AddrHashBank4 0 0xc36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_AddrHashBank5 0 0xc37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_0_EccErrCntSel 0 0xf28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH7_0_EccErrCnt 0 0xf29 1 0 1 EccErrCnt 0 15 regUMCCH7_0_PerfMonCtlClk 0 0xf40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH7_0_PerfMonCtrClk_Lo 0 0xf41 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtrClk_Hi 0 0xf42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH7_0_PerfMonCtl1 0 0xf44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr1_Lo 0 0xf45 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr1_Hi 0 0xf46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl2 0 0xf47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr2_Lo 0 0xf48 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr2_Hi 0 0xf49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl3 0 0xf4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr3_Lo 0 0xf4b 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr3_Hi 0 0xf4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl4 0 0xf4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr4_Lo 0 0xf4e 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr4_Hi 0 0xf4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl5 0 0xf50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr5_Lo 0 0xf51 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr5_Hi 0 0xf52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl6 0 0xf53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr6_Lo 0 0xf54 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr6_Hi 0 0xf55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl7 0 0xf56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr7_Lo 0 0xf57 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr7_Hi 0 0xf58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_0_PerfMonCtl8 0 0xf59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_0_PerfMonCtr8_Lo 0 0xf5a 1 0 1 Data 0 31 regUMCCH7_0_PerfMonCtr8_Hi 0 0xf5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_BaseAddrCS0 0 0x40000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH0_1_AddrMaskCS01 0 0x40008 1 0 1 AddrMask 1 31 regUMCCH0_1_AddrSelCS01 0 0x40010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH0_1_AddrHashBank0 0 0x40032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_AddrHashBank1 0 0x40033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_AddrHashBank2 0 0x40034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_AddrHashBank3 0 0x40035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_AddrHashBank4 0 0x40036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_AddrHashBank5 0 0x40037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_1_EccErrCntSel 0 0x40328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH0_1_EccErrCnt 0 0x40329 1 0 1 EccErrCnt 0 15 regUMCCH0_1_PerfMonCtlClk 0 0x40340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH0_1_PerfMonCtrClk_Lo 0 0x40341 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtrClk_Hi 0 0x40342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH0_1_PerfMonCtl1 0 0x40344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr1_Lo 0 0x40345 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr1_Hi 0 0x40346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl2 0 0x40347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr2_Lo 0 0x40348 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr2_Hi 0 0x40349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl3 0 0x4034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr3_Lo 0 0x4034b 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr3_Hi 0 0x4034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl4 0 0x4034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr4_Lo 0 0x4034e 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr4_Hi 0 0x4034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl5 0 0x40350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr5_Lo 0 0x40351 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr5_Hi 0 0x40352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl6 0 0x40353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr6_Lo 0 0x40354 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr6_Hi 0 0x40355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl7 0 0x40356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr7_Lo 0 0x40357 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr7_Hi 0 0x40358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_1_PerfMonCtl8 0 0x40359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_1_PerfMonCtr8_Lo 0 0x4035a 1 0 1 Data 0 31 regUMCCH0_1_PerfMonCtr8_Hi 0 0x4035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_BaseAddrCS0 0 0x40400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH1_1_AddrMaskCS01 0 0x40408 1 0 1 AddrMask 1 31 regUMCCH1_1_AddrSelCS01 0 0x40410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH1_1_AddrHashBank0 0 0x40432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_AddrHashBank1 0 0x40433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_AddrHashBank2 0 0x40434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_AddrHashBank3 0 0x40435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_AddrHashBank4 0 0x40436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_AddrHashBank5 0 0x40437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_1_EccErrCntSel 0 0x40728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH1_1_EccErrCnt 0 0x40729 1 0 1 EccErrCnt 0 15 regUMCCH1_1_PerfMonCtlClk 0 0x40740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH1_1_PerfMonCtrClk_Lo 0 0x40741 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtrClk_Hi 0 0x40742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH1_1_PerfMonCtl1 0 0x40744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr1_Lo 0 0x40745 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr1_Hi 0 0x40746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl2 0 0x40747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr2_Lo 0 0x40748 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr2_Hi 0 0x40749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl3 0 0x4074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr3_Lo 0 0x4074b 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr3_Hi 0 0x4074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl4 0 0x4074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr4_Lo 0 0x4074e 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr4_Hi 0 0x4074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl5 0 0x40750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr5_Lo 0 0x40751 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr5_Hi 0 0x40752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl6 0 0x40753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr6_Lo 0 0x40754 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr6_Hi 0 0x40755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl7 0 0x40756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr7_Lo 0 0x40757 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr7_Hi 0 0x40758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_1_PerfMonCtl8 0 0x40759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_1_PerfMonCtr8_Lo 0 0x4075a 1 0 1 Data 0 31 regUMCCH1_1_PerfMonCtr8_Hi 0 0x4075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_BaseAddrCS0 0 0x40800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH2_1_AddrMaskCS01 0 0x40808 1 0 1 AddrMask 1 31 regUMCCH2_1_AddrSelCS01 0 0x40810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH2_1_AddrHashBank0 0 0x40832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_AddrHashBank1 0 0x40833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_AddrHashBank2 0 0x40834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_AddrHashBank3 0 0x40835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_AddrHashBank4 0 0x40836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_AddrHashBank5 0 0x40837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_1_EccErrCntSel 0 0x40b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH2_1_EccErrCnt 0 0x40b29 1 0 1 EccErrCnt 0 15 regUMCCH2_1_PerfMonCtlClk 0 0x40b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH2_1_PerfMonCtrClk_Lo 0 0x40b41 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtrClk_Hi 0 0x40b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH2_1_PerfMonCtl1 0 0x40b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr1_Lo 0 0x40b45 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr1_Hi 0 0x40b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl2 0 0x40b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr2_Lo 0 0x40b48 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr2_Hi 0 0x40b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl3 0 0x40b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr3_Lo 0 0x40b4b 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr3_Hi 0 0x40b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl4 0 0x40b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr4_Lo 0 0x40b4e 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr4_Hi 0 0x40b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl5 0 0x40b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr5_Lo 0 0x40b51 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr5_Hi 0 0x40b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl6 0 0x40b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr6_Lo 0 0x40b54 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr6_Hi 0 0x40b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl7 0 0x40b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr7_Lo 0 0x40b57 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr7_Hi 0 0x40b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_1_PerfMonCtl8 0 0x40b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_1_PerfMonCtr8_Lo 0 0x40b5a 1 0 1 Data 0 31 regUMCCH2_1_PerfMonCtr8_Hi 0 0x40b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_BaseAddrCS0 0 0x40c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH3_1_AddrMaskCS01 0 0x40c08 1 0 1 AddrMask 1 31 regUMCCH3_1_AddrSelCS01 0 0x40c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH3_1_AddrHashBank0 0 0x40c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_AddrHashBank1 0 0x40c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_AddrHashBank2 0 0x40c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_AddrHashBank3 0 0x40c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_AddrHashBank4 0 0x40c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_AddrHashBank5 0 0x40c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_1_EccErrCntSel 0 0x40f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH3_1_EccErrCnt 0 0x40f29 1 0 1 EccErrCnt 0 15 regUMCCH3_1_PerfMonCtlClk 0 0x40f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH3_1_PerfMonCtrClk_Lo 0 0x40f41 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtrClk_Hi 0 0x40f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH3_1_PerfMonCtl1 0 0x40f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr1_Lo 0 0x40f45 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr1_Hi 0 0x40f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl2 0 0x40f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr2_Lo 0 0x40f48 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr2_Hi 0 0x40f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl3 0 0x40f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr3_Lo 0 0x40f4b 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr3_Hi 0 0x40f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl4 0 0x40f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr4_Lo 0 0x40f4e 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr4_Hi 0 0x40f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl5 0 0x40f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr5_Lo 0 0x40f51 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr5_Hi 0 0x40f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl6 0 0x40f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr6_Lo 0 0x40f54 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr6_Hi 0 0x40f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl7 0 0x40f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr7_Lo 0 0x40f57 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr7_Hi 0 0x40f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_1_PerfMonCtl8 0 0x40f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_1_PerfMonCtr8_Lo 0 0x40f5a 1 0 1 Data 0 31 regUMCCH3_1_PerfMonCtr8_Hi 0 0x40f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_BaseAddrCS0 0 0x80000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH4_1_AddrMaskCS01 0 0x80008 1 0 1 AddrMask 1 31 regUMCCH4_1_AddrSelCS01 0 0x80010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH4_1_AddrHashBank0 0 0x80032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_AddrHashBank1 0 0x80033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_AddrHashBank2 0 0x80034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_AddrHashBank3 0 0x80035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_AddrHashBank4 0 0x80036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_AddrHashBank5 0 0x80037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_1_EccErrCntSel 0 0x80328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH4_1_EccErrCnt 0 0x80329 1 0 1 EccErrCnt 0 15 regUMCCH4_1_PerfMonCtlClk 0 0x80340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH4_1_PerfMonCtrClk_Lo 0 0x80341 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtrClk_Hi 0 0x80342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH4_1_PerfMonCtl1 0 0x80344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr1_Lo 0 0x80345 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr1_Hi 0 0x80346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl2 0 0x80347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr2_Lo 0 0x80348 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr2_Hi 0 0x80349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl3 0 0x8034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr3_Lo 0 0x8034b 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr3_Hi 0 0x8034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl4 0 0x8034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr4_Lo 0 0x8034e 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr4_Hi 0 0x8034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl5 0 0x80350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr5_Lo 0 0x80351 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr5_Hi 0 0x80352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl6 0 0x80353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr6_Lo 0 0x80354 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr6_Hi 0 0x80355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl7 0 0x80356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr7_Lo 0 0x80357 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr7_Hi 0 0x80358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_1_PerfMonCtl8 0 0x80359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_1_PerfMonCtr8_Lo 0 0x8035a 1 0 1 Data 0 31 regUMCCH4_1_PerfMonCtr8_Hi 0 0x8035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_BaseAddrCS0 0 0x80400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH5_1_AddrMaskCS01 0 0x80408 1 0 1 AddrMask 1 31 regUMCCH5_1_AddrSelCS01 0 0x80410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH5_1_AddrHashBank0 0 0x80432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_AddrHashBank1 0 0x80433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_AddrHashBank2 0 0x80434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_AddrHashBank3 0 0x80435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_AddrHashBank4 0 0x80436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_AddrHashBank5 0 0x80437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_1_EccErrCntSel 0 0x80728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH5_1_EccErrCnt 0 0x80729 1 0 1 EccErrCnt 0 15 regUMCCH5_1_PerfMonCtlClk 0 0x80740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH5_1_PerfMonCtrClk_Lo 0 0x80741 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtrClk_Hi 0 0x80742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH5_1_PerfMonCtl1 0 0x80744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr1_Lo 0 0x80745 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr1_Hi 0 0x80746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl2 0 0x80747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr2_Lo 0 0x80748 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr2_Hi 0 0x80749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl3 0 0x8074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr3_Lo 0 0x8074b 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr3_Hi 0 0x8074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl4 0 0x8074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr4_Lo 0 0x8074e 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr4_Hi 0 0x8074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl5 0 0x80750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr5_Lo 0 0x80751 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr5_Hi 0 0x80752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl6 0 0x80753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr6_Lo 0 0x80754 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr6_Hi 0 0x80755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl7 0 0x80756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr7_Lo 0 0x80757 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr7_Hi 0 0x80758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_1_PerfMonCtl8 0 0x80759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_1_PerfMonCtr8_Lo 0 0x8075a 1 0 1 Data 0 31 regUMCCH5_1_PerfMonCtr8_Hi 0 0x8075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_BaseAddrCS0 0 0x80800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH6_1_AddrMaskCS01 0 0x80808 1 0 1 AddrMask 1 31 regUMCCH6_1_AddrSelCS01 0 0x80810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH6_1_AddrHashBank0 0 0x80832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_AddrHashBank1 0 0x80833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_AddrHashBank2 0 0x80834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_AddrHashBank3 0 0x80835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_AddrHashBank4 0 0x80836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_AddrHashBank5 0 0x80837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_1_EccErrCntSel 0 0x80b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH6_1_EccErrCnt 0 0x80b29 1 0 1 EccErrCnt 0 15 regUMCCH6_1_PerfMonCtlClk 0 0x80b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH6_1_PerfMonCtrClk_Lo 0 0x80b41 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtrClk_Hi 0 0x80b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH6_1_PerfMonCtl1 0 0x80b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr1_Lo 0 0x80b45 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr1_Hi 0 0x80b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl2 0 0x80b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr2_Lo 0 0x80b48 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr2_Hi 0 0x80b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl3 0 0x80b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr3_Lo 0 0x80b4b 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr3_Hi 0 0x80b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl4 0 0x80b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr4_Lo 0 0x80b4e 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr4_Hi 0 0x80b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl5 0 0x80b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr5_Lo 0 0x80b51 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr5_Hi 0 0x80b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl6 0 0x80b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr6_Lo 0 0x80b54 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr6_Hi 0 0x80b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl7 0 0x80b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr7_Lo 0 0x80b57 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr7_Hi 0 0x80b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_1_PerfMonCtl8 0 0x80b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_1_PerfMonCtr8_Lo 0 0x80b5a 1 0 1 Data 0 31 regUMCCH6_1_PerfMonCtr8_Hi 0 0x80b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_BaseAddrCS0 0 0x80c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH7_1_AddrMaskCS01 0 0x80c08 1 0 1 AddrMask 1 31 regUMCCH7_1_AddrSelCS01 0 0x80c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH7_1_AddrHashBank0 0 0x80c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_AddrHashBank1 0 0x80c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_AddrHashBank2 0 0x80c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_AddrHashBank3 0 0x80c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_AddrHashBank4 0 0x80c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_AddrHashBank5 0 0x80c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_1_EccErrCntSel 0 0x80f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH7_1_EccErrCnt 0 0x80f29 1 0 1 EccErrCnt 0 15 regUMCCH7_1_PerfMonCtlClk 0 0x80f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH7_1_PerfMonCtrClk_Lo 0 0x80f41 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtrClk_Hi 0 0x80f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH7_1_PerfMonCtl1 0 0x80f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr1_Lo 0 0x80f45 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr1_Hi 0 0x80f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl2 0 0x80f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr2_Lo 0 0x80f48 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr2_Hi 0 0x80f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl3 0 0x80f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr3_Lo 0 0x80f4b 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr3_Hi 0 0x80f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl4 0 0x80f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr4_Lo 0 0x80f4e 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr4_Hi 0 0x80f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl5 0 0x80f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr5_Lo 0 0x80f51 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr5_Hi 0 0x80f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl6 0 0x80f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr6_Lo 0 0x80f54 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr6_Hi 0 0x80f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl7 0 0x80f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr7_Lo 0 0x80f57 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr7_Hi 0 0x80f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_1_PerfMonCtl8 0 0x80f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_1_PerfMonCtr8_Lo 0 0x80f5a 1 0 1 Data 0 31 regUMCCH7_1_PerfMonCtr8_Hi 0 0x80f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_BaseAddrCS0 0 0xc0000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH0_2_AddrMaskCS01 0 0xc0008 1 0 1 AddrMask 1 31 regUMCCH0_2_AddrSelCS01 0 0xc0010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH0_2_AddrHashBank0 0 0xc0032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_AddrHashBank1 0 0xc0033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_AddrHashBank2 0 0xc0034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_AddrHashBank3 0 0xc0035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_AddrHashBank4 0 0xc0036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_AddrHashBank5 0 0xc0037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_2_EccErrCntSel 0 0xc0328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH0_2_EccErrCnt 0 0xc0329 1 0 1 EccErrCnt 0 15 regUMCCH0_2_PerfMonCtlClk 0 0xc0340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH0_2_PerfMonCtrClk_Lo 0 0xc0341 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtrClk_Hi 0 0xc0342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH0_2_PerfMonCtl1 0 0xc0344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr1_Lo 0 0xc0345 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr1_Hi 0 0xc0346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl2 0 0xc0347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr2_Lo 0 0xc0348 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr2_Hi 0 0xc0349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl3 0 0xc034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr3_Lo 0 0xc034b 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr3_Hi 0 0xc034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl4 0 0xc034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr4_Lo 0 0xc034e 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr4_Hi 0 0xc034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl5 0 0xc0350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr5_Lo 0 0xc0351 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr5_Hi 0 0xc0352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl6 0 0xc0353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr6_Lo 0 0xc0354 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr6_Hi 0 0xc0355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl7 0 0xc0356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr7_Lo 0 0xc0357 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr7_Hi 0 0xc0358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_2_PerfMonCtl8 0 0xc0359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_2_PerfMonCtr8_Lo 0 0xc035a 1 0 1 Data 0 31 regUMCCH0_2_PerfMonCtr8_Hi 0 0xc035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_BaseAddrCS0 0 0xc0400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH1_2_AddrMaskCS01 0 0xc0408 1 0 1 AddrMask 1 31 regUMCCH1_2_AddrSelCS01 0 0xc0410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH1_2_AddrHashBank0 0 0xc0432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_AddrHashBank1 0 0xc0433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_AddrHashBank2 0 0xc0434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_AddrHashBank3 0 0xc0435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_AddrHashBank4 0 0xc0436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_AddrHashBank5 0 0xc0437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_2_EccErrCntSel 0 0xc0728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH1_2_EccErrCnt 0 0xc0729 1 0 1 EccErrCnt 0 15 regUMCCH1_2_PerfMonCtlClk 0 0xc0740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH1_2_PerfMonCtrClk_Lo 0 0xc0741 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtrClk_Hi 0 0xc0742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH1_2_PerfMonCtl1 0 0xc0744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr1_Lo 0 0xc0745 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr1_Hi 0 0xc0746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl2 0 0xc0747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr2_Lo 0 0xc0748 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr2_Hi 0 0xc0749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl3 0 0xc074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr3_Lo 0 0xc074b 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr3_Hi 0 0xc074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl4 0 0xc074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr4_Lo 0 0xc074e 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr4_Hi 0 0xc074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl5 0 0xc0750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr5_Lo 0 0xc0751 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr5_Hi 0 0xc0752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl6 0 0xc0753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr6_Lo 0 0xc0754 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr6_Hi 0 0xc0755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl7 0 0xc0756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr7_Lo 0 0xc0757 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr7_Hi 0 0xc0758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_2_PerfMonCtl8 0 0xc0759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_2_PerfMonCtr8_Lo 0 0xc075a 1 0 1 Data 0 31 regUMCCH1_2_PerfMonCtr8_Hi 0 0xc075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_BaseAddrCS0 0 0xc0800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH2_2_AddrMaskCS01 0 0xc0808 1 0 1 AddrMask 1 31 regUMCCH2_2_AddrSelCS01 0 0xc0810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH2_2_AddrHashBank0 0 0xc0832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_AddrHashBank1 0 0xc0833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_AddrHashBank2 0 0xc0834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_AddrHashBank3 0 0xc0835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_AddrHashBank4 0 0xc0836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_AddrHashBank5 0 0xc0837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_2_EccErrCntSel 0 0xc0b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH2_2_EccErrCnt 0 0xc0b29 1 0 1 EccErrCnt 0 15 regUMCCH2_2_PerfMonCtlClk 0 0xc0b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH2_2_PerfMonCtrClk_Lo 0 0xc0b41 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtrClk_Hi 0 0xc0b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH2_2_PerfMonCtl1 0 0xc0b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr1_Lo 0 0xc0b45 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr1_Hi 0 0xc0b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl2 0 0xc0b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr2_Lo 0 0xc0b48 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr2_Hi 0 0xc0b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl3 0 0xc0b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr3_Lo 0 0xc0b4b 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr3_Hi 0 0xc0b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl4 0 0xc0b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr4_Lo 0 0xc0b4e 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr4_Hi 0 0xc0b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl5 0 0xc0b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr5_Lo 0 0xc0b51 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr5_Hi 0 0xc0b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl6 0 0xc0b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr6_Lo 0 0xc0b54 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr6_Hi 0 0xc0b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl7 0 0xc0b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr7_Lo 0 0xc0b57 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr7_Hi 0 0xc0b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_2_PerfMonCtl8 0 0xc0b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_2_PerfMonCtr8_Lo 0 0xc0b5a 1 0 1 Data 0 31 regUMCCH2_2_PerfMonCtr8_Hi 0 0xc0b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_BaseAddrCS0 0 0xc0c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH3_2_AddrMaskCS01 0 0xc0c08 1 0 1 AddrMask 1 31 regUMCCH3_2_AddrSelCS01 0 0xc0c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH3_2_AddrHashBank0 0 0xc0c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_AddrHashBank1 0 0xc0c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_AddrHashBank2 0 0xc0c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_AddrHashBank3 0 0xc0c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_AddrHashBank4 0 0xc0c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_AddrHashBank5 0 0xc0c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_2_EccErrCntSel 0 0xc0f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH3_2_EccErrCnt 0 0xc0f29 1 0 1 EccErrCnt 0 15 regUMCCH3_2_PerfMonCtlClk 0 0xc0f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH3_2_PerfMonCtrClk_Lo 0 0xc0f41 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtrClk_Hi 0 0xc0f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH3_2_PerfMonCtl1 0 0xc0f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr1_Lo 0 0xc0f45 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr1_Hi 0 0xc0f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl2 0 0xc0f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr2_Lo 0 0xc0f48 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr2_Hi 0 0xc0f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl3 0 0xc0f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr3_Lo 0 0xc0f4b 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr3_Hi 0 0xc0f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl4 0 0xc0f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr4_Lo 0 0xc0f4e 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr4_Hi 0 0xc0f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl5 0 0xc0f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr5_Lo 0 0xc0f51 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr5_Hi 0 0xc0f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl6 0 0xc0f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr6_Lo 0 0xc0f54 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr6_Hi 0 0xc0f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl7 0 0xc0f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr7_Lo 0 0xc0f57 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr7_Hi 0 0xc0f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_2_PerfMonCtl8 0 0xc0f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_2_PerfMonCtr8_Lo 0 0xc0f5a 1 0 1 Data 0 31 regUMCCH3_2_PerfMonCtr8_Hi 0 0xc0f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_BaseAddrCS0 0 0x100000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH4_2_AddrMaskCS01 0 0x100008 1 0 1 AddrMask 1 31 regUMCCH4_2_AddrSelCS01 0 0x100010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH4_2_AddrHashBank0 0 0x100032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_AddrHashBank1 0 0x100033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_AddrHashBank2 0 0x100034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_AddrHashBank3 0 0x100035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_AddrHashBank4 0 0x100036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_AddrHashBank5 0 0x100037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_2_EccErrCntSel 0 0x100328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH4_2_EccErrCnt 0 0x100329 1 0 1 EccErrCnt 0 15 regUMCCH4_2_PerfMonCtlClk 0 0x100340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH4_2_PerfMonCtrClk_Lo 0 0x100341 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtrClk_Hi 0 0x100342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH4_2_PerfMonCtl1 0 0x100344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr1_Lo 0 0x100345 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr1_Hi 0 0x100346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl2 0 0x100347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr2_Lo 0 0x100348 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr2_Hi 0 0x100349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl3 0 0x10034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr3_Lo 0 0x10034b 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr3_Hi 0 0x10034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl4 0 0x10034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr4_Lo 0 0x10034e 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr4_Hi 0 0x10034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl5 0 0x100350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr5_Lo 0 0x100351 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr5_Hi 0 0x100352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl6 0 0x100353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr6_Lo 0 0x100354 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr6_Hi 0 0x100355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl7 0 0x100356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr7_Lo 0 0x100357 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr7_Hi 0 0x100358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_2_PerfMonCtl8 0 0x100359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_2_PerfMonCtr8_Lo 0 0x10035a 1 0 1 Data 0 31 regUMCCH4_2_PerfMonCtr8_Hi 0 0x10035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_BaseAddrCS0 0 0x100400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH5_2_AddrMaskCS01 0 0x100408 1 0 1 AddrMask 1 31 regUMCCH5_2_AddrSelCS01 0 0x100410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH5_2_AddrHashBank0 0 0x100432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_AddrHashBank1 0 0x100433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_AddrHashBank2 0 0x100434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_AddrHashBank3 0 0x100435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_AddrHashBank4 0 0x100436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_AddrHashBank5 0 0x100437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_2_EccErrCntSel 0 0x100728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH5_2_EccErrCnt 0 0x100729 1 0 1 EccErrCnt 0 15 regUMCCH5_2_PerfMonCtlClk 0 0x100740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH5_2_PerfMonCtrClk_Lo 0 0x100741 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtrClk_Hi 0 0x100742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH5_2_PerfMonCtl1 0 0x100744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr1_Lo 0 0x100745 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr1_Hi 0 0x100746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl2 0 0x100747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr2_Lo 0 0x100748 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr2_Hi 0 0x100749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl3 0 0x10074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr3_Lo 0 0x10074b 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr3_Hi 0 0x10074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl4 0 0x10074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr4_Lo 0 0x10074e 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr4_Hi 0 0x10074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl5 0 0x100750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr5_Lo 0 0x100751 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr5_Hi 0 0x100752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl6 0 0x100753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr6_Lo 0 0x100754 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr6_Hi 0 0x100755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl7 0 0x100756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr7_Lo 0 0x100757 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr7_Hi 0 0x100758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_2_PerfMonCtl8 0 0x100759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_2_PerfMonCtr8_Lo 0 0x10075a 1 0 1 Data 0 31 regUMCCH5_2_PerfMonCtr8_Hi 0 0x10075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_BaseAddrCS0 0 0x100800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH6_2_AddrMaskCS01 0 0x100808 1 0 1 AddrMask 1 31 regUMCCH6_2_AddrSelCS01 0 0x100810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH6_2_AddrHashBank0 0 0x100832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_AddrHashBank1 0 0x100833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_AddrHashBank2 0 0x100834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_AddrHashBank3 0 0x100835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_AddrHashBank4 0 0x100836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_AddrHashBank5 0 0x100837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_2_EccErrCntSel 0 0x100b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH6_2_EccErrCnt 0 0x100b29 1 0 1 EccErrCnt 0 15 regUMCCH6_2_PerfMonCtlClk 0 0x100b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH6_2_PerfMonCtrClk_Lo 0 0x100b41 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtrClk_Hi 0 0x100b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH6_2_PerfMonCtl1 0 0x100b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr1_Lo 0 0x100b45 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr1_Hi 0 0x100b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl2 0 0x100b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr2_Lo 0 0x100b48 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr2_Hi 0 0x100b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl3 0 0x100b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr3_Lo 0 0x100b4b 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr3_Hi 0 0x100b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl4 0 0x100b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr4_Lo 0 0x100b4e 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr4_Hi 0 0x100b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl5 0 0x100b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr5_Lo 0 0x100b51 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr5_Hi 0 0x100b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl6 0 0x100b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr6_Lo 0 0x100b54 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr6_Hi 0 0x100b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl7 0 0x100b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr7_Lo 0 0x100b57 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr7_Hi 0 0x100b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_2_PerfMonCtl8 0 0x100b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_2_PerfMonCtr8_Lo 0 0x100b5a 1 0 1 Data 0 31 regUMCCH6_2_PerfMonCtr8_Hi 0 0x100b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_BaseAddrCS0 0 0x100c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH7_2_AddrMaskCS01 0 0x100c08 1 0 1 AddrMask 1 31 regUMCCH7_2_AddrSelCS01 0 0x100c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH7_2_AddrHashBank0 0 0x100c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_AddrHashBank1 0 0x100c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_AddrHashBank2 0 0x100c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_AddrHashBank3 0 0x100c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_AddrHashBank4 0 0x100c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_AddrHashBank5 0 0x100c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_2_EccErrCntSel 0 0x100f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH7_2_EccErrCnt 0 0x100f29 1 0 1 EccErrCnt 0 15 regUMCCH7_2_PerfMonCtlClk 0 0x100f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH7_2_PerfMonCtrClk_Lo 0 0x100f41 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtrClk_Hi 0 0x100f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH7_2_PerfMonCtl1 0 0x100f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr1_Lo 0 0x100f45 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr1_Hi 0 0x100f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl2 0 0x100f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr2_Lo 0 0x100f48 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr2_Hi 0 0x100f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl3 0 0x100f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr3_Lo 0 0x100f4b 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr3_Hi 0 0x100f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl4 0 0x100f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr4_Lo 0 0x100f4e 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr4_Hi 0 0x100f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl5 0 0x100f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr5_Lo 0 0x100f51 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr5_Hi 0 0x100f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl6 0 0x100f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr6_Lo 0 0x100f54 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr6_Hi 0 0x100f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl7 0 0x100f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr7_Lo 0 0x100f57 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr7_Hi 0 0x100f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_2_PerfMonCtl8 0 0x100f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_2_PerfMonCtr8_Lo 0 0x100f5a 1 0 1 Data 0 31 regUMCCH7_2_PerfMonCtr8_Hi 0 0x100f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_BaseAddrCS0 0 0x140000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH0_3_AddrMaskCS01 0 0x140008 1 0 1 AddrMask 1 31 regUMCCH0_3_AddrSelCS01 0 0x140010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH0_3_AddrHashBank0 0 0x140032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_AddrHashBank1 0 0x140033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_AddrHashBank2 0 0x140034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_AddrHashBank3 0 0x140035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_AddrHashBank4 0 0x140036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_AddrHashBank5 0 0x140037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH0_3_EccErrCntSel 0 0x140328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH0_3_EccErrCnt 0 0x140329 1 0 1 EccErrCnt 0 15 regUMCCH0_3_PerfMonCtlClk 0 0x140340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH0_3_PerfMonCtrClk_Lo 0 0x140341 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtrClk_Hi 0 0x140342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH0_3_PerfMonCtl1 0 0x140344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr1_Lo 0 0x140345 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr1_Hi 0 0x140346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl2 0 0x140347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr2_Lo 0 0x140348 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr2_Hi 0 0x140349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl3 0 0x14034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr3_Lo 0 0x14034b 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr3_Hi 0 0x14034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl4 0 0x14034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr4_Lo 0 0x14034e 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr4_Hi 0 0x14034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl5 0 0x140350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr5_Lo 0 0x140351 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr5_Hi 0 0x140352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl6 0 0x140353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr6_Lo 0 0x140354 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr6_Hi 0 0x140355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl7 0 0x140356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr7_Lo 0 0x140357 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr7_Hi 0 0x140358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH0_3_PerfMonCtl8 0 0x140359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH0_3_PerfMonCtr8_Lo 0 0x14035a 1 0 1 Data 0 31 regUMCCH0_3_PerfMonCtr8_Hi 0 0x14035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_BaseAddrCS0 0 0x140400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH1_3_AddrMaskCS01 0 0x140408 1 0 1 AddrMask 1 31 regUMCCH1_3_AddrSelCS01 0 0x140410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH1_3_AddrHashBank0 0 0x140432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_AddrHashBank1 0 0x140433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_AddrHashBank2 0 0x140434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_AddrHashBank3 0 0x140435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_AddrHashBank4 0 0x140436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_AddrHashBank5 0 0x140437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH1_3_EccErrCntSel 0 0x140728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH1_3_EccErrCnt 0 0x140729 1 0 1 EccErrCnt 0 15 regUMCCH1_3_PerfMonCtlClk 0 0x140740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH1_3_PerfMonCtrClk_Lo 0 0x140741 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtrClk_Hi 0 0x140742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH1_3_PerfMonCtl1 0 0x140744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr1_Lo 0 0x140745 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr1_Hi 0 0x140746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl2 0 0x140747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr2_Lo 0 0x140748 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr2_Hi 0 0x140749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl3 0 0x14074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr3_Lo 0 0x14074b 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr3_Hi 0 0x14074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl4 0 0x14074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr4_Lo 0 0x14074e 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr4_Hi 0 0x14074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl5 0 0x140750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr5_Lo 0 0x140751 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr5_Hi 0 0x140752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl6 0 0x140753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr6_Lo 0 0x140754 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr6_Hi 0 0x140755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl7 0 0x140756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr7_Lo 0 0x140757 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr7_Hi 0 0x140758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH1_3_PerfMonCtl8 0 0x140759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH1_3_PerfMonCtr8_Lo 0 0x14075a 1 0 1 Data 0 31 regUMCCH1_3_PerfMonCtr8_Hi 0 0x14075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_BaseAddrCS0 0 0x140800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH2_3_AddrMaskCS01 0 0x140808 1 0 1 AddrMask 1 31 regUMCCH2_3_AddrSelCS01 0 0x140810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH2_3_AddrHashBank0 0 0x140832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_AddrHashBank1 0 0x140833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_AddrHashBank2 0 0x140834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_AddrHashBank3 0 0x140835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_AddrHashBank4 0 0x140836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_AddrHashBank5 0 0x140837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH2_3_EccErrCntSel 0 0x140b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH2_3_EccErrCnt 0 0x140b29 1 0 1 EccErrCnt 0 15 regUMCCH2_3_PerfMonCtlClk 0 0x140b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH2_3_PerfMonCtrClk_Lo 0 0x140b41 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtrClk_Hi 0 0x140b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH2_3_PerfMonCtl1 0 0x140b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr1_Lo 0 0x140b45 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr1_Hi 0 0x140b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl2 0 0x140b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr2_Lo 0 0x140b48 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr2_Hi 0 0x140b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl3 0 0x140b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr3_Lo 0 0x140b4b 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr3_Hi 0 0x140b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl4 0 0x140b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr4_Lo 0 0x140b4e 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr4_Hi 0 0x140b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl5 0 0x140b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr5_Lo 0 0x140b51 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr5_Hi 0 0x140b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl6 0 0x140b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr6_Lo 0 0x140b54 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr6_Hi 0 0x140b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl7 0 0x140b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr7_Lo 0 0x140b57 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr7_Hi 0 0x140b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH2_3_PerfMonCtl8 0 0x140b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH2_3_PerfMonCtr8_Lo 0 0x140b5a 1 0 1 Data 0 31 regUMCCH2_3_PerfMonCtr8_Hi 0 0x140b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_BaseAddrCS0 0 0x140c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH3_3_AddrMaskCS01 0 0x140c08 1 0 1 AddrMask 1 31 regUMCCH3_3_AddrSelCS01 0 0x140c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH3_3_AddrHashBank0 0 0x140c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_AddrHashBank1 0 0x140c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_AddrHashBank2 0 0x140c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_AddrHashBank3 0 0x140c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_AddrHashBank4 0 0x140c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_AddrHashBank5 0 0x140c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH3_3_EccErrCntSel 0 0x140f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH3_3_EccErrCnt 0 0x140f29 1 0 1 EccErrCnt 0 15 regUMCCH3_3_PerfMonCtlClk 0 0x140f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH3_3_PerfMonCtrClk_Lo 0 0x140f41 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtrClk_Hi 0 0x140f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH3_3_PerfMonCtl1 0 0x140f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr1_Lo 0 0x140f45 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr1_Hi 0 0x140f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl2 0 0x140f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr2_Lo 0 0x140f48 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr2_Hi 0 0x140f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl3 0 0x140f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr3_Lo 0 0x140f4b 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr3_Hi 0 0x140f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl4 0 0x140f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr4_Lo 0 0x140f4e 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr4_Hi 0 0x140f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl5 0 0x140f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr5_Lo 0 0x140f51 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr5_Hi 0 0x140f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl6 0 0x140f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr6_Lo 0 0x140f54 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr6_Hi 0 0x140f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl7 0 0x140f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr7_Lo 0 0x140f57 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr7_Hi 0 0x140f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH3_3_PerfMonCtl8 0 0x140f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH3_3_PerfMonCtr8_Lo 0 0x140f5a 1 0 1 Data 0 31 regUMCCH3_3_PerfMonCtr8_Hi 0 0x140f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_BaseAddrCS0 0 0x180000 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH4_3_AddrMaskCS01 0 0x180008 1 0 1 AddrMask 1 31 regUMCCH4_3_AddrSelCS01 0 0x180010 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH4_3_AddrHashBank0 0 0x180032 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_AddrHashBank1 0 0x180033 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_AddrHashBank2 0 0x180034 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_AddrHashBank3 0 0x180035 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_AddrHashBank4 0 0x180036 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_AddrHashBank5 0 0x180037 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH4_3_EccErrCntSel 0 0x180328 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH4_3_EccErrCnt 0 0x180329 1 0 1 EccErrCnt 0 15 regUMCCH4_3_PerfMonCtlClk 0 0x180340 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH4_3_PerfMonCtrClk_Lo 0 0x180341 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtrClk_Hi 0 0x180342 2 0 1 Data 0 15 Overflow 16 16 regUMCCH4_3_PerfMonCtl1 0 0x180344 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr1_Lo 0 0x180345 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr1_Hi 0 0x180346 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl2 0 0x180347 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr2_Lo 0 0x180348 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr2_Hi 0 0x180349 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl3 0 0x18034a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr3_Lo 0 0x18034b 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr3_Hi 0 0x18034c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl4 0 0x18034d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr4_Lo 0 0x18034e 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr4_Hi 0 0x18034f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl5 0 0x180350 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr5_Lo 0 0x180351 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr5_Hi 0 0x180352 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl6 0 0x180353 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr6_Lo 0 0x180354 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr6_Hi 0 0x180355 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl7 0 0x180356 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr7_Lo 0 0x180357 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr7_Hi 0 0x180358 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH4_3_PerfMonCtl8 0 0x180359 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH4_3_PerfMonCtr8_Lo 0 0x18035a 1 0 1 Data 0 31 regUMCCH4_3_PerfMonCtr8_Hi 0 0x18035b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_BaseAddrCS0 0 0x180400 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH5_3_AddrMaskCS01 0 0x180408 1 0 1 AddrMask 1 31 regUMCCH5_3_AddrSelCS01 0 0x180410 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH5_3_AddrHashBank0 0 0x180432 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_AddrHashBank1 0 0x180433 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_AddrHashBank2 0 0x180434 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_AddrHashBank3 0 0x180435 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_AddrHashBank4 0 0x180436 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_AddrHashBank5 0 0x180437 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH5_3_EccErrCntSel 0 0x180728 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH5_3_EccErrCnt 0 0x180729 1 0 1 EccErrCnt 0 15 regUMCCH5_3_PerfMonCtlClk 0 0x180740 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH5_3_PerfMonCtrClk_Lo 0 0x180741 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtrClk_Hi 0 0x180742 2 0 1 Data 0 15 Overflow 16 16 regUMCCH5_3_PerfMonCtl1 0 0x180744 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr1_Lo 0 0x180745 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr1_Hi 0 0x180746 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl2 0 0x180747 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr2_Lo 0 0x180748 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr2_Hi 0 0x180749 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl3 0 0x18074a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr3_Lo 0 0x18074b 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr3_Hi 0 0x18074c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl4 0 0x18074d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr4_Lo 0 0x18074e 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr4_Hi 0 0x18074f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl5 0 0x180750 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr5_Lo 0 0x180751 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr5_Hi 0 0x180752 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl6 0 0x180753 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr6_Lo 0 0x180754 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr6_Hi 0 0x180755 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl7 0 0x180756 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr7_Lo 0 0x180757 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr7_Hi 0 0x180758 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH5_3_PerfMonCtl8 0 0x180759 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH5_3_PerfMonCtr8_Lo 0 0x18075a 1 0 1 Data 0 31 regUMCCH5_3_PerfMonCtr8_Hi 0 0x18075b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_BaseAddrCS0 0 0x180800 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH6_3_AddrMaskCS01 0 0x180808 1 0 1 AddrMask 1 31 regUMCCH6_3_AddrSelCS01 0 0x180810 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH6_3_AddrHashBank0 0 0x180832 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_AddrHashBank1 0 0x180833 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_AddrHashBank2 0 0x180834 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_AddrHashBank3 0 0x180835 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_AddrHashBank4 0 0x180836 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_AddrHashBank5 0 0x180837 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH6_3_EccErrCntSel 0 0x180b28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH6_3_EccErrCnt 0 0x180b29 1 0 1 EccErrCnt 0 15 regUMCCH6_3_PerfMonCtlClk 0 0x180b40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH6_3_PerfMonCtrClk_Lo 0 0x180b41 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtrClk_Hi 0 0x180b42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH6_3_PerfMonCtl1 0 0x180b44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr1_Lo 0 0x180b45 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr1_Hi 0 0x180b46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl2 0 0x180b47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr2_Lo 0 0x180b48 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr2_Hi 0 0x180b49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl3 0 0x180b4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr3_Lo 0 0x180b4b 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr3_Hi 0 0x180b4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl4 0 0x180b4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr4_Lo 0 0x180b4e 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr4_Hi 0 0x180b4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl5 0 0x180b50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr5_Lo 0 0x180b51 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr5_Hi 0 0x180b52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl6 0 0x180b53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr6_Lo 0 0x180b54 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr6_Hi 0 0x180b55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl7 0 0x180b56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr7_Lo 0 0x180b57 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr7_Hi 0 0x180b58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH6_3_PerfMonCtl8 0 0x180b59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH6_3_PerfMonCtr8_Lo 0 0x180b5a 1 0 1 Data 0 31 regUMCCH6_3_PerfMonCtr8_Hi 0 0x180b5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_BaseAddrCS0 0 0x180c00 2 0 1 CSEnable 0 0 BaseAddr 1 31 regUMCCH7_3_AddrMaskCS01 0 0x180c08 1 0 1 AddrMask 1 31 regUMCCH7_3_AddrSelCS01 0 0x180c10 7 0 1 BankBit0 0 3 BankBit1 4 7 BankBit2 8 11 BankBit3 12 15 BankBit4 16 20 RowLo 24 27 RowHi 28 31 regUMCCH7_3_AddrHashBank0 0 0x180c32 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_AddrHashBank1 0 0x180c33 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_AddrHashBank2 0 0x180c34 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_AddrHashBank3 0 0x180c35 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_AddrHashBank4 0 0x180c36 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_AddrHashBank5 0 0x180c37 3 0 1 XorEnable 0 0 ColXor 1 13 RowXor 14 31 regUMCCH7_3_EccErrCntSel 0 0x180f28 3 0 1 EccErrCntCsSel 0 3 EccErrInt 12 13 EccErrCntEn 15 15 regUMCCH7_3_EccErrCnt 0 0x180f29 1 0 1 EccErrCnt 0 15 regUMCCH7_3_PerfMonCtlClk 0 0x180f40 6 0 1 GlblResetMsk 0 8 ClkGate 22 22 GlblReset 24 24 GlblMonEn 25 25 NumCounters 26 29 CtrClkEn 31 31 regUMCCH7_3_PerfMonCtrClk_Lo 0 0x180f41 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtrClk_Hi 0 0x180f42 2 0 1 Data 0 15 Overflow 16 16 regUMCCH7_3_PerfMonCtl1 0 0x180f44 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr1_Lo 0 0x180f45 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr1_Hi 0 0x180f46 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl2 0 0x180f47 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr2_Lo 0 0x180f48 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr2_Hi 0 0x180f49 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl3 0 0x180f4a 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr3_Lo 0 0x180f4b 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr3_Hi 0 0x180f4c 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl4 0 0x180f4d 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr4_Lo 0 0x180f4e 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr4_Hi 0 0x180f4f 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl5 0 0x180f50 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr5_Lo 0 0x180f51 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr5_Hi 0 0x180f52 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl6 0 0x180f53 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr6_Lo 0 0x180f54 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr6_Hi 0 0x180f55 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl7 0 0x180f56 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr7_Lo 0 0x180f57 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr7_Hi 0 0x180f58 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31 regUMCCH7_3_PerfMonCtl8 0 0x180f59 8 0 1 EventSelect 0 7 RdWrMask 8 9 PriorityMask 10 13 ReqSizeMask 14 15 BankSel 16 23 VCSel 24 28 SubChanMask 29 30 Enable 31 31 regUMCCH7_3_PerfMonCtr8_Lo 0 0x180f5a 1 0 1 Data 0 31 regUMCCH7_3_PerfMonCtr8_Hi 0 0x180f5b 4 0 1 Data 0 15 Overflow 16 16 ThreshCntEn 18 19 ThreshCnt 20 31