69 ixUVD_CGC_CTRL2 2 0xc1 3 0 4294967295 DYN_OCLK_RAMP_EN 0 0 DYN_RCLK_RAMP_EN 1 1 GATER_DIV_ID 2 4 ixUVD_CGC_MEM_CTRL 2 0xc0 16 0 4294967295 LCM_LS_EN 13 13 LMI_MC_LS_EN 0 0 LS_CLEAR_DELAY 20 23 LS_SET_DELAY 16 19 MIF_LS_EN 12 12 MPC_LS_EN 1 1 MPRD_LS_EN 2 2 SCPU_LS_EN 11 11 SYS_LS_EN 9 9 UDEC_CM_LS_EN 5 5 UDEC_DB_LS_EN 7 7 UDEC_IT_LS_EN 6 6 UDEC_MP_LS_EN 8 8 UDEC_RE_LS_EN 4 4 VCPU_LS_EN 10 10 WCB_LS_EN 3 3 ixUVD_LMI_ADDR_EXT2 2 0xab 4 0 4294967295 SCPU_ADDR_EXT 0 3 SCPU_NC0_ADDR_EXT 8 11 SCPU_NC1_ADDR_EXT 12 15 SCPU_VM_ADDR_EXT 4 7 ixUVD_LMI_CACHE_CTRL 2 0x9b 6 0 4294967295 CM_EN 2 2 CM_FLUSH 3 3 IT_EN 0 0 IT_FLUSH 1 1 VCPU_EN 4 4 VCPU_FLUSH 5 5 ixUVD_LMI_SWAP_CNTL2 2 0xaa 2 0 4294967295 SCPU_R_MC_SWAP 0 1 SCPU_W_MC_SWAP 2 3 ixUVD_MIF_CURR_ADDR_CONFIG 2 0x48 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 ixUVD_MIF_RECON1_ADDR_CONFIG 2 0x114 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 ixUVD_MIF_REF_ADDR_CONFIG 2 0x4c 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmUVD_CGC_CTRL 0 0x3d2c 23 0 4294967295 CLK_GATE_DLY_TIMER 2 5 CLK_OFF_DELAY 6 10 DYN_CLOCK_MODE 0 0 IDCT_MODE 23 23 LBSI_MODE 26 26 LMI_MC_MODE 21 21 LMI_UMC_MODE 22 22 LRBBM_MODE 27 27 MPC_MODE 25 25 MPEG2_MODE 18 18 MPRD_MODE 24 24 RBC_MODE 20 20 REGS_MODE 19 19 SCPU_MODE 30 30 SYS_MODE 16 16 UDEC_CM_MODE 12 12 UDEC_DB_MODE 14 14 UDEC_IT_MODE 13 13 UDEC_MODE 17 17 UDEC_MP_MODE 15 15 UDEC_RE_MODE 11 11 VCPU_MODE 29 29 WCB_MODE 28 28 mmUVD_CGC_GATE 0 0x3d2a 20 0 4294967295 IDCT 7 7 LBSI 10 10 LMI_MC 5 5 LMI_UMC 6 6 LRBBM 11 11 MPC 9 9 MPEG2 2 2 MPRD 8 8 RBC 4 4 REGS 3 3 SCPU 19 19 SYS 0 0 UDEC_CM 13 13 UDEC_DB 15 15 UDEC_IT 14 14 UDEC 1 1 UDEC_MP 16 16 UDEC_RE 12 12 VCPU 18 18 WCB 17 17 mmUVD_CGC_STATUS 0 0x3d2b 29 0 4294967295 IDCT_SCLK 14 14 IDCT_VCLK 15 15 LBSI_SCLK 21 21 LBSI_VCLK 22 22 LMI_MC_SCLK 12 12 LMI_UMC_SCLK 13 13 LRBBM_SCLK 23 23 MPC_DCLK 20 20 MPC_SCLK 19 19 MPEG2_DCLK 7 7 MPEG2_SCLK 6 6 MPEG2_VCLK 8 8 MPRD_DCLK 17 17 MPRD_SCLK 16 16 MPRD_VCLK 18 18 RBC_SCLK 11 11 REGS_SCLK 9 9 REGS_VCLK 10 10 SCPU_SCLK 27 27 SCPU_VCLK 28 28 SYS_DCLK 1 1 SYS_SCLK 0 0 SYS_VCLK 2 2 UDEC_DCLK 4 4 UDEC_SCLK 3 3 UDEC_VCLK 5 5 VCPU_SCLK 25 25 VCPU_VCLK 26 26 WCB_SCLK 24 24 mmUVD_CGC_UDEC_STATUS 0 0x3d2d 15 0 4294967295 CM_DCLK 4 4 CM_SCLK 3 3 CM_VCLK 5 5 DB_DCLK 10 10 DB_SCLK 9 9 DB_VCLK 11 11 IT_DCLK 7 7 IT_SCLK 6 6 IT_VCLK 8 8 MP_DCLK 13 13 MP_SCLK 12 12 MP_VCLK 14 14 RE_DCLK 1 1 RE_SCLK 0 0 RE_VCLK 2 2 mmUVD_CONTEXT_ID 0 0x3dbd 1 0 4294967295 CONTEXT_ID 0 31 mmUVD_CTX_DATA 0 0x3d29 1 0 4294967295 DATA 0 31 mmUVD_CTX_INDEX 0 0x3d28 1 0 4294967295 INDEX 0 8 mmUVD_ENGINE_CNTL 0 0x3bc6 2 0 4294967295 ENGINE_START 0 0 ENGINE_START_MODE 1 1 mmUVD_GPCOM_VCPU_CMD 0 0x3bc3 3 0 4294967295 CMD 1 30 CMD_SEND 0 0 CMD_SOURCE 31 31 mmUVD_GPCOM_VCPU_DATA0 0 0x3bc4 1 0 4294967295 DATA0 0 31 mmUVD_GPCOM_VCPU_DATA1 0 0x3bc5 1 0 4294967295 DATA1 0 31 mmUVD_GP_SCRATCH4 0 0x3d38 0 0 4294967295 mmUVD_LMI_ADDR_EXT 0 0x3d65 8 0 4294967295 CM_ADDR_EXT 4 7 IT_ADDR_EXT 8 11 MP_ADDR_EXT 20 23 RE_ADDR_EXT 16 19 VCPU_ADDR_EXT 0 3 VCPU_NC0_ADDR_EXT 24 27 VCPU_NC1_ADDR_EXT 28 31 VCPU_VM_ADDR_EXT 12 15 mmUVD_LMI_CTRL 0 0x3d66 16 0 4294967295 ASSERT_MC_URGENT 11 11 CM_DATA_COHERENCY_EN 22 22 CRC_RESET 14 14 CRC_SEL 15 19 DATA_COHERENCY_EN 13 13 DB_DB_DATA_COHERENCY_EN 23 23 DB_IT_DATA_COHERENCY_EN 24 24 DISABLE_ON_FWV_FAIL 20 20 IT_IT_DATA_COHERENCY_EN 25 25 MASK_MC_URGENT 12 12 MIF_MIF_DATA_COHERENCY_EN 26 26 REQ_MODE 9 9 RFU 26 31 VCPU_DATA_COHERENCY_EN 21 21 WRITE_CLEAN_TIMER_EN 8 8 WRITE_CLEAN_TIMER 0 7 mmUVD_LMI_CTRL2 0 0x3d3d 12 0 4294967295 ASSERT_UMC_URGENT 2 2 DRCITF_BUBBLE_FIX_DIS 7 7 MASK_UMC_URGENT 3 3 MCIF_WR_WATERMARK 4 6 MC_READ_ID_SEL 9 10 MC_WRITE_ID_SEL 11 12 SPH_DIS 0 0 SPU_EXTRA_CID_EN 15 15 STALL_ARB 1 1 STALL_ARB_UMC 8 8 VCPU_NC0_EXT_EN 13 13 VCPU_NC1_EXT_EN 14 14 mmUVD_LMI_EXT40_ADDR 0 0x3d26 3 0 4294967295 ADDR 0 7 INDEX 16 20 WRITE_ADDR 31 31 mmUVD_LMI_STATUS 0 0x3d67 14 0 4294967295 ADP_MC_READ_CLEAN 12 12 ADP_UMC_READ_CLEAN 13 13 PENDING_UVD_MC_WRITE 7 7 READ_CLEAN 0 0 READ_CLEAN_RAW 8 8 UMC_AVP_IDLE 11 11 UMC_READ_CLEAN 4 4 UMC_READ_CLEAN_RAW 9 9 UMC_UVD_IDLE 10 10 UMC_WRITE_CLEAN 5 5 UMC_WRITE_CLEAN_RAW 6 6 VCPU_LMI_WRITE_CLEAN 3 3 WRITE_CLEAN 1 1 WRITE_CLEAN_RAW 2 2 mmUVD_LMI_SWAP_CNTL 0 0x3d6d 15 0 4294967295 CM_MC_SWAP 10 11 CSM_MC_SWAP 18 19 DB_R_MC_SWAP 14 15 DB_W_MC_SWAP 16 17 DBW_MC_SWAP 24 25 IB_MC_SWAP 2 3 IT_MC_SWAP 12 13 MP_MC_SWAP 30 31 MP_REF16_MC_SWAP 22 23 RB_MC_SWAP 0 1 RB_RPTR_MC_SWAP 4 5 RB_WR_MC_SWAP 26 27 RE_MC_SWAP 28 29 VCPU_R_MC_SWAP 6 7 VCPU_W_MC_SWAP 8 9 mmUVD_MASTINT_EN 0 0x3d40 4 0 4294967295 INT_OVERRUN 4 22 OVERRUN_RST 0 0 SYS_EN 2 2 VCPU_EN 1 1 mmUVD_MPC_CNTL 0 0x3d77 5 0 4294967295 AVE_WEIGHT 16 17 DBG_MUX 8 10 PERF_RST 6 6 REPLACEMENT_MODE 3 5 URGENT_EN 18 18 mmUVD_MPC_SET_ALU 0 0x3d7e 2 0 4294967295 FUNCT 0 2 OPERAND 4 11 mmUVD_MPC_SET_MUX 0 0x3d7d 3 0 4294967295 SET_0 0 2 SET_1 3 5 SET_2 6 8 mmUVD_MPC_SET_MUXA0 0 0x3d79 5 0 4294967295 VARA_0 0 5 VARA_1 6 11 VARA_2 12 17 VARA_3 18 23 VARA_4 24 29 mmUVD_MPC_SET_MUXA1 0 0x3d7a 3 0 4294967295 VARA_5 0 5 VARA_6 6 11 VARA_7 12 17 mmUVD_MPC_SET_MUXB0 0 0x3d7b 5 0 4294967295 VARB_0 0 5 VARB_1 6 11 VARB_2 12 17 VARB_3 18 23 VARB_4 24 29 mmUVD_MPC_SET_MUXB1 0 0x3d7c 3 0 4294967295 VARB_5 0 5 VARB_6 6 11 VARB_7 12 17 mmUVD_MP_SWAP_CNTL 0 0x3d6f 16 0 4294967295 MP_REF0_MC_SWAP 0 1 MP_REF10_MC_SWAP 20 21 MP_REF11_MC_SWAP 22 23 MP_REF12_MC_SWAP 24 25 MP_REF13_MC_SWAP 26 27 MP_REF14_MC_SWAP 28 29 MP_REF15_MC_SWAP 30 31 MP_REF1_MC_SWAP 2 3 MP_REF2_MC_SWAP 4 5 MP_REF3_MC_SWAP 6 7 MP_REF4_MC_SWAP 8 9 MP_REF5_MC_SWAP 10 11 MP_REF6_MC_SWAP 12 13 MP_REF7_MC_SWAP 14 15 MP_REF8_MC_SWAP 16 17 MP_REF9_MC_SWAP 18 19 mmUVD_NO_OP 0 0x3bff 0 0 4294967295 mmUVD_PGFSM_CONFIG 0 0x38f8 8 0 4294967295 UVD_PGFSM_FSM_ADDR 0 7 UVD_PGFSM_P1_SELECT 10 10 UVD_PGFSM_P2_SELECT 11 11 UVD_PGFSM_POWER_DOWN 8 8 UVD_PGFSM_POWER_UP 9 9 UVD_PGFSM_READ 13 13 UVD_PGFSM_REG_ADDR 28 31 UVD_PGFSM_WRITE 12 12 mmUVD_PGFSM_READ_TILE1 0 0x38fa 1 0 4294967295 UVD_PGFSM_READ_TILE1_VALUE 0 23 mmUVD_PGFSM_READ_TILE2 0 0x38fb 1 0 4294967295 UVD_PGFSM_READ_TILE2_VALUE 0 23 mmUVD_POWER_STATUS 0 0x38fc 1 0 4294967295 UVD_POWER_STATUS 0 0 mmUVD_RBC_IB_BASE 0 0x3da1 1 0 4294967295 IB_BASE 6 31 mmUVD_RBC_IB_SIZE 0 0x3da2 1 0 4294967295 IB_SIZE 4 22 mmUVD_RBC_IB_SIZE_UPDATE 0 0x3df1 0 0 4294967295 mmUVD_RBC_RB_BASE 0 0x3da3 1 0 4294967295 RB_BASE 6 31 mmUVD_RBC_RB_CNTL 0 0x3da9 6 0 4294967295 RB_BLKSZ 8 12 RB_BUFSZ 0 4 RB_NO_FETCH 16 16 RB_NO_UPDATE 24 24 RB_RPTR_WR_EN 28 28 RB_WPTR_POLL_EN 20 20 mmUVD_RBC_RB_RPTR 0 0x3da4 1 0 4294967295 RB_RPTR 4 22 mmUVD_RBC_RB_RPTR_ADDR 0 0x3daa 1 0 4294967295 RB_RPTR_ADDR 0 31 mmUVD_RBC_RB_WPTR 0 0x3da5 1 0 4294967295 RB_WPTR 4 22 mmUVD_RBC_RB_WPTR_CNTL 0 0x3da6 0 0 4294967295 mmUVD_SEMA_ADDR_HIGH 0 0x3bc1 1 0 4294967295 ADDR_42_23 0 19 mmUVD_SEMA_ADDR_LOW 0 0x3bc0 1 0 4294967295 ADDR_22_3 0 19 mmUVD_SEMA_CMD 0 0x3bc2 5 0 4294967295 MODE 6 6 REQ_CMD 0 3 VMID_EN 7 7 VMID 8 11 WR_PHASE 4 5 mmUVD_SEMA_CNTL 0 0x3d00 2 0 4294967295 ADVANCED_MODE_DIS 1 1 SEMAPHORE_EN 0 0 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0 0x3db3 3 0 4294967295 RESEND_TIMER 24 26 SIGNAL_INCOMPLETE_COUNT 1 20 SIGNAL_INCOMPLETE_EN 0 0 mmUVD_SEMA_TIMEOUT_STATUS 0 0x3db0 4 0 4294967295 SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT 2 2 SEMAPHORE_TIMEOUT_CLEAR 3 3 SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT 1 1 SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT 0 0 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0 0x3db2 3 0 4294967295 RESEND_TIMER 24 26 WAIT_FAULT_COUNT 1 20 WAIT_FAULT_EN 0 0 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0 0x3db1 3 0 4294967295 RESEND_TIMER 24 26 WAIT_INCOMPLETE_COUNT 1 20 WAIT_INCOMPLETE_EN 0 0 mmUVD_SOFT_RESET 0 0x3da0 17 0 4294967295 CSM_SOFT_RESET 5 5 CXW_SOFT_RESET 6 6 FWV_SOFT_RESET 9 9 IDCT_SOFT_RESET 12 12 IH_SOFT_RESET 10 10 LBSI_SOFT_RESET 1 1 LCM_SOFT_RESET 16 16 LMI_SOFT_RESET 2 2 LMI_UMC_SOFT_RESET 13 13 MIF_SOFT_RESET 15 15 MPC_SOFT_RESET 8 8 MPRD_SOFT_RESET 11 11 RBC_SOFT_RESET 0 0 SPH_SOFT_RESET 14 14 TAP_SOFT_RESET 7 7 UDEC_SOFT_RESET 4 4 VCPU_SOFT_RESET 3 3 mmUVD_STATUS 0 0x3daf 2 0 4294967295 RBC_BUSY 0 0 VCPU_REPORT 1 7 mmUVD_UDEC_ADDR_CONFIG 0 0x3bd3 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmUVD_UDEC_DB_ADDR_CONFIG 0 0x3bd4 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmUVD_UDEC_DBW_ADDR_CONFIG 0 0x3bd5 9 0 4294967295 BANK_INTERLEAVE_SIZE 8 10 MULTI_GPU_TILE_SIZE 24 25 NUM_GPUS 20 22 NUM_LOWER_PIPES 30 30 NUM_PIPES 0 2 NUM_SHADER_ENGINES 12 13 PIPE_INTERLEAVE_SIZE 4 6 ROW_SIZE 28 29 SHADER_ENGINE_TILE_SIZE 16 18 mmUVD_VCPU_CACHE_OFFSET0 0 0x3d36 1 0 4294967295 CACHE_OFFSET0 0 24 mmUVD_VCPU_CACHE_OFFSET1 0 0x3d38 1 0 4294967295 CACHE_OFFSET1 0 24 mmUVD_VCPU_CACHE_OFFSET2 0 0x3d3a 1 0 4294967295 CACHE_OFFSET2 0 24 mmUVD_VCPU_CACHE_SIZE0 0 0x3d37 1 0 4294967295 CACHE_SIZE0 0 20 mmUVD_VCPU_CACHE_SIZE1 0 0x3d39 1 0 4294967295 CACHE_SIZE1 0 20 mmUVD_VCPU_CACHE_SIZE2 0 0x3d3b 1 0 4294967295 CACHE_SIZE2 0 20 mmUVD_VCPU_CNTL 0 0x3d98 17 0 4294967295 ABORT_REQ 8 8 AXI_MAX_BRST_SIZE_IS_4 4 4 CABAC_MB_ACC 28 28 CLK_ACTIVE 17 17 CLK_EN 9 9 DBG_MUX 13 15 ECPU_AM32_EN 29 29 IRQ_ERR 0 3 JTAG_EN 16 16 PMB_ED_ENABLE 5 5 PMB_SOFT_RESET 6 6 PRB_TIMEOUT_VAL 20 27 RBBM_SOFT_RESET 7 7 TIMEOUT_DIS 18 18 TRCE_EN 10 10 TRCE_MUX 11 12 WMV9_EN 30 30