93 mmUVD_POWER_STATUS 0 0xc4 9 0 1 UVD_POWER_STATUS 0 1 UVD_PG_MODE 2 2 UVD_STATUS_CHECK_TIMEOUT 3 3 PWR_ON_CHECK_TIMEOUT 4 4 PWR_OFF_CHECK_TIMEOUT 5 5 UVD_PGFSM_TIMEOUT_MODE 6 7 UVD_PG_EN 8 8 PAUSE_DPG_REQ 9 9 PAUSE_DPG_ACK 10 10 mmUVD_DPG_RBC_RB_CNTL 0 0xcb 6 0 1 RB_BUFSZ 0 4 RB_BLKSZ 8 12 RB_NO_FETCH 16 16 RB_WPTR_POLL_EN 20 20 RB_NO_UPDATE 24 24 RB_RPTR_WR_EN 28 28 mmUVD_DPG_RBC_RB_BASE_LOW 0 0xcc 1 0 1 RB_BASE_LOW 0 31 mmUVD_DPG_RBC_RB_BASE_HIGH 0 0xcd 1 0 1 RB_BASE_HIGH 0 31 mmUVD_DPG_RBC_RB_WPTR_CNTL 0 0xce 1 0 1 RB_PRE_WRITE_TIMER 0 14 mmUVD_DPG_RBC_RB_RPTR 0 0xcf 1 0 1 RB_RPTR 4 22 mmUVD_DPG_RBC_RB_WPTR 0 0xd0 1 0 1 RB_WPTR 4 22 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0xe5 1 0 1 BITS_31_0 0 31 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0xe6 1 0 1 BITS_63_32 0 31 mmUVD_DPG_VCPU_CACHE_OFFSET0 0 0xe7 1 0 1 CACHE_OFFSET0 0 24 mmUVD_JPEG_ADDR_CONFIG 0 0x21f 13 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 mmUVD_GPCOM_VCPU_CMD 0 0x3c3 3 0 1 CMD_SEND 0 0 CMD 1 30 CMD_SOURCE 31 31 mmUVD_GPCOM_VCPU_DATA0 0 0x3c4 1 0 1 DATA0 0 31 mmUVD_GPCOM_VCPU_DATA1 0 0x3c5 1 0 1 DATA1 0 31 mmUVD_UDEC_ADDR_CONFIG 0 0x3d3 13 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 mmUVD_UDEC_DB_ADDR_CONFIG 0 0x3d4 13 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 mmUVD_UDEC_DBW_ADDR_CONFIG 0 0x3d5 13 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 BANK_INTERLEAVE_SIZE 8 10 NUM_BANKS 12 14 SHADER_ENGINE_TILE_SIZE 16 18 NUM_SHADER_ENGINES 19 20 NUM_GPUS 21 23 MULTI_GPU_TILE_SIZE 24 25 NUM_RB_PER_SE 26 27 ROW_SIZE 28 29 NUM_LOWER_PIPES 30 30 SE_ENABLE 31 31 mmUVD_SUVD_CGC_GATE 0 0x3e4 19 0 1 SRE 0 0 SIT 1 1 SMP 2 2 SCM 3 3 SDB 4 4 SRE_H264 5 5 SRE_HEVC 6 6 SIT_H264 7 7 SIT_HEVC 8 8 SCM_H264 9 9 SCM_HEVC 10 10 SDB_H264 11 11 SDB_HEVC 12 12 SCLR 13 13 UVD_SC 14 14 ENT 15 15 IME 16 16 SIT_HEVC_DEC 17 17 SIT_HEVC_ENC 18 18 mmUVD_SUVD_CGC_CTRL 0 0x3e6 9 0 1 SRE_MODE 0 0 SIT_MODE 1 1 SMP_MODE 2 2 SCM_MODE 3 3 SDB_MODE 4 4 SCLR_MODE 5 5 UVD_SC_MODE 6 6 ENT_MODE 7 7 IME_MODE 8 8 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0 0x3ec 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0 0x3ed 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0 0x3f0 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0 0x3f1 1 0 1 BITS_63_32 0 31 mmUVD_POWER_STATUS_U 0 0x3fd 1 0 1 UVD_POWER_STATUS 0 1 mmUVD_NO_OP 0 0x3ff 1 0 1 NO_OP 0 31 mmUVD_GP_SCRATCH8 0 0x40a 1 0 1 DATA 0 31 mmUVD_RB_BASE_LO2 0 0x421 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI2 0 0x422 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE2 0 0x423 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR2 0 0x424 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR2 0 0x425 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO 0 0x426 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI 0 0x427 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE 0 0x428 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR 0 0x429 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR 0 0x42a 1 0 1 RB_WPTR 4 22 mmUVD_JRBC_RB_RPTR 0 0x457 1 0 1 RB_RPTR 4 22 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0x45e 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0x45f 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0 0x466 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0 0x467 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0 0x468 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0 0x469 1 0 1 BITS_31_0 0 31 mmUVD_SEMA_CNTL 0 0x500 2 0 1 SEMAPHORE_EN 0 0 ADVANCED_MODE_DIS 1 1 mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0 0x503 1 0 1 BITS_31_0 0 31 mmUVD_JRBC_RB_WPTR 0 0x509 1 0 1 RB_WPTR 4 22 mmUVD_RB_RPTR3 0 0x51b 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR3 0 0x51c 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO3 0 0x51d 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI3 0 0x51e 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE3 0 0x51f 1 0 1 RB_SIZE 4 22 mmJPEG_CGC_GATE 0 0x526 2 0 1 JPEG 20 20 JPEG2 21 21 mmUVD_CTX_INDEX 0 0x528 1 0 1 INDEX 0 8 mmUVD_CTX_DATA 0 0x529 1 0 1 DATA 0 31 mmUVD_CGC_GATE 0 0x52a 20 0 1 SYS 0 0 UDEC 1 1 MPEG2 2 2 REGS 3 3 RBC 4 4 LMI_MC 5 5 LMI_UMC 6 6 IDCT 7 7 MPRD 8 8 MPC 9 9 LBSI 10 10 LRBBM 11 11 UDEC_RE 12 12 UDEC_CM 13 13 UDEC_IT 14 14 UDEC_DB 15 15 UDEC_MP 16 16 WCB 17 17 VCPU 18 18 SCPU 19 19 mmUVD_CGC_CTRL 0 0x52c 23 0 1 DYN_CLOCK_MODE 0 0 CLK_GATE_DLY_TIMER 2 5 CLK_OFF_DELAY 6 10 UDEC_RE_MODE 11 11 UDEC_CM_MODE 12 12 UDEC_IT_MODE 13 13 UDEC_DB_MODE 14 14 UDEC_MP_MODE 15 15 SYS_MODE 16 16 UDEC_MODE 17 17 MPEG2_MODE 18 18 REGS_MODE 19 19 RBC_MODE 20 20 LMI_MC_MODE 21 21 LMI_UMC_MODE 22 22 IDCT_MODE 23 23 MPRD_MODE 24 24 MPC_MODE 25 25 LBSI_MODE 26 26 LRBBM_MODE 27 27 WCB_MODE 28 28 VCPU_MODE 29 29 SCPU_MODE 30 30 mmUVD_GP_SCRATCH4 0 0x538 1 0 1 DATA 0 31 mmUVD_LMI_CTRL2 0 0x53d 8 0 1 SPH_DIS 0 0 STALL_ARB 1 1 ASSERT_UMC_URGENT 2 2 MASK_UMC_URGENT 3 3 DRCITF_BUBBLE_FIX_DIS 7 7 STALL_ARB_UMC 8 8 MC_READ_ID_SEL 9 10 MC_WRITE_ID_SEL 11 12 mmUVD_MASTINT_EN 0 0x540 4 0 1 OVERRUN_RST 0 0 VCPU_EN 1 1 SYS_EN 2 2 INT_OVERRUN 4 22 mmUVD_FW_STATUS 0 0x557 9 0 1 BUSY 0 0 ACTIVE 1 1 SEND_EFUSE_REQ 2 2 DONE 8 8 PASS 16 16 FAIL 17 17 INVALID_LEN 18 18 INVALID_0_PADDING 19 19 INVALID_NONCE 20 20 mmJPEG_CGC_CTRL 0 0x565 5 0 1 DYN_CLOCK_MODE 0 0 JPEG2_MODE 1 1 CLK_GATE_DLY_TIMER 2 5 CLK_OFF_DELAY 6 10 JPEG_MODE 31 31 mmUVD_LMI_CTRL 0 0x566 14 0 1 WRITE_CLEAN_TIMER 0 7 WRITE_CLEAN_TIMER_EN 8 8 REQ_MODE 9 9 ASSERT_MC_URGENT 11 11 MASK_MC_URGENT 12 12 DATA_COHERENCY_EN 13 13 CRC_RESET 14 14 CRC_SEL 15 19 VCPU_DATA_COHERENCY_EN 21 21 CM_DATA_COHERENCY_EN 22 22 DB_DB_DATA_COHERENCY_EN 23 23 DB_IT_DATA_COHERENCY_EN 24 24 IT_IT_DATA_COHERENCY_EN 25 25 RFU 27 31 mmUVD_LMI_VM_CTRL 0 0x568 0 0 1 mmUVD_LMI_SWAP_CNTL 0 0x56d 15 0 1 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_RPTR_MC_SWAP 4 5 VCPU_R_MC_SWAP 6 7 VCPU_W_MC_SWAP 8 9 CM_MC_SWAP 10 11 IT_MC_SWAP 12 13 DB_R_MC_SWAP 14 15 DB_W_MC_SWAP 16 17 CSM_MC_SWAP 18 19 MP_REF16_MC_SWAP 22 23 DBW_MC_SWAP 24 25 RB_WR_MC_SWAP 26 27 RE_MC_SWAP 28 29 MP_MC_SWAP 30 31 mmUVD_MP_SWAP_CNTL 0 0x56f 16 0 1 MP_REF0_MC_SWAP 0 1 MP_REF1_MC_SWAP 2 3 MP_REF2_MC_SWAP 4 5 MP_REF3_MC_SWAP 6 7 MP_REF4_MC_SWAP 8 9 MP_REF5_MC_SWAP 10 11 MP_REF6_MC_SWAP 12 13 MP_REF7_MC_SWAP 14 15 MP_REF8_MC_SWAP 16 17 MP_REF9_MC_SWAP 18 19 MP_REF10_MC_SWAP 20 21 MP_REF11_MC_SWAP 22 23 MP_REF12_MC_SWAP 24 25 MP_REF13_MC_SWAP 26 27 MP_REF14_MC_SWAP 28 29 MP_REF15_MC_SWAP 30 31 mmUVD_MPC_SET_MUXA0 0 0x579 5 0 1 VARA_0 0 5 VARA_1 6 11 VARA_2 12 17 VARA_3 18 23 VARA_4 24 29 mmUVD_MPC_SET_MUXA1 0 0x57a 3 0 1 VARA_5 0 5 VARA_6 6 11 VARA_7 12 17 mmUVD_MPC_SET_MUXB0 0 0x57b 5 0 1 VARB_0 0 5 VARB_1 6 11 VARB_2 12 17 VARB_3 18 23 VARB_4 24 29 mmUVD_MPC_SET_MUXB1 0 0x57c 3 0 1 VARB_5 0 5 VARB_6 6 11 VARB_7 12 17 mmUVD_MPC_SET_MUX 0 0x57d 3 0 1 SET_0 0 2 SET_1 3 5 SET_2 6 8 mmUVD_MPC_SET_ALU 0 0x57e 2 0 1 FUNCT 0 2 OPERAND 4 11 mmUVD_VCPU_CACHE_OFFSET0 0 0x582 1 0 1 CACHE_OFFSET0 0 24 mmUVD_VCPU_CACHE_SIZE0 0 0x583 1 0 1 CACHE_SIZE0 0 20 mmUVD_VCPU_CACHE_OFFSET1 0 0x584 1 0 1 CACHE_OFFSET1 0 24 mmUVD_VCPU_CACHE_SIZE1 0 0x585 1 0 1 CACHE_SIZE1 0 20 mmUVD_VCPU_CACHE_OFFSET2 0 0x586 1 0 1 CACHE_OFFSET2 0 24 mmUVD_VCPU_CACHE_SIZE2 0 0x587 1 0 1 CACHE_SIZE2 0 20 mmUVD_VCPU_CNTL 0 0x598 1 0 1 CLK_EN 9 9 mmUVD_SOFT_RESET 0 0x5a0 26 0 1 RBC_SOFT_RESET 0 0 LBSI_SOFT_RESET 1 1 LMI_SOFT_RESET 2 2 VCPU_SOFT_RESET 3 3 UDEC_SOFT_RESET 4 4 CSM_SOFT_RESET 5 5 CXW_SOFT_RESET 6 6 TAP_SOFT_RESET 7 7 MPC_SOFT_RESET 8 8 IH_SOFT_RESET 10 10 LMI_UMC_SOFT_RESET 13 13 SPH_SOFT_RESET 14 14 MIF_SOFT_RESET 15 15 LCM_SOFT_RESET 16 16 SUVD_SOFT_RESET 17 17 LBSI_VCLK_RESET_STATUS 18 18 VCPU_VCLK_RESET_STATUS 19 19 UDEC_VCLK_RESET_STATUS 20 20 UDEC_DCLK_RESET_STATUS 21 21 MPC_DCLK_RESET_STATUS 22 22 MIF_DCLK_RESET_STATUS 26 26 LCM_DCLK_RESET_STATUS 27 27 SUVD_VCLK_RESET_STATUS 28 28 SUVD_DCLK_RESET_STATUS 29 29 RE_DCLK_RESET_STATUS 30 30 SRE_DCLK_RESET_STATUS 31 31 mmUVD_LMI_RBC_IB_VMID 0 0x5a1 1 0 1 IB_VMID 0 3 mmUVD_RBC_IB_SIZE 0 0x5a2 1 0 1 IB_SIZE 4 22 mmUVD_RBC_RB_RPTR 0 0x5a4 1 0 1 RB_RPTR 4 22 mmUVD_RBC_RB_WPTR 0 0x5a5 1 0 1 RB_WPTR 4 22 mmUVD_RBC_RB_WPTR_CNTL 0 0x5a6 1 0 1 RB_PRE_WRITE_TIMER 0 14 mmUVD_RBC_RB_CNTL 0 0x5a9 6 0 1 RB_BUFSZ 0 4 RB_BLKSZ 8 12 RB_NO_FETCH 16 16 RB_WPTR_POLL_EN 20 20 RB_NO_UPDATE 24 24 RB_RPTR_WR_EN 28 28 mmUVD_RBC_RB_RPTR_ADDR 0 0x5aa 1 0 1 RB_RPTR_ADDR 0 31 mmUVD_STATUS 0 0x5af 11 0 1 RBC_BUSY 0 0 VCPU_REPORT 1 7 AVP_BUSY 8 8 IDCT_BUSY 9 9 IDCT_CTL_ACK 11 11 UVD_CTL_ACK 12 12 AVP_BLOCK_ACK 13 13 IDCT_BLOCK_ACK 14 14 UVD_BLOCK_ACK 15 15 RBC_ACCESS_GPCOM 16 16 SYS_GPCOM_REQ 31 31 mmUVD_SEMA_TIMEOUT_STATUS 0 0x5b0 4 0 1 SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT 0 0 SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT 1 1 SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT 2 2 SEMAPHORE_TIMEOUT_CLEAR 3 3 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0 0x5b1 3 0 1 WAIT_INCOMPLETE_EN 0 0 WAIT_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0 0x5b2 3 0 1 WAIT_FAULT_EN 0 0 WAIT_FAULT_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0 0x5b3 3 0 1 SIGNAL_INCOMPLETE_EN 0 0 SIGNAL_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_CONTEXT_ID 0 0x5bd 1 0 1 CONTEXT_ID 0 31 mmUVD_CONTEXT_ID2 0 0x5bf 1 0 1 CONTEXT_ID2 0 31