81 mmVCE_STATUS 0 0xa01 5 0 0 JOB_BUSY 0 0 VCPU_REPORT 1 7 UENC_BUSY 8 8 VCE_CONFIGURATION 22 23 VCE_INSTANCE_ID 24 25 mmVCE_VCPU_CNTL 0 0xa05 4 0 0 CLK_EN 0 0 ED_ENABLE 1 1 RBBM_SOFT_RESET 18 18 ONE_CACHE_SURFACE_EN 21 21 mmVCE_VCPU_CACHE_OFFSET0 0 0xa09 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE0 0 0xa0a 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET1 0 0xa0b 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE1 0 0xa0c 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET2 0 0xa0d 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE2 0 0xa0e 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET3 0 0xa0f 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE3 0 0xa10 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET4 0 0xa11 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE4 0 0xa12 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET5 0 0xa13 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE5 0 0xa14 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET6 0 0xa15 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE6 0 0xa16 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET7 0 0xa17 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE7 0 0xa18 1 0 0 SIZE 0 23 mmVCE_VCPU_CACHE_OFFSET8 0 0xa19 1 0 0 OFFSET 0 27 mmVCE_VCPU_CACHE_SIZE8 0 0xa1a 1 0 0 SIZE 0 23 mmVCE_SOFT_RESET 0 0xa48 21 0 0 ECPU_SOFT_RESET 0 0 UENC_SOFT_RESET 1 1 FME_SOFT_RESET 2 2 MIF_SOFT_RESET 3 3 DBF_SOFT_RESET 4 4 ENT_SOFT_RESET 5 5 TBE_SOFT_RESET 6 6 LCM_SOFT_RESET 7 7 CTL_SOFT_RESET 8 8 IME_SOFT_RESET 9 9 IH_SOFT_RESET 10 10 SEM_SOFT_RESET 11 11 DCAP_SOFT_RESET 12 12 ACAP_SOFT_RESET 13 13 TAP_SOFT_RESET 14 14 LMI_SOFT_RESET 15 15 LMI_UMC_SOFT_RESET 16 16 AVMUX_SOFT_RESET 19 19 VREG_SOFT_RESET 20 20 DCAP_FSM_SOFT_RESET 21 21 VEP_SOFT_RESET 22 22 mmVCE_RB_BASE_LO2 0 0xa5b 1 0 0 RB_BASE_LO 6 31 mmVCE_RB_BASE_HI2 0 0xa5c 1 0 0 RB_BASE_HI 0 31 mmVCE_RB_SIZE2 0 0xa5d 1 0 0 RB_SIZE 4 22 mmVCE_RB_RPTR2 0 0xa5e 1 0 0 RB_RPTR 4 22 mmVCE_RB_WPTR2 0 0xa5f 1 0 0 RB_WPTR 4 22 mmVCE_RB_BASE_LO 0 0xa60 1 0 0 RB_BASE_LO 6 31 mmVCE_RB_BASE_HI 0 0xa61 1 0 0 RB_BASE_HI 0 31 mmVCE_RB_SIZE 0 0xa62 1 0 0 RB_SIZE 4 22 mmVCE_RB_RPTR 0 0xa63 1 0 0 RB_RPTR 4 22 mmVCE_RB_WPTR 0 0xa64 1 0 0 RB_WPTR 4 22 mmVCE_RB_ARB_CTRL 0 0xa9f 2 0 0 RB_ARB_CTRL 0 8 VCE_CGTT_OVERRIDE 16 16 mmVCE_CLOCK_GATING_A 0 0xabe 3 0 0 CGC_CLK_ON_DELAY 0 3 CGC_CLK_OFF_DELAY 4 11 CGC_REG_AWAKE 17 17 mmVCE_CLOCK_GATING_B 0 0xabf 18 0 0 CGC_SYS_CLK_FORCE_ON 0 0 CGC_LMI_MC_CLK_FORCE_ON 1 1 CGC_LMI_UMC_CLK_FORCE_ON 2 2 CGC_UENC_CLK_FORCE_ON 3 3 CGC_VREG_CLK_FORCE_ON 4 4 CGC_ECPU_CLK_FORCE_ON 5 5 CGC_IH_CLK_FORCE_ON 6 6 CGC_SEM_CLK_FORCE_ON 7 7 CGC_CTLREG_CLK_FORCE_ON 8 8 CGC_MMSCH_CLK_FORCE_ON 9 9 CGC_SYS_CLK_FORCE_OFF 16 16 CGC_LMI_MC_CLK_FORCE_OFF 17 17 CGC_LMI_UMC_CLK_FORCE_OFF 18 18 CGC_UENC_CLK_FORCE_OFF 19 19 CGC_ECPU_CLK_FORCE_OFF 21 21 CGC_IH_CLK_FORCE_OFF 22 22 CGC_SEM_CLK_FORCE_OFF 23 23 CGC_MMSCH_CLK_FORCE_OFF 24 24 mmVCE_RB_BASE_LO3 0 0xad4 1 0 0 RB_BASE_LO 6 31 mmVCE_RB_BASE_HI3 0 0xad5 1 0 0 RB_BASE_HI 0 31 mmVCE_RB_SIZE3 0 0xad6 1 0 0 RB_SIZE 4 22 mmVCE_RB_RPTR3 0 0xad7 1 0 0 RB_RPTR 4 22 mmVCE_RB_WPTR3 0 0xad8 1 0 0 RB_WPTR 4 22 mmVCE_SYS_INT_EN 0 0xb00 2 0 0 VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN 0 0 VCE_SYS_INT_TRAP_INTERRUPT_EN 3 3 mmVCE_SYS_INT_ACK 0 0xb01 2 0 0 VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK 0 0 VCE_SYS_INT_TRAP_INTERRUPT_ACK 3 3 mmVCE_SYS_INT_STATUS 0 0xb01 2 0 0 VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT 0 0 VCE_SYS_INT_TRAP_INTERRUPT_INT 3 3 mmVCE_UENC_CLOCK_GATING 0 0xbef 22 0 0 CLOCK_ON_DELAY 0 3 CLOCK_OFF_DELAY 4 11 VEPCLK_FORCE_ON 12 12 IMECLK_FORCE_ON 13 13 FMECLK_FORCE_ON 14 14 TBECLK_FORCE_ON 15 15 DBFCLK_FORCE_ON 16 16 ENTCLK_FORCE_ON 17 17 LCMCLK_FORCE_ON 18 18 AVMCLK_FORCE_ON 19 19 DCAPCLK_FORCE_ON 20 20 ACAPCLK_FORCE_ON 21 21 ACAPCLK_FORCE_OFF 22 22 VEPCLK_FORCE_OFF 23 23 IMECLK_FORCE_OFF 24 24 FMECLK_FORCE_OFF 25 25 TBECLK_FORCE_OFF 26 26 DBFCLK_FORCE_OFF 27 27 ENTCLK_FORCE_OFF 28 28 LCMCLK_FORCE_OFF 29 29 AVMCLK_FORCE_OFF 30 30 DCAPCLK_FORCE_OFF 31 31 mmVCE_UENC_REG_CLOCK_GATING 0 0xbf0 11 0 0 MIFREGCLK_FORCE_ON 0 0 IMEREGCLK_FORCE_ON 1 1 FMEREGCLK_FORCE_ON 2 2 TBEREGCLK_FORCE_ON 3 3 DBFREGCLK_FORCE_ON 4 4 ENTREGCLK_FORCE_ON 5 5 LCMREGCLK_FORCE_ON 6 6 RESERVED 7 7 AVMREGCLK_FORCE_ON 8 8 DCAPREGCLK_FORCE_ON 9 9 VEPREGCLK_FORCE_ON 10 10 mmVCE_UENC_CLOCK_GATING_2 0 0xc10 2 0 0 DBF2CLK_FORCE_ON 1 1 DBF2CLK_FORCE_OFF 16 16 mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0 0xfcc 1 0 0 BAR 0 31 mmVCE_LMI_CTRL2 0 0xfcf 4 0 0 STALL_ARB 1 1 ASSERT_UMC_URGENT 2 2 MASK_UMC_URGENT 3 3 STALL_ARB_UMC 8 8 mmVCE_LMI_SWAP_CNTL3 0 0xfd0 3 0 0 RD_MC_CID_SWAP 0 1 RD_MC_CID_TRAN 20 20 RD_MC_CID_URG 26 26 mmVCE_LMI_CTRL 0 0xfd6 7 0 0 ASSERT_MC_URGENT 11 11 MASK_MC_URGENT 12 12 DATA_COHERENCY_EN 13 13 VCPU_DATA_COHERENCY_EN 21 21 MIF_DATA_COHERENCY_EN 22 22 VCPU_RD_CACHE_MISS_COUNT_EN 23 23 VCPU_RD_CACHE_MISS_COUNT_RESET 24 24 mmVCE_LMI_STATUS 0 0xfd7 0 0 0 mmVCE_LMI_VM_CTRL 0 0xfd8 0 0 0 mmVCE_LMI_SWAP_CNTL 0 0xfdd 4 0 0 VCPU_W_MC_SWAP 0 1 WR_MC_CID_SWAP 2 13 WR_MC_CID_TRAN 20 25 WR_MC_CID_URG 26 31 mmVCE_LMI_SWAP_CNTL1 0 0xfde 4 0 0 VCPU_R_MC_SWAP 0 1 RD_MC_CID_SWAP 2 13 RD_MC_CID_TRAN 20 25 RD_MC_CID_URG 26 31 mmVCE_LMI_SWAP_CNTL2 0 0xfe2 3 0 0 WR_MC_CID_SWAP 0 7 WR_MC_CID_TRAN 20 23 WR_MC_CID_URG 26 29 mmVCE_LMI_CACHE_CTRL 0 0xfec 2 0 0 VCPU_EN 0 0 VCPU_FLUSH 1 1 mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0 0x1086 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0 0x1087 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0 0x1088 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0 0x1089 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0 0x108a 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0 0x108b 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0 0x108c 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0 0x108d 1 0 0 BAR 0 7 mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0 0x1096 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0 0x1097 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0 0x1098 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0 0x1099 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0 0x109a 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0 0x109b 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0 0x109c 1 0 0 BAR 0 31 mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0 0x109d 1 0 0 BAR 0 31 mmVCE_MMSCH_VF_VMID 0 0x10cb 2 0 0 VF_CTX_VMID 0 3 VF_GPCOM_VMID 4 7 mmVCE_MMSCH_VF_CTX_ADDR_LO 0 0x10cc 1 0 0 VF_CTX_ADDR_LO 6 31 mmVCE_MMSCH_VF_CTX_ADDR_HI 0 0x10cd 1 0 0 VF_CTX_ADDR_HI 0 31 mmVCE_MMSCH_VF_CTX_SIZE 0 0x10ce 1 0 0 VF_CTX_SIZE 0 31 mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0 0x10cf 1 0 0 VF_GPCOM_ADDR_LO 6 31 mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0 0x10d0 1 0 0 VF_GPCOM_ADDR_HI 0 31 mmVCE_MMSCH_VF_GPCOM_SIZE 0 0x10d1 1 0 0 VF_GPCOM_SIZE 0 31 mmVCE_MMSCH_VF_MAILBOX_HOST 0 0x10d2 1 0 0 DATA 0 31 mmVCE_MMSCH_VF_MAILBOX_RESP 0 0x10d3 1 0 0 RESP 0 31 mmVCE_HW_VERSION 0 0x11e8 3 0 0 VCE_VERSION 0 7 VCE_CONFIGURATION 8 9 VCE_INSTANCE_ID 10 11