467 mmUVD_JPEG_CNTL 0 0x80 4 0 0 REQUEST_EN 1 1 ERR_RST_EN 2 2 HUFF_SPEED_EN 3 3 HUFF_SPEED_STATUS 4 4 mmUVD_JPEG_RB_BASE 0 0x81 2 0 0 RB_BYTE_OFF 0 5 RB_BASE 6 31 mmUVD_JPEG_RB_WPTR 0 0x82 1 0 0 RB_WPTR 4 29 mmUVD_JPEG_RB_RPTR 0 0x83 1 0 0 RB_RPTR 4 29 mmUVD_JPEG_RB_SIZE 0 0x84 1 0 0 RB_SIZE 4 29 mmUVD_JPEG_DEC_SCRATCH0 0 0x89 1 0 0 SCRATCH0 0 31 mmUVD_JPEG_INT_EN 0 0x8a 13 0 0 OUTBUF_WPTR_INC_EN 0 0 JOB_AVAIL_EN 1 1 FENCE_VAL_EN 2 2 FIFO_OVERFLOW_ERR_EN 6 6 BLK_CNT_OUT_OF_SYNC_ERR_EN 7 7 EOI_ERR_EN 8 8 HFM_ERR_EN 9 9 RST_ERR_EN 10 10 ECS_MK_ERR_EN 11 11 TIMEOUT_ERR_EN 12 12 MARKER_ERR_EN 13 13 FMT_ERR_EN 14 14 PROFILE_ERR_EN 15 15 mmUVD_JPEG_INT_STAT 0 0x8b 13 0 0 OUTBUF_WPTR_INC_INT 0 0 JOB_AVAIL_INT 1 1 FENCE_VAL_INT 2 2 FIFO_OVERFLOW_ERR_INT 6 6 BLK_CNT_OUT_OF_SYNC_ERR_INT 7 7 EOI_ERR_INT 8 8 HFM_ERR_INT 9 9 RST_ERR_INT 10 10 ECS_MK_ERR_INT 11 11 TIMEOUT_ERR_INT 12 12 MARKER_ERR_INT 13 13 FMT_ERR_INT 14 14 PROFILE_ERR_INT 15 15 mmUVD_JPEG_PITCH 0 0x9f 1 0 0 PITCH 0 31 mmUVD_JPEG_UV_PITCH 0 0xa0 1 0 0 UV_PITCH 0 31 mmJPEG_DEC_Y_GFX8_TILING_SURFACE 0 0xa1 7 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 PIPE_CONFIG 8 12 TILE_SPLIT 13 15 ARRAY_MODE 16 19 mmJPEG_DEC_UV_GFX8_TILING_SURFACE 0 0xa2 7 0 0 BANK_WIDTH 0 1 BANK_HEIGHT 2 3 MACRO_TILE_ASPECT 4 5 NUM_BANKS 6 7 PIPE_CONFIG 8 12 TILE_SPLIT 13 15 ARRAY_MODE 16 19 mmJPEG_DEC_GFX8_ADDR_CONFIG 0 0xa3 1 0 0 PIPE_INTERLEAVE_SIZE 4 6 mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0 0xa4 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0 0xa5 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_DEC_GFX10_ADDR_CONFIG 0 0xa6 4 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmJPEG_DEC_ADDR_MODE 0 0xa7 3 0 0 ADDR_MODE_Y 0 1 ADDR_MODE_UV 2 3 ADDR_LIB_SEL 12 14 mmUVD_JPEG_GPCOM_CMD 0 0xa9 1 0 0 CMD 1 3 mmUVD_JPEG_GPCOM_DATA0 0 0xaa 1 0 0 DATA0 0 31 mmUVD_JPEG_GPCOM_DATA1 0 0xab 1 0 0 DATA1 0 31 mmUVD_JPEG_SCRATCH1 0 0xae 1 0 0 SCRATCH1 0 31 mmUVD_JPEG_DEC_SOFT_RST 0 0xaf 2 0 0 SOFT_RESET 0 0 RESET_STATUS 16 16 mmUVD_JPEG_ENC_INT_EN 0 0xc1 7 0 0 HUFF_JOB_DONE_INT_EN 0 0 SCLR_JOB_DONE_INT_EN 1 1 HUFF_ERROR_INT_EN 2 2 SCLR_ERROR_INT_EN 3 3 QTBL_ERROR_INT_EN 4 4 PIC_SIZE_ERROR_INT_EN 5 5 FENCE_VAL_INT_EN 6 6 mmUVD_JPEG_ENC_INT_STATUS 0 0xc2 7 0 0 HUFF_JOB_DONE_STATUS 0 0 SCLR_JOB_DONE_STATUS 1 1 HUFF_ERROR_STATUS 2 2 SCLR_ERROR_STATUS 3 3 QTBL_ERROR_STATUS 4 4 PIC_SIZE_ERROR_STATUS 5 5 FENCE_VAL_STATUS 6 6 mmUVD_JPEG_ENC_ENGINE_CNTL 0 0xc5 6 0 0 HUFF_WR_COMB_DIS 0 0 DISTINCT_CHROMA_QUANT_TABLES 1 1 SCALAR_EN 2 2 ENCODE_EN 3 3 CMP_NEEDED 4 4 ECS_RESTRICT_32B_EN 9 9 mmUVD_JPEG_ENC_SCRATCH1 0 0xce 1 0 0 SCRATCH1 0 31 mmUVD_JPEG_ENC_STATUS 0 0xe5 4 0 0 PEL_FETCH_IDLE 0 0 HUFF_CORE_IDLE 1 1 FDCT_IDLE 2 2 SCALAR_IDLE 3 3 mmUVD_JPEG_ENC_PITCH 0 0xe6 2 0 0 PITCH_Y 0 11 PITCH_UV 16 27 mmUVD_JPEG_ENC_LUMA_BASE 0 0xe7 1 0 0 LUMA_BASE 0 31 mmUVD_JPEG_ENC_CHROMAU_BASE 0 0xe8 1 0 0 CHROMAU_BASE 0 31 mmUVD_JPEG_ENC_CHROMAV_BASE 0 0xe9 1 0 0 CHROMAV_BASE 0 31 mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0 0xea 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0 0xeb 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_ENC_GFX10_ADDR_CONFIG 0 0xec 4 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmJPEG_ENC_ADDR_MODE 0 0xed 3 0 0 ADDR_MODE_Y 0 1 ADDR_MODE_UV 2 3 ADDR_LIB_SEL 12 14 mmUVD_JPEG_ENC_GPCOM_CMD 0 0xee 1 0 0 CMD 1 3 mmUVD_JPEG_ENC_GPCOM_DATA0 0 0xef 1 0 0 DATA0 0 31 mmUVD_JPEG_ENC_GPCOM_DATA1 0 0xf0 1 0 0 DATA1 0 31 mmUVD_JPEG_ENC_CGC_CNTL 0 0xf5 1 0 0 CGC_EN 0 0 mmUVD_JPEG_ENC_SCRATCH0 0 0xf6 1 0 0 SCRATCH0 0 31 mmUVD_JPEG_ENC_SOFT_RST 0 0xf7 2 0 0 SOFT_RST 0 0 RESET_STATUS 16 16 mmUVD_JRBC_RB_WPTR 0 0x100 1 0 0 RB_WPTR 4 22 mmUVD_JRBC_RB_CNTL 0 0x101 3 0 0 RB_NO_FETCH 0 0 RB_RPTR_WR_EN 1 1 RB_PRE_WRITE_TIMER 4 18 mmUVD_JRBC_IB_SIZE 0 0x102 1 0 0 IB_SIZE 4 22 mmUVD_JRBC_URGENT_CNTL 0 0x103 1 0 0 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_JRBC_RB_REF_DATA 0 0x104 1 0 0 REF_DATA 0 31 mmUVD_JRBC_RB_COND_RD_TIMER 0 0x105 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_SOFT_RESET 0 0x108 2 0 0 RESET 0 0 SCLK_RESET_STATUS 17 17 mmUVD_JRBC_STATUS 0 0x109 15 0 0 RB_JOB_DONE 0 0 IB_JOB_DONE 1 1 RB_ILLEGAL_CMD 2 2 RB_COND_REG_RD_TIMEOUT 3 3 RB_MEM_WR_TIMEOUT 4 4 RB_MEM_RD_TIMEOUT 5 5 IB_ILLEGAL_CMD 6 6 IB_COND_REG_RD_TIMEOUT 7 7 IB_MEM_WR_TIMEOUT 8 8 IB_MEM_RD_TIMEOUT 9 9 RB_TRAP_STATUS 10 10 PREEMPT_STATUS 11 11 IB_TRAP_STATUS 12 12 INT_EN 16 16 INT_ACK 17 17 mmUVD_JRBC_RB_RPTR 0 0x10a 1 0 0 RB_RPTR 4 22 mmUVD_JRBC_RB_BUF_STATUS 0 0x10b 3 0 0 RB_BUF_VALID 0 15 RB_BUF_RD_ADDR 16 19 RB_BUF_WR_ADDR 24 25 mmUVD_JRBC_IB_BUF_STATUS 0 0x10c 3 0 0 IB_BUF_VALID 0 15 IB_BUF_RD_ADDR 16 19 IB_BUF_WR_ADDR 24 25 mmUVD_JRBC_IB_SIZE_UPDATE 0 0x10d 1 0 0 REMAIN_IB_SIZE 4 22 mmUVD_JRBC_IB_COND_RD_TIMER 0 0x10e 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_IB_REF_DATA 0 0x10f 1 0 0 REF_DATA 0 31 mmUVD_JPEG_PREEMPT_CMD 0 0x110 3 0 0 PREEMPT_EN 0 0 WAIT_JPEG_JOB_DONE 1 1 PREEMPT_FENCE_CMD 2 2 mmUVD_JPEG_PREEMPT_FENCE_DATA0 0 0x111 1 0 0 PREEMPT_FENCE_DATA0 0 31 mmUVD_JPEG_PREEMPT_FENCE_DATA1 0 0x112 1 0 0 PREEMPT_FENCE_DATA1 0 31 mmUVD_JRBC_RB_SIZE 0 0x113 1 0 0 RB_SIZE 4 23 mmUVD_JRBC_SCRATCH0 0 0x114 1 0 0 SCRATCH0 0 31 mmUVD_JRBC_ENC_RB_WPTR 0 0x120 1 0 0 RB_WPTR 4 22 mmUVD_JRBC_ENC_RB_CNTL 0 0x121 3 0 0 RB_NO_FETCH 0 0 RB_RPTR_WR_EN 1 1 RB_PRE_WRITE_TIMER 4 18 mmUVD_JRBC_ENC_IB_SIZE 0 0x122 1 0 0 IB_SIZE 4 22 mmUVD_JRBC_ENC_URGENT_CNTL 0 0x123 1 0 0 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_JRBC_ENC_RB_REF_DATA 0 0x124 1 0 0 REF_DATA 0 31 mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0 0x125 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_ENC_SOFT_RESET 0 0x128 2 0 0 RESET 0 0 SCLK_RESET_STATUS 17 17 mmUVD_JRBC_ENC_STATUS 0 0x129 15 0 0 RB_JOB_DONE 0 0 IB_JOB_DONE 1 1 RB_ILLEGAL_CMD 2 2 RB_COND_REG_RD_TIMEOUT 3 3 RB_MEM_WR_TIMEOUT 4 4 RB_MEM_RD_TIMEOUT 5 5 IB_ILLEGAL_CMD 6 6 IB_COND_REG_RD_TIMEOUT 7 7 IB_MEM_WR_TIMEOUT 8 8 IB_MEM_RD_TIMEOUT 9 9 RB_TRAP_STATUS 10 10 PREEMPT_STATUS 11 11 IB_TRAP_STATUS 12 12 INT_EN 16 16 INT_ACK 17 17 mmUVD_JRBC_ENC_RB_RPTR 0 0x12a 1 0 0 RB_RPTR 4 22 mmUVD_JRBC_ENC_RB_BUF_STATUS 0 0x12b 3 0 0 RB_BUF_VALID 0 15 RB_BUF_RD_ADDR 16 19 RB_BUF_WR_ADDR 24 25 mmUVD_JRBC_ENC_IB_BUF_STATUS 0 0x12c 3 0 0 IB_BUF_VALID 0 15 IB_BUF_RD_ADDR 16 19 IB_BUF_WR_ADDR 24 25 mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0 0x12d 1 0 0 REMAIN_IB_SIZE 4 22 mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0 0x12e 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_ENC_IB_REF_DATA 0 0x12f 1 0 0 REF_DATA 0 31 mmUVD_JPEG_ENC_PREEMPT_CMD 0 0x130 3 0 0 PREEMPT_EN 0 0 WAIT_JPEG_JOB_DONE 1 1 PREEMPT_FENCE_CMD 2 2 mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0 0x131 1 0 0 PREEMPT_FENCE_DATA0 0 31 mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0 0x132 1 0 0 PREEMPT_FENCE_DATA1 0 31 mmUVD_JRBC_ENC_RB_SIZE 0 0x133 1 0 0 RB_SIZE 4 23 mmUVD_JRBC_ENC_SCRATCH0 0 0x134 1 0 0 SCRATCH0 0 31 mmUVD_JMI_CTRL 0 0x145 7 0 0 STALL_MC_ARB 0 0 MASK_MC_URGENT 1 1 ASSERT_MC_URGENT 2 2 MC_RD_ARB_WAIT_TIMER 8 15 MC_WR_ARB_WAIT_TIMER 16 23 CRC_RESET 24 24 CRC_SEL 25 28 mmUVD_LMI_JRBC_CTRL 0 0x146 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_LMI_JPEG_CTRL 0 0x147 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_JMI_EJRBC_CTRL 0 0x148 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_LMI_EJPEG_CTRL 0 0x149 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_LMI_JRBC_IB_VMID 0 0x14f 3 0 0 IB_WR_VMID 0 3 IB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_LMI_JRBC_RB_VMID 0 0x150 3 0 0 RB_WR_VMID 0 3 RB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_LMI_JPEG_VMID 0 0x151 3 0 0 JPEG_RD_VMID 0 3 JPEG_WR_VMID 4 7 ATOMIC_USER0_WR_VMID 8 11 mmUVD_JMI_ENC_JRBC_IB_VMID 0 0x152 3 0 0 IB_WR_VMID 0 3 IB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_JMI_ENC_JRBC_RB_VMID 0 0x153 3 0 0 RB_WR_VMID 0 3 RB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_JMI_ENC_JPEG_VMID 0 0x154 6 0 0 PEL_RD_VMID 0 3 BS_WR_VMID 5 8 SCALAR_RD_VMID 10 13 SCALAR_WR_VMID 15 18 HUFF_FENCE_VMID 19 22 ATOMIC_USER1_WR_VMID 23 26 mmUVD_JMI_PERFMON_CTRL 0 0x15c 2 0 0 PERFMON_STATE 0 1 PERFMON_SEL 8 11 mmUVD_JMI_PERFMON_COUNT_LO 0 0x15d 1 0 0 PERFMON_COUNT 0 31 mmUVD_JMI_PERFMON_COUNT_HI 0 0x15e 1 0 0 PERFMON_COUNT 0 15 mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0 0x160 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0 0x161 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0 0x162 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0 0x163 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0 0x164 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0 0x165 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0 0x166 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0 0x167 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0 0x168 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0 0x169 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0 0x16a 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0 0x16b 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0 0x16c 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0 0x16d 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0 0x16e 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0 0x16f 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0 0x170 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0 0x171 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0 0x17a 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0 0x17b 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0 0x17c 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0 0x17d 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0 0x17e 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0 0x17f 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0 0x180 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0 0x181 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0 0x182 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0 0x183 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0 0x184 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0 0x185 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0 0x186 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0 0x187 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_PREEMPT_VMID 0 0x188 1 0 0 VMID 0 3 mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0 0x189 1 0 0 VMID 0 3 mmUVD_LMI_JPEG2_VMID 0 0x18a 2 0 0 JPEG2_RD_VMID 0 3 JPEG2_WR_VMID 4 7 mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0 0x18b 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0 0x18c 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0 0x18d 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0 0x18e 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_CTRL2 0 0x18f 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_JMI_DEC_SWAP_CNTL 0 0x190 9 0 0 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_MEM_WR_MC_SWAP 4 5 IB_MEM_WR_MC_SWAP 6 7 RB_MEM_RD_MC_SWAP 8 9 IB_MEM_RD_MC_SWAP 10 11 PREEMPT_WR_MC_SWAP 12 13 JPEG_RD_MC_SWAP 14 15 JPEG_WR_MC_SWAP 16 17 mmUVD_JMI_ENC_SWAP_CNTL 0 0x191 12 0 0 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_MEM_WR_MC_SWAP 4 5 IB_MEM_WR_MC_SWAP 6 7 RB_MEM_RD_MC_SWAP 8 9 IB_MEM_RD_MC_SWAP 10 11 PREEMPT_WR_MC_SWAP 12 13 PEL_RD_MC_SWAP 14 15 BS_WR_MC_SWAP 16 17 SCALAR_RD_MC_SWAP 18 19 SCALAR_WR_MC_SWAP 20 21 HUFF_FENCE_MC_SWAP 22 23 mmUVD_JMI_CNTL 0 0x192 2 0 0 SOFT_RESET 0 0 MC_RD_REQ_RET_MAX 8 17 mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0 0x19a 1 0 0 BITS_31_0 0 31 mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0 0x19b 1 0 0 BITS_63_32 0 31 mmUVD_JMI_DEC_SWAP_CNTL2 0 0x19c 2 0 0 JPEG2_RD_MC_SWAP 0 1 JPEG2_WR_MC_SWAP 2 3 mmJPEG_SOFT_RESET_STATUS 0 0x1c0 6 0 0 JPEG_DEC_RESET_STATUS 0 0 JPEG2_DEC_RESET_STATUS 1 1 DJRBC_RESET_STATUS 2 2 JPEG_ENC_RESET_STATUS 3 3 EJRBC_RESET_STATUS 4 4 JMCIF_RESET_STATUS 5 5 mmJPEG_SYS_INT_EN 0 0x1c1 7 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 mmJPEG_SYS_INT_STATUS 0 0x1c2 7 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 mmJPEG_SYS_INT_ACK 0 0x1c3 7 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 mmJPEG_MASTINT_EN 0 0x1c8 2 0 0 OVERRUN_RST 0 0 INT_OVERRUN 4 22 mmJPEG_IH_CTRL 0 0x1c9 6 0 0 IH_SOFT_RESET 0 0 IH_STALL_EN 1 1 IH_STATUS_CLEAN 2 2 IH_VMID 3 6 IH_USER_DATA 7 18 IH_RINGID 19 26 mmJRBBM_ARB_CTRL 0 0x1cb 3 0 0 DJRBC_DROP 0 0 EJRBC_DROP 1 1 SRBM_DROP 2 2 mmJPEG_CGC_GATE 0 0x1e0 5 0 0 JPEG_DEC 0 0 JPEG2_DEC 1 1 JPEG_ENC 2 2 JMCIF 3 3 JRBBM 4 4 mmJPEG_CGC_CTRL 0 0x1e1 11 0 0 DYN_CLOCK_MODE 0 0 CLK_GATE_DLY_TIMER 1 4 CLK_OFF_DELAY 5 9 DYN_OCLK_RAMP_EN 10 10 DYN_RCLK_RAMP_EN 11 11 GATER_DIV_ID 12 14 JPEG_DEC_MODE 16 16 JPEG2_DEC_MODE 17 17 JPEG_ENC_MODE 18 18 JMCIF_MODE 19 19 JRBBM_MODE 20 20 mmJPEG_CGC_STATUS 0 0x1e2 9 0 0 JPEG_DEC_VCLK_ACTIVE 0 0 JPEG_DEC_SCLK_ACTIVE 1 1 JPEG2_DEC_VCLK_ACTIVE 2 2 JPEG2_DEC_SCLK_ACTIVE 3 3 JPEG_ENC_VCLK_ACTIVE 4 4 JPEG_ENC_SCLK_ACTIVE 5 5 JMCIF_SCLK_ACTIVE 6 6 JRBBM_VCLK_ACTIVE 7 7 JRBBM_SCLK_ACTIVE 8 8 mmJPEG_COMN_CGC_MEM_CTRL 0 0x1e3 5 0 0 JMCIF_LS_EN 0 0 JMCIF_DS_EN 1 1 JMCIF_SD_EN 2 2 LS_SET_DELAY 16 19 LS_CLEAR_DELAY 20 23 mmJPEG_DEC_CGC_MEM_CTRL 0 0x1e4 3 0 0 JPEG_DEC_LS_EN 0 0 JPEG_DEC_DS_EN 1 1 JPEG_DEC_SD_EN 2 2 mmJPEG2_DEC_CGC_MEM_CTRL 0 0x1e5 3 0 0 JPEG2_DEC_LS_EN 0 0 JPEG2_DEC_DS_EN 1 1 JPEG2_DEC_SD_EN 2 2 mmJPEG_ENC_CGC_MEM_CTRL 0 0x1e6 3 0 0 JPEG_ENC_LS_EN 0 0 JPEG_ENC_DS_EN 1 1 JPEG_ENC_SD_EN 2 2 mmJPEG_SOFT_RESET2 0 0x1e7 1 0 0 ATOMIC_SOFT_RESET 0 0 mmJPEG_PERF_BANK_CONF 0 0x1e8 3 0 0 RESET 0 3 PEEK 8 11 CONCATENATE 16 17 mmJPEG_PERF_BANK_EVENT_SEL 0 0x1e9 4 0 0 SEL0 0 7 SEL1 8 15 SEL2 16 23 SEL3 24 31 mmJPEG_PERF_BANK_COUNT0 0 0x1ea 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT1 0 0x1eb 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT2 0 0x1ec 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT3 0 0x1ed 1 0 0 COUNT 0 31 mmUVD_PGFSM_CONFIG 0 0x0 12 0 1 UVDM_PWR_CONFIG 0 1 UVDU_PWR_CONFIG 2 3 UVDF_PWR_CONFIG 4 5 UVDC_PWR_CONFIG 6 7 UVDB_PWR_CONFIG 8 9 UVDIL_PWR_CONFIG 10 11 UVDIR_PWR_CONFIG 12 13 UVDTD_PWR_CONFIG 14 15 UVDTE_PWR_CONFIG 16 17 UVDE_PWR_CONFIG 18 19 UVDW_PWR_CONFIG 20 21 UVDJ_PWR_CONFIG 22 23 mmUVD_PGFSM_STATUS 0 0x1 12 0 1 UVDM_PWR_STATUS 0 1 UVDU_PWR_STATUS 2 3 UVDF_PWR_STATUS 4 5 UVDC_PWR_STATUS 6 7 UVDB_PWR_STATUS 8 9 UVDIL_PWR_STATUS 10 11 UVDIR_PWR_STATUS 12 13 UVDTD_PWR_STATUS 14 15 UVDTE_PWR_STATUS 16 17 UVDE_PWR_STATUS 18 19 UVDW_PWR_STATUS 20 21 UVDJ_PWR_STATUS 22 23 mmUVD_POWER_STATUS 0 0x4 7 0 1 UVD_POWER_STATUS 0 1 UVD_PG_MODE 2 2 UVD_CG_MODE 4 5 UVD_PG_EN 8 8 RBC_SNOOP_DIS 9 9 SW_RB_SNOOP_DIS 11 11 STALL_DPG_POWER_UP 31 31 mmUVD_PG_IND_INDEX 0 0x5 1 0 1 INDEX 0 5 mmUVD_PG_IND_DATA 0 0x6 1 0 1 DATA 0 31 mmCC_UVD_HARVESTING 0 0x7 2 0 1 MMSCH_DISABLE 0 0 UVD_DISABLE 1 1 mmUVD_JPEG_POWER_STATUS 0 0xa 5 0 1 JPEG_POWER_STATUS 0 0 JPEG_PG_MODE 4 4 JRBC_DEC_SNOOP_DIS 8 8 JRBC_ENC_SNOOP_DIS 9 9 STALL_JDPG_POWER_UP 31 31 mmUVD_DPG_LMA_CTL 0 0x11 5 0 1 READ_WRITE 0 0 MASK_EN 1 1 ADDR_AUTO_INCREMENT 2 2 SRAM_SEL 4 4 READ_WRITE_ADDR 16 31 mmUVD_DPG_LMA_DATA 0 0x12 1 0 1 LMA_DATA 0 31 mmUVD_DPG_LMA_MASK 0 0x13 1 0 1 LMA_MASK 0 31 mmUVD_DPG_PAUSE 0 0x14 4 0 1 JPEG_PAUSE_DPG_REQ 0 0 JPEG_PAUSE_DPG_ACK 1 1 NJ_PAUSE_DPG_REQ 2 2 NJ_PAUSE_DPG_ACK 3 3 mmUVD_SCRATCH1 0 0x15 1 0 1 SCRATCH1_DATA 0 31 mmUVD_SCRATCH2 0 0x16 1 0 1 SCRATCH2_DATA 0 31 mmUVD_SCRATCH3 0 0x17 1 0 1 SCRATCH3_DATA 0 31 mmUVD_SCRATCH4 0 0x18 1 0 1 SCRATCH4_DATA 0 31 mmUVD_SCRATCH5 0 0x19 1 0 1 SCRATCH5_DATA 0 31 mmUVD_SCRATCH6 0 0x1a 1 0 1 SCRATCH6_DATA 0 31 mmUVD_SCRATCH7 0 0x1b 1 0 1 SCRATCH7_DATA 0 31 mmUVD_SCRATCH8 0 0x1c 1 0 1 SCRATCH8_DATA 0 31 mmUVD_SCRATCH9 0 0x1d 1 0 1 SCRATCH9_DATA 0 31 mmUVD_SCRATCH10 0 0x1e 1 0 1 SCRATCH10_DATA 0 31 mmUVD_SCRATCH11 0 0x1f 1 0 1 SCRATCH11_DATA 0 31 mmUVD_SCRATCH12 0 0x20 1 0 1 SCRATCH12_DATA 0 31 mmUVD_SCRATCH13 0 0x21 1 0 1 SCRATCH13_DATA 0 31 mmUVD_SCRATCH14 0 0x22 1 0 1 SCRATCH14_DATA 0 31 mmUVD_FREE_COUNTER_REG 0 0x24 1 0 1 FREE_COUNTER 0 31 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0x25 1 0 1 BITS_31_0 0 31 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0x26 1 0 1 BITS_63_32 0 31 mmUVD_DPG_VCPU_CACHE_OFFSET0 0 0x27 1 0 1 CACHE_OFFSET0 0 24 mmUVD_DPG_LMI_VCPU_CACHE_VMID 0 0x28 1 0 1 VCPU_CACHE_VMID 0 3 mmUVD_PF_STATUS 0 0x39 19 0 1 JPEG_PF_OCCURED 0 0 NJ_PF_OCCURED 1 1 ENCODER0_PF_OCCURED 2 2 ENCODER1_PF_OCCURED 3 3 ENCODER2_PF_OCCURED 4 4 ENCODER3_PF_OCCURED 5 5 ENCODER4_PF_OCCURED 6 6 EJPEG_PF_OCCURED 7 7 JPEG_PF_CLEAR 8 8 NJ_PF_CLEAR 9 9 ENCODER0_PF_CLEAR 10 10 ENCODER1_PF_CLEAR 11 11 ENCODER2_PF_CLEAR 12 12 ENCODER3_PF_CLEAR 13 13 ENCODER4_PF_CLEAR 14 14 EJPEG_PF_CLEAR 15 15 NJ_ATM_PF_OCCURED 16 16 DJ_ATM_PF_OCCURED 17 17 EJ_ATM_PF_OCCURED 18 18 mmUVD_DPG_CLK_EN_VCPU_REPORT 0 0x3c 2 0 1 CLK_EN 0 0 VCPU_REPORT 1 7 mmUVD_GFX8_ADDR_CONFIG 0 0x49 1 0 1 PIPE_INTERLEAVE_SIZE 4 6 mmUVD_GFX10_ADDR_CONFIG 0 0x4a 4 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmUVD_GPCNT2_CNTL 0 0x4b 3 0 1 CLR 0 0 START 1 1 COUNTUP 2 2 mmUVD_GPCNT2_TARGET_LOWER 0 0x4c 1 0 1 TARGET 0 31 mmUVD_GPCNT2_STATUS_LOWER 0 0x4d 1 0 1 COUNT 0 31 mmUVD_GPCNT2_TARGET_UPPER 0 0x4e 1 0 1 TARGET 0 15 mmUVD_GPCNT2_STATUS_UPPER 0 0x4f 1 0 1 COUNT 0 15 mmUVD_GPCNT3_CNTL 0 0x50 5 0 1 CLR 0 0 START 1 1 COUNTUP 2 2 FREQ 3 9 DIV 10 16 mmUVD_GPCNT3_TARGET_LOWER 0 0x51 1 0 1 TARGET 0 31 mmUVD_GPCNT3_STATUS_LOWER 0 0x52 1 0 1 COUNT 0 31 mmUVD_GPCNT3_TARGET_UPPER 0 0x53 1 0 1 TARGET 0 15 mmUVD_GPCNT3_STATUS_UPPER 0 0x54 1 0 1 COUNT 0 15 mmUVD_TSC_LOWER 0 0x57 1 0 1 COUNT 0 31 mmUVD_TSC_UPPER 0 0x58 1 0 1 COUNT 0 23 mmUVD_SEMA_CNTL 0 0x1c0 2 0 1 SEMAPHORE_EN 0 0 ADVANCED_MODE_DIS 1 1 mmUVD_RB_RPTR3 0 0x1db 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR3 0 0x1dc 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO3 0 0x1dd 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI3 0 0x1de 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE3 0 0x1df 1 0 1 RB_SIZE 4 22 mmUVD_RB_ARB_CTRL 0 0x1e0 9 0 1 SRBM_DROP 0 0 SRBM_DIS 1 1 VCPU_DROP 2 2 VCPU_DIS 3 3 RBC_DROP 4 4 RBC_DIS 5 5 FWOFLD_DROP 6 6 FWOFLD_DIS 7 7 FAST_PATH_EN 8 8 mmUVD_LMI_LAT_CTRL 0 0x1e2 6 0 1 SCALE 0 7 MAX_START 8 8 MIN_START 9 9 AVG_START 10 10 PERFMON_SYNC 11 11 SKIP 16 19 mmUVD_LMI_LAT_CNTR 0 0x1e3 2 0 1 MAX_LAT 0 7 MIN_LAT 8 15 mmUVD_LMI_AVG_LAT_CNTR 0 0x1e4 3 0 1 ENV_LOW 0 7 ENV_HIGH 8 15 ENV_HIT 16 31 mmUVD_SOFT_RESET2 0 0x1e6 3 0 1 ATOMIC_SOFT_RESET 0 0 MMSCH_VCLK_RESET_STATUS 16 16 MMSCH_SCLK_RESET_STATUS 17 17 mmUVD_LMI_SPH 0 0x1e7 4 0 1 ADDR 0 27 STS 28 29 STS_VALID 30 30 STS_OVERFLOW 31 31 mmUVD_CTX_INDEX 0 0x1e8 1 0 1 INDEX 0 8 mmUVD_CTX_DATA 0 0x1e9 1 0 1 DATA 0 31 mmUVD_CGC_GATE 0 0x1ea 21 0 1 SYS 0 0 UDEC 1 1 MPEG2 2 2 REGS 3 3 RBC 4 4 LMI_MC 5 5 LMI_UMC 6 6 IDCT 7 7 MPRD 8 8 MPC 9 9 LBSI 10 10 LRBBM 11 11 UDEC_RE 12 12 UDEC_CM 13 13 UDEC_IT 14 14 UDEC_DB 15 15 UDEC_MP 16 16 WCB 17 17 VCPU 18 18 SCPU 19 19 MMSCH 20 20 mmUVD_CGC_STATUS 0 0x1eb 31 0 1 SYS_SCLK 0 0 SYS_DCLK 1 1 SYS_VCLK 2 2 UDEC_SCLK 3 3 UDEC_DCLK 4 4 UDEC_VCLK 5 5 MPEG2_SCLK 6 6 MPEG2_DCLK 7 7 MPEG2_VCLK 8 8 REGS_SCLK 9 9 REGS_VCLK 10 10 RBC_SCLK 11 11 LMI_MC_SCLK 12 12 LMI_UMC_SCLK 13 13 IDCT_SCLK 14 14 IDCT_VCLK 15 15 MPRD_SCLK 16 16 MPRD_DCLK 17 17 MPRD_VCLK 18 18 MPC_SCLK 19 19 MPC_DCLK 20 20 LBSI_SCLK 21 21 LBSI_VCLK 22 22 LRBBM_SCLK 23 23 WCB_SCLK 24 24 VCPU_SCLK 25 25 VCPU_VCLK 26 26 MMSCH_SCLK 27 27 MMSCH_VCLK 28 28 ALL_ENC_ACTIVE 29 29 ALL_DEC_ACTIVE 31 31 mmUVD_CGC_CTRL 0 0x1ec 24 0 1 DYN_CLOCK_MODE 0 0 CLK_GATE_DLY_TIMER 2 5 CLK_OFF_DELAY 6 10 UDEC_RE_MODE 11 11 UDEC_CM_MODE 12 12 UDEC_IT_MODE 13 13 UDEC_DB_MODE 14 14 UDEC_MP_MODE 15 15 SYS_MODE 16 16 UDEC_MODE 17 17 MPEG2_MODE 18 18 REGS_MODE 19 19 RBC_MODE 20 20 LMI_MC_MODE 21 21 LMI_UMC_MODE 22 22 IDCT_MODE 23 23 MPRD_MODE 24 24 MPC_MODE 25 25 LBSI_MODE 26 26 LRBBM_MODE 27 27 WCB_MODE 28 28 VCPU_MODE 29 29 SCPU_MODE 30 30 MMSCH_MODE 31 31 mmUVD_CGC_UDEC_STATUS 0 0x1ed 15 0 1 RE_SCLK 0 0 RE_DCLK 1 1 RE_VCLK 2 2 CM_SCLK 3 3 CM_DCLK 4 4 CM_VCLK 5 5 IT_SCLK 6 6 IT_DCLK 7 7 IT_VCLK 8 8 DB_SCLK 9 9 DB_DCLK 10 10 DB_VCLK 11 11 MP_SCLK 12 12 MP_DCLK 13 13 MP_VCLK 14 14 mmUVD_CXW_WR_INT_ID 0 0x1ee 1 0 1 ID 0 7 mmUVD_CXW_WR_INT_CTX_ID 0 0x1ef 1 0 1 ID 0 27 mmUVD_VCPU_INT_ROUTE 0 0x1f3 3 0 1 DRV_FW_MSG 0 0 FW_DRV_MSG_ACK 1 1 VCPU_GPCOM 2 2 mmUVD_GP_SCRATCH0 0 0x1f4 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH1 0 0x1f5 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH2 0 0x1f6 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH3 0 0x1f7 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH4 0 0x1f8 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH5 0 0x1f9 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH6 0 0x1fa 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH7 0 0x1fb 1 0 1 DATA 0 31 mmUVD_LMI_VCPU_CACHE_VMID 0 0x1fc 1 0 1 VCPU_CACHE_VMID 0 3 mmUVD_LMI_CTRL2 0 0x1fd 17 0 1 SPH_DIS 0 0 STALL_ARB 1 1 ASSERT_UMC_URGENT 2 2 MASK_UMC_URGENT 3 3 CRC1_RESET 4 4 DRCITF_BUBBLE_FIX_DIS 7 7 STALL_ARB_UMC 8 8 MC_READ_ID_SEL 9 10 MC_WRITE_ID_SEL 11 12 VCPU_NC0_EXT_EN 13 13 VCPU_NC1_EXT_EN 14 14 SPU_EXTRA_CID_EN 15 15 RE_OFFLOAD_EN 16 16 RE_OFLD_MIF_WR_REQ_NUM 17 24 CLEAR_NJ_PF_BP 25 25 NJ_MIF_GATING 26 26 CRC1_SEL 27 31 mmUVD_MASTINT_EN 0 0x200 4 0 1 OVERRUN_RST 0 0 VCPU_EN 1 1 SYS_EN 2 2 INT_OVERRUN 4 22 mmUVD_SYS_INT_EN 0 0x201 19 0 1 PIF_ADDR_ERR_EN 0 0 SEMA_WAIT_FAULT_TIMEOUT_EN 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN 2 2 CXW_WR_EN 3 3 RBC_REG_PRIV_FAULT_EN 6 6 UVD_HOST_CXW_EN 8 8 LBSI_EN 11 11 UDEC_EN 12 12 JOB_DONE_EN 16 16 WPTR_IDLE_EN 21 21 RBC_REG_PRIV_FAULT_IDCT_EN 22 22 SEMA_WAIT_FAIL_SIG_EN 23 23 IDCT_EN 24 24 MPRD_EN 25 25 FCS_EN 26 26 CLK_SWT_EN 27 27 MIF_HWINT_EN 28 28 MPRD_ERR_EN 29 29 AVM_INT_EN 31 31 mmUVD_SYS_INT_STATUS 0 0x202 20 0 1 PIF_ADDR_ERR_INT 0 0 SEMA_WAIT_FAULT_TIMEOUT_INT 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT 2 2 CXW_WR_INT 3 3 RBC_REG_PRIV_FAULT_INT 6 6 UVD_HOST_CXW_INT 8 8 LBSI_INT 11 11 UDEC_INT 12 12 JOB_DONE_INT 16 16 GPCOM_INT 18 18 WPTR_IDLE_INT 21 21 RBC_REG_PRIV_FAULT_IDCT_INT 22 22 SEMA_WAIT_FAIL_SIG_INT 23 23 IDCT_INT 24 24 MPRD_INT 25 25 FCS_INT 26 26 CLK_SWT_INT 27 27 MIF_HWINT 28 28 MPRD_ERR_INT 29 29 AVM_INT 31 31 mmUVD_SYS_INT_ACK 0 0x203 19 0 1 PIF_ADDR_ERR_ACK 0 0 SEMA_WAIT_FAULT_TIMEOUT_ACK 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK 2 2 CXW_WR_ACK 3 3 RBC_REG_PRIV_FAULT_ACK 6 6 UVD_HOST_CXW_ACK 8 8 LBSI_ACK 11 11 UDEC_ACK 12 12 JOB_DONE_ACK 16 16 WPTR_IDLE_ACK 21 21 RBC_REG_PRIV_FAULT_IDCT_ACK 22 22 SEMA_WAIT_FAIL_SIG_ACK 23 23 IDCT_ACK 24 24 MPRD_ACK 25 25 FCS_ACK 26 26 CLK_SWT_ACK 27 27 MIF_HWINT_ACK 28 28 MPRD_ERR_ACK 29 29 AVM_INT_ACK 31 31 mmUVD_VCPU_INT_EN 0 0x204 27 0 1 PIF_ADDR_ERR_EN 0 0 SEMA_WAIT_FAULT_TIMEOUT_EN 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN 2 2 NJ_PF_RPT_EN 3 3 SW_RB1_INT_EN 4 4 SW_RB2_INT_EN 5 5 RBC_REG_PRIV_FAULT_EN 6 6 SW_RB3_INT_EN 7 7 UVD_HOST_CXW_EN 8 8 SW_RB4_INT_EN 9 9 SW_RB5_INT_EN 10 10 LBSI_EN 11 11 UDEC_EN 12 12 RPTR_WR_EN 16 16 JOB_START_EN 17 17 NJ_PF_EN 18 18 WPTR_IDLE_EN 21 21 RBC_REG_PRIV_FAULT_IDCT_EN 22 22 SEMA_WAIT_FAIL_SIG_EN 23 23 IDCT_EN 24 24 MPRD_EN 25 25 AVM_INT_EN 26 26 CLK_SWT_EN 27 27 MIF_HWINT_EN 28 28 MPRD_ERR_EN 29 29 DRV_FW_REQ_EN 30 30 DRV_FW_ACK_EN 31 31 mmUVD_VCPU_INT_ACK 0 0x206 27 0 1 PIF_ADDR_ERR_ACK 0 0 SEMA_WAIT_FAULT_TIMEOUT_ACK 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK 2 2 NJ_PF_RPT_ACK 3 3 SW_RB1_INT_ACK 4 4 SW_RB2_INT_ACK 5 5 RBC_REG_PRIV_FAULT_ACK 6 6 SW_RB3_INT_ACK 7 7 UVD_HOST_CXW_ACK 8 8 SW_RB4_INT_ACK 9 9 SW_RB5_INT_ACK 10 10 LBSI_ACK 11 11 UDEC_ACK 12 12 RPTR_WR_ACK 16 16 JOB_START_ACK 17 17 NJ_PF_ACK 18 18 WPTR_IDLE_ACK 21 21 RBC_REG_PRIV_FAULT_IDCT_ACK 22 22 SEMA_WAIT_FAIL_SIG_ACK 23 23 IDCT_ACK 24 24 MPRD_ACK 25 25 AVM_INT_ACK 26 26 CLK_SWT_ACK 27 27 MIF_HWINT_ACK 28 28 MPRD_ERR_ACK 29 29 DRV_FW_REQ_ACK 30 30 DRV_FW_ACK_ACK 31 31 mmUVD_TOP_CTRL 0 0x207 2 0 1 STANDARD 0 3 STD_VERSION 4 7 mmUVD_ENC_VCPU_INT_EN 0 0x21f 3 0 1 DCE_UVD_SCAN_IN_BUFMGR_EN 0 0 DCE_UVD_SCAN_IN_BUFMGR2_EN 1 1 DCE_UVD_SCAN_IN_BUFMGR3_EN 2 2 mmUVD_ENC_VCPU_INT_ACK 0 0x221 3 0 1 DCE_UVD_SCAN_IN_BUFMGR_ACK 0 0 DCE_UVD_SCAN_IN_BUFMGR2_ACK 1 1 DCE_UVD_SCAN_IN_BUFMGR3_ACK 2 2 mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0 0x222 8 0 1 VCPU_CACHE1_VMID 0 3 VCPU_CACHE2_VMID 4 7 VCPU_CACHE3_VMID 8 11 VCPU_CACHE4_VMID 12 15 VCPU_CACHE5_VMID 16 19 VCPU_CACHE6_VMID 20 23 VCPU_CACHE7_VMID 24 27 VCPU_CACHE8_VMID 28 31 mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0 0x223 6 0 1 VCPU_NC2_VMID 4 7 VCPU_NC3_VMID 8 11 VCPU_NC4_VMID 12 15 VCPU_NC5_VMID 16 19 VCPU_NC6_VMID 20 23 VCPU_NC7_VMID 24 27 mmUVD_LMI_URGENT_CTRL 0 0x224 12 0 1 ENABLE_MC_RD_URGENT_STALL 0 0 ASSERT_MC_RD_STALL 1 1 ASSERT_MC_RD_URGENT 2 5 ENABLE_MC_WR_URGENT_STALL 8 8 ASSERT_MC_WR_STALL 9 9 ASSERT_MC_WR_URGENT 10 13 ENABLE_UMC_RD_URGENT_STALL 16 16 ASSERT_UMC_RD_STALL 17 17 ASSERT_UMC_RD_URGENT 18 21 ENABLE_UMC_WR_URGENT_STALL 24 24 ASSERT_UMC_WR_STALL 25 25 ASSERT_UMC_WR_URGENT 26 29 mmUVD_LMI_CTRL 0 0x226 16 0 1 WRITE_CLEAN_TIMER 0 7 WRITE_CLEAN_TIMER_EN 8 8 REQ_MODE 9 9 ASSERT_MC_URGENT 11 11 MASK_MC_URGENT 12 12 DATA_COHERENCY_EN 13 13 CRC_RESET 14 14 CRC_SEL 15 19 VCPU_DATA_COHERENCY_EN 21 21 CM_DATA_COHERENCY_EN 22 22 DB_DB_DATA_COHERENCY_EN 23 23 DB_IT_DATA_COHERENCY_EN 24 24 IT_IT_DATA_COHERENCY_EN 25 25 MIF_MIF_DATA_COHERENCY_EN 26 26 MIF_LESS_OUTSTANDING_RD_REQ 27 27 RFU 28 31 mmUVD_LMI_STATUS 0 0x227 19 0 1 READ_CLEAN 0 0 WRITE_CLEAN 1 1 WRITE_CLEAN_RAW 2 2 VCPU_LMI_WRITE_CLEAN 3 3 UMC_READ_CLEAN 4 4 UMC_WRITE_CLEAN 5 5 UMC_WRITE_CLEAN_RAW 6 6 PENDING_UVD_MC_WRITE 7 7 READ_CLEAN_RAW 8 8 UMC_READ_CLEAN_RAW 9 9 UMC_UVD_IDLE 10 10 UMC_AVP_IDLE 11 11 ADP_MC_READ_CLEAN 12 12 ADP_UMC_READ_CLEAN 13 13 BSP0_WRITE_CLEAN 18 18 BSP1_WRITE_CLEAN 19 19 BSP2_WRITE_CLEAN 20 20 BSP3_WRITE_CLEAN 21 21 CENC_READ_CLEAN 22 22 mmUVD_LMI_VM_CTRL 0 0x228 14 0 1 VCPU_VM 0 0 CM_VM 1 1 IT_VM 2 2 MP_VM 3 3 DB_VM 4 4 RB_VM 5 5 IB_VM 6 6 CSM_VM 7 7 RB_WR_VM 8 8 DBW_VM 10 10 RB_RPTR_VM 11 11 RE_VM 12 12 SCPU_VM 13 13 ACAP_VM 14 14 mmUVD_LMI_PERFMON_CTRL 0 0x22a 2 0 1 PERFMON_STATE 0 1 PERFMON_SEL 8 12 mmUVD_LMI_PERFMON_COUNT_LO 0 0x22b 1 0 1 PERFMON_COUNT 0 31 mmUVD_LMI_PERFMON_COUNT_HI 0 0x22c 1 0 1 PERFMON_COUNT 0 15 mmUVD_LMI_SWAP_CNTL 0 0x22d 16 0 1 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_RPTR_MC_SWAP 4 5 VCPU_R_MC_SWAP 6 7 VCPU_W_MC_SWAP 8 9 CM_MC_SWAP 10 11 IT_MC_SWAP 12 13 DB_R_MC_SWAP 14 15 DB_W_MC_SWAP 16 17 CSM_MC_SWAP 18 19 ACAP_MC_SWAP 20 21 MP_REF16_MC_SWAP 22 23 DBW_MC_SWAP 24 25 RB_WR_MC_SWAP 26 27 RE_MC_SWAP 28 29 MP_MC_SWAP 30 31 mmUVD_UDEC_ADR 0 0x22e 1 0 1 SYNC_RE 7 7 mmUVD_MP_SWAP_CNTL 0 0x22f 16 0 1 MP_REF0_MC_SWAP 0 1 MP_REF1_MC_SWAP 2 3 MP_REF2_MC_SWAP 4 5 MP_REF3_MC_SWAP 6 7 MP_REF4_MC_SWAP 8 9 MP_REF5_MC_SWAP 10 11 MP_REF6_MC_SWAP 12 13 MP_REF7_MC_SWAP 14 15 MP_REF8_MC_SWAP 16 17 MP_REF9_MC_SWAP 18 19 MP_REF10_MC_SWAP 20 21 MP_REF11_MC_SWAP 22 23 MP_REF12_MC_SWAP 24 25 MP_REF13_MC_SWAP 26 27 MP_REF14_MC_SWAP 28 29 MP_REF15_MC_SWAP 30 31 mmUVD_MPC_LUMA_SRCH 0 0x231 1 0 1 CNTR 0 31 mmUVD_MPC_LUMA_HIT 0 0x232 1 0 1 CNTR 0 31 mmUVD_MPC_LUMA_HITPEND 0 0x233 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_SRCH 0 0x234 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_HIT 0 0x235 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_HITPEND 0 0x236 1 0 1 CNTR 0 31 mmUVD_MPC_CNTL 0 0x237 6 0 1 REPLACEMENT_MODE 3 5 PERF_RST 6 6 AVE_WEIGHT 16 17 URGENT_EN 18 18 SMPAT_REQ_SPEED_UP 19 19 TEST_MODE_EN 20 20 mmUVD_MPC_PITCH 0 0x238 1 0 1 LUMA_PITCH 0 10 mmUVD_MPC_SET_MUXA0 0 0x239 5 0 1 VARA_0 0 5 VARA_1 6 11 VARA_2 12 17 VARA_3 18 23 VARA_4 24 29 mmUVD_MPC_SET_MUXA1 0 0x23a 3 0 1 VARA_5 0 5 VARA_6 6 11 VARA_7 12 17 mmUVD_MPC_SET_MUXB0 0 0x23b 5 0 1 VARB_0 0 5 VARB_1 6 11 VARB_2 12 17 VARB_3 18 23 VARB_4 24 29 mmUVD_MPC_SET_MUXB1 0 0x23c 3 0 1 VARB_5 0 5 VARB_6 6 11 VARB_7 12 17 mmUVD_MPC_SET_MUX 0 0x23d 3 0 1 SET_0 0 2 SET_1 3 5 SET_2 6 8 mmUVD_MPC_SET_ALU 0 0x23e 2 0 1 FUNCT 0 2 OPERAND 4 11 mmUVD_GPCOM_SYS_CMD 0 0x23f 3 0 1 CMD_SEND 0 0 CMD 1 30 CMD_SOURCE 31 31 mmUVD_GPCOM_SYS_DATA0 0 0x240 1 0 1 DATA0 0 31 mmUVD_GPCOM_SYS_DATA1 0 0x241 1 0 1 DATA1 0 31 mmUVD_VCPU_CACHE_OFFSET0 0 0x242 1 0 1 CACHE_OFFSET0 0 20 mmUVD_VCPU_CACHE_SIZE0 0 0x243 1 0 1 CACHE_SIZE0 0 20 mmUVD_VCPU_CACHE_OFFSET1 0 0x244 1 0 1 CACHE_OFFSET1 0 20 mmUVD_VCPU_CACHE_SIZE1 0 0x245 1 0 1 CACHE_SIZE1 0 20 mmUVD_VCPU_CACHE_OFFSET2 0 0x246 1 0 1 CACHE_OFFSET2 0 20 mmUVD_VCPU_CACHE_SIZE2 0 0x247 1 0 1 CACHE_SIZE2 0 20 mmUVD_VCPU_CACHE_OFFSET3 0 0x248 1 0 1 CACHE_OFFSET3 0 20 mmUVD_VCPU_CACHE_SIZE3 0 0x249 1 0 1 CACHE_SIZE3 0 20 mmUVD_VCPU_CACHE_OFFSET4 0 0x24a 1 0 1 CACHE_OFFSET4 0 20 mmUVD_VCPU_CACHE_SIZE4 0 0x24b 1 0 1 CACHE_SIZE4 0 20 mmUVD_VCPU_CACHE_OFFSET5 0 0x24c 1 0 1 CACHE_OFFSET5 0 20 mmUVD_VCPU_CACHE_SIZE5 0 0x24d 1 0 1 CACHE_SIZE5 0 20 mmUVD_VCPU_CACHE_OFFSET6 0 0x24e 1 0 1 CACHE_OFFSET6 0 20 mmUVD_VCPU_CACHE_SIZE6 0 0x24f 1 0 1 CACHE_SIZE6 0 20 mmUVD_VCPU_CACHE_OFFSET7 0 0x250 1 0 1 CACHE_OFFSET7 0 20 mmUVD_VCPU_CACHE_SIZE7 0 0x251 1 0 1 CACHE_SIZE7 0 20 mmUVD_VCPU_CACHE_OFFSET8 0 0x252 1 0 1 CACHE_OFFSET8 0 20 mmUVD_VCPU_CACHE_SIZE8 0 0x253 1 0 1 CACHE_SIZE8 0 20 mmUVD_VCPU_NONCACHE_OFFSET0 0 0x254 1 0 1 NONCACHE_OFFSET0 0 24 mmUVD_VCPU_NONCACHE_SIZE0 0 0x255 1 0 1 NONCACHE_SIZE0 0 20 mmUVD_VCPU_NONCACHE_OFFSET1 0 0x256 1 0 1 NONCACHE_OFFSET1 0 24 mmUVD_VCPU_NONCACHE_SIZE1 0 0x257 1 0 1 NONCACHE_SIZE1 0 20 mmUVD_VCPU_CNTL 0 0x258 16 0 1 IRQ_ERR 0 3 PMB_ED_ENABLE 5 5 PMB_SOFT_RESET 6 6 RBBM_SOFT_RESET 7 7 ABORT_REQ 8 8 CLK_EN 9 9 TRCE_EN 10 10 TRCE_MUX 11 12 JTAG_EN 16 16 MIF_WR_LOW_THRESHOLD_BP 17 17 TIMEOUT_DIS 18 18 SUVD_EN 19 19 PRB_TIMEOUT_VAL 20 27 CABAC_MB_ACC 28 28 WMV9_EN 30 30 RE_OFFLOAD_EN 31 31 mmUVD_VCPU_PRID 0 0x259 1 0 1 PRID 0 15 mmUVD_VCPU_TRCE 0 0x25a 1 0 1 PC 0 27 mmUVD_VCPU_TRCE_RD 0 0x25b 1 0 1 DATA 0 31 mmUVD_MPC_PERF0 0 0x25c 1 0 1 MAX_LAT 0 9 mmUVD_MPC_PERF1 0 0x25d 1 0 1 AVE_LAT 0 9 mmUVD_CXW_WR 0 0x25f 2 0 1 DAT 0 27 STAT 31 31 mmUVD_SOFT_RESET 0 0x260 32 0 1 RBC_SOFT_RESET 0 0 LBSI_SOFT_RESET 1 1 LMI_SOFT_RESET 2 2 VCPU_SOFT_RESET 3 3 UDEC_SOFT_RESET 4 4 CSM_SOFT_RESET 5 5 CXW_SOFT_RESET 6 6 TAP_SOFT_RESET 7 7 MPC_SOFT_RESET 8 8 EFC_SOFT_RESET 9 9 IH_SOFT_RESET 10 10 MPRD_SOFT_RESET 11 11 IDCT_SOFT_RESET 12 12 LMI_UMC_SOFT_RESET 13 13 SPH_SOFT_RESET 14 14 MIF_SOFT_RESET 15 15 LCM_SOFT_RESET 16 16 SUVD_SOFT_RESET 17 17 LBSI_VCLK_RESET_STATUS 18 18 VCPU_VCLK_RESET_STATUS 19 19 UDEC_VCLK_RESET_STATUS 20 20 UDEC_DCLK_RESET_STATUS 21 21 MPC_DCLK_RESET_STATUS 22 22 MPRD_VCLK_RESET_STATUS 23 23 MPRD_DCLK_RESET_STATUS 24 24 IDCT_VCLK_RESET_STATUS 25 25 MIF_DCLK_RESET_STATUS 26 26 LCM_DCLK_RESET_STATUS 27 27 SUVD_VCLK_RESET_STATUS 28 28 SUVD_DCLK_RESET_STATUS 29 29 RE_DCLK_RESET_STATUS 30 30 SRE_DCLK_RESET_STATUS 31 31 mmUVD_LMI_RBC_IB_VMID 0 0x261 1 0 1 IB_VMID 0 3 mmUVD_RBC_IB_SIZE 0 0x262 1 0 1 IB_SIZE 4 22 mmUVD_LMI_RBC_RB_VMID 0 0x263 1 0 1 RB_VMID 0 3 mmUVD_RBC_RB_RPTR 0 0x264 1 0 1 RB_RPTR 4 22 mmUVD_RBC_RB_WPTR 0 0x265 1 0 1 RB_WPTR 4 22 mmUVD_RBC_RB_WPTR_CNTL 0 0x266 1 0 1 RB_PRE_WRITE_TIMER 0 14 mmUVD_RBC_READ_REQ_URGENT_CNTL 0 0x267 1 0 1 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_RBC_WPTR_STATUS 0 0x268 1 0 1 RB_WPTR_IN_USE 4 22 mmUVD_RBC_RB_CNTL 0 0x269 6 0 1 RB_BUFSZ 0 4 RB_BLKSZ 8 12 RB_NO_FETCH 16 16 RB_WPTR_POLL_EN 20 20 RB_NO_UPDATE 24 24 RB_RPTR_WR_EN 28 28 mmUVD_RBC_RB_RPTR_ADDR 0 0x26a 1 0 1 RB_RPTR_ADDR 0 31 mmUVD_JOB_START 0 0x26d 1 0 1 JOB_START 0 0 mmUVD_JOB_DONE 0 0x26e 1 0 1 JOB_DONE 0 1 mmUVD_STATUS 0 0x26f 11 0 1 RBC_BUSY 0 0 VCPU_REPORT 1 7 AVP_BUSY 8 8 IDCT_BUSY 9 9 IDCT_CTL_ACK 11 11 UVD_CTL_ACK 12 12 AVP_BLOCK_ACK 13 13 IDCT_BLOCK_ACK 14 14 UVD_BLOCK_ACK 15 15 RBC_ACCESS_GPCOM 16 16 SYS_GPCOM_REQ 31 31 mmUVD_SEMA_TIMEOUT_STATUS 0 0x270 4 0 1 SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT 0 0 SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT 1 1 SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT 2 2 SEMAPHORE_TIMEOUT_CLEAR 3 3 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0 0x271 3 0 1 WAIT_INCOMPLETE_EN 0 0 WAIT_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0 0x272 3 0 1 WAIT_FAULT_EN 0 0 WAIT_FAULT_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0 0x273 3 0 1 SIGNAL_INCOMPLETE_EN 0 0 SIGNAL_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_CXW_EN 0 0x274 1 0 1 CXW_ENABLE 0 0 mmUVD_CXW_SE 0 0x275 1 0 1 CXW_SCAN_ENABLE 0 0 mmUVD_CXW_FINISHED 0 0x276 1 0 1 CXW_FINISHED 0 0 mmUVD_CXW_SHIFT_FINISHED 0 0x277 1 0 1 SHIFT_FINISHED 0 0 mmUVD_CXW_START 0 0x278 1 0 1 START_CXW 0 0 mmUVD_CXW_BLOCK_STATUS 0 0x279 3 0 1 VCPU_IDLE 0 0 LBSI_IDLE 1 1 LMI_IDLE 2 2 mmUVD_STOP_CONTEXT 0 0x27a 2 0 1 STOP_CONTEXT 0 0 CONTEXT_MODE 1 1 mmUVD_CXW_SAVE_AREA_ADDR 0 0x27b 1 0 1 CXW_SAVE_AREA_ADDR 6 31 mmUVD_CBUF_ID 0 0x27c 1 0 1 CBUF_ID 0 31 mmUVD_CONTEXT_ID 0 0x27d 1 0 1 CONTEXT_ID 0 31 mmUVD_CXW_SAVE_AREA_SIZE 0 0x27e 1 0 1 CXW_SAVE_AREA_SIZE 0 31 mmUVD_CONTEXT_ID2 0 0x27f 1 0 1 CONTEXT_ID2 0 31 mmUVD_CXW_CNTL 0 0x280 6 0 1 HOST_CXW_EN 0 0 EXTERNAL_CXW_EN 1 1 SEMAPHORE_TIMEOUT_CXW_EN 3 3 HOST_CXW_INT_EN 4 4 EXTERNAL_CXW_INT_EN 5 5 SEMAPHORE_TIMEOUT_CXW_INT_EN 7 7 mmUVD_CXW_EVENT 0 0x281 5 0 1 HOST_CXW_EVENT_OCCURRED 0 0 EXTERNAL_CXW_EVENT_OCCURRED 1 1 SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED 3 3 SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED 4 4 SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED 5 5 mmUVD_CXW_SCAN_AREA_OFFSET 0 0x282 3 0 1 CXW_SCAN_AREA_OFFSET 0 25 CXW_CONTEXT_RESTORE 26 26 CXW_CONTEXT_SAVE 27 27 mmUVD_CXW_SHIFT_CNTL 0 0x283 2 0 1 SHIFT_CNTL 0 0 SHIFT_COUNT 1 11 mmUVD_RBC_CAM_EN 0 0x286 1 0 1 RBC_CAM_EN 0 0 mmUVD_RBC_CAM_INDEX 0 0x287 1 0 1 RBC_CAM_INDEX 0 31 mmUVD_RBC_CAM_DATA 0 0x288 2 0 1 RBC_CAM_DATA_ORG 0 15 RBC_CAM_DATA_MAP 16 31 mmUVD_RBC_VCPU_ACCESS 0 0x289 1 0 1 ENABLE_RBC 0 0 mmUVD_CXW_INT_ID 0 0x293 1 0 1 ID 0 7 mmUVD_LMI_CRC0 0 0x294 1 0 1 CRC32 0 31 mmUVD_LMI_CRC1 0 0x295 1 0 1 CRC32 0 31 mmUVD_LMI_CRC2 0 0x296 1 0 1 CRC32 0 31 mmUVD_LMI_CRC3 0 0x297 1 0 1 CRC32 0 31 mmUVD_RBC_WPTR_POLL_CNTL 0 0x298 2 0 1 POLL_FREQ 0 15 IDLE_POLL_COUNT 16 31 mmUVD_RBC_WPTR_POLL_ADDR 0 0x299 1 0 1 POLL_ADDR 2 31 mmUVD_RB_BASE_LO4 0 0x29f 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI4 0 0x2a0 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE4 0 0x2a1 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR4 0 0x2a2 1 0 1 RB_RPTR 4 22 mmUVD_LMI_MC_CREDITS 0 0x2a3 4 0 1 UVD_RD_CREDITS 0 5 UVD_WR_CREDITS 8 13 UMC_RD_CREDITS 16 21 UMC_WR_CREDITS 24 29 mmUVD_RBC_BUF_STATUS 0 0x2b0 6 0 1 RB_BUF_VALID 0 7 IB_BUF_VALID 8 15 RB_BUF_RD_ADDR 16 18 IB_BUF_RD_ADDR 19 21 RB_BUF_WR_ADDR 22 24 IB_BUF_WR_ADDR 25 27 mmUVD_RBC_IB_SIZE_UPDATE 0 0x2b1 1 0 1 REMAIN_IB_SIZE 4 22 mmUVD_RBC_BDM_PRE 0 0x2b2 1 0 1 BDM_ENABLE 0 0 mmCG_TIMESTAMP_LOW 0 0x2b5 1 0 1 CG_LOW 0 31 mmCG_TIMESTAMP_HIGH 0 0x2b6 1 0 1 CG_HIGH 0 31 mmUVD_UMC_UVD_CTL_CMD 0 0x2b7 1 0 1 CMC_REQ 0 0 mmUVD_UMC_UVD_BLOCK_REQ 0 0x2b8 1 0 1 CMC_BLOCK_REQ 0 0 mmUVD_RBC_CXW_RELEASE 0 0x2b9 1 0 1 SOFT_RELEASE_RBC 0 0 mmUVD_YBASE 0 0x2ba 1 0 1 DUM 0 31 mmUVD_UVBASE 0 0x2bb 1 0 1 DUM 0 31 mmUVD_PITCH 0 0x2bc 1 0 1 DUM 0 31 mmUVD_WIDTH 0 0x2bd 1 0 1 DUM 0 31 mmUVD_HEIGHT 0 0x2be 1 0 1 DUM 0 31 mmUVD_PICCOUNT 0 0x2bf 1 0 1 DUM 0 31 mmUVD_SEMA_ADDR_LOW 0 0x580 1 0 1 ADDR_26_3 0 23 mmUVD_SEMA_ADDR_HIGH 0 0x581 1 0 1 ADDR_47_27 0 20 mmUVD_SEMA_CMD 0 0x582 5 0 1 REQ_CMD 0 3 WR_PHASE 4 5 MODE 6 6 VMID_EN 7 7 VMID 8 11 mmUVD_GPCOM_VCPU_CMD 0 0x583 3 0 1 CMD_SEND 0 0 CMD 1 30 CMD_SOURCE 31 31 mmUVD_GPCOM_VCPU_DATA0 0 0x584 1 0 1 DATA0 0 31 mmUVD_GPCOM_VCPU_DATA1 0 0x585 1 0 1 DATA1 0 31 mmUVD_ENGINE_CNTL 0 0x586 3 0 1 ENGINE_START 0 0 ENGINE_START_MODE 1 1 NJ_PF_HANDLE_DISABLE 2 2 mmUVD_SUVD_CGC_GATE 0 0x5a4 26 0 1 SRE 0 0 SIT 1 1 SMP 2 2 SCM 3 3 SDB 4 4 SRE_H264 5 5 SRE_HEVC 6 6 SIT_H264 7 7 SIT_HEVC 8 8 SCM_H264 9 9 SCM_HEVC 10 10 SDB_H264 11 11 SDB_HEVC 12 12 SCLR 13 13 UVD_SC 14 14 ENT 15 15 IME 16 16 SIT_HEVC_DEC 17 17 SIT_HEVC_ENC 18 18 SITE 19 19 SRE_VP9 20 20 SCM_VP9 21 21 SIT_VP9_DEC 22 22 SDB_VP9 23 23 IME_HEVC 24 24 EFC 25 25 mmUVD_SUVD_CGC_STATUS 0 0x5a5 29 0 1 SRE_VCLK 0 0 SRE_DCLK 1 1 SIT_DCLK 2 2 SMP_DCLK 3 3 SCM_DCLK 4 4 SDB_DCLK 5 5 SRE_H264_VCLK 6 6 SRE_HEVC_VCLK 7 7 SIT_H264_DCLK 8 8 SIT_HEVC_DCLK 9 9 SCM_H264_DCLK 10 10 SCM_HEVC_DCLK 11 11 SDB_H264_DCLK 12 12 SDB_HEVC_DCLK 13 13 SCLR_DCLK 14 14 UVD_SC 15 15 ENT_DCLK 16 16 IME_DCLK 17 17 SIT_HEVC_DEC_DCLK 18 18 SIT_HEVC_ENC_DCLK 19 19 SITE_DCLK 20 20 SITE_HEVC_DCLK 21 21 SITE_HEVC_ENC_DCLK 22 22 SRE_VP9_VCLK 23 23 SCM_VP9_VCLK 24 24 SIT_VP9_DEC_DCLK 25 25 SDB_VP9_DCLK 26 26 IME_HEVC_DCLK 27 27 EFC_DCLK 28 28 mmUVD_SUVD_CGC_CTRL 0 0x5a6 11 0 1 SRE_MODE 0 0 SIT_MODE 1 1 SMP_MODE 2 2 SCM_MODE 3 3 SDB_MODE 4 4 SCLR_MODE 5 5 UVD_SC_MODE 6 6 ENT_MODE 7 7 IME_MODE 8 8 SITE_MODE 9 9 EFC_MODE 10 10 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0 0x5ac 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0 0x5ad 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0 0x5ae 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0 0x5af 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0 0x5b0 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0 0x5b1 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0 0x5b2 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0 0x5b3 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0 0x5b4 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0 0x5b5 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0 0x5b6 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0 0x5b7 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0 0x5b8 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0 0x5b9 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0 0x5ba 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0 0x5bb 1 0 1 BITS_63_32 0 31 mmUVD_SCRATCH_NP 0 0x5bc 1 0 1 DATA 0 31 mmUVD_NO_OP 0 0x5bf 1 0 1 NO_OP 0 31 mmMDM_DMA_CMD 0 0x5c0 1 0 1 MDM_DMA_CMD 0 31 mmMDM_DMA_STATUS 0 0x5c1 7 0 1 SDB_DMA_WR_BUSY 0 0 SCM_DMA_WR_BUSY 1 1 SCM_DMA_RD_BUSY 2 2 RB_DMA_WR_BUSY 3 3 RB_DMA_RD_BUSY 4 4 SDB_DMA_RD_BUSY 5 5 SCLR_DMA_WR_BUSY 6 6 mmMDM_DMA_CTL 0 0x5c2 5 0 1 MDM_BYPASS 0 0 FOUR_CMD 1 1 ENCODE_MODE 2 2 VP9_DEC_MODE 3 3 SW_DRST 31 31 mmMDM_ENC_PIPE_BUSY 0 0x5c3 27 0 1 IME_BUSY 0 0 SMP_BUSY 1 1 SIT_BUSY 2 2 SDB_BUSY 3 3 ENT_BUSY 4 4 ENT_HEADER_BUSY 5 5 LCM_BUSY 6 6 MDM_RD_CUR_BUSY 7 7 MDM_RD_REF_BUSY 8 8 MDM_RD_GEN_BUSY 9 9 MDM_WR_RECON_BUSY 10 10 MDM_WR_GEN_BUSY 11 11 MDM_EFC_BUSY 12 12 MDM_EFC_PROGRAM_BUSY 13 13 MIF_RD_CUR_BUSY 16 16 MIF_RD_REF0_BUSY 17 17 MIF_WR_GEN0_BUSY 18 18 MIF_RD_GEN0_BUSY 19 19 MIF_WR_GEN1_BUSY 20 20 MIF_RD_GEN1_BUSY 21 21 MIF_WR_BSP0_BUSY 22 22 MIF_WR_BSP1_BUSY 23 23 MIF_RD_BSD0_BUSY 24 24 MIF_RD_BSD1_BUSY 25 25 MIF_RD_BSD2_BUSY 26 26 MIF_RD_BSD3_BUSY 27 27 MIF_RD_BSD4_BUSY 28 28 mmMDM_WIG_PIPE_BUSY 0 0x5c5 30 0 1 WIG_TBE_BUSY 0 0 WIG_ENT_BUSY 1 1 WIG_ENT_HEADER_BUSY 2 2 WIG_ENT_HEADER_FIFO_FULL 3 3 LCM_BUSY 4 4 MDM_RD_CUR_BUSY 5 5 MDM_RD_REF_BUSY 6 6 MDM_RD_GEN_BUSY 7 7 MDM_WR_RECON_BUSY 8 8 MDM_WR_GEN_BUSY 9 9 MIF_RD_CUR_BUSY 10 10 MIF_RD_REF0_BUSY 11 11 MIF_WR_GEN0_BUSY 12 12 MIF_RD_GEN0_BUSY 13 13 MIF_WR_GEN1_BUSY 14 14 MIF_RD_GEN1_BUSY 15 15 MIF_WR_BSP0_BUSY 16 16 MIF_WR_BSP1_BUSY 17 17 MIF_RD_BSD0_BUSY 18 18 MIF_RD_BSD1_BUSY 19 19 MIF_RD_BSD2_BUSY 20 20 MIF_RD_BSD3_BUSY 21 21 MIF_RD_BSD4_BUSY 22 22 MIF_RD_BSD5_BUSY 23 23 MIF_WR_BSP2_BUSY 24 24 MIF_WR_BSP3_BUSY 25 25 LCM_BSP0_NOT_EMPTY 26 26 LCM_BSP1_NOT_EMPTY 27 27 LCM_BSP2_NOT_EMPTY 28 28 LCM_BSP3_NOT_EMPTY 29 29 mmUVD_VERSION 0 0x5c9 2 0 1 MINOR_VERSION 0 15 MAJOR_VERSION 16 31 mmUVD_GP_SCRATCH8 0 0x5ca 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH9 0 0x5cb 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH10 0 0x5cc 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH11 0 0x5cd 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH12 0 0x5ce 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH13 0 0x5cf 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH14 0 0x5d0 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH15 0 0x5d1 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH16 0 0x5d2 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH17 0 0x5d3 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH18 0 0x5d4 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH19 0 0x5d5 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH20 0 0x5d6 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH21 0 0x5d7 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH22 0 0x5d8 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH23 0 0x5d9 1 0 1 DATA 0 31 mmUVD_ENC_REG_INDEX 0 0x5da 1 0 1 INDEX 0 12 mmUVD_ENC_REG_DATA 0 0x5db 1 0 1 DATA 0 31 mmUVD_OUT_RB_BASE_LO 0 0x5dc 1 0 1 RB_BASE_LO 6 31 mmUVD_OUT_RB_BASE_HI 0 0x5dd 1 0 1 RB_BASE_HI 0 31 mmUVD_OUT_RB_SIZE 0 0x5de 1 0 1 RB_SIZE 4 22 mmUVD_OUT_RB_RPTR 0 0x5df 1 0 1 RB_RPTR 4 22 mmUVD_OUT_RB_WPTR 0 0x5e0 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO2 0 0x5e1 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI2 0 0x5e2 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE2 0 0x5e3 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR2 0 0x5e4 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR2 0 0x5e5 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO 0 0x5e6 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI 0 0x5e7 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE 0 0x5e8 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR 0 0x5e9 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR 0 0x5ea 1 0 1 RB_WPTR 4 22 mmUVD_ENC_PIPE_BUSY 0 0x5eb 27 0 1 IME_BUSY 0 0 SMP_BUSY 1 1 SIT_BUSY 2 2 SDB_BUSY 3 3 ENT_BUSY 4 4 ENT_HEADER_BUSY 5 5 LCM_BUSY 6 6 MDM_RD_CUR_BUSY 7 7 MDM_RD_REF_BUSY 8 8 MDM_RD_GEN_BUSY 9 9 MDM_WR_RECON_BUSY 10 10 MDM_WR_GEN_BUSY 11 11 MIF_RD_CUR_BUSY 16 16 MIF_RD_REF0_BUSY 17 17 MIF_WR_GEN0_BUSY 18 18 MIF_RD_GEN0_BUSY 19 19 MIF_WR_GEN1_BUSY 20 20 MIF_RD_GEN1_BUSY 21 21 MIF_WR_BSP0_BUSY 22 22 MIF_WR_BSP1_BUSY 23 23 MIF_RD_BSD0_BUSY 24 24 MIF_RD_BSD1_BUSY 25 25 MIF_RD_BSD2_BUSY 26 26 MIF_RD_BSD3_BUSY 27 27 MIF_RD_BSD4_BUSY 28 28 MIF_WR_BSP2_BUSY 29 29 MIF_WR_BSP3_BUSY 30 30 mmUVD_RB_WPTR4 0 0x616 1 0 1 RB_WPTR 4 22 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0x61e 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0x61f 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0 0x620 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0 0x621 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0 0x622 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0 0x623 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0 0x626 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0 0x627 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0 0x628 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0 0x629 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0 0x640 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0 0x641 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0 0x642 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0 0x643 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0 0x644 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0 0x645 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0 0x646 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0 0x647 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0 0x648 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0 0x649 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0 0x64a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0 0x64b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0 0x64c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0 0x64d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0 0x64e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0 0x64f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC_VMID 0 0x651 8 0 1 MMSCH_NC0_VMID 0 3 MMSCH_NC1_VMID 4 7 MMSCH_NC2_VMID 8 11 MMSCH_NC3_VMID 12 15 MMSCH_NC4_VMID 16 19 MMSCH_NC5_VMID 20 23 MMSCH_NC6_VMID 24 27 MMSCH_NC7_VMID 28 31 mmUVD_LMI_MMSCH_CTRL 0 0x652 8 0 1 MMSCH_DATA_COHERENCY_EN 0 0 MMSCH_VM 1 1 MMSCH_R_MC_SWAP 3 4 MMSCH_W_MC_SWAP 5 6 MMSCH_RD 7 8 MMSCH_WR 9 10 MMSCH_RD_DROP 11 11 MMSCH_WR_DROP 12 12 mmUVD_MMSCH_SOFT_RESET 0 0x654 3 0 1 MMSCH_RESET 0 0 TAP_SOFT_RESET 1 1 MMSCH_LOCK 31 31 mmUVD_LMI_ARB_CTRL2 0 0x662 6 0 1 CENC_RD_WAIT_EN 0 0 ATOMIC_WR_WAIT_EN 1 1 CENC_RD_MAX_BURST 2 5 ATOMIC_WR_MAX_BURST 6 9 MIF_RD_REQ_RET_MAX 10 19 MIF_WR_REQ_RET_MAX 20 31