744 mmMMSCH_UCODE_ADDR 0 0x0 2 0 0 UCODE_ADDR 2 13 UCODE_LOCK 31 31 mmMMSCH_UCODE_DATA 0 0x1 1 0 0 UCODE_DATA 0 31 mmMMSCH_SRAM_ADDR 0 0x2 2 0 0 SRAM_ADDR 2 12 SRAM_LOCK 31 31 mmMMSCH_SRAM_DATA 0 0x3 1 0 0 SRAM_DATA 0 31 mmMMSCH_VF_SRAM_OFFSET 0 0x4 2 0 0 VF_SRAM_OFFSET 2 12 VF_SRAM_NUM_DW_PER_VF 16 23 mmMMSCH_DB_SRAM_OFFSET 0 0x5 3 0 0 DB_SRAM_OFFSET 2 12 DB_SRAM_NUM_ENG 16 23 DB_SRAM_NUM_RING_PER_ENG 24 31 mmMMSCH_CTX_SRAM_OFFSET 0 0x6 2 0 0 CTX_SRAM_OFFSET 2 12 CTX_SRAM_SIZE 16 31 mmMMSCH_CTL 0 0x7 4 0 0 P_RUNSTALL 0 0 P_RESET 1 1 VFID_FIFO_EN 4 4 P_LOCK 31 31 mmMMSCH_INTR 0 0x8 1 0 0 INTR 0 12 mmMMSCH_INTR_ACK 0 0x9 1 0 0 INTR 0 12 mmMMSCH_INTR_STATUS 0 0xa 1 0 0 INTR 0 12 mmMMSCH_VF_VMID 0 0xb 2 0 0 VF_CTX_VMID 0 4 VF_GPCOM_VMID 5 9 mmMMSCH_VF_CTX_ADDR_LO 0 0xc 1 0 0 VF_CTX_ADDR_LO 6 31 mmMMSCH_VF_CTX_ADDR_HI 0 0xd 1 0 0 VF_CTX_ADDR_HI 0 31 mmMMSCH_VF_CTX_SIZE 0 0xe 1 0 0 VF_CTX_SIZE 0 31 mmMMSCH_VF_GPCOM_ADDR_LO 0 0xf 1 0 0 VF_GPCOM_ADDR_LO 6 31 mmMMSCH_VF_GPCOM_ADDR_HI 0 0x10 1 0 0 VF_GPCOM_ADDR_HI 0 31 mmMMSCH_VF_GPCOM_SIZE 0 0x11 1 0 0 VF_GPCOM_SIZE 0 31 mmMMSCH_VF_MAILBOX_HOST 0 0x12 1 0 0 DATA 0 31 mmMMSCH_VF_MAILBOX_RESP 0 0x13 1 0 0 RESP 0 31 mmMMSCH_VF_MAILBOX_0 0 0x14 1 0 0 DATA 0 31 mmMMSCH_VF_MAILBOX_0_RESP 0 0x15 1 0 0 RESP 0 31 mmMMSCH_VF_MAILBOX_1 0 0x16 1 0 0 DATA 0 31 mmMMSCH_VF_MAILBOX_1_RESP 0 0x17 1 0 0 RESP 0 31 mmMMSCH_CNTL 0 0x1c 7 0 0 CLK_EN 0 0 ED_ENABLE 1 1 MMSCH_IRQ_ERR 5 8 MMSCH_NACK_INTR_EN 9 9 MMSCH_DB_BUSY_INTR_EN 10 10 PRB_TIMEOUT_VAL 20 27 TIMEOUT_DIS 28 28 mmMMSCH_NONCACHE_OFFSET0 0 0x1d 1 0 0 OFFSET 0 27 mmMMSCH_NONCACHE_SIZE0 0 0x1e 1 0 0 SIZE 0 23 mmMMSCH_NONCACHE_OFFSET1 0 0x1f 1 0 0 OFFSET 0 27 mmMMSCH_NONCACHE_SIZE1 0 0x20 1 0 0 SIZE 0 23 mmMMSCH_PROC_STATE1 0 0x26 1 0 0 PC 0 31 mmMMSCH_LAST_MC_ADDR 0 0x27 2 0 0 MC_ADDR 0 27 RW 31 31 mmMMSCH_LAST_MEM_ACCESS_HI 0 0x28 3 0 0 PROC_CMD 0 2 FIFO_RPTR 8 10 FIFO_WPTR 12 14 mmMMSCH_LAST_MEM_ACCESS_LO 0 0x29 1 0 0 PROC_ADDR 0 31 mmMMSCH_IOV_ACTIVE_FCN_ID 0 0x2a 2 0 0 ACTIVE_VF_ID 0 4 ACTIVE_PF_VF 31 31 mmMMSCH_SCRATCH_0 0 0x2b 1 0 0 SCRATCH_0 0 31 mmMMSCH_SCRATCH_1 0 0x2c 1 0 0 SCRATCH_1 0 31 mmMMSCH_GPUIOV_SCH_BLOCK_0 0 0x2d 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_CONTROL_0 0 0x2e 6 0 0 CMD_TYPE 0 3 CMD_EXECUTE 4 4 CMD_EXECUTE_INTR_EN 5 5 VM_BUSY_INTR_EN 6 6 FUNCTINO_ID 8 15 NEXT_FUNCTINO_ID 16 23 mmMMSCH_GPUIOV_CMD_STATUS_0 0 0x2f 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_VM_BUSY_STATUS_0 0 0x30 1 0 0 BUSY 0 31 mmMMSCH_GPUIOV_ACTIVE_FCNS_0 0 0x31 1 0 0 ACTIVE_FCNS 0 31 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_0 0 0x32 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_GPUIOV_DW6_0 0 0x33 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW7_0 0 0x34 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW8_0 0 0x35 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_SCH_BLOCK_1 0 0x36 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_CONTROL_1 0 0x37 6 0 0 CMD_TYPE 0 3 CMD_EXECUTE 4 4 CMD_EXECUTE_INTR_EN 5 5 VM_BUSY_INTR_EN 6 6 FUNCTINO_ID 8 15 NEXT_FUNCTINO_ID 16 23 mmMMSCH_GPUIOV_CMD_STATUS_1 0 0x38 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_VM_BUSY_STATUS_1 0 0x39 1 0 0 BUSY 0 31 mmMMSCH_GPUIOV_ACTIVE_FCNS_1 0 0x3a 1 0 0 ACTIVE_FCNS 0 31 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_1 0 0x3b 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_GPUIOV_DW6_1 0 0x3c 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW7_1 0 0x3d 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW8_1 0 0x3e 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_CNTXT 0 0x3f 3 0 0 CNTXT_SIZE 0 6 CNTXT_LOCATION 7 7 CNTXT_OFFSET 10 31 mmMMSCH_SCRATCH_2 0 0x40 1 0 0 SCRATCH_2 0 31 mmMMSCH_SCRATCH_3 0 0x41 1 0 0 SCRATCH_3 0 31 mmMMSCH_SCRATCH_4 0 0x42 1 0 0 SCRATCH_4 0 31 mmMMSCH_SCRATCH_5 0 0x43 1 0 0 SCRATCH_5 0 31 mmMMSCH_SCRATCH_6 0 0x44 1 0 0 SCRATCH_6 0 31 mmMMSCH_SCRATCH_7 0 0x45 1 0 0 SCRATCH_7 0 31 mmMMSCH_VFID_FIFO_HEAD_0 0 0x46 1 0 0 HEAD 0 5 mmMMSCH_VFID_FIFO_TAIL_0 0 0x47 1 0 0 TAIL 0 5 mmMMSCH_VFID_FIFO_HEAD_1 0 0x48 1 0 0 HEAD 0 5 mmMMSCH_VFID_FIFO_TAIL_1 0 0x49 1 0 0 TAIL 0 5 mmMMSCH_NACK_STATUS 0 0x4a 2 0 0 WR_NACK_STATUS 0 1 RD_NACK_STATUS 2 3 mmMMSCH_VF_MAILBOX0_DATA 0 0x4b 1 0 0 DATA 0 31 mmMMSCH_VF_MAILBOX1_DATA 0 0x4c 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_SCH_BLOCK_IP_0 0 0x4d 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_STATUS_IP_0 0 0x4e 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 0 0x4f 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_GPUIOV_SCH_BLOCK_IP_1 0 0x50 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_STATUS_IP_1 0 0x51 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 0 0x52 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_GPUIOV_CNTXT_IP 0 0x53 2 0 0 CNTXT_SIZE 0 6 CNTXT_LOCATION 7 7 mmMMSCH_GPUIOV_SCH_BLOCK_2 0 0x54 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_CONTROL_2 0 0x55 6 0 0 CMD_TYPE 0 3 CMD_EXECUTE 4 4 CMD_EXECUTE_INTR_EN 5 5 VM_BUSY_INTR_EN 6 6 FUNCTINO_ID 8 15 NEXT_FUNCTINO_ID 16 23 mmMMSCH_GPUIOV_CMD_STATUS_2 0 0x56 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_VM_BUSY_STATUS_2 0 0x57 1 0 0 BUSY 0 31 mmMMSCH_GPUIOV_ACTIVE_FCNS_2 0 0x58 1 0 0 ACTIVE_FCNS 0 31 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_2 0 0x59 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_GPUIOV_DW6_2 0 0x5a 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW7_2 0 0x5b 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_DW8_2 0 0x5c 1 0 0 DATA 0 31 mmMMSCH_GPUIOV_SCH_BLOCK_IP_2 0 0x5d 3 0 0 ID 0 3 VERSION 4 7 SIZE 8 15 mmMMSCH_GPUIOV_CMD_STATUS_IP_2 0 0x5e 1 0 0 CMD_STATUS 0 3 mmMMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 0 0x5f 2 0 0 ID 0 7 ID_STATUS 8 11 mmMMSCH_VFID_FIFO_HEAD_2 0 0x60 1 0 0 HEAD 0 5 mmMMSCH_VFID_FIFO_TAIL_2 0 0x61 1 0 0 TAIL 0 5 mmMMSCH_VM_BUSY_STATUS_0 0 0x62 1 0 0 BUSY 0 31 mmMMSCH_VM_BUSY_STATUS_1 0 0x63 1 0 0 BUSY 0 31 mmMMSCH_VM_BUSY_STATUS_2 0 0x64 1 0 0 BUSY 0 31 mmUVD_JPEG_CNTL 0 0x80 4 0 0 REQUEST_EN 1 1 ERR_RST_EN 2 2 HUFF_SPEED_EN 3 3 HUFF_SPEED_STATUS 4 4 mmUVD_JPEG_RB_BASE 0 0x81 2 0 0 RB_BYTE_OFF 0 5 RB_BASE 6 31 mmUVD_JPEG_RB_WPTR 0 0x82 1 0 0 RB_WPTR 4 29 mmUVD_JPEG_RB_RPTR 0 0x83 1 0 0 RB_RPTR 4 29 mmUVD_JPEG_RB_SIZE 0 0x84 1 0 0 RB_SIZE 4 29 mmUVD_JPEG_DEC_CNT 0 0x85 1 0 0 DECODE_COUNT 0 31 mmUVD_JPEG_SPS_INFO 0 0x86 2 0 0 PIC_WIDTH 0 15 PIC_HEIGHT 16 31 mmUVD_JPEG_SPS1_INFO 0 0x87 3 0 0 CHROMA_FORMAT_IDC 0 2 YUV422_SUBFORMAT 3 3 OUT_FMT_422 4 4 mmUVD_JPEG_RE_TIMER 0 0x88 2 0 0 TIMER_OUT 0 7 TIMER_OUT_EN 16 16 mmUVD_JPEG_DEC_SCRATCH0 0 0x89 1 0 0 SCRATCH0 0 31 mmUVD_JPEG_INT_EN 0 0x8a 13 0 0 OUTBUF_WPTR_INC_EN 0 0 JOB_AVAIL_EN 1 1 FENCE_VAL_EN 2 2 FIFO_OVERFLOW_ERR_EN 6 6 BLK_CNT_OUT_OF_SYNC_ERR_EN 7 7 EOI_ERR_EN 8 8 HFM_ERR_EN 9 9 RST_ERR_EN 10 10 ECS_MK_ERR_EN 11 11 TIMEOUT_ERR_EN 12 12 MARKER_ERR_EN 13 13 FMT_ERR_EN 14 14 PROFILE_ERR_EN 15 15 mmUVD_JPEG_INT_STAT 0 0x8b 13 0 0 OUTBUF_WPTR_INC_INT 0 0 JOB_AVAIL_INT 1 1 FENCE_VAL_INT 2 2 FIFO_OVERFLOW_ERR_INT 6 6 BLK_CNT_OUT_OF_SYNC_ERR_INT 7 7 EOI_ERR_INT 8 8 HFM_ERR_INT 9 9 RST_ERR_INT 10 10 ECS_MK_ERR_INT 11 11 TIMEOUT_ERR_INT 12 12 MARKER_ERR_INT 13 13 FMT_ERR_INT 14 14 PROFILE_ERR_INT 15 15 mmUVD_JPEG_TIER_CNTL0 0 0x8d 13 0 0 TIER_SEL 0 1 Y_COMP_ID 2 3 U_COMP_ID 4 5 V_COMP_ID 6 7 Y_H_SAMP_FAC 8 10 Y_V_SAMP_FAC 11 13 U_H_SAMP_FAC 14 16 U_V_SAMP_FAC 17 19 V_H_SAMP_FAC 20 22 V_V_SAMP_FAC 23 25 Y_TQ 26 27 U_TQ 28 29 V_TQ 30 31 mmUVD_JPEG_TIER_CNTL1 0 0x8e 2 0 0 SRC_WIDTH 0 15 SRC_HEIGHT 16 31 mmUVD_JPEG_TIER_CNTL2 0 0x8f 9 0 0 TBL_ECS_SEL 0 0 TBL_TYPE 1 1 TQ 2 3 TH 4 5 TC 6 6 TD 7 9 TA 10 12 TIER2_HTBL_CNTLEN 14 14 DRI_VAL 16 31 mmUVD_JPEG_TIER_STATUS 0 0x90 2 0 0 BSI_FETCH_DONE 0 0 DECODE_DONE 1 1 mmUVD_JPEG_OUTBUF_CNTL 0 0x9c 5 0 0 OUTBUF_CNT 0 1 HGT_ALIGN 2 2 JPEG0_DECODE_DONE_FIX 6 6 JPEG0_WR_COMB_MAX_CNT 7 8 JPEG0_WR_COMB_TIMER 9 12 mmUVD_JPEG_OUTBUF_WPTR 0 0x9d 1 0 0 OUTBUF_WPTR 0 31 mmUVD_JPEG_OUTBUF_RPTR 0 0x9e 1 0 0 OUTBUF_RPTR 0 31 mmUVD_JPEG_PITCH 0 0x9f 1 0 0 PITCH 0 31 mmUVD_JPEG_UV_PITCH 0 0xa0 1 0 0 UV_PITCH 0 31 mmJPEG_DEC_Y_GFX10_TILING_SURFACE 0 0xa4 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_DEC_UV_GFX10_TILING_SURFACE 0 0xa5 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_DEC_GFX10_ADDR_CONFIG 0 0xa6 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 NUM_PKRS 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmJPEG_DEC_ADDR_MODE 0 0xa7 3 0 0 ADDR_MODE_Y 0 1 ADDR_MODE_UV 2 3 ADDR_LIB_SEL 12 14 mmUVD_JPEG_OUTPUT_XY 0 0xa8 2 0 0 OUTPUT_X 0 13 OUTPUT_Y 16 29 mmUVD_JPEG_GPCOM_CMD 0 0xa9 1 0 0 CMD 1 3 mmUVD_JPEG_GPCOM_DATA0 0 0xaa 1 0 0 DATA0 0 31 mmUVD_JPEG_GPCOM_DATA1 0 0xab 1 0 0 DATA1 0 31 mmUVD_JPEG_INDEX 0 0xac 1 0 0 INDEX 0 8 mmUVD_JPEG_DATA 0 0xad 1 0 0 DATA 0 31 mmUVD_JPEG_SCRATCH1 0 0xae 1 0 0 SCRATCH1 0 31 mmUVD_JPEG_DEC_SOFT_RST 0 0xaf 2 0 0 SOFT_RESET 0 0 RESET_STATUS 16 16 mmUVD_JPEG_ENC_SPS_INFO 0 0xe0 3 0 0 SRC_FORMAT 0 2 YUY2_SUBFORMAT 3 3 OUT_FMT_422 4 4 mmUVD_JPEG_ENC_SPS_INFO1 0 0xe1 2 0 0 SRC_WIDTH 0 15 SRC_HEIGHT 16 31 mmUVD_JPEG_ENC_TBL_SIZE 0 0xe2 1 0 0 TBL_SIZE 6 11 mmUVD_JPEG_ENC_TBL_CNTL 0 0xe3 4 0 0 TBL_PEL_SEL 0 0 TBL_TYPE 1 1 TBL_SUBTYPE 2 3 HTBL_CNTLEN 4 4 mmUVD_JPEG_ENC_MC_REQ_CNTL 0 0xe4 1 0 0 RD_REQ_PRIORITY_MARK 0 5 mmUVD_JPEG_ENC_STATUS 0 0xe5 4 0 0 PEL_FETCH_IDLE 0 0 HUFF_CORE_IDLE 1 1 FDCT_IDLE 2 2 SCALAR_IDLE 3 3 mmUVD_JPEG_ENC_PITCH 0 0xe6 2 0 0 PITCH_Y 0 11 PITCH_UV 16 27 mmUVD_JPEG_ENC_LUMA_BASE 0 0xe7 1 0 0 LUMA_BASE 0 31 mmUVD_JPEG_ENC_CHROMAU_BASE 0 0xe8 1 0 0 CHROMAU_BASE 0 31 mmUVD_JPEG_ENC_CHROMAV_BASE 0 0xe9 1 0 0 CHROMAV_BASE 0 31 mmJPEG_ENC_Y_GFX10_TILING_SURFACE 0 0xea 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_ENC_UV_GFX10_TILING_SURFACE 0 0xeb 1 0 0 SWIZZLE_MODE 0 4 mmJPEG_ENC_GFX10_ADDR_CONFIG 0 0xec 5 0 0 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 NUM_PKRS 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmJPEG_ENC_ADDR_MODE 0 0xed 3 0 0 ADDR_MODE_Y 0 1 ADDR_MODE_UV 2 3 ADDR_LIB_SEL 12 14 mmUVD_JPEG_ENC_GPCOM_CMD 0 0xee 1 0 0 CMD 1 3 mmUVD_JPEG_ENC_GPCOM_DATA0 0 0xef 1 0 0 DATA0 0 31 mmUVD_JPEG_ENC_GPCOM_DATA1 0 0xf0 1 0 0 DATA1 0 31 mmUVD_JPEG_TBL_DAT0 0 0xf1 1 0 0 TBL_DAT_31_0 0 31 mmUVD_JPEG_TBL_DAT1 0 0xf2 1 0 0 TBL_DAT_63_32 0 31 mmUVD_JPEG_TBL_IDX 0 0xf3 1 0 0 TBL_IDX 0 7 mmUVD_JPEG_ENC_CGC_CNTL 0 0xf5 1 0 0 CGC_EN 0 0 mmUVD_JPEG_ENC_SCRATCH0 0 0xf6 1 0 0 SCRATCH0 0 31 mmUVD_JPEG_ENC_SOFT_RST 0 0xf7 2 0 0 SOFT_RST 0 0 RESET_STATUS 16 16 mmUVD_JRBC_RB_WPTR 0 0x100 1 0 0 RB_WPTR 4 22 mmUVD_JRBC_RB_CNTL 0 0x101 3 0 0 RB_NO_FETCH 0 0 RB_RPTR_WR_EN 1 1 RB_PRE_WRITE_TIMER 4 18 mmUVD_JRBC_IB_SIZE 0 0x102 1 0 0 IB_SIZE 4 22 mmUVD_JRBC_URGENT_CNTL 0 0x103 1 0 0 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_JRBC_RB_REF_DATA 0 0x104 1 0 0 REF_DATA 0 31 mmUVD_JRBC_RB_COND_RD_TIMER 0 0x105 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_SOFT_RESET 0 0x108 2 0 0 RESET 0 0 SCLK_RESET_STATUS 17 17 mmUVD_JRBC_STATUS 0 0x109 15 0 0 RB_JOB_DONE 0 0 IB_JOB_DONE 1 1 RB_ILLEGAL_CMD 2 2 RB_COND_REG_RD_TIMEOUT 3 3 RB_MEM_WR_TIMEOUT 4 4 RB_MEM_RD_TIMEOUT 5 5 IB_ILLEGAL_CMD 6 6 IB_COND_REG_RD_TIMEOUT 7 7 IB_MEM_WR_TIMEOUT 8 8 IB_MEM_RD_TIMEOUT 9 9 RB_TRAP_STATUS 10 10 PREEMPT_STATUS 11 11 IB_TRAP_STATUS 12 12 INT_EN 16 16 INT_ACK 17 17 mmUVD_JRBC_RB_RPTR 0 0x10a 1 0 0 RB_RPTR 4 22 mmUVD_JRBC_RB_BUF_STATUS 0 0x10b 3 0 0 RB_BUF_VALID 0 15 RB_BUF_RD_ADDR 16 19 RB_BUF_WR_ADDR 24 25 mmUVD_JRBC_IB_BUF_STATUS 0 0x10c 3 0 0 IB_BUF_VALID 0 15 IB_BUF_RD_ADDR 16 19 IB_BUF_WR_ADDR 24 25 mmUVD_JRBC_IB_SIZE_UPDATE 0 0x10d 1 0 0 REMAIN_IB_SIZE 4 22 mmUVD_JRBC_IB_COND_RD_TIMER 0 0x10e 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_IB_REF_DATA 0 0x10f 1 0 0 REF_DATA 0 31 mmUVD_JPEG_PREEMPT_CMD 0 0x110 3 0 0 PREEMPT_EN 0 0 WAIT_JPEG_JOB_DONE 1 1 PREEMPT_FENCE_CMD 2 2 mmUVD_JPEG_PREEMPT_FENCE_DATA0 0 0x111 1 0 0 PREEMPT_FENCE_DATA0 0 31 mmUVD_JPEG_PREEMPT_FENCE_DATA1 0 0x112 1 0 0 PREEMPT_FENCE_DATA1 0 31 mmUVD_JRBC_RB_SIZE 0 0x113 1 0 0 RB_SIZE 4 23 mmUVD_JRBC_SCRATCH0 0 0x114 1 0 0 SCRATCH0 0 31 mmUVD_JRBC_ENC_RB_WPTR 0 0x120 1 0 0 RB_WPTR 4 22 mmUVD_JRBC_ENC_RB_CNTL 0 0x121 3 0 0 RB_NO_FETCH 0 0 RB_RPTR_WR_EN 1 1 RB_PRE_WRITE_TIMER 4 18 mmUVD_JRBC_ENC_IB_SIZE 0 0x122 1 0 0 IB_SIZE 4 22 mmUVD_JRBC_ENC_URGENT_CNTL 0 0x123 1 0 0 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_JRBC_ENC_RB_REF_DATA 0 0x124 1 0 0 REF_DATA 0 31 mmUVD_JRBC_ENC_RB_COND_RD_TIMER 0 0x125 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_ENC_SOFT_RESET 0 0x128 2 0 0 RESET 0 0 SCLK_RESET_STATUS 17 17 mmUVD_JRBC_ENC_STATUS 0 0x129 15 0 0 RB_JOB_DONE 0 0 IB_JOB_DONE 1 1 RB_ILLEGAL_CMD 2 2 RB_COND_REG_RD_TIMEOUT 3 3 RB_MEM_WR_TIMEOUT 4 4 RB_MEM_RD_TIMEOUT 5 5 IB_ILLEGAL_CMD 6 6 IB_COND_REG_RD_TIMEOUT 7 7 IB_MEM_WR_TIMEOUT 8 8 IB_MEM_RD_TIMEOUT 9 9 RB_TRAP_STATUS 10 10 PREEMPT_STATUS 11 11 IB_TRAP_STATUS 12 12 INT_EN 16 16 INT_ACK 17 17 mmUVD_JRBC_ENC_RB_RPTR 0 0x12a 1 0 0 RB_RPTR 4 22 mmUVD_JRBC_ENC_RB_BUF_STATUS 0 0x12b 3 0 0 RB_BUF_VALID 0 15 RB_BUF_RD_ADDR 16 19 RB_BUF_WR_ADDR 24 25 mmUVD_JRBC_ENC_IB_BUF_STATUS 0 0x12c 3 0 0 IB_BUF_VALID 0 15 IB_BUF_RD_ADDR 16 19 IB_BUF_WR_ADDR 24 25 mmUVD_JRBC_ENC_IB_SIZE_UPDATE 0 0x12d 1 0 0 REMAIN_IB_SIZE 4 22 mmUVD_JRBC_ENC_IB_COND_RD_TIMER 0 0x12e 4 0 0 RETRY_TIMER_CNT 0 15 RETRY_INTERVAL_CNT 16 23 CONTINUOUS_POLL_EN 24 24 MEM_TIMEOUT_EN 25 25 mmUVD_JRBC_ENC_IB_REF_DATA 0 0x12f 1 0 0 REF_DATA 0 31 mmUVD_JPEG_ENC_PREEMPT_CMD 0 0x130 3 0 0 PREEMPT_EN 0 0 WAIT_JPEG_JOB_DONE 1 1 PREEMPT_FENCE_CMD 2 2 mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0 0 0x131 1 0 0 PREEMPT_FENCE_DATA0 0 31 mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1 0 0x132 1 0 0 PREEMPT_FENCE_DATA1 0 31 mmUVD_JRBC_ENC_RB_SIZE 0 0x133 1 0 0 RB_SIZE 4 23 mmUVD_JRBC_ENC_SCRATCH0 0 0x134 1 0 0 SCRATCH0 0 31 mmUVD_JADP_MCIF_URGENT_CTRL 0 0x141 7 0 0 WR_WATERMARK 0 5 RD_WATERMARK 6 10 WR_RD_URGENT_TIMER 11 16 WR_URGENT_PROG_STEP 17 20 RD_URGENT_PROG_STEP 21 24 WR_QOS_EN 25 25 RD_QOS_EN 26 26 mmUVD_JMI_URGENT_CTRL 0 0x142 4 0 0 ENABLE_MC_RD_URGENT_STALL 0 0 ASSERT_MC_RD_URGENT 4 7 ENABLE_MC_WR_URGENT_STALL 16 16 ASSERT_MC_WR_URGENT 20 23 mmUVD_JPEG_DEC_PF_CTRL 0 0x143 2 0 0 DEC_PF_HANDLING_DIS 0 0 DEC_PF_SW_GATING 1 1 mmUVD_JPEG_ENC_PF_CTRL 0 0x144 2 0 0 ENC_PF_HANDLING_DIS 0 0 ENC_PF_SW_GATING 1 1 mmUVD_JMI_CTRL 0 0x145 7 0 0 STALL_MC_ARB 0 0 MASK_MC_URGENT 1 1 ASSERT_MC_URGENT 2 2 MC_RD_ARB_WAIT_TIMER 8 15 MC_WR_ARB_WAIT_TIMER 16 23 CRC_RESET 24 24 CRC_SEL 25 28 mmUVD_LMI_JRBC_CTRL 0 0x146 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_LMI_JPEG_CTRL 0 0x147 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_JMI_EJRBC_CTRL 0 0x148 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_LMI_EJPEG_CTRL 0 0x149 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_JMI_SCALER_CTRL 0 0x14a 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmJPEG_LMI_DROP 0 0x14b 4 0 0 JPEG_WR_DROP 0 0 JRBC_WR_DROP 1 1 JPEG_RD_DROP 2 2 JRBC_RD_DROP 3 3 mmUVD_JMI_EJPEG_DROP 0 0x14c 6 0 0 EJRBC_RD_DROP 0 0 EJRBC_WR_DROP 1 1 EJPEG_RD_DROP 2 2 EJPEG_WR_DROP 3 3 SCALAR_RD_DROP 4 4 SCALAR_WR_DROP 5 5 mmJPEG_MEMCHECK_CLAMPING 0 0x14d 7 0 0 JPEG_WR_CLAMPING_EN 13 13 JPEG2_WR_CLAMPING_EN 14 14 JPEG_RD_CLAMPING_EN 22 22 JPEG2_RD_CLAMPING_EN 23 23 JRBC_RD_CLAMPING_EN 25 25 JRBC_WR_CLAMPING_EN 26 26 CLAMP_TO_SAFE_ADDR_EN 31 31 mmUVD_JMI_EJPEG_MEMCHECK_CLAMPING 0 0x14e 7 0 0 JRBC_RD_CLAMPING_EN 0 0 JRBC_WR_CLAMPING_EN 1 1 JPEG_RD_CLAMPING_EN 2 2 JPEG_WR_CLAMPING_EN 3 3 SCALAR_RD_CLAMPING_EN 4 4 SCALAR_WR_CLAMPING_EN 5 5 CLAMP_TO_SAFE_ADDR_EN 31 31 mmUVD_LMI_JRBC_IB_VMID 0 0x14f 3 0 0 IB_WR_VMID 0 3 IB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_LMI_JRBC_RB_VMID 0 0x150 3 0 0 RB_WR_VMID 0 3 RB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_LMI_JPEG_VMID 0 0x151 3 0 0 JPEG_RD_VMID 0 3 JPEG_WR_VMID 4 7 ATOMIC_USER0_WR_VMID 8 11 mmUVD_JMI_ENC_JRBC_IB_VMID 0 0x152 3 0 0 IB_WR_VMID 0 3 IB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_JMI_ENC_JRBC_RB_VMID 0 0x153 3 0 0 RB_WR_VMID 0 3 RB_RD_VMID 4 7 MEM_RD_VMID 8 11 mmUVD_JMI_ENC_JPEG_VMID 0 0x154 6 0 0 PEL_RD_VMID 0 3 BS_WR_VMID 5 8 SCALAR_RD_VMID 10 13 SCALAR_WR_VMID 15 18 HUFF_FENCE_VMID 19 22 ATOMIC_USER1_WR_VMID 23 26 mmJPEG_MEMCHECK_SAFE_ADDR 0 0x157 1 0 0 MEMCHECK_SAFE_ADDR 0 31 mmJPEG_MEMCHECK_SAFE_ADDR_64BIT 0 0x158 1 0 0 MEMCHECK_SAFE_ADDR_64BIT 0 31 mmUVD_JMI_LAT_CTRL 0 0x159 6 0 0 SCALE 0 7 MAX_START 8 8 MIN_START 9 9 AVG_START 10 10 PERFMON_SYNC 11 11 SKIP 16 19 mmUVD_JMI_LAT_CNTR 0 0x15a 2 0 0 MAX_LAT 0 7 MIN_LAT 8 15 mmUVD_JMI_AVG_LAT_CNTR 0 0x15b 3 0 0 ENV_LOW 0 7 ENV_HIGH 8 15 ENV_HIT 16 31 mmUVD_JMI_PERFMON_CTRL 0 0x15c 2 0 0 PERFMON_STATE 0 1 PERFMON_SEL 8 11 mmUVD_JMI_PERFMON_COUNT_LO 0 0x15d 1 0 0 PERFMON_COUNT 0 31 mmUVD_JMI_PERFMON_COUNT_HI 0 0x15e 1 0 0 PERFMON_COUNT 0 15 mmUVD_JMI_CLEAN_STATUS 0 0x15f 17 0 0 LMI_READ_CLEAN 0 0 LMI_READ_CLEAN_RAW 1 1 LMI_WRITE_CLEAN 2 2 LMI_WRITE_CLEAN_RAW 3 3 DJRBC_READ_CLEAN 4 4 EJRBC_READ_CLEAN 5 5 JPEG_READ_CLEAN 6 6 PEL_READ_CLEAN 7 7 SCALAR_READ_CLEAN 8 8 DJRBC_WRITE_CLEAN 9 9 EJRBC_WRITE_CLEAN 10 10 BS_WRITE_CLEAN 11 11 JPEG_WRITE_CLEAN 12 12 SCALAR_WRITE_CLEAN 13 13 MC_WRITE_PENDING 14 14 JPEG2_WRITE_CLEAN 15 15 JPEG2_READ_CLEAN 16 16 mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0 0x160 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0 0x161 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0 0x162 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0 0x163 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0 0x164 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0 0x165 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0 0x166 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0 0x167 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0 0x168 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0 0x169 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0 0x16a 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0 0x16b 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0 0x16c 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0 0x16d 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0 0x16e 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0 0x16f 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 0 0x170 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 0 0x171 1 0 0 BITS_63_32 0 31 mmUVD_JMI_PEL_RD_64BIT_BAR_LOW 0 0x172 1 0 0 BITS_31_0 0 31 mmUVD_JMI_PEL_RD_64BIT_BAR_HIGH 0 0x173 1 0 0 BITS_63_32 0 31 mmUVD_JMI_BS_WR_64BIT_BAR_LOW 0 0x174 1 0 0 BITS_31_0 0 31 mmUVD_JMI_BS_WR_64BIT_BAR_HIGH 0 0x175 1 0 0 BITS_63_32 0 31 mmUVD_JMI_SCALAR_RD_64BIT_BAR_LOW 0 0x176 1 0 0 BITS_31_0 0 31 mmUVD_JMI_SCALAR_RD_64BIT_BAR_HIGH 0 0x177 1 0 0 BITS_63_32 0 31 mmUVD_JMI_SCALAR_WR_64BIT_BAR_LOW 0 0x178 1 0 0 BITS_31_0 0 31 mmUVD_JMI_SCALAR_WR_64BIT_BAR_HIGH 0 0x179 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0 0x17a 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0 0x17b 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW 0 0x17c 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 0 0x17d 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW 0 0x17e 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 0 0x17f 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 0 0x180 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 0 0x181 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 0 0x182 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 0 0x183 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 0 0x184 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 0 0x185 1 0 0 BITS_63_32 0 31 mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 0 0x186 1 0 0 BITS_31_0 0 31 mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 0 0x187 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_PREEMPT_VMID 0 0x188 1 0 0 VMID 0 3 mmUVD_LMI_ENC_JPEG_PREEMPT_VMID 0 0x189 1 0 0 VMID 0 3 mmUVD_LMI_JPEG2_VMID 0 0x18a 2 0 0 JPEG2_RD_VMID 0 3 JPEG2_WR_VMID 4 7 mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW 0 0x18b 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 0 0x18c 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 0 0x18d 1 0 0 BITS_31_0 0 31 mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 0 0x18e 1 0 0 BITS_63_32 0 31 mmUVD_LMI_JPEG_CTRL2 0 0x18f 6 0 0 ARB_RD_WAIT_EN 0 0 ARB_WR_WAIT_EN 1 1 RD_MAX_BURST 4 7 WR_MAX_BURST 8 11 RD_SWAP 20 21 WR_SWAP 22 23 mmUVD_JMI_DEC_SWAP_CNTL 0 0x190 9 0 0 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_MEM_WR_MC_SWAP 4 5 IB_MEM_WR_MC_SWAP 6 7 RB_MEM_RD_MC_SWAP 8 9 IB_MEM_RD_MC_SWAP 10 11 PREEMPT_WR_MC_SWAP 12 13 JPEG_RD_MC_SWAP 14 15 JPEG_WR_MC_SWAP 16 17 mmUVD_JMI_ENC_SWAP_CNTL 0 0x191 12 0 0 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_MEM_WR_MC_SWAP 4 5 IB_MEM_WR_MC_SWAP 6 7 RB_MEM_RD_MC_SWAP 8 9 IB_MEM_RD_MC_SWAP 10 11 PREEMPT_WR_MC_SWAP 12 13 PEL_RD_MC_SWAP 14 15 BS_WR_MC_SWAP 16 17 SCALAR_RD_MC_SWAP 18 19 SCALAR_WR_MC_SWAP 20 21 HUFF_FENCE_MC_SWAP 22 23 mmUVD_JMI_CNTL 0 0x192 2 0 0 SOFT_RESET 0 0 MC_RD_REQ_RET_MAX 8 17 mmUVD_JMI_ATOMIC_CNTL 0 0x193 6 0 0 atomic_arb_wait_en 0 0 atomic_max_burst 1 4 atomic_wr_drop 5 5 atomic_wr_clamping_en 6 6 ATOMIC_WR_URG 7 10 ATOMIC_SW_GATE 11 11 mmUVD_JMI_ATOMIC_CNTL2 0 0x194 2 0 0 atomic_uvd_swap 16 23 ATOMIC_MC_SWAP 24 31 mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0 0x195 1 0 0 BITS_31_0 0 31 mmUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0 0x196 1 0 0 BITS_63_32 0 31 mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_LOW 0 0x197 1 0 0 BITS_31_0 0 31 mmUVD_JMI_ATOMIC_USER1_WRITE_64BIT_BAR_HIGH 0 0x198 1 0 0 BITS_63_32 0 31 mmJPEG2_LMI_DROP 0 0x199 2 0 0 JPEG2_WR_DROP 0 0 JPEG2_RD_DROP 1 1 mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 0 0x19a 1 0 0 BITS_31_0 0 31 mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 0 0x19b 1 0 0 BITS_63_32 0 31 mmUVD_JMI_DEC_SWAP_CNTL2 0 0x19c 2 0 0 JPEG2_RD_MC_SWAP 0 1 JPEG2_WR_MC_SWAP 2 3 mmUVD_JPEG_DEC2_PF_CTRL 0 0x19f 2 0 0 DEC2_PF_HANDLING_DIS 0 0 DEC2_PF_SW_GATING 1 1 mmJPEG_SOFT_RESET_STATUS 0 0x1c0 6 0 0 JPEG_DEC_RESET_STATUS 0 0 JPEG2_DEC_RESET_STATUS 1 1 DJRBC_RESET_STATUS 2 2 JPEG_ENC_RESET_STATUS 3 3 EJRBC_RESET_STATUS 4 4 JMCIF_RESET_STATUS 5 5 mmJPEG_SYS_INT_EN 0 0x1c1 8 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 DJPEG2_PF_RPT 7 7 mmJPEG_SYS_INT_STATUS 0 0x1c2 8 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 DJPEG2_PF_RPT 7 7 mmJPEG_SYS_INT_ACK 0 0x1c3 8 0 0 DJPEG_CORE 0 0 DJRBC 1 1 DJPEG_PF_RPT 2 2 EJPEG_PF_RPT 3 3 EJPEG_CORE 4 4 EJRBC 5 5 DJPEG_CORE2 6 6 DJPEG2_PF_RPT 7 7 mmJPEG_MEMCHECK_SYS_INT_EN 0 0x1c4 12 0 0 DJRBC_RD_ERR_EN 0 0 EJRBC_RD_ERR_EN 1 1 BSFETCH_RD_ERR_EN 2 2 PELFETCH_RD_ERR_EN 3 3 SCALAR_RD_ERR_EN 4 4 JPEG2_RD_ERR_EN 5 5 DJRBC_WR_ERR_EN 6 6 EJRBC_WR_ERR_EN 7 7 BS_WR_ERR_EN 8 8 OBUF_WR_ERR_EN 9 9 SCALAR_WR_ERR_EN 10 10 JPEG2_WR_ERR_EN 11 11 mmJPEG_MEMCHECK_SYS_INT_STAT 0 0x1c5 24 0 0 DJRBC_RD_HI_ERR 0 0 DJRBC_RD_LO_ERR 1 1 EJRBC_RD_HI_ERR 2 2 EJRBC_RD_LO_ERR 3 3 BSFETCH_RD_HI_ERR 4 4 BSFETCH_RD_LO_ERR 5 5 PELFETCH_RD_HI_ERR 6 6 PELFETCH_RD_LO_ERR 7 7 SCALAR_RD_HI_ERR 8 8 SCALAR_RD_LO_ERR 9 9 JPEG2_RD_HI_ERR 10 10 JPEG2_RD_LO_ERR 11 11 DJRBC_WR_HI_ERR 12 12 DJRBC_WR_LO_ERR 13 13 EJRBC_WR_HI_ERR 14 14 EJRBC_WR_LO_ERR 15 15 BS_WR_HI_ERR 16 16 BS_WR_LO_ERR 17 17 OBUF_WR_HI_ERR 18 18 OBUF_WR_LO_ERR 19 19 SCALAR_WR_HI_ERR 20 20 SCALAR_WR_LO_ERR 21 21 JPEG2_WR_HI_ERR 22 22 JPEG2_WR_LO_ERR 23 23 mmJPEG_MEMCHECK_SYS_INT_ACK 0 0x1c6 24 0 0 DJRBC_RD_HI_ERR 0 0 DJRBC_RD_LO_ERR 1 1 EJRBC_RD_HI_ERR 2 2 EJRBC_RD_LO_ERR 3 3 BSFETCH_RD_HI_ERR 4 4 BSFETCH_RD_LO_ERR 5 5 PELFETCH_RD_HI_ERR 6 6 PELFETCH_RD_LO_ERR 7 7 SCALAR_RD_HI_ERR 8 8 SCALAR_RD_LO_ERR 9 9 JPEG2_RD_HI_ERR 10 10 JPEG2_RD_LO_ERR 11 11 DJRBC_WR_HI_ERR 12 12 DJRBC_WR_LO_ERR 13 13 EJRBC_WR_HI_ERR 14 14 EJRBC_WR_LO_ERR 15 15 BS_WR_HI_ERR 16 16 BS_WR_LO_ERR 17 17 OBUF_WR_HI_ERR 18 18 OBUF_WR_LO_ERR 19 19 SCALAR_WR_HI_ERR 20 20 SCALAR_WR_LO_ERR 21 21 JPEG2_WR_HI_ERR 22 22 JPEG2_WR_LO_ERR 23 23 mmUVD_JPEG_IOV_ACTIVE_FCN_ID 0 0x1c7 2 0 0 VF_ID 0 5 PF_VF 31 31 mmJPEG_MASTINT_EN 0 0x1c8 2 0 0 OVERRUN_RST 0 0 INT_OVERRUN 4 22 mmJPEG_IH_CTRL 0 0x1c9 6 0 0 IH_SOFT_RESET 0 0 IH_STALL_EN 1 1 IH_STATUS_CLEAN 2 2 IH_VMID 3 6 IH_USER_DATA 7 18 IH_RINGID 19 26 mmJRBBM_ARB_CTRL 0 0x1cb 3 0 0 DJRBC_DROP 0 0 EJRBC_DROP 1 1 SRBM_DROP 2 2 mmJPEG_CGC_GATE 0 0x1e0 5 0 0 JPEG_DEC 0 0 JPEG2_DEC 1 1 JPEG_ENC 2 2 JMCIF 3 3 JRBBM 4 4 mmJPEG_CGC_CTRL 0 0x1e1 11 0 0 DYN_CLOCK_MODE 0 0 CLK_GATE_DLY_TIMER 1 4 CLK_OFF_DELAY 5 9 DYN_OCLK_RAMP_EN 10 10 DYN_RCLK_RAMP_EN 11 11 GATER_DIV_ID 12 14 JPEG_DEC_MODE 16 16 JPEG2_DEC_MODE 17 17 JPEG_ENC_MODE 18 18 JMCIF_MODE 19 19 JRBBM_MODE 20 20 mmJPEG_CGC_STATUS 0 0x1e2 9 0 0 JPEG_DEC_VCLK_ACTIVE 0 0 JPEG_DEC_SCLK_ACTIVE 1 1 JPEG2_DEC_VCLK_ACTIVE 2 2 JPEG2_DEC_SCLK_ACTIVE 3 3 JPEG_ENC_VCLK_ACTIVE 4 4 JPEG_ENC_SCLK_ACTIVE 5 5 JMCIF_SCLK_ACTIVE 6 6 JRBBM_VCLK_ACTIVE 7 7 JRBBM_SCLK_ACTIVE 8 8 mmJPEG_COMN_CGC_MEM_CTRL 0 0x1e3 5 0 0 JMCIF_LS_EN 0 0 JMCIF_DS_EN 1 1 JMCIF_SD_EN 2 2 LS_SET_DELAY 16 19 LS_CLEAR_DELAY 20 23 mmJPEG_DEC_CGC_MEM_CTRL 0 0x1e4 3 0 0 JPEG_DEC_LS_EN 0 0 JPEG_DEC_DS_EN 1 1 JPEG_DEC_SD_EN 2 2 mmJPEG2_DEC_CGC_MEM_CTRL 0 0x1e5 3 0 0 JPEG2_DEC_LS_EN 0 0 JPEG2_DEC_DS_EN 1 1 JPEG2_DEC_SD_EN 2 2 mmJPEG_ENC_CGC_MEM_CTRL 0 0x1e6 3 0 0 JPEG_ENC_LS_EN 0 0 JPEG_ENC_DS_EN 1 1 JPEG_ENC_SD_EN 2 2 mmJPEG_SOFT_RESET2 0 0x1e7 1 0 0 ATOMIC_SOFT_RESET 0 0 mmJPEG_PERF_BANK_CONF 0 0x1e8 3 0 0 RESET 0 3 PEEK 8 11 CONCATENATE 16 17 mmJPEG_PERF_BANK_EVENT_SEL 0 0x1e9 4 0 0 SEL0 0 7 SEL1 8 15 SEL2 16 23 SEL3 24 31 mmJPEG_PERF_BANK_COUNT0 0 0x1ea 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT1 0 0x1eb 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT2 0 0x1ec 1 0 0 COUNT 0 31 mmJPEG_PERF_BANK_COUNT3 0 0x1ed 1 0 0 COUNT 0 31 mmUVD_PGFSM_CONFIG 0 0x0 15 0 1 UVDM_PWR_CONFIG 0 1 UVDU_PWR_CONFIG 2 3 UVDF_PWR_CONFIG 4 5 UVDC_PWR_CONFIG 6 7 UVDB_PWR_CONFIG 8 9 UVDIRL_PWR_CONFIG 10 11 UVDLM_PWR_CONFIG 12 13 UVDTD_PWR_CONFIG 14 15 UVDTE_PWR_CONFIG 16 17 UVDE_PWR_CONFIG 18 19 UVDAB_PWR_CONFIG 20 21 UVDJ_PWR_CONFIG 22 23 UVDATD_PWR_CONFIG 24 25 UVDNA_PWR_CONFIG 26 27 UVDNB_PWR_CONFIG 28 29 mmUVD_PGFSM_STATUS 0 0x1 15 0 1 UVDM_PWR_STATUS 0 1 UVDU_PWR_STATUS 2 3 UVDF_PWR_STATUS 4 5 UVDC_PWR_STATUS 6 7 UVDB_PWR_STATUS 8 9 UVDIRL_PWR_STATUS 10 11 UVDLM_PWR_STATUS 12 13 UVDTD_PWR_STATUS 14 15 UVDTE_PWR_STATUS 16 17 UVDE_PWR_STATUS 18 19 UVDAB_PWR_STATUS 20 21 UVDJ_PWR_STATUS 22 23 UVDATD_PWR_STATUS 24 25 UVDNA_PWR_STATUS 26 27 UVDNB_PWR_STATUS 28 29 mmUVD_POWER_STATUS 0 0x4 7 0 1 UVD_POWER_STATUS 0 1 UVD_PG_MODE 2 2 UVD_CG_MODE 4 5 UVD_PG_EN 8 8 RBC_SNOOP_DIS 9 9 SW_RB_SNOOP_DIS 11 11 STALL_DPG_POWER_UP 31 31 mmUVD_PG_IND_INDEX 0 0x5 1 0 1 INDEX 0 5 mmUVD_PG_IND_DATA 0 0x6 1 0 1 DATA 0 31 mmCC_UVD_HARVESTING 0 0x7 2 0 1 MMSCH_DISABLE 0 0 UVD_DISABLE 1 1 mmUVD_JPEG_POWER_STATUS 0 0xa 5 0 1 JPEG_POWER_STATUS 0 0 JPEG_PG_MODE 4 4 JRBC_DEC_SNOOP_DIS 8 8 JRBC_ENC_SNOOP_DIS 9 9 STALL_JDPG_POWER_UP 31 31 mmUVD_MC_DJPEG_RD_SPACE 0 0xd 1 0 1 DJPEG_RD_SPACE 0 17 mmUVD_MC_DJPEG_WR_SPACE 0 0xe 1 0 1 DJPEG_WR_SPACE 0 17 mmUVD_MC_EJPEG_RD_SPACE 0 0xf 1 0 1 EJPEG_RD_SPACE 0 17 mmUVD_MC_EJPEG_WR_SPACE 0 0x10 1 0 1 EJPEG_WR_SPACE 0 17 mmUVD_DPG_LMA_CTL 0 0x11 5 0 1 READ_WRITE 0 0 MASK_EN 1 1 ADDR_AUTO_INCREMENT 2 2 SRAM_SEL 4 4 READ_WRITE_ADDR 16 31 mmUVD_DPG_LMA_DATA 0 0x12 1 0 1 LMA_DATA 0 31 mmUVD_DPG_LMA_MASK 0 0x13 1 0 1 LMA_MASK 0 31 mmUVD_DPG_PAUSE 0 0x14 4 0 1 JPEG_PAUSE_DPG_REQ 0 0 JPEG_PAUSE_DPG_ACK 1 1 NJ_PAUSE_DPG_REQ 2 2 NJ_PAUSE_DPG_ACK 3 3 mmUVD_SCRATCH1 0 0x15 1 0 1 SCRATCH1_DATA 0 31 mmUVD_SCRATCH2 0 0x16 1 0 1 SCRATCH2_DATA 0 31 mmUVD_SCRATCH3 0 0x17 1 0 1 SCRATCH3_DATA 0 31 mmUVD_SCRATCH4 0 0x18 1 0 1 SCRATCH4_DATA 0 31 mmUVD_SCRATCH5 0 0x19 1 0 1 SCRATCH5_DATA 0 31 mmUVD_SCRATCH6 0 0x1a 1 0 1 SCRATCH6_DATA 0 31 mmUVD_SCRATCH7 0 0x1b 1 0 1 SCRATCH7_DATA 0 31 mmUVD_SCRATCH8 0 0x1c 1 0 1 SCRATCH8_DATA 0 31 mmUVD_SCRATCH9 0 0x1d 1 0 1 SCRATCH9_DATA 0 31 mmUVD_SCRATCH10 0 0x1e 1 0 1 SCRATCH10_DATA 0 31 mmUVD_SCRATCH11 0 0x1f 1 0 1 SCRATCH11_DATA 0 31 mmUVD_SCRATCH12 0 0x20 1 0 1 SCRATCH12_DATA 0 31 mmUVD_SCRATCH13 0 0x21 1 0 1 SCRATCH13_DATA 0 31 mmUVD_SCRATCH14 0 0x22 1 0 1 SCRATCH14_DATA 0 31 mmUVD_FREE_COUNTER_REG 0 0x24 1 0 1 FREE_COUNTER 0 31 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0x25 1 0 1 BITS_31_0 0 31 mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0x26 1 0 1 BITS_63_32 0 31 mmUVD_DPG_VCPU_CACHE_OFFSET0 0 0x27 1 0 1 CACHE_OFFSET0 0 24 mmUVD_DPG_LMI_VCPU_CACHE_VMID 0 0x28 1 0 1 VCPU_CACHE_VMID 0 3 mmUVD_REG_FILTER_EN 0 0x29 4 0 1 UVD_REG_FILTER_EN 0 0 MMSCH_HI_PRIV 1 1 VIDEO_PRIV_EN 2 2 JPEG_PRIV_EN 3 3 mmCC_UVD_VCPU_ERR_DETECT_BOT_LO 0 0x31 1 0 1 UVD_VCPU_ERR_DETECT_BOT_LO 12 31 mmCC_UVD_VCPU_ERR_DETECT_BOT_HI 0 0x32 1 0 1 UVD_VCPU_ERR_DETECT_BOT_HI 0 15 mmCC_UVD_VCPU_ERR_DETECT_TOP_LO 0 0x33 1 0 1 UVD_VCPU_ERR_DETECT_TOP_LO 12 31 mmCC_UVD_VCPU_ERR_DETECT_TOP_HI 0 0x34 1 0 1 UVD_VCPU_ERR_DETECT_TOP_HI 0 15 mmCC_UVD_VCPU_ERR 0 0x35 4 0 1 UVD_VCPU_ERR_STATUS 0 0 UVD_VCPU_ERR_CLEAR 1 1 UVD_VCPU_ERR_DETECT_EN 2 2 RESET_ON_FAULT 4 4 mmCC_UVD_VCPU_ERR_INST_ADDR_LO 0 0x36 1 0 1 UVD_VCPU_ERR_INST_ADDR_LO 0 31 mmCC_UVD_VCPU_ERR_INST_ADDR_HI 0 0x37 1 0 1 UVD_VCPU_ERR_INST_ADDR_HI 0 15 mmUVD_PF_STATUS 0 0x39 24 0 1 JPEG_PF_OCCURED 0 0 NJ_PF_OCCURED 1 1 ENCODER0_PF_OCCURED 2 2 ENCODER1_PF_OCCURED 3 3 ENCODER2_PF_OCCURED 4 4 ENCODER3_PF_OCCURED 5 5 ENCODER4_PF_OCCURED 6 6 EJPEG_PF_OCCURED 7 7 JPEG_PF_CLEAR 8 8 NJ_PF_CLEAR 9 9 ENCODER0_PF_CLEAR 10 10 ENCODER1_PF_CLEAR 11 11 ENCODER2_PF_CLEAR 12 12 ENCODER3_PF_CLEAR 13 13 ENCODER4_PF_CLEAR 14 14 EJPEG_PF_CLEAR 15 15 NJ_ATM_PF_OCCURED 16 16 DJ_ATM_PF_OCCURED 17 17 EJ_ATM_PF_OCCURED 18 18 JPEG2_PF_OCCURED 19 19 DJ2_ATM_PF_OCCURED 20 20 JPEG2_PF_CLEAR 21 21 ENCODER5_PF_OCCURED 22 22 ENCODER5_PF_CLEAR 23 23 mmUVD_FW_VERSION 0 0x3a 1 0 1 FW_VERSION 0 31 mmUVD_DPG_CLK_EN_VCPU_REPORT 0 0x3c 2 0 1 CLK_EN 0 0 VCPU_REPORT 1 7 mmUVD_SECURITY_REG_VIO_REPORT 0 0x3f 6 0 1 HOST_REG_VIO 0 0 VCPU_REG_VIO 1 1 VIDEO_REG_VIO 2 2 DPG_REG_VIO 3 3 JPEG_REG_VIO 4 4 JDPG_REG_VIO 5 5 mmUVD_LMI_MMSCH_NC_SPACE 0 0x45 8 0 1 MMSCH_NC0_SPACE 0 2 MMSCH_NC1_SPACE 3 5 MMSCH_NC2_SPACE 6 8 MMSCH_NC3_SPACE 9 11 MMSCH_NC4_SPACE 12 14 MMSCH_NC5_SPACE 15 17 MMSCH_NC6_SPACE 18 20 MMSCH_NC7_SPACE 21 23 mmUVD_LMI_ATOMIC_SPACE 0 0x46 4 0 1 ATOMIC_USER0_SPACE 0 2 ATOMIC_USER1_SPACE 3 5 ATOMIC_USER2_SPACE 6 8 ATOMIC_USER3_SPACE 9 11 mmUVD_GFX10_ADDR_CONFIG 0 0x4a 6 0 1 NUM_PIPES 0 2 PIPE_INTERLEAVE_SIZE 3 5 MAX_COMPRESSED_FRAGS 6 7 NUM_PKRS 8 10 NUM_BANKS 12 14 NUM_SHADER_ENGINES 19 20 mmUVD_GPCNT2_CNTL 0 0x4b 3 0 1 CLR 0 0 START 1 1 COUNTUP 2 2 mmUVD_GPCNT2_TARGET_LOWER 0 0x4c 1 0 1 TARGET 0 31 mmUVD_GPCNT2_STATUS_LOWER 0 0x4d 1 0 1 COUNT 0 31 mmUVD_GPCNT2_TARGET_UPPER 0 0x4e 1 0 1 TARGET 0 15 mmUVD_GPCNT2_STATUS_UPPER 0 0x4f 1 0 1 COUNT 0 15 mmUVD_GPCNT3_CNTL 0 0x50 5 0 1 CLR 0 0 START 1 1 COUNTUP 2 2 FREQ 3 9 DIV 10 16 mmUVD_GPCNT3_TARGET_LOWER 0 0x51 1 0 1 TARGET 0 31 mmUVD_GPCNT3_STATUS_LOWER 0 0x52 1 0 1 COUNT 0 31 mmUVD_GPCNT3_TARGET_UPPER 0 0x53 1 0 1 TARGET 0 15 mmUVD_GPCNT3_STATUS_UPPER 0 0x54 1 0 1 COUNT 0 15 mmUVD_VCLK_DS_CNTL 0 0x55 3 0 1 VCLK_DS_EN 0 0 VCLK_DS_STATUS 4 4 VCLK_DS_HYSTERESIS_CNT 16 31 mmUVD_DCLK_DS_CNTL 0 0x56 3 0 1 DCLK_DS_EN 0 0 DCLK_DS_STATUS 4 4 DCLK_DS_HYSTERESIS_CNT 16 31 mmUVD_TSC_LOWER 0 0x57 1 0 1 COUNT 0 31 mmUVD_TSC_UPPER 0 0x58 1 0 1 COUNT 0 23 mmVCN_FEATURES 0 0x59 15 0 1 HAS_VIDEO_DEC 0 0 HAS_VIDEO_ENC 1 1 HAS_MJPEG_DEC 2 2 HAS_MJPEG_ENC 3 3 HAS_VIDEO_VIRT 4 4 HAS_H264_LEGACY_DEC 5 5 HAS_UDEC_DEC 6 6 HAS_MJPEG2_IDCT_DEC 7 7 HAS_SCLR_DEC 8 8 HAS_VP9_DEC 9 9 HAS_AV1_DEC 10 10 HAS_EFC_ENC 11 11 HAS_EFC_HDR2SDR_ENC 12 12 HAS_DUAL_MJPEG_DEC 13 13 INSTANCE_ID 28 31 mmUVD_GPUIOV_STATUS 0 0x5d 1 0 1 UVD_GPUIOV_STATUS_VF_ENABLE 0 0 mmUVD_STATUS 0 0x80 4 0 1 RBC_BUSY 0 0 VCPU_REPORT 1 7 RBC_ACCESS_GPCOM 16 16 SYS_GPCOM_REQ 31 31 mmUVD_ENC_PIPE_BUSY 0 0x81 26 0 1 IME_BUSY 0 0 SMP_BUSY 1 1 SIT_BUSY 2 2 SDB_BUSY 3 3 ENT_BUSY 4 4 ENT_HEADER_BUSY 5 5 LCM_BUSY 6 6 MDM_RD_CUR_BUSY 7 7 MDM_RD_REF_BUSY 8 8 MDM_WR_RECON_BUSY 10 10 MIF_RD_CUR_BUSY 16 16 MIF_RD_REF0_BUSY 17 17 MIF_WR_GEN0_BUSY 18 18 MIF_RD_GEN0_BUSY 19 19 MIF_WR_GEN1_BUSY 20 20 MIF_RD_GEN1_BUSY 21 21 MIF_WR_BSP0_BUSY 22 22 MIF_WR_BSP1_BUSY 23 23 MIF_RD_BSD0_BUSY 24 24 MIF_RD_BSD1_BUSY 25 25 MIF_RD_BSD2_BUSY 26 26 MIF_RD_BSD3_BUSY 27 27 MIF_RD_BSD4_BUSY 28 28 MIF_WR_BSP2_BUSY 29 29 MIF_WR_BSP3_BUSY 30 30 SAOE_BUSY 31 31 mmUVD_FW_POWER_STATUS 0 0x82 11 0 1 UVDF_PWR_OFF 0 0 UVDC_PWR_OFF 1 1 UVDB_PWR_OFF 2 2 UVDIRL_PWR_OFF 3 3 UVDTD_PWR_OFF 4 4 UVDTE_PWR_OFF 5 5 UVDE_PWR_OFF 6 6 UVDAB_PWR_OFF 7 7 UVDATD_PWR_OFF 8 8 UVDNA_PWR_OFF 9 9 UVDNB_PWR_OFF 10 10 mmUVD_CNTL 0 0x83 4 0 1 MIF_WR_LOW_THRESHOLD_BP 17 17 SUVD_EN 19 19 CABAC_MB_ACC 28 28 LRBBM_SAFE_SYNC_DIS 31 31 mmUVD_SOFT_RESET 0 0x84 31 0 1 RBC_SOFT_RESET 0 0 LBSI_SOFT_RESET 1 1 LMI_SOFT_RESET 2 2 VCPU_SOFT_RESET 3 3 UDEC_SOFT_RESET 4 4 CXW_SOFT_RESET 6 6 TAP_SOFT_RESET 7 7 MPC_SOFT_RESET 8 8 EFC_SOFT_RESET 9 9 IH_SOFT_RESET 10 10 MPRD_SOFT_RESET 11 11 IDCT_SOFT_RESET 12 12 LMI_UMC_SOFT_RESET 13 13 SPH_SOFT_RESET 14 14 MIF_SOFT_RESET 15 15 LCM_SOFT_RESET 16 16 SUVD_SOFT_RESET 17 17 LBSI_VCLK_RESET_STATUS 18 18 VCPU_VCLK_RESET_STATUS 19 19 UDEC_VCLK_RESET_STATUS 20 20 UDEC_DCLK_RESET_STATUS 21 21 MPC_DCLK_RESET_STATUS 22 22 MPRD_VCLK_RESET_STATUS 23 23 MPRD_DCLK_RESET_STATUS 24 24 IDCT_VCLK_RESET_STATUS 25 25 MIF_DCLK_RESET_STATUS 26 26 LCM_DCLK_RESET_STATUS 27 27 SUVD_VCLK_RESET_STATUS 28 28 SUVD_DCLK_RESET_STATUS 29 29 RE_DCLK_RESET_STATUS 30 30 SRE_DCLK_RESET_STATUS 31 31 mmUVD_SOFT_RESET2 0 0x85 3 0 1 ATOMIC_SOFT_RESET 0 0 MMSCH_VCLK_RESET_STATUS 16 16 MMSCH_SCLK_RESET_STATUS 17 17 mmUVD_MMSCH_SOFT_RESET 0 0x86 3 0 1 MMSCH_RESET 0 0 TAP_SOFT_RESET 1 1 MMSCH_LOCK 31 31 mmUVD_WIG_CTRL 0 0x87 5 0 1 AVM_SOFT_RESET 0 0 ACAP_SOFT_RESET 1 1 WIG_SOFT_RESET 2 2 WIG_REGCLK_FORCE_ON 3 3 AVM_REGCLK_FORCE_ON 4 4 mmUVD_CGC_GATE 0 0x88 20 0 1 SYS 0 0 UDEC 1 1 MPEG2 2 2 REGS 3 3 RBC 4 4 LMI_MC 5 5 LMI_UMC 6 6 IDCT 7 7 MPRD 8 8 MPC 9 9 LBSI 10 10 LRBBM 11 11 UDEC_RE 12 12 UDEC_CM 13 13 UDEC_IT 14 14 UDEC_DB 15 15 UDEC_MP 16 16 WCB 17 17 VCPU 18 18 MMSCH 20 20 mmUVD_CGC_STATUS 0 0x89 31 0 1 SYS_SCLK 0 0 SYS_DCLK 1 1 SYS_VCLK 2 2 UDEC_SCLK 3 3 UDEC_DCLK 4 4 UDEC_VCLK 5 5 MPEG2_SCLK 6 6 MPEG2_DCLK 7 7 MPEG2_VCLK 8 8 REGS_SCLK 9 9 REGS_VCLK 10 10 RBC_SCLK 11 11 LMI_MC_SCLK 12 12 LMI_UMC_SCLK 13 13 IDCT_SCLK 14 14 IDCT_VCLK 15 15 MPRD_SCLK 16 16 MPRD_DCLK 17 17 MPRD_VCLK 18 18 MPC_SCLK 19 19 MPC_DCLK 20 20 LBSI_SCLK 21 21 LBSI_VCLK 22 22 LRBBM_SCLK 23 23 WCB_SCLK 24 24 VCPU_SCLK 25 25 VCPU_VCLK 26 26 MMSCH_SCLK 27 27 MMSCH_VCLK 28 28 ALL_ENC_ACTIVE 29 29 ALL_DEC_ACTIVE 31 31 mmUVD_CGC_CTRL 0 0x8a 23 0 1 DYN_CLOCK_MODE 0 0 CLK_GATE_DLY_TIMER 2 5 CLK_OFF_DELAY 6 10 UDEC_RE_MODE 11 11 UDEC_CM_MODE 12 12 UDEC_IT_MODE 13 13 UDEC_DB_MODE 14 14 UDEC_MP_MODE 15 15 SYS_MODE 16 16 UDEC_MODE 17 17 MPEG2_MODE 18 18 REGS_MODE 19 19 RBC_MODE 20 20 LMI_MC_MODE 21 21 LMI_UMC_MODE 22 22 IDCT_MODE 23 23 MPRD_MODE 24 24 MPC_MODE 25 25 LBSI_MODE 26 26 LRBBM_MODE 27 27 WCB_MODE 28 28 VCPU_MODE 29 29 MMSCH_MODE 31 31 mmUVD_CGC_UDEC_STATUS 0 0x8b 15 0 1 RE_SCLK 0 0 RE_DCLK 1 1 RE_VCLK 2 2 CM_SCLK 3 3 CM_DCLK 4 4 CM_VCLK 5 5 IT_SCLK 6 6 IT_DCLK 7 7 IT_VCLK 8 8 DB_SCLK 9 9 DB_DCLK 10 10 DB_VCLK 11 11 MP_SCLK 12 12 MP_DCLK 13 13 MP_VCLK 14 14 mmUVD_SUVD_CGC_GATE 0 0x8c 32 0 1 SRE 0 0 SIT 1 1 SMP 2 2 SCM 3 3 SDB 4 4 SRE_H264 5 5 SRE_HEVC 6 6 SIT_H264 7 7 SIT_HEVC 8 8 SCM_H264 9 9 SCM_HEVC 10 10 SDB_H264 11 11 SDB_HEVC 12 12 SCLR 13 13 UVD_SC 14 14 ENT 15 15 IME 16 16 SIT_HEVC_DEC 17 17 SIT_HEVC_ENC 18 18 SITE 19 19 SRE_VP9 20 20 SCM_VP9 21 21 SIT_VP9_DEC 22 22 SDB_VP9 23 23 IME_HEVC 24 24 EFC 25 25 SAOE 26 26 SRE_AV1 27 27 FBC_PCLK 28 28 FBC_CCLK 29 29 SCM_AV1 30 30 SMPA 31 31 mmUVD_SUVD_CGC_STATUS 0 0x8d 32 0 1 SRE_VCLK 0 0 SRE_DCLK 1 1 SIT_DCLK 2 2 SMP_DCLK 3 3 SCM_DCLK 4 4 SDB_DCLK 5 5 SRE_H264_VCLK 6 6 SRE_HEVC_VCLK 7 7 SIT_H264_DCLK 8 8 SIT_HEVC_DCLK 9 9 SCM_H264_DCLK 10 10 SCM_HEVC_DCLK 11 11 SDB_H264_DCLK 12 12 SDB_HEVC_DCLK 13 13 SCLR_DCLK 14 14 UVD_SC 15 15 ENT_DCLK 16 16 IME_DCLK 17 17 SIT_HEVC_DEC_DCLK 18 18 SIT_HEVC_ENC_DCLK 19 19 SITE_DCLK 20 20 SITE_HEVC_DCLK 21 21 SITE_HEVC_ENC_DCLK 22 22 SRE_VP9_VCLK 23 23 SCM_VP9_VCLK 24 24 SIT_VP9_DEC_DCLK 25 25 SDB_VP9_DCLK 26 26 IME_HEVC_DCLK 27 27 EFC_DCLK 28 28 SAOE_DCLK 29 29 SRE_AV1_VCLK 30 30 SCM_AV1_DCLK 31 31 mmUVD_SUVD_CGC_CTRL 0 0x8e 20 0 1 SRE_MODE 0 0 SIT_MODE 1 1 SMP_MODE 2 2 SCM_MODE 3 3 SDB_MODE 4 4 SCLR_MODE 5 5 UVD_SC_MODE 6 6 ENT_MODE 7 7 IME_MODE 8 8 SITE_MODE 9 9 EFC_MODE 10 10 SAOE_MODE 11 11 SMPA_MODE 12 12 MPBE0_MODE 13 13 MPBE1_MODE 14 14 SIT_AV1_MODE 15 15 SDB_AV1_MODE 16 16 MPC1_MODE 17 17 FBC_PCLK 28 28 FBC_CCLK 29 29 mmUVD_GPCOM_VCPU_CMD 0 0x8f 3 0 1 CMD_SEND 0 0 CMD 1 30 CMD_SOURCE 31 31 mmUVD_GPCOM_VCPU_DATA0 0 0x90 1 0 1 DATA0 0 31 mmUVD_GPCOM_VCPU_DATA1 0 0x91 1 0 1 DATA1 0 31 mmUVD_GPCOM_SYS_CMD 0 0x92 3 0 1 CMD_SEND 0 0 CMD 1 30 CMD_SOURCE 31 31 mmUVD_GPCOM_SYS_DATA0 0 0x93 1 0 1 DATA0 0 31 mmUVD_GPCOM_SYS_DATA1 0 0x94 1 0 1 DATA1 0 31 mmUVD_VCPU_INT_EN 0 0x95 28 0 1 PIF_ADDR_ERR_EN 0 0 SEMA_WAIT_FAULT_TIMEOUT_EN 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN 2 2 NJ_PF_RPT_EN 3 3 SW_RB1_INT_EN 4 4 SW_RB2_INT_EN 5 5 RBC_REG_PRIV_FAULT_EN 6 6 SW_RB3_INT_EN 7 7 SW_RB4_INT_EN 9 9 SW_RB5_INT_EN 10 10 LBSI_EN 11 11 UDEC_EN 12 12 SUVD_EN 15 15 RPTR_WR_EN 16 16 JOB_START_EN 17 17 NJ_PF_EN 18 18 CNN_3D_BLOCK_DONE_INT_EN 19 19 CNN_MIF_DMA_DONE_INT_EN 21 21 CNN_FEATURE_THRESHOLD_DONE_INT_EN 22 22 SEMA_WAIT_FAIL_SIG_EN 23 23 IDCT_EN 24 24 MPRD_EN 25 25 AVM_INT_EN 26 26 CLK_SWT_EN 27 27 MIF_HWINT_EN 28 28 MPRD_ERR_EN 29 29 DRV_FW_REQ_EN 30 30 DRV_FW_ACK_EN 31 31 mmUVD_VCPU_INT_STATUS 0 0x96 29 0 1 PIF_ADDR_ERR_INT 0 0 SEMA_WAIT_FAULT_TIMEOUT_INT 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT 2 2 NJ_PF_RPT_INT 3 3 SW_RB1_INT 4 4 SW_RB2_INT 5 5 RBC_REG_PRIV_FAULT_INT 6 6 SW_RB3_INT 7 7 SW_RB4_INT 9 9 SW_RB5_INT 10 10 LBSI_INT 11 11 UDEC_INT 12 12 SUVD_INT 15 15 RPTR_WR_INT 16 16 JOB_START_INT 17 17 NJ_PF_INT 18 18 CNN_3D_BLOCK_DONE_INT 19 19 GPCOM_INT 20 20 CNN_MIF_DMA_DONE_INT 21 21 CNN_FEATURE_THRESHOLD_DONE_INT 22 22 SEMA_WAIT_FAIL_SIG_INT 23 23 IDCT_INT 24 24 MPRD_INT 25 25 AVM_INT 26 26 CLK_SWT_INT 27 27 MIF_HWINT 28 28 MPRD_ERR_INT 29 29 DRV_FW_REQ_INT 30 30 DRV_FW_ACK_INT 31 31 mmUVD_VCPU_INT_ACK 0 0x97 28 0 1 PIF_ADDR_ERR_ACK 0 0 SEMA_WAIT_FAULT_TIMEOUT_ACK 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK 2 2 NJ_PF_RPT_ACK 3 3 SW_RB1_INT_ACK 4 4 SW_RB2_INT_ACK 5 5 RBC_REG_PRIV_FAULT_ACK 6 6 SW_RB3_INT_ACK 7 7 SW_RB4_INT_ACK 9 9 SW_RB5_INT_ACK 10 10 LBSI_ACK 11 11 UDEC_ACK 12 12 SUVD_ACK 15 15 RPTR_WR_ACK 16 16 JOB_START_ACK 17 17 NJ_PF_ACK 18 18 CNN_3D_BLOCK_DONE_INT_ACK 19 19 CNN_MIF_DMA_DONE_INT_ACK 21 21 CNN_FEATURE_THRESHOLD_DONE_INT_ACK 22 22 SEMA_WAIT_FAIL_SIG_ACK 23 23 IDCT_ACK 24 24 MPRD_ACK 25 25 AVM_INT_ACK 26 26 CLK_SWT_ACK 27 27 MIF_HWINT_ACK 28 28 MPRD_ERR_ACK 29 29 DRV_FW_REQ_ACK 30 30 DRV_FW_ACK_ACK 31 31 mmUVD_VCPU_INT_ROUTE 0 0x98 3 0 1 DRV_FW_MSG 0 0 FW_DRV_MSG_ACK 1 1 VCPU_GPCOM 2 2 mmUVD_DRV_FW_MSG 0 0x99 1 0 1 MSG 0 31 mmUVD_FW_DRV_MSG_ACK 0 0x9a 1 0 1 ACK 0 0 mmUVD_SUVD_INT_EN 0 0x9b 11 0 1 SRE_FUNC_INT_EN 0 4 SRE_ERR_INT_EN 5 5 SIT_FUNC_INT_EN 6 10 SIT_ERR_INT_EN 11 11 SMP_FUNC_INT_EN 12 16 SMP_ERR_INT_EN 17 17 SCM_FUNC_INT_EN 18 22 SCM_ERR_INT_EN 23 23 SDB_FUNC_INT_EN 24 28 SDB_ERR_INT_EN 29 29 FBC_ERR_INT_EN 30 30 mmUVD_SUVD_INT_STATUS 0 0x9c 11 0 1 SRE_FUNC_INT 0 4 SRE_ERR_INT 5 5 SIT_FUNC_INT 6 10 SIT_ERR_INT 11 11 SMP_FUNC_INT 12 16 SMP_ERR_INT 17 17 SCM_FUNC_INT 18 22 SCM_ERR_INT 23 23 SDB_FUNC_INT 24 28 SDB_ERR_INT 29 29 FBC_ERR_INT 30 30 mmUVD_SUVD_INT_ACK 0 0x9d 11 0 1 SRE_FUNC_INT_ACK 0 4 SRE_ERR_INT_ACK 5 5 SIT_FUNC_INT_ACK 6 10 SIT_ERR_INT_ACK 11 11 SMP_FUNC_INT_ACK 12 16 SMP_ERR_INT_ACK 17 17 SCM_FUNC_INT_ACK 18 22 SCM_ERR_INT_ACK 23 23 SDB_FUNC_INT_ACK 24 28 SDB_ERR_INT_ACK 29 29 FBC_ERR_INT_ACK 30 30 mmUVD_ENC_VCPU_INT_EN 0 0x9e 3 0 1 DCE_UVD_SCAN_IN_BUFMGR_EN 0 0 DCE_UVD_SCAN_IN_BUFMGR2_EN 1 1 DCE_UVD_SCAN_IN_BUFMGR3_EN 2 2 mmUVD_ENC_VCPU_INT_STATUS 0 0x9f 3 0 1 DCE_UVD_SCAN_IN_BUFMGR_INT 0 0 DCE_UVD_SCAN_IN_BUFMGR2_INT 1 1 DCE_UVD_SCAN_IN_BUFMGR3_INT 2 2 mmUVD_ENC_VCPU_INT_ACK 0 0xa0 3 0 1 DCE_UVD_SCAN_IN_BUFMGR_ACK 0 0 DCE_UVD_SCAN_IN_BUFMGR2_ACK 1 1 DCE_UVD_SCAN_IN_BUFMGR3_ACK 2 2 mmUVD_MASTINT_EN 0 0xa1 4 0 1 OVERRUN_RST 0 0 VCPU_EN 1 1 SYS_EN 2 2 INT_OVERRUN 4 22 mmUVD_SYS_INT_EN 0 0xa2 16 0 1 PIF_ADDR_ERR_EN 0 0 SEMA_WAIT_FAULT_TIMEOUT_EN 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN 2 2 CXW_WR_EN 3 3 RBC_REG_PRIV_FAULT_EN 6 6 LBSI_EN 11 11 UDEC_EN 12 12 SUVD_EN 15 15 JOB_DONE_EN 16 16 SEMA_WAIT_FAIL_SIG_EN 23 23 IDCT_EN 24 24 MPRD_EN 25 25 CLK_SWT_EN 27 27 MIF_HWINT_EN 28 28 MPRD_ERR_EN 29 29 AVM_INT_EN 31 31 mmUVD_SYS_INT_STATUS 0 0xa3 17 0 1 PIF_ADDR_ERR_INT 0 0 SEMA_WAIT_FAULT_TIMEOUT_INT 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT 2 2 CXW_WR_INT 3 3 RBC_REG_PRIV_FAULT_INT 6 6 LBSI_INT 11 11 UDEC_INT 12 12 SUVD_INT 15 15 JOB_DONE_INT 16 16 GPCOM_INT 18 18 SEMA_WAIT_FAIL_SIG_INT 23 23 IDCT_INT 24 24 MPRD_INT 25 25 CLK_SWT_INT 27 27 MIF_HWINT 28 28 MPRD_ERR_INT 29 29 AVM_INT 31 31 mmUVD_SYS_INT_ACK 0 0xa4 16 0 1 PIF_ADDR_ERR_ACK 0 0 SEMA_WAIT_FAULT_TIMEOUT_ACK 1 1 SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK 2 2 CXW_WR_ACK 3 3 RBC_REG_PRIV_FAULT_ACK 6 6 LBSI_ACK 11 11 UDEC_ACK 12 12 SUVD_ACK 15 15 JOB_DONE_ACK 16 16 SEMA_WAIT_FAIL_SIG_ACK 23 23 IDCT_ACK 24 24 MPRD_ACK 25 25 CLK_SWT_ACK 27 27 MIF_HWINT_ACK 28 28 MPRD_ERR_ACK 29 29 AVM_INT_ACK 31 31 mmUVD_JOB_DONE 0 0xa5 1 0 1 JOB_DONE 0 1 mmUVD_CBUF_ID 0 0xa6 1 0 1 CBUF_ID 0 31 mmUVD_CONTEXT_ID 0 0xa7 1 0 1 CONTEXT_ID 0 31 mmUVD_CONTEXT_ID2 0 0xa8 1 0 1 CONTEXT_ID2 0 31 mmUVD_NO_OP 0 0xa9 1 0 1 NO_OP 0 31 mmUVD_RB_BASE_LO 0 0xaa 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI 0 0xab 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE 0 0xac 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR 0 0xad 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR 0 0xae 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO2 0 0xaf 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI2 0 0xb0 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE2 0 0xb1 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR2 0 0xb2 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR2 0 0xb3 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO3 0 0xb4 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI3 0 0xb5 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE3 0 0xb6 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR3 0 0xb7 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR3 0 0xb8 1 0 1 RB_WPTR 4 22 mmUVD_RB_BASE_LO4 0 0xb9 1 0 1 RB_BASE_LO 6 31 mmUVD_RB_BASE_HI4 0 0xba 1 0 1 RB_BASE_HI 0 31 mmUVD_RB_SIZE4 0 0xbb 1 0 1 RB_SIZE 4 22 mmUVD_RB_RPTR4 0 0xbc 1 0 1 RB_RPTR 4 22 mmUVD_RB_WPTR4 0 0xbd 1 0 1 RB_WPTR 4 22 mmUVD_OUT_RB_BASE_LO 0 0xbe 1 0 1 RB_BASE_LO 6 31 mmUVD_OUT_RB_BASE_HI 0 0xbf 1 0 1 RB_BASE_HI 0 31 mmUVD_OUT_RB_SIZE 0 0xc0 1 0 1 RB_SIZE 4 22 mmUVD_OUT_RB_RPTR 0 0xc1 1 0 1 RB_RPTR 4 22 mmUVD_OUT_RB_WPTR 0 0xc2 1 0 1 RB_WPTR 4 22 mmUVD_IOV_ACTIVE_FCN_ID 0 0xc3 2 0 1 VF_ID 0 5 PF_VF 31 31 mmUVD_IOV_MAILBOX 0 0xc4 1 0 1 MAILBOX 0 31 mmUVD_IOV_MAILBOX_RESP 0 0xc5 1 0 1 RESP 0 31 mmUVD_RB_ARB_CTRL 0 0xc6 9 0 1 SRBM_DROP 0 0 SRBM_DIS 1 1 VCPU_DROP 2 2 VCPU_DIS 3 3 RBC_DROP 4 4 RBC_DIS 5 5 FWOFLD_DROP 6 6 FWOFLD_DIS 7 7 FAST_PATH_EN 8 8 mmUVD_CTX_INDEX 0 0xc7 1 0 1 INDEX 0 8 mmUVD_CTX_DATA 0 0xc8 1 0 1 DATA 0 31 mmUVD_CXW_WR 0 0xc9 2 0 1 DAT 0 27 STAT 31 31 mmUVD_CXW_WR_INT_ID 0 0xca 1 0 1 ID 0 7 mmUVD_CXW_WR_INT_CTX_ID 0 0xcb 1 0 1 ID 0 27 mmUVD_CXW_INT_ID 0 0xcc 1 0 1 ID 0 7 mmUVD_MPEG2_ERROR 0 0xcd 1 0 1 STATUS 0 31 mmUVD_TOP_CTRL 0 0xcf 2 0 1 STANDARD 0 3 STD_VERSION 4 7 mmUVD_YBASE 0 0xd0 1 0 1 DUM 0 31 mmUVD_UVBASE 0 0xd1 1 0 1 DUM 0 31 mmUVD_PITCH 0 0xd2 1 0 1 DUM 0 31 mmUVD_WIDTH 0 0xd3 1 0 1 DUM 0 31 mmUVD_HEIGHT 0 0xd4 1 0 1 DUM 0 31 mmUVD_PICCOUNT 0 0xd5 1 0 1 DUM 0 31 mmUVD_MPRD_INITIAL_XY 0 0xd6 2 0 1 MPRD_SCREEN_X 0 11 MPRD_SCREEN_Y 16 27 mmUVD_MPEG2_CTRL 0 0xd7 3 0 1 EN 0 0 TRICK_MODE 1 1 NUM_MB_PER_JOB 16 31 mmUVD_MB_CTL_BUF_BASE 0 0xd8 1 0 1 BASE 0 31 mmUVD_PIC_CTL_BUF_BASE 0 0xd9 1 0 1 BASE 0 31 mmUVD_DXVA_BUF_SIZE 0 0xda 2 0 1 PIC_SIZE 0 15 MB_SIZE 16 31 mmUVD_SCRATCH_NP 0 0xdb 1 0 1 DATA 0 31 mmUVD_CLK_SWT_HANDSHAKE 0 0xdc 2 0 1 CLK_SWT_TYPE 0 1 CLK_DOMAIN_SWT 8 9 mmUVD_VERSION 0 0xdd 4 0 1 VARIANT_TYPE 0 7 MINOR_VERSION 8 15 MAJOR_VERSION 16 27 INSTANCE_ID 28 31 mmUVD_GP_SCRATCH0 0 0xde 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH1 0 0xdf 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH2 0 0xe0 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH3 0 0xe1 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH4 0 0xe2 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH5 0 0xe3 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH6 0 0xe4 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH7 0 0xe5 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH8 0 0xe6 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH9 0 0xe7 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH10 0 0xe8 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH11 0 0xe9 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH12 0 0xea 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH13 0 0xeb 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH14 0 0xec 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH15 0 0xed 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH16 0 0xee 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH17 0 0xef 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH18 0 0xf0 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH19 0 0xf1 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH20 0 0xf2 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH21 0 0xf3 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH22 0 0xf4 1 0 1 DATA 0 31 mmUVD_GP_SCRATCH23 0 0xf5 1 0 1 DATA 0 31 mmUVD_AUDIO_RB_BASE_LO 0 0xf6 1 0 1 RB_BASE_LO 6 31 mmUVD_AUDIO_RB_BASE_HI 0 0xf7 1 0 1 RB_BASE_HI 0 31 mmUVD_AUDIO_RB_SIZE 0 0xf8 1 0 1 RB_SIZE 4 22 mmUVD_AUDIO_RB_RPTR 0 0xf9 1 0 1 RB_RPTR 4 22 mmUVD_AUDIO_RB_WPTR 0 0xfa 1 0 1 RB_WPTR 4 22 mmUVD_VCPU_INT_STATUS2 0 0xfb 1 0 1 SW_RB6_INT 0 0 mmUVD_VCPU_INT_ACK2 0 0xfc 1 0 1 SW_RB6_INT_ACK 0 0 mmUVD_VCPU_INT_EN2 0 0xfd 1 0 1 SW_RB6_INT_EN 0 0 mmUVD_SUVD_CGC_STATUS2 0 0xfe 10 0 1 SMPA_VCLK 0 0 SMPA_DCLK 1 1 MPBE1_DCLK 3 3 SIT_AV1_DCLK 4 4 SDB_AV1_DCLK 5 5 MPC1_DCLK 6 6 MPC1_SCLK 7 7 MPC1_VCLK 8 8 FBC_PCLK 28 28 FBC_CCLK 29 29 mmUVD_SUVD_CGC_GATE2 0 0xff 5 0 1 MPBE0 0 0 MPBE1 1 1 SIT_AV1 2 2 SDB_AV1 3 3 MPC1 4 4 mmUVD_SUVD_INT_STATUS2 0 0x100 4 0 1 SMPA_FUNC_INT 0 4 SMPA_ERR_INT 5 5 SDB_AV1_FUNC_INT 6 10 SDB_AV1_ERR_INT 11 11 mmUVD_SUVD_INT_EN2 0 0x101 4 0 1 SMPA_FUNC_INT_EN 0 4 SMPA_ERR_INT_EN 5 5 SDB_AV1_FUNC_INT_EN 6 10 SDB_AV1_ERR_INT_EN 11 11 mmUVD_SUVD_INT_ACK2 0 0x102 4 0 1 SMPA_FUNC_INT_ACK 0 4 SMPA_ERR_INT_ACK 5 5 SDB_AV1_FUNC_INT_ACK 6 10 SDB_AV1_ERR_INT_ACK 11 11 mmUVD_VCPU_CACHE_OFFSET0 0 0x140 1 0 1 CACHE_OFFSET0 0 20 mmUVD_VCPU_CACHE_SIZE0 0 0x141 1 0 1 CACHE_SIZE0 0 20 mmUVD_VCPU_CACHE_OFFSET1 0 0x142 1 0 1 CACHE_OFFSET1 0 20 mmUVD_VCPU_CACHE_SIZE1 0 0x143 1 0 1 CACHE_SIZE1 0 20 mmUVD_VCPU_CACHE_OFFSET2 0 0x144 1 0 1 CACHE_OFFSET2 0 20 mmUVD_VCPU_CACHE_SIZE2 0 0x145 1 0 1 CACHE_SIZE2 0 20 mmUVD_VCPU_CACHE_OFFSET3 0 0x146 1 0 1 CACHE_OFFSET3 0 20 mmUVD_VCPU_CACHE_SIZE3 0 0x147 1 0 1 CACHE_SIZE3 0 20 mmUVD_VCPU_CACHE_OFFSET4 0 0x148 1 0 1 CACHE_OFFSET4 0 20 mmUVD_VCPU_CACHE_SIZE4 0 0x149 1 0 1 CACHE_SIZE4 0 20 mmUVD_VCPU_CACHE_OFFSET5 0 0x14a 1 0 1 CACHE_OFFSET5 0 20 mmUVD_VCPU_CACHE_SIZE5 0 0x14b 1 0 1 CACHE_SIZE5 0 20 mmUVD_VCPU_CACHE_OFFSET6 0 0x14c 1 0 1 CACHE_OFFSET6 0 20 mmUVD_VCPU_CACHE_SIZE6 0 0x14d 1 0 1 CACHE_SIZE6 0 20 mmUVD_VCPU_CACHE_OFFSET7 0 0x14e 1 0 1 CACHE_OFFSET7 0 20 mmUVD_VCPU_CACHE_SIZE7 0 0x14f 1 0 1 CACHE_SIZE7 0 20 mmUVD_VCPU_CACHE_OFFSET8 0 0x150 1 0 1 CACHE_OFFSET8 0 20 mmUVD_VCPU_CACHE_SIZE8 0 0x151 1 0 1 CACHE_SIZE8 0 20 mmUVD_VCPU_NONCACHE_OFFSET0 0 0x152 1 0 1 NONCACHE_OFFSET0 0 24 mmUVD_VCPU_NONCACHE_SIZE0 0 0x153 1 0 1 NONCACHE_SIZE0 0 20 mmUVD_VCPU_NONCACHE_OFFSET1 0 0x154 1 0 1 NONCACHE_OFFSET1 0 24 mmUVD_VCPU_NONCACHE_SIZE1 0 0x155 1 0 1 NONCACHE_SIZE1 0 20 mmUVD_VCPU_CNTL 0 0x156 13 0 1 IRQ_ERR 0 3 PMB_ED_ENABLE 5 5 PMB_SOFT_RESET 6 6 RBBM_SOFT_RESET 7 7 ABORT_REQ 8 8 CLK_EN 9 9 TRCE_EN 10 10 TRCE_MUX 11 12 JTAG_EN 16 16 TIMEOUT_DIS 18 18 PRB_TIMEOUT_VAL 20 27 BLK_RST 28 28 RUNSTALL 29 29 mmUVD_VCPU_PRID 0 0x157 1 0 1 PRID 0 15 mmUVD_VCPU_TRCE 0 0x158 1 0 1 PC 0 27 mmUVD_VCPU_TRCE_RD 0 0x159 1 0 1 DATA 0 31 mmUVD_VCPU_IND_INDEX 0 0x15b 1 0 1 INDEX 0 8 mmUVD_VCPU_IND_DATA 0 0x15c 1 0 1 DATA 0 31 mmUVD_MP_SWAP_CNTL 0 0x2c4 16 0 1 MP_REF0_MC_SWAP 0 1 MP_REF1_MC_SWAP 2 3 MP_REF2_MC_SWAP 4 5 MP_REF3_MC_SWAP 6 7 MP_REF4_MC_SWAP 8 9 MP_REF5_MC_SWAP 10 11 MP_REF6_MC_SWAP 12 13 MP_REF7_MC_SWAP 14 15 MP_REF8_MC_SWAP 16 17 MP_REF9_MC_SWAP 18 19 MP_REF10_MC_SWAP 20 21 MP_REF11_MC_SWAP 22 23 MP_REF12_MC_SWAP 24 25 MP_REF13_MC_SWAP 26 27 MP_REF14_MC_SWAP 28 29 MP_REF15_MC_SWAP 30 31 mmUVD_MP_SWAP_CNTL2 0 0x2c5 1 0 1 MP_REF16_MC_SWAP 0 1 mmUVD_MPC_LUMA_SRCH 0 0x2c6 1 0 1 CNTR 0 31 mmUVD_MPC_LUMA_HIT 0 0x2c7 1 0 1 CNTR 0 31 mmUVD_MPC_LUMA_HITPEND 0 0x2c8 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_SRCH 0 0x2c9 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_HIT 0 0x2ca 1 0 1 CNTR 0 31 mmUVD_MPC_CHROMA_HITPEND 0 0x2cb 1 0 1 CNTR 0 31 mmUVD_MPC_CNTL 0 0x2cc 8 0 1 BLK_RST 0 0 REG_MPC1_PERF_SELECT 1 1 REPLACEMENT_MODE 3 5 PERF_RST 6 6 AVE_WEIGHT 16 17 URGENT_EN 18 18 SMPAT_REQ_SPEED_UP 19 19 TEST_MODE_EN 20 20 mmUVD_MPC_PITCH 0 0x2cd 1 0 1 LUMA_PITCH 0 10 mmUVD_MPC_SET_MUXA0 0 0x2ce 5 0 1 VARA_0 0 5 VARA_1 6 11 VARA_2 12 17 VARA_3 18 23 VARA_4 24 29 mmUVD_MPC_SET_MUXA1 0 0x2cf 3 0 1 VARA_5 0 5 VARA_6 6 11 VARA_7 12 17 mmUVD_MPC_SET_MUXB0 0 0x2d0 5 0 1 VARB_0 0 5 VARB_1 6 11 VARB_2 12 17 VARB_3 18 23 VARB_4 24 29 mmUVD_MPC_SET_MUXB1 0 0x2d1 3 0 1 VARB_5 0 5 VARB_6 6 11 VARB_7 12 17 mmUVD_MPC_SET_MUX 0 0x2d2 3 0 1 SET_0 0 2 SET_1 3 5 SET_2 6 8 mmUVD_MPC_SET_ALU 0 0x2d3 2 0 1 FUNCT 0 2 OPERAND 4 11 mmUVD_MPC_PERF0 0 0x2d4 1 0 1 MAX_LAT 0 9 mmUVD_MPC_PERF1 0 0x2d5 1 0 1 AVE_LAT 0 9 mmUVD_MPC_IND_INDEX 0 0x2d6 1 0 1 INDEX 0 8 mmUVD_MPC_IND_DATA 0 0x2d7 1 0 1 DATA 0 31 mmUVD_RBC_IB_SIZE 0 0x2dc 1 0 1 IB_SIZE 4 22 mmUVD_RBC_IB_SIZE_UPDATE 0 0x2dd 1 0 1 REMAIN_IB_SIZE 4 22 mmUVD_RBC_RB_CNTL 0 0x2de 7 0 1 RB_BUFSZ 0 4 RB_BLKSZ 8 12 RB_NO_FETCH 16 16 RB_WPTR_POLL_EN 20 20 RB_NO_UPDATE 24 24 RB_RPTR_WR_EN 28 28 BLK_RST 29 29 mmUVD_RBC_RB_RPTR_ADDR 0 0x2df 1 0 1 RB_RPTR_ADDR 0 31 mmUVD_RBC_RB_RPTR 0 0x2e0 1 0 1 RB_RPTR 4 22 mmUVD_RBC_RB_WPTR 0 0x2e1 1 0 1 RB_WPTR 4 22 mmUVD_RBC_VCPU_ACCESS 0 0x2e2 1 0 1 ENABLE_RBC 0 0 mmUVD_FW_SEMAPHORE_CNTL 0 0x2e3 3 0 1 START 0 0 BUSY 8 8 PASS 9 9 mmUVD_RBC_READ_REQ_URGENT_CNTL 0 0x2e5 1 0 1 CMD_READ_REQ_PRIORITY_MARK 0 1 mmUVD_RBC_RB_WPTR_CNTL 0 0x2e6 1 0 1 RB_PRE_WRITE_TIMER 0 14 mmUVD_RBC_WPTR_STATUS 0 0x2e7 1 0 1 RB_WPTR_IN_USE 4 22 mmUVD_RBC_WPTR_POLL_CNTL 0 0x2e8 2 0 1 POLL_FREQ 0 15 IDLE_POLL_COUNT 16 31 mmUVD_RBC_WPTR_POLL_ADDR 0 0x2e9 1 0 1 POLL_ADDR 2 31 mmUVD_SEMA_CMD 0 0x2ea 5 0 1 REQ_CMD 0 3 WR_PHASE 4 5 MODE 6 6 VMID_EN 7 7 VMID 8 11 mmUVD_SEMA_ADDR_LOW 0 0x2eb 1 0 1 ADDR_26_3 0 23 mmUVD_SEMA_ADDR_HIGH 0 0x2ec 1 0 1 ADDR_47_27 0 20 mmUVD_ENGINE_CNTL 0 0x2ed 3 0 1 ENGINE_START 0 0 ENGINE_START_MODE 1 1 NJ_PF_HANDLE_DISABLE 2 2 mmUVD_SEMA_TIMEOUT_STATUS 0 0x2ee 4 0 1 SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT 0 0 SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT 1 1 SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT 2 2 SEMAPHORE_TIMEOUT_CLEAR 3 3 mmUVD_SEMA_CNTL 0 0x2ef 2 0 1 SEMAPHORE_EN 0 0 ADVANCED_MODE_DIS 1 1 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0 0x2f0 3 0 1 SIGNAL_INCOMPLETE_EN 0 0 SIGNAL_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0 0x2f1 3 0 1 WAIT_FAULT_EN 0 0 WAIT_FAULT_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0 0x2f2 3 0 1 WAIT_INCOMPLETE_EN 0 0 WAIT_INCOMPLETE_COUNT 1 20 RESEND_TIMER 24 26 mmUVD_JOB_START 0 0x2f3 1 0 1 JOB_START 0 0 mmUVD_RBC_BUF_STATUS 0 0x2f4 6 0 1 RB_BUF_VALID 0 7 IB_BUF_VALID 8 15 RB_BUF_RD_ADDR 16 18 IB_BUF_RD_ADDR 19 21 RB_BUF_WR_ADDR 22 24 IB_BUF_WR_ADDR 25 27 mmUVD_RBC_SWAP_CNTL 0 0x2f5 4 0 1 RB_MC_SWAP 0 1 IB_MC_SWAP 2 3 RB_RPTR_MC_SWAP 4 5 RB_WR_MC_SWAP 26 27 mmUVD_LMI_RE_64BIT_BAR_LOW 0 0x41c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RE_64BIT_BAR_HIGH 0 0x41d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_IT_64BIT_BAR_LOW 0 0x41e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_IT_64BIT_BAR_HIGH 0 0x41f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MP_64BIT_BAR_LOW 0 0x420 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MP_64BIT_BAR_HIGH 0 0x421 1 0 1 BITS_63_32 0 31 mmUVD_LMI_CM_64BIT_BAR_LOW 0 0x422 1 0 1 BITS_31_0 0 31 mmUVD_LMI_CM_64BIT_BAR_HIGH 0 0x423 1 0 1 BITS_63_32 0 31 mmUVD_LMI_DB_64BIT_BAR_LOW 0 0x424 1 0 1 BITS_31_0 0 31 mmUVD_LMI_DB_64BIT_BAR_HIGH 0 0x425 1 0 1 BITS_63_32 0 31 mmUVD_LMI_DBW_64BIT_BAR_LOW 0 0x426 1 0 1 BITS_31_0 0 31 mmUVD_LMI_DBW_64BIT_BAR_HIGH 0 0x427 1 0 1 BITS_63_32 0 31 mmUVD_LMI_IDCT_64BIT_BAR_LOW 0 0x428 1 0 1 BITS_31_0 0 31 mmUVD_LMI_IDCT_64BIT_BAR_HIGH 0 0x429 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0 0x42a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0 0x42b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0 0x42c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0 0x42d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0 0x42e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0 0x42f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MPC_64BIT_BAR_LOW 0 0x430 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MPC_64BIT_BAR_HIGH 0 0x431 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0 0x432 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0 0x433 1 0 1 BITS_63_32 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0 0x434 1 0 1 BITS_31_0 0 31 mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0 0x435 1 0 1 BITS_63_32 0 31 mmUVD_LMI_LBSI_64BIT_BAR_LOW 0 0x436 1 0 1 BITS_31_0 0 31 mmUVD_LMI_LBSI_64BIT_BAR_HIGH 0 0x437 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0 0x438 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0 0x439 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0 0x43a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0 0x43b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0 0x43c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0 0x43d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_CENC_64BIT_BAR_LOW 0 0x43e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_CENC_64BIT_BAR_HIGH 0 0x43f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_SRE_64BIT_BAR_LOW 0 0x440 1 0 1 BITS_31_0 0 31 mmUVD_LMI_SRE_64BIT_BAR_HIGH 0 0x441 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0 0x442 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0 0x443 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0 0x444 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0 0x445 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0 0x446 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0 0x447 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_REF_64BIT_BAR_LOW 0 0x448 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH 0 0x449 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0 0x44a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0 0x44b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0 0x44c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0 0x44d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0 0x44e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0 0x44f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0 0x450 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0 0x451 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0 0x452 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0 0x453 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0 0x454 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0 0x455 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0 0x456 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0 0x457 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0 0x458 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0 0x459 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0 0x45a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0 0x45b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0 0x45c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0 0x45d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0 0x45e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0 0x45f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0 0x468 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0 0x469 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0 0x46a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0 0x46b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0 0x46c 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0 0x46d 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0 0x46e 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0 0x46f 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0 0x470 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0 0x471 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0 0x472 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0 0x473 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0 0x474 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0 0x475 1 0 1 BITS_63_32 0 31 mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0 0x476 1 0 1 BITS_31_0 0 31 mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0 0x477 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0 0x478 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0 0x479 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0 0x47a 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0 0x47b 1 0 1 BITS_63_32 0 31 mmUVD_LMI_SPH_64BIT_BAR_HIGH 0 0x47c 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0 0x47d 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0 0x47e 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0 0x47f 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0 0x480 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0 0x481 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0 0x482 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0 0x483 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0 0x484 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0 0x485 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0 0x486 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0 0x487 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0 0x488 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0 0x489 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0 0x48a 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0 0x48b 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0 0x48c 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MMSCH_NC_VMID 0 0x48d 8 0 1 MMSCH_NC0_VMID 0 3 MMSCH_NC1_VMID 4 7 MMSCH_NC2_VMID 8 11 MMSCH_NC3_VMID 12 15 MMSCH_NC4_VMID 16 19 MMSCH_NC5_VMID 20 23 MMSCH_NC6_VMID 24 27 MMSCH_NC7_VMID 28 31 mmUVD_LMI_MMSCH_CTRL 0 0x48e 9 0 1 MMSCH_DATA_COHERENCY_EN 0 0 MMSCH_VM 1 1 PRIV_CLIENT_MMSCH 2 2 MMSCH_R_MC_SWAP 3 4 MMSCH_W_MC_SWAP 5 6 MMSCH_RD 7 8 MMSCH_WR 9 10 MMSCH_RD_DROP 11 11 MMSCH_WR_DROP 12 12 mmUVD_MMSCH_LMI_STATUS 0 0x48f 3 0 1 MMSCH_LMI_WRITE_CLEAN 2 2 MMSCH_RD_CLEAN 13 13 MMSCH_WR_CLEAN 14 14 mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0 0x490 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0 0x491 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0 0x492 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0 0x493 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0 0x494 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0 0x495 1 0 1 BITS_63_32 0 31 mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0 0x496 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0 0x497 1 0 1 BITS_63_32 0 31 mmUVD_ADP_ATOMIC_CONFIG 0 0x499 5 0 1 ATOMIC_USER0_WR_CACHE 0 3 ATOMIC_USER1_WR_CACHE 4 7 ATOMIC_USER2_WR_CACHE 8 11 ATOMIC_USER3_WR_CACHE 12 15 ATOMIC_RD_URG 16 19 mmUVD_LMI_ARB_CTRL2 0 0x49a 6 0 1 CENC_RD_WAIT_EN 0 0 ATOMIC_WR_WAIT_EN 1 1 CENC_RD_MAX_BURST 2 5 ATOMIC_WR_MAX_BURST 6 9 MIF_RD_REQ_RET_MAX 10 19 MIF_WR_REQ_RET_MAX 20 31 mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0 0x49f 8 0 1 VCPU_CACHE1_VMID 0 3 VCPU_CACHE2_VMID 4 7 VCPU_CACHE3_VMID 8 11 VCPU_CACHE4_VMID 12 15 VCPU_CACHE5_VMID 16 19 VCPU_CACHE6_VMID 20 23 VCPU_CACHE7_VMID 24 27 VCPU_CACHE8_VMID 28 31 mmUVD_LMI_VCPU_NC_VMIDS_MULTI 0 0x4a0 6 0 1 VCPU_NC2_VMID 4 7 VCPU_NC3_VMID 8 11 VCPU_NC4_VMID 12 15 VCPU_NC5_VMID 16 19 VCPU_NC6_VMID 20 23 VCPU_NC7_VMID 24 27 mmUVD_LMI_LAT_CTRL 0 0x4a1 6 0 1 SCALE 0 7 MAX_START 8 8 MIN_START 9 9 AVG_START 10 10 PERFMON_SYNC 11 11 SKIP 16 19 mmUVD_LMI_LAT_CNTR 0 0x4a2 2 0 1 MAX_LAT 0 7 MIN_LAT 8 15 mmUVD_LMI_AVG_LAT_CNTR 0 0x4a3 3 0 1 ENV_LOW 0 7 ENV_HIGH 8 15 ENV_HIT 16 31 mmUVD_LMI_SPH 0 0x4a4 4 0 1 ADDR 0 27 STS 28 29 STS_VALID 30 30 STS_OVERFLOW 31 31 mmUVD_LMI_VCPU_CACHE_VMID 0 0x4a5 1 0 1 VCPU_CACHE_VMID 0 3 mmUVD_LMI_CTRL2 0 0x4a6 17 0 1 SPH_DIS 0 0 STALL_ARB 1 1 ASSERT_UMC_URGENT 2 2 MASK_UMC_URGENT 3 3 CRC1_RESET 4 4 DRCITF_BUBBLE_FIX_DIS 7 7 STALL_ARB_UMC 8 8 MC_READ_ID_SEL 9 10 MC_WRITE_ID_SEL 11 12 VCPU_NC0_EXT_EN 13 13 VCPU_NC1_EXT_EN 14 14 SPU_EXTRA_CID_EN 15 15 RE_OFFLOAD_EN 16 16 RE_OFLD_MIF_WR_REQ_NUM 17 24 CLEAR_NJ_PF_BP 25 25 NJ_MIF_GATING 26 26 CRC1_SEL 27 31 mmUVD_LMI_URGENT_CTRL 0 0x4a7 12 0 1 ENABLE_MC_RD_URGENT_STALL 0 0 ASSERT_MC_RD_STALL 1 1 ASSERT_MC_RD_URGENT 2 5 ENABLE_MC_WR_URGENT_STALL 8 8 ASSERT_MC_WR_STALL 9 9 ASSERT_MC_WR_URGENT 10 13 ENABLE_UMC_RD_URGENT_STALL 16 16 ASSERT_UMC_RD_STALL 17 17 ASSERT_UMC_RD_URGENT 18 21 ENABLE_UMC_WR_URGENT_STALL 24 24 ASSERT_UMC_WR_STALL 25 25 ASSERT_UMC_WR_URGENT 26 29 mmUVD_LMI_CTRL 0 0x4a8 19 0 1 WRITE_CLEAN_TIMER 0 7 WRITE_CLEAN_TIMER_EN 8 8 REQ_MODE 9 9 ASSERT_MC_URGENT 11 11 MASK_MC_URGENT 12 12 DATA_COHERENCY_EN 13 13 CRC_RESET 14 14 CRC_SEL 15 19 DISABLE_ON_FWV_FAIL 20 20 VCPU_DATA_COHERENCY_EN 21 21 CM_DATA_COHERENCY_EN 22 22 DB_DB_DATA_COHERENCY_EN 23 23 DB_IT_DATA_COHERENCY_EN 24 24 IT_IT_DATA_COHERENCY_EN 25 25 MIF_MIF_DATA_COHERENCY_EN 26 26 MIF_LESS_OUTSTANDING_RD_REQ 27 27 MC_BLK_RST 28 28 UMC_BLK_RST 29 29 RFU 30 31 mmUVD_LMI_STATUS 0 0x4a9 23 0 1 READ_CLEAN 0 0 WRITE_CLEAN 1 1 WRITE_CLEAN_RAW 2 2 VCPU_LMI_WRITE_CLEAN 3 3 UMC_READ_CLEAN 4 4 UMC_WRITE_CLEAN 5 5 UMC_WRITE_CLEAN_RAW 6 6 PENDING_UVD_MC_WRITE 7 7 READ_CLEAN_RAW 8 8 UMC_READ_CLEAN_RAW 9 9 UMC_UVD_IDLE 10 10 UMC_AVP_IDLE 11 11 ADP_MC_READ_CLEAN 12 12 ADP_UMC_READ_CLEAN 13 13 BSP0_WRITE_CLEAN 18 18 BSP1_WRITE_CLEAN 19 19 BSP2_WRITE_CLEAN 20 20 BSP3_WRITE_CLEAN 21 21 CENC_READ_CLEAN 22 22 DPB_MPC2_NO_HIT 28 28 DPB_MPC2_MULTI_HIT 29 29 DPB_MPC_NO_HIT 30 30 DPB_MPC_MULTI_HIT 31 31 mmUVD_LMI_PERFMON_CTRL 0 0x4ac 2 0 1 PERFMON_STATE 0 1 PERFMON_SEL 8 12 mmUVD_LMI_PERFMON_COUNT_LO 0 0x4ad 1 0 1 PERFMON_COUNT 0 31 mmUVD_LMI_PERFMON_COUNT_HI 0 0x4ae 1 0 1 PERFMON_COUNT 0 15 mmUVD_LMI_ADP_SWAP_CNTL 0 0x4af 11 0 1 VCPU_R_MC_SWAP 6 7 VCPU_W_MC_SWAP 8 9 CM_MC_SWAP 10 11 IT_MC_SWAP 12 13 DB_R_MC_SWAP 14 15 DB_W_MC_SWAP 16 17 CSM_MC_SWAP 18 19 PREF_MC_SWAP 20 21 DBW_MC_SWAP 24 25 RE_MC_SWAP 28 29 MP_MC_SWAP 30 31 mmUVD_LMI_RBC_RB_VMID 0 0x4b0 1 0 1 RB_VMID 0 3 mmUVD_LMI_RBC_IB_VMID 0 0x4b1 1 0 1 IB_VMID 0 3 mmUVD_LMI_MC_CREDITS 0 0x4b2 4 0 1 UVD_RD_CREDITS 0 5 UVD_WR_CREDITS 8 13 UMC_RD_CREDITS 16 21 UMC_WR_CREDITS 24 29 mmUVD_LMI_ADP_IND_INDEX 0 0x4b6 1 0 1 INDEX 0 12 mmUVD_LMI_ADP_IND_DATA 0 0x4b7 1 0 1 DATA 0 31 mmUVD_LMI_ADP_PF_EN 0 0x4b8 3 0 1 VCPU_CACHE0_PF_EN 0 0 VCPU_CACHE1_PF_EN 1 1 VCPU_CACHE2_PF_EN 2 2 mmUVD_LMI_ADP_CNN_CTRL 0 0x4b9 1 0 1 CNN_MODE_EN 0 0 mmUVD_LMI_PREF_CTRL 0 0x4ba 6 0 1 PREF_RST 0 0 PREF_BUSY_STATUS 1 1 PREF_WSTRB 2 2 PREF_WRITE_SIZE 3 3 PREF_STEP_SIZE 4 6 PREF_SIZE 19 31 mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW 0 0x4d5 1 0 1 BITS_31_0 0 31 mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH 0 0x4d6 1 0 1 BITS_63_32 0 31 ixUVD_CGC_MEM_CTRL 2 0x0 17 0 4294967295 LMI_MC_LS_EN 0 0 MPC_LS_EN 1 1 MPRD_LS_EN 2 2 WCB_LS_EN 3 3 UDEC_RE_LS_EN 4 4 UDEC_CM_LS_EN 5 5 UDEC_IT_LS_EN 6 6 UDEC_DB_LS_EN 7 7 UDEC_MP_LS_EN 8 8 SYS_LS_EN 9 9 VCPU_LS_EN 10 10 MIF_LS_EN 12 12 LCM_LS_EN 13 13 MMSCH_LS_EN 14 14 MPC1_LS_EN 15 15 LS_SET_DELAY 16 19 LS_CLEAR_DELAY 20 23 ixUVD_CGC_CTRL2 2 0x1 3 0 4294967295 DYN_OCLK_RAMP_EN 0 0 DYN_RCLK_RAMP_EN 1 1 GATER_DIV_ID 2 4 ixUVD_CGC_MEM_DS_CTRL 2 0x2 15 0 4294967295 LMI_MC_DS_EN 0 0 MPC_DS_EN 1 1 MPRD_DS_EN 2 2 WCB_DS_EN 3 3 UDEC_RE_DS_EN 4 4 UDEC_CM_DS_EN 5 5 UDEC_IT_DS_EN 6 6 UDEC_DB_DS_EN 7 7 UDEC_MP_DS_EN 8 8 SYS_DS_EN 9 9 VCPU_DS_EN 10 10 MIF_DS_EN 12 12 LCM_DS_EN 13 13 MMSCH_DS_EN 14 14 MPC1_DS_EN 15 15 ixUVD_CGC_MEM_SD_CTRL 2 0x3 15 0 4294967295 LMI_MC_SD_EN 0 0 MPC_SD_EN 1 1 MPRD_SD_EN 2 2 WCB_SD_EN 3 3 UDEC_RE_SD_EN 4 4 UDEC_CM_SD_EN 5 5 UDEC_IT_SD_EN 6 6 UDEC_DB_SD_EN 7 7 UDEC_MP_SD_EN 8 8 SYS_SD_EN 9 9 VCPU_SD_EN 10 10 MIF_SD_EN 12 12 LCM_SD_EN 13 13 MMSCH_SD_EN 14 14 MPC1_SD_EN 15 15 ixUVD_SW_SCRATCH_00 2 0x4 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_01 2 0x5 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_02 2 0x6 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_03 2 0x7 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_04 2 0x8 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_05 2 0x9 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_06 2 0xa 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_07 2 0xb 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_08 2 0xc 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_09 2 0xd 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_10 2 0xe 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_11 2 0xf 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_12 2 0x10 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_13 2 0x11 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_14 2 0x12 1 0 4294967295 DATA 0 31 ixUVD_SW_SCRATCH_15 2 0x13 1 0 4294967295 DATA 0 31 ixUVD_MEMCHECK_SYS_INT_EN 2 0x14 26 0 4294967295 RE_ERR_EN 0 0 IT_ERR_EN 1 1 MP_ERR_EN 2 2 DB_ERR_EN 3 3 DBW_ERR_EN 4 4 CM_ERR_EN 5 5 MIF_REF_ERR_EN 6 6 VCPU_ERR_EN 7 7 MIF_DBW_ERR_EN 8 8 MIF_CM_COLOC_ERR_EN 9 9 MIF_BSP0_ERR_EN 10 10 MIF_BSP1_ERR_EN 11 11 SRE_ERR_EN 12 12 IT_RD_ERR_EN 15 15 CM_RD_ERR_EN 16 16 DB_RD_ERR_EN 17 17 MIF_RD_ERR_EN 18 18 IDCT_RD_ERR_EN 19 19 MPC_RD_ERR_EN 20 20 LBSI_RD_ERR_EN 21 21 RBC_RD_ERR_EN 24 24 MIF_BSP2_ERR_EN 27 27 MIF_BSP3_ERR_EN 28 28 MIF_SCLR_ERR_EN 29 29 MIF_SCLR2_ERR_EN 30 30 PREF_ERR_EN 31 31 ixUVD_MEMCHECK_SYS_INT_STAT 2 0x15 28 0 4294967295 RE_LO_ERR 0 0 RE_HI_ERR 1 1 IT_LO_ERR 2 2 IT_HI_ERR 3 3 MP_LO_ERR 4 4 MP_HI_ERR 5 5 DB_LO_ERR 6 6 DB_HI_ERR 7 7 DBW_LO_ERR 8 8 DBW_HI_ERR 9 9 CM_LO_ERR 10 10 CM_HI_ERR 11 11 MIF_REF_LO_ERR 12 12 MIF_REF_HI_ERR 13 13 VCPU_LO_ERR 14 14 VCPU_HI_ERR 15 15 MIF_DBW_LO_ERR 16 16 MIF_DBW_HI_ERR 17 17 MIF_CM_COLOC_LO_ERR 18 18 MIF_CM_COLOC_HI_ERR 19 19 MIF_BSP0_LO_ERR 20 20 MIF_BSP0_HI_ERR 21 21 MIF_BSP1_LO_ERR 22 22 MIF_BSP1_HI_ERR 23 23 SRE_LO_ERR 24 24 SRE_HI_ERR 25 25 IT_RD_LO_ERR 30 30 IT_RD_HI_ERR 31 31 ixUVD_MEMCHECK_SYS_INT_ACK 2 0x16 28 0 4294967295 RE_LO_ACK 0 0 RE_HI_ACK 1 1 IT_LO_ACK 2 2 IT_HI_ACK 3 3 MP_LO_ACK 4 4 MP_HI_ACK 5 5 DB_LO_ACK 6 6 DB_HI_ACK 7 7 DBW_LO_ACK 8 8 DBW_HI_ACK 9 9 CM_LO_ACK 10 10 CM_HI_ACK 11 11 MIF_REF_LO_ACK 12 12 MIF_REF_HI_ACK 13 13 VCPU_LO_ACK 14 14 VCPU_HI_ACK 15 15 MIF_DBW_LO_ACK 16 16 MIF_DBW_HI_ACK 17 17 MIF_CM_COLOC_LO_ACK 18 18 MIF_CM_COLOC_HI_ACK 19 19 MIF_BSP0_LO_ACK 20 20 MIF_BSP0_HI_ACK 21 21 MIF_BSP1_LO_ACK 22 22 MIF_BSP1_HI_ACK 23 23 SRE_LO_ACK 24 24 SRE_HI_ACK 25 25 IT_RD_LO_ACK 30 30 IT_RD_HI_ACK 31 31 ixUVD_MEMCHECK_VCPU_INT_EN 2 0x17 26 0 4294967295 RE_ERR_EN 0 0 IT_ERR_EN 1 1 MP_ERR_EN 2 2 DB_ERR_EN 3 3 DBW_ERR_EN 4 4 CM_ERR_EN 5 5 MIF_REF_ERR_EN 6 6 VCPU_ERR_EN 7 7 MIF_DBW_ERR_EN 8 8 MIF_CM_COLOC_ERR_EN 9 9 MIF_BSP0_ERR_EN 10 10 MIF_BSP1_ERR_EN 11 11 SRE_ERR_EN 12 12 IT_RD_ERR_EN 15 15 CM_RD_ERR_EN 16 16 DB_RD_ERR_EN 17 17 MIF_RD_ERR_EN 18 18 IDCT_RD_ERR_EN 19 19 MPC_RD_ERR_EN 20 20 LBSI_RD_ERR_EN 21 21 RBC_RD_ERR_EN 24 24 MIF_BSP2_ERR_EN 25 25 MIF_BSP3_ERR_EN 26 26 MIF_SCLR_ERR_EN 27 27 MIF_SCLR2_ERR_EN 28 28 PREF_ERR_EN 29 29 ixUVD_MEMCHECK_VCPU_INT_STAT 2 0x18 28 0 4294967295 RE_LO_ERR 0 0 RE_HI_ERR 1 1 IT_LO_ERR 2 2 IT_HI_ERR 3 3 MP_LO_ERR 4 4 MP_HI_ERR 5 5 DB_LO_ERR 6 6 DB_HI_ERR 7 7 DBW_LO_ERR 8 8 DBW_HI_ERR 9 9 CM_LO_ERR 10 10 CM_HI_ERR 11 11 MIF_REF_LO_ERR 12 12 MIF_REF_HI_ERR 13 13 VCPU_LO_ERR 14 14 VCPU_HI_ERR 15 15 MIF_DBW_LO_ERR 16 16 MIF_DBW_HI_ERR 17 17 MIF_CM_COLOC_LO_ERR 18 18 MIF_CM_COLOC_HI_ERR 19 19 MIF_BSP0_LO_ERR 20 20 MIF_BSP0_HI_ERR 21 21 MIF_BSP1_LO_ERR 22 22 MIF_BSP1_HI_ERR 23 23 SRE_LO_ERR 24 24 SRE_HI_ERR 25 25 IT_RD_LO_ERR 30 30 IT_RD_HI_ERR 31 31 ixUVD_MEMCHECK_VCPU_INT_ACK 2 0x19 28 0 4294967295 RE_LO_ACK 0 0 RE_HI_ACK 1 1 IT_LO_ACK 2 2 IT_HI_ACK 3 3 MP_LO_ACK 4 4 MP_HI_ACK 5 5 DB_LO_ACK 6 6 DB_HI_ACK 7 7 DBW_LO_ACK 8 8 DBW_HI_ACK 9 9 CM_LO_ACK 10 10 CM_HI_ACK 11 11 MIF_REF_LO_ACK 12 12 MIF_REF_HI_ACK 13 13 VCPU_LO_ACK 14 14 VCPU_HI_ACK 15 15 MIF_DBW_LO_ACK 16 16 MIF_DBW_HI_ACK 17 17 MIF_CM_COLOC_LO_ACK 18 18 MIF_CM_COLOC_HI_ACK 19 19 MIF_BSP0_LO_ACK 20 20 MIF_BSP0_HI_ACK 21 21 MIF_BSP1_LO_ACK 22 22 MIF_BSP1_HI_ACK 23 23 SRE_LO_ACK 24 24 SRE_HI_ACK 25 25 IT_RD_LO_ACK 30 30 IT_RD_HI_ACK 31 31 ixUVD_MEMCHECK2_SYS_INT_STAT 2 0x1a 24 0 4294967295 CM_RD_LO_ERR 0 0 CM_RD_HI_ERR 1 1 DB_RD_LO_ERR 2 2 DB_RD_HI_ERR 3 3 MIF_RD_LO_ERR 4 4 MIF_RD_HI_ERR 5 5 IDCT_RD_LO_ERR 6 6 IDCT_RD_HI_ERR 7 7 MPC_RD_LO_ERR 8 8 MPC_RD_HI_ERR 9 9 LBSI_RD_LO_ERR 10 10 LBSI_RD_HI_ERR 11 11 RBC_RD_LO_ERR 16 16 RBC_RD_HI_ERR 17 17 MIF_BSP2_LO_ERR 22 22 MIF_BSP2_HI_ERR 23 23 MIF_BSP3_LO_ERR 24 24 MIF_BSP3_HI_ERR 25 25 MIF_SCLR_LO_ERR 26 26 MIF_SCLR_HI_ERR 27 27 MIF_SCLR2_LO_ERR 28 28 MIF_SCLR2_HI_ERR 29 29 PREF_LO_ERR 30 30 PREF_HI_ERR 31 31 ixUVD_MEMCHECK2_SYS_INT_ACK 2 0x1b 24 0 4294967295 CM_RD_LO_ACK 0 0 CM_RD_HI_ACK 1 1 DB_RD_LO_ACK 2 2 DB_RD_HI_ACK 3 3 MIF_RD_LO_ACK 4 4 MIF_RD_HI_ACK 5 5 IDCT_RD_LO_ACK 6 6 IDCT_RD_HI_ACK 7 7 MPC_RD_LO_ACK 8 8 MPC_RD_HI_ACK 9 9 LBSI_RD_LO_ACK 10 10 LBSI_RD_HI_ACK 11 11 RBC_RD_LO_ACK 16 16 RBC_RD_HI_ACK 17 17 MIF_BSP2_LO_ACK 22 22 MIF_BSP2_HI_ACK 23 23 MIF_BSP3_LO_ACK 24 24 MIF_BSP3_HI_ACK 25 25 MIF_SCLR_LO_ACK 26 26 MIF_SCLR_HI_ACK 27 27 MIF_SCLR2_LO_ACK 28 28 MIF_SCLR2_HI_ACK 29 29 PREF_LO_ACK 30 30 PREF_HI_ACK 31 31 ixUVD_MEMCHECK2_VCPU_INT_STAT 2 0x1c 24 0 4294967295 CM_RD_LO_ERR 0 0 CM_RD_HI_ERR 1 1 DB_RD_LO_ERR 2 2 DB_RD_HI_ERR 3 3 MIF_RD_LO_ERR 4 4 MIF_RD_HI_ERR 5 5 IDCT_RD_LO_ERR 6 6 IDCT_RD_HI_ERR 7 7 MPC_RD_LO_ERR 8 8 MPC_RD_HI_ERR 9 9 LBSI_RD_LO_ERR 10 10 LBSI_RD_HI_ERR 11 11 RBC_RD_LO_ERR 16 16 RBC_RD_HI_ERR 17 17 MIF_BSP2_LO_ERR 18 18 MIF_BSP2_HI_ERR 19 19 MIF_BSP3_LO_ERR 20 20 MIF_BSP3_HI_ERR 21 21 MIF_SCLR_LO_ERR 22 22 MIF_SCLR_HI_ERR 23 23 MIF_SCLR2_LO_ERR 24 24 MIF_SCLR2_HI_ERR 25 25 PREF_LO_ERR 26 26 PREF_HI_ERR 27 27 ixUVD_MEMCHECK2_VCPU_INT_ACK 2 0x1d 24 0 4294967295 CM_RD_LO_ACK 0 0 CM_RD_HI_ACK 1 1 DB_RD_LO_ACK 2 2 DB_RD_HI_ACK 3 3 MIF_RD_LO_ACK 4 4 MIF_RD_HI_ACK 5 5 IDCT_RD_LO_ACK 6 6 IDCT_RD_HI_ACK 7 7 MPC_RD_LO_ACK 8 8 MPC_RD_HI_ACK 9 9 LBSI_RD_LO_ACK 10 10 LBSI_RD_HI_ACK 11 11 RBC_RD_LO_ACK 16 16 RBC_RD_HI_ACK 17 17 MIF_BSP2_LO_ACK 18 18 MIF_BSP2_HI_ACK 19 19 MIF_BSP3_LO_ACK 20 20 MIF_BSP3_HI_ACK 21 21 MIF_SCLR_LO_ACK 22 22 MIF_SCLR_HI_ACK 23 23 MIF_SCLR2_LO_ACK 24 24 MIF_SCLR2_HI_ACK 25 25 PREF_LO_ACK 26 26 PREF_HI_ACK 27 27 ixUVD_IH_SEM_CTRL 2 0x1e 7 0 4294967295 IH_STALL_EN 0 0 SEM_STALL_EN 1 1 IH_STATUS_CLEAN 2 2 SEM_STATUS_CLEAN 3 3 IH_VMID 4 7 IH_USER_DATA 8 19 IH_RINGID 20 27