; PTE with T (further) bit set

; mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32=0x0
; mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32=0x0
; mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32=0xfe551001
; mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32=0x1
; mmGCVM_CONTEXT3_CNTL=0x7
; mmVGA_MEMORY_BASE_ADDRESS=0x0
; mmVGA_MEMORY_BASE_ADDRESS_HIGH=0x0
; mmMC_VM_FB_OFFSET=0x0
; mmGCMC_VM_MX_L1_TLB_CNTL=0x0
; mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR=0x0
; mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x0
; mmGCMC_VM_FB_LOCATION_BASE=0x0
; mmGCMC_VM_FB_LOCATION_TOP=0x0

MMIO@0xA618={0x0}     ; mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR
MMIO@0xA614={0x0}     ; mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR
MMIO@0xA600={0x0}       ; mmGCMC_VM_FB_LOCATION_BASE
MMIO@0xA604={0x0}       ; mmGCMC_VM_FB_LOCATION_TOP
MMIO@0xA444={0x0}          ; mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
MMIO@0xA448={0x0}          ; mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
MMIO@0xA4C4={0xFFFFFFFF}  ; mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32=0xFFFFFFFF
MMIO@0xA4C8={0xFFFFFFFF}  ; mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32=0xFFFFFFFF
MMIO@0xA20C={0x7}     ; mmGCVM_CONTEXT3_CNTL
MMIO@0x0310={0x0}            ; mmVGA_MEMORY_BASE_ADDRESS
MMIO@0x0324={0x0}            ; mmVGA_MEMORY_BASE_ADDRESS_HIGH=0xf4
MMIO@0xA5AC={0x0}          ; mmGCMC_VM_FB_OFFSET
MMIO@0xA61C={0x0}       ; mmGCMC_VM_MX_L1_TLB_CNTL
MMIO@0xA3C4={0xfe551001}          ; mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
MMIO@0xA3C8={0x1}          ; mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32

; PDE2
VRAM@0x1FE551008={01e054fe01000000}

; PDE1 
VRAM@0x1fe54efe0={01904bfe01000000}

; PDE0
VRAM@0x1fe4b9018={01304bfe01000030}

; PTE.T=1
VRAM@0x1fe4b3008={01424bfe01000001}

; PTE
VRAM@0x1fe4b4280={73f0099401000300}

; SYSRAM
SYSRAM@0x19409f000={0001020304050607}